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Differential D129203

[AArch64] Use Neoverse N2 sched model as default for:
ClosedPublic

Authored by c-rhodes on Jul 6 2022, 7:38 AM.

Details

Reviewers
paulwalker-arm
dmgreen
peterwaller-arm
bsmith
andreadb
Commits
rGd1c51d45f080: [AArch64] Use Neoverse N2 sched model as default for:
Summary
  • Cortex-A710
  • Cortex-X2
  • Neoverse-V1
  • Neoverse-512tvb

Diff Detail

Event Timeline

c-rhodes created this revision.Jul 6 2022, 7:38 AM
Herald added a project: Restricted Project. · View Herald TranscriptJul 6 2022, 7:38 AM
Herald added subscribers: hiraditya, kristof.beyls. · View Herald Transcript
c-rhodes requested review of this revision.Jul 6 2022, 7:38 AM
Herald added a project: Restricted Project. · View Herald TranscriptJul 6 2022, 7:38 AM
c-rhodes added a parent revision: D128631: [AArch64] Initial sched model for Neoverse N2.Jul 6 2022, 7:38 AM
c-rhodes mentioned this in D128631: [AArch64] Initial sched model for Neoverse N2.
c-rhodes added inline comments.Jul 6 2022, 7:42 AM
llvm/lib/Target/AArch64/AArch64.td
1157–1160

@dmgreen Is it ok to use the N2 as the default model for these cores given they're not Armv9 and only support SVEv1?

Matt added a subscriber: Matt.Jul 6 2022, 8:27 AM
Harbormaster completed remote builds in B173895: Diff 442566.Jul 6 2022, 8:30 AM
dmgreen accepted this revision.Jul 7 2022, 12:43 PM

Thanks for the patch. It may be possible to write a quick test that the scheduling info for one of the new instructions.

Otherwise LGTM.

llvm/lib/Target/AArch64/AArch64.td
1157–1160

Yeah - I think that's OK. The model will just have more coverage than the core. It should always be a better fit than the A57 model. The extra info in the schedules will just be unused.

This revision is now accepted and ready to land.Jul 7 2022, 12:43 PM
c-rhodes updated this revision to Diff 443195.Jul 8 2022, 3:46 AM

Add simple tests to check N2 model is being used.

Herald added a reviewer: andreadb. · View Herald TranscriptJul 8 2022, 3:46 AM
Herald added a subscriber: gbedwell. · View Herald Transcript
c-rhodes added a comment.Jul 8 2022, 3:47 AM
In D129203#3636861, @dmgreen wrote:

Thanks for the patch. It may be possible to write a quick test that the scheduling info for one of the new instructions.

Otherwise LGTM.

Cheers Dave, I've added some tests.

Harbormaster completed remote builds in B174349: Diff 443195.Jul 8 2022, 4:36 AM
This revision was landed with ongoing or failed builds.Jul 8 2022, 6:34 AM
Closed by commit rGd1c51d45f080: [AArch64] Use Neoverse N2 sched model as default for: (authored by c-rhodes). · Explain Why
This revision was automatically updated to reflect the committed changes.
c-rhodes added a commit: rGd1c51d45f080: [AArch64] Use Neoverse N2 sched model as default for:.

Revision Contents

PathSize
llvm/
lib/
Target/
AArch64/
8 lines
test/
tools/
llvm-mca/
AArch64/
Cortex/
40 lines
40 lines
Neoverse/
40 lines
40 lines

Diff 443233

llvm/lib/Target/AArch64/AArch64.td

Show First 20 Lines • Show All 1,132 Lines • ▼ Show 20 Lines
def : ProcessorModel<"cortex-a76ae", CortexA57Model, ProcessorFeatures.A76, def : ProcessorModel<"cortex-a76ae", CortexA57Model, ProcessorFeatures.A76,
[TuneA76]>; [TuneA76]>;
def : ProcessorModel<"cortex-a77", CortexA57Model, ProcessorFeatures.A77, def : ProcessorModel<"cortex-a77", CortexA57Model, ProcessorFeatures.A77,
[TuneA77]>; [TuneA77]>;
def : ProcessorModel<"cortex-a78", CortexA57Model, ProcessorFeatures.A78, def : ProcessorModel<"cortex-a78", CortexA57Model, ProcessorFeatures.A78,
[TuneA78]>; [TuneA78]>;
def : ProcessorModel<"cortex-a78c", CortexA57Model, ProcessorFeatures.A78C, def : ProcessorModel<"cortex-a78c", CortexA57Model, ProcessorFeatures.A78C,
[TuneA78C]>; [TuneA78C]>;
def : ProcessorModel<"cortex-a710", CortexA57Model, ProcessorFeatures.A710, def : ProcessorModel<"cortex-a710", NeoverseN2Model, ProcessorFeatures.A710,
[TuneA710]>; [TuneA710]>;
def : ProcessorModel<"cortex-r82", CortexA55Model, ProcessorFeatures.R82, def : ProcessorModel<"cortex-r82", CortexA55Model, ProcessorFeatures.R82,
[TuneR82]>; [TuneR82]>;
def : ProcessorModel<"cortex-x1", CortexA57Model, ProcessorFeatures.X1, def : ProcessorModel<"cortex-x1", CortexA57Model, ProcessorFeatures.X1,
[TuneX1]>; [TuneX1]>;
def : ProcessorModel<"cortex-x1c", CortexA57Model, ProcessorFeatures.X1C, def : ProcessorModel<"cortex-x1c", CortexA57Model, ProcessorFeatures.X1C,
[TuneX1]>; [TuneX1]>;
def : ProcessorModel<"cortex-x2", CortexA57Model, ProcessorFeatures.X2, def : ProcessorModel<"cortex-x2", NeoverseN2Model, ProcessorFeatures.X2,
[TuneX2]>; [TuneX2]>;
def : ProcessorModel<"neoverse-e1", CortexA53Model, def : ProcessorModel<"neoverse-e1", CortexA53Model,
ProcessorFeatures.NeoverseE1, [TuneNeoverseE1]>; ProcessorFeatures.NeoverseE1, [TuneNeoverseE1]>;
def : ProcessorModel<"neoverse-n1", CortexA57Model, def : ProcessorModel<"neoverse-n1", CortexA57Model,
ProcessorFeatures.NeoverseN1, [TuneNeoverseN1]>; ProcessorFeatures.NeoverseN1, [TuneNeoverseN1]>;
def : ProcessorModel<"neoverse-n2", NeoverseN2Model, def : ProcessorModel<"neoverse-n2", NeoverseN2Model,
ProcessorFeatures.NeoverseN2, [TuneNeoverseN2]>; ProcessorFeatures.NeoverseN2, [TuneNeoverseN2]>;
def : ProcessorModel<"neoverse-512tvb", CortexA57Model, def : ProcessorModel<"neoverse-512tvb", NeoverseN2Model,
ProcessorFeatures.Neoverse512TVB, [TuneNeoverse512TVB]>; ProcessorFeatures.Neoverse512TVB, [TuneNeoverse512TVB]>;
def : ProcessorModel<"neoverse-v1", CortexA57Model, def : ProcessorModel<"neoverse-v1", NeoverseN2Model,
ProcessorFeatures.NeoverseV1, [TuneNeoverseV1]>; ProcessorFeatures.NeoverseV1, [TuneNeoverseV1]>;
c-rhodesAuthorUnsubmitted
Not Done
ReplyInline Actions

@dmgreen Is it ok to use the N2 as the default model for these cores given they're not Armv9 and only support SVEv1?

c-rhodes: @dmgreen Is it ok to use the N2 as the default model for these cores given they're not Armv9…
dmgreenUnsubmitted
Not Done
ReplyInline Actions

Yeah - I think that's OK. The model will just have more coverage than the core. It should always be a better fit than the A57 model. The extra info in the schedules will just be unused.

dmgreen: Yeah - I think that's OK. The model will just have more coverage than the core. It should…
def : ProcessorModel<"exynos-m3", ExynosM3Model, ProcessorFeatures.ExynosM3, def : ProcessorModel<"exynos-m3", ExynosM3Model, ProcessorFeatures.ExynosM3,
[TuneExynosM3]>; [TuneExynosM3]>;
def : ProcessorModel<"exynos-m4", ExynosM4Model, ProcessorFeatures.ExynosM4, def : ProcessorModel<"exynos-m4", ExynosM4Model, ProcessorFeatures.ExynosM4,
[TuneExynosM4]>; [TuneExynosM4]>;
def : ProcessorModel<"exynos-m5", ExynosM5Model, ProcessorFeatures.ExynosM4, def : ProcessorModel<"exynos-m5", ExynosM5Model, ProcessorFeatures.ExynosM4,
[TuneExynosM4]>; [TuneExynosM4]>;
def : ProcessorModel<"falkor", FalkorModel, ProcessorFeatures.Falkor, def : ProcessorModel<"falkor", FalkorModel, ProcessorFeatures.Falkor,
[TuneFalkor]>; [TuneFalkor]>;
▲ Show 20 Lines • Show All 123 Lines • Show Last 20 Lines

llvm/test/tools/llvm-mca/AArch64/Cortex/A710-sve-instructions.s

  • This file was added.
# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
# RUN: llvm-mca -mtriple=aarch64 -mcpu=cortex-a710 -instruction-tables < %s | FileCheck %s
# Check the Neoverse N2 model is used.
bext z0.b, z1.b, z31.b
# CHECK: Instruction Info:
# CHECK-NEXT: [1]: #uOps
# CHECK-NEXT: [2]: Latency
# CHECK-NEXT: [3]: RThroughput
# CHECK-NEXT: [4]: MayLoad
# CHECK-NEXT: [5]: MayStore
# CHECK-NEXT: [6]: HasSideEffects (U)
# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
# CHECK-NEXT: 2 6 2.00 bext z0.b, z1.b, z31.b
# CHECK: Resources:
# CHECK-NEXT: [0.0] - N2UnitB
# CHECK-NEXT: [0.1] - N2UnitB
# CHECK-NEXT: [1.0] - N2UnitD
# CHECK-NEXT: [1.1] - N2UnitD
# CHECK-NEXT: [2] - N2UnitL2
# CHECK-NEXT: [3.0] - N2UnitL01
# CHECK-NEXT: [3.1] - N2UnitL01
# CHECK-NEXT: [4] - N2UnitM0
# CHECK-NEXT: [5] - N2UnitM1
# CHECK-NEXT: [6.0] - N2UnitS
# CHECK-NEXT: [6.1] - N2UnitS
# CHECK-NEXT: [7] - N2UnitV0
# CHECK-NEXT: [8] - N2UnitV1
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0.0] [0.1] [1.0] [1.1] [2] [3.0] [3.1] [4] [5] [6.0] [6.1] [7] [8]
# CHECK-NEXT: - - - - - - - - - - - - 2.00
# CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0.0] [0.1] [1.0] [1.1] [2] [3.0] [3.1] [4] [5] [6.0] [6.1] [7] [8] Instructions:
# CHECK-NEXT: - - - - - - - - - - - - 2.00 bext z0.b, z1.b, z31.b

llvm/test/tools/llvm-mca/AArch64/Cortex/X2-sve-instructions.s

  • This file was added.
# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
# RUN: llvm-mca -mtriple=aarch64 -mcpu=cortex-x2 -instruction-tables < %s | FileCheck %s
# Check the Neoverse N2 model is used.
addhnb z0.b, z1.h, z31.h
# CHECK: Instruction Info:
# CHECK-NEXT: [1]: #uOps
# CHECK-NEXT: [2]: Latency
# CHECK-NEXT: [3]: RThroughput
# CHECK-NEXT: [4]: MayLoad
# CHECK-NEXT: [5]: MayStore
# CHECK-NEXT: [6]: HasSideEffects (U)
# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
# CHECK-NEXT: 1 2 0.50 addhnb z0.b, z1.h, z31.h
# CHECK: Resources:
# CHECK-NEXT: [0.0] - N2UnitB
# CHECK-NEXT: [0.1] - N2UnitB
# CHECK-NEXT: [1.0] - N2UnitD
# CHECK-NEXT: [1.1] - N2UnitD
# CHECK-NEXT: [2] - N2UnitL2
# CHECK-NEXT: [3.0] - N2UnitL01
# CHECK-NEXT: [3.1] - N2UnitL01
# CHECK-NEXT: [4] - N2UnitM0
# CHECK-NEXT: [5] - N2UnitM1
# CHECK-NEXT: [6.0] - N2UnitS
# CHECK-NEXT: [6.1] - N2UnitS
# CHECK-NEXT: [7] - N2UnitV0
# CHECK-NEXT: [8] - N2UnitV1
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0.0] [0.1] [1.0] [1.1] [2] [3.0] [3.1] [4] [5] [6.0] [6.1] [7] [8]
# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50
# CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0.0] [0.1] [1.0] [1.1] [2] [3.0] [3.1] [4] [5] [6.0] [6.1] [7] [8] Instructions:
# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 addhnb z0.b, z1.h, z31.h

llvm/test/tools/llvm-mca/AArch64/Neoverse/512tvb-sve-instructions.s

  • This file was added.
# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
# RUN: llvm-mca -mtriple=aarch64 -mcpu=neoverse-512tvb -instruction-tables < %s | FileCheck %s
# Check the Neoverse N2 model is used.
abs z0.b, p0/m, z0.b
# CHECK: Instruction Info:
# CHECK-NEXT: [1]: #uOps
# CHECK-NEXT: [2]: Latency
# CHECK-NEXT: [3]: RThroughput
# CHECK-NEXT: [4]: MayLoad
# CHECK-NEXT: [5]: MayStore
# CHECK-NEXT: [6]: HasSideEffects (U)
# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
# CHECK-NEXT: 1 2 0.50 abs z0.b, p0/m, z0.b
# CHECK: Resources:
# CHECK-NEXT: [0.0] - N2UnitB
# CHECK-NEXT: [0.1] - N2UnitB
# CHECK-NEXT: [1.0] - N2UnitD
# CHECK-NEXT: [1.1] - N2UnitD
# CHECK-NEXT: [2] - N2UnitL2
# CHECK-NEXT: [3.0] - N2UnitL01
# CHECK-NEXT: [3.1] - N2UnitL01
# CHECK-NEXT: [4] - N2UnitM0
# CHECK-NEXT: [5] - N2UnitM1
# CHECK-NEXT: [6.0] - N2UnitS
# CHECK-NEXT: [6.1] - N2UnitS
# CHECK-NEXT: [7] - N2UnitV0
# CHECK-NEXT: [8] - N2UnitV1
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0.0] [0.1] [1.0] [1.1] [2] [3.0] [3.1] [4] [5] [6.0] [6.1] [7] [8]
# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50
# CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0.0] [0.1] [1.0] [1.1] [2] [3.0] [3.1] [4] [5] [6.0] [6.1] [7] [8] Instructions:
# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 abs z0.b, p0/m, z0.b

llvm/test/tools/llvm-mca/AArch64/Neoverse/V1-sve-instructions.s

  • This file was added.
# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
# RUN: llvm-mca -mtriple=aarch64 -mcpu=neoverse-v1 -instruction-tables < %s | FileCheck %s
# Check the Neoverse N2 model is used.
abs z0.b, p0/m, z0.b
# CHECK: Instruction Info:
# CHECK-NEXT: [1]: #uOps
# CHECK-NEXT: [2]: Latency
# CHECK-NEXT: [3]: RThroughput
# CHECK-NEXT: [4]: MayLoad
# CHECK-NEXT: [5]: MayStore
# CHECK-NEXT: [6]: HasSideEffects (U)
# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
# CHECK-NEXT: 1 2 0.50 abs z0.b, p0/m, z0.b
# CHECK: Resources:
# CHECK-NEXT: [0.0] - N2UnitB
# CHECK-NEXT: [0.1] - N2UnitB
# CHECK-NEXT: [1.0] - N2UnitD
# CHECK-NEXT: [1.1] - N2UnitD
# CHECK-NEXT: [2] - N2UnitL2
# CHECK-NEXT: [3.0] - N2UnitL01
# CHECK-NEXT: [3.1] - N2UnitL01
# CHECK-NEXT: [4] - N2UnitM0
# CHECK-NEXT: [5] - N2UnitM1
# CHECK-NEXT: [6.0] - N2UnitS
# CHECK-NEXT: [6.1] - N2UnitS
# CHECK-NEXT: [7] - N2UnitV0
# CHECK-NEXT: [8] - N2UnitV1
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0.0] [0.1] [1.0] [1.1] [2] [3.0] [3.1] [4] [5] [6.0] [6.1] [7] [8]
# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50
# CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0.0] [0.1] [1.0] [1.1] [2] [3.0] [3.1] [4] [5] [6.0] [6.1] [7] [8] Instructions:
# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 abs z0.b, p0/m, z0.b