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Differential D128972

[RISCV][NFC] Simplify condition of IsTU.
ClosedPublic

Authored by fakepaper56 on Jul 1 2022, 12:29 AM.

Details

Reviewers
khchen
frasercrmck
Commits
rG8590a35ef900: [RISCV][NFC] Simplify condition of IsTU.
Summary

Just simplify code.

Diff Detail

Event Timeline

fakepaper56 created this revision.Jul 1 2022, 12:29 AM
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fakepaper56 requested review of this revision.Jul 1 2022, 12:29 AM
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Harbormaster completed remote builds in B173187: Diff 441621.Jul 1 2022, 1:08 AM
khchen accepted this revision.Jul 1 2022, 7:25 AM

LGTM, thanks!

This revision is now accepted and ready to land.Jul 1 2022, 7:25 AM
This revision was landed with ongoing or failed builds.Jul 1 2022, 6:20 PM
Closed by commit rG8590a35ef900: [RISCV][NFC] Simplify condition of IsTU. (authored by fakepaper56). · Explain Why
This revision was automatically updated to reflect the committed changes.
fakepaper56 added a commit: rG8590a35ef900: [RISCV][NFC] Simplify condition of IsTU..

Revision Contents

PathSize
llvm/
lib/
Target/
RISCV/
9 lines

Diff 441836

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

Show First 20 Lines • Show All 1,358 Lines • ▼ Show 20 Lines case Intrinsic::riscv_vluxei_mask: {
bool IsOrdered = IntNo == Intrinsic::riscv_vloxei || bool IsOrdered = IntNo == Intrinsic::riscv_vloxei ||
IntNo == Intrinsic::riscv_vloxei_mask; IntNo == Intrinsic::riscv_vloxei_mask;
MVT VT = Node->getSimpleValueType(0); MVT VT = Node->getSimpleValueType(0);
unsigned Log2SEW = Log2_32(VT.getScalarSizeInBits()); unsigned Log2SEW = Log2_32(VT.getScalarSizeInBits());
unsigned CurOp = 2; unsigned CurOp = 2;
// Masked intrinsic only have TU version pseduo instructions. // Masked intrinsic only have TU version pseduo instructions.
bool IsTU = IsMasked || (!IsMasked && !Node->getOperand(CurOp).isUndef()); bool IsTU = IsMasked || !Node->getOperand(CurOp).isUndef();
SmallVector<SDValue, 8> Operands; SmallVector<SDValue, 8> Operands;
if (IsTU) if (IsTU)
Operands.push_back(Node->getOperand(CurOp++)); Operands.push_back(Node->getOperand(CurOp++));
else else
// Skip the undef passthru operand for nomask TA version pseudo // Skip the undef passthru operand for nomask TA version pseudo
CurOp++; CurOp++;
MVT IndexVT; MVT IndexVT;
Show All 35 Lines case Intrinsic::riscv_vlse_mask: {
MVT VT = Node->getSimpleValueType(0); MVT VT = Node->getSimpleValueType(0);
unsigned Log2SEW = Log2_32(VT.getScalarSizeInBits()); unsigned Log2SEW = Log2_32(VT.getScalarSizeInBits());
unsigned CurOp = 2; unsigned CurOp = 2;
// The riscv_vlm intrinsic are always tail agnostic and no passthru operand. // The riscv_vlm intrinsic are always tail agnostic and no passthru operand.
bool HasPassthruOperand = IntNo != Intrinsic::riscv_vlm; bool HasPassthruOperand = IntNo != Intrinsic::riscv_vlm;
// Masked intrinsic only have TU version pseduo instructions. // Masked intrinsic only have TU version pseduo instructions.
bool IsTU = bool IsTU = HasPassthruOperand &&
HasPassthruOperand && (IsMasked || !Node->getOperand(CurOp).isUndef());
((!IsMasked && !Node->getOperand(CurOp).isUndef()) || IsMasked);
SmallVector<SDValue, 8> Operands; SmallVector<SDValue, 8> Operands;
if (IsTU) if (IsTU)
Operands.push_back(Node->getOperand(CurOp++)); Operands.push_back(Node->getOperand(CurOp++));
else if (HasPassthruOperand) else if (HasPassthruOperand)
// Skip the undef passthru operand for nomask TA version pseudo // Skip the undef passthru operand for nomask TA version pseudo
CurOp++; CurOp++;
addVectorLoadStoreOperands(Node, Log2SEW, DL, CurOp, IsMasked, IsStrided, addVectorLoadStoreOperands(Node, Log2SEW, DL, CurOp, IsMasked, IsStrided,
Show All 16 Lines case ISD::INTRINSIC_W_CHAIN: {
case Intrinsic::riscv_vleff_mask: { case Intrinsic::riscv_vleff_mask: {
bool IsMasked = IntNo == Intrinsic::riscv_vleff_mask; bool IsMasked = IntNo == Intrinsic::riscv_vleff_mask;
MVT VT = Node->getSimpleValueType(0); MVT VT = Node->getSimpleValueType(0);
unsigned Log2SEW = Log2_32(VT.getScalarSizeInBits()); unsigned Log2SEW = Log2_32(VT.getScalarSizeInBits());
unsigned CurOp = 2; unsigned CurOp = 2;
// Masked intrinsic only have TU version pseduo instructions. // Masked intrinsic only have TU version pseduo instructions.
bool IsTU = IsMasked || (!IsMasked && !Node->getOperand(CurOp).isUndef()); bool IsTU = IsMasked || !Node->getOperand(CurOp).isUndef();
SmallVector<SDValue, 7> Operands; SmallVector<SDValue, 7> Operands;
if (IsTU) if (IsTU)
Operands.push_back(Node->getOperand(CurOp++)); Operands.push_back(Node->getOperand(CurOp++));
else else
// Skip the undef passthru operand for nomask TA version pseudo // Skip the undef passthru operand for nomask TA version pseudo
CurOp++; CurOp++;
addVectorLoadStoreOperands(Node, Log2SEW, DL, CurOp, IsMasked, addVectorLoadStoreOperands(Node, Log2SEW, DL, CurOp, IsMasked,
▲ Show 20 Lines • Show All 1,023 Lines • Show Last 20 Lines