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[clang-format] Handle Verilog case statements
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Authored by sstwcw on Jun 28 2022, 1:34 AM.

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Summary

These statements are like switch statements in C, but without the 'case'
keyword in labels.

How labels are parsed. In UnwrappedLineParser, the program tries to
parse a statement every time it sees a colon. In TokenAnnotator, a
colon that isn't part of an expression is annotated as a label.

The token type TT_GotoLabelColon is added. We did not include Verilog
in the name because we thought we would eventually have to fix the
problem that case labels in C can't contain ternary conditional
expressions and we would use that token type.

The style is like below. Labels are on separate lines and indented by
default. The linked style guide also has examples where labels and the
corresponding statements are on the same lines. They are not supported
for now.

https://github.com/lowRISC/style-guides/blob/master/VerilogCodingStyle.md

case (state_q)
  StIdle:
    state_d = StA;
  StA: begin
    state_d = StB;
  end
endcase

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sstwcw created this revision.Jun 28 2022, 1:34 AM
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sstwcw added a project: Restricted Project.Jun 28 2022, 1:41 AM
clang/lib/Format/Format.cpp
1265

You should put that below.

1349

Here.

sstwcw updated this revision to Diff 443608.Jul 11 2022, 5:25 AM
sstwcw marked 2 inline comments as done.Jul 11 2022, 5:33 AM
This revision is now accepted and ready to land.Jul 11 2022, 12:50 PM
This revision was automatically updated to reflect the committed changes.