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[clang-format] Handle Verilog user-defined primitives
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Authored by sstwcw on Jun 28 2022, 1:32 AM.

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sstwcw created this revision.Jun 28 2022, 1:32 AM
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sstwcw requested review of this revision.Jun 28 2022, 1:32 AM
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sstwcw added a project: Restricted Project.Jun 28 2022, 1:41 AM
This revision is now accepted and ready to land.Jun 28 2022, 2:25 AM
owenpan accepted this revision.Jun 29 2022, 12:39 PM
owenpan added inline comments.
clang/lib/Format/TokenAnnotator.cpp
4007
clang/lib/Format/UnwrappedLineParser.cpp
4165
sstwcw updated this revision to Diff 443607.Mon, Jul 11, 5:22 AM
sstwcw marked 2 inline comments as done.
This revision was automatically updated to reflect the committed changes.