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[clang-format] Handle Verilog blocks
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Authored by sstwcw on Jun 28 2022, 1:30 AM.

Details

Summary

Now stuff inside begin-end blocks get indented.

Some tests are moved into FormatTestVerilog.Block from
FormatTestVerilog.If because they have nothing to do with if statements.

Diff Detail

Event Timeline

sstwcw created this revision.Jun 28 2022, 1:30 AM
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sstwcw requested review of this revision.Jun 28 2022, 1:30 AM
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sstwcw added a project: Restricted Project.Jun 28 2022, 1:39 AM
This revision is now accepted and ready to land.Jun 28 2022, 2:09 AM
owenpan accepted this revision.Jun 29 2022, 12:38 PM
This revision was landed with ongoing or failed builds.Thu, Jul 28, 5:39 PM
This revision was automatically updated to reflect the committed changes.