Now stuff inside begin-end blocks get indented.
Some tests are moved into FormatTestVerilog.Block from
FormatTestVerilog.If because they have nothing to do with if statements.
Differential D128711
[clang-format] Handle Verilog blocks sstwcw on Jun 28 2022, 1:30 AM. Authored by
Details Now stuff inside begin-end blocks get indented. Some tests are moved into FormatTestVerilog.Block from
Diff Detail
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