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Differential D127721

[RISCV][NFC] Add load/store instructions in rv64*-invalid.s
ClosedPublic

Authored by Pretty-box on Jun 13 2022, 11:56 PM.

Details

Reviewers
benshi001
sunshaoce
Commits
rG880ac5189d63: [RISCV][NFC] Add load/store instructions in rv64*-invalid.s

Diff Detail

Event Timeline

Pretty-box created this revision.Jun 13 2022, 11:56 PM
Herald added subscribers: VincentWu, luke957, vkmr and 27 others. · View Herald TranscriptJun 13 2022, 11:56 PM
Pretty-box requested review of this revision.Jun 13 2022, 11:56 PM
Herald added subscribers: llvm-commits, • pcwang-thead, eopXD, MaskRay. · View Herald TranscriptJun 13 2022, 11:56 PM
Harbormaster completed remote builds in B169636: Diff 436672.Jun 14 2022, 1:13 AM
benshi001 added inline comments.Jun 14 2022, 5:48 AM
llvm/test/MC/RISCV/rv64zdinx-invalid.s
4

I guess you probably want fld and fsd ?

llvm/test/MC/RISCV/rv64zfh-invalid.s
12

also add invalid operand for fld/fsd along with fsw/flw ?

llvm/test/MC/RISCV/rv64zhinx-invalid.s
4

I guess you want flh/fsh ?

llvm/test/MC/RISCV/rv64zhinxmin-invalid.s
4

I guess you want flh/fsh ?

sunshaoce added inline comments.Jun 14 2022, 9:23 AM
llvm/test/MC/RISCV/rv64zdinx-invalid.s
4

In zdinx, you should use ld rather than fld or flw.

benshi001 added inline comments.Jun 14 2022, 6:23 PM
llvm/test/MC/RISCV/rv64zdinx-invalid.s
4

Sure. So we need to test neither fld/fsd nor fsw/flw is valid.

Pretty-box updated this revision to Diff 437016.Jun 14 2022, 8:28 PM
Harbormaster completed remote builds in B169896: Diff 437016.Jun 14 2022, 9:02 PM
Pretty-box marked 6 inline comments as done.Jun 14 2022, 11:19 PM
Pretty-box added inline comments.
llvm/test/MC/RISCV/rv64zhinxmin-invalid.s
4

Modified RUN line -mattr

benshi001 accepted this revision.Jun 15 2022, 12:02 AM
This revision is now accepted and ready to land.Jun 15 2022, 12:02 AM
This revision was landed with ongoing or failed builds.Jun 17 2022, 12:18 AM
Closed by commit rG880ac5189d63: [RISCV][NFC] Add load/store instructions in rv64*-invalid.s (authored by Pretty-box). · Explain Why
This revision was automatically updated to reflect the committed changes.
Pretty-box marked an inline comment as done.
Pretty-box added a commit: rG880ac5189d63: [RISCV][NFC] Add load/store instructions in rv64*-invalid.s.

Revision Contents

Diff 436672

llvm/test/MC/RISCV/rv64zdinx-invalid.s

# RUN: not llvm-mc -triple riscv64 -mattr=+zdinx %s 2>&1 | FileCheck %s # RUN: not llvm-mc -triple riscv64 -mattr=+zdinx %s 2>&1 | FileCheck %s
# Invalid Instructions # Not support float registers
flw fa4, 12(sp) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'F' (Single-Precision Floating-Point)
benshi001Unsubmitted
Done
ReplyInline Actions

I guess you probably want fld and fsd ?

benshi001: I guess you probably want `fld` and `fsd` ?
sunshaoceUnsubmitted
Done
ReplyInline Actions

In zdinx, you should use ld rather than fld or flw.

sunshaoce: In zdinx, you should use `ld` rather than `fld` or `flw`.
benshi001Unsubmitted
Done
ReplyInline Actions

Sure. So we need to test neither fld/fsd nor fsw/flw is valid.

benshi001: Sure. So we need to test neither fld/fsd nor fsw/flw is valid.
# Invalid instructions
fsw a5, 12(sp) # CHECK: :[[@LINE]]:5: error: invalid operand for instruction
fmv.x.d t2, a2 # CHECK: :[[@LINE]]:13: error: invalid operand for instruction fmv.x.d t2, a2 # CHECK: :[[@LINE]]:13: error: invalid operand for instruction
fmv.d.x a5, t5 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction fmv.d.x a5, t5 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
# FP registers where integer regs are expected # FP registers where integer regs are expected
fcvt.d.l a3, ft3 # CHECK: :[[@LINE]]:14: error: invalid operand for instruction fcvt.d.l a3, ft3 # CHECK: :[[@LINE]]:14: error: invalid operand for instruction
fcvt.d.lu a4, ft4 # CHECK: :[[@LINE]]:15: error: invalid operand for instruction fcvt.d.lu a4, ft4 # CHECK: :[[@LINE]]:15: error: invalid operand for instruction

llvm/test/MC/RISCV/rv64zfh-invalid.s

# RUN: not llvm-mc -triple riscv64 -mattr=+zfh < %s 2>&1 | \ # RUN: not llvm-mc -triple riscv64 -mattr=+zfh < %s 2>&1 | \
# RUN: FileCheck %s # RUN: FileCheck %s
# Out of range immediates
## simm12
flh ft1, -2049(a0) # CHECK: :[[@LINE]]:10: error: operand must be a symbol with %lo/%pcrel_lo/%tprel_lo modifier or an integer in the range [-2048, 2047]
fsh ft2, 2048(a1) # CHECK: :[[@LINE]]:10: error: operand must be a symbol with %lo/%pcrel_lo/%tprel_lo modifier or an integer in the range [-2048, 2047]
# Memory operand not formatted correctly
flw ft1, a0, -200 # CHECK: :[[@LINE]]:14: error: invalid operand for instruction
fsw ft2, a1, 100 # CHECK: :[[@LINE]]:14: error: invalid operand for instruction
benshi001Unsubmitted
Done
ReplyInline Actions

also add invalid operand for fld/fsd along with fsw/flw ?

benshi001: also add `invalid operand` for `fld`/`fsd` along with `fsw`/`flw` ?
# Integer registers where FP regs are expected # Integer registers where FP regs are expected
fcvt.l.h ft0, a0 # CHECK: :[[@LINE]]:10: error: invalid operand for instruction fcvt.l.h ft0, a0 # CHECK: :[[@LINE]]:10: error: invalid operand for instruction
fcvt.lu.h ft1, a1 # CHECK: :[[@LINE]]:11: error: invalid operand for instruction fcvt.lu.h ft1, a1 # CHECK: :[[@LINE]]:11: error: invalid operand for instruction
# FP registers where integer regs are expected # FP registers where integer regs are expected
fcvt.h.l a2, ft2 # CHECK: :[[@LINE]]:10: error: invalid operand for instruction fcvt.h.l a2, ft2 # CHECK: :[[@LINE]]:10: error: invalid operand for instruction
fcvt.h.lu a3, ft3 # CHECK: :[[@LINE]]:11: error: invalid operand for instruction fcvt.h.lu a3, ft3 # CHECK: :[[@LINE]]:11: error: invalid operand for instruction

llvm/test/MC/RISCV/rv64zfinx-invalid.s

# RUN: not llvm-mc -triple riscv64 -mattr=+zfinx %s 2>&1 | FileCheck %s # RUN: not llvm-mc -triple riscv64 -mattr=+zfinx %s 2>&1 | FileCheck %s
# Not support float registers
flw fa4, 12(sp) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'F' (Single-Precision Floating-Point)
# Invalid instructions # Invalid instructions
fsw a5, 12(sp) # CHECK: :[[@LINE]]:5: error: invalid operand for instruction
fmv.x.w t2, a2 # CHECK: :[[@LINE]]:13: error: invalid operand for instruction fmv.x.w t2, a2 # CHECK: :[[@LINE]]:13: error: invalid operand for instruction
fmv.w.x a5, t5 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction fmv.w.x a5, t5 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
# FP registers where integer regs are expected # FP registers where integer regs are expected
fcvt.s.l a2, ft2 # CHECK: :[[@LINE]]:14: error: invalid operand for instruction fcvt.s.l a2, ft2 # CHECK: :[[@LINE]]:14: error: invalid operand for instruction
fcvt.s.lu a3, ft3 # CHECK: :[[@LINE]]:15: error: invalid operand for instruction fcvt.s.lu a3, ft3 # CHECK: :[[@LINE]]:15: error: invalid operand for instruction

llvm/test/MC/RISCV/rv64zhinx-invalid.s

# RUN: not llvm-mc -triple riscv64 -mattr=+zhinx %s 2>&1 | FileCheck %s # RUN: not llvm-mc -triple riscv64 -mattr=+zhinx %s 2>&1 | FileCheck %s
# Not support float registers
flw fa4, 12(sp) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'F' (Single-Precision Floating-Point)
benshi001Unsubmitted
Done
ReplyInline Actions

I guess you want flh/fsh ?

benshi001: I guess you want `flh`/`fsh` ?
# Invalid instructions # Invalid instructions
fsw a5, 12(sp) # CHECK: :[[@LINE]]:5: error: invalid operand for instruction
fmv.x.h t2, a2 # CHECK: :[[@LINE]]:13: error: invalid operand for instruction fmv.x.h t2, a2 # CHECK: :[[@LINE]]:13: error: invalid operand for instruction
fmv.h.x a5, t5 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction fmv.h.x a5, t5 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
# FP registers where integer regs are expected # FP registers where integer regs are expected
fcvt.h.l a2, ft2 # CHECK: :[[@LINE]]:14: error: invalid operand for instruction fcvt.h.l a2, ft2 # CHECK: :[[@LINE]]:14: error: invalid operand for instruction
fcvt.h.lu a3, ft3 # CHECK: :[[@LINE]]:15: error: invalid operand for instruction fcvt.h.lu a3, ft3 # CHECK: :[[@LINE]]:15: error: invalid operand for instruction

llvm/test/MC/RISCV/rv64zhinxmin-invalid.s

# RUN: not llvm-mc -triple riscv64 -mattr=+zhinx %s 2>&1 | FileCheck %s # RUN: not llvm-mc -triple riscv64 -mattr=+zhinx %s 2>&1 | FileCheck %s
# Not support float registers
flw fa4, 12(sp) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'F' (Single-Precision Floating-Point)
benshi001Unsubmitted
Done
ReplyInline Actions

I guess you want flh/fsh ?

benshi001: I guess you want `flh`/`fsh` ?
Pretty-boxAuthorUnsubmitted
Done
ReplyInline Actions

Modified RUN line -mattr

Pretty-box: Modified RUN line -mattr
# Invalid instructions # Invalid instructions
fsw a5, 12(sp) # CHECK: :[[@LINE]]:5: error: invalid operand for instruction
fmv.x.h t2, a2 # CHECK: :[[@LINE]]:13: error: invalid operand for instruction fmv.x.h t2, a2 # CHECK: :[[@LINE]]:13: error: invalid operand for instruction
fmv.h.x a5, t5 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction fmv.h.x a5, t5 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
# FP registers where integer regs are expected # FP registers where integer regs are expected
fcvt.d.h a0, fa2 # CHECK: :[[@LINE]]:14: error: invalid operand for instruction fcvt.d.h a0, fa2 # CHECK: :[[@LINE]]:14: error: invalid operand for instruction
fcvt.h.d a0, fa2 # CHECK: :[[@LINE]]:14: error: invalid operand for instruction fcvt.h.d a0, fa2 # CHECK: :[[@LINE]]:14: error: invalid operand for instruction