This is an archive of the discontinued LLVM Phabricator instance.

Show First 20 Lines • Show All 692 Lines • ▼ Show 20 Lines	Generic
access to LDS requires hardware aperture setup and M0 (GFX7-GFX8) register		access to LDS requires hardware aperture setup and M0 (GFX7-GFX8) register
setup (see :ref:`amdgpu-amdhsa-kernel-prolog-m0`).		setup (see :ref:`amdgpu-amdhsa-kernel-prolog-m0`).

To convert between a private or group address space address (termed a segment		To convert between a private or group address space address (termed a segment
address) and a flat address the base address of the corresponding aperture		address) and a flat address the base address of the corresponding aperture
can be used. For GFX7-GFX8 these are available in the		can be used. For GFX7-GFX8 these are available in the
:ref:`amdgpu-amdhsa-hsa-aql-queue` the address of which can be obtained with		:ref:`amdgpu-amdhsa-hsa-aql-queue` the address of which can be obtained with
Queue Ptr SGPR (see :ref:`amdgpu-amdhsa-initial-kernel-execution-state`). For		Queue Ptr SGPR (see :ref:`amdgpu-amdhsa-initial-kernel-execution-state`). For
GFX9-GFX10 the aperture base addresses are directly available as inline		GFX9-GFX11 the aperture base addresses are directly available as inline
constant registers ``SRC_SHARED_BASE/LIMIT`` and ``SRC_PRIVATE_BASE/LIMIT``.		constant registers ``SRC_SHARED_BASE/LIMIT`` and ``SRC_PRIVATE_BASE/LIMIT``.
In 64-bit address mode the aperture sizes are 2^32 bytes and the base is		In 64-bit address mode the aperture sizes are 2^32 bytes and the base is
aligned to 2^32 which makes it easier to convert from flat to segment or		aligned to 2^32 which makes it easier to convert from flat to segment or
segment to flat.		segment to flat.

A global address space address has the same value when used as a flat address		A global address space address has the same value when used as a flat address
so no conversion is needed.		so no conversion is needed.

▲ Show 20 Lines • Show All 53 Lines • ▼ Show 20 Lines	Private
There are different ways that the wavefront scratch base address is		There are different ways that the wavefront scratch base address is
determined by a wavefront (see		determined by a wavefront (see
:ref:`amdgpu-amdhsa-initial-kernel-execution-state`).		:ref:`amdgpu-amdhsa-initial-kernel-execution-state`).

Scratch memory can be accessed in an interleaved manner using buffer		Scratch memory can be accessed in an interleaved manner using buffer
instructions with the scratch buffer descriptor and per wavefront scratch		instructions with the scratch buffer descriptor and per wavefront scratch
offset, by the scratch instructions, or by flat instructions. Multi-dword		offset, by the scratch instructions, or by flat instructions. Multi-dword
access is not supported except by flat and scratch instructions in		access is not supported except by flat and scratch instructions in
GFX9-GFX10.		GFX9-GFX11.

Constant 32-bit		Constant 32-bit
TODO		TODO

Buffer Fat Pointer		Buffer Fat Pointer
The buffer fat pointer is an experimental address space that is currently		The buffer fat pointer is an experimental address space that is currently
unsupported in the backend. It exposes a non-integral pointer that is in		unsupported in the backend. It exposes a non-integral pointer that is in
the future intended to support the modelling of 128-bit buffer descriptors		the future intended to support the modelling of 128-bit buffer descriptors
▲ Show 20 Lines • Show All 1,751 Lines • ▼ Show 20 Lines
``address_size`` (ubyte)		``address_size`` (ubyte)
Matches the address size for the ``Global`` address space defined in		Matches the address size for the ``Global`` address space defined in
:ref:`amdgpu-dwarf-address-space-identifier`.		:ref:`amdgpu-dwarf-address-space-identifier`.

``segment_selector_size`` (ubyte)		``segment_selector_size`` (ubyte)
AMDGPU does not use a segment selector so this is 0.		AMDGPU does not use a segment selector so this is 0.

``minimum_instruction_length`` (ubyte)		``minimum_instruction_length`` (ubyte)
For GFX9-GFX10 this is 4.		For GFX9-GFX11 this is 4.

``maximum_operations_per_instruction`` (ubyte)		``maximum_operations_per_instruction`` (ubyte)
For GFX9-GFX10 this is 1.		For GFX9-GFX11 this is 1.

Source text for online-compiled programs (for example, those compiled by the		Source text for online-compiled programs (for example, those compiled by the
OpenCL language runtime) may be embedded into the DWARF Version 5 line table.		OpenCL language runtime) may be embedded into the DWARF Version 5 line table.
See DWARF Version 5 section 6.2.4.1 which is updated by *DWARF Extensions For		See DWARF Version 5 section 6.2.4.1 which is updated by *DWARF Extensions For
Heterogeneous Debugging* section :ref:`DW_LNCT_LLVM_source		Heterogeneous Debugging* section :ref:`DW_LNCT_LLVM_source
<amdgpu-dwarf-line-number-information-dw-lnct-llvm-source>`.		<amdgpu-dwarf-line-number-information-dw-lnct-llvm-source>`.

The Clang option used to control source embedding in AMDGPU is defined in		The Clang option used to control source embedding in AMDGPU is defined in
▲ Show 20 Lines • Show All 466 Lines • ▼ Show 20 Lines	"KernargSegmentAlign" integer Required The maximum byte
arguments in the		arguments in the
kernarg segment. Must		kernarg segment. Must
be a power of 2.		be a power of 2.
"WavefrontSize" integer Required Wavefront size. Must		"WavefrontSize" integer Required Wavefront size. Must
be a power of 2.		be a power of 2.
"NumSGPRs" integer Required Number of scalar		"NumSGPRs" integer Required Number of scalar
registers used by a		registers used by a
wavefront for		wavefront for
GFX6-GFX10. This		GFX6-GFX11. This
includes the special		includes the special
SGPRs for VCC, Flat		SGPRs for VCC, Flat
Scratch (GFX7-GFX10)		Scratch (GFX7-GFX10)
and XNACK (for		and XNACK (for
GFX8-GFX10). It does		GFX8-GFX10). It does
not include the 16		not include the 16
SGPR added if a trap		SGPR added if a trap
handler is		handler is
enabled. It is not		enabled. It is not
rounded up to the		rounded up to the
allocation		allocation
granularity.		granularity.
"NumVGPRs" integer Required Number of vector		"NumVGPRs" integer Required Number of vector
registers used by		registers used by
each work-item for		each work-item for
GFX6-GFX10		GFX6-GFX11
"MaxFlatWorkGroupSize" integer Required Maximum flat		"MaxFlatWorkGroupSize" integer Required Maximum flat
work-group size		work-group size
supported by the		supported by the
kernel in work-items.		kernel in work-items.
Must be >=1 and		Must be >=1 and
consistent with		consistent with
ReqdWorkGroupSize if		ReqdWorkGroupSize if
not 0, 0, 0.		not 0, 0, 0.
▲ Show 20 Lines • Show All 738 Lines • ▼ Show 20 Lines

There are different ways that the wavefront scratch base address is determined		There are different ways that the wavefront scratch base address is determined
by a wavefront (see :ref:`amdgpu-amdhsa-initial-kernel-execution-state`). This		by a wavefront (see :ref:`amdgpu-amdhsa-initial-kernel-execution-state`). This
memory can be accessed in an interleaved manner using buffer instruction with		memory can be accessed in an interleaved manner using buffer instruction with
the scratch buffer descriptor and per wavefront scratch offset, by the scratch		the scratch buffer descriptor and per wavefront scratch offset, by the scratch
instructions, or by flat instructions. If each lane of a wavefront accesses the		instructions, or by flat instructions. If each lane of a wavefront accesses the
same private address, the interleaving results in adjacent dwords being accessed		same private address, the interleaving results in adjacent dwords being accessed
and hence requires fewer cache lines to be fetched. Multi-dword access is not		and hence requires fewer cache lines to be fetched. Multi-dword access is not
supported except by flat and scratch instructions in GFX9-GFX10.		supported except by flat and scratch instructions in GFX9-GFX11.

The generic address space uses the hardware flat address support available in		The generic address space uses the hardware flat address support available in
GFX7-GFX10. This uses two fixed ranges of virtual addresses (the private and		GFX7-GFX11. This uses two fixed ranges of virtual addresses (the private and
local apertures), that are outside the range of addressible global memory, to		local apertures), that are outside the range of addressible global memory, to
map from a flat address to a private or local address.		map from a flat address to a private or local address.

FLAT instructions can take a flat address and access global, private (scratch)		FLAT instructions can take a flat address and access global, private (scratch)
and group (LDS) memory depending on if the address is within one of the		and group (LDS) memory depending on if the address is within one of the
aperture ranges. Flat access to scratch requires hardware aperture setup and		aperture ranges. Flat access to scratch requires hardware aperture setup and
setup in the kernel prologue (see		setup in the kernel prologue (see
:ref:`amdgpu-amdhsa-kernel-prolog-flat-scratch`). Flat access to LDS requires		:ref:`amdgpu-amdhsa-kernel-prolog-flat-scratch`). Flat access to LDS requires
hardware aperture setup and M0 (GFX7-GFX8) register setup (see		hardware aperture setup and M0 (GFX7-GFX8) register setup (see
:ref:`amdgpu-amdhsa-kernel-prolog-m0`).		:ref:`amdgpu-amdhsa-kernel-prolog-m0`).

To convert between a segment address and a flat address the base address of the		To convert between a segment address and a flat address the base address of the
apertures address can be used. For GFX7-GFX8 these are available in the		apertures address can be used. For GFX7-GFX8 these are available in the
:ref:`amdgpu-amdhsa-hsa-aql-queue` the address of which can be obtained with		:ref:`amdgpu-amdhsa-hsa-aql-queue` the address of which can be obtained with
Queue Ptr SGPR (see :ref:`amdgpu-amdhsa-initial-kernel-execution-state`). For		Queue Ptr SGPR (see :ref:`amdgpu-amdhsa-initial-kernel-execution-state`). For
GFX9-GFX10 the aperture base addresses are directly available as inline constant		GFX9-GFX11 the aperture base addresses are directly available as inline constant
registers ``SRC_SHARED_BASE/LIMIT`` and ``SRC_PRIVATE_BASE/LIMIT``. In 64 bit		registers ``SRC_SHARED_BASE/LIMIT`` and ``SRC_PRIVATE_BASE/LIMIT``. In 64 bit
address mode the aperture sizes are 2^32 bytes and the base is aligned to 2^32		address mode the aperture sizes are 2^32 bytes and the base is aligned to 2^32
which makes it easier to convert from flat to segment or segment to flat.		which makes it easier to convert from flat to segment or segment to flat.

Image and Samplers		Image and Samplers
~~~~~~~~~~~~~~~~~~		~~~~~~~~~~~~~~~~~~

Image and sample handles created by an HSA compatible runtime (see		Image and sample handles created by an HSA compatible runtime (see
▲ Show 20 Lines • Show All 107 Lines • ▼ Show 20 Lines	383:352 4 bytes COMPUTE_PGM_RSRC3 GFX6-GFX9
GFX90A, GFX940		GFX90A, GFX940
Compute Shader (CS)		Compute Shader (CS)
program settings used by		program settings used by
CP to set up		CP to set up
``COMPUTE_PGM_RSRC3``		``COMPUTE_PGM_RSRC3``
configuration		configuration
register. See		register. See
:ref:`amdgpu-amdhsa-compute_pgm_rsrc3-gfx90a-table`.		:ref:`amdgpu-amdhsa-compute_pgm_rsrc3-gfx90a-table`.
GFX10		GFX10-GFX11
Compute Shader (CS)		Compute Shader (CS)
program settings used by		program settings used by
CP to set up		CP to set up
``COMPUTE_PGM_RSRC3``		``COMPUTE_PGM_RSRC3``
configuration		configuration
register. See		register. See
:ref:`amdgpu-amdhsa-compute_pgm_rsrc3-gfx10-table`.		:ref:`amdgpu-amdhsa-compute_pgm_rsrc3-gfx10-gfx11-table`.
415:384 4 bytes COMPUTE_PGM_RSRC1 Compute Shader (CS)		415:384 4 bytes COMPUTE_PGM_RSRC1 Compute Shader (CS)
program settings used by		program settings used by
CP to set up		CP to set up
``COMPUTE_PGM_RSRC1``		``COMPUTE_PGM_RSRC1``
configuration		configuration
register. See		register. See
:ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx10-table`.		:ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx11-table`.
447:416 4 bytes COMPUTE_PGM_RSRC2 Compute Shader (CS)		447:416 4 bytes COMPUTE_PGM_RSRC2 Compute Shader (CS)
program settings used by		program settings used by
CP to set up		CP to set up
``COMPUTE_PGM_RSRC2``		``COMPUTE_PGM_RSRC2``
configuration		configuration
register. See		register. See
:ref:`amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx10-table`.		:ref:`amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx11-table`.
458:448 7 bits See separate bits below. Enable the setup of the		458:448 7 bits See separate bits below. Enable the setup of the
SGPR user data registers		SGPR user data registers
(see		(see
:ref:`amdgpu-amdhsa-initial-kernel-execution-state`).		:ref:`amdgpu-amdhsa-initial-kernel-execution-state`).

The total number of SGPR		The total number of SGPR
user data registers		user data registers
requested must not exceed		requested must not exceed
Show All 17 Lines	>453 1 bit ENABLE_SGPR_FLAT_SCRATCH_INIT If the Target Properties
specifies *Architected flat		specifies *Architected flat
scratch* then not supported		scratch* then not supported
and must be 0,		and must be 0,
>454 1 bit ENABLE_SGPR_PRIVATE_SEGMENT		>454 1 bit ENABLE_SGPR_PRIVATE_SEGMENT
_SIZE		_SIZE
457:455 3 bits Reserved, must be 0.		457:455 3 bits Reserved, must be 0.
458 1 bit ENABLE_WAVEFRONT_SIZE32 GFX6-GFX9		458 1 bit ENABLE_WAVEFRONT_SIZE32 GFX6-GFX9
Reserved, must be 0.		Reserved, must be 0.
GFX10		GFX10-GFX11
- If 0 execute in		- If 0 execute in
wavefront size 64 mode.		wavefront size 64 mode.
- If 1 execute in		- If 1 execute in
native wavefront size		native wavefront size
32 mode.		32 mode.
463:459 1 bit Reserved, must be 0.		463:459 1 bit Reserved, must be 0.
464 1 bit RESERVED_464 Deprecated, must be 0.		464 1 bit RESERVED_464 Deprecated, must be 0.
467:465 3 bits Reserved, must be 0.		467:465 3 bits Reserved, must be 0.
468 1 bit RESERVED_468 Deprecated, must be 0.		468 1 bit RESERVED_468 Deprecated, must be 0.
469:471 3 bits Reserved, must be 0.		469:471 3 bits Reserved, must be 0.
511:472 5 bytes Reserved, must be 0.		511:472 5 bytes Reserved, must be 0.
512 Total size 64 bytes.		512 Total size 64 bytes.
======= ====================================================================		======= ====================================================================

..		..

.. table:: compute_pgm_rsrc1 for GFX6-GFX10		.. table:: compute_pgm_rsrc1 for GFX6-GFX11
:name: amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx10-table		:name: amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx11-table

======= ======= =============================== ===========================================================================		======= ======= =============================== ===========================================================================
Bits Size Field Name Description		Bits Size Field Name Description
======= ======= =============================== ===========================================================================		======= ======= =============================== ===========================================================================
5:0 6 bits GRANULATED_WORKITEM_VGPR_COUNT Number of vector register		5:0 6 bits GRANULATED_WORKITEM_VGPR_COUNT Number of vector register
blocks used by each work-item;		blocks used by each work-item;
granularity is device		granularity is device
specific:		specific:

GFX6-GFX9		GFX6-GFX9
- vgprs_used 0..256		- vgprs_used 0..256
- max(0, ceil(vgprs_used / 4) - 1)		- max(0, ceil(vgprs_used / 4) - 1)
GFX90A, GFX940		GFX90A, GFX940
- vgprs_used 0..512		- vgprs_used 0..512
- vgprs_used = align(arch_vgprs, 4)		- vgprs_used = align(arch_vgprs, 4)
+ acc_vgprs		+ acc_vgprs
- max(0, ceil(vgprs_used / 8) - 1)		- max(0, ceil(vgprs_used / 8) - 1)
GFX10 (wavefront size 64)		GFX10-GFX11 (wavefront size 64)
- max_vgpr 1..256		- max_vgpr 1..256
- max(0, ceil(vgprs_used / 4) - 1)		- max(0, ceil(vgprs_used / 4) - 1)
GFX10 (wavefront size 32)		GFX10-GFX11 (wavefront size 32)
- max_vgpr 1..256		- max_vgpr 1..256
- max(0, ceil(vgprs_used / 8) - 1)		- max(0, ceil(vgprs_used / 8) - 1)

Where vgprs_used is defined		Where vgprs_used is defined
as the highest VGPR number		as the highest VGPR number
explicitly referenced plus		explicitly referenced plus
one.		one.

Show All 17 Lines	9:6 4 bits GRANULATED_WAVEFRONT_SGPR_COUNT Number of scalar register
specific:		specific:

GFX6-GFX8		GFX6-GFX8
- sgprs_used 0..112		- sgprs_used 0..112
- max(0, ceil(sgprs_used / 8) - 1)		- max(0, ceil(sgprs_used / 8) - 1)
GFX9		GFX9
- sgprs_used 0..112		- sgprs_used 0..112
- 2 * max(0, ceil(sgprs_used / 16) - 1)		- 2 * max(0, ceil(sgprs_used / 16) - 1)
GFX10		GFX10-GFX11
Reserved, must be 0.		Reserved, must be 0.
(128 SGPRs always		(128 SGPRs always
allocated.)		allocated.)

Where sgprs_used is		Where sgprs_used is
defined as the highest		defined as the highest
SGPR number explicitly		SGPR number explicitly
referenced plus one, plus		referenced plus one, plus
▲ Show 20 Lines • Show All 150 Lines • ▼ Show 20 Lines	25 1 bit CDBG_USER Must be 0.
Flag that can be used to		Flag that can be used to
control debugging code.		control debugging code.

CP is responsible for		CP is responsible for
filling in		filling in
``COMPUTE_PGM_RSRC1.CDBG_USER``.		``COMPUTE_PGM_RSRC1.CDBG_USER``.
26 1 bit FP16_OVFL GFX6-GFX8		26 1 bit FP16_OVFL GFX6-GFX8
Reserved, must be 0.		Reserved, must be 0.
GFX9-GFX10		GFX9-GFX11
Wavefront starts execution		Wavefront starts execution
with specified fp16 overflow		with specified fp16 overflow
mode.		mode.

- If 0, fp16 overflow generates		- If 0, fp16 overflow generates
+/-INF values.		+/-INF values.
- If 1, fp16 overflow that is the		- If 1, fp16 overflow that is the
result of an +/-INF input value		result of an +/-INF input value
or divide by 0 produces a +/-INF,		or divide by 0 produces a +/-INF,
otherwise clamps computed		otherwise clamps computed
overflow to +/-MAX_FP16 as		overflow to +/-MAX_FP16 as
appropriate.		appropriate.

Used by CP to set up		Used by CP to set up
``COMPUTE_PGM_RSRC1.FP16_OVFL``.		``COMPUTE_PGM_RSRC1.FP16_OVFL``.
28:27 2 bits Reserved, must be 0.		28:27 2 bits Reserved, must be 0.
29 1 bit WGP_MODE GFX6-GFX9		29 1 bit WGP_MODE GFX6-GFX9
Reserved, must be 0.		Reserved, must be 0.
GFX10		GFX10-GFX11
- If 0 execute work-groups in		- If 0 execute work-groups in
CU wavefront execution mode.		CU wavefront execution mode.
- If 1 execute work-groups on		- If 1 execute work-groups on
in WGP wavefront execution mode.		in WGP wavefront execution mode.

See :ref:`amdgpu-amdhsa-memory-model`.		See :ref:`amdgpu-amdhsa-memory-model`.

Used by CP to set up		Used by CP to set up
``COMPUTE_PGM_RSRC1.WGP_MODE``.		``COMPUTE_PGM_RSRC1.WGP_MODE``.
30 1 bit MEM_ORDERED GFX6-GFX9		30 1 bit MEM_ORDERED GFX6-GFX9
Reserved, must be 0.		Reserved, must be 0.
GFX10		GFX10-GFX11
Controls the behavior of the		Controls the behavior of the
s_waitcnt's vmcnt and vscnt		s_waitcnt's vmcnt and vscnt
counters.		counters.

- If 0 vmcnt reports completion		- If 0 vmcnt reports completion
of load and atomic with return		of load and atomic with return
out of order with sample		out of order with sample
instructions, and the vscnt		instructions, and the vscnt
reports the completion of		reports the completion of
store and atomic without		store and atomic without
return in order.		return in order.
- If 1 vmcnt reports completion		- If 1 vmcnt reports completion
of load, atomic with return		of load, atomic with return
and sample instructions in		and sample instructions in
order, and the vscnt reports		order, and the vscnt reports
the completion of store and		the completion of store and
atomic without return in order.		atomic without return in order.

Used by CP to set up		Used by CP to set up
``COMPUTE_PGM_RSRC1.MEM_ORDERED``.		``COMPUTE_PGM_RSRC1.MEM_ORDERED``.
31 1 bit FWD_PROGRESS GFX6-GFX9		31 1 bit FWD_PROGRESS GFX6-GFX9
Reserved, must be 0.		Reserved, must be 0.
GFX10		GFX10-GFX11
- If 0 execute SIMD wavefronts		- If 0 execute SIMD wavefronts
using oldest first policy.		using oldest first policy.
- If 1 execute SIMD wavefronts to		- If 1 execute SIMD wavefronts to
ensure wavefronts will make some		ensure wavefronts will make some
forward progress.		forward progress.

Used by CP to set up		Used by CP to set up
``COMPUTE_PGM_RSRC1.FWD_PROGRESS``.		``COMPUTE_PGM_RSRC1.FWD_PROGRESS``.
32 Total size 4 bytes		32 Total size 4 bytes
======= ===================================================================================================================		======= ===================================================================================================================

..		..

.. table:: compute_pgm_rsrc2 for GFX6-GFX10		.. table:: compute_pgm_rsrc2 for GFX6-GFX11
:name: amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx10-table		:name: amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx11-table

======= ======= =============================== ===========================================================================		======= ======= =============================== ===========================================================================
Bits Size Field Name Description		Bits Size Field Name Description
======= ======= =============================== ===========================================================================		======= ======= =============================== ===========================================================================
0 1 bit ENABLE_PRIVATE_SEGMENT * Enable the setup of the		0 1 bit ENABLE_PRIVATE_SEGMENT * Enable the setup of the
private segment.		private segment.
* If the Target Properties		* If the Target Properties
column of		column of
▲ Show 20 Lines • Show All 120 Lines • ▼ Show 20 Lines	23:15 9 bits GRANULATED_LDS_SIZE Must be 0.

Amount of group segment		Amount of group segment
(LDS) to allocate for each		(LDS) to allocate for each
work-group. Granularity is		work-group. Granularity is
device specific:		device specific:

GFX6		GFX6
roundup(lds-size / (64 * 4))		roundup(lds-size / (64 * 4))
GFX7-GFX10		GFX7-GFX11
roundup(lds-size / (128 * 4))		roundup(lds-size / (128 * 4))

24 1 bit ENABLE_EXCEPTION_IEEE_754_FP Wavefront starts execution		24 1 bit ENABLE_EXCEPTION_IEEE_754_FP Wavefront starts execution
_INVALID_OPERATION with specified exceptions		_INVALID_OPERATION with specified exceptions
enabled.		enabled.

Used by CP to set up		Used by CP to set up
``COMPUTE_PGM_RSRC2.EXCP_EN``		``COMPUTE_PGM_RSRC2.EXCP_EN``
Show All 39 Lines	16 1 bit TG_SPLIT - If 0 the waves of a work-group are
cannot use S_BARRIER or LDS.		cannot use S_BARRIER or LDS.
17:31 15 Reserved, must be 0.		17:31 15 Reserved, must be 0.
bits		bits
32 Total size 4 bytes.		32 Total size 4 bytes.
======= ===================================================================================================================		======= ===================================================================================================================

..		..

.. table:: compute_pgm_rsrc3 for GFX10		.. table:: compute_pgm_rsrc3 for GFX10-GFX11
:name: amdgpu-amdhsa-compute_pgm_rsrc3-gfx10-table		:name: amdgpu-amdhsa-compute_pgm_rsrc3-gfx10-gfx11-table

======= ======= =============================== ===========================================================================		======= ======= =============================== ===========================================================================
Bits Size Field Name Description		Bits Size Field Name Description
======= ======= =============================== ===========================================================================		======= ======= =============================== ===========================================================================
3:0 4 bits SHARED_VGPR_COUNT Number of shared VGPR blocks when executing in subvector mode. For		3:0 4 bits SHARED_VGPR_COUNT Number of shared VGPR blocks when executing in subvector mode. For
wavefront size 64 the value is 0-15, representing 0-120 VGPRs (granularity		wavefront size 64 the value is 0-15, representing 0-120 VGPRs (granularity
of 8), such that (compute_pgm_rsrc1.vgprs +1)4 + shared_vgpr_count8 does		of 8), such that (compute_pgm_rsrc1.vgprs +1)4 + shared_vgpr_count8 does
not exceed 256. For wavefront size 32 shared_vgpr_count must be 0.		not exceed 256. For wavefront size 32 shared_vgpr_count must be 0.
31:4 28 Reserved, must be 0.		9:4 6 bits INST_PREF_SIZE GFX10
bits		Reserved, must be 0.
		GFX11
		Number of instruction bytes to prefetch, starting at the kernel's entry
		point instruction, before wavefront starts execution. The value is 0..63
		with a granularity of 128 bytes.
		10 1 bit TRAP_ON_START GFX10
		Reserved, must be 0.
		GFX11
		Must be 0.

		If 1, wavefront starts execution by trapping into the trap handler.

		CP is responsible for filling in the trap on start bit in
		``COMPUTE_PGM_RSRC3.TRAP_ON_START`` according to what the runtime
		requests.
		11 1 bit TRAP_ON_END GFX10
		Reserved, must be 0.
		GFX11
		Must be 0.

		If 1, wavefront execution terminates by trapping into the trap handler.

		CP is responsible for filling in the trap on end bit in
		``COMPUTE_PGM_RSRC3.TRAP_ON_END`` according to what the runtime requests.
		30:12 19 bits Reserved, must be 0.
		31 1 bit IMAGE_OP GFX10
		Reserved, must be 0.
		GFX11
		If 1, the kernel execution contains image instructions. If executed as
		arsenmUnsubmitted Done Reply Inline Actions Weird looking wrapping throughout arsenm: Weird looking wrapping throughout
		part of a graphics pipeline, image read instructions will stall waiting
		for any necessary ``WAIT_SYNC`` fence to be performed in order to
		indicate that earlier pipeline stages have completed writing to the
		image.

		Not used for compute kernels that are not part of a graphics pipeline and
		must be 0.
32 Total size 4 bytes.		32 Total size 4 bytes.
======= ===================================================================================================================		======= ===================================================================================================================

..		..

.. table:: Floating Point Rounding Mode Enumeration Values		.. table:: Floating Point Rounding Mode Enumeration Values
:name: amdgpu-amdhsa-floating-point-rounding-mode-enumeration-values-table		:name: amdgpu-amdhsa-floating-point-rounding-mode-enumeration-values-table

▲ Show 20 Lines • Show All 109 Lines • ▼ Show 20 Lines	then Private Segment Size 1 The 32-bit byte size of a
Having CP load it once avoids		Having CP load it once avoids
loading it at the beginning of		loading it at the beginning of
every wavefront.		every wavefront.

This is not used for		This is not used for
GFX7-GFX8 since it is the same		GFX7-GFX8 since it is the same
value as the second SGPR of		value as the second SGPR of
Flat Scratch Init. However, it		Flat Scratch Init. However, it
may be needed for GFX9-GFX10 which		may be needed for GFX9-GFX11 which
changes the meaning of the		changes the meaning of the
Flat Scratch Init value.		Flat Scratch Init value.
then Work-Group Id X 1 32-bit work-group id in X		then Work-Group Id X 1 32-bit work-group id in X
(enable_sgpr_workgroup_id dimension of grid for		(enable_sgpr_workgroup_id dimension of grid for
_X) wavefront.		_X) wavefront.
then Work-Group Id Y 1 32-bit work-group id in Y		then Work-Group Id Y 1 32-bit work-group id in Y
(enable_sgpr_workgroup_id dimension of grid for		(enable_sgpr_workgroup_id dimension of grid for
_Y) wavefront.		_Y) wavefront.
▲ Show 20 Lines • Show All 85 Lines • ▼ Show 20 Lines	3. Scratch Wavefront Offset is set by SPI in a per wavefront basis which is why
its value cannot be included with the flat scratch init value which is per		its value cannot be included with the flat scratch init value which is per
queue (see :ref:`amdgpu-amdhsa-kernel-prolog-flat-scratch`).		queue (see :ref:`amdgpu-amdhsa-kernel-prolog-flat-scratch`).
4. The VGPRs are set by SPI which only supports specifying either (X), (X, Y)		4. The VGPRs are set by SPI which only supports specifying either (X), (X, Y)
or (X, Y, Z).		or (X, Y, Z).
5. Flat Scratch register pair initialization is described in		5. Flat Scratch register pair initialization is described in
:ref:`amdgpu-amdhsa-kernel-prolog-flat-scratch`.		:ref:`amdgpu-amdhsa-kernel-prolog-flat-scratch`.

The global segment can be accessed either using buffer instructions (GFX6 which		The global segment can be accessed either using buffer instructions (GFX6 which
has V# 64-bit address support), flat instructions (GFX7-GFX10), or global		has V# 64-bit address support), flat instructions (GFX7-GFX11), or global
instructions (GFX9-GFX10).		instructions (GFX9-GFX11).

If buffer operations are used, then the compiler can generate a V# with the		If buffer operations are used, then the compiler can generate a V# with the
following properties:		following properties:

* base address of 0		* base address of 0
* no swizzle		* no swizzle
* ATC: 1 if IOMMU present (such as APU)		* ATC: 1 if IOMMU present (such as APU)
* ptr64: 1		* ptr64: 1
Show All 29 Lines
++		++

GFX6-GFX8		GFX6-GFX8
The M0 register must be initialized with a value at least the total LDS size		The M0 register must be initialized with a value at least the total LDS size
if the kernel may access LDS via DS or flat operations. Total LDS size is		if the kernel may access LDS via DS or flat operations. Total LDS size is
available in dispatch packet. For M0, it is also possible to use maximum		available in dispatch packet. For M0, it is also possible to use maximum
possible value of LDS for given target (0x7FFF for GFX6 and 0xFFFF for		possible value of LDS for given target (0x7FFF for GFX6 and 0xFFFF for
GFX7-GFX8).		GFX7-GFX8).
GFX9-GFX10		GFX9-GFX11
The M0 register is not used for range checking LDS accesses and so does not		The M0 register is not used for range checking LDS accesses and so does not
need to be initialized in the prolog.		need to be initialized in the prolog.

.. _amdgpu-amdhsa-kernel-prolog-stack-pointer:		.. _amdgpu-amdhsa-kernel-prolog-stack-pointer:

Stack Pointer		Stack Pointer
+++++++++++++		+++++++++++++

▲ Show 20 Lines • Show All 95 Lines • ▼ Show 20 Lines	* If the Target Properties column of :ref:`amdgpu-processor-table`
The Scratch Wavefront Offset must also be used as an offset with Private		The Scratch Wavefront Offset must also be used as an offset with Private
segment address when using the Scratch Segment Buffer (see		segment address when using the Scratch Segment Buffer (see
:ref:`amdgpu-amdhsa-kernel-prolog-private-segment-buffer`).		:ref:`amdgpu-amdhsa-kernel-prolog-private-segment-buffer`).

* If the Target Properties column of :ref:`amdgpu-processor-table`		* If the Target Properties column of :ref:`amdgpu-processor-table`
specifies Architected flat scratch:		specifies Architected flat scratch:

If ENABLE_PRIVATE_SEGMENT is enabled in		If ENABLE_PRIVATE_SEGMENT is enabled in
:ref:`amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx10-table` then the FLAT_SCRATCH		:ref:`amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx11-table` then the FLAT_SCRATCH
register pair will be initialized to the 64-bit address of the base of scratch		register pair will be initialized to the 64-bit address of the base of scratch
backing memory being managed by SPI for the queue executing the kernel		backing memory being managed by SPI for the queue executing the kernel
dispatch plus the value of the wave's Scratch Wavefront Offset for use as the		dispatch plus the value of the wave's Scratch Wavefront Offset for use as the
flat scratch base in flat memory instructions.		flat scratch base in flat memory instructions.

.. _amdgpu-amdhsa-kernel-prolog-private-segment-buffer:		.. _amdgpu-amdhsa-kernel-prolog-private-segment-buffer:

Private Segment Buffer		Private Segment Buffer
▲ Show 20 Lines • Show All 92 Lines • ▼ Show 20 Lines

``ds/flat_load/store/atomic`` instructions to local memory are termed LDS		``ds/flat_load/store/atomic`` instructions to local memory are termed LDS
operations.		operations.

``buffer/global/flat_load/store/atomic`` instructions to global memory are		``buffer/global/flat_load/store/atomic`` instructions to global memory are
termed vector memory operations.		termed vector memory operations.

Private address space uses ``buffer_load/store`` using the scratch V#		Private address space uses ``buffer_load/store`` using the scratch V#
(GFX6-GFX8), or ``scratch_load/store`` (GFX9-GFX10). Since only a single thread		(GFX6-GFX8), or ``scratch_load/store`` (GFX9-GFX11). Since only a single thread
is accessing the memory, atomic memory orderings are not meaningful, and all		is accessing the memory, atomic memory orderings are not meaningful, and all
accesses are treated as non-atomic.		accesses are treated as non-atomic.

Constant address space uses ``buffer/global_load`` instructions (or equivalent		Constant address space uses ``buffer/global_load`` instructions (or equivalent
scalar memory instructions). Since the constant address space contents do not		scalar memory instructions). Since the constant address space contents do not
change during the execution of a kernel dispatch it is not legal to perform		change during the execution of a kernel dispatch it is not legal to perform
stores, and atomic memory orderings are not meaningful, and all accesses are		stores, and atomic memory orderings are not meaningful, and all accesses are
treated as non-atomic.		treated as non-atomic.
▲ Show 20 Lines • Show All 50 Lines • ▼ Show 20 Lines	.. table:: AMDHSA Memory Model Single Thread Optimization Constraints
============ ==============================================================		============ ==============================================================

The code sequences used to implement the memory model are defined in the		The code sequences used to implement the memory model are defined in the
following sections:		following sections:

* :ref:`amdgpu-amdhsa-memory-model-gfx6-gfx9`		* :ref:`amdgpu-amdhsa-memory-model-gfx6-gfx9`
* :ref:`amdgpu-amdhsa-memory-model-gfx90a`		* :ref:`amdgpu-amdhsa-memory-model-gfx90a`
* :ref:`amdgpu-amdhsa-memory-model-gfx940`		* :ref:`amdgpu-amdhsa-memory-model-gfx940`
* :ref:`amdgpu-amdhsa-memory-model-gfx10`		* :ref:`amdgpu-amdhsa-memory-model-gfx10-gfx11`

.. _amdgpu-amdhsa-memory-model-gfx6-gfx9:		.. _amdgpu-amdhsa-memory-model-gfx6-gfx9:

Memory Model GFX6-GFX9		Memory Model GFX6-GFX9
++++++++++++++++++++++		++++++++++++++++++++++

For GFX6-GFX9:		For GFX6-GFX9:

▲ Show 20 Lines • Show All 6,053 Lines • ▼ Show 20 Lines	atomicrmw seq_cst - singlethread - global *Same as corresponding
- system for OpenCL.*		- system for OpenCL.*
fence seq_cst - singlethread none *Same as corresponding		fence seq_cst - singlethread none *Same as corresponding
- wavefront fence acq_rel,		- wavefront fence acq_rel,
- workgroup except must generate		- workgroup except must generate
- agent all instructions even		- agent all instructions even
- system for OpenCL.*		- system for OpenCL.*
============ ============ ============== ========== ================================		============ ============ ============== ========== ================================

.. _amdgpu-amdhsa-memory-model-gfx10:		.. _amdgpu-amdhsa-memory-model-gfx10-gfx11:

Memory Model GFX10		Memory Model GFX10-GFX11
++++++++++++++++++		++++++++++++++++++++++++

For GFX10:		For GFX10-GFX11:

* Each agent has multiple shader arrays (SA).		* Each agent has multiple shader arrays (SA).
* Each SA has multiple work-group processors (WGP).		* Each SA has multiple work-group processors (WGP).
* Each WGP has multiple compute units (CU).		* Each WGP has multiple compute units (CU).
* Each CU has multiple SIMDs that execute wavefronts.		* Each CU has multiple SIMDs that execute wavefronts.
* The wavefronts for a single work-group are executed in the same		* The wavefronts for a single work-group are executed in the same
WGP. In CU wavefront execution mode the wavefronts may be executed by		WGP. In CU wavefront execution mode the wavefronts may be executed by
different SIMDs in the same CU. In WGP wavefront execution mode the		different SIMDs in the same CU. In WGP wavefront execution mode the
▲ Show 20 Lines • Show All 92 Lines • ▼ Show 20 Lines
with MTYPE NC (non-coherent). Since the private address space is only accessed		with MTYPE NC (non-coherent). Since the private address space is only accessed
by a single thread, and is always write-before-read, there is never a need to		by a single thread, and is always write-before-read, there is never a need to
invalidate these entries from the L0 or L1 caches.		invalidate these entries from the L0 or L1 caches.

Wavefronts are executed in native mode with in-order reporting of loads and		Wavefronts are executed in native mode with in-order reporting of loads and
sample instructions. In this mode vmcnt reports completion of load, atomic with		sample instructions. In this mode vmcnt reports completion of load, atomic with
return and sample instructions in order, and the vscnt reports the completion of		return and sample instructions in order, and the vscnt reports the completion of
store and atomic without return in order. See ``MEM_ORDERED`` field in		store and atomic without return in order. See ``MEM_ORDERED`` field in
:ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx10-table`.		:ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx11-table`.

Wavefronts can be executed in WGP or CU wavefront execution mode:		Wavefronts can be executed in WGP or CU wavefront execution mode:

* In WGP wavefront execution mode the wavefronts of a work-group are executed		* In WGP wavefront execution mode the wavefronts of a work-group are executed
on the SIMDs of both CUs of the WGP. Therefore, explicit management of the per		on the SIMDs of both CUs of the WGP. Therefore, explicit management of the per
CU L0 caches is required for work-group synchronization. Also accesses to L1		CU L0 caches is required for work-group synchronization. Also accesses to L1
at work-group scope need to be explicitly ordered as the accesses from		at work-group scope need to be explicitly ordered as the accesses from
different CUs are not ordered.		different CUs are not ordered.
* In CU wavefront execution mode the wavefronts of a work-group are executed on		* In CU wavefront execution mode the wavefronts of a work-group are executed on
the SIMDs of a single CU of the WGP. Therefore, all global memory access by		the SIMDs of a single CU of the WGP. Therefore, all global memory access by
the work-group access the same L0 which in turn ensures L1 accesses are		the work-group access the same L0 which in turn ensures L1 accesses are
ordered and so do not require explicit management of the caches for		ordered and so do not require explicit management of the caches for
work-group synchronization.		work-group synchronization.

See ``WGP_MODE`` field in		See ``WGP_MODE`` field in
:ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx10-table` and		:ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx11-table` and
:ref:`amdgpu-target-features`.		:ref:`amdgpu-target-features`.

The code sequences used to implement the memory model for GFX10 are defined in		The code sequences used to implement the memory model for GFX10-GFX11 are defined in
table :ref:`amdgpu-amdhsa-memory-model-code-sequences-gfx10-table`.		table :ref:`amdgpu-amdhsa-memory-model-code-sequences-gfx10-gfx11-table`.

.. table:: AMDHSA Memory Model Code Sequences GFX10		.. table:: AMDHSA Memory Model Code Sequences GFX10-GFX11
:name: amdgpu-amdhsa-memory-model-code-sequences-gfx10-table		:name: amdgpu-amdhsa-memory-model-code-sequences-gfx10-gfx11-table

============ ============ ============== ========== ================================		============ ============ ============== ========== ================================
LLVM Instr LLVM Memory LLVM Memory AMDGPU AMDGPU Machine Code		LLVM Instr LLVM Memory LLVM Memory AMDGPU AMDGPU Machine Code
Ordering Sync Scope Address GFX10		Ordering Sync Scope Address GFX10-GFX11
Space		Space
============ ============ ============== ========== ================================		============ ============ ============== ========== ================================
Non-Atomic		Non-Atomic
------------------------------------------------------------------------------------		------------------------------------------------------------------------------------
load none none - global - !volatile & !nontemporal		load none none - global - !volatile & !nontemporal
- generic		- generic
- private 1. buffer/global/flat_load		- private 1. buffer/global/flat_load
- constant		- constant
▲ Show 20 Lines • Show All 2,013 Lines • ▼ Show 20 Lines	.. table:: AMDGPU Trap Handler for AMDHSA OS Code Object V3
=================== =============== =============== =======================================		=================== =============== =============== =======================================

..		..

.. table:: AMDGPU Trap Handler for AMDHSA OS Code Object V4 and Above		.. table:: AMDGPU Trap Handler for AMDHSA OS Code Object V4 and Above
:name: amdgpu-trap-handler-for-amdhsa-os-v4-onwards-table		:name: amdgpu-trap-handler-for-amdhsa-os-v4-onwards-table

=================== =============== ================ ================= =======================================		=================== =============== ================ ================= =======================================
Usage Code Sequence GFX6-GFX8 Inputs GFX9-GFX10 Inputs Description		Usage Code Sequence GFX6-GFX8 Inputs GFX9-GFX11 Inputs Description
=================== =============== ================ ================= =======================================		=================== =============== ================ ================= =======================================
reserved ``s_trap 0x00`` Reserved by hardware.		reserved ``s_trap 0x00`` Reserved by hardware.
debugger breakpoint ``s_trap 0x01`` none none Reserved for debugger to use for		debugger breakpoint ``s_trap 0x01`` none none Reserved for debugger to use for
breakpoints. Causes wave to be halted		breakpoints. Causes wave to be halted
with the PC at the trap instruction.		with the PC at the trap instruction.
The debugger is responsible to resume		The debugger is responsible to resume
the wave, including the instruction		the wave, including the instruction
that the breakpoint overwrote.		that the breakpoint overwrote.
▲ Show 20 Lines • Show All 881 Lines • ▼ Show 20 Lines
1. The HSA memory model is used (see :ref:`amdgpu-amdhsa-memory-model`).		1. The HSA memory model is used (see :ref:`amdgpu-amdhsa-memory-model`).

.. _amdgpu-assembler:		.. _amdgpu-assembler:

Assembler		Assembler
---------		---------

AMDGPU backend has LLVM-MC based assembler which is currently in development.		AMDGPU backend has LLVM-MC based assembler which is currently in development.
It supports AMDGCN GFX6-GFX10.		It supports AMDGCN GFX6-GFX11.

This section describes general syntax for instructions and operands.		This section describes general syntax for instructions and operands.

Instructions		Instructions
~~~~~~~~~~~~		~~~~~~~~~~~~

An instruction has the following :doc:`syntax<AMDGPUInstructionSyntax>`:		An instruction has the following :doc:`syntax<AMDGPUInstructionSyntax>`:

▲ Show 20 Lines • Show All 543 Lines • ▼ Show 20 Lines
terminated by an ``.end_amdhsa_kernel`` directive.		terminated by an ``.end_amdhsa_kernel`` directive.

.. table:: AMDHSA Kernel Assembler Directives		.. table:: AMDHSA Kernel Assembler Directives
:name: amdhsa-kernel-directives-table		:name: amdhsa-kernel-directives-table

======================================================== =================== ============ ===================		======================================================== =================== ============ ===================
Directive Default Supported On Description		Directive Default Supported On Description
======================================================== =================== ============ ===================		======================================================== =================== ============ ===================
``.amdhsa_group_segment_fixed_size`` 0 GFX6-GFX10 Controls GROUP_SEGMENT_FIXED_SIZE in		``.amdhsa_group_segment_fixed_size`` 0 GFX6-GFX11 Controls GROUP_SEGMENT_FIXED_SIZE in
:ref:`amdgpu-amdhsa-kernel-descriptor-v3-table`.		:ref:`amdgpu-amdhsa-kernel-descriptor-v3-table`.
``.amdhsa_private_segment_fixed_size`` 0 GFX6-GFX10 Controls PRIVATE_SEGMENT_FIXED_SIZE in		``.amdhsa_private_segment_fixed_size`` 0 GFX6-GFX11 Controls PRIVATE_SEGMENT_FIXED_SIZE in
:ref:`amdgpu-amdhsa-kernel-descriptor-v3-table`.		:ref:`amdgpu-amdhsa-kernel-descriptor-v3-table`.
``.amdhsa_kernarg_size`` 0 GFX6-GFX10 Controls KERNARG_SIZE in		``.amdhsa_kernarg_size`` 0 GFX6-GFX11 Controls KERNARG_SIZE in
:ref:`amdgpu-amdhsa-kernel-descriptor-v3-table`.		:ref:`amdgpu-amdhsa-kernel-descriptor-v3-table`.
``.amdhsa_user_sgpr_count`` 0 GFX6-GFX10 Controls USER_SGPR_COUNT in COMPUTE_PGM_RSRC2		``.amdhsa_user_sgpr_count`` 0 GFX6-GFX11 Controls USER_SGPR_COUNT in COMPUTE_PGM_RSRC2
:ref:`amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx10-table`		:ref:`amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx11-table`
``.amdhsa_user_sgpr_private_segment_buffer`` 0 GFX6-GFX10 Controls ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER in		``.amdhsa_user_sgpr_private_segment_buffer`` 0 GFX6-GFX10 Controls ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER in
(except :ref:`amdgpu-amdhsa-kernel-descriptor-v3-table`.		(except :ref:`amdgpu-amdhsa-kernel-descriptor-v3-table`.
GFX940)		GFX940)
``.amdhsa_user_sgpr_dispatch_ptr`` 0 GFX6-GFX10 Controls ENABLE_SGPR_DISPATCH_PTR in		``.amdhsa_user_sgpr_dispatch_ptr`` 0 GFX6-GFX11 Controls ENABLE_SGPR_DISPATCH_PTR in
:ref:`amdgpu-amdhsa-kernel-descriptor-v3-table`.		:ref:`amdgpu-amdhsa-kernel-descriptor-v3-table`.
``.amdhsa_user_sgpr_queue_ptr`` 0 GFX6-GFX10 Controls ENABLE_SGPR_QUEUE_PTR in		``.amdhsa_user_sgpr_queue_ptr`` 0 GFX6-GFX11 Controls ENABLE_SGPR_QUEUE_PTR in
:ref:`amdgpu-amdhsa-kernel-descriptor-v3-table`.		:ref:`amdgpu-amdhsa-kernel-descriptor-v3-table`.
``.amdhsa_user_sgpr_kernarg_segment_ptr`` 0 GFX6-GFX10 Controls ENABLE_SGPR_KERNARG_SEGMENT_PTR in		``.amdhsa_user_sgpr_kernarg_segment_ptr`` 0 GFX6-GFX11 Controls ENABLE_SGPR_KERNARG_SEGMENT_PTR in
:ref:`amdgpu-amdhsa-kernel-descriptor-v3-table`.		:ref:`amdgpu-amdhsa-kernel-descriptor-v3-table`.
``.amdhsa_user_sgpr_dispatch_id`` 0 GFX6-GFX10 Controls ENABLE_SGPR_DISPATCH_ID in		``.amdhsa_user_sgpr_dispatch_id`` 0 GFX6-GFX11 Controls ENABLE_SGPR_DISPATCH_ID in
:ref:`amdgpu-amdhsa-kernel-descriptor-v3-table`.		:ref:`amdgpu-amdhsa-kernel-descriptor-v3-table`.
``.amdhsa_user_sgpr_flat_scratch_init`` 0 GFX6-GFX10 Controls ENABLE_SGPR_FLAT_SCRATCH_INIT in		``.amdhsa_user_sgpr_flat_scratch_init`` 0 GFX6-GFX10 Controls ENABLE_SGPR_FLAT_SCRATCH_INIT in
(except :ref:`amdgpu-amdhsa-kernel-descriptor-v3-table`.		(except :ref:`amdgpu-amdhsa-kernel-descriptor-v3-table`.
GFX940)		GFX940)
``.amdhsa_user_sgpr_private_segment_size`` 0 GFX6-GFX10 Controls ENABLE_SGPR_PRIVATE_SEGMENT_SIZE in		``.amdhsa_user_sgpr_private_segment_size`` 0 GFX6-GFX11 Controls ENABLE_SGPR_PRIVATE_SEGMENT_SIZE in
:ref:`amdgpu-amdhsa-kernel-descriptor-v3-table`.		:ref:`amdgpu-amdhsa-kernel-descriptor-v3-table`.
``.amdhsa_wavefront_size32`` Target GFX10 Controls ENABLE_WAVEFRONT_SIZE32 in		``.amdhsa_wavefront_size32`` Target GFX10-GFX11 Controls ENABLE_WAVEFRONT_SIZE32 in
Feature :ref:`amdgpu-amdhsa-kernel-descriptor-v3-table`.		Feature :ref:`amdgpu-amdhsa-kernel-descriptor-v3-table`.
Specific		Specific
(wavefrontsize64)		(wavefrontsize64)
``.amdhsa_system_sgpr_private_segment_wavefront_offset`` 0 GFX6-GFX10 Controls ENABLE_PRIVATE_SEGMENT in		``.amdhsa_system_sgpr_private_segment_wavefront_offset`` 0 GFX6-GFX10 Controls ENABLE_PRIVATE_SEGMENT in
(except :ref:`amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx10-table`.		(except :ref:`amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx11-table`.
GFX940)		GFX940)
``.amdhsa_enable_private_segment`` 0 GFX940 Controls ENABLE_PRIVATE_SEGMENT in		``.amdhsa_enable_private_segment`` 0 GFX940, Controls ENABLE_PRIVATE_SEGMENT in
:ref:`amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx10-table`.		GFX11 :ref:`amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx11-table`.
``.amdhsa_system_sgpr_workgroup_id_x`` 1 GFX6-GFX10 Controls ENABLE_SGPR_WORKGROUP_ID_X in		``.amdhsa_system_sgpr_workgroup_id_x`` 1 GFX6-GFX11 Controls ENABLE_SGPR_WORKGROUP_ID_X in
:ref:`amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx10-table`.		:ref:`amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx11-table`.
``.amdhsa_system_sgpr_workgroup_id_y`` 0 GFX6-GFX10 Controls ENABLE_SGPR_WORKGROUP_ID_Y in		``.amdhsa_system_sgpr_workgroup_id_y`` 0 GFX6-GFX11 Controls ENABLE_SGPR_WORKGROUP_ID_Y in
:ref:`amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx10-table`.		:ref:`amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx11-table`.
``.amdhsa_system_sgpr_workgroup_id_z`` 0 GFX6-GFX10 Controls ENABLE_SGPR_WORKGROUP_ID_Z in		``.amdhsa_system_sgpr_workgroup_id_z`` 0 GFX6-GFX11 Controls ENABLE_SGPR_WORKGROUP_ID_Z in
:ref:`amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx10-table`.		:ref:`amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx11-table`.
``.amdhsa_system_sgpr_workgroup_info`` 0 GFX6-GFX10 Controls ENABLE_SGPR_WORKGROUP_INFO in		``.amdhsa_system_sgpr_workgroup_info`` 0 GFX6-GFX11 Controls ENABLE_SGPR_WORKGROUP_INFO in
:ref:`amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx10-table`.		:ref:`amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx11-table`.
``.amdhsa_system_vgpr_workitem_id`` 0 GFX6-GFX10 Controls ENABLE_VGPR_WORKITEM_ID in		``.amdhsa_system_vgpr_workitem_id`` 0 GFX6-GFX11 Controls ENABLE_VGPR_WORKITEM_ID in
:ref:`amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx10-table`.		:ref:`amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx11-table`.
Possible values are defined in		Possible values are defined in
:ref:`amdgpu-amdhsa-system-vgpr-work-item-id-enumeration-values-table`.		:ref:`amdgpu-amdhsa-system-vgpr-work-item-id-enumeration-values-table`.
``.amdhsa_next_free_vgpr`` Required GFX6-GFX10 Maximum VGPR number explicitly referenced, plus one.		``.amdhsa_next_free_vgpr`` Required GFX6-GFX11 Maximum VGPR number explicitly referenced, plus one.
Used to calculate GRANULATED_WORKITEM_VGPR_COUNT in		Used to calculate GRANULATED_WORKITEM_VGPR_COUNT in
:ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx10-table`.		:ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx11-table`.
``.amdhsa_next_free_sgpr`` Required GFX6-GFX10 Maximum SGPR number explicitly referenced, plus one.		``.amdhsa_next_free_sgpr`` Required GFX6-GFX11 Maximum SGPR number explicitly referenced, plus one.
Used to calculate GRANULATED_WAVEFRONT_SGPR_COUNT in		Used to calculate GRANULATED_WAVEFRONT_SGPR_COUNT in
:ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx10-table`.		:ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx11-table`.
``.amdhsa_accum_offset`` Required GFX90A, Offset of a first AccVGPR in the unified register file.		``.amdhsa_accum_offset`` Required GFX90A, Offset of a first AccVGPR in the unified register file.
GFX940 Used to calculate ACCUM_OFFSET in		GFX940 Used to calculate ACCUM_OFFSET in
:ref:`amdgpu-amdhsa-compute_pgm_rsrc3-gfx90a-table`.		:ref:`amdgpu-amdhsa-compute_pgm_rsrc3-gfx90a-table`.
``.amdhsa_reserve_vcc`` 1 GFX6-GFX10 Whether the kernel may use the special VCC SGPR.		``.amdhsa_reserve_vcc`` 1 GFX6-GFX11 Whether the kernel may use the special VCC SGPR.
Used to calculate GRANULATED_WAVEFRONT_SGPR_COUNT in		Used to calculate GRANULATED_WAVEFRONT_SGPR_COUNT in
:ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx10-table`.		:ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx11-table`.
``.amdhsa_reserve_flat_scratch`` 1 GFX7-GFX10 Whether the kernel may use flat instructions to access		``.amdhsa_reserve_flat_scratch`` 1 GFX7-GFX10 Whether the kernel may use flat instructions to access
(except scratch memory. Used to calculate		(except scratch memory. Used to calculate
GFX940) GRANULATED_WAVEFRONT_SGPR_COUNT in		GFX940) GRANULATED_WAVEFRONT_SGPR_COUNT in
:ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx10-table`.		:ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx11-table`.
``.amdhsa_reserve_xnack_mask`` Target GFX8-GFX10 Whether the kernel may trigger XNACK replay.		``.amdhsa_reserve_xnack_mask`` Target GFX8-GFX10 Whether the kernel may trigger XNACK replay.
Feature Used to calculate GRANULATED_WAVEFRONT_SGPR_COUNT in		Feature Used to calculate GRANULATED_WAVEFRONT_SGPR_COUNT in
Specific :ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx10-table`.		Specific :ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx11-table`.
(xnack)		(xnack)
``.amdhsa_float_round_mode_32`` 0 GFX6-GFX10 Controls FLOAT_ROUND_MODE_32 in		``.amdhsa_float_round_mode_32`` 0 GFX6-GFX11 Controls FLOAT_ROUND_MODE_32 in
:ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx10-table`.		:ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx11-table`.
Possible values are defined in		Possible values are defined in
:ref:`amdgpu-amdhsa-floating-point-rounding-mode-enumeration-values-table`.		:ref:`amdgpu-amdhsa-floating-point-rounding-mode-enumeration-values-table`.
``.amdhsa_float_round_mode_16_64`` 0 GFX6-GFX10 Controls FLOAT_ROUND_MODE_16_64 in		``.amdhsa_float_round_mode_16_64`` 0 GFX6-GFX11 Controls FLOAT_ROUND_MODE_16_64 in
:ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx10-table`.		:ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx11-table`.
Possible values are defined in		Possible values are defined in
:ref:`amdgpu-amdhsa-floating-point-rounding-mode-enumeration-values-table`.		:ref:`amdgpu-amdhsa-floating-point-rounding-mode-enumeration-values-table`.
``.amdhsa_float_denorm_mode_32`` 0 GFX6-GFX10 Controls FLOAT_DENORM_MODE_32 in		``.amdhsa_float_denorm_mode_32`` 0 GFX6-GFX11 Controls FLOAT_DENORM_MODE_32 in
:ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx10-table`.		:ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx11-table`.
Possible values are defined in		Possible values are defined in
:ref:`amdgpu-amdhsa-floating-point-denorm-mode-enumeration-values-table`.		:ref:`amdgpu-amdhsa-floating-point-denorm-mode-enumeration-values-table`.
``.amdhsa_float_denorm_mode_16_64`` 3 GFX6-GFX10 Controls FLOAT_DENORM_MODE_16_64 in		``.amdhsa_float_denorm_mode_16_64`` 3 GFX6-GFX11 Controls FLOAT_DENORM_MODE_16_64 in
:ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx10-table`.		:ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx11-table`.
Possible values are defined in		Possible values are defined in
:ref:`amdgpu-amdhsa-floating-point-denorm-mode-enumeration-values-table`.		:ref:`amdgpu-amdhsa-floating-point-denorm-mode-enumeration-values-table`.
``.amdhsa_dx10_clamp`` 1 GFX6-GFX10 Controls ENABLE_DX10_CLAMP in		``.amdhsa_dx10_clamp`` 1 GFX6-GFX11 Controls ENABLE_DX10_CLAMP in
:ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx10-table`.		:ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx11-table`.
``.amdhsa_ieee_mode`` 1 GFX6-GFX10 Controls ENABLE_IEEE_MODE in		``.amdhsa_ieee_mode`` 1 GFX6-GFX11 Controls ENABLE_IEEE_MODE in
:ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx10-table`.		:ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx11-table`.
``.amdhsa_fp16_overflow`` 0 GFX9-GFX10 Controls FP16_OVFL in		``.amdhsa_fp16_overflow`` 0 GFX9-GFX11 Controls FP16_OVFL in
:ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx10-table`.		:ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx11-table`.
``.amdhsa_tg_split`` Target GFX90A, Controls TG_SPLIT in		``.amdhsa_tg_split`` Target GFX90A, Controls TG_SPLIT in
Feature GFX940 :ref:`amdgpu-amdhsa-compute_pgm_rsrc3-gfx90a-table`.		Feature GFX940, :ref:`amdgpu-amdhsa-compute_pgm_rsrc3-gfx90a-table`.
Specific		Specific GFX11
(tgsplit)		(tgsplit)
``.amdhsa_workgroup_processor_mode`` Target GFX10 Controls ENABLE_WGP_MODE in		``.amdhsa_workgroup_processor_mode`` Target GFX10-GFX11 Controls ENABLE_WGP_MODE in
Feature :ref:`amdgpu-amdhsa-kernel-descriptor-v3-table`.		Feature :ref:`amdgpu-amdhsa-kernel-descriptor-v3-table`.
Specific		Specific
(cumode)		(cumode)
``.amdhsa_memory_ordered`` 1 GFX10 Controls MEM_ORDERED in		``.amdhsa_memory_ordered`` 1 GFX10-GFX11 Controls MEM_ORDERED in
:ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx10-table`.		:ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx11-table`.
``.amdhsa_forward_progress`` 0 GFX10 Controls FWD_PROGRESS in		``.amdhsa_forward_progress`` 0 GFX10-GFX11 Controls FWD_PROGRESS in
:ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx10-table`.		:ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx11-table`.
``.amdhsa_shared_vgpr_count`` 0 GFX10 Controls SHARED_VGPR_COUNT in		``.amdhsa_exception_fp_ieee_invalid_op`` 0 GFX6-GFX11 Controls ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION in
:ref:`amdgpu-amdhsa-compute_pgm_rsrc3-gfx10-table`.		:ref:`amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx11-table`.
``.amdhsa_exception_fp_ieee_invalid_op`` 0 GFX6-GFX10 Controls ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION in		``.amdhsa_exception_fp_denorm_src`` 0 GFX6-GFX11 Controls ENABLE_EXCEPTION_FP_DENORMAL_SOURCE in
:ref:`amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx10-table`.		:ref:`amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx11-table`.
``.amdhsa_exception_fp_denorm_src`` 0 GFX6-GFX10 Controls ENABLE_EXCEPTION_FP_DENORMAL_SOURCE in		``.amdhsa_exception_fp_ieee_div_zero`` 0 GFX6-GFX11 Controls ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO in
:ref:`amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx10-table`.		:ref:`amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx11-table`.
``.amdhsa_exception_fp_ieee_div_zero`` 0 GFX6-GFX10 Controls ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO in		``.amdhsa_exception_fp_ieee_overflow`` 0 GFX6-GFX11 Controls ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW in
:ref:`amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx10-table`.		:ref:`amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx11-table`.
``.amdhsa_exception_fp_ieee_overflow`` 0 GFX6-GFX10 Controls ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW in		``.amdhsa_exception_fp_ieee_underflow`` 0 GFX6-GFX11 Controls ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW in
:ref:`amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx10-table`.		:ref:`amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx11-table`.
``.amdhsa_exception_fp_ieee_underflow`` 0 GFX6-GFX10 Controls ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW in		``.amdhsa_exception_fp_ieee_inexact`` 0 GFX6-GFX11 Controls ENABLE_EXCEPTION_IEEE_754_FP_INEXACT in
:ref:`amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx10-table`.		:ref:`amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx11-table`.
``.amdhsa_exception_fp_ieee_inexact`` 0 GFX6-GFX10 Controls ENABLE_EXCEPTION_IEEE_754_FP_INEXACT in		``.amdhsa_exception_int_div_zero`` 0 GFX6-GFX11 Controls ENABLE_EXCEPTION_INT_DIVIDE_BY_ZERO in
:ref:`amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx10-table`.		:ref:`amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx11-table`.
``.amdhsa_exception_int_div_zero`` 0 GFX6-GFX10 Controls ENABLE_EXCEPTION_INT_DIVIDE_BY_ZERO in
:ref:`amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx10-table`.
======================================================== =================== ============ ===================		======================================================== =================== ============ ===================

.amdgpu_metadata		.amdgpu_metadata
++++++++++++++++		++++++++++++++++

Optional directive which declares the contents of the ``NT_AMDGPU_METADATA``		Optional directive which declares the contents of the ``NT_AMDGPU_METADATA``
note record (see :ref:`amdgpu-elf-note-records-table-v3-onwards`).		note record (see :ref:`amdgpu-elf-note-records-table-v3-onwards`).

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[AMDGPU] Add GFX11 documentation to AMDGPUUsage
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