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Differential D127371

[RISCV][test] Add widen STEP_VECTOR tests.
ClosedPublic

Authored by Jimerlife on Jun 8 2022, 6:51 PM.

Details

Reviewers
craig.topper
frasercrmck
benshi001
reames
Commits
rG362a02dabe7b: [RISCV][test] Add widen STEP_VECTOR tests.
Summary

Based on D126168. Add widen STEP_VECTOR tests for RISCV.

Diff Detail

Unit TestsFailed

TimeTest
60,110 msx64 debian > Clang.CodeGen/RISCV/rvv-intrinsics::vlsegff_mask.c
60,090 msx64 debian > Clang.CodeGenCXX::dllimport-members.cpp
60,390 msx64 debian > Clang.Driver::arm-cortex-cpus-2.c
60,120 msx64 debian > Clang.Driver::emit-reproducer.c
60,480 msx64 debian > Clang.Driver::fsanitize.c
View Full Test Results (14 Failed)

Event Timeline

Jimerlife created this revision.Jun 8 2022, 6:51 PM
Herald added a project: Restricted Project. · View Herald TranscriptJun 8 2022, 6:51 PM
Herald added subscribers: sunshaoce, VincentWu, luke957 and 28 others. · View Herald Transcript
Jimerlife requested review of this revision.Jun 8 2022, 6:51 PM
Herald added subscribers: llvm-commits, • pcwang-thead, eopXD and 2 others. · View Herald TranscriptJun 8 2022, 6:51 PM
reames accepted this revision.Jun 8 2022, 7:19 PM
This revision is now accepted and ready to land.Jun 8 2022, 7:19 PM
Harbormaster completed remote builds in B168725: Diff 435398.Jun 8 2022, 7:38 PM
This revision was landed with ongoing or failed builds.Jun 9 2022, 12:47 AM
Closed by commit rG362a02dabe7b: [RISCV][test] Add widen STEP_VECTOR tests. (authored by Jimerlife). · Explain Why
This revision was automatically updated to reflect the committed changes.
Jimerlife added a commit: rG362a02dabe7b: [RISCV][test] Add widen STEP_VECTOR tests..

Revision Contents

PathSize
llvm/
test/
CodeGen/
RISCV/
rvv/
12 lines
12 lines
48 lines

Diff 435398

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-stepvector-rv32.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1 ; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1
; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX2 ; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX2
declare <2 x i8> @llvm.experimental.stepvector.v2i8() declare <2 x i8> @llvm.experimental.stepvector.v2i8()
define <2 x i8> @stepvector_v2i8() { define <2 x i8> @stepvector_v2i8() {
; CHECK-LABEL: stepvector_v2i8: ; CHECK-LABEL: stepvector_v2i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
; CHECK-NEXT: vid.v v8 ; CHECK-NEXT: vid.v v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <2 x i8> @llvm.experimental.stepvector.v2i8() %v = call <2 x i8> @llvm.experimental.stepvector.v2i8()
ret <2 x i8> %v ret <2 x i8> %v
} }
declare <3 x i8> @llvm.experimental.stepvector.v3i8()
define <3 x i8> @stepvector_v3i8() {
; CHECK-LABEL: stepvector_v3i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
; CHECK-NEXT: vid.v v8
; CHECK-NEXT: ret
%v = call <3 x i8> @llvm.experimental.stepvector.v3i8()
ret <3 x i8> %v
}
declare <4 x i8> @llvm.experimental.stepvector.v4i8() declare <4 x i8> @llvm.experimental.stepvector.v4i8()
define <4 x i8> @stepvector_v4i8() { define <4 x i8> @stepvector_v4i8() {
; CHECK-LABEL: stepvector_v4i8: ; CHECK-LABEL: stepvector_v4i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
; CHECK-NEXT: vid.v v8 ; CHECK-NEXT: vid.v v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
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llvm/test/CodeGen/RISCV/rvv/fixed-vectors-stepvector-rv64.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1 ; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1
; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX2 ; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX2
declare <2 x i8> @llvm.experimental.stepvector.v2i8() declare <2 x i8> @llvm.experimental.stepvector.v2i8()
define <2 x i8> @stepvector_v2i8() { define <2 x i8> @stepvector_v2i8() {
; CHECK-LABEL: stepvector_v2i8: ; CHECK-LABEL: stepvector_v2i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
; CHECK-NEXT: vid.v v8 ; CHECK-NEXT: vid.v v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <2 x i8> @llvm.experimental.stepvector.v2i8() %v = call <2 x i8> @llvm.experimental.stepvector.v2i8()
ret <2 x i8> %v ret <2 x i8> %v
} }
declare <3 x i8> @llvm.experimental.stepvector.v3i8()
define <3 x i8> @stepvector_v3i8() {
; CHECK-LABEL: stepvector_v3i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
; CHECK-NEXT: vid.v v8
; CHECK-NEXT: ret
%v = call <3 x i8> @llvm.experimental.stepvector.v3i8()
ret <3 x i8> %v
}
declare <4 x i8> @llvm.experimental.stepvector.v4i8() declare <4 x i8> @llvm.experimental.stepvector.v4i8()
define <4 x i8> @stepvector_v4i8() { define <4 x i8> @stepvector_v4i8() {
; CHECK-LABEL: stepvector_v4i8: ; CHECK-LABEL: stepvector_v4i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
; CHECK-NEXT: vid.v v8 ; CHECK-NEXT: vid.v v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
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llvm/test/CodeGen/RISCV/rvv/stepvector.ll

Show All 20 Lines
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, mu
; CHECK-NEXT: vid.v v8 ; CHECK-NEXT: vid.v v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <vscale x 2 x i8> @llvm.experimental.stepvector.nxv2i8() %v = call <vscale x 2 x i8> @llvm.experimental.stepvector.nxv2i8()
ret <vscale x 2 x i8> %v ret <vscale x 2 x i8> %v
} }
declare <vscale x 3 x i8> @llvm.experimental.stepvector.nxv3i8()
define <vscale x 3 x i8> @stepvector_nxv3i8() {
; CHECK-LABEL: stepvector_nxv3i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, mu
; CHECK-NEXT: vid.v v8
; CHECK-NEXT: ret
%v = call <vscale x 3 x i8> @llvm.experimental.stepvector.nxv3i8()
ret <vscale x 3 x i8> %v
}
declare <vscale x 4 x i8> @llvm.experimental.stepvector.nxv4i8() declare <vscale x 4 x i8> @llvm.experimental.stepvector.nxv4i8()
define <vscale x 4 x i8> @stepvector_nxv4i8() { define <vscale x 4 x i8> @stepvector_nxv4i8() {
; CHECK-LABEL: stepvector_nxv4i8: ; CHECK-LABEL: stepvector_nxv4i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, mu
; CHECK-NEXT: vid.v v8 ; CHECK-NEXT: vid.v v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
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; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu
; CHECK-NEXT: vid.v v8 ; CHECK-NEXT: vid.v v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <vscale x 2 x i16> @llvm.experimental.stepvector.nxv2i16() %v = call <vscale x 2 x i16> @llvm.experimental.stepvector.nxv2i16()
ret <vscale x 2 x i16> %v ret <vscale x 2 x i16> %v
} }
declare <vscale x 3 x i16> @llvm.experimental.stepvector.nxv3i16()
define <vscale x 3 x i16> @stepvector_nxv3i16() {
; CHECK-LABEL: stepvector_nxv3i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
; CHECK-NEXT: vid.v v8
; CHECK-NEXT: ret
%v = call <vscale x 3 x i16> @llvm.experimental.stepvector.nxv3i16()
ret <vscale x 3 x i16> %v
}
declare <vscale x 4 x i16> @llvm.experimental.stepvector.nxv4i16() declare <vscale x 4 x i16> @llvm.experimental.stepvector.nxv4i16()
define <vscale x 4 x i16> @stepvector_nxv4i16() { define <vscale x 4 x i16> @stepvector_nxv4i16() {
; CHECK-LABEL: stepvector_nxv4i16: ; CHECK-LABEL: stepvector_nxv4i16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
; CHECK-NEXT: vid.v v8 ; CHECK-NEXT: vid.v v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
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; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
; CHECK-NEXT: vid.v v8 ; CHECK-NEXT: vid.v v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <vscale x 2 x i32> @llvm.experimental.stepvector.nxv2i32() %v = call <vscale x 2 x i32> @llvm.experimental.stepvector.nxv2i32()
ret <vscale x 2 x i32> %v ret <vscale x 2 x i32> %v
} }
declare <vscale x 3 x i32> @llvm.experimental.stepvector.nxv3i32()
define <vscale x 3 x i32> @stepvector_nxv3i32() {
; CHECK-LABEL: stepvector_nxv3i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
; CHECK-NEXT: vid.v v8
; CHECK-NEXT: ret
%v = call <vscale x 3 x i32> @llvm.experimental.stepvector.nxv3i32()
ret <vscale x 3 x i32> %v
}
declare <vscale x 4 x i32> @llvm.experimental.stepvector.nxv4i32() declare <vscale x 4 x i32> @llvm.experimental.stepvector.nxv4i32()
define <vscale x 4 x i32> @stepvector_nxv4i32() { define <vscale x 4 x i32> @stepvector_nxv4i32() {
; CHECK-LABEL: stepvector_nxv4i32: ; CHECK-LABEL: stepvector_nxv4i32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
; CHECK-NEXT: vid.v v8 ; CHECK-NEXT: vid.v v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
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; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu
; CHECK-NEXT: vid.v v8 ; CHECK-NEXT: vid.v v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <vscale x 2 x i64> @llvm.experimental.stepvector.nxv2i64() %v = call <vscale x 2 x i64> @llvm.experimental.stepvector.nxv2i64()
ret <vscale x 2 x i64> %v ret <vscale x 2 x i64> %v
} }
declare <vscale x 3 x i64> @llvm.experimental.stepvector.nxv3i64()
define <vscale x 3 x i64> @stepvector_nxv3i64() {
; CHECK-LABEL: stepvector_nxv3i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu
; CHECK-NEXT: vid.v v8
; CHECK-NEXT: ret
%v = call <vscale x 3 x i64> @llvm.experimental.stepvector.nxv3i64()
ret <vscale x 3 x i64> %v
}
declare <vscale x 4 x i64> @llvm.experimental.stepvector.nxv4i64() declare <vscale x 4 x i64> @llvm.experimental.stepvector.nxv4i64()
define <vscale x 4 x i64> @stepvector_nxv4i64() { define <vscale x 4 x i64> @stepvector_nxv4i64() {
; CHECK-LABEL: stepvector_nxv4i64: ; CHECK-LABEL: stepvector_nxv4i64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu
; CHECK-NEXT: vid.v v8 ; CHECK-NEXT: vid.v v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
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