[LoongArch] Use register R0 (ZERO) for constant 0

[myhsu]

LGTM

llvm/lib/Target/LoongArch/LoongArchISelDAGToDAG.cpp

35

nit: is this variable used in any other place? could we either put it in the inner local scope or spell it out in-place?

[SixWeining]

Address @myhsu's comment. Thanks.

[xen0n]

Codegen improvements are exactly as intended. Thanks!

[MaskRay]

llvm/test/CodeGen/LoongArch/imm.ll

167

Usually simple tests are placed before complex ones.

[SixWeining]

llvm/lib/Target/LoongArch/LoongArchISelDAGToDAG.cpp

35

Thanks. Currently this variable is only used once but will be used in ohter place later. Let me spell it out in-place.

llvm/test/CodeGen/LoongArch/imm.ll

167

Yes, I agree. Let me make it be the first one of this file. Thanks.

[SixWeining]

1. Address @MaskRay's comment by moving imm0 testing to the top of the test file.
2. Remove the patch number in the title.

[MaskRay]

Depends on D127204

The dependency is inverted.

I think this should be placed before other patches.

[SixWeining]

In D127205#3575143, @MaskRay wrote:

Depends on D127204

The dependency is inverted.

I think this should be placed before other patches.

The reason why I place it after other patches is that we can obviously see the improvements from the test (introduced by early patches) updates. If this is not good, I can revert the dependency. There is no problem. Thanks.

[MaskRay]

In D127205#3575164, @SixWeining wrote:

In D127205#3575143, @MaskRay wrote:

Depends on D127204

The dependency is inverted.

I think this should be placed before other patches.

The reason why I place it after other patches is that we can obviously see the improvements from the test (introduced by early patches) updates. If this is not good, I can revert the dependency. There is no problem. Thanks.

If you think it's worthwhile, you can mention this in D127204's summary. No need to add unnecessary intermediate steps to the tests to show the effect.

[SixWeining]

In D127205#3575174, @MaskRay wrote:

In D127205#3575164, @SixWeining wrote:

In D127205#3575143, @MaskRay wrote:

Depends on D127204

The dependency is inverted.

I think this should be placed before other patches.

The reason why I place it after other patches is that we can obviously see the improvements from the test (introduced by early patches) updates. If this is not good, I can revert the dependency. There is no problem. Thanks.

If you think it's worthwhile, you can mention this in D127204's summary. No need to add unnecessary intermediate steps to the tests to show the effect.

That sounds good. Let me mention this in D127204's summary. Thanks.

[SixWeining]

rebase

[MaskRay]

There are still many changes to sext-zext-trunc.ll

[SixWeining]

In D127205#3576929, @MaskRay wrote:

There are still many changes to sext-zext-trunc.ll

Sorry. Maybe I misunderstood your last comment.

To reduce these changes to sext-zext-trunc.ll I should have to revert the dependence, right?

[MaskRay]

In D127205#3576996, @SixWeining wrote:

In D127205#3576929, @MaskRay wrote:

There are still many changes to sext-zext-trunc.ll

Sorry. Maybe I misunderstood your last comment.

To reduce these changes to sext-zext-trunc.ll I should have to revert the dependence, right?

Right. Reverse the dependency.

[SixWeining]

reverse the dependency

[MaskRay]

Thanks!

llvm/lib/Target/LoongArch/LoongArchISelDAGToDAG.cpp

if (Node->isMachineOpcode()) {
     return;
   }
 
   // Instruction Selection not handled by the auto-generated tablegen selection
   // should be handled here.
   unsigned Opcode = Node->getOpcode();
   MVT GRLenVT = Subtarget->getGRLenVT();
   SDLoc DL(Node);
 
   switch (Opcode) {
   default:
     break;
   case ISD::Constant: {
     int64_t Imm = cast<ConstantSDNode>(Node)->getSExtValue();
+    if (Imm == 0 && Node->getSimpleValueType(0) == GRLenVT) {
+      SDValue New = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL,
+                                           LoongArch::R0, GRLenVT);
+      ReplaceNode(Node, New.getNode());
+      return;
+    }
     SDNode *Result = nullptr;
     SDValue SrcReg = CurDAG->getRegister(LoongArch::R0, GRLenVT);
-
     // The instructions in the sequence are handled here.
     for (LoongArchMatInt::Inst &Inst : LoongArchMatInt::generateInstSeq(Imm)) {
       SDValue SDImm = CurDAG->getTargetConstant(Inst.Imm, DL, GRLenVT);
       if (Inst.Opc == LoongArch::LU12I_W)
         Result = CurDAG->getMachineNode(LoongArch::LU12I_W, DL, GRLenVT, SDImm);
       else
         Result = CurDAG->getMachineNode(Inst.Opc, DL, GRLenVT, SrcReg, SDImm);
       SrcReg = SDValue(Result, 0);

llvm/test/CodeGen/LoongArch/imm.ll

 ; RUN: llc --mtriple=loongarch64 < %s | FileCheck %s
 
+define i64 @imm0() {
+; CHECK-LABEL: imm0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    move $a0, $zero
+; CHECK-NEXT:    jirl $zero, $ra, 0
+  ret i64 0
+}
+
 define i64 @imm7ff0000000000000() {
 ; CHECK-LABEL: imm7ff0000000000000:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lu52i.d $a0, $zero, 2047
 ; CHECK-NEXT:    jirl $zero, $ra, 0
   ret i64 9218868437227405312
 }
 

 ; CHECK-LABEL: imm0008000080000800:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lu12i.w $a0, -524288
 ; CHECK-NEXT:    ori $a0, $a0, 2048
 ; CHECK-NEXT:    lu32i.d $a0, -524288
 ; CHECK-NEXT:    lu52i.d $a0, $a0, 0
 ; CHECK-NEXT:    jirl $zero, $ra, 0
   ret i64 2251801961170944
 }

llvm/test/CodeGen/LoongArch/ir-instruction/and.ll

entry:
   ret i64 %r
 }
 
 ;; FIXME: remove redundant immediate style tests
 
 define i1 @and_i1_4(i1 %b) {
 ; LA32-LABEL: and_i1_4:
 ; LA32:       # %bb.0: # %entry
-; LA32-NEXT:    ori $a0, $zero, 0
+; LA32-NEXT:    move $a0, $zero
 ; LA32-NEXT:    jirl $zero, $ra, 0
 ;
 ; LA64-LABEL: and_i1_4:
 ; LA64:       # %bb.0: # %entry
-; LA64-NEXT:    ori $a0, $zero, 0
+; LA64-NEXT:    move $a0, $zero
 ; LA64-NEXT:    jirl $zero, $ra, 0
 entry:
   %r = and i1 4, %b
   ret i1 %r
 }
 
 define i8 @and_i8_4(i8 %b) {
 ; LA32-LABEL: and_i8_4:
entry:
   %r = and i32 4, %b
   ret i32 %r
 }
 
 define i64 @and_i64_4(i64 %b) {
 ; LA32-LABEL: and_i64_4:
 ; LA32:       # %bb.0: # %entry
 ; LA32-NEXT:    andi $a0, $a0, 4
-; LA32-NEXT:    ori $a1, $zero, 0
+; LA32-NEXT:    move $a1, $zero
 ; LA32-NEXT:    jirl $zero, $ra, 0
 ;
 ; LA64-LABEL: and_i64_4:
 ; LA64:       # %bb.0: # %entry
 ; LA64-NEXT:    andi $a0, $a0, 4
 ; LA64-NEXT:    jirl $zero, $ra, 0
 entry:
   %r = and i64 4, %b
entry:
   %r = and i32 31, %b
   ret i32 %r
 }
 
 define i64 @and_i64_31(i64 %b) {
 ; LA32-LABEL: and_i64_31:
 ; LA32:       # %bb.0: # %entry
 ; LA32-NEXT:    andi $a0, $a0, 31
-; LA32-NEXT:    ori $a1, $zero, 0
+; LA32-NEXT:    move $a1, $zero
 ; LA32-NEXT:    jirl $zero, $ra, 0
 ;
 ; LA64-LABEL: and_i64_31:
 ; LA64:       # %bb.0: # %entry
 ; LA64-NEXT:    andi $a0, $a0, 31
 ; LA64-NEXT:    jirl $zero, $ra, 0
 entry:
   %r = and i64 31, %b
entry:
   %r = and i32 65, %b
   ret i32 %r
 }
 
 define i64 @and_i64_65(i64 %b) {
 ; LA32-LABEL: and_i64_65:
 ; LA32:       # %bb.0: # %entry
 ; LA32-NEXT:    andi $a0, $a0, 65
-; LA32-NEXT:    ori $a1, $zero, 0
+; LA32-NEXT:    move $a1, $zero
 ; LA32-NEXT:    jirl $zero, $ra, 0
 ;
 ; LA64-LABEL: and_i64_65:
 ; LA64:       # %bb.0: # %entry
 ; LA64-NEXT:    andi $a0, $a0, 65
 ; LA64-NEXT:    jirl $zero, $ra, 0
 entry:
   %r = and i64 65, %b
entry:
   %r = and i32 255, %b
   ret i32 %r
 }
 
 define i64 @and_i64_255(i64 %b) {
 ; LA32-LABEL: and_i64_255:
 ; LA32:       # %bb.0: # %entry
 ; LA32-NEXT:    andi $a0, $a0, 255
-; LA32-NEXT:    ori $a1, $zero, 0
+; LA32-NEXT:    move $a1, $zero
 ; LA32-NEXT:    jirl $zero, $ra, 0
 ;
 ; LA64-LABEL: and_i64_255:
 ; LA64:       # %bb.0: # %entry
 ; LA64-NEXT:    andi $a0, $a0, 255
 ; LA64-NEXT:    jirl $zero, $ra, 0
 entry:
   %r = and i64 255, %b
   ret i64 %r
 }
 
 define i1 @and_i1_256(i1 %b) {
 ; LA32-LABEL: and_i1_256:
 ; LA32:       # %bb.0: # %entry
-; LA32-NEXT:    ori $a0, $zero, 0
+; LA32-NEXT:    move $a0, $zero
 ; LA32-NEXT:    jirl $zero, $ra, 0
 ;
 ; LA64-LABEL: and_i1_256:
 ; LA64:       # %bb.0: # %entry
-; LA64-NEXT:    ori $a0, $zero, 0
+; LA64-NEXT:    move $a0, $zero
 ; LA64-NEXT:    jirl $zero, $ra, 0
 entry:
   %r = and i1 256, %b
   ret i1 %r
 }
 
 define i8 @and_i8_256(i8 %b) {
 ; LA32-LABEL: and_i8_256:
 ; LA32:       # %bb.0: # %entry
-; LA32-NEXT:    ori $a0, $zero, 0
+; LA32-NEXT:    move $a0, $zero
 ; LA32-NEXT:    jirl $zero, $ra, 0
 ;
 ; LA64-LABEL: and_i8_256:
 ; LA64:       # %bb.0: # %entry
-; LA64-NEXT:    ori $a0, $zero, 0
+; LA64-NEXT:    move $a0, $zero
 ; LA64-NEXT:    jirl $zero, $ra, 0
 entry:
   %r = and i8 256, %b
   ret i8 %r
 }
 
 define i16 @and_i16_256(i16 %b) {
 ; LA32-LABEL: and_i16_256:
entry:
   %r = and i32 256, %b
   ret i32 %r
 }
 
 define i64 @and_i64_256(i64 %b) {
 ; LA32-LABEL: and_i64_256:
 ; LA32:       # %bb.0: # %entry
 ; LA32-NEXT:    andi $a0, $a0, 256
-; LA32-NEXT:    ori $a1, $zero, 0
+; LA32-NEXT:    move $a1, $zero
 ; LA32-NEXT:    jirl $zero, $ra, 0
 ;
 ; LA64-LABEL: and_i64_256:
 ; LA64:       # %bb.0: # %entry
 ; LA64-NEXT:    andi $a0, $a0, 256
 ; LA64-NEXT:    jirl $zero, $ra, 0
 entry:
   %r = and i64 256, %b
   ret i64 %r
 }
 
 define i1 @and_i1_2048(i1 %b) {
 ; LA32-LABEL: and_i1_2048:
 ; LA32:       # %bb.0: # %entry
-; LA32-NEXT:    ori $a0, $zero, 0
+; LA32-NEXT:    move $a0, $zero
 ; LA32-NEXT:    jirl $zero, $ra, 0
 ;
 ; LA64-LABEL: and_i1_2048:
 ; LA64:       # %bb.0: # %entry
-; LA64-NEXT:    ori $a0, $zero, 0
+; LA64-NEXT:    move $a0, $zero
 ; LA64-NEXT:    jirl $zero, $ra, 0
 entry:
   %r = and i1 2048, %b
   ret i1 %r
 }
 
 define i8 @and_i8_2048(i8 %b) {
 ; LA32-LABEL: and_i8_2048:
 ; LA32:       # %bb.0: # %entry
-; LA32-NEXT:    ori $a0, $zero, 0
+; LA32-NEXT:    move $a0, $zero
 ; LA32-NEXT:    jirl $zero, $ra, 0
 ;
 ; LA64-LABEL: and_i8_2048:
 ; LA64:       # %bb.0: # %entry
-; LA64-NEXT:    ori $a0, $zero, 0
+; LA64-NEXT:    move $a0, $zero
 ; LA64-NEXT:    jirl $zero, $ra, 0
 entry:
   %r = and i8 2048, %b
   ret i8 %r
 }
 
 define i16 @and_i16_2048(i16 %b) {
 ; LA32-LABEL: and_i16_2048:
entry:
   %r = and i32 2048, %b
   ret i32 %r
 }
 
 define i64 @and_i64_2048(i64 %b) {
 ; LA32-LABEL: and_i64_2048:
 ; LA32:       # %bb.0: # %entry
 ; LA32-NEXT:    andi $a0, $a0, 2048
-; LA32-NEXT:    ori $a1, $zero, 0
+; LA32-NEXT:    move $a1, $zero
 ; LA32-NEXT:    jirl $zero, $ra, 0
 ;
 ; LA64-LABEL: and_i64_2048:
 ; LA64:       # %bb.0: # %entry
 ; LA64-NEXT:    andi $a0, $a0, 2048
 ; LA64-NEXT:    jirl $zero, $ra, 0
 entry:
   %r = and i64 2048, %b
   ret i64 %r
 }
 
 define i1 @and_i1_4096(i1 %b) {
 ; LA32-LABEL: and_i1_4096:
 ; LA32:       # %bb.0: # %entry
-; LA32-NEXT:    ori $a0, $zero, 0
+; LA32-NEXT:    move $a0, $zero
 ; LA32-NEXT:    jirl $zero, $ra, 0
 ;
 ; LA64-LABEL: and_i1_4096:
 ; LA64:       # %bb.0: # %entry
-; LA64-NEXT:    ori $a0, $zero, 0
+; LA64-NEXT:    move $a0, $zero
 ; LA64-NEXT:    jirl $zero, $ra, 0
 entry:
   %r = and i1 4096, %b
   ret i1 %r
 }
 
 define i8 @and_i8_4096(i8 %b) {
 ; LA32-LABEL: and_i8_4096:
 ; LA32:       # %bb.0: # %entry
-; LA32-NEXT:    ori $a0, $zero, 0
+; LA32-NEXT:    move $a0, $zero
 ; LA32-NEXT:    jirl $zero, $ra, 0
 ;
 ; LA64-LABEL: and_i8_4096:
 ; LA64:       # %bb.0: # %entry
-; LA64-NEXT:    ori $a0, $zero, 0
+; LA64-NEXT:    move $a0, $zero
 ; LA64-NEXT:    jirl $zero, $ra, 0
 entry:
   %r = and i8 4096, %b
   ret i8 %r
 }
 
 define i16 @and_i16_4096(i16 %b) {
 ; LA32-LABEL: and_i16_4096:
entry:
   ret i32 %r
 }
 
 define i64 @and_i64_4096(i64 %b) {
 ; LA32-LABEL: and_i64_4096:
 ; LA32:       # %bb.0: # %entry
 ; LA32-NEXT:    lu12i.w $a1, 1
 ; LA32-NEXT:    and $a0, $a0, $a1
-; LA32-NEXT:    ori $a1, $zero, 0
+; LA32-NEXT:    move $a1, $zero
 ; LA32-NEXT:    jirl $zero, $ra, 0
 ;
 ; LA64-LABEL: and_i64_4096:
 ; LA64:       # %bb.0: # %entry
 ; LA64-NEXT:    lu12i.w $a1, 1
 ; LA64-NEXT:    and $a0, $a0, $a1
 ; LA64-NEXT:    jirl $zero, $ra, 0
 entry:
   %r = and i64 4096, %b
   ret i64 %r
 }

llvm/test/CodeGen/LoongArch/ir-instruction/fcmp-dbl.ll

 ; RUN: llc --mtriple=loongarch32 --mattr=+d < %s | FileCheck %s --check-prefix=LA32
 ; RUN: llc --mtriple=loongarch64 --mattr=+d < %s | FileCheck %s --check-prefix=LA64
 
 ;; Test the 'fcmp' LLVM IR: https://llvm.org/docs/LangRef.html#fcmp-instruction
 ;; over double values.
 
 define i1 @fcmp_false(double %a, double %b) {
 ; LA32-LABEL: fcmp_false:
 ; LA32:       # %bb.0:
-; LA32-NEXT:    ori $a0, $zero, 0
+; LA32-NEXT:    move $a0, $zero
 ; LA32-NEXT:    jirl $zero, $ra, 0
 ;
 ; LA64-LABEL: fcmp_false:
 ; LA64:       # %bb.0:
-; LA64-NEXT:    ori $a0, $zero, 0
+; LA64-NEXT:    move $a0, $zero
 ; LA64-NEXT:    jirl $zero, $ra, 0
   %cmp = fcmp false double %a, %b
   ret i1 %cmp
 }
 
 define i1 @fcmp_oeq(double %a, double %b) {
 ; LA32-LABEL: fcmp_oeq:
 ; LA32:       # %bb.0:

llvm/test/CodeGen/LoongArch/ir-instruction/fcmp-flt.ll

 ; RUN: llc --mtriple=loongarch32 --mattr=+f,-d < %s | FileCheck %s --check-prefix=LA32
 ; RUN: llc --mtriple=loongarch64 --mattr=+f,-d < %s | FileCheck %s --check-prefix=LA64
 
 ;; Test the 'fcmp' LLVM IR: https://llvm.org/docs/LangRef.html#fcmp-instruction
 ;; over float values.
 
 define i1 @fcmp_false(float %a, float %b) {
 ; LA32-LABEL: fcmp_false:
 ; LA32:       # %bb.0:
-; LA32-NEXT:    ori $a0, $zero, 0
+; LA32-NEXT:    move $a0, $zero
 ; LA32-NEXT:    jirl $zero, $ra, 0
 ;
 ; LA64-LABEL: fcmp_false:
 ; LA64:       # %bb.0:
-; LA64-NEXT:    ori $a0, $zero, 0
+; LA64-NEXT:    move $a0, $zero
 ; LA64-NEXT:    jirl $zero, $ra, 0
   %cmp = fcmp false float %a, %b
   ret i1 %cmp
 }
 
 define i1 @fcmp_oeq(float %a, float %b) {
 ; LA32-LABEL: fcmp_oeq:
 ; LA32:       # %bb.0:

llvm/test/CodeGen/LoongArch/ir-instruction/sext-zext-trunc.ll

 ; RUN: llc --mtriple=loongarch32 < %s | FileCheck %s --check-prefix=LA32
 ; RUN: llc --mtriple=loongarch64 < %s | FileCheck %s --check-prefix=LA64
 
 ;; Test sext/zext/trunc
 
 define i8 @sext_i1_to_i8(i1 %a) {
 ; LA32-LABEL: sext_i1_to_i8:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    andi $a0, $a0, 1
-; LA32-NEXT:    ori $a1, $zero, 0
-; LA32-NEXT:    sub.w $a0, $a1, $a0
+; LA32-NEXT:    sub.w $a0, $zero, $a0
 ; LA32-NEXT:    jirl $zero, $ra, 0
 ;
 ; LA64-LABEL: sext_i1_to_i8:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    andi $a0, $a0, 1
-; LA64-NEXT:    ori $a1, $zero, 0
-; LA64-NEXT:    sub.d $a0, $a1, $a0
+; LA64-NEXT:    sub.d $a0, $zero, $a0
 ; LA64-NEXT:    jirl $zero, $ra, 0
   %1 = sext i1 %a to i8
   ret i8 %1
 }
 
 define i16 @sext_i1_to_i16(i1 %a) {
 ; LA32-LABEL: sext_i1_to_i16:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    andi $a0, $a0, 1
-; LA32-NEXT:    ori $a1, $zero, 0
-; LA32-NEXT:    sub.w $a0, $a1, $a0
+; LA32-NEXT:    sub.w $a0, $zero, $a0
 ; LA32-NEXT:    jirl $zero, $ra, 0
 ;
 ; LA64-LABEL: sext_i1_to_i16:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    andi $a0, $a0, 1
-; LA64-NEXT:    ori $a1, $zero, 0
-; LA64-NEXT:    sub.d $a0, $a1, $a0
+; LA64-NEXT:    sub.d $a0, $zero, $a0
 ; LA64-NEXT:    jirl $zero, $ra, 0
   %1 = sext i1 %a to i16
   ret i16 %1
 }
 
 define i32 @sext_i1_to_i32(i1 %a) {
 ; LA32-LABEL: sext_i1_to_i32:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    andi $a0, $a0, 1
-; LA32-NEXT:    ori $a1, $zero, 0
-; LA32-NEXT:    sub.w $a0, $a1, $a0
+; LA32-NEXT:    sub.w $a0, $zero, $a0
 ; LA32-NEXT:    jirl $zero, $ra, 0
 ;
 ; LA64-LABEL: sext_i1_to_i32:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    andi $a0, $a0, 1
-; LA64-NEXT:    ori $a1, $zero, 0
-; LA64-NEXT:    sub.d $a0, $a1, $a0
+; LA64-NEXT:    sub.d $a0, $zero, $a0
 ; LA64-NEXT:    jirl $zero, $ra, 0
   %1 = sext i1 %a to i32
   ret i32 %1
 }
 
 define i64 @sext_i1_to_i64(i1 %a) {
 ; LA32-LABEL: sext_i1_to_i64:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    andi $a0, $a0, 1
-; LA32-NEXT:    ori $a1, $zero, 0
-; LA32-NEXT:    sub.w $a0, $a1, $a0
+; LA32-NEXT:    sub.w $a0, $zero, $a0
 ; LA32-NEXT:    move $a1, $a0
 ; LA32-NEXT:    jirl $zero, $ra, 0
 ;
 ; LA64-LABEL: sext_i1_to_i64:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    andi $a0, $a0, 1
-; LA64-NEXT:    ori $a1, $zero, 0
-; LA64-NEXT:    sub.d $a0, $a1, $a0
+; LA64-NEXT:    sub.d $a0, $zero, $a0
 ; LA64-NEXT:    jirl $zero, $ra, 0
   %1 = sext i1 %a to i64
   ret i64 %1
 }
 
 define i16 @sext_i8_to_i16(i8 %a) {
 ; LA32-LABEL: sext_i8_to_i16:
 ; LA32:       # %bb.0:
; LA64-NEXT:    jirl $zero, $ra, 0
   %1 = zext i1 %a to i32
   ret i32 %1
 }
 
 define i64 @zext_i1_to_i64(i1 %a) {
 ; LA32-LABEL: zext_i1_to_i64:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    andi $a0, $a0, 1
-; LA32-NEXT:    ori $a1, $zero, 0
+; LA32-NEXT:    move $a1, $zero
 ; LA32-NEXT:    jirl $zero, $ra, 0
 ;
 ; LA64-LABEL: zext_i1_to_i64:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    andi $a0, $a0, 1
 ; LA64-NEXT:    jirl $zero, $ra, 0
   %1 = zext i1 %a to i64
   ret i64 %1
; LA64-NEXT:    jirl $zero, $ra, 0
   %1 = zext i8 %a to i32
   ret i32 %1
 }
 
 define i64 @zext_i8_to_i64(i8 %a) {
 ; LA32-LABEL: zext_i8_to_i64:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    andi $a0, $a0, 255
-; LA32-NEXT:    ori $a1, $zero, 0
+; LA32-NEXT:    move $a1, $zero
 ; LA32-NEXT:    jirl $zero, $ra, 0
 ;
 ; LA64-LABEL: zext_i8_to_i64:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    andi $a0, $a0, 255
 ; LA64-NEXT:    jirl $zero, $ra, 0
   %1 = zext i8 %a to i64
   ret i64 %1

 }
 
 define i64 @zext_i16_to_i64(i16 %a) {
 ; LA32-LABEL: zext_i16_to_i64:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    lu12i.w $a1, 15
 ; LA32-NEXT:    ori $a1, $a1, 4095
 ; LA32-NEXT:    and $a0, $a0, $a1
-; LA32-NEXT:    ori $a1, $zero, 0
+; LA32-NEXT:    move $a1, $zero
 ; LA32-NEXT:    jirl $zero, $ra, 0
 ;
 ; LA64-LABEL: zext_i16_to_i64:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    lu12i.w $a1, 15
 ; LA64-NEXT:    ori $a1, $a1, 4095
 ; LA64-NEXT:    and $a0, $a0, $a1
 ; LA64-NEXT:    jirl $zero, $ra, 0
   %1 = zext i16 %a to i64
   ret i64 %1
 }
 
 define i64 @zext_i32_to_i64(i32 %a) {
 ; LA32-LABEL: zext_i32_to_i64:
 ; LA32:       # %bb.0:
-; LA32-NEXT:    ori $a1, $zero, 0
+; LA32-NEXT:    move $a1, $zero
 ; LA32-NEXT:    jirl $zero, $ra, 0
 ;
 ; LA64-LABEL: zext_i32_to_i64:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    addi.w $a1, $zero, -1
 ; LA64-NEXT:    lu32i.d $a1, 0
 ; LA64-NEXT:    and $a0, $a0, $a1
 ; LA64-NEXT:    jirl $zero, $ra, 0