[LoongArch] Add codegen support for the binary operations

[SixWeining]

Summary

These binary operations include sub/fadd/fsub/fmul/fdiv. Others ops
like mul/udiv/sdiv/urem/srem would be added later since they depend on
shift and truncate that have not been supported.

Note add has been added in a previous patch.

Reference:
https://llvm.org/docs/LangRef.html#binary-operations

Depends on D127205

[rengolin]

LGTM, thanks!

Perhaps wait a few days to make sure other people have time to comment, too.

Also, now that the target is in-tree, you don't need to number the series anymore, the patches can be independent and be reviewed as they come.

[SixWeining]

In D127199#3563269, @rengolin wrote:

LGTM, thanks!

Perhaps wait a few days to make sure other people have time to comment, too.

Also, now that the target is in-tree, you don't need to number the series anymore, the patches can be independent and be reviewed as they come.

Thanks. Let me remove the number before submit.

[xry111]

Does anyone have any idea about "why the CI is failing"? It seems happening for this batch of LoongArch patches and also one MIPS patch I've reviewed today. I guess something is wrong in the CI system or LLVM codebase.

[rengolin]

In D127199#3564217, @xry111 wrote:

Does anyone have any idea about "why the CI is failing"? It seems happening for this batch of LoongArch patches and also one MIPS patch I've reviewed today. I guess something is wrong in the CI system or LLVM codebase.

This pre-commit CI isn't trust-worthy. The LLVM codebase relies on live buildbots that test main and warrant reverts if they break, instead of duplicating all tests as pre-commit (too many!) and then get something wrong after merge.

What I do, and I recommend to everyone merging patches to main is to run a build + check-all with the tools you need (llvm only, clang, etc).

If main is failing without your patch and your patch doesn't add any more failures (nor change the existing failures) it should be ok to merge.

[xen0n]

Seems good to me, thanks!

llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp

90–95

I would probably use a switch here but this is only a minor nit and bikeshedding. No problem in the current form.

[SixWeining]

Remove the patch number in the title.

[MaskRay]

These binary operations include add/sub/fadd/fsub/fmul/fdiv.

add has been added by a previous patch.

[MaskRay]

llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp

75

const MCPhysReg ArgFPR32s[] = {...} has internal linkage, so static can be avoided.

[SixWeining]

Address @MaskRay's comments:

1. Revise the title.
2. Remove necessary static keywords.

[SixWeining]

Fix clang-format issue.

[SixWeining]

Address @MaskRay's comment in D127200: use ;; to emphasize non-RUN non-CHECK lines.

[SixWeining]

adjust the dependency

[xen0n]

still LGTM after rebase

llvm/lib/Target/LoongArch/LoongArchFloat32InstrInfo.td

 
 // Bound Check Memory Access Instructions
 def FLDGT_S : FP_LOAD_3R<0b00111000011101000, "fldgt.s", FPR32>;
 def FLDLE_S : FP_LOAD_3R<0b00111000011101010, "fldle.s", FPR32>;
 def FSTGT_S : FP_STORE_3R<0b00111000011101100, "fstgt.s", FPR32>;
 def FSTLE_S : FP_STORE_3R<0b00111000011101110, "fstle.s", FPR32>;
 
 } // Predicates = [HasBasicF]
+
+//===----------------------------------------------------------------------===//
+// Pseudo-instructions and codegen patterns
+//===----------------------------------------------------------------------===//
+
+/// Generic pattern classes
+
+class PatFprFpr<SDPatternOperator OpNode, LAInst Inst, RegisterClass RegTy>
+    : Pat<(OpNode RegTy:$fj, RegTy:$fk), (Inst $fj, $fk)>;
+
+let Predicates = [HasBasicF] in {
+
+/// Float arithmetic operations
+
+def : PatFprFpr<fadd, FADD_S, FPR32>;
+def : PatFprFpr<fsub, FSUB_S, FPR32>;
+def : PatFprFpr<fmul, FMUL_S, FPR32>;
+def : PatFprFpr<fdiv, FDIV_S, FPR32>;
+
+} // Predicates = [HasBasicF]

llvm/lib/Target/LoongArch/LoongArchFloat64InstrInfo.td

 } // Predicates = [HasBasicD]
 
 // Instructions only available on LA64
 let Predicates = [HasBasicD, IsLA64] in {
 def MOVGR2FR_D  : FP_MOV<0b0000000100010100101010, "movgr2fr.d", FPR64, GPR>;
 def MOVFR2GR_D  : FP_MOV<0b0000000100010100101110, "movfr2gr.d", GPR, FPR64>;
 } // Predicates = [HasBasicD, IsLA64]
 
+//===----------------------------------------------------------------------===//
+// Pseudo-instructions and codegen patterns
+//===----------------------------------------------------------------------===//
+
+let Predicates = [HasBasicD] in {
+
+/// Float arithmetic operations
+
+def : PatFprFpr<fadd, FADD_D, FPR64>;
+def : PatFprFpr<fsub, FSUB_D, FPR64>;
+def : PatFprFpr<fmul, FMUL_D, FPR64>;
+def : PatFprFpr<fdiv, FDIV_D, FPR64>;
+
+} // Predicates = [HasBasicD]

llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp

 
 LoongArchTargetLowering::LoongArchTargetLowering(const TargetMachine &TM,
                                                  const LoongArchSubtarget &STI)
     : TargetLowering(TM), Subtarget(STI) {
 
   MVT GRLenVT = Subtarget.getGRLenVT();
   // Set up the register classes.
   addRegisterClass(GRLenVT, &LoongArch::GPRRegClass);
+  if (Subtarget.hasBasicF())
+    addRegisterClass(MVT::f32, &LoongArch::FPR32RegClass);
+  if (Subtarget.hasBasicD())
+    addRegisterClass(MVT::f64, &LoongArch::FPR64RegClass);
 
   // TODO: add necessary setOperationAction calls later.
 
   // Compute derived properties from the register classes.
   computeRegisterProperties(STI.getRegisterInfo());
 
   setStackPointerRegisterToSaveRestore(LoongArch::R3);
 
+  setBooleanContents(ZeroOrOneBooleanContent);
+
   // Function alignments.
   const Align FunctionAlignment(4);
   setMinFunctionAlignment(FunctionAlignment);
 }
 
 const char *LoongArchTargetLowering::getTargetNodeName(unsigned Opcode) const {
   switch ((LoongArchISD::NodeType)Opcode) {
   case LoongArchISD::FIRST_NUMBER:

 #undef NODE_NAME_CASE
   return nullptr;
 }
 
 //===----------------------------------------------------------------------===//
 //                     Calling Convention Implementation
 //===----------------------------------------------------------------------===//
 // FIXME: Now, we only support CallingConv::C with fixed arguments which are
-// passed with integer registers.
+// passed with integer or floating-point registers.
 const MCPhysReg ArgGPRs[] = {LoongArch::R4,  LoongArch::R5, LoongArch::R6,
                              LoongArch::R7,  LoongArch::R8, LoongArch::R9,
                              LoongArch::R10, LoongArch::R11};
+const MCPhysReg ArgFPR32s[] = {LoongArch::F0, LoongArch::F1, LoongArch::F2,
+                               LoongArch::F3, LoongArch::F4, LoongArch::F5,
+                               LoongArch::F6, LoongArch::F7};
+const MCPhysReg ArgFPR64s[] = {
+    LoongArch::F0_64, LoongArch::F1_64, LoongArch::F2_64, LoongArch::F3_64,
+    LoongArch::F4_64, LoongArch::F5_64, LoongArch::F6_64, LoongArch::F7_64};
 
 // Implements the LoongArch calling convention. Returns true upon failure.
 static bool CC_LoongArch(unsigned ValNo, MVT ValVT,
                          CCValAssign::LocInfo LocInfo, CCState &State) {
   // Allocate to a register if possible.
-  Register Reg = State.AllocateReg(ArgGPRs);
+  Register Reg;
+
+  if (ValVT == MVT::f32)
+    Reg = State.AllocateReg(ArgFPR32s);
+  else if (ValVT == MVT::f64)
+    Reg = State.AllocateReg(ArgFPR64s);
+  else
+    Reg = State.AllocateReg(ArgGPRs);
   if (Reg) {
     State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, ValVT, LocInfo));
     return false;
   }
 
   // TODO: Handle arguments passed without register.
   return true;
 }

llvm/lib/Target/LoongArch/LoongArchInstrInfo.td

 
 class PatGprImm<SDPatternOperator OpNode, LAInst Inst, Operand ImmOpnd>
     : Pat<(OpNode GPR:$rj, ImmOpnd:$imm),
           (Inst GPR:$rj, ImmOpnd:$imm)>;
 class PatGprImm_32<SDPatternOperator OpNode, LAInst Inst, Operand ImmOpnd>
     : Pat<(sext_inreg (OpNode GPR:$rj, ImmOpnd:$imm), i32),
           (Inst GPR:$rj, ImmOpnd:$imm)>;
 
-def : PatGprGpr<and, AND>;
-def : PatGprGpr<or, OR>;
-def : PatGprGpr<xor, XOR>;
-
-/// Branches and jumps
-
-let isBarrier = 1, isReturn = 1, isTerminator = 1 in
-def PseudoRET : Pseudo<(outs), (ins), [(loongarch_ret)]>,
-                PseudoInstExpansion<(JIRL R0, R1, 0)>;
-
-/// LA32 patterns
+/// Simple arithmetic operations
 
 let Predicates = [IsLA32] in {
 def : PatGprGpr<add, ADD_W>;
 def : PatGprImm<add, ADDI_W, simm12>;
+def : PatGprGpr<sub, SUB_W>;
 } // Predicates = [IsLA32]
 
-/// LA64 patterns
-
 let Predicates = [IsLA64] in {
-def : Pat<(sext_inreg GPR:$rj, i32), (ADDI_W GPR:$rj, 0)>;
-
 def : PatGprGpr<add, ADD_D>;
 def : PatGprGpr_32<add, ADD_W>;
-
 def : PatGprImm<add, ADDI_D, simm12>;
 def : PatGprImm_32<add, ADDI_W, simm12>;
+def : PatGprGpr<sub, SUB_D>;
+def : PatGprGpr_32<sub, SUB_W>;
 } // Predicates = [IsLA64]
 
+def : PatGprGpr<and, AND>;
+def : PatGprGpr<or, OR>;
+def : PatGprGpr<xor, XOR>;
+
+/// sext and zext
+
+let Predicates = [IsLA64] in {
+def : Pat<(sext_inreg GPR:$rj, i32), (ADDI_W GPR:$rj, 0)>;
+} // Predicates = [IsLA64]
+
+/// Setcc
+
+def : PatGprGpr<setult, SLTU>;
+
+/// Branches and jumps
+
+let isBarrier = 1, isReturn = 1, isTerminator = 1 in
+def PseudoRET : Pseudo<(outs), (ins), [(loongarch_ret)]>,
+                PseudoInstExpansion<(JIRL R0, R1, 0)>;
+
 //===----------------------------------------------------------------------===//
 // Assembler Pseudo Instructions
 //===----------------------------------------------------------------------===//
 
 def : InstAlias<"nop", (ANDI R0, R0, 0)>;
 def : InstAlias<"move $dst, $src", (OR GPR:$dst, GPR:$src, R0)>;
 
 //===----------------------------------------------------------------------===//

llvm/test/CodeGen/LoongArch/ir-instruction/add.ll

-; RUN: llc --mtriple=loongarch32 < %s | FileCheck %s --check-prefix=CHECK32
-; RUN: llc --mtriple=loongarch64 < %s | FileCheck %s --check-prefix=CHECK64
+; RUN: llc --mtriple=loongarch32 < %s | FileCheck %s --check-prefix=LA32
+; RUN: llc --mtriple=loongarch64 < %s | FileCheck %s --check-prefix=LA64
 
-define i32 @addRR(i32 %x, i32 %y) {
-; CHECK32-LABEL: addRR:
-; CHECK32:       # %bb.0: # %entry
-; CHECK32-NEXT:    add.w $a0, $a1, $a0
-; CHECK32-NEXT:    jirl $zero, $ra, 0
-;
-; CHECK64-LABEL: addRR:
-; CHECK64:       # %bb.0: # %entry
-; CHECK64-NEXT:    add.d $a0, $a1, $a0
-; CHECK64-NEXT:    jirl $zero, $ra, 0
-entry:
-  %add = add nsw i32 %y, %x
+;; Exercise the 'add' LLVM IR: https://llvm.org/docs/LangRef.html#add-instruction
+
+define i1 @add_i1(i1 %x, i1 %y) {
+; LA32-LABEL: add_i1:
+; LA32:       # %bb.0:
+; LA32-NEXT:    add.w $a0, $a0, $a1
+; LA32-NEXT:    jirl $zero, $ra, 0
+;
+; LA64-LABEL: add_i1:
+; LA64:       # %bb.0:
+; LA64-NEXT:    add.d $a0, $a0, $a1
+; LA64-NEXT:    jirl $zero, $ra, 0
+  %add = add i1 %x, %y
+  ret i1 %add
+}
+
+define i8 @add_i8(i8 %x, i8 %y) {
+; LA32-LABEL: add_i8:
+; LA32:       # %bb.0:
+; LA32-NEXT:    add.w $a0, $a0, $a1
+; LA32-NEXT:    jirl $zero, $ra, 0
+;
+; LA64-LABEL: add_i8:
+; LA64:       # %bb.0:
+; LA64-NEXT:    add.d $a0, $a0, $a1
+; LA64-NEXT:    jirl $zero, $ra, 0
+  %add = add i8 %x, %y
+  ret i8 %add
+}
+
+define i16 @add_i16(i16 %x, i16 %y) {
+; LA32-LABEL: add_i16:
+; LA32:       # %bb.0:
+; LA32-NEXT:    add.w $a0, $a0, $a1
+; LA32-NEXT:    jirl $zero, $ra, 0
+;
+; LA64-LABEL: add_i16:
+; LA64:       # %bb.0:
+; LA64-NEXT:    add.d $a0, $a0, $a1
+; LA64-NEXT:    jirl $zero, $ra, 0
+  %add = add i16 %x, %y
+  ret i16 %add
+}
+
+define i32 @add_i32(i32 %x, i32 %y) {
+; LA32-LABEL: add_i32:
+; LA32:       # %bb.0:
+; LA32-NEXT:    add.w $a0, $a0, $a1
+; LA32-NEXT:    jirl $zero, $ra, 0
+;
+; LA64-LABEL: add_i32:
+; LA64:       # %bb.0:
+; LA64-NEXT:    add.d $a0, $a0, $a1
+; LA64-NEXT:    jirl $zero, $ra, 0
+  %add = add i32 %x, %y
+  ret i32 %add
+}
+
+;; Match the pattern:
+;; def : PatGprGpr_32<add, ADD_W>;
+define signext i32 @add_i32_sext(i32 %x, i32 %y) {
+; LA32-LABEL: add_i32_sext:
+; LA32:       # %bb.0:
+; LA32-NEXT:    add.w $a0, $a0, $a1
+; LA32-NEXT:    jirl $zero, $ra, 0
+;
+; LA64-LABEL: add_i32_sext:
+; LA64:       # %bb.0:
+; LA64-NEXT:    add.w $a0, $a0, $a1
+; LA64-NEXT:    jirl $zero, $ra, 0
+  %add = add i32 %x, %y
+  ret i32 %add
+}
+
+define i64 @add_i64(i64 %x, i64 %y) {
+; LA32-LABEL: add_i64:
+; LA32:       # %bb.0:
+; LA32-NEXT:    add.w $a1, $a1, $a3
+; LA32-NEXT:    add.w $a2, $a0, $a2
+; LA32-NEXT:    sltu $a0, $a2, $a0
+; LA32-NEXT:    add.w $a1, $a1, $a0
+; LA32-NEXT:    move $a0, $a2
+; LA32-NEXT:    jirl $zero, $ra, 0
+;
+; LA64-LABEL: add_i64:
+; LA64:       # %bb.0:
+; LA64-NEXT:    add.d $a0, $a0, $a1
+; LA64-NEXT:    jirl $zero, $ra, 0
+  %add = add i64 %x, %y
+  ret i64 %add
+}
+
+define i1 @add_i1_3(i1 %x) {
+; LA32-LABEL: add_i1_3:
+; LA32:       # %bb.0:
+; LA32-NEXT:    addi.w $a0, $a0, 1
+; LA32-NEXT:    jirl $zero, $ra, 0
+;
+; LA64-LABEL: add_i1_3:
+; LA64:       # %bb.0:
+; LA64-NEXT:    addi.d $a0, $a0, 1
+; LA64-NEXT:    jirl $zero, $ra, 0
+  %add = add i1 %x, 3
+  ret i1 %add
+}
+
+define i8 @add_i8_3(i8 %x) {
+; LA32-LABEL: add_i8_3:
+; LA32:       # %bb.0:
+; LA32-NEXT:    addi.w $a0, $a0, 3
+; LA32-NEXT:    jirl $zero, $ra, 0
+;
+; LA64-LABEL: add_i8_3:
+; LA64:       # %bb.0:
+; LA64-NEXT:    addi.d $a0, $a0, 3
+; LA64-NEXT:    jirl $zero, $ra, 0
+  %add = add i8 %x, 3
+  ret i8 %add
+}
+
+define i16 @add_i16_3(i16 %x) {
+; LA32-LABEL: add_i16_3:
+; LA32:       # %bb.0:
+; LA32-NEXT:    addi.w $a0, $a0, 3
+; LA32-NEXT:    jirl $zero, $ra, 0
+;
+; LA64-LABEL: add_i16_3:
+; LA64:       # %bb.0:
+; LA64-NEXT:    addi.d $a0, $a0, 3
+; LA64-NEXT:    jirl $zero, $ra, 0
+  %add = add i16 %x, 3
+  ret i16 %add
+}
+
+define i32 @add_i32_3(i32 %x) {
+; LA32-LABEL: add_i32_3:
+; LA32:       # %bb.0:
+; LA32-NEXT:    addi.w $a0, $a0, 3
+; LA32-NEXT:    jirl $zero, $ra, 0
+;
+; LA64-LABEL: add_i32_3:
+; LA64:       # %bb.0:
+; LA64-NEXT:    addi.d $a0, $a0, 3
+; LA64-NEXT:    jirl $zero, $ra, 0
+  %add = add i32 %x, 3
   ret i32 %add
 }
+
+;; Match the pattern:
+;; def : PatGprImm_32<add, ADDI_W, simm12>;
+define signext i32 @add_i32_3_sext(i32 %x) {
+; LA32-LABEL: add_i32_3_sext:
+; LA32:       # %bb.0:
+; LA32-NEXT:    addi.w $a0, $a0, 3
+; LA32-NEXT:    jirl $zero, $ra, 0
+;
+; LA64-LABEL: add_i32_3_sext:
+; LA64:       # %bb.0:
+; LA64-NEXT:    addi.w $a0, $a0, 3
+; LA64-NEXT:    jirl $zero, $ra, 0
+  %add = add i32 %x, 3
+  ret i32 %add
+}
+
+define i64 @add_i64_3(i64 %x) {
+; LA32-LABEL: add_i64_3:
+; LA32:       # %bb.0:
+; LA32-NEXT:    addi.w $a2, $a0, 3
+; LA32-NEXT:    sltu $a0, $a2, $a0
+; LA32-NEXT:    add.w $a1, $a1, $a0
+; LA32-NEXT:    move $a0, $a2
+; LA32-NEXT:    jirl $zero, $ra, 0
+;
+; LA64-LABEL: add_i64_3:
+; LA64:       # %bb.0:
+; LA64-NEXT:    addi.d $a0, $a0, 3
+; LA64-NEXT:    jirl $zero, $ra, 0
+  %add = add i64 %x, 3
+  ret i64 %add
+}

llvm/test/CodeGen/LoongArch/ir-instruction/fadd.ll

+; RUN: llc --mtriple=loongarch32 --mattr=+d < %s | FileCheck %s --check-prefix=LA32
+; RUN: llc --mtriple=loongarch64 --mattr=+d < %s | FileCheck %s --check-prefix=LA64
+
+;; Exercise the 'fadd' LLVM IR: https://llvm.org/docs/LangRef.html#fadd-instruction
+
+define float @fadd_s(float %x, float %y) {
+; LA32-LABEL: fadd_s:
+; LA32:       # %bb.0:
+; LA32-NEXT:    fadd.s $fa0, $fa0, $fa1
+; LA32-NEXT:    jirl $zero, $ra, 0
+;
+; LA64-LABEL: fadd_s:
+; LA64:       # %bb.0:
+; LA64-NEXT:    fadd.s $fa0, $fa0, $fa1
+; LA64-NEXT:    jirl $zero, $ra, 0
+  %add = fadd float %x, %y
+  ret float %add
+}
+
+define double @fadd_d(double %x, double %y) {
+; LA32-LABEL: fadd_d:
+; LA32:       # %bb.0:
+; LA32-NEXT:    fadd.d $fa0, $fa0, $fa1
+; LA32-NEXT:    jirl $zero, $ra, 0
+;
+; LA64-LABEL: fadd_d:
+; LA64:       # %bb.0:
+; LA64-NEXT:    fadd.d $fa0, $fa0, $fa1
+; LA64-NEXT:    jirl $zero, $ra, 0
+  %add = fadd double %x, %y
+  ret double %add
+}

llvm/test/CodeGen/LoongArch/ir-instruction/fdiv.ll

+; RUN: llc --mtriple=loongarch32 --mattr=+d < %s | FileCheck %s --check-prefix=LA32
+; RUN: llc --mtriple=loongarch64 --mattr=+d < %s | FileCheck %s --check-prefix=LA64
+
+;; Exercise the 'fdiv' LLVM IR: https://llvm.org/docs/LangRef.html#fdiv-instruction
+
+define float @fdiv_s(float %x, float %y) {
+; LA32-LABEL: fdiv_s:
+; LA32:       # %bb.0:
+; LA32-NEXT:    fdiv.s $fa0, $fa0, $fa1
+; LA32-NEXT:    jirl $zero, $ra, 0
+;
+; LA64-LABEL: fdiv_s:
+; LA64:       # %bb.0:
+; LA64-NEXT:    fdiv.s $fa0, $fa0, $fa1
+; LA64-NEXT:    jirl $zero, $ra, 0
+  %div = fdiv float %x, %y
+  ret float %div
+}
+
+define double @fdiv_d(double %x, double %y) {
+; LA32-LABEL: fdiv_d:
+; LA32:       # %bb.0:
+; LA32-NEXT:    fdiv.d $fa0, $fa0, $fa1
+; LA32-NEXT:    jirl $zero, $ra, 0
+;
+; LA64-LABEL: fdiv_d:
+; LA64:       # %bb.0:
+; LA64-NEXT:    fdiv.d $fa0, $fa0, $fa1
+; LA64-NEXT:    jirl $zero, $ra, 0
+  %div = fdiv double %x, %y
+  ret double %div
+}

llvm/test/CodeGen/LoongArch/ir-instruction/fmul.ll

+; RUN: llc --mtriple=loongarch32 --mattr=+d < %s | FileCheck %s --check-prefix=LA32
+; RUN: llc --mtriple=loongarch64 --mattr=+d < %s | FileCheck %s --check-prefix=LA64
+
+;; Exercise the 'fmul' LLVM IR: https://llvm.org/docs/LangRef.html#fmul-instruction
+
+define float @fmul_s(float %x, float %y) {
+; LA32-LABEL: fmul_s:
+; LA32:       # %bb.0:
+; LA32-NEXT:    fmul.s $fa0, $fa0, $fa1
+; LA32-NEXT:    jirl $zero, $ra, 0
+;
+; LA64-LABEL: fmul_s:
+; LA64:       # %bb.0:
+; LA64-NEXT:    fmul.s $fa0, $fa0, $fa1
+; LA64-NEXT:    jirl $zero, $ra, 0
+  %mul = fmul float %x, %y
+  ret float %mul
+}
+
+define double @fmul_d(double %x, double %y) {
+; LA32-LABEL: fmul_d:
+; LA32:       # %bb.0:
+; LA32-NEXT:    fmul.d $fa0, $fa0, $fa1
+; LA32-NEXT:    jirl $zero, $ra, 0
+;
+; LA64-LABEL: fmul_d:
+; LA64:       # %bb.0:
+; LA64-NEXT:    fmul.d $fa0, $fa0, $fa1
+; LA64-NEXT:    jirl $zero, $ra, 0
+  %mul = fmul double %x, %y
+  ret double %mul
+}

llvm/test/CodeGen/LoongArch/ir-instruction/fsub.ll

+; RUN: llc --mtriple=loongarch32 --mattr=+d < %s | FileCheck %s --check-prefix=LA32
+; RUN: llc --mtriple=loongarch64 --mattr=+d < %s | FileCheck %s --check-prefix=LA64
+
+;; Exercise the 'fsub' LLVM IR: https://llvm.org/docs/LangRef.html#fsub-instruction
+
+define float @fsub_s(float %x, float %y) {
+; LA32-LABEL: fsub_s:
+; LA32:       # %bb.0:
+; LA32-NEXT:    fsub.s $fa0, $fa0, $fa1
+; LA32-NEXT:    jirl $zero, $ra, 0
+;
+; LA64-LABEL: fsub_s:
+; LA64:       # %bb.0:
+; LA64-NEXT:    fsub.s $fa0, $fa0, $fa1
+; LA64-NEXT:    jirl $zero, $ra, 0
+  %sub = fsub float %x, %y
+  ret float %sub
+}
+
+define double @fsub_d(double %x, double %y) {
+; LA32-LABEL: fsub_d:
+; LA32:       # %bb.0:
+; LA32-NEXT:    fsub.d $fa0, $fa0, $fa1
+; LA32-NEXT:    jirl $zero, $ra, 0
+;
+; LA64-LABEL: fsub_d:
+; LA64:       # %bb.0:
+; LA64-NEXT:    fsub.d $fa0, $fa0, $fa1
+; LA64-NEXT:    jirl $zero, $ra, 0
+  %sub = fsub double %x, %y
+  ret double %sub
+}

llvm/test/CodeGen/LoongArch/ir-instruction/sub.ll

+; RUN: llc --mtriple=loongarch32 < %s | FileCheck %s --check-prefix=LA32
+; RUN: llc --mtriple=loongarch64 < %s | FileCheck %s --check-prefix=LA64
+
+;; Exercise the 'sub' LLVM IR: https://llvm.org/docs/LangRef.html#sub-instruction
+
+define i1 @sub_i1(i1 %x, i1 %y) {
+; LA32-LABEL: sub_i1:
+; LA32:       # %bb.0:
+; LA32-NEXT:    sub.w $a0, $a0, $a1
+; LA32-NEXT:    jirl $zero, $ra, 0
+;
+; LA64-LABEL: sub_i1:
+; LA64:       # %bb.0:
+; LA64-NEXT:    sub.d $a0, $a0, $a1
+; LA64-NEXT:    jirl $zero, $ra, 0
+  %sub = sub i1 %x, %y
+  ret i1 %sub
+}
+
+define i8 @sub_i8(i8 %x, i8 %y) {
+; LA32-LABEL: sub_i8:
+; LA32:       # %bb.0:
+; LA32-NEXT:    sub.w $a0, $a0, $a1
+; LA32-NEXT:    jirl $zero, $ra, 0
+;
+; LA64-LABEL: sub_i8:
+; LA64:       # %bb.0:
+; LA64-NEXT:    sub.d $a0, $a0, $a1
+; LA64-NEXT:    jirl $zero, $ra, 0
+  %sub = sub i8 %x, %y
+  ret i8 %sub
+}
+
+define i16 @sub_i16(i16 %x, i16 %y) {
+; LA32-LABEL: sub_i16:
+; LA32:       # %bb.0:
+; LA32-NEXT:    sub.w $a0, $a0, $a1
+; LA32-NEXT:    jirl $zero, $ra, 0
+;
+; LA64-LABEL: sub_i16:
+; LA64:       # %bb.0:
+; LA64-NEXT:    sub.d $a0, $a0, $a1
+; LA64-NEXT:    jirl $zero, $ra, 0
+  %sub = sub i16 %x, %y
+  ret i16 %sub
+}
+
+define i32 @sub_i32(i32 %x, i32 %y) {
+; LA32-LABEL: sub_i32:
+; LA32:       # %bb.0:
+; LA32-NEXT:    sub.w $a0, $a0, $a1
+; LA32-NEXT:    jirl $zero, $ra, 0
+;
+; LA64-LABEL: sub_i32:
+; LA64:       # %bb.0:
+; LA64-NEXT:    sub.d $a0, $a0, $a1
+; LA64-NEXT:    jirl $zero, $ra, 0
+  %sub = sub i32 %x, %y
+  ret i32 %sub
+}
+
+;; Match the pattern:
+;; def : PatGprGpr_32<sub, SUB_W>;
+define signext i32 @sub_i32_sext(i32 %x, i32 %y) {
+; LA32-LABEL: sub_i32_sext:
+; LA32:       # %bb.0:
+; LA32-NEXT:    sub.w $a0, $a0, $a1
+; LA32-NEXT:    jirl $zero, $ra, 0
+;
+; LA64-LABEL: sub_i32_sext:
+; LA64:       # %bb.0:
+; LA64-NEXT:    sub.w $a0, $a0, $a1
+; LA64-NEXT:    jirl $zero, $ra, 0
+  %sub = sub i32 %x, %y
+  ret i32 %sub
+}
+
+define i64 @sub_i64(i64 %x, i64 %y) {
+; LA32-LABEL: sub_i64:
+; LA32:       # %bb.0:
+; LA32-NEXT:    sub.w $a1, $a1, $a3
+; LA32-NEXT:    sltu $a3, $a0, $a2
+; LA32-NEXT:    sub.w $a1, $a1, $a3
+; LA32-NEXT:    sub.w $a0, $a0, $a2
+; LA32-NEXT:    jirl $zero, $ra, 0
+;
+; LA64-LABEL: sub_i64:
+; LA64:       # %bb.0:
+; LA64-NEXT:    sub.d $a0, $a0, $a1
+; LA64-NEXT:    jirl $zero, $ra, 0
+  %sub = sub i64 %x, %y
+  ret i64 %sub
+}