[DAGCombiner][RISCV] Improve computeKnownBits for (smin X, C) where C is negative.

[Pretty-box]

Summary

[DAGCombiner][RISCV] Improve computeKnownBits for (smin X, C) where C is negative.

If C is negative, the result of the smin must also be
negative, so all sign bits of the result are 1.

[craig.topper]

Pre-commit the test?

llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

3713

CstHigh and CstLow might have been swapped on line 368.

llvm/test/CodeGen/RISCV/min-max.ll

642

pos here meant positive. This is a negative constant.

[craig.topper]

llvm/test/CodeGen/RISCV/min-max.ll

655

This is the code we get without this patch. That's why I didn't bother with the smin case.

llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

if (CstLow && CstHigh) {
         if (ValueLow.isNonNegative() && ValueHigh.isNonNegative()) {
           Known.Zero.setHighBits(MinSignBits);
           break;
         }
       }
     }
     // For SMAX, if CstLow is non-negative we know the result will be
     // non-negative and thus all sign bits are 0.
-    // TODO: There's an equivalent of this for smin with negative constant for
-    // known ones.
+    // For SMIN, if CstHigh is negative we know the result will be
+    // negative and thus all sign bits are 1.
     if (IsMax && CstLow) {
       const APInt &ValueLow = CstLow->getAPIntValue();
       if (ValueLow.isNonNegative()) {
         unsigned SignBits = ComputeNumSignBits(Op.getOperand(0), Depth + 1);
         Known.Zero.setHighBits(std::min(SignBits, ValueLow.getNumSignBits()));
         break;
       }
     }
 
+    if (!IsMax && CstHigh) {
+      const APInt &ValueHigh = CstHigh->getAPIntValue();
+      if (ValueHigh.isNegative()) {
+        unsigned SignBits = ComputeNumSignBits(Op.getOperand(0), Depth + 1);
+        Known.One.setHighBits(std::min(SignBits, ValueHigh.getNumSignBits()));
+        break;
+      }
+    }
+
     Known = computeKnownBits(Op.getOperand(0), DemandedElts, Depth + 1);
     Known2 = computeKnownBits(Op.getOperand(1), DemandedElts, Depth + 1);
     if (IsMax)
       Known = KnownBits::smax(Known, Known2);
     else
       Known = KnownBits::smin(Known, Known2);
     break;
   }

llvm/test/CodeGen/RISCV/min-max.ll

 ; ZBB-LABEL: smax_i32_pos_constant:
 ; ZBB:       # %bb.0:
 ; ZBB-NEXT:    li a1, 10
 ; ZBB-NEXT:    max a0, a0, a1
 ; ZBB-NEXT:    ret
   %c = call i32 @llvm.smax.i32(i32 %a, i32 10)
   ret i32 %c
 }
+
+define signext i32 @smin_i32_pos_constant(i32 signext %a) {
+; NOZBB-LABEL: smin_i32_pos_constant:
+; NOZBB:       # %bb.0:
+; NOZBB-NEXT:    li a1, -10
+; NOZBB-NEXT:    blt a0, a1, .LBB25_2
+; NOZBB-NEXT:  # %bb.1:
+; NOZBB-NEXT:    li a0, -10
+; NOZBB-NEXT:  .LBB25_2:
+; NOZBB-NEXT:    ret
+;
+; ZBB-LABEL: smin_i32_pos_constant:
+; ZBB:       # %bb.0:
+; ZBB-NEXT:    li a1, -10
+; ZBB-NEXT:    min a0, a0, a1
+; ZBB-NEXT:    ret
+  %c = call i32 @llvm.smin.i32(i32 %a, i32 -10)
+  ret i32 %c
+}