[AMDGPU][GFX9][GFX10] Support base+soffset+offset s_dcache_discard's.

[kosarev]

Summary

Resolves part of
https://github.com/llvm/llvm-project/issues/38652

[kosarev]

Removed extra empty line.

[dp]

LGTM.

llvm/lib/Target/AMDGPU/SMInstructions.td

215

For my taste, these comments do not improve code readability (especially being repeated 3 times).
Also I think we should not dogmatically follow 80 columns rule in td files.
The following variant looks better for me despite being a bit wider than recommended:

def _SGPR_IMM : SM_Discard_Pseudo <opName, 
  "_SGPR_IMM", (ins SReg_32:$soffset, smem_offset_mod:$offset), "$soffset$offset", 1, 1>;

[kosarev]

Updated as suugested.

llvm/lib/Target/AMDGPU/SMInstructions.td

class SM_Store_Pseudo <string opName, RegisterClass baseClass,
   RegisterClass SrcClass = srcClass;
   let mayLoad = 0;
   let mayStore = 1;
   let has_glc = 1;
   let has_dlc = 1;
   let ScalarStore = 1;
 }
 
-class SM_Discard_Pseudo <string opName, dag ins, bit isImm>
-  : SM_Pseudo<opName, (outs), ins,
-              " $sbase, " # !if(isImm, "$offset", "$soffset")> {
+class SM_Discard_Pseudo <string opName, string variant, dag offsets,
+                         string asmOffsets, bit hasOffset, bit hasSOffset>
+  : SM_Pseudo<opName, (outs), !con((ins SReg_64:$sbase), offsets),
+              " $sbase, " # asmOffsets> {
   let mayLoad = 0;
   let mayStore = 0;
   let has_glc = 0;
   let has_sdst = 0;
   let ScalarStore = 0;
   let hasSideEffects = 1;
-  let has_offset = isImm;
-  let has_soffset = !not(isImm);
-  let PseudoInstr = opName # !if(isImm, "_IMM", "_SGPR");
+  let has_offset = hasOffset;
+  let has_soffset = hasSOffset;
+  let PseudoInstr = opName # variant;
 }
 
 multiclass SM_Pseudo_Loads<string opName,
                            RegisterClass baseClass,
                            RegisterClass dstClass> {
   def _IMM  : SM_Load_Pseudo <opName,
                               (outs dstClass:$sdst),
                               (ins baseClass:$sbase, i32imm:$offset, CPol:$cpol),
def _SGPR_IMM : SM_Store_Pseudo <opName, baseClass, srcClass,
     " $sdata, $sbase, $soffset$offset$cpol"> {
     let has_offset = 1;
     let has_soffset = 1;
     let PseudoInstr = opName # "_SGPR_IMM";
   }
 }
 
 multiclass SM_Pseudo_Discards<string opName> {
-  def _IMM  : SM_Discard_Pseudo <opName, (ins SReg_64:$sbase, smem_offset:$offset), 1>;
-  def _SGPR : SM_Discard_Pseudo <opName, (ins SReg_64:$sbase, SReg_32:$soffset), 0>;
+  def _IMM  : SM_Discard_Pseudo <opName, "_IMM",
+    (ins smem_offset:$offset), "$offset", 1, 0>;
+  def _SGPR : SM_Discard_Pseudo <opName, "_SGPR",
+    (ins SReg_32:$soffset), "$soffset", 0, 1>;
+  def _SGPR_IMM : SM_Discard_Pseudo <opName, "_SGPR_IMM",
+    (ins SReg_32:$soffset, smem_offset_mod:$offset), "$soffset$offset", 1, 1>;
 }
 
 class SM_Time_Pseudo<string opName, SDPatternOperator node = null_frag> : SM_Pseudo<
   opName, (outs SReg_64_XEXEC:$sdst), (ins),
   " $sdst", [(set i64:$sdst, (node))]> {
   let hasSideEffects = 1;
 
   let mayStore = 0;
   let mayLoad = 0;
   let has_sbase = 0;
 }

 //===----------------------------------------------------------------------===//
 // VI and GFX9.
 //===----------------------------------------------------------------------===//
 
 class SMEM_Real_vi <bits<8> op, SM_Pseudo ps>
   : SM_Real<ps>
   , SIMCInstr<ps.PseudoInstr, SIEncodingFamily.VI>
   , Enc64 {
-  field bit IsGFX9Specific = false;
-  let AssemblerPredicate = !if(IsGFX9Specific, isGFX9Only, isGFX8GFX9);
+  field bit IsGFX9SpecificEncoding = false;
+  let AssemblerPredicate = !if(IsGFX9SpecificEncoding, isGFX9Only, isGFX8GFX9);
   let DecoderNamespace = "GFX8";
 
   let Inst{5-0}   = !if(ps.has_sbase, sbase{6-1}, ?);
   let Inst{12-6}  = !if(ps.has_sdst, sdst{6-0}, ?);
 
   // Note that for GFX9 instructions with immediate offsets, soffset_en
   // must be defined, whereas in GFX8 it's undefined in all cases,
   // meaning GFX9 is not perfectly backward-compatible with GFX8, despite
   // documentation suggesting otherwise.
-  field bit SOffsetEn = !if(IsGFX9Specific,
+  field bit SOffsetEn = !if(IsGFX9SpecificEncoding,
     !if(ps.has_offset, ps.has_soffset, !if(ps.has_soffset, 0, ?)),
     ?);
   let Inst{14} = SOffsetEn;
 
   let Inst{16} = !if(ps.has_glc, cpol{CPolBit.GLC}, ?);
 
   // imm
   // TODO: Shall not be defined if the instruction has no offset nor
   // soffset.
   let Inst{17} = ps.has_offset;
 
   let Inst{25-18} = op;
   let Inst{31-26} = 0x30; //encoding
 
   // VI supports 20-bit unsigned offsets while GFX9+ supports 21-bit signed.
   // Offset value is corrected accordingly when offset is encoded/decoded.
   // TODO: Forbid non-M0 register offsets for GFX8 stores and atomics.
   field bits<21> Offset;
   let Offset{6-0} = !if(ps.has_offset, offset{6-0},
                                        !if(ps.has_soffset, soffset{6-0}, ?));
   let Offset{20-7} = !if(ps.has_offset, offset{20-7}, ?);
   let Inst{52-32} = Offset;
 
   // soffset
-  let Inst{63-57} = !if(!and(IsGFX9Specific, ps.has_soffset), soffset{6-0}, ?);
+  let Inst{63-57} = !if(!and(IsGFX9SpecificEncoding, ps.has_soffset),
+                        soffset{6-0}, ?);
 }
 
 class SMEM_Real_Load_vi<bits<8> op, string ps, dag offsets>
     : SMEM_Real_vi<op, !cast<SM_Pseudo>(ps)> {
   RegisterClass BaseClass = !cast<SM_Load_Pseudo>(ps).BaseClass;
   let InOperandList = !con((ins BaseClass:$sbase), offsets, (ins CPol:$cpol));
 }
 
-multiclass SM_Real_Loads_vi<bits<8> op, string ps> {
-  def _IMM_vi : SMEM_Real_Load_vi <op, ps#"_IMM", (ins smem_offset:$offset)>;
-  def _SGPR_vi : SMEM_Real_Load_vi <op, ps#"_SGPR", (ins SReg_32:$soffset)>;
-  let IsGFX9Specific = true in {
-    // The alternative GFX9 SGPR encoding using soffset to encode the
-    // offset register. Not available in assembler and goes to the GFX9
-    // encoding family to avoid conflicts with the primary SGPR variant.
-    let SOffsetEn = 1, Offset = ?, Subtarget = SIEncodingFamily.GFX9,
-        AsmVariantName = "NonParsable" in
-    def _SGPR_alt_gfx9 : SMEM_Real_Load_vi <op, ps#"_SGPR",
-                                            (ins SReg_32:$soffset)>;
-    def _SGPR_IMM_gfx9 : SMEM_Real_Load_vi <
-      op, ps#"_SGPR_IMM", (ins SReg_32:$soffset, smem_offset_mod:$offset)>;
-  }
-}
+class SMEM_Real_SGPR_alt_gfx9 {
+  bit IsGFX9SpecificEncoding = true;
+  bit SOffsetEn = 1;
+  bit Offset = ?;
+  int Subtarget = SIEncodingFamily.GFX9;
+  string AsmVariantName = "NonParsable";
+}
+
+multiclass SM_Real_Loads_vi<bits<8> op, string ps> {
+  def _IMM_vi : SMEM_Real_Load_vi <op, ps#"_IMM", (ins smem_offset:$offset)>;
+  def _SGPR_vi : SMEM_Real_Load_vi <op, ps#"_SGPR", (ins SReg_32:$soffset)>;
+                                          (ins SReg_32:$soffset)>,
+                       SMEM_Real_SGPR_alt_gfx9;
+  let IsGFX9SpecificEncoding = true in
 
 class SMEM_Real_Store_Base_vi <bits<8> op, SM_Pseudo ps> : SMEM_Real_vi <op, ps> {
   // encoding
   bits<7> sdata;
 
   let sdst = ?;
   let Inst{12-6}  = !if(ps.has_sdst, sdata{6-0}, ?);
 }
 
 class SMEM_Real_Store_vi <bits<8> op, string ps, dag offsets>
     : SMEM_Real_Store_Base_vi <op, !cast<SM_Pseudo>(ps)> {
   RegisterClass SrcClass = !cast<SM_Store_Pseudo>(ps).SrcClass;
   RegisterClass BaseClass = !cast<SM_Store_Pseudo>(ps).BaseClass;
   let InOperandList = !con((ins SrcClass:$sdata, BaseClass:$sbase),
                            offsets, (ins CPol:$cpol));
 }
 
 multiclass SM_Real_Stores_vi<bits<8> op, string ps> {
   def _IMM_vi : SMEM_Real_Store_vi <op, ps#_IMM, (ins smem_offset:$offset)>;
   def _SGPR_vi : SMEM_Real_Store_vi <op, ps#_SGPR, (ins SReg_32:$soffset)>;
-  let IsGFX9Specific = true in {
-    // The alternative GFX9 SGPR encoding using soffset to encode the
-    // offset register. Not available in assembler and goes to the GFX9
-    // encoding family to avoid conflicts with the primary SGPR variant.
-    let SOffsetEn = 1, Offset = ?, Subtarget = SIEncodingFamily.GFX9,
-        AsmVariantName = "NonParsable" in
-    def _SGPR_alt_gfx9 : SMEM_Real_Store_vi <op, ps#"_SGPR",
-                                             (ins SReg_32:$soffset)>;
-    def _SGPR_IMM_gfx9 : SMEM_Real_Store_vi <
-      op, ps#"_SGPR_IMM", (ins SReg_32:$soffset, smem_offset_mod:$offset)>;
-  }
-}
+                                           (ins SReg_32:$soffset)>,
+                       SMEM_Real_SGPR_alt_gfx9;
+  let IsGFX9SpecificEncoding = true in
 
 multiclass SM_Real_Probe_vi<bits<8> op, string ps> {
   def _IMM_vi  : SMEM_Real_Store_Base_vi <op, !cast<SM_Probe_Pseudo>(ps#_IMM)>;
   def _SGPR_vi : SMEM_Real_Store_Base_vi <op, !cast<SM_Probe_Pseudo>(ps#_SGPR)>;
 }
 
 defm S_LOAD_DWORD           : SM_Real_Loads_vi <0x00, "S_LOAD_DWORD">;
 defm S_LOAD_DWORDX2         : SM_Real_Loads_vi <0x01, "S_LOAD_DWORDX2">;

 defm S_ATOMIC_OR_X2               : SM_Real_Atomics_vi <0xa9, "S_ATOMIC_OR_X2">;
 defm S_ATOMIC_XOR_X2              : SM_Real_Atomics_vi <0xaa, "S_ATOMIC_XOR_X2">;
 defm S_ATOMIC_INC_X2              : SM_Real_Atomics_vi <0xab, "S_ATOMIC_INC_X2">;
 defm S_ATOMIC_DEC_X2              : SM_Real_Atomics_vi <0xac, "S_ATOMIC_DEC_X2">;
 
 multiclass SM_Real_Discard_vi<bits<8> op, string ps> {
   def _IMM_vi  : SMEM_Real_vi <op, !cast<SM_Discard_Pseudo>(ps#_IMM)>;
   def _SGPR_vi : SMEM_Real_vi <op, !cast<SM_Discard_Pseudo>(ps#_SGPR)>;
+  def _SGPR_alt_gfx9 : SMEM_Real_vi <op, !cast<SM_Discard_Pseudo>(ps#_SGPR)>,
+                       SMEM_Real_SGPR_alt_gfx9;
+  let IsGFX9SpecificEncoding = true in
+  def _SGPR_IMM_gfx9 : SMEM_Real_vi <op, !cast<SM_Discard_Pseudo>(ps#_SGPR_IMM)>;
 }
 
 defm S_DCACHE_DISCARD    : SM_Real_Discard_vi <0x28, "S_DCACHE_DISCARD">;
 defm S_DCACHE_DISCARD_X2 : SM_Real_Discard_vi <0x29, "S_DCACHE_DISCARD_X2">;
 
 //===----------------------------------------------------------------------===//
 // CI
 //===----------------------------------------------------------------------===//

 defm S_ATOMIC_OR_X2               : SM_Real_Atomics_gfx10 <0xa9, "S_ATOMIC_OR_X2">;
 defm S_ATOMIC_XOR_X2              : SM_Real_Atomics_gfx10 <0xaa, "S_ATOMIC_XOR_X2">;
 defm S_ATOMIC_INC_X2              : SM_Real_Atomics_gfx10 <0xab, "S_ATOMIC_INC_X2">;
 defm S_ATOMIC_DEC_X2              : SM_Real_Atomics_gfx10 <0xac, "S_ATOMIC_DEC_X2">;
 
 multiclass SM_Real_Discard_gfx10<bits<8> op, string ps> {
   def _IMM_gfx10  : SMEM_Real_gfx10 <op, !cast<SM_Pseudo>(ps#_IMM)>;
   def _SGPR_gfx10 : SMEM_Real_gfx10 <op, !cast<SM_Pseudo>(ps#_SGPR)>;
+  def _SGPR_IMM_gfx10 : SMEM_Real_gfx10 <op, !cast<SM_Pseudo>(ps#_SGPR_IMM)>;
 }
 
 defm S_DCACHE_DISCARD    : SM_Real_Discard_gfx10 <0x28, "S_DCACHE_DISCARD">;
 defm S_DCACHE_DISCARD_X2 : SM_Real_Discard_gfx10 <0x29, "S_DCACHE_DISCARD_X2">;
 
 } // End SubtargetPredicate = HasScalarAtomics
 
 def SMInfoTable : GenericTable {

llvm/test/MC/AMDGPU/gfx10_asm_smem.s

 // GFX10: s_atc_probe_buffer 7, s[8:11], 0x64 ; encoding: [0xc4,0x01,0x9c,0xf4,0x64,0x00,0x00,0xfa]
 
 s_dcache_discard s[2:3], s2
 // GFX10: s_dcache_discard s[2:3], s2 ; encoding: [0x01,0x00,0xa0,0xf4,0x00,0x00,0x00,0x04]
 
 s_dcache_discard s[2:3], 100
 // GFX10: s_dcache_discard s[2:3], 0x64 ; encoding: [0x01,0x00,0xa0,0xf4,0x64,0x00,0x00,0xfa]
 
+s_dcache_discard s[2:3], s7 offset:100
+// GFX10: s_dcache_discard s[2:3], s7 offset:0x64 ; encoding: [0x01,0x00,0xa0,0xf4,0x64,0x00,0x00,0x0e]
+
 s_dcache_discard_x2 s[2:3], s2
 // GFX10: s_dcache_discard_x2 s[2:3], s2 ; encoding: [0x01,0x00,0xa4,0xf4,0x00,0x00,0x00,0x04]
 
 s_dcache_discard_x2 s[2:3], 100
 // GFX10: s_dcache_discard_x2 s[2:3], 0x64 ; encoding: [0x01,0x00,0xa4,0xf4,0x64,0x00,0x00,0xfa]
 
+s_dcache_discard_x2 s[2:3], s7 offset:100
+// GFX10: s_dcache_discard_x2 s[2:3], s7 offset:0x64 ; encoding: [0x01,0x00,0xa4,0xf4,0x64,0x00,0x00,0x0e]
+
 s_atomic_add s5, s[2:3], s101
 // GFX10: encoding: [0x41,0x01,0x08,0xf6,0x00,0x00,0x00,0xca]
 
 s_atomic_add s5, s[2:3], 0x64
 // GFX10: encoding: [0x41,0x01,0x08,0xf6,0x64,0x00,0x00,0xfa]
 
 s_atomic_add_x2 s[10:11], s[2:3], s101
 // GFX10: encoding: [0x81,0x02,0x88,0xf6,0x00,0x00,0x00,0xca]

llvm/test/MC/AMDGPU/gfx11_asm_smem.s

 // GFX11-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 s_dcache_discard s[2:3], s2
 // GFX11-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 s_dcache_discard s[2:3], 100
 // GFX11-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
+s_dcache_discard s[2:3], s7 offset:100
+// GFX11-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
+
 s_dcache_discard_x2 s[2:3], s2
 // GFX11-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 s_dcache_discard_x2 s[2:3], 100
 // GFX11-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 s_atomic_add s5, s[2:3], s101
 // GFX11-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU

llvm/test/MC/AMDGPU/gfx9_asm_smem.s

 // CHECK: [0x01,0x00,0xa0,0xc0,0x7b,0x00,0x00,0x00]
 
 s_dcache_discard s[2:3], m0
 // CHECK: [0x01,0x00,0xa0,0xc0,0x7c,0x00,0x00,0x00]
 
 s_dcache_discard s[2:3], 0x0
 // CHECK: [0x01,0x00,0xa2,0xc0,0x00,0x00,0x00,0x00]
 
+s_dcache_discard s[2:3], s7 offset:0x0
+// CHECK: [0x01,0x40,0xa2,0xc0,0x00,0x00,0x00,0x0e]
+
 s_dcache_discard_x2 s[2:3], s0
 // CHECK: [0x01,0x00,0xa4,0xc0,0x00,0x00,0x00,0x00]
 
 s_dcache_discard_x2 s[4:5], s0
 // CHECK: [0x02,0x00,0xa4,0xc0,0x00,0x00,0x00,0x00]
 
 s_dcache_discard_x2 s[100:101], s0
 // CHECK: [0x32,0x00,0xa4,0xc0,0x00,0x00,0x00,0x00]

 // CHECK: [0x01,0x00,0xa4,0xc0,0x7b,0x00,0x00,0x00]
 
 s_dcache_discard_x2 s[2:3], m0
 // CHECK: [0x01,0x00,0xa4,0xc0,0x7c,0x00,0x00,0x00]
 
 s_dcache_discard_x2 s[2:3], 0x0
 // CHECK: [0x01,0x00,0xa6,0xc0,0x00,0x00,0x00,0x00]
 
+s_dcache_discard_x2 s[2:3], s7 offset:0x0
+// CHECK: [0x01,0x40,0xa6,0xc0,0x00,0x00,0x00,0x0e]
+
 s_buffer_atomic_swap s5, s[4:7], s0
 // CHECK: [0x42,0x01,0x00,0xc1,0x00,0x00,0x00,0x00]
 
 s_buffer_atomic_swap s101, s[4:7], s0
 // CHECK: [0x42,0x19,0x00,0xc1,0x00,0x00,0x00,0x00]
 
 s_buffer_atomic_swap flat_scratch_lo, s[4:7], s0
 // CHECK: [0x82,0x19,0x00,0xc1,0x00,0x00,0x00,0x00]

llvm/test/MC/Disassembler/AMDGPU/gfx10_dasm_all.txt

 0x42,0x01,0x29,0xf5,0x00,0x00,0x00,0x04
 
 # GFX10: s_dcache_discard s[2:3], 0x64           ; encoding: [0x01,0x00,0xa0,0xf4,0x64,0x00,0x00,0xfa]
 0x01,0x00,0xa0,0xf4,0x64,0x00,0x00,0xfa
 
 # GFX10: s_dcache_discard s[2:3], s2             ; encoding: [0x01,0x00,0xa0,0xf4,0x00,0x00,0x00,0x04]
 0x01,0x00,0xa0,0xf4,0x00,0x00,0x00,0x04
 
+# GFX10: s_dcache_discard s[2:3], s2 offset:0x12345 ; encoding: [0x01,0x00,0xa0,0xf4,0x45,0x23,0x01,0x04]
+0x01,0x00,0xa0,0xf4,0x45,0x23,0x01,0x04
+
 # GFX10: s_dcache_discard_x2 s[2:3], 0x64        ; encoding: [0x01,0x00,0xa4,0xf4,0x64,0x00,0x00,0xfa]
 0x01,0x00,0xa4,0xf4,0x64,0x00,0x00,0xfa
 
 # GFX10: s_dcache_discard_x2 s[2:3], s2          ; encoding: [0x01,0x00,0xa4,0xf4,0x00,0x00,0x00,0x04]
 0x01,0x00,0xa4,0xf4,0x00,0x00,0x00,0x04
 
+# GFX10: s_dcache_discard_x2 s[2:3], s2 offset:0x12345 ; encoding: [0x01,0x00,0xa4,0xf4,0x45,0x23,0x01,0x04]
+0x01,0x00,0xa4,0xf4,0x45,0x23,0x01,0x04
+
 # GFX10: s_dcache_inv                            ; encoding: [0x00,0x00,0x80,0xf4,0x00,0x00,0x00,0x00]
 0x00,0x00,0x80,0xf4,0x00,0x00,0x00,0x00
 
 # GFX10: s_dcache_wb                             ; encoding: [0x00,0x00,0x84,0xf4,0x00,0x00,0x00,0x00]
 0x00,0x00,0x84,0xf4,0x00,0x00,0x00,0x00
 
 # GFX10: s_decperflevel 0                        ; encoding: [0x00,0x00,0x95,0xbf]
 0x00,0x00,0x95,0xbf

llvm/test/MC/Disassembler/AMDGPU/smem_gfx9.txt

 
 #===------------------------------------------------------------------------===#
 # s_dcache_discard
 #===------------------------------------------------------------------------===#
 
 # GFX9: s_dcache_discard s[100:101], s0 ; encoding: [0x32,0x00,0xa0,0xc0,0x00,0x00,0x00,0x00]
 0x32,0x00,0xa0,0xc0,0x00,0x00,0x00,0x00
 
+# The SGRP variants can alternatively be encoded with imm=0, soffset_en=1
+# and the offset register encoded in the soffset field with the offset
+# field being disregarded.
+# GFX9: s_dcache_discard s[100:101], s64 ; encoding: [0x32,0x40,0xa0,0xc0,0x00,0x00,0x00,0x80]
+0x32,0x40,0xa0,0xc0,0x25,0x00,0x00,0x80
+
 # GFX9: s_dcache_discard s[2:3], 0x0 ; encoding: [0x01,0x00,0xa2,0xc0,0x00,0x00,0x00,0x00]
 0x01,0x00,0xa2,0xc0,0x00,0x00,0x00,0x00
 
+# GFX9: s_dcache_discard s[2:3], s2 offset:0x12345 ; encoding: [0x01,0x40,0xa2,0xc0,0x45,0x23,0x01,0x04]
+0x01,0x40,0xa2,0xc0,0x45,0x23,0x01,0x04
+
 # GFX9: s_dcache_discard_x2 s[2:3], s101 ; encoding: [0x01,0x00,0xa4,0xc0,0x65,0x00,0x00,0x00]
 0x01,0x00,0xa4,0xc0,0x65,0x00,0x00,0x00
 
 # GFX9: s_dcache_discard_x2 s[2:3], 0x0 ; encoding: [0x01,0x00,0xa6,0xc0,0x00,0x00,0x00,0x00]
 0x01,0x00,0xa6,0xc0,0x00,0x00,0x00,0x00
 
+# GFX9: s_dcache_discard_x2 s[2:3], s2 offset:0x12345 ; encoding: [0x01,0x40,0xa6,0xc0,0x45,0x23,0x01,0x04]
+0x01,0x40,0xa6,0xc0,0x45,0x23,0x01,0x04
+
 #===------------------------------------------------------------------------===#
 # s_atomic
 #===------------------------------------------------------------------------===#
 
 # GFX9: s_atomic_add s5, s[2:3], s101    ; encoding: [0x41,0x01,0x08,0xc2,0x65,0x00,0x00,0x00]
 0x41,0x01,0x08,0xc2,0x65,0x00,0x00,0x00
 
 # GFX9: s_atomic_add_x2 s[10:11], s[2:3], s101    ; encoding: [0x81,0x02,0x88,0xc2,0x65,0x00,0x00,0x00]