[SLP][TTI][X86] Implement addsub cost calculation.

[vporpo]

Summary

This patch adds support for the addsub instructions in SLP's getEntryCost().
This relies on extending TTI->getShuffleCost() to return the correct cost
for such instructions.

[vporpo]

Moved the cost calculation code from getShuffleCost() to a separate function: getAltInstrCost().

[vporpo]

Rebased.

llvm/lib/Target/X86/X86TargetTransformInfo.cpp

InstructionCost X86TTIImpl::getShuffleCost(TTI::ShuffleKind Kind,
   // For 2-input shuffles, we must account for splitting the 2 inputs into many.
   if (Kind == TTI::SK_PermuteTwoSrc && LT.first != 1) {
     // We assume that source and destination have the same vector type.
     InstructionCost NumOfDests = LT.first;
     InstructionCost NumOfShufflesPerDest = LT.first * 2 - 1;
     LT.first = NumOfDests * NumOfShufflesPerDest;
   }
 
+  // Add-sub pattern.
+  if (Kind == TTI::SK_Select && Args.size() == 2 && isa<Instruction>(Args[0]) &&
+      isa<Instruction>(Args[1]) && LT.second.isVector()) {
+    unsigned EvenOpcode = cast<Instruction>(Args[0])->getOpcode();
+    unsigned OddOpcode = cast<Instruction>(Args[1])->getOpcode();
+    unsigned Lanes = LT.second.getVectorNumElements();
+    auto *VecTy = FixedVectorType::get(BaseTp->getElementType(), Lanes);
+    if (isLegalAltInstr(VecTy, EvenOpcode, OddOpcode)) {
+      static const CostTblEntry SSE3AddSubTable[] = {
+          {TTI::SK_Select, MVT::v4f32, 1}, // addsubps
+          {TTI::SK_Select, MVT::v2f64, 1}, // addsubpd
+      };
+      static const CostTblEntry AVXAddSubTable[] = {
+          {TTI::SK_Select, MVT::v4f32, 1}, // vaddsubps
+          {TTI::SK_Select, MVT::v2f64, 1}, // vaddsubpd
+      };
+      static const CostTblEntry AVX2AddSubTable[] = {
+          {TTI::SK_Select, MVT::v8f32, 1}, // vaddsubps
+          {TTI::SK_Select, MVT::v4f64, 1}, // vaddsubpd
+      };
+      if (ST->hasSSE3())
+        if (const auto *Entry =
+                CostTableLookup(SSE3AddSubTable, Kind, LT.second))
+          return LT.first * Entry->Cost;
+      if (ST->hasAVX())
+        if (const auto *Entry =
+                CostTableLookup(AVXAddSubTable, Kind, LT.second))
+          return LT.first * Entry->Cost;
+      if (ST->hasAVX2())
+        if (const auto *Entry =
+                CostTableLookup(AVX2AddSubTable, Kind, LT.second))
+          return LT.first * Entry->Cost;
+    }
+  }
+
   static const CostTblEntry AVX512FP16ShuffleTbl[] = {
       {TTI::SK_Broadcast, MVT::v32f16, 1}, // vpbroadcastw
       {TTI::SK_Broadcast, MVT::v16f16, 1}, // vpbroadcastw
       {TTI::SK_Broadcast, MVT::v8f16, 1},  // vpbroadcastw
 
       {TTI::SK_Reverse, MVT::v32f16, 2}, // vpermw
       {TTI::SK_Reverse, MVT::v16f16, 2}, // vpermw
       {TTI::SK_Reverse, MVT::v8f16, 1},  // vpshufb

llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp

public:
 
   /// Gets reordering data for the given tree entry. If the entry is vectorized
   /// - just return ReorderIndices, otherwise check if the scalars can be
   /// reordered and return the most optimal order.
   /// \param TopToBottom If true, include the order of vectorized stores and
   /// insertelement nodes, otherwise skip them.
   Optional<OrdersType> getReorderingData(const TreeEntry &TE, bool TopToBottom);
 
+  /// \Returns true if \p TE is an alt-shuffle that can be lowered to a single
+  /// instruction. An example of this is the X86 addsub instruction.
+  bool isAltShuffleThatLowersToOneInstr(const TreeEntry *TE) const;
+
   /// Reorders the current graph to the most profitable order starting from the
   /// root node to the leaf nodes. The best order is chosen only from the nodes
   /// of the same size (vectorization factor). Smaller nodes are considered
   /// parts of subgraph with smaller VF and they are reordered independently. We
   /// can make it because we still need to extend smaller nodes to the wider VF
   /// and we can merge reordering shuffles with the widening shuffles.
   void reorderTopToBottom();
 
if (Optional<OrdersType> CurrentOrder = findReusedOrderedScalars(TE))
       return CurrentOrder;
     if (TE.Scalars.size() >= 4)
       if (Optional<OrdersType> Order = findPartiallyOrderedLoads(TE))
         return Order;
   }
   return None;
 }
 
+bool BoUpSLP::isAltShuffleThatLowersToOneInstr(const TreeEntry *TE) const {
+  if (TE->isAltShuffleWithRepeatingEvenOddOpcodes()) {
+    VectorType *VecTy =
+        FixedVectorType::get(TE->Scalars[0]->getType(), TE->Scalars.size());
+    unsigned EvenOpcode = TE->getOpcode();
+    unsigned OddOpcode = TE->getAltOpcode();
+    if (TTI->isLegalAltInstr(VecTy, EvenOpcode, OddOpcode))
+      return true;
+  }
+    return false;
+}
+
 void BoUpSLP::reorderTopToBottom() {
   // Maps VF to the graph nodes.
   DenseMap<unsigned, SetVector<TreeEntry *>> VFToOrderedEntries;
   // ExtractElement gather nodes which can be vectorized and need to handle
   // their ordering.
   DenseMap<const TreeEntry *, OrdersType> GathersToOrders;
 
   // AltShuffles can also have a preferred ordering that leads to fewer
if (!ExternalUserReorderIndices.empty()) {
       VFToOrderedEntries[TE->Scalars.size()].insert(TE.get());
       ExternalUserReorderMap.try_emplace(TE.get(),
                                          std::move(ExternalUserReorderIndices));
     }
 
     // Patterns like [fadd,fsub] can be combined into a single instruction in
     // x86. Reordering them into [fsub,fadd] blocks this pattern. So we need
     // to take into account their order when looking for the most used order.
-    if (TE->isAltShuffleWithRepeatingEvenOddOpcodes()) {
-      VectorType *VecTy =
-          FixedVectorType::get(TE->Scalars[0]->getType(), TE->Scalars.size());
-      unsigned EvenOpcode = TE->getOpcode();
-      unsigned OddOpcode = TE->getAltOpcode();
-      if (TTI->isLegalAltInstr(VecTy, EvenOpcode, OddOpcode)) {
-        VFToOrderedEntries[TE->Scalars.size()].insert(TE.get());
-        AltShufflesToOrders.try_emplace(TE.get(), OrdersType());
-      }
+    if (isAltShuffleThatLowersToOneInstr(TE.get())) {
       // TODO: Check the reverse order too.
     }
 
     if (Optional<OrdersType> CurrentOrder =
             getReorderingData(*TE, /*TopToBottom=*/true)) {
       // Do not include ordering for nodes used in the alt opcode vectorization,
       // better to reorder them during bottom-to-top stage. If follow the order
       // here, it causes reordering of the whole graph though actually it is
case Instruction::ShuffleVector: {
         }
       }
       for (Value *V : VL) {
         Instruction *I = cast<Instruction>(V);
         assert(E->isOpcodeOrAlt(I) && "Unexpected main/alternate opcode");
         ScalarCost += TTI->getInstructionCost(I, CostKind);
       }
       // VecCost is equal to sum of the cost of creating 2 vectors
-      // and the cost of creating shuffle.
+      // and the cost of creating shuffle, except if this is an alternate
+      // sequence that can be lowered to a single instruction, like x86 addsub.
       InstructionCost VecCost = 0;
+      bool LowersToOneInstr = isAltShuffleThatLowersToOneInstr(E);
       // Try to find the previous shuffle node with the same operands and same
       // main/alternate ops.
       auto &&TryFindNodeWithEqualOperands = [this, E]() {
         for (const std::unique_ptr<TreeEntry> &TE : VectorizableTree) {
           if (TE.get() == E)
             break;
           if (TE->isAltShuffle() &&
               ((TE->getOpcode() == E->getOpcode() &&
                 TE->getAltOpcode() == E->getAltOpcode()) ||
                (TE->getOpcode() == E->getAltOpcode() &&
                 TE->getAltOpcode() == E->getOpcode())) &&
               TE->hasEqualOperands(*E))
             return true;
         }
         return false;
       };
       if (TryFindNodeWithEqualOperands()) {
         LLVM_DEBUG({
           dbgs() << "SLP: diamond match for alternate node found.\n";
           E->dump();
         });
         // No need to add new vector costs here since we're going to reuse
         // same main/alternate vector ops, just do different shuffling.
       } else if (Instruction::isBinaryOp(E->getOpcode())) {
-        VecCost = TTI->getArithmeticInstrCost(E->getOpcode(), VecTy, CostKind);
-        VecCost += TTI->getArithmeticInstrCost(E->getAltOpcode(), VecTy,
-                                               CostKind);
+        if (!LowersToOneInstr) {
+          VecCost =
+              TTI->getArithmeticInstrCost(E->getOpcode(), VecTy, CostKind);
+          VecCost +=
+              TTI->getArithmeticInstrCost(E->getAltOpcode(), VecTy, CostKind);
+        }
       } else if (auto *CI0 = dyn_cast<CmpInst>(VL0)) {
         VecCost = TTI->getCmpSelInstrCost(E->getOpcode(), ScalarTy,
                                           Builder.getInt1Ty(),
                                           CI0->getPredicate(), CostKind, VL0);
         VecCost += TTI->getCmpSelInstrCost(
             E->getOpcode(), ScalarTy, Builder.getInt1Ty(),
             cast<CmpInst>(E->getAltOp())->getPredicate(), CostKind,
             E->getAltOp());
       } else {
         Type *Src0SclTy = E->getMainOp()->getOperand(0)->getType();
         Type *Src1SclTy = E->getAltOp()->getOperand(0)->getType();
         auto *Src0Ty = FixedVectorType::get(Src0SclTy, VL.size());
         auto *Src1Ty = FixedVectorType::get(Src1SclTy, VL.size());
         VecCost = TTI->getCastInstrCost(E->getOpcode(), VecTy, Src0Ty,
                                         TTI::CastContextHint::None, CostKind);
         VecCost += TTI->getCastInstrCost(E->getAltOpcode(), VecTy, Src1Ty,
                                          TTI::CastContextHint::None, CostKind);
       }
 
       if (E->ReuseShuffleIndices.empty()) {
-        CommonCost =
-            TTI->getShuffleCost(TargetTransformInfo::SK_Select, FinalVecTy);
+        ArrayRef<Value *> Args = {VL[0], VL[1]};
+        CommonCost = TTI->getShuffleCost(
+            TargetTransformInfo::SK_Select, FinalVecTy, /*Mask=*/None,
+            /*Index=*/0, /*SubTp=*/nullptr, /*Args=*/ Args);
       } else {
         SmallVector<int> Mask;
         buildShuffleEntryMask(
             E->Scalars, E->ReorderIndices, E->ReuseShuffleIndices,
             [E](Instruction *I) {
               assert(E->isOpcodeOrAlt(I) && "Unexpected main/alternate opcode");
               return I->getOpcode() == E->getAltOpcode();
             },

llvm/test/Analysis/CostModel/X86/shuffle-add-sub.ll

 ; SSE3-NEXT:  Cost Model: Found an estimated cost of 32 for instruction: %add_16xf16 = fadd <16 x half> undef, undef
 ; SSE3-NEXT:  Cost Model: Found an estimated cost of 32 for instruction: %sub_16xf16 = fsub <16 x half> undef, undef
 ; SSE3-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %addsub_16xf16 = shufflevector <16 x half> %sub_16xf16, <16 x half> %add_16xf16, <16 x i32> <i32 0, i32 17, i32 2, i32 19, i32 4, i32 21, i32 6, i32 23, i32 8, i32 25, i32 10, i32 27, i32 12, i32 29, i32 14, i32 31>
 ; SSE3-NEXT:  Cost Model: Found an estimated cost of 64 for instruction: %add_32xf16 = fadd <32 x half> undef, undef
 ; SSE3-NEXT:  Cost Model: Found an estimated cost of 64 for instruction: %sub_32xf16 = fsub <32 x half> undef, undef
 ; SSE3-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %addsub_32xf16 = shufflevector <32 x half> %sub_32xf16, <32 x half> %add_32xf16, <32 x i32> <i32 0, i32 33, i32 2, i32 35, i32 4, i32 37, i32 6, i32 39, i32 8, i32 41, i32 10, i32 43, i32 12, i32 45, i32 14, i32 47, i32 16, i32 49, i32 18, i32 51, i32 20, i32 53, i32 22, i32 55, i32 24, i32 57, i32 26, i32 59, i32 28, i32 61, i32 30, i32 63>
 ; SSE3-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %add_2xf32 = fadd <2 x float> undef, undef
 ; SSE3-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %sub_2xf32 = fsub <2 x float> undef, undef
-; SSE3-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %addsub_2xf32 = shufflevector <2 x float> %sub_2xf32, <2 x float> %add_2xf32, <2 x i32> <i32 0, i32 3>
+; SSE3-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %addsub_2xf32 = shufflevector <2 x float> %sub_2xf32, <2 x float> %add_2xf32, <2 x i32> <i32 0, i32 3>
 ; SSE3-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %add_4xf32 = fadd <4 x float> undef, undef
 ; SSE3-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %sub_4xf32 = fsub <4 x float> undef, undef
-; SSE3-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %addsub_4xf32 = shufflevector <4 x float> %sub_4xf32, <4 x float> %add_4xf32, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
+; SSE3-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %addsub_4xf32 = shufflevector <4 x float> %sub_4xf32, <4 x float> %add_4xf32, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
 ; SSE3-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %add_8xf32 = fadd <8 x float> undef, undef
 ; SSE3-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %sub_8xf32 = fsub <8 x float> undef, undef
-; SSE3-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %addsub_8xf32 = shufflevector <8 x float> %sub_8xf32, <8 x float> %add_8xf32, <8 x i32> <i32 0, i32 9, i32 2, i32 11, i32 4, i32 13, i32 6, i32 15>
+; SSE3-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %addsub_8xf32 = shufflevector <8 x float> %sub_8xf32, <8 x float> %add_8xf32, <8 x i32> <i32 0, i32 9, i32 2, i32 11, i32 4, i32 13, i32 6, i32 15>
 ; SSE3-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %add_16xf32 = fadd <16 x float> undef, undef
 ; SSE3-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %sub_16xf32 = fsub <16 x float> undef, undef
-; SSE3-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %addsub_16xf32 = shufflevector <16 x float> %sub_16xf32, <16 x float> %add_16xf32, <16 x i32> <i32 0, i32 17, i32 2, i32 19, i32 4, i32 21, i32 6, i32 23, i32 8, i32 25, i32 10, i32 27, i32 12, i32 29, i32 14, i32 31>
+; SSE3-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %addsub_16xf32 = shufflevector <16 x float> %sub_16xf32, <16 x float> %add_16xf32, <16 x i32> <i32 0, i32 17, i32 2, i32 19, i32 4, i32 21, i32 6, i32 23, i32 8, i32 25, i32 10, i32 27, i32 12, i32 29, i32 14, i32 31>
 ; SSE3-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %add_2xf64 = fadd <2 x double> undef, undef
 ; SSE3-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %sub_2xf64 = fsub <2 x double> undef, undef
 ; SSE3-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %addsub_2xf64 = shufflevector <2 x double> %sub_2xf64, <2 x double> %add_2xf64, <2 x i32> <i32 0, i32 3>
 ; SSE3-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %add_4xf64 = fadd <4 x double> undef, undef
 ; SSE3-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %sub_4xf64 = fsub <4 x double> undef, undef
 ; SSE3-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %addsub_4xf64 = shufflevector <4 x double> %sub_4xf64, <4 x double> %add_4xf64, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
 ; SSE3-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %add_8xf64 = fadd <8 x double> undef, undef
 ; SSE3-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %sub_8xf64 = fsub <8 x double> undef, undef

 ; AVX-NEXT:  Cost Model: Found an estimated cost of 32 for instruction: %add_16xf16 = fadd <16 x half> undef, undef
 ; AVX-NEXT:  Cost Model: Found an estimated cost of 32 for instruction: %sub_16xf16 = fsub <16 x half> undef, undef
 ; AVX-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %addsub_16xf16 = shufflevector <16 x half> %sub_16xf16, <16 x half> %add_16xf16, <16 x i32> <i32 0, i32 17, i32 2, i32 19, i32 4, i32 21, i32 6, i32 23, i32 8, i32 25, i32 10, i32 27, i32 12, i32 29, i32 14, i32 31>
 ; AVX-NEXT:  Cost Model: Found an estimated cost of 64 for instruction: %add_32xf16 = fadd <32 x half> undef, undef
 ; AVX-NEXT:  Cost Model: Found an estimated cost of 64 for instruction: %sub_32xf16 = fsub <32 x half> undef, undef
 ; AVX-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %addsub_32xf16 = shufflevector <32 x half> %sub_32xf16, <32 x half> %add_32xf16, <32 x i32> <i32 0, i32 33, i32 2, i32 35, i32 4, i32 37, i32 6, i32 39, i32 8, i32 41, i32 10, i32 43, i32 12, i32 45, i32 14, i32 47, i32 16, i32 49, i32 18, i32 51, i32 20, i32 53, i32 22, i32 55, i32 24, i32 57, i32 26, i32 59, i32 28, i32 61, i32 30, i32 63>
 ; AVX-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %add_2xf32 = fadd <2 x float> undef, undef
 ; AVX-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %sub_2xf32 = fsub <2 x float> undef, undef
-; AVX-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %addsub_2xf32 = shufflevector <2 x float> %sub_2xf32, <2 x float> %add_2xf32, <2 x i32> <i32 0, i32 3>
+; AVX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %addsub_2xf32 = shufflevector <2 x float> %sub_2xf32, <2 x float> %add_2xf32, <2 x i32> <i32 0, i32 3>
 ; AVX-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %add_4xf32 = fadd <4 x float> undef, undef
 ; AVX-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %sub_4xf32 = fsub <4 x float> undef, undef
-; AVX-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %addsub_4xf32 = shufflevector <4 x float> %sub_4xf32, <4 x float> %add_4xf32, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
+; AVX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %addsub_4xf32 = shufflevector <4 x float> %sub_4xf32, <4 x float> %add_4xf32, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
 ; AVX-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %add_8xf32 = fadd <8 x float> undef, undef
 ; AVX-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %sub_8xf32 = fsub <8 x float> undef, undef
-; AVX-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %addsub_8xf32 = shufflevector <8 x float> %sub_8xf32, <8 x float> %add_8xf32, <8 x i32> <i32 0, i32 9, i32 2, i32 11, i32 4, i32 13, i32 6, i32 15>
+; AVX-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %addsub_8xf32 = shufflevector <8 x float> %sub_8xf32, <8 x float> %add_8xf32, <8 x i32> <i32 0, i32 9, i32 2, i32 11, i32 4, i32 13, i32 6, i32 15>
 ; AVX-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %add_16xf32 = fadd <16 x float> undef, undef
 ; AVX-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %sub_16xf32 = fsub <16 x float> undef, undef
-; AVX-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %addsub_16xf32 = shufflevector <16 x float> %sub_16xf32, <16 x float> %add_16xf32, <16 x i32> <i32 0, i32 17, i32 2, i32 19, i32 4, i32 21, i32 6, i32 23, i32 8, i32 25, i32 10, i32 27, i32 12, i32 29, i32 14, i32 31>
+; AVX-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %addsub_16xf32 = shufflevector <16 x float> %sub_16xf32, <16 x float> %add_16xf32, <16 x i32> <i32 0, i32 17, i32 2, i32 19, i32 4, i32 21, i32 6, i32 23, i32 8, i32 25, i32 10, i32 27, i32 12, i32 29, i32 14, i32 31>
 ; AVX-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %add_2xf64 = fadd <2 x double> undef, undef
 ; AVX-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %sub_2xf64 = fsub <2 x double> undef, undef
 ; AVX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %addsub_2xf64 = shufflevector <2 x double> %sub_2xf64, <2 x double> %add_2xf64, <2 x i32> <i32 0, i32 3>
 ; AVX-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %add_4xf64 = fadd <4 x double> undef, undef
 ; AVX-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %sub_4xf64 = fsub <4 x double> undef, undef
 ; AVX-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %addsub_4xf64 = shufflevector <4 x double> %sub_4xf64, <4 x double> %add_4xf64, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
 ; AVX-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %add_8xf64 = fadd <8 x double> undef, undef
 ; AVX-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %sub_8xf64 = fsub <8 x double> undef, undef

 ; AVX2-NEXT:  Cost Model: Found an estimated cost of 32 for instruction: %add_16xf16 = fadd <16 x half> undef, undef
 ; AVX2-NEXT:  Cost Model: Found an estimated cost of 32 for instruction: %sub_16xf16 = fsub <16 x half> undef, undef
 ; AVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %addsub_16xf16 = shufflevector <16 x half> %sub_16xf16, <16 x half> %add_16xf16, <16 x i32> <i32 0, i32 17, i32 2, i32 19, i32 4, i32 21, i32 6, i32 23, i32 8, i32 25, i32 10, i32 27, i32 12, i32 29, i32 14, i32 31>
 ; AVX2-NEXT:  Cost Model: Found an estimated cost of 64 for instruction: %add_32xf16 = fadd <32 x half> undef, undef
 ; AVX2-NEXT:  Cost Model: Found an estimated cost of 64 for instruction: %sub_32xf16 = fsub <32 x half> undef, undef
 ; AVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %addsub_32xf16 = shufflevector <32 x half> %sub_32xf16, <32 x half> %add_32xf16, <32 x i32> <i32 0, i32 33, i32 2, i32 35, i32 4, i32 37, i32 6, i32 39, i32 8, i32 41, i32 10, i32 43, i32 12, i32 45, i32 14, i32 47, i32 16, i32 49, i32 18, i32 51, i32 20, i32 53, i32 22, i32 55, i32 24, i32 57, i32 26, i32 59, i32 28, i32 61, i32 30, i32 63>
 ; AVX2-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %add_2xf32 = fadd <2 x float> undef, undef
 ; AVX2-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %sub_2xf32 = fsub <2 x float> undef, undef
-; AVX2-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %addsub_2xf32 = shufflevector <2 x float> %sub_2xf32, <2 x float> %add_2xf32, <2 x i32> <i32 0, i32 3>
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %addsub_2xf32 = shufflevector <2 x float> %sub_2xf32, <2 x float> %add_2xf32, <2 x i32> <i32 0, i32 3>
 ; AVX2-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %add_4xf32 = fadd <4 x float> undef, undef
 ; AVX2-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %sub_4xf32 = fsub <4 x float> undef, undef
-; AVX2-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %addsub_4xf32 = shufflevector <4 x float> %sub_4xf32, <4 x float> %add_4xf32, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %addsub_4xf32 = shufflevector <4 x float> %sub_4xf32, <4 x float> %add_4xf32, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
 ; AVX2-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %add_8xf32 = fadd <8 x float> undef, undef
 ; AVX2-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %sub_8xf32 = fsub <8 x float> undef, undef
-; AVX2-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %addsub_8xf32 = shufflevector <8 x float> %sub_8xf32, <8 x float> %add_8xf32, <8 x i32> <i32 0, i32 9, i32 2, i32 11, i32 4, i32 13, i32 6, i32 15>
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %addsub_8xf32 = shufflevector <8 x float> %sub_8xf32, <8 x float> %add_8xf32, <8 x i32> <i32 0, i32 9, i32 2, i32 11, i32 4, i32 13, i32 6, i32 15>
 ; AVX2-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %add_16xf32 = fadd <16 x float> undef, undef
 ; AVX2-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %sub_16xf32 = fsub <16 x float> undef, undef
-; AVX2-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %addsub_16xf32 = shufflevector <16 x float> %sub_16xf32, <16 x float> %add_16xf32, <16 x i32> <i32 0, i32 17, i32 2, i32 19, i32 4, i32 21, i32 6, i32 23, i32 8, i32 25, i32 10, i32 27, i32 12, i32 29, i32 14, i32 31>
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %addsub_16xf32 = shufflevector <16 x float> %sub_16xf32, <16 x float> %add_16xf32, <16 x i32> <i32 0, i32 17, i32 2, i32 19, i32 4, i32 21, i32 6, i32 23, i32 8, i32 25, i32 10, i32 27, i32 12, i32 29, i32 14, i32 31>
 ; AVX2-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %add_2xf64 = fadd <2 x double> undef, undef
 ; AVX2-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %sub_2xf64 = fsub <2 x double> undef, undef
 ; AVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %addsub_2xf64 = shufflevector <2 x double> %sub_2xf64, <2 x double> %add_2xf64, <2 x i32> <i32 0, i32 3>
 ; AVX2-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %add_4xf64 = fadd <4 x double> undef, undef
 ; AVX2-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %sub_4xf64 = fsub <4 x double> undef, undef
 ; AVX2-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %addsub_4xf64 = shufflevector <4 x double> %sub_4xf64, <4 x double> %add_4xf64, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
 ; AVX2-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %add_8xf64 = fadd <8 x double> undef, undef
 ; AVX2-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %sub_8xf64 = fsub <8 x double> undef, undef

 ; AVX512-NEXT:  Cost Model: Found an estimated cost of 32 for instruction: %add_16xf16 = fadd <16 x half> undef, undef
 ; AVX512-NEXT:  Cost Model: Found an estimated cost of 32 for instruction: %sub_16xf16 = fsub <16 x half> undef, undef
 ; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %addsub_16xf16 = shufflevector <16 x half> %sub_16xf16, <16 x half> %add_16xf16, <16 x i32> <i32 0, i32 17, i32 2, i32 19, i32 4, i32 21, i32 6, i32 23, i32 8, i32 25, i32 10, i32 27, i32 12, i32 29, i32 14, i32 31>
 ; AVX512-NEXT:  Cost Model: Found an estimated cost of 64 for instruction: %add_32xf16 = fadd <32 x half> undef, undef
 ; AVX512-NEXT:  Cost Model: Found an estimated cost of 64 for instruction: %sub_32xf16 = fsub <32 x half> undef, undef
 ; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %addsub_32xf16 = shufflevector <32 x half> %sub_32xf16, <32 x half> %add_32xf16, <32 x i32> <i32 0, i32 33, i32 2, i32 35, i32 4, i32 37, i32 6, i32 39, i32 8, i32 41, i32 10, i32 43, i32 12, i32 45, i32 14, i32 47, i32 16, i32 49, i32 18, i32 51, i32 20, i32 53, i32 22, i32 55, i32 24, i32 57, i32 26, i32 59, i32 28, i32 61, i32 30, i32 63>
 ; AVX512-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %add_2xf32 = fadd <2 x float> undef, undef
 ; AVX512-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %sub_2xf32 = fsub <2 x float> undef, undef
-; AVX512-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %addsub_2xf32 = shufflevector <2 x float> %sub_2xf32, <2 x float> %add_2xf32, <2 x i32> <i32 0, i32 3>
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %addsub_2xf32 = shufflevector <2 x float> %sub_2xf32, <2 x float> %add_2xf32, <2 x i32> <i32 0, i32 3>
 ; AVX512-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %add_4xf32 = fadd <4 x float> undef, undef
 ; AVX512-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %sub_4xf32 = fsub <4 x float> undef, undef
-; AVX512-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %addsub_4xf32 = shufflevector <4 x float> %sub_4xf32, <4 x float> %add_4xf32, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %addsub_4xf32 = shufflevector <4 x float> %sub_4xf32, <4 x float> %add_4xf32, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
 ; AVX512-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %add_8xf32 = fadd <8 x float> undef, undef
 ; AVX512-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %sub_8xf32 = fsub <8 x float> undef, undef
-; AVX512-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %addsub_8xf32 = shufflevector <8 x float> %sub_8xf32, <8 x float> %add_8xf32, <8 x i32> <i32 0, i32 9, i32 2, i32 11, i32 4, i32 13, i32 6, i32 15>
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %addsub_8xf32 = shufflevector <8 x float> %sub_8xf32, <8 x float> %add_8xf32, <8 x i32> <i32 0, i32 9, i32 2, i32 11, i32 4, i32 13, i32 6, i32 15>
 ; AVX512-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %add_16xf32 = fadd <16 x float> undef, undef
 ; AVX512-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %sub_16xf32 = fsub <16 x float> undef, undef
-; AVX512-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %addsub_16xf32 = shufflevector <16 x float> %sub_16xf32, <16 x float> %add_16xf32, <16 x i32> <i32 0, i32 17, i32 2, i32 19, i32 4, i32 21, i32 6, i32 23, i32 8, i32 25, i32 10, i32 27, i32 12, i32 29, i32 14, i32 31>
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %addsub_16xf32 = shufflevector <16 x float> %sub_16xf32, <16 x float> %add_16xf32, <16 x i32> <i32 0, i32 17, i32 2, i32 19, i32 4, i32 21, i32 6, i32 23, i32 8, i32 25, i32 10, i32 27, i32 12, i32 29, i32 14, i32 31>
 ; AVX512-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %add_2xf64 = fadd <2 x double> undef, undef
 ; AVX512-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %sub_2xf64 = fsub <2 x double> undef, undef
 ; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %addsub_2xf64 = shufflevector <2 x double> %sub_2xf64, <2 x double> %add_2xf64, <2 x i32> <i32 0, i32 3>
 ; AVX512-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %add_4xf64 = fadd <4 x double> undef, undef
 ; AVX512-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %sub_4xf64 = fsub <4 x double> undef, undef
 ; AVX512-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %addsub_4xf64 = shufflevector <4 x double> %sub_4xf64, <4 x double> %add_4xf64, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
 ; AVX512-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %add_8xf64 = fadd <8 x double> undef, undef
 ; AVX512-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %sub_8xf64 = fsub <8 x double> undef, undef
 ; AVX512-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %addsub_8xf64 = shufflevector <8 x double> %sub_8xf64, <8 x double> %add_8xf64, <8 x i32> <i32 0, i32 9, i32 2, i32 11, i32 4, i32 13, i32 6, i32 15>
 ; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret void
 ;
 
 
+
   %add_2xi8 = add <2 x i8> undef, undef
   %sub_2xi8 = sub <2 x i8> undef, undef
   %addsub_2xi8 = shufflevector <2 x i8> %sub_2xi8, <2 x i8> %add_2xi8, <2 x i32> <i32 0, i32 3>
 
   %add_4xi8 = add <4 x i8> undef, undef
   %sub_4xi8 = sub <4 x i8> undef, undef
   %addsub_4xi8 = shufflevector <4 x i8> %sub_4xi8, <4 x i8> %add_4xi8, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
 

llvm/test/Transforms/SLPVectorizer/X86/supernode.ll

 ; S[0] = (A[0] - B[0]) - C[0]
 ; S[1] = (B[1] + C[1]) + A[1]
 define void @test_supernode_addsub_alt(double* %Aarray, double* %Barray, double *%Carray, double *%Sarray) {
 ; ENABLED-LABEL: @test_supernode_addsub_alt(
 ; ENABLED-NEXT:  entry:
 ; ENABLED-NEXT:    [[IDXA0:%.*]] = getelementptr inbounds double, double* [[AARRAY:%.*]], i64 0
 ; ENABLED-NEXT:    [[IDXA1:%.*]] = getelementptr inbounds double, double* [[AARRAY]], i64 1
 ; ENABLED-NEXT:    [[IDXB0:%.*]] = getelementptr inbounds double, double* [[BARRAY:%.*]], i64 0
-; ENABLED-NEXT:    [[IDXB1:%.*]] = getelementptr inbounds double, double* [[BARRAY]], i64 1
 ; ENABLED-NEXT:    [[IDXC0:%.*]] = getelementptr inbounds double, double* [[CARRAY:%.*]], i64 0
 ; ENABLED-NEXT:    [[IDXC1:%.*]] = getelementptr inbounds double, double* [[CARRAY]], i64 1
 ; ENABLED-NEXT:    [[IDXS0:%.*]] = getelementptr inbounds double, double* [[SARRAY:%.*]], i64 0
-; ENABLED-NEXT:    [[IDXS1:%.*]] = getelementptr inbounds double, double* [[SARRAY]], i64 1
 ; ENABLED-NEXT:    [[A0:%.*]] = load double, double* [[IDXA0]], align 8
 ; ENABLED-NEXT:    [[A1:%.*]] = load double, double* [[IDXA1]], align 8
-; ENABLED-NEXT:    [[B0:%.*]] = load double, double* [[IDXB0]], align 8
-; ENABLED-NEXT:    [[B1:%.*]] = load double, double* [[IDXB1]], align 8
+; ENABLED-NEXT:    [[TMP0:%.*]] = bitcast double* [[IDXB0]] to <2 x double>*
+; ENABLED-NEXT:    [[TMP1:%.*]] = load <2 x double>, <2 x double>* [[TMP0]], align 8
 ; ENABLED-NEXT:    [[C0:%.*]] = load double, double* [[IDXC0]], align 8
 ; ENABLED-NEXT:    [[C1:%.*]] = load double, double* [[IDXC1]], align 8
-; ENABLED-NEXT:    [[SUBA0B0:%.*]] = fsub fast double [[A0]], [[B0]]
-; ENABLED-NEXT:    [[ADDB1C1:%.*]] = fadd fast double [[B1]], [[C1]]
-; ENABLED-NEXT:    [[SUB0:%.*]] = fsub fast double [[SUBA0B0]], [[C0]]
-; ENABLED-NEXT:    [[ADD1:%.*]] = fadd fast double [[ADDB1C1]], [[A1]]
-; ENABLED-NEXT:    store double [[SUB0]], double* [[IDXS0]], align 8
-; ENABLED-NEXT:    store double [[ADD1]], double* [[IDXS1]], align 8
+; ENABLED-NEXT:    [[TMP2:%.*]] = insertelement <2 x double> poison, double [[A0]], i32 0
+; ENABLED-NEXT:    [[TMP3:%.*]] = insertelement <2 x double> [[TMP2]], double [[C1]], i32 1
+; ENABLED-NEXT:    [[TMP4:%.*]] = fsub fast <2 x double> [[TMP3]], [[TMP1]]
+; ENABLED-NEXT:    [[TMP5:%.*]] = fadd fast <2 x double> [[TMP3]], [[TMP1]]
+; ENABLED-NEXT:    [[TMP6:%.*]] = shufflevector <2 x double> [[TMP4]], <2 x double> [[TMP5]], <2 x i32> <i32 0, i32 3>
+; ENABLED-NEXT:    [[TMP7:%.*]] = insertelement <2 x double> poison, double [[C0]], i32 0
+; ENABLED-NEXT:    [[TMP8:%.*]] = insertelement <2 x double> [[TMP7]], double [[A1]], i32 1
+; ENABLED-NEXT:    [[TMP9:%.*]] = fsub fast <2 x double> [[TMP6]], [[TMP8]]
+; ENABLED-NEXT:    [[TMP10:%.*]] = fadd fast <2 x double> [[TMP6]], [[TMP8]]
+; ENABLED-NEXT:    [[TMP11:%.*]] = shufflevector <2 x double> [[TMP9]], <2 x double> [[TMP10]], <2 x i32> <i32 0, i32 3>
+; ENABLED-NEXT:    [[TMP12:%.*]] = bitcast double* [[IDXS0]] to <2 x double>*
+; ENABLED-NEXT:    store <2 x double> [[TMP11]], <2 x double>* [[TMP12]], align 8
 ; ENABLED-NEXT:    ret void
 ;
 entry:
   %idxA0 = getelementptr inbounds double, double* %Aarray, i64 0
   %idxA1 = getelementptr inbounds double, double* %Aarray, i64 1
   %idxB0 = getelementptr inbounds double, double* %Barray, i64 0
   %idxB1 = getelementptr inbounds double, double* %Barray, i64 1
   %idxC0 = getelementptr inbounds double, double* %Carray, i64 0