[LegalizeTypes][VP] Add integer promote support for vp.gather and vp.scatter

[Jimerlife]

Summary

Add integer promote support for vp.gather and vp.scatter

[craig.topper]

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpgather.ll

13

This isn't correct code for the IR. This is loading 32 bit elements from memory, but the memory value is only 7 bits.

[craig.topper]

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpgather.ll

13

Oops. I guess it's reading 8 bit elements. So maybe it's ok.

[craig.topper]

llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp

2128

Do we need to promote index and mask for gather?

We don't seem to be testing index and mask promotion for scatter.

[Jimerlife]

llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp

2128

Now I couldn't write index and mask promotion test in RISCV. I think index and mask promotion are unnecessary to RISCV. I add PromoteIntOp_VP_SCATTER with reference to PromoteIntOp_MSCATTER.

[craig.topper]

llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp

2128

Thinking about it. Does RISC-V even need the promote support for data? Shouldn’t the vectorizer be using isLegalMaskedGather from TTI?

llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp

#endif
   case ISD::CTTZ:        Res = PromoteIntRes_CTTZ(N); break;
   case ISD::EXTRACT_VECTOR_ELT:
                          Res = PromoteIntRes_EXTRACT_VECTOR_ELT(N); break;
   case ISD::LOAD:        Res = PromoteIntRes_LOAD(cast<LoadSDNode>(N)); break;
   case ISD::MLOAD:       Res = PromoteIntRes_MLOAD(cast<MaskedLoadSDNode>(N));
     break;
   case ISD::MGATHER:     Res = PromoteIntRes_MGATHER(cast<MaskedGatherSDNode>(N));
     break;
+  case ISD::VP_GATHER:
+    Res = PromoteIntRes_VP_GATHER(cast<VPGatherSDNode>(N));
+    break;
   case ISD::SELECT:
   case ISD::VSELECT:
   case ISD::VP_SELECT:
   case ISD::VP_MERGE:
     Res = PromoteIntRes_Select(N);
     break;
   case ISD::SELECT_CC:   Res = PromoteIntRes_SELECT_CC(N); break;
   case ISD::STRICT_FSETCC:
SDValue Res = DAG.getMaskedGather(DAG.getVTList(NVT, MVT::Other),
                                     N->getMemOperand(), N->getIndexType(),
                                     ExtType);
   // Legalize the chain result - switch anything that used the old chain to
   // use the new one.
   ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
   return Res;
 }
 
+SDValue DAGTypeLegalizer::PromoteIntRes_VP_GATHER(VPGatherSDNode *N) {
+  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
+
+  SDLoc dl(N);
+  SDValue Ops[] = {N->getChain(), N->getBasePtr(), N->getIndex(),
+                   N->getScale(), N->getMask(),    N->getVectorLength()};
+  SDValue Res =
+      DAG.getGatherVP(DAG.getVTList(NVT, MVT::Other), N->getMemoryVT(), dl, Ops,
+                      N->getMemOperand(), N->getIndexType());
+  // Legalize the chain result - switch anything that used the old chain to
+  // use the new one.
+  ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
+  return Res;
+}
+
 /// Promote the overflow flag of an overflowing arithmetic node.
 SDValue DAGTypeLegalizer::PromoteIntRes_Overflow(SDNode *N) {
   // Change the return type of the boolean result while obeying
   // getSetCCResultType.
   EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(1));
   EVT VT = N->getValueType(0);
   EVT SVT = getSetCCResultType(VT);
   SDValue Ops[3] = { N->getOperand(0), N->getOperand(1) };
bool DAGTypeLegalizer::PromoteIntegerOperand(SDNode *N, unsigned OpNo) {
   case ISD::MSTORE:       Res = PromoteIntOp_MSTORE(cast<MaskedStoreSDNode>(N),
                                                     OpNo); break;
   case ISD::MLOAD:        Res = PromoteIntOp_MLOAD(cast<MaskedLoadSDNode>(N),
                                                     OpNo); break;
   case ISD::MGATHER:  Res = PromoteIntOp_MGATHER(cast<MaskedGatherSDNode>(N),
                                                  OpNo); break;
   case ISD::MSCATTER: Res = PromoteIntOp_MSCATTER(cast<MaskedScatterSDNode>(N),
                                                   OpNo); break;
+  case ISD::VP_SCATTER:
+    Res = PromoteIntOp_VP_SCATTER(cast<VPScatterSDNode>(N), OpNo);
+    break;
   case ISD::VP_TRUNCATE:
   case ISD::TRUNCATE:     Res = PromoteIntOp_TRUNCATE(N); break;
   case ISD::FP16_TO_FP:
   case ISD::VP_UITOFP:
   case ISD::UINT_TO_FP:   Res = PromoteIntOp_UINT_TO_FP(N); break;
   case ISD::STRICT_UINT_TO_FP:  Res = PromoteIntOp_STRICT_UINT_TO_FP(N); break;
   case ISD::ZERO_EXTEND:  Res = PromoteIntOp_ZERO_EXTEND(N); break;
   case ISD::EXTRACT_SUBVECTOR: Res = PromoteIntOp_EXTRACT_SUBVECTOR(N); break;
if (OpNo == 2) {
     TruncateStore = true;
   }
 
   return DAG.getMaskedScatter(DAG.getVTList(MVT::Other), N->getMemoryVT(),
                               SDLoc(N), NewOps, N->getMemOperand(),
                               N->getIndexType(), TruncateStore);
 }
 
+SDValue DAGTypeLegalizer::PromoteIntOp_VP_SCATTER(VPScatterSDNode *N,
+                                                  unsigned OpNo) {
+  SmallVector<SDValue, 6> NewOps(N->op_begin(), N->op_end());
+
+  if (OpNo == 5) {
+    // The Mask
+    EVT DataVT = N->getValue().getValueType();
+    NewOps[OpNo] = PromoteTargetBoolean(N->getOperand(OpNo), DataVT);
+  } else if (OpNo == 3) {
+    // The Index
+    if (N->isIndexSigned())
+      // Need to sign extend the index since the bits will likely be used.
+      NewOps[OpNo] = SExtPromotedInteger(N->getOperand(OpNo));
+    else
+      NewOps[OpNo] = ZExtPromotedInteger(N->getOperand(OpNo));
+  } else {
+    NewOps[OpNo] = GetPromotedInteger(N->getOperand(OpNo));
+  }
+
+  return DAG.getScatterVP(DAG.getVTList(MVT::Other), N->getMemoryVT(), SDLoc(N),
+                          NewOps, N->getMemOperand(), N->getIndexType());
+}
+
 SDValue DAGTypeLegalizer::PromoteIntOp_TRUNCATE(SDNode *N) {
   SDValue Op = GetPromotedInteger(N->getOperand(0));
   if (N->getOpcode() == ISD::VP_TRUNCATE)
     return DAG.getNode(ISD::VP_TRUNCATE, SDLoc(N), N->getValueType(0), Op,
                        N->getOperand(1), N->getOperand(2));
   return DAG.getNode(ISD::TRUNCATE, SDLoc(N), N->getValueType(0), Op);
 }
 

llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h

private:
   SDValue PromoteIntRes_FP_TO_XINT(SDNode *N);
   SDValue PromoteIntRes_FP_TO_XINT_SAT(SDNode *N);
   SDValue PromoteIntRes_FP_TO_FP16(SDNode *N);
   SDValue PromoteIntRes_FREEZE(SDNode *N);
   SDValue PromoteIntRes_INT_EXTEND(SDNode *N);
   SDValue PromoteIntRes_LOAD(LoadSDNode *N);
   SDValue PromoteIntRes_MLOAD(MaskedLoadSDNode *N);
   SDValue PromoteIntRes_MGATHER(MaskedGatherSDNode *N);
+  SDValue PromoteIntRes_VP_GATHER(VPGatherSDNode *N);
   SDValue PromoteIntRes_Overflow(SDNode *N);
   SDValue PromoteIntRes_SADDSUBO(SDNode *N, unsigned ResNo);
   SDValue PromoteIntRes_Select(SDNode *N);
   SDValue PromoteIntRes_SELECT_CC(SDNode *N);
   SDValue PromoteIntRes_SETCC(SDNode *N);
   SDValue PromoteIntRes_SHL(SDNode *N);
   SDValue PromoteIntRes_SimpleIntBinOp(SDNode *N);
   SDValue PromoteIntRes_ZExtIntBinOp(SDNode *N);
private:
   SDValue PromoteIntOp_STORE(StoreSDNode *N, unsigned OpNo);
   SDValue PromoteIntOp_TRUNCATE(SDNode *N);
   SDValue PromoteIntOp_UINT_TO_FP(SDNode *N);
   SDValue PromoteIntOp_STRICT_UINT_TO_FP(SDNode *N);
   SDValue PromoteIntOp_ZERO_EXTEND(SDNode *N);
   SDValue PromoteIntOp_MSTORE(MaskedStoreSDNode *N, unsigned OpNo);
   SDValue PromoteIntOp_MLOAD(MaskedLoadSDNode *N, unsigned OpNo);
   SDValue PromoteIntOp_MSCATTER(MaskedScatterSDNode *N, unsigned OpNo);
+  SDValue PromoteIntOp_VP_SCATTER(VPScatterSDNode *N, unsigned OpNo);
   SDValue PromoteIntOp_MGATHER(MaskedGatherSDNode *N, unsigned OpNo);
   SDValue PromoteIntOp_ADDSUBCARRY(SDNode *N, unsigned OpNo);
   SDValue PromoteIntOp_FRAMERETURNADDR(SDNode *N);
   SDValue PromoteIntOp_PREFETCH(SDNode *N, unsigned OpNo);
   SDValue PromoteIntOp_FIX(SDNode *N);
   SDValue PromoteIntOp_FPOWI(SDNode *N);
   SDValue PromoteIntOp_VECREDUCE(SDNode *N);
   SDValue PromoteIntOp_VP_REDUCE(SDNode *N, unsigned OpNo);

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpgather.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+experimental-zvfh,+v -riscv-v-vector-bits-min=128 \
 ; RUN:   -verify-machineinstrs < %s | FileCheck %s --check-prefixes=RV32
 ; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+experimental-zvfh,+v -riscv-v-vector-bits-min=128 \
 ; RUN:   -verify-machineinstrs < %s | FileCheck %s --check-prefixes=RV64
 
+declare <2 x i7> @llvm.vp.gather.v2i7.v2p0i7(<2 x i7*>, <2 x i1>, i32)
+
+define <2 x i7> @vpgather_v2i7(<2 x i7*> %ptrs, <2 x i1> %m, i32 zeroext %evl) {
+; RV32-LABEL: vpgather_v2i7:
+; RV32:       # %bb.0:
+; RV32-NEXT:    vsetvli zero, a0, e8, mf8, ta, mu
+; RV32-NEXT:    vluxei32.v v9, (zero), v8, v0.t
+; RV32-NEXT:    vmv1r.v v8, v9
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vpgather_v2i7:
+; RV64:       # %bb.0:
+; RV64-NEXT:    vsetvli zero, a0, e8, mf8, ta, mu
+; RV64-NEXT:    vluxei64.v v9, (zero), v8, v0.t
+; RV64-NEXT:    vmv1r.v v8, v9
+; RV64-NEXT:    ret
+  %v = call <2 x i7> @llvm.vp.gather.v2i7.v2p0i7(<2 x i7*> %ptrs, <2 x i1> %m, i32 %evl)
+  ret <2 x i7> %v
+}
+
 declare <2 x i8> @llvm.vp.gather.v2i8.v2p0i8(<2 x i8*>, <2 x i1>, i32)
 
 define <2 x i8> @vpgather_v2i8(<2 x i8*> %ptrs, <2 x i1> %m, i32 zeroext %evl) {
 ; RV32-LABEL: vpgather_v2i8:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    vsetvli zero, a0, e8, mf8, ta, mu
 ; RV32-NEXT:    vluxei32.v v9, (zero), v8, v0.t
 ; RV32-NEXT:    vmv1r.v v8, v9

 ; RV32-NEXT:    vluxei32.v v8, (a0), v16, v0.t
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vpgather_baseidx_v32i8:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    addi a3, a1, -16
 ; RV64-NEXT:    vmv1r.v v10, v0
 ; RV64-NEXT:    li a2, 0
-; RV64-NEXT:    bltu a1, a3, .LBB13_2
+; RV64-NEXT:    bltu a1, a3, .LBB14_2
 ; RV64-NEXT:  # %bb.1:
 ; RV64-NEXT:    mv a2, a3
-; RV64-NEXT:  .LBB13_2:
+; RV64-NEXT:  .LBB14_2:
 ; RV64-NEXT:    vsetivli zero, 16, e8, m2, ta, mu
 ; RV64-NEXT:    vslidedown.vi v12, v8, 16
 ; RV64-NEXT:    vsetivli zero, 16, e64, m8, ta, mu
 ; RV64-NEXT:    vsext.vf8 v16, v12
 ; RV64-NEXT:    vsetivli zero, 2, e8, mf4, ta, mu
 ; RV64-NEXT:    vslidedown.vi v0, v10, 2
 ; RV64-NEXT:    vsetvli zero, a2, e8, m1, ta, mu
 ; RV64-NEXT:    vluxei64.v v12, (a0), v16, v0.t
 ; RV64-NEXT:    li a2, 16
-; RV64-NEXT:    bltu a1, a2, .LBB13_4
+; RV64-NEXT:    bltu a1, a2, .LBB14_4
 ; RV64-NEXT:  # %bb.3:
 ; RV64-NEXT:    li a1, 16
-; RV64-NEXT:  .LBB13_4:
+; RV64-NEXT:  .LBB14_4:
 ; RV64-NEXT:    vsetivli zero, 16, e64, m8, ta, mu
 ; RV64-NEXT:    vsext.vf8 v16, v8
 ; RV64-NEXT:    vsetvli zero, a1, e8, m1, ta, mu
 ; RV64-NEXT:    vmv1r.v v0, v10
 ; RV64-NEXT:    vluxei64.v v8, (a0), v16, v0.t
 ; RV64-NEXT:    li a0, 32
 ; RV64-NEXT:    vsetvli zero, a0, e8, m2, tu, mu
 ; RV64-NEXT:    vslideup.vi v8, v12, 16

 declare <32 x double> @llvm.vp.gather.v32f64.v32p0f64(<32 x double*>, <32 x i1>, i32)
 
 define <32 x double> @vpgather_v32f64(<32 x double*> %ptrs, <32 x i1> %m, i32 zeroext %evl) {
 ; RV32-LABEL: vpgather_v32f64:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    addi a2, a0, -16
 ; RV32-NEXT:    vmv1r.v v1, v0
 ; RV32-NEXT:    li a1, 0
-; RV32-NEXT:    bltu a0, a2, .LBB86_2
+; RV32-NEXT:    bltu a0, a2, .LBB87_2
 ; RV32-NEXT:  # %bb.1:
 ; RV32-NEXT:    mv a1, a2
-; RV32-NEXT:  .LBB86_2:
+; RV32-NEXT:  .LBB87_2:
 ; RV32-NEXT:    vsetivli zero, 16, e32, m8, ta, mu
 ; RV32-NEXT:    vslidedown.vi v24, v8, 16
 ; RV32-NEXT:    vsetivli zero, 2, e8, mf4, ta, mu
 ; RV32-NEXT:    vslidedown.vi v0, v1, 2
 ; RV32-NEXT:    vsetvli zero, a1, e64, m8, ta, mu
 ; RV32-NEXT:    vluxei32.v v16, (zero), v24, v0.t
 ; RV32-NEXT:    li a1, 16
-; RV32-NEXT:    bltu a0, a1, .LBB86_4
+; RV32-NEXT:    bltu a0, a1, .LBB87_4
 ; RV32-NEXT:  # %bb.3:
 ; RV32-NEXT:    li a0, 16
-; RV32-NEXT:  .LBB86_4:
+; RV32-NEXT:  .LBB87_4:
 ; RV32-NEXT:    vsetvli zero, a0, e64, m8, ta, mu
 ; RV32-NEXT:    vmv1r.v v0, v1
 ; RV32-NEXT:    vluxei32.v v24, (zero), v8, v0.t
 ; RV32-NEXT:    vmv.v.v v8, v24
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vpgather_v32f64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    addi a2, a0, -16
 ; RV64-NEXT:    vmv1r.v v24, v0
 ; RV64-NEXT:    li a1, 0
-; RV64-NEXT:    bltu a0, a2, .LBB86_2
+; RV64-NEXT:    bltu a0, a2, .LBB87_2
 ; RV64-NEXT:  # %bb.1:
 ; RV64-NEXT:    mv a1, a2
-; RV64-NEXT:  .LBB86_2:
+; RV64-NEXT:  .LBB87_2:
 ; RV64-NEXT:    vsetivli zero, 2, e8, mf4, ta, mu
 ; RV64-NEXT:    vslidedown.vi v0, v24, 2
 ; RV64-NEXT:    vsetvli zero, a1, e64, m8, ta, mu
 ; RV64-NEXT:    vluxei64.v v16, (zero), v16, v0.t
 ; RV64-NEXT:    li a1, 16
-; RV64-NEXT:    bltu a0, a1, .LBB86_4
+; RV64-NEXT:    bltu a0, a1, .LBB87_4
 ; RV64-NEXT:  # %bb.3:
 ; RV64-NEXT:    li a0, 16
-; RV64-NEXT:  .LBB86_4:
+; RV64-NEXT:  .LBB87_4:
 ; RV64-NEXT:    vsetvli zero, a0, e64, m8, ta, mu
 ; RV64-NEXT:    vmv1r.v v0, v24
 ; RV64-NEXT:    vluxei64.v v8, (zero), v8, v0.t
 ; RV64-NEXT:    ret
   %v = call <32 x double> @llvm.vp.gather.v32f64.v32p0f64(<32 x double*> %ptrs, <32 x i1> %m, i32 %evl)
   ret <32 x double> %v
 }
 
 define <32 x double> @vpgather_baseidx_v32i8_v32f64(double* %base, <32 x i8> %idxs, <32 x i1> %m, i32 zeroext %evl) {
 ; RV32-LABEL: vpgather_baseidx_v32i8_v32f64:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    li a3, 16
 ; RV32-NEXT:    mv a2, a1
-; RV32-NEXT:    bltu a1, a3, .LBB87_2
+; RV32-NEXT:    bltu a1, a3, .LBB88_2
 ; RV32-NEXT:  # %bb.1:
 ; RV32-NEXT:    li a2, 16
-; RV32-NEXT:  .LBB87_2:
+; RV32-NEXT:  .LBB88_2:
 ; RV32-NEXT:    li a3, 32
 ; RV32-NEXT:    vsetvli zero, a3, e32, m8, ta, mu
 ; RV32-NEXT:    vsext.vf4 v16, v8
 ; RV32-NEXT:    vsll.vi v16, v16, 3
 ; RV32-NEXT:    vsetvli zero, a2, e64, m8, ta, mu
 ; RV32-NEXT:    vluxei32.v v8, (a0), v16, v0.t
 ; RV32-NEXT:    addi a3, a1, -16
 ; RV32-NEXT:    li a2, 0
-; RV32-NEXT:    bltu a1, a3, .LBB87_4
+; RV32-NEXT:    bltu a1, a3, .LBB88_4
 ; RV32-NEXT:  # %bb.3:
 ; RV32-NEXT:    mv a2, a3
-; RV32-NEXT:  .LBB87_4:
+; RV32-NEXT:  .LBB88_4:
 ; RV32-NEXT:    vsetivli zero, 2, e8, mf4, ta, mu
 ; RV32-NEXT:    vslidedown.vi v0, v0, 2
 ; RV32-NEXT:    vsetivli zero, 16, e32, m8, ta, mu
 ; RV32-NEXT:    vslidedown.vi v24, v16, 16
 ; RV32-NEXT:    vsetvli zero, a2, e64, m8, ta, mu
 ; RV32-NEXT:    vluxei32.v v16, (a0), v24, v0.t
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vpgather_baseidx_v32i8_v32f64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    addi a3, a1, -16
 ; RV64-NEXT:    vmv1r.v v10, v0
 ; RV64-NEXT:    li a2, 0
-; RV64-NEXT:    bltu a1, a3, .LBB87_2
+; RV64-NEXT:    bltu a1, a3, .LBB88_2
 ; RV64-NEXT:  # %bb.1:
 ; RV64-NEXT:    mv a2, a3
-; RV64-NEXT:  .LBB87_2:
+; RV64-NEXT:  .LBB88_2:
 ; RV64-NEXT:    vsetivli zero, 2, e8, mf4, ta, mu
 ; RV64-NEXT:    vslidedown.vi v0, v10, 2
 ; RV64-NEXT:    vsetivli zero, 16, e8, m2, ta, mu
 ; RV64-NEXT:    vslidedown.vi v12, v8, 16
 ; RV64-NEXT:    vsetivli zero, 16, e64, m8, ta, mu
 ; RV64-NEXT:    vsext.vf8 v16, v12
 ; RV64-NEXT:    vsll.vi v16, v16, 3
 ; RV64-NEXT:    vsetvli zero, a2, e64, m8, ta, mu
 ; RV64-NEXT:    vluxei64.v v16, (a0), v16, v0.t
 ; RV64-NEXT:    li a2, 16
-; RV64-NEXT:    bltu a1, a2, .LBB87_4
+; RV64-NEXT:    bltu a1, a2, .LBB88_4
 ; RV64-NEXT:  # %bb.3:
 ; RV64-NEXT:    li a1, 16
-; RV64-NEXT:  .LBB87_4:
+; RV64-NEXT:  .LBB88_4:
 ; RV64-NEXT:    vsetivli zero, 16, e64, m8, ta, mu
 ; RV64-NEXT:    vsext.vf8 v24, v8
 ; RV64-NEXT:    vsll.vi v24, v24, 3
 ; RV64-NEXT:    vsetvli zero, a1, e64, m8, ta, mu
 ; RV64-NEXT:    vmv1r.v v0, v10
 ; RV64-NEXT:    vluxei64.v v8, (a0), v24, v0.t
 ; RV64-NEXT:    ret
   %ptrs = getelementptr inbounds double, double* %base, <32 x i8> %idxs
   %v = call <32 x double> @llvm.vp.gather.v32f64.v32p0f64(<32 x double*> %ptrs, <32 x i1> %m, i32 %evl)
   ret <32 x double> %v
 }
 
 define <32 x double> @vpgather_baseidx_sext_v32i8_v32f64(double* %base, <32 x i8> %idxs, <32 x i1> %m, i32 zeroext %evl) {
 ; RV32-LABEL: vpgather_baseidx_sext_v32i8_v32f64:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    vmv1r.v v10, v0
 ; RV32-NEXT:    li a2, 0
 ; RV32-NEXT:    vsetivli zero, 16, e8, m2, ta, mu
 ; RV32-NEXT:    vslidedown.vi v12, v8, 16
 ; RV32-NEXT:    vsetivli zero, 16, e64, m8, ta, mu
 ; RV32-NEXT:    addi a3, a1, -16
 ; RV32-NEXT:    vsext.vf8 v16, v12
-; RV32-NEXT:    bltu a1, a3, .LBB88_2
+; RV32-NEXT:    bltu a1, a3, .LBB89_2
 ; RV32-NEXT:  # %bb.1:
 ; RV32-NEXT:    mv a2, a3
-; RV32-NEXT:  .LBB88_2:
+; RV32-NEXT:  .LBB89_2:
 ; RV32-NEXT:    vsext.vf8 v24, v8
 ; RV32-NEXT:    vsll.vi v16, v16, 3
 ; RV32-NEXT:    vsetvli zero, a2, e32, m4, ta, mu
 ; RV32-NEXT:    vncvt.x.x.w v12, v16
 ; RV32-NEXT:    vsetivli zero, 2, e8, mf4, ta, mu
 ; RV32-NEXT:    vslidedown.vi v0, v10, 2
 ; RV32-NEXT:    vsetvli zero, a2, e64, m8, ta, mu
 ; RV32-NEXT:    vluxei32.v v16, (a0), v12, v0.t
 ; RV32-NEXT:    li a2, 16
-; RV32-NEXT:    bltu a1, a2, .LBB88_4
+; RV32-NEXT:    bltu a1, a2, .LBB89_4
 ; RV32-NEXT:  # %bb.3:
 ; RV32-NEXT:    li a1, 16
-; RV32-NEXT:  .LBB88_4:
+; RV32-NEXT:  .LBB89_4:
 ; RV32-NEXT:    vsetivli zero, 16, e64, m8, ta, mu
 ; RV32-NEXT:    vsll.vi v24, v24, 3
 ; RV32-NEXT:    vsetvli zero, a1, e32, m4, ta, mu
 ; RV32-NEXT:    vncvt.x.x.w v4, v24
 ; RV32-NEXT:    vsetvli zero, zero, e64, m8, ta, mu
 ; RV32-NEXT:    vmv1r.v v0, v10
 ; RV32-NEXT:    vluxei32.v v8, (a0), v4, v0.t
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vpgather_baseidx_sext_v32i8_v32f64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vmv1r.v v10, v0
 ; RV64-NEXT:    li a2, 0
 ; RV64-NEXT:    vsetivli zero, 16, e8, m2, ta, mu
 ; RV64-NEXT:    vslidedown.vi v12, v8, 16
 ; RV64-NEXT:    vsetivli zero, 16, e64, m8, ta, mu
 ; RV64-NEXT:    addi a3, a1, -16
 ; RV64-NEXT:    vsext.vf8 v16, v12
-; RV64-NEXT:    bltu a1, a3, .LBB88_2
+; RV64-NEXT:    bltu a1, a3, .LBB89_2
 ; RV64-NEXT:  # %bb.1:
 ; RV64-NEXT:    mv a2, a3
-; RV64-NEXT:  .LBB88_2:
+; RV64-NEXT:  .LBB89_2:
 ; RV64-NEXT:    vsext.vf8 v24, v8
 ; RV64-NEXT:    vsetivli zero, 2, e8, mf4, ta, mu
 ; RV64-NEXT:    vslidedown.vi v0, v10, 2
 ; RV64-NEXT:    vsetivli zero, 16, e64, m8, ta, mu
 ; RV64-NEXT:    vsll.vi v16, v16, 3
 ; RV64-NEXT:    vsetvli zero, a2, e64, m8, ta, mu
 ; RV64-NEXT:    vluxei64.v v16, (a0), v16, v0.t
 ; RV64-NEXT:    li a2, 16
-; RV64-NEXT:    bltu a1, a2, .LBB88_4
+; RV64-NEXT:    bltu a1, a2, .LBB89_4
 ; RV64-NEXT:  # %bb.3:
 ; RV64-NEXT:    li a1, 16
-; RV64-NEXT:  .LBB88_4:
+; RV64-NEXT:  .LBB89_4:
 ; RV64-NEXT:    vsetivli zero, 16, e64, m8, ta, mu
 ; RV64-NEXT:    vsll.vi v24, v24, 3
 ; RV64-NEXT:    vsetvli zero, a1, e64, m8, ta, mu
 ; RV64-NEXT:    vmv1r.v v0, v10
 ; RV64-NEXT:    vluxei64.v v8, (a0), v24, v0.t
 ; RV64-NEXT:    ret
   %eidxs = sext <32 x i8> %idxs to <32 x i64>
   %ptrs = getelementptr inbounds double, double* %base, <32 x i64> %eidxs
   %v = call <32 x double> @llvm.vp.gather.v32f64.v32p0f64(<32 x double*> %ptrs, <32 x i1> %m, i32 %evl)
   ret <32 x double> %v
 }
 
 define <32 x double> @vpgather_baseidx_zext_v32i8_v32f64(double* %base, <32 x i8> %idxs, <32 x i1> %m, i32 zeroext %evl) {
 ; RV32-LABEL: vpgather_baseidx_zext_v32i8_v32f64:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    vmv1r.v v10, v0
 ; RV32-NEXT:    li a2, 0
 ; RV32-NEXT:    vsetivli zero, 16, e8, m2, ta, mu
 ; RV32-NEXT:    vslidedown.vi v12, v8, 16
 ; RV32-NEXT:    vsetivli zero, 16, e64, m8, ta, mu
 ; RV32-NEXT:    addi a3, a1, -16
 ; RV32-NEXT:    vzext.vf8 v16, v12
-; RV32-NEXT:    bltu a1, a3, .LBB89_2
+; RV32-NEXT:    bltu a1, a3, .LBB90_2
 ; RV32-NEXT:  # %bb.1:
 ; RV32-NEXT:    mv a2, a3
-; RV32-NEXT:  .LBB89_2:
+; RV32-NEXT:  .LBB90_2:
 ; RV32-NEXT:    vzext.vf8 v24, v8
 ; RV32-NEXT:    vsll.vi v16, v16, 3
 ; RV32-NEXT:    vsetvli zero, a2, e32, m4, ta, mu
 ; RV32-NEXT:    vncvt.x.x.w v12, v16
 ; RV32-NEXT:    vsetivli zero, 2, e8, mf4, ta, mu
 ; RV32-NEXT:    vslidedown.vi v0, v10, 2
 ; RV32-NEXT:    vsetvli zero, a2, e64, m8, ta, mu
 ; RV32-NEXT:    vluxei32.v v16, (a0), v12, v0.t
 ; RV32-NEXT:    li a2, 16
-; RV32-NEXT:    bltu a1, a2, .LBB89_4
+; RV32-NEXT:    bltu a1, a2, .LBB90_4
 ; RV32-NEXT:  # %bb.3:
 ; RV32-NEXT:    li a1, 16
-; RV32-NEXT:  .LBB89_4:
+; RV32-NEXT:  .LBB90_4:
 ; RV32-NEXT:    vsetivli zero, 16, e64, m8, ta, mu
 ; RV32-NEXT:    vsll.vi v24, v24, 3
 ; RV32-NEXT:    vsetvli zero, a1, e32, m4, ta, mu
 ; RV32-NEXT:    vncvt.x.x.w v4, v24
 ; RV32-NEXT:    vsetvli zero, zero, e64, m8, ta, mu
 ; RV32-NEXT:    vmv1r.v v0, v10
 ; RV32-NEXT:    vluxei32.v v8, (a0), v4, v0.t
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vpgather_baseidx_zext_v32i8_v32f64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vmv1r.v v10, v0
 ; RV64-NEXT:    li a2, 0
 ; RV64-NEXT:    vsetivli zero, 16, e8, m2, ta, mu
 ; RV64-NEXT:    vslidedown.vi v12, v8, 16
 ; RV64-NEXT:    vsetivli zero, 16, e64, m8, ta, mu
 ; RV64-NEXT:    addi a3, a1, -16
 ; RV64-NEXT:    vzext.vf8 v16, v12
-; RV64-NEXT:    bltu a1, a3, .LBB89_2
+; RV64-NEXT:    bltu a1, a3, .LBB90_2
 ; RV64-NEXT:  # %bb.1:
 ; RV64-NEXT:    mv a2, a3
-; RV64-NEXT:  .LBB89_2:
+; RV64-NEXT:  .LBB90_2:
 ; RV64-NEXT:    vzext.vf8 v24, v8
 ; RV64-NEXT:    vsetivli zero, 2, e8, mf4, ta, mu
 ; RV64-NEXT:    vslidedown.vi v0, v10, 2
 ; RV64-NEXT:    vsetivli zero, 16, e64, m8, ta, mu
 ; RV64-NEXT:    vsll.vi v16, v16, 3
 ; RV64-NEXT:    vsetvli zero, a2, e64, m8, ta, mu
 ; RV64-NEXT:    vluxei64.v v16, (a0), v16, v0.t
 ; RV64-NEXT:    li a2, 16
-; RV64-NEXT:    bltu a1, a2, .LBB89_4
+; RV64-NEXT:    bltu a1, a2, .LBB90_4
 ; RV64-NEXT:  # %bb.3:
 ; RV64-NEXT:    li a1, 16
-; RV64-NEXT:  .LBB89_4:
+; RV64-NEXT:  .LBB90_4:
 ; RV64-NEXT:    vsetivli zero, 16, e64, m8, ta, mu
 ; RV64-NEXT:    vsll.vi v24, v24, 3
 ; RV64-NEXT:    vsetvli zero, a1, e64, m8, ta, mu
 ; RV64-NEXT:    vmv1r.v v0, v10
 ; RV64-NEXT:    vluxei64.v v8, (a0), v24, v0.t
 ; RV64-NEXT:    ret
   %eidxs = zext <32 x i8> %idxs to <32 x i64>
   %ptrs = getelementptr inbounds double, double* %base, <32 x i64> %eidxs
   %v = call <32 x double> @llvm.vp.gather.v32f64.v32p0f64(<32 x double*> %ptrs, <32 x i1> %m, i32 %evl)
   ret <32 x double> %v
 }
 
 define <32 x double> @vpgather_baseidx_v32i16_v32f64(double* %base, <32 x i16> %idxs, <32 x i1> %m, i32 zeroext %evl) {
 ; RV32-LABEL: vpgather_baseidx_v32i16_v32f64:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    li a3, 16
 ; RV32-NEXT:    mv a2, a1
-; RV32-NEXT:    bltu a1, a3, .LBB90_2
+; RV32-NEXT:    bltu a1, a3, .LBB91_2
 ; RV32-NEXT:  # %bb.1:
 ; RV32-NEXT:    li a2, 16
-; RV32-NEXT:  .LBB90_2:
+; RV32-NEXT:  .LBB91_2:
 ; RV32-NEXT:    li a3, 32
 ; RV32-NEXT:    vsetvli zero, a3, e32, m8, ta, mu
 ; RV32-NEXT:    vsext.vf2 v16, v8
 ; RV32-NEXT:    vsll.vi v16, v16, 3
 ; RV32-NEXT:    vsetvli zero, a2, e64, m8, ta, mu
 ; RV32-NEXT:    vluxei32.v v8, (a0), v16, v0.t
 ; RV32-NEXT:    addi a3, a1, -16
 ; RV32-NEXT:    li a2, 0
-; RV32-NEXT:    bltu a1, a3, .LBB90_4
+; RV32-NEXT:    bltu a1, a3, .LBB91_4
 ; RV32-NEXT:  # %bb.3:
 ; RV32-NEXT:    mv a2, a3
-; RV32-NEXT:  .LBB90_4:
+; RV32-NEXT:  .LBB91_4:
 ; RV32-NEXT:    vsetivli zero, 2, e8, mf4, ta, mu
 ; RV32-NEXT:    vslidedown.vi v0, v0, 2
 ; RV32-NEXT:    vsetivli zero, 16, e32, m8, ta, mu
 ; RV32-NEXT:    vslidedown.vi v24, v16, 16
 ; RV32-NEXT:    vsetvli zero, a2, e64, m8, ta, mu
 ; RV32-NEXT:    vluxei32.v v16, (a0), v24, v0.t
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vpgather_baseidx_v32i16_v32f64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    addi a3, a1, -16
 ; RV64-NEXT:    vmv1r.v v12, v0
 ; RV64-NEXT:    li a2, 0
-; RV64-NEXT:    bltu a1, a3, .LBB90_2
+; RV64-NEXT:    bltu a1, a3, .LBB91_2
 ; RV64-NEXT:  # %bb.1:
 ; RV64-NEXT:    mv a2, a3
-; RV64-NEXT:  .LBB90_2:
+; RV64-NEXT:  .LBB91_2:
 ; RV64-NEXT:    vsetivli zero, 2, e8, mf4, ta, mu
 ; RV64-NEXT:    vslidedown.vi v0, v12, 2
 ; RV64-NEXT:    vsetivli zero, 16, e16, m4, ta, mu
 ; RV64-NEXT:    vslidedown.vi v16, v8, 16
 ; RV64-NEXT:    vsetivli zero, 16, e64, m8, ta, mu
 ; RV64-NEXT:    vsext.vf4 v24, v16
 ; RV64-NEXT:    vsll.vi v16, v24, 3
 ; RV64-NEXT:    vsetvli zero, a2, e64, m8, ta, mu
 ; RV64-NEXT:    vluxei64.v v16, (a0), v16, v0.t
 ; RV64-NEXT:    li a2, 16
-; RV64-NEXT:    bltu a1, a2, .LBB90_4
+; RV64-NEXT:    bltu a1, a2, .LBB91_4
 ; RV64-NEXT:  # %bb.3:
 ; RV64-NEXT:    li a1, 16
-; RV64-NEXT:  .LBB90_4:
+; RV64-NEXT:  .LBB91_4:
 ; RV64-NEXT:    vsetivli zero, 16, e64, m8, ta, mu
 ; RV64-NEXT:    vsext.vf4 v24, v8
 ; RV64-NEXT:    vsll.vi v24, v24, 3
 ; RV64-NEXT:    vsetvli zero, a1, e64, m8, ta, mu
 ; RV64-NEXT:    vmv1r.v v0, v12
 ; RV64-NEXT:    vluxei64.v v8, (a0), v24, v0.t
 ; RV64-NEXT:    ret
   %ptrs = getelementptr inbounds double, double* %base, <32 x i16> %idxs
   %v = call <32 x double> @llvm.vp.gather.v32f64.v32p0f64(<32 x double*> %ptrs, <32 x i1> %m, i32 %evl)
   ret <32 x double> %v
 }
 
 define <32 x double> @vpgather_baseidx_sext_v32i16_v32f64(double* %base, <32 x i16> %idxs, <32 x i1> %m, i32 zeroext %evl) {
 ; RV32-LABEL: vpgather_baseidx_sext_v32i16_v32f64:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    vmv1r.v v12, v0
 ; RV32-NEXT:    li a2, 0
 ; RV32-NEXT:    vsetivli zero, 16, e16, m4, ta, mu
 ; RV32-NEXT:    vslidedown.vi v24, v8, 16
 ; RV32-NEXT:    vsetivli zero, 16, e64, m8, ta, mu
 ; RV32-NEXT:    addi a3, a1, -16
 ; RV32-NEXT:    vsext.vf4 v16, v24
-; RV32-NEXT:    bltu a1, a3, .LBB91_2
+; RV32-NEXT:    bltu a1, a3, .LBB92_2
 ; RV32-NEXT:  # %bb.1:
 ; RV32-NEXT:    mv a2, a3
-; RV32-NEXT:  .LBB91_2:
+; RV32-NEXT:  .LBB92_2:
 ; RV32-NEXT:    vsext.vf4 v24, v8
 ; RV32-NEXT:    vsll.vi v16, v16, 3
 ; RV32-NEXT:    vsetvli zero, a2, e32, m4, ta, mu
 ; RV32-NEXT:    vncvt.x.x.w v8, v16
 ; RV32-NEXT:    vsetivli zero, 2, e8, mf4, ta, mu
 ; RV32-NEXT:    vslidedown.vi v0, v12, 2
 ; RV32-NEXT:    vsetvli zero, a2, e64, m8, ta, mu
 ; RV32-NEXT:    vluxei32.v v16, (a0), v8, v0.t
 ; RV32-NEXT:    li a2, 16
-; RV32-NEXT:    bltu a1, a2, .LBB91_4
+; RV32-NEXT:    bltu a1, a2, .LBB92_4
 ; RV32-NEXT:  # %bb.3:
 ; RV32-NEXT:    li a1, 16
-; RV32-NEXT:  .LBB91_4:
+; RV32-NEXT:  .LBB92_4:
 ; RV32-NEXT:    vsetivli zero, 16, e64, m8, ta, mu
 ; RV32-NEXT:    vsll.vi v24, v24, 3
 ; RV32-NEXT:    vsetvli zero, a1, e32, m4, ta, mu
 ; RV32-NEXT:    vncvt.x.x.w v4, v24
 ; RV32-NEXT:    vsetvli zero, zero, e64, m8, ta, mu
 ; RV32-NEXT:    vmv1r.v v0, v12
 ; RV32-NEXT:    vluxei32.v v8, (a0), v4, v0.t
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vpgather_baseidx_sext_v32i16_v32f64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vmv1r.v v12, v0
 ; RV64-NEXT:    li a2, 0
 ; RV64-NEXT:    vsetivli zero, 16, e16, m4, ta, mu
 ; RV64-NEXT:    vslidedown.vi v24, v8, 16
 ; RV64-NEXT:    vsetivli zero, 16, e64, m8, ta, mu
 ; RV64-NEXT:    addi a3, a1, -16
 ; RV64-NEXT:    vsext.vf4 v16, v24
-; RV64-NEXT:    bltu a1, a3, .LBB91_2
+; RV64-NEXT:    bltu a1, a3, .LBB92_2
 ; RV64-NEXT:  # %bb.1:
 ; RV64-NEXT:    mv a2, a3
-; RV64-NEXT:  .LBB91_2:
+; RV64-NEXT:  .LBB92_2:
 ; RV64-NEXT:    vsext.vf4 v24, v8
 ; RV64-NEXT:    vsetivli zero, 2, e8, mf4, ta, mu
 ; RV64-NEXT:    vslidedown.vi v0, v12, 2
 ; RV64-NEXT:    vsetivli zero, 16, e64, m8, ta, mu
 ; RV64-NEXT:    vsll.vi v16, v16, 3
 ; RV64-NEXT:    vsetvli zero, a2, e64, m8, ta, mu
 ; RV64-NEXT:    vluxei64.v v16, (a0), v16, v0.t
 ; RV64-NEXT:    li a2, 16
-; RV64-NEXT:    bltu a1, a2, .LBB91_4
+; RV64-NEXT:    bltu a1, a2, .LBB92_4
 ; RV64-NEXT:  # %bb.3:
 ; RV64-NEXT:    li a1, 16
-; RV64-NEXT:  .LBB91_4:
+; RV64-NEXT:  .LBB92_4:
 ; RV64-NEXT:    vsetivli zero, 16, e64, m8, ta, mu
 ; RV64-NEXT:    vsll.vi v24, v24, 3
 ; RV64-NEXT:    vsetvli zero, a1, e64, m8, ta, mu
 ; RV64-NEXT:    vmv1r.v v0, v12
 ; RV64-NEXT:    vluxei64.v v8, (a0), v24, v0.t
 ; RV64-NEXT:    ret
   %eidxs = sext <32 x i16> %idxs to <32 x i64>
   %ptrs = getelementptr inbounds double, double* %base, <32 x i64> %eidxs
   %v = call <32 x double> @llvm.vp.gather.v32f64.v32p0f64(<32 x double*> %ptrs, <32 x i1> %m, i32 %evl)
   ret <32 x double> %v
 }
 
 define <32 x double> @vpgather_baseidx_zext_v32i16_v32f64(double* %base, <32 x i16> %idxs, <32 x i1> %m, i32 zeroext %evl) {
 ; RV32-LABEL: vpgather_baseidx_zext_v32i16_v32f64:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    vmv1r.v v12, v0
 ; RV32-NEXT:    li a2, 0
 ; RV32-NEXT:    vsetivli zero, 16, e16, m4, ta, mu
 ; RV32-NEXT:    vslidedown.vi v24, v8, 16
 ; RV32-NEXT:    vsetivli zero, 16, e64, m8, ta, mu
 ; RV32-NEXT:    addi a3, a1, -16
 ; RV32-NEXT:    vzext.vf4 v16, v24
-; RV32-NEXT:    bltu a1, a3, .LBB92_2
+; RV32-NEXT:    bltu a1, a3, .LBB93_2
 ; RV32-NEXT:  # %bb.1:
 ; RV32-NEXT:    mv a2, a3
-; RV32-NEXT:  .LBB92_2:
+; RV32-NEXT:  .LBB93_2:
 ; RV32-NEXT:    vzext.vf4 v24, v8
 ; RV32-NEXT:    vsll.vi v16, v16, 3
 ; RV32-NEXT:    vsetvli zero, a2, e32, m4, ta, mu
 ; RV32-NEXT:    vncvt.x.x.w v8, v16
 ; RV32-NEXT:    vsetivli zero, 2, e8, mf4, ta, mu
 ; RV32-NEXT:    vslidedown.vi v0, v12, 2
 ; RV32-NEXT:    vsetvli zero, a2, e64, m8, ta, mu
 ; RV32-NEXT:    vluxei32.v v16, (a0), v8, v0.t
 ; RV32-NEXT:    li a2, 16
-; RV32-NEXT:    bltu a1, a2, .LBB92_4
+; RV32-NEXT:    bltu a1, a2, .LBB93_4
 ; RV32-NEXT:  # %bb.3:
 ; RV32-NEXT:    li a1, 16
-; RV32-NEXT:  .LBB92_4:
+; RV32-NEXT:  .LBB93_4:
 ; RV32-NEXT:    vsetivli zero, 16, e64, m8, ta, mu
 ; RV32-NEXT:    vsll.vi v24, v24, 3
 ; RV32-NEXT:    vsetvli zero, a1, e32, m4, ta, mu
 ; RV32-NEXT:    vncvt.x.x.w v4, v24
 ; RV32-NEXT:    vsetvli zero, zero, e64, m8, ta, mu
 ; RV32-NEXT:    vmv1r.v v0, v12
 ; RV32-NEXT:    vluxei32.v v8, (a0), v4, v0.t
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vpgather_baseidx_zext_v32i16_v32f64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vmv1r.v v12, v0
 ; RV64-NEXT:    li a2, 0
 ; RV64-NEXT:    vsetivli zero, 16, e16, m4, ta, mu
 ; RV64-NEXT:    vslidedown.vi v24, v8, 16
 ; RV64-NEXT:    vsetivli zero, 16, e64, m8, ta, mu
 ; RV64-NEXT:    addi a3, a1, -16
 ; RV64-NEXT:    vzext.vf4 v16, v24
-; RV64-NEXT:    bltu a1, a3, .LBB92_2
+; RV64-NEXT:    bltu a1, a3, .LBB93_2
 ; RV64-NEXT:  # %bb.1:
 ; RV64-NEXT:    mv a2, a3
-; RV64-NEXT:  .LBB92_2:
+; RV64-NEXT:  .LBB93_2:
 ; RV64-NEXT:    vzext.vf4 v24, v8
 ; RV64-NEXT:    vsetivli zero, 2, e8, mf4, ta, mu
 ; RV64-NEXT:    vslidedown.vi v0, v12, 2
 ; RV64-NEXT:    vsetivli zero, 16, e64, m8, ta, mu
 ; RV64-NEXT:    vsll.vi v16, v16, 3
 ; RV64-NEXT:    vsetvli zero, a2, e64, m8, ta, mu
 ; RV64-NEXT:    vluxei64.v v16, (a0), v16, v0.t
 ; RV64-NEXT:    li a2, 16
-; RV64-NEXT:    bltu a1, a2, .LBB92_4
+; RV64-NEXT:    bltu a1, a2, .LBB93_4
 ; RV64-NEXT:  # %bb.3:
 ; RV64-NEXT:    li a1, 16
-; RV64-NEXT:  .LBB92_4:
+; RV64-NEXT:  .LBB93_4:
 ; RV64-NEXT:    vsetivli zero, 16, e64, m8, ta, mu
 ; RV64-NEXT:    vsll.vi v24, v24, 3
 ; RV64-NEXT:    vsetvli zero, a1, e64, m8, ta, mu
 ; RV64-NEXT:    vmv1r.v v0, v12
 ; RV64-NEXT:    vluxei64.v v8, (a0), v24, v0.t
 ; RV64-NEXT:    ret
   %eidxs = zext <32 x i16> %idxs to <32 x i64>
   %ptrs = getelementptr inbounds double, double* %base, <32 x i64> %eidxs
   %v = call <32 x double> @llvm.vp.gather.v32f64.v32p0f64(<32 x double*> %ptrs, <32 x i1> %m, i32 %evl)
   ret <32 x double> %v
 }
 
 define <32 x double> @vpgather_baseidx_v32i32_v32f64(double* %base, <32 x i32> %idxs, <32 x i1> %m, i32 zeroext %evl) {
 ; RV32-LABEL: vpgather_baseidx_v32i32_v32f64:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    li a3, 16
 ; RV32-NEXT:    mv a2, a1
-; RV32-NEXT:    bltu a1, a3, .LBB93_2
+; RV32-NEXT:    bltu a1, a3, .LBB94_2
 ; RV32-NEXT:  # %bb.1:
 ; RV32-NEXT:    li a2, 16
-; RV32-NEXT:  .LBB93_2:
+; RV32-NEXT:  .LBB94_2:
 ; RV32-NEXT:    li a3, 32
 ; RV32-NEXT:    vsetvli zero, a3, e32, m8, ta, mu
 ; RV32-NEXT:    vsll.vi v16, v8, 3
 ; RV32-NEXT:    vsetvli zero, a2, e64, m8, ta, mu
 ; RV32-NEXT:    vluxei32.v v8, (a0), v16, v0.t
 ; RV32-NEXT:    addi a3, a1, -16
 ; RV32-NEXT:    li a2, 0
-; RV32-NEXT:    bltu a1, a3, .LBB93_4
+; RV32-NEXT:    bltu a1, a3, .LBB94_4
 ; RV32-NEXT:  # %bb.3:
 ; RV32-NEXT:    mv a2, a3
-; RV32-NEXT:  .LBB93_4:
+; RV32-NEXT:  .LBB94_4:
 ; RV32-NEXT:    vsetivli zero, 16, e32, m8, ta, mu
 ; RV32-NEXT:    vslidedown.vi v24, v16, 16
 ; RV32-NEXT:    vsetivli zero, 2, e8, mf4, ta, mu
 ; RV32-NEXT:    vslidedown.vi v0, v0, 2
 ; RV32-NEXT:    vsetvli zero, a2, e64, m8, ta, mu
 ; RV32-NEXT:    vluxei32.v v16, (a0), v24, v0.t
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vpgather_baseidx_v32i32_v32f64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    addi a3, a1, -16
 ; RV64-NEXT:    vmv1r.v v1, v0
 ; RV64-NEXT:    li a2, 0
-; RV64-NEXT:    bltu a1, a3, .LBB93_2
+; RV64-NEXT:    bltu a1, a3, .LBB94_2
 ; RV64-NEXT:  # %bb.1:
 ; RV64-NEXT:    mv a2, a3
-; RV64-NEXT:  .LBB93_2:
+; RV64-NEXT:  .LBB94_2:
 ; RV64-NEXT:    vsetivli zero, 2, e8, mf4, ta, mu
 ; RV64-NEXT:    vslidedown.vi v0, v1, 2
 ; RV64-NEXT:    vsetivli zero, 16, e32, m8, ta, mu
 ; RV64-NEXT:    vslidedown.vi v16, v8, 16
 ; RV64-NEXT:    vsetivli zero, 16, e64, m8, ta, mu
 ; RV64-NEXT:    vsext.vf2 v24, v16
 ; RV64-NEXT:    vsll.vi v16, v24, 3
 ; RV64-NEXT:    vsetvli zero, a2, e64, m8, ta, mu
 ; RV64-NEXT:    vluxei64.v v16, (a0), v16, v0.t
 ; RV64-NEXT:    li a2, 16
-; RV64-NEXT:    bltu a1, a2, .LBB93_4
+; RV64-NEXT:    bltu a1, a2, .LBB94_4
 ; RV64-NEXT:  # %bb.3:
 ; RV64-NEXT:    li a1, 16
-; RV64-NEXT:  .LBB93_4:
+; RV64-NEXT:  .LBB94_4:
 ; RV64-NEXT:    vsetivli zero, 16, e64, m8, ta, mu
 ; RV64-NEXT:    vsext.vf2 v24, v8
 ; RV64-NEXT:    vsll.vi v8, v24, 3
 ; RV64-NEXT:    vsetvli zero, a1, e64, m8, ta, mu
 ; RV64-NEXT:    vmv1r.v v0, v1
 ; RV64-NEXT:    vluxei64.v v8, (a0), v8, v0.t
 ; RV64-NEXT:    ret
   %ptrs = getelementptr inbounds double, double* %base, <32 x i32> %idxs
   %v = call <32 x double> @llvm.vp.gather.v32f64.v32p0f64(<32 x double*> %ptrs, <32 x i1> %m, i32 %evl)
   ret <32 x double> %v
 }
 
 define <32 x double> @vpgather_baseidx_sext_v32i32_v32f64(double* %base, <32 x i32> %idxs, <32 x i1> %m, i32 zeroext %evl) {
 ; RV32-LABEL: vpgather_baseidx_sext_v32i32_v32f64:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    vmv1r.v v1, v0
 ; RV32-NEXT:    li a2, 0
 ; RV32-NEXT:    vsetivli zero, 16, e32, m8, ta, mu
 ; RV32-NEXT:    vslidedown.vi v24, v8, 16
 ; RV32-NEXT:    vsetivli zero, 16, e64, m8, ta, mu
 ; RV32-NEXT:    addi a3, a1, -16
 ; RV32-NEXT:    vsext.vf2 v16, v24
-; RV32-NEXT:    bltu a1, a3, .LBB94_2
+; RV32-NEXT:    bltu a1, a3, .LBB95_2
 ; RV32-NEXT:  # %bb.1:
 ; RV32-NEXT:    mv a2, a3
-; RV32-NEXT:  .LBB94_2:
+; RV32-NEXT:  .LBB95_2:
 ; RV32-NEXT:    vsext.vf2 v24, v8
 ; RV32-NEXT:    vsll.vi v8, v16, 3
 ; RV32-NEXT:    vsetvli zero, a2, e32, m4, ta, mu
 ; RV32-NEXT:    vncvt.x.x.w v4, v8
 ; RV32-NEXT:    vsetivli zero, 2, e8, mf4, ta, mu
 ; RV32-NEXT:    vslidedown.vi v0, v1, 2
 ; RV32-NEXT:    vsetvli zero, a2, e64, m8, ta, mu
 ; RV32-NEXT:    vluxei32.v v16, (a0), v4, v0.t
 ; RV32-NEXT:    li a2, 16
-; RV32-NEXT:    bltu a1, a2, .LBB94_4
+; RV32-NEXT:    bltu a1, a2, .LBB95_4
 ; RV32-NEXT:  # %bb.3:
 ; RV32-NEXT:    li a1, 16
-; RV32-NEXT:  .LBB94_4:
+; RV32-NEXT:  .LBB95_4:
 ; RV32-NEXT:    vsetivli zero, 16, e64, m8, ta, mu
 ; RV32-NEXT:    vsll.vi v8, v24, 3
 ; RV32-NEXT:    vsetvli zero, a1, e32, m4, ta, mu
 ; RV32-NEXT:    vncvt.x.x.w v24, v8
 ; RV32-NEXT:    vsetvli zero, zero, e64, m8, ta, mu
 ; RV32-NEXT:    vmv1r.v v0, v1
 ; RV32-NEXT:    vluxei32.v v8, (a0), v24, v0.t
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vpgather_baseidx_sext_v32i32_v32f64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vmv1r.v v1, v0
 ; RV64-NEXT:    li a2, 0
 ; RV64-NEXT:    vsetivli zero, 16, e32, m8, ta, mu
 ; RV64-NEXT:    vslidedown.vi v24, v8, 16
 ; RV64-NEXT:    vsetivli zero, 16, e64, m8, ta, mu
 ; RV64-NEXT:    addi a3, a1, -16
 ; RV64-NEXT:    vsext.vf2 v16, v24
-; RV64-NEXT:    bltu a1, a3, .LBB94_2
+; RV64-NEXT:    bltu a1, a3, .LBB95_2
 ; RV64-NEXT:  # %bb.1:
 ; RV64-NEXT:    mv a2, a3
-; RV64-NEXT:  .LBB94_2:
+; RV64-NEXT:  .LBB95_2:
 ; RV64-NEXT:    vsext.vf2 v24, v8
 ; RV64-NEXT:    vsetivli zero, 2, e8, mf4, ta, mu
 ; RV64-NEXT:    vslidedown.vi v0, v1, 2
 ; RV64-NEXT:    vsetivli zero, 16, e64, m8, ta, mu
 ; RV64-NEXT:    vsll.vi v8, v16, 3
 ; RV64-NEXT:    vsetvli zero, a2, e64, m8, ta, mu
 ; RV64-NEXT:    vluxei64.v v16, (a0), v8, v0.t
 ; RV64-NEXT:    li a2, 16
-; RV64-NEXT:    bltu a1, a2, .LBB94_4
+; RV64-NEXT:    bltu a1, a2, .LBB95_4
 ; RV64-NEXT:  # %bb.3:
 ; RV64-NEXT:    li a1, 16
-; RV64-NEXT:  .LBB94_4:
+; RV64-NEXT:  .LBB95_4:
 ; RV64-NEXT:    vsetivli zero, 16, e64, m8, ta, mu
 ; RV64-NEXT:    vsll.vi v8, v24, 3
 ; RV64-NEXT:    vsetvli zero, a1, e64, m8, ta, mu
 ; RV64-NEXT:    vmv1r.v v0, v1
 ; RV64-NEXT:    vluxei64.v v8, (a0), v8, v0.t
 ; RV64-NEXT:    ret
   %eidxs = sext <32 x i32> %idxs to <32 x i64>
   %ptrs = getelementptr inbounds double, double* %base, <32 x i64> %eidxs
   %v = call <32 x double> @llvm.vp.gather.v32f64.v32p0f64(<32 x double*> %ptrs, <32 x i1> %m, i32 %evl)
   ret <32 x double> %v
 }
 
 define <32 x double> @vpgather_baseidx_zext_v32i32_v32f64(double* %base, <32 x i32> %idxs, <32 x i1> %m, i32 zeroext %evl) {
 ; RV32-LABEL: vpgather_baseidx_zext_v32i32_v32f64:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    vmv1r.v v1, v0
 ; RV32-NEXT:    li a2, 0
 ; RV32-NEXT:    vsetivli zero, 16, e32, m8, ta, mu
 ; RV32-NEXT:    vslidedown.vi v24, v8, 16
 ; RV32-NEXT:    vsetivli zero, 16, e64, m8, ta, mu
 ; RV32-NEXT:    addi a3, a1, -16
 ; RV32-NEXT:    vzext.vf2 v16, v24
-; RV32-NEXT:    bltu a1, a3, .LBB95_2
+; RV32-NEXT:    bltu a1, a3, .LBB96_2
 ; RV32-NEXT:  # %bb.1:
 ; RV32-NEXT:    mv a2, a3
-; RV32-NEXT:  .LBB95_2:
+; RV32-NEXT:  .LBB96_2:
 ; RV32-NEXT:    vzext.vf2 v24, v8
 ; RV32-NEXT:    vsll.vi v8, v16, 3
 ; RV32-NEXT:    vsetvli zero, a2, e32, m4, ta, mu
 ; RV32-NEXT:    vncvt.x.x.w v4, v8
 ; RV32-NEXT:    vsetivli zero, 2, e8, mf4, ta, mu
 ; RV32-NEXT:    vslidedown.vi v0, v1, 2
 ; RV32-NEXT:    vsetvli zero, a2, e64, m8, ta, mu
 ; RV32-NEXT:    vluxei32.v v16, (a0), v4, v0.t
 ; RV32-NEXT:    li a2, 16
-; RV32-NEXT:    bltu a1, a2, .LBB95_4
+; RV32-NEXT:    bltu a1, a2, .LBB96_4
 ; RV32-NEXT:  # %bb.3:
 ; RV32-NEXT:    li a1, 16
-; RV32-NEXT:  .LBB95_4:
+; RV32-NEXT:  .LBB96_4:
 ; RV32-NEXT:    vsetivli zero, 16, e64, m8, ta, mu
 ; RV32-NEXT:    vsll.vi v8, v24, 3
 ; RV32-NEXT:    vsetvli zero, a1, e32, m4, ta, mu
 ; RV32-NEXT:    vncvt.x.x.w v24, v8
 ; RV32-NEXT:    vsetvli zero, zero, e64, m8, ta, mu
 ; RV32-NEXT:    vmv1r.v v0, v1
 ; RV32-NEXT:    vluxei32.v v8, (a0), v24, v0.t
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vpgather_baseidx_zext_v32i32_v32f64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vmv1r.v v1, v0
 ; RV64-NEXT:    li a2, 0
 ; RV64-NEXT:    vsetivli zero, 16, e32, m8, ta, mu
 ; RV64-NEXT:    vslidedown.vi v24, v8, 16
 ; RV64-NEXT:    vsetivli zero, 16, e64, m8, ta, mu
 ; RV64-NEXT:    addi a3, a1, -16
 ; RV64-NEXT:    vzext.vf2 v16, v24
-; RV64-NEXT:    bltu a1, a3, .LBB95_2
+; RV64-NEXT:    bltu a1, a3, .LBB96_2
 ; RV64-NEXT:  # %bb.1:
 ; RV64-NEXT:    mv a2, a3
-; RV64-NEXT:  .LBB95_2:
+; RV64-NEXT:  .LBB96_2:
 ; RV64-NEXT:    vzext.vf2 v24, v8
 ; RV64-NEXT:    vsetivli zero, 2, e8, mf4, ta, mu
 ; RV64-NEXT:    vslidedown.vi v0, v1, 2
 ; RV64-NEXT:    vsetivli zero, 16, e64, m8, ta, mu
 ; RV64-NEXT:    vsll.vi v8, v16, 3
 ; RV64-NEXT:    vsetvli zero, a2, e64, m8, ta, mu
 ; RV64-NEXT:    vluxei64.v v16, (a0), v8, v0.t
 ; RV64-NEXT:    li a2, 16
-; RV64-NEXT:    bltu a1, a2, .LBB95_4
+; RV64-NEXT:    bltu a1, a2, .LBB96_4
 ; RV64-NEXT:  # %bb.3:
 ; RV64-NEXT:    li a1, 16
-; RV64-NEXT:  .LBB95_4:
+; RV64-NEXT:  .LBB96_4:
 ; RV64-NEXT:    vsetivli zero, 16, e64, m8, ta, mu
 ; RV64-NEXT:    vsll.vi v8, v24, 3
 ; RV64-NEXT:    vsetvli zero, a1, e64, m8, ta, mu
 ; RV64-NEXT:    vmv1r.v v0, v1
 ; RV64-NEXT:    vluxei64.v v8, (a0), v8, v0.t
 ; RV64-NEXT:    ret
   %eidxs = zext <32 x i32> %idxs to <32 x i64>
   %ptrs = getelementptr inbounds double, double* %base, <32 x i64> %eidxs
   %v = call <32 x double> @llvm.vp.gather.v32f64.v32p0f64(<32 x double*> %ptrs, <32 x i1> %m, i32 %evl)
   ret <32 x double> %v
 }
 
 define <32 x double> @vpgather_baseidx_v32f64(double* %base, <32 x i64> %idxs, <32 x i1> %m, i32 zeroext %evl) {
 ; RV32-LABEL: vpgather_baseidx_v32f64:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    addi a3, a1, -16
 ; RV32-NEXT:    vmv1r.v v24, v0
 ; RV32-NEXT:    li a2, 0
-; RV32-NEXT:    bltu a1, a3, .LBB96_2
+; RV32-NEXT:    bltu a1, a3, .LBB97_2
 ; RV32-NEXT:  # %bb.1:
 ; RV32-NEXT:    mv a2, a3
-; RV32-NEXT:  .LBB96_2:
+; RV32-NEXT:  .LBB97_2:
 ; RV32-NEXT:    vsetivli zero, 16, e64, m8, ta, mu
 ; RV32-NEXT:    vsll.vi v16, v16, 3
 ; RV32-NEXT:    vsetvli zero, a2, e32, m4, ta, mu
 ; RV32-NEXT:    vncvt.x.x.w v28, v16
 ; RV32-NEXT:    vsetivli zero, 2, e8, mf4, ta, mu
 ; RV32-NEXT:    vslidedown.vi v0, v24, 2
 ; RV32-NEXT:    vsetvli zero, a2, e64, m8, ta, mu
 ; RV32-NEXT:    vluxei32.v v16, (a0), v28, v0.t
 ; RV32-NEXT:    li a2, 16
-; RV32-NEXT:    bltu a1, a2, .LBB96_4
+; RV32-NEXT:    bltu a1, a2, .LBB97_4
 ; RV32-NEXT:  # %bb.3:
 ; RV32-NEXT:    li a1, 16
-; RV32-NEXT:  .LBB96_4:
+; RV32-NEXT:  .LBB97_4:
 ; RV32-NEXT:    vsetivli zero, 16, e64, m8, ta, mu
 ; RV32-NEXT:    vsll.vi v8, v8, 3
 ; RV32-NEXT:    vsetvli zero, a1, e32, m4, ta, mu
 ; RV32-NEXT:    vncvt.x.x.w v28, v8
 ; RV32-NEXT:    vsetvli zero, zero, e64, m8, ta, mu
 ; RV32-NEXT:    vmv1r.v v0, v24
 ; RV32-NEXT:    vluxei32.v v8, (a0), v28, v0.t
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vpgather_baseidx_v32f64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    addi a3, a1, -16
 ; RV64-NEXT:    vmv1r.v v24, v0
 ; RV64-NEXT:    li a2, 0
-; RV64-NEXT:    bltu a1, a3, .LBB96_2
+; RV64-NEXT:    bltu a1, a3, .LBB97_2
 ; RV64-NEXT:  # %bb.1:
 ; RV64-NEXT:    mv a2, a3
-; RV64-NEXT:  .LBB96_2:
+; RV64-NEXT:  .LBB97_2:
 ; RV64-NEXT:    vsetivli zero, 2, e8, mf4, ta, mu
 ; RV64-NEXT:    vslidedown.vi v0, v24, 2
 ; RV64-NEXT:    vsetivli zero, 16, e64, m8, ta, mu
 ; RV64-NEXT:    vsll.vi v16, v16, 3
 ; RV64-NEXT:    vsetvli zero, a2, e64, m8, ta, mu
 ; RV64-NEXT:    vluxei64.v v16, (a0), v16, v0.t
 ; RV64-NEXT:    li a2, 16
-; RV64-NEXT:    bltu a1, a2, .LBB96_4
+; RV64-NEXT:    bltu a1, a2, .LBB97_4
 ; RV64-NEXT:  # %bb.3:
 ; RV64-NEXT:    li a1, 16
-; RV64-NEXT:  .LBB96_4:
+; RV64-NEXT:  .LBB97_4:
 ; RV64-NEXT:    vsetivli zero, 16, e64, m8, ta, mu
 ; RV64-NEXT:    vsll.vi v8, v8, 3
 ; RV64-NEXT:    vsetvli zero, a1, e64, m8, ta, mu
 ; RV64-NEXT:    vmv1r.v v0, v24
 ; RV64-NEXT:    vluxei64.v v8, (a0), v8, v0.t
 ; RV64-NEXT:    ret
   %ptrs = getelementptr inbounds double, double* %base, <32 x i64> %idxs
   %v = call <32 x double> @llvm.vp.gather.v32f64.v32p0f64(<32 x double*> %ptrs, <32 x i1> %m, i32 %evl)
   ret <32 x double> %v
 }

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpscatter.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+experimental-zvfh,+v,+m -riscv-v-vector-bits-min=128 \
 ; RUN:   -verify-machineinstrs < %s | FileCheck %s --check-prefixes=RV32
 ; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+experimental-zvfh,+v,+m -riscv-v-vector-bits-min=128 \
 ; RUN:   -verify-machineinstrs < %s | FileCheck %s --check-prefixes=RV64
 
+declare void @llvm.vp.scatter.v2i7.v2p0i7(<2 x i7>, <2 x i7*>, <2 x i1>, i32)
+
+define void @vpscatter_v2i7(<2 x i7> %val, <2 x i7*> %ptrs, <2 x i1> %m, i32 zeroext %evl) {
+; RV32-LABEL: vpscatter_v2i7:
+; RV32:       # %bb.0:
+; RV32-NEXT:    vsetvli zero, a0, e8, mf8, ta, mu
+; RV32-NEXT:    vsoxei32.v v8, (zero), v9, v0.t
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vpscatter_v2i7:
+; RV64:       # %bb.0:
+; RV64-NEXT:    vsetvli zero, a0, e8, mf8, ta, mu
+; RV64-NEXT:    vsoxei64.v v8, (zero), v9, v0.t
+; RV64-NEXT:    ret
+  call void @llvm.vp.scatter.v2i7.v2p0i7(<2 x i7> %val, <2 x i7*> %ptrs, <2 x i1> %m, i32 %evl)
+  ret void
+}
+
 declare void @llvm.vp.scatter.v2i8.v2p0i8(<2 x i8>, <2 x i8*>, <2 x i1>, i32)
 
 define void @vpscatter_v2i8(<2 x i8> %val, <2 x i8*> %ptrs, <2 x i1> %m, i32 zeroext %evl) {
 ; RV32-LABEL: vpscatter_v2i8:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    vsetvli zero, a0, e8, mf8, ta, mu
 ; RV32-NEXT:    vsoxei32.v v8, (zero), v9, v0.t
 ; RV32-NEXT:    ret

 define void @vpscatter_v32f64(<32 x double> %val, <32 x double*> %ptrs, <32 x i1> %m, i32 zeroext %evl) {
 ; RV32-LABEL: vpscatter_v32f64:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    li a2, 32
 ; RV32-NEXT:    vsetvli zero, a2, e32, m8, ta, mu
 ; RV32-NEXT:    vle32.v v24, (a0)
 ; RV32-NEXT:    li a0, 16
 ; RV32-NEXT:    mv a2, a1
-; RV32-NEXT:    bltu a1, a0, .LBB79_2
+; RV32-NEXT:    bltu a1, a0, .LBB80_2
 ; RV32-NEXT:  # %bb.1:
 ; RV32-NEXT:    li a2, 16
-; RV32-NEXT:  .LBB79_2:
+; RV32-NEXT:  .LBB80_2:
 ; RV32-NEXT:    li a0, 0
 ; RV32-NEXT:    vsetvli zero, a2, e64, m8, ta, mu
 ; RV32-NEXT:    addi a2, a1, -16
 ; RV32-NEXT:    vsoxei32.v v8, (zero), v24, v0.t
-; RV32-NEXT:    bltu a1, a2, .LBB79_4
+; RV32-NEXT:    bltu a1, a2, .LBB80_4
 ; RV32-NEXT:  # %bb.3:
 ; RV32-NEXT:    mv a0, a2
-; RV32-NEXT:  .LBB79_4:
+; RV32-NEXT:  .LBB80_4:
 ; RV32-NEXT:    vsetivli zero, 16, e32, m8, ta, mu
 ; RV32-NEXT:    vslidedown.vi v8, v24, 16
 ; RV32-NEXT:    vsetivli zero, 2, e8, mf4, ta, mu
 ; RV32-NEXT:    vslidedown.vi v0, v0, 2
 ; RV32-NEXT:    vsetvli zero, a0, e64, m8, ta, mu
 ; RV32-NEXT:    vsoxei32.v v16, (zero), v8, v0.t
 ; RV32-NEXT:    ret
 ;

 ; RV64-NEXT:    add a1, sp, a1
 ; RV64-NEXT:    addi a1, a1, 16
 ; RV64-NEXT:    vs8r.v v24, (a1) # Unknown-size Folded Spill
 ; RV64-NEXT:    addi a1, sp, 16
 ; RV64-NEXT:    vs8r.v v16, (a1) # Unknown-size Folded Spill
 ; RV64-NEXT:    li a3, 16
 ; RV64-NEXT:    addi a0, a0, 128
 ; RV64-NEXT:    mv a1, a2
-; RV64-NEXT:    bltu a2, a3, .LBB79_2
+; RV64-NEXT:    bltu a2, a3, .LBB80_2
 ; RV64-NEXT:  # %bb.1:
 ; RV64-NEXT:    li a1, 16
-; RV64-NEXT:  .LBB79_2:
+; RV64-NEXT:  .LBB80_2:
 ; RV64-NEXT:    li a3, 0
 ; RV64-NEXT:    vle64.v v16, (a0)
 ; RV64-NEXT:    vsetvli zero, a1, e64, m8, ta, mu
 ; RV64-NEXT:    addi a0, a2, -16
 ; RV64-NEXT:    csrr a1, vlenb
 ; RV64-NEXT:    slli a1, a1, 3
 ; RV64-NEXT:    add a1, sp, a1
 ; RV64-NEXT:    addi a1, a1, 16
 ; RV64-NEXT:    vl8re8.v v24, (a1) # Unknown-size Folded Reload
 ; RV64-NEXT:    vsoxei64.v v8, (zero), v24, v0.t
-; RV64-NEXT:    bltu a2, a0, .LBB79_4
+; RV64-NEXT:    bltu a2, a0, .LBB80_4
 ; RV64-NEXT:  # %bb.3:
 ; RV64-NEXT:    mv a3, a0
-; RV64-NEXT:  .LBB79_4:
+; RV64-NEXT:  .LBB80_4:
 ; RV64-NEXT:    vsetivli zero, 2, e8, mf4, ta, mu
 ; RV64-NEXT:    vslidedown.vi v0, v0, 2
 ; RV64-NEXT:    vsetvli zero, a3, e64, m8, ta, mu
 ; RV64-NEXT:    addi a0, sp, 16
 ; RV64-NEXT:    vl8re8.v v8, (a0) # Unknown-size Folded Reload
 ; RV64-NEXT:    vsoxei64.v v8, (zero), v16, v0.t
 ; RV64-NEXT:    csrr a0, vlenb
 ; RV64-NEXT:    slli a0, a0, 4
 ; RV64-NEXT:    add sp, sp, a0
 ; RV64-NEXT:    addi sp, sp, 16
 ; RV64-NEXT:    ret
   call void @llvm.vp.scatter.v32f64.v32p0f64(<32 x double> %val, <32 x double*> %ptrs, <32 x i1> %m, i32 %evl)
   ret void
 }
 
 define void @vpscatter_baseidx_v32i32_v32f64(<32 x double> %val, double* %base, <32 x i32> %idxs, <32 x i1> %m, i32 zeroext %evl) {
 ; RV32-LABEL: vpscatter_baseidx_v32i32_v32f64:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    li a3, 32
 ; RV32-NEXT:    vsetvli zero, a3, e32, m8, ta, mu
 ; RV32-NEXT:    vle32.v v24, (a1)
 ; RV32-NEXT:    li a3, 16
 ; RV32-NEXT:    mv a1, a2
-; RV32-NEXT:    bltu a2, a3, .LBB80_2
+; RV32-NEXT:    bltu a2, a3, .LBB81_2
 ; RV32-NEXT:  # %bb.1:
 ; RV32-NEXT:    li a1, 16
-; RV32-NEXT:  .LBB80_2:
+; RV32-NEXT:  .LBB81_2:
 ; RV32-NEXT:    li a3, 0
 ; RV32-NEXT:    vsll.vi v24, v24, 3
 ; RV32-NEXT:    vsetvli zero, a1, e64, m8, ta, mu
 ; RV32-NEXT:    addi a1, a2, -16
 ; RV32-NEXT:    vsoxei32.v v8, (a0), v24, v0.t
-; RV32-NEXT:    bltu a2, a1, .LBB80_4
+; RV32-NEXT:    bltu a2, a1, .LBB81_4
 ; RV32-NEXT:  # %bb.3:
 ; RV32-NEXT:    mv a3, a1
-; RV32-NEXT:  .LBB80_4:
+; RV32-NEXT:  .LBB81_4:
 ; RV32-NEXT:    vsetivli zero, 2, e8, mf4, ta, mu
 ; RV32-NEXT:    vslidedown.vi v0, v0, 2
 ; RV32-NEXT:    vsetivli zero, 16, e32, m8, ta, mu
 ; RV32-NEXT:    vslidedown.vi v8, v24, 16
 ; RV32-NEXT:    vsetvli zero, a3, e64, m8, ta, mu
 ; RV32-NEXT:    vsoxei32.v v16, (a0), v8, v0.t
 ; RV32-NEXT:    ret
 ;

 ; RV64-NEXT:    csrr a1, vlenb
 ; RV64-NEXT:    add a1, sp, a1
 ; RV64-NEXT:    addi a1, a1, 16
 ; RV64-NEXT:    vs8r.v v24, (a1) # Unknown-size Folded Spill
 ; RV64-NEXT:    li a1, 16
 ; RV64-NEXT:    addi a3, sp, 16
 ; RV64-NEXT:    vs1r.v v0, (a3) # Unknown-size Folded Spill
 ; RV64-NEXT:    mv a3, a2
-; RV64-NEXT:    bltu a2, a1, .LBB80_2
+; RV64-NEXT:    bltu a2, a1, .LBB81_2
 ; RV64-NEXT:  # %bb.1:
 ; RV64-NEXT:    li a3, 16
-; RV64-NEXT:  .LBB80_2:
+; RV64-NEXT:  .LBB81_2:
 ; RV64-NEXT:    li a1, 0
 ; RV64-NEXT:    vsetivli zero, 16, e64, m8, ta, mu
 ; RV64-NEXT:    csrr a4, vlenb
 ; RV64-NEXT:    add a4, sp, a4
 ; RV64-NEXT:    addi a4, a4, 16
 ; RV64-NEXT:    vl8re8.v v0, (a4) # Unknown-size Folded Reload
 ; RV64-NEXT:    vsext.vf2 v24, v0
 ; RV64-NEXT:    vsll.vi v24, v24, 3
 ; RV64-NEXT:    vsetvli zero, a3, e64, m8, ta, mu
 ; RV64-NEXT:    addi a3, a2, -16
 ; RV64-NEXT:    addi a4, sp, 16
 ; RV64-NEXT:    vl1r.v v0, (a4) # Unknown-size Folded Reload
 ; RV64-NEXT:    vsoxei64.v v8, (a0), v24, v0.t
-; RV64-NEXT:    bltu a2, a3, .LBB80_4
+; RV64-NEXT:    bltu a2, a3, .LBB81_4
 ; RV64-NEXT:  # %bb.3:
 ; RV64-NEXT:    mv a1, a3
-; RV64-NEXT:  .LBB80_4:
+; RV64-NEXT:  .LBB81_4:
 ; RV64-NEXT:    vsetivli zero, 2, e8, mf4, ta, mu
 ; RV64-NEXT:    vslidedown.vi v0, v0, 2
 ; RV64-NEXT:    vsetivli zero, 16, e32, m8, ta, mu
 ; RV64-NEXT:    csrr a2, vlenb
 ; RV64-NEXT:    add a2, sp, a2
 ; RV64-NEXT:    addi a2, a2, 16
 ; RV64-NEXT:    vl8re8.v v8, (a2) # Unknown-size Folded Reload
 ; RV64-NEXT:    vslidedown.vi v8, v8, 16

 ; RV32-NEXT:    addi a1, sp, 16
 ; RV32-NEXT:    vs8r.v v8, (a1) # Unknown-size Folded Spill
 ; RV32-NEXT:    vsetivli zero, 16, e32, m8, ta, mu
 ; RV32-NEXT:    vslidedown.vi v8, v24, 16
 ; RV32-NEXT:    vsetivli zero, 16, e64, m8, ta, mu
 ; RV32-NEXT:    li a3, 16
 ; RV32-NEXT:    vsext.vf2 v16, v24
 ; RV32-NEXT:    mv a1, a2
-; RV32-NEXT:    bltu a2, a3, .LBB81_2
+; RV32-NEXT:    bltu a2, a3, .LBB82_2
 ; RV32-NEXT:  # %bb.1:
 ; RV32-NEXT:    li a1, 16
-; RV32-NEXT:  .LBB81_2:
+; RV32-NEXT:  .LBB82_2:
 ; RV32-NEXT:    li a3, 0
 ; RV32-NEXT:    vsext.vf2 v24, v8
 ; RV32-NEXT:    vsll.vi v8, v16, 3
 ; RV32-NEXT:    vsetvli zero, a1, e32, m4, ta, mu
 ; RV32-NEXT:    vncvt.x.x.w v16, v8
 ; RV32-NEXT:    vsetvli zero, zero, e64, m8, ta, mu
 ; RV32-NEXT:    addi a1, a2, -16
 ; RV32-NEXT:    addi a4, sp, 16
 ; RV32-NEXT:    vl8re8.v v8, (a4) # Unknown-size Folded Reload
 ; RV32-NEXT:    vsoxei32.v v8, (a0), v16, v0.t
-; RV32-NEXT:    bltu a2, a1, .LBB81_4
+; RV32-NEXT:    bltu a2, a1, .LBB82_4
 ; RV32-NEXT:  # %bb.3:
 ; RV32-NEXT:    mv a3, a1
-; RV32-NEXT:  .LBB81_4:
+; RV32-NEXT:  .LBB82_4:
 ; RV32-NEXT:    vsetivli zero, 16, e64, m8, ta, mu
 ; RV32-NEXT:    vsll.vi v8, v24, 3
 ; RV32-NEXT:    vsetvli zero, a3, e32, m4, ta, mu
 ; RV32-NEXT:    vncvt.x.x.w v16, v8
 ; RV32-NEXT:    vsetivli zero, 2, e8, mf4, ta, mu
 ; RV32-NEXT:    vslidedown.vi v0, v0, 2
 ; RV32-NEXT:    vsetvli zero, a3, e64, m8, ta, mu
 ; RV32-NEXT:    csrr a1, vlenb

 ; RV64-NEXT:    vsetivli zero, 16, e32, m8, ta, mu
 ; RV64-NEXT:    vslidedown.vi v8, v24, 16
 ; RV64-NEXT:    addi a1, sp, 16
 ; RV64-NEXT:    vs8r.v v8, (a1) # Unknown-size Folded Spill
 ; RV64-NEXT:    vsetivli zero, 16, e64, m8, ta, mu
 ; RV64-NEXT:    li a3, 16
 ; RV64-NEXT:    vsext.vf2 v8, v24
 ; RV64-NEXT:    mv a1, a2
-; RV64-NEXT:    bltu a2, a3, .LBB81_2
+; RV64-NEXT:    bltu a2, a3, .LBB82_2
 ; RV64-NEXT:  # %bb.1:
 ; RV64-NEXT:    li a1, 16
-; RV64-NEXT:  .LBB81_2:
+; RV64-NEXT:  .LBB82_2:
 ; RV64-NEXT:    li a3, 0
 ; RV64-NEXT:    addi a4, sp, 16
 ; RV64-NEXT:    vl8re8.v v24, (a4) # Unknown-size Folded Reload
 ; RV64-NEXT:    vsext.vf2 v16, v24
 ; RV64-NEXT:    vsll.vi v8, v8, 3
 ; RV64-NEXT:    vsetvli zero, a1, e64, m8, ta, mu
 ; RV64-NEXT:    addi a1, a2, -16
 ; RV64-NEXT:    csrr a4, vlenb
 ; RV64-NEXT:    slli a4, a4, 3
 ; RV64-NEXT:    add a4, sp, a4
 ; RV64-NEXT:    addi a4, a4, 16
 ; RV64-NEXT:    vl8re8.v v24, (a4) # Unknown-size Folded Reload
 ; RV64-NEXT:    vsoxei64.v v24, (a0), v8, v0.t
-; RV64-NEXT:    bltu a2, a1, .LBB81_4
+; RV64-NEXT:    bltu a2, a1, .LBB82_4
 ; RV64-NEXT:  # %bb.3:
 ; RV64-NEXT:    mv a3, a1
-; RV64-NEXT:  .LBB81_4:
+; RV64-NEXT:  .LBB82_4:
 ; RV64-NEXT:    vsetivli zero, 2, e8, mf4, ta, mu
 ; RV64-NEXT:    vslidedown.vi v0, v0, 2
 ; RV64-NEXT:    vsetivli zero, 16, e64, m8, ta, mu
 ; RV64-NEXT:    vsll.vi v8, v16, 3
 ; RV64-NEXT:    vsetvli zero, a3, e64, m8, ta, mu
 ; RV64-NEXT:    csrr a1, vlenb
 ; RV64-NEXT:    slli a1, a1, 4
 ; RV64-NEXT:    add a1, sp, a1

 ; RV32-NEXT:    addi a1, sp, 16
 ; RV32-NEXT:    vs8r.v v8, (a1) # Unknown-size Folded Spill
 ; RV32-NEXT:    vsetivli zero, 16, e32, m8, ta, mu
 ; RV32-NEXT:    vslidedown.vi v8, v24, 16
 ; RV32-NEXT:    vsetivli zero, 16, e64, m8, ta, mu
 ; RV32-NEXT:    li a3, 16
 ; RV32-NEXT:    vzext.vf2 v16, v24
 ; RV32-NEXT:    mv a1, a2
-; RV32-NEXT:    bltu a2, a3, .LBB82_2
+; RV32-NEXT:    bltu a2, a3, .LBB83_2
 ; RV32-NEXT:  # %bb.1:
 ; RV32-NEXT:    li a1, 16
-; RV32-NEXT:  .LBB82_2:
+; RV32-NEXT:  .LBB83_2:
 ; RV32-NEXT:    li a3, 0
 ; RV32-NEXT:    vzext.vf2 v24, v8
 ; RV32-NEXT:    vsll.vi v8, v16, 3
 ; RV32-NEXT:    vsetvli zero, a1, e32, m4, ta, mu
 ; RV32-NEXT:    vncvt.x.x.w v16, v8
 ; RV32-NEXT:    vsetvli zero, zero, e64, m8, ta, mu
 ; RV32-NEXT:    addi a1, a2, -16
 ; RV32-NEXT:    addi a4, sp, 16
 ; RV32-NEXT:    vl8re8.v v8, (a4) # Unknown-size Folded Reload
 ; RV32-NEXT:    vsoxei32.v v8, (a0), v16, v0.t
-; RV32-NEXT:    bltu a2, a1, .LBB82_4
+; RV32-NEXT:    bltu a2, a1, .LBB83_4
 ; RV32-NEXT:  # %bb.3:
 ; RV32-NEXT:    mv a3, a1
-; RV32-NEXT:  .LBB82_4:
+; RV32-NEXT:  .LBB83_4:
 ; RV32-NEXT:    vsetivli zero, 16, e64, m8, ta, mu
 ; RV32-NEXT:    vsll.vi v8, v24, 3
 ; RV32-NEXT:    vsetvli zero, a3, e32, m4, ta, mu
 ; RV32-NEXT:    vncvt.x.x.w v16, v8
 ; RV32-NEXT:    vsetivli zero, 2, e8, mf4, ta, mu
 ; RV32-NEXT:    vslidedown.vi v0, v0, 2
 ; RV32-NEXT:    vsetvli zero, a3, e64, m8, ta, mu
 ; RV32-NEXT:    csrr a1, vlenb

 ; RV64-NEXT:    vsetivli zero, 16, e32, m8, ta, mu
 ; RV64-NEXT:    vslidedown.vi v8, v24, 16
 ; RV64-NEXT:    addi a1, sp, 16
 ; RV64-NEXT:    vs8r.v v8, (a1) # Unknown-size Folded Spill
 ; RV64-NEXT:    vsetivli zero, 16, e64, m8, ta, mu
 ; RV64-NEXT:    li a3, 16
 ; RV64-NEXT:    vzext.vf2 v8, v24
 ; RV64-NEXT:    mv a1, a2
-; RV64-NEXT:    bltu a2, a3, .LBB82_2
+; RV64-NEXT:    bltu a2, a3, .LBB83_2
 ; RV64-NEXT:  # %bb.1:
 ; RV64-NEXT:    li a1, 16
-; RV64-NEXT:  .LBB82_2:
+; RV64-NEXT:  .LBB83_2:
 ; RV64-NEXT:    li a3, 0
 ; RV64-NEXT:    addi a4, sp, 16
 ; RV64-NEXT:    vl8re8.v v24, (a4) # Unknown-size Folded Reload
 ; RV64-NEXT:    vzext.vf2 v16, v24
 ; RV64-NEXT:    vsll.vi v8, v8, 3
 ; RV64-NEXT:    vsetvli zero, a1, e64, m8, ta, mu
 ; RV64-NEXT:    addi a1, a2, -16
 ; RV64-NEXT:    csrr a4, vlenb
 ; RV64-NEXT:    slli a4, a4, 3
 ; RV64-NEXT:    add a4, sp, a4
 ; RV64-NEXT:    addi a4, a4, 16
 ; RV64-NEXT:    vl8re8.v v24, (a4) # Unknown-size Folded Reload
 ; RV64-NEXT:    vsoxei64.v v24, (a0), v8, v0.t
-; RV64-NEXT:    bltu a2, a1, .LBB82_4
+; RV64-NEXT:    bltu a2, a1, .LBB83_4
 ; RV64-NEXT:  # %bb.3:
 ; RV64-NEXT:    mv a3, a1
-; RV64-NEXT:  .LBB82_4:
+; RV64-NEXT:  .LBB83_4:
 ; RV64-NEXT:    vsetivli zero, 2, e8, mf4, ta, mu
 ; RV64-NEXT:    vslidedown.vi v0, v0, 2
 ; RV64-NEXT:    vsetivli zero, 16, e64, m8, ta, mu
 ; RV64-NEXT:    vsll.vi v8, v16, 3
 ; RV64-NEXT:    vsetvli zero, a3, e64, m8, ta, mu
 ; RV64-NEXT:    csrr a1, vlenb
 ; RV64-NEXT:    slli a1, a1, 4
 ; RV64-NEXT:    add a1, sp, a1

llvm/test/CodeGen/RISCV/rvv/vpgather-sdnode.ll

 ; RV64-NEXT:    vsetvli zero, a0, e8, mf4, ta, mu
 ; RV64-NEXT:    vluxei64.v v10, (zero), v8, v0.t
 ; RV64-NEXT:    vmv1r.v v8, v10
 ; RV64-NEXT:    ret
   %v = call <vscale x 2 x i8> @llvm.vp.gather.nxv2i8.nxv2p0i8(<vscale x 2 x i8*> %ptrs, <vscale x 2 x i1> %m, i32 %evl)
   ret <vscale x 2 x i8> %v
 }
 
+declare <vscale x 2 x i7> @llvm.vp.gather.nxv2i7.nxv2p0i7(<vscale x 2 x i7*>, <vscale x 2 x i1>, i32)
+
+define <vscale x 2 x i7> @vpgather_nxv2i7(<vscale x 2 x i7*> %ptrs, <vscale x 2 x i1> %m, i32 zeroext %evl) {
+; RV32-LABEL: vpgather_nxv2i7:
+; RV32:       # %bb.0:
+; RV32-NEXT:    vsetvli zero, a0, e8, mf4, ta, mu
+; RV32-NEXT:    vluxei32.v v9, (zero), v8, v0.t
+; RV32-NEXT:    vmv1r.v v8, v9
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vpgather_nxv2i7:
+; RV64:       # %bb.0:
+; RV64-NEXT:    vsetvli zero, a0, e8, mf4, ta, mu
+; RV64-NEXT:    vluxei64.v v10, (zero), v8, v0.t
+; RV64-NEXT:    vmv1r.v v8, v10
+; RV64-NEXT:    ret
+  %v = call <vscale x 2 x i7> @llvm.vp.gather.nxv2i7.nxv2p0i7(<vscale x 2 x i7*> %ptrs, <vscale x 2 x i1> %m, i32 %evl)
+  ret <vscale x 2 x i7> %v
+}
+
 define <vscale x 2 x i16> @vpgather_nxv2i8_sextload_nxv2i16(<vscale x 2 x i8*> %ptrs, <vscale x 2 x i1> %m, i32 zeroext %evl) {
 ; RV32-LABEL: vpgather_nxv2i8_sextload_nxv2i16:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    vsetvli zero, a0, e8, mf4, ta, mu
 ; RV32-NEXT:    vluxei32.v v9, (zero), v8, v0.t
 ; RV32-NEXT:    vsetvli a0, zero, e16, mf2, ta, mu
 ; RV32-NEXT:    vsext.vf2 v8, v9
 ; RV32-NEXT:    ret

 ; RV32-NEXT:    vmv1r.v v12, v0
 ; RV32-NEXT:    li a3, 0
 ; RV32-NEXT:    csrr a2, vlenb
 ; RV32-NEXT:    srli a5, a2, 2
 ; RV32-NEXT:    vsetvli a4, zero, e8, mf2, ta, mu
 ; RV32-NEXT:    slli a2, a2, 1
 ; RV32-NEXT:    sub a4, a1, a2
 ; RV32-NEXT:    vslidedown.vx v0, v0, a5
-; RV32-NEXT:    bltu a1, a4, .LBB12_2
+; RV32-NEXT:    bltu a1, a4, .LBB13_2
 ; RV32-NEXT:  # %bb.1:
 ; RV32-NEXT:    mv a3, a4
-; RV32-NEXT:  .LBB12_2:
+; RV32-NEXT:  .LBB13_2:
 ; RV32-NEXT:    vsetvli a4, zero, e32, m8, ta, mu
 ; RV32-NEXT:    vsext.vf4 v24, v10
 ; RV32-NEXT:    vsetvli zero, a3, e8, m2, ta, mu
 ; RV32-NEXT:    vluxei32.v v18, (a0), v24, v0.t
-; RV32-NEXT:    bltu a1, a2, .LBB12_4
+; RV32-NEXT:    bltu a1, a2, .LBB13_4
 ; RV32-NEXT:  # %bb.3:
 ; RV32-NEXT:    mv a1, a2
-; RV32-NEXT:  .LBB12_4:
+; RV32-NEXT:  .LBB13_4:
 ; RV32-NEXT:    vsetvli a2, zero, e32, m8, ta, mu
 ; RV32-NEXT:    vsext.vf4 v24, v8
 ; RV32-NEXT:    vsetvli zero, a1, e8, m2, ta, mu
 ; RV32-NEXT:    vmv1r.v v0, v12
 ; RV32-NEXT:    vluxei32.v v16, (a0), v24, v0.t
 ; RV32-NEXT:    vmv4r.v v8, v16
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vpgather_baseidx_nxv32i8:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    csrr a3, vlenb
 ; RV64-NEXT:    slli a5, a3, 1
 ; RV64-NEXT:    sub a6, a1, a5
 ; RV64-NEXT:    vmv1r.v v12, v0
 ; RV64-NEXT:    li a4, 0
 ; RV64-NEXT:    li a2, 0
-; RV64-NEXT:    bltu a1, a6, .LBB12_2
+; RV64-NEXT:    bltu a1, a6, .LBB13_2
 ; RV64-NEXT:  # %bb.1:
 ; RV64-NEXT:    mv a2, a6
-; RV64-NEXT:  .LBB12_2:
+; RV64-NEXT:  .LBB13_2:
 ; RV64-NEXT:    sub a6, a2, a3
 ; RV64-NEXT:    mv a7, a4
-; RV64-NEXT:    bltu a2, a6, .LBB12_4
+; RV64-NEXT:    bltu a2, a6, .LBB13_4
 ; RV64-NEXT:  # %bb.3:
 ; RV64-NEXT:    mv a7, a6
-; RV64-NEXT:  .LBB12_4:
+; RV64-NEXT:  .LBB13_4:
 ; RV64-NEXT:    srli a6, a3, 2
 ; RV64-NEXT:    vsetvli t0, zero, e8, mf2, ta, mu
 ; RV64-NEXT:    vslidedown.vx v13, v12, a6
 ; RV64-NEXT:    srli a6, a3, 3
 ; RV64-NEXT:    vsetvli t0, zero, e8, mf4, ta, mu
 ; RV64-NEXT:    vslidedown.vx v0, v13, a6
 ; RV64-NEXT:    vsetvli t0, zero, e64, m8, ta, mu
 ; RV64-NEXT:    vsext.vf8 v24, v11
 ; RV64-NEXT:    vsetvli zero, a7, e8, m1, ta, mu
 ; RV64-NEXT:    vluxei64.v v19, (a0), v24, v0.t
-; RV64-NEXT:    bltu a1, a5, .LBB12_6
+; RV64-NEXT:    bltu a1, a5, .LBB13_6
 ; RV64-NEXT:  # %bb.5:
 ; RV64-NEXT:    mv a1, a5
-; RV64-NEXT:  .LBB12_6:
+; RV64-NEXT:  .LBB13_6:
 ; RV64-NEXT:    sub a5, a1, a3
-; RV64-NEXT:    bltu a1, a5, .LBB12_8
+; RV64-NEXT:    bltu a1, a5, .LBB13_8
 ; RV64-NEXT:  # %bb.7:
 ; RV64-NEXT:    mv a4, a5
-; RV64-NEXT:  .LBB12_8:
+; RV64-NEXT:  .LBB13_8:
 ; RV64-NEXT:    vsetvli a5, zero, e8, mf4, ta, mu
 ; RV64-NEXT:    vslidedown.vx v0, v12, a6
 ; RV64-NEXT:    vsetvli a5, zero, e64, m8, ta, mu
 ; RV64-NEXT:    vsext.vf8 v24, v9
 ; RV64-NEXT:    vsetvli zero, a4, e8, m1, ta, mu
 ; RV64-NEXT:    vluxei64.v v17, (a0), v24, v0.t
-; RV64-NEXT:    bltu a1, a3, .LBB12_10
+; RV64-NEXT:    bltu a1, a3, .LBB13_10
 ; RV64-NEXT:  # %bb.9:
 ; RV64-NEXT:    mv a1, a3
-; RV64-NEXT:  .LBB12_10:
+; RV64-NEXT:  .LBB13_10:
 ; RV64-NEXT:    vsetvli a4, zero, e64, m8, ta, mu
 ; RV64-NEXT:    vsext.vf8 v24, v8
 ; RV64-NEXT:    vsetvli zero, a1, e8, m1, ta, mu
 ; RV64-NEXT:    vmv1r.v v0, v12
 ; RV64-NEXT:    vluxei64.v v16, (a0), v24, v0.t
-; RV64-NEXT:    bltu a2, a3, .LBB12_12
+; RV64-NEXT:    bltu a2, a3, .LBB13_12
 ; RV64-NEXT:  # %bb.11:
 ; RV64-NEXT:    mv a2, a3
-; RV64-NEXT:  .LBB12_12:
+; RV64-NEXT:  .LBB13_12:
 ; RV64-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
 ; RV64-NEXT:    vsext.vf8 v24, v10
 ; RV64-NEXT:    vsetvli zero, a2, e8, m1, ta, mu
 ; RV64-NEXT:    vmv1r.v v0, v13
 ; RV64-NEXT:    vluxei64.v v18, (a0), v24, v0.t
 ; RV64-NEXT:    vmv4r.v v8, v16
 ; RV64-NEXT:    ret
   %ptrs = getelementptr inbounds i8, i8* %base, <vscale x 32 x i8> %idxs

 ; RV32:       # %bb.0:
 ; RV32-NEXT:    vmv1r.v v24, v0
 ; RV32-NEXT:    li a2, 0
 ; RV32-NEXT:    csrr a1, vlenb
 ; RV32-NEXT:    srli a4, a1, 3
 ; RV32-NEXT:    vsetvli a3, zero, e8, mf4, ta, mu
 ; RV32-NEXT:    sub a3, a0, a1
 ; RV32-NEXT:    vslidedown.vx v0, v0, a4
-; RV32-NEXT:    bltu a0, a3, .LBB102_2
+; RV32-NEXT:    bltu a0, a3, .LBB103_2
 ; RV32-NEXT:  # %bb.1:
 ; RV32-NEXT:    mv a2, a3
-; RV32-NEXT:  .LBB102_2:
+; RV32-NEXT:  .LBB103_2:
 ; RV32-NEXT:    vsetvli zero, a2, e64, m8, ta, mu
 ; RV32-NEXT:    vluxei32.v v16, (zero), v12, v0.t
-; RV32-NEXT:    bltu a0, a1, .LBB102_4
+; RV32-NEXT:    bltu a0, a1, .LBB103_4
 ; RV32-NEXT:  # %bb.3:
 ; RV32-NEXT:    mv a0, a1
-; RV32-NEXT:  .LBB102_4:
+; RV32-NEXT:  .LBB103_4:
 ; RV32-NEXT:    vsetvli zero, a0, e64, m8, ta, mu
 ; RV32-NEXT:    vmv1r.v v0, v24
 ; RV32-NEXT:    vluxei32.v v24, (zero), v8, v0.t
 ; RV32-NEXT:    vmv.v.v v8, v24
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vpgather_nxv16f64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vmv1r.v v24, v0
 ; RV64-NEXT:    li a2, 0
 ; RV64-NEXT:    csrr a1, vlenb
 ; RV64-NEXT:    srli a4, a1, 3
 ; RV64-NEXT:    vsetvli a3, zero, e8, mf4, ta, mu
 ; RV64-NEXT:    sub a3, a0, a1
 ; RV64-NEXT:    vslidedown.vx v0, v0, a4
-; RV64-NEXT:    bltu a0, a3, .LBB102_2
+; RV64-NEXT:    bltu a0, a3, .LBB103_2
 ; RV64-NEXT:  # %bb.1:
 ; RV64-NEXT:    mv a2, a3
-; RV64-NEXT:  .LBB102_2:
+; RV64-NEXT:  .LBB103_2:
 ; RV64-NEXT:    vsetvli zero, a2, e64, m8, ta, mu
 ; RV64-NEXT:    vluxei64.v v16, (zero), v16, v0.t
-; RV64-NEXT:    bltu a0, a1, .LBB102_4
+; RV64-NEXT:    bltu a0, a1, .LBB103_4
 ; RV64-NEXT:  # %bb.3:
 ; RV64-NEXT:    mv a0, a1
-; RV64-NEXT:  .LBB102_4:
+; RV64-NEXT:  .LBB103_4:
 ; RV64-NEXT:    vsetvli zero, a0, e64, m8, ta, mu
 ; RV64-NEXT:    vmv1r.v v0, v24
 ; RV64-NEXT:    vluxei64.v v8, (zero), v8, v0.t
 ; RV64-NEXT:    ret
   %v = call <vscale x 16 x double> @llvm.vp.gather.nxv16f64.nxv16p0f64(<vscale x 16 x double*> %ptrs, <vscale x 16 x i1> %m, i32 %evl)
   ret <vscale x 16 x double> %v
 }
 
 define <vscale x 16 x double> @vpgather_baseidx_nxv16i16_nxv16f64(double* %base, <vscale x 16 x i16> %idxs, <vscale x 16 x i1> %m, i32 zeroext %evl) {
 ; RV32-LABEL: vpgather_baseidx_nxv16i16_nxv16f64:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    vmv1r.v v12, v0
 ; RV32-NEXT:    li a3, 0
 ; RV32-NEXT:    csrr a2, vlenb
 ; RV32-NEXT:    srli a5, a2, 3
 ; RV32-NEXT:    vsetvli a4, zero, e8, mf4, ta, mu
 ; RV32-NEXT:    sub a4, a1, a2
 ; RV32-NEXT:    vslidedown.vx v0, v0, a5
-; RV32-NEXT:    bltu a1, a4, .LBB103_2
+; RV32-NEXT:    bltu a1, a4, .LBB104_2
 ; RV32-NEXT:  # %bb.1:
 ; RV32-NEXT:    mv a3, a4
-; RV32-NEXT:  .LBB103_2:
+; RV32-NEXT:  .LBB104_2:
 ; RV32-NEXT:    vsetvli a4, zero, e32, m8, ta, mu
 ; RV32-NEXT:    vsext.vf2 v16, v8
 ; RV32-NEXT:    vsll.vi v24, v16, 3
 ; RV32-NEXT:    vsetvli zero, a3, e64, m8, ta, mu
 ; RV32-NEXT:    vluxei32.v v16, (a0), v28, v0.t
-; RV32-NEXT:    bltu a1, a2, .LBB103_4
+; RV32-NEXT:    bltu a1, a2, .LBB104_4
 ; RV32-NEXT:  # %bb.3:
 ; RV32-NEXT:    mv a1, a2
-; RV32-NEXT:  .LBB103_4:
+; RV32-NEXT:  .LBB104_4:
 ; RV32-NEXT:    vsetvli zero, a1, e64, m8, ta, mu
 ; RV32-NEXT:    vmv1r.v v0, v12
 ; RV32-NEXT:    vluxei32.v v8, (a0), v24, v0.t
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vpgather_baseidx_nxv16i16_nxv16f64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vmv1r.v v12, v0
 ; RV64-NEXT:    li a3, 0
 ; RV64-NEXT:    csrr a2, vlenb
 ; RV64-NEXT:    srli a5, a2, 3
 ; RV64-NEXT:    vsetvli a4, zero, e8, mf4, ta, mu
 ; RV64-NEXT:    sub a4, a1, a2
 ; RV64-NEXT:    vslidedown.vx v0, v0, a5
-; RV64-NEXT:    bltu a1, a4, .LBB103_2
+; RV64-NEXT:    bltu a1, a4, .LBB104_2
 ; RV64-NEXT:  # %bb.1:
 ; RV64-NEXT:    mv a3, a4
-; RV64-NEXT:  .LBB103_2:
+; RV64-NEXT:  .LBB104_2:
 ; RV64-NEXT:    vsetvli a4, zero, e64, m8, ta, mu
 ; RV64-NEXT:    vsext.vf4 v16, v10
 ; RV64-NEXT:    vsll.vi v16, v16, 3
 ; RV64-NEXT:    vsetvli zero, a3, e64, m8, ta, mu
 ; RV64-NEXT:    vluxei64.v v16, (a0), v16, v0.t
-; RV64-NEXT:    bltu a1, a2, .LBB103_4
+; RV64-NEXT:    bltu a1, a2, .LBB104_4
 ; RV64-NEXT:  # %bb.3:
 ; RV64-NEXT:    mv a1, a2
-; RV64-NEXT:  .LBB103_4:
+; RV64-NEXT:  .LBB104_4:
 ; RV64-NEXT:    vsetvli a2, zero, e64, m8, ta, mu
 ; RV64-NEXT:    vsext.vf4 v24, v8
 ; RV64-NEXT:    vsll.vi v24, v24, 3
 ; RV64-NEXT:    vsetvli zero, a1, e64, m8, ta, mu
 ; RV64-NEXT:    vmv1r.v v0, v12
 ; RV64-NEXT:    vluxei64.v v8, (a0), v24, v0.t
 ; RV64-NEXT:    ret
   %ptrs = getelementptr inbounds double, double* %base, <vscale x 16 x i16> %idxs
   %v = call <vscale x 16 x double> @llvm.vp.gather.nxv16f64.nxv16p0f64(<vscale x 16 x double*> %ptrs, <vscale x 16 x i1> %m, i32 %evl)
   ret <vscale x 16 x double> %v
 }
 
 define <vscale x 16 x double> @vpgather_baseidx_sext_nxv16i16_nxv16f64(double* %base, <vscale x 16 x i16> %idxs, <vscale x 16 x i1> %m, i32 zeroext %evl) {
 ; RV32-LABEL: vpgather_baseidx_sext_nxv16i16_nxv16f64:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    vsetvli a2, zero, e64, m8, ta, mu
 ; RV32-NEXT:    csrr a2, vlenb
 ; RV32-NEXT:    vsext.vf4 v16, v8
 ; RV32-NEXT:    mv a3, a1
-; RV32-NEXT:    bltu a1, a2, .LBB104_2
+; RV32-NEXT:    bltu a1, a2, .LBB105_2
 ; RV32-NEXT:  # %bb.1:
 ; RV32-NEXT:    mv a3, a2
-; RV32-NEXT:  .LBB104_2:
+; RV32-NEXT:  .LBB105_2:
 ; RV32-NEXT:    li a4, 0
 ; RV32-NEXT:    vsext.vf4 v24, v10
 ; RV32-NEXT:    vsll.vi v8, v16, 3
 ; RV32-NEXT:    vsetvli zero, a3, e32, m4, ta, mu
 ; RV32-NEXT:    vncvt.x.x.w v16, v8
 ; RV32-NEXT:    vsetvli zero, zero, e64, m8, ta, mu
 ; RV32-NEXT:    vluxei32.v v8, (a0), v16, v0.t
 ; RV32-NEXT:    srli a3, a2, 3
 ; RV32-NEXT:    vsetvli a5, zero, e8, mf4, ta, mu
 ; RV32-NEXT:    sub a2, a1, a2
 ; RV32-NEXT:    vslidedown.vx v0, v0, a3
-; RV32-NEXT:    bltu a1, a2, .LBB104_4
+; RV32-NEXT:    bltu a1, a2, .LBB105_4
 ; RV32-NEXT:  # %bb.3:
 ; RV32-NEXT:    mv a4, a2
-; RV32-NEXT:  .LBB104_4:
+; RV32-NEXT:  .LBB105_4:
 ; RV32-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
 ; RV32-NEXT:    vsll.vi v16, v24, 3
 ; RV32-NEXT:    vsetvli zero, a4, e32, m4, ta, mu
 ; RV32-NEXT:    vncvt.x.x.w v24, v16
 ; RV32-NEXT:    vsetvli zero, zero, e64, m8, ta, mu
 ; RV32-NEXT:    vluxei32.v v16, (a0), v24, v0.t
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vpgather_baseidx_sext_nxv16i16_nxv16f64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vmv1r.v v12, v0
 ; RV64-NEXT:    li a3, 0
 ; RV64-NEXT:    vsetvli a2, zero, e64, m8, ta, mu
 ; RV64-NEXT:    vsext.vf4 v16, v10
 ; RV64-NEXT:    csrr a2, vlenb
 ; RV64-NEXT:    srli a5, a2, 3
 ; RV64-NEXT:    vsetvli a4, zero, e8, mf4, ta, mu
 ; RV64-NEXT:    sub a4, a1, a2
 ; RV64-NEXT:    vslidedown.vx v0, v0, a5
-; RV64-NEXT:    bltu a1, a4, .LBB104_2
+; RV64-NEXT:    bltu a1, a4, .LBB105_2
 ; RV64-NEXT:  # %bb.1:
 ; RV64-NEXT:    mv a3, a4
-; RV64-NEXT:  .LBB104_2:
+; RV64-NEXT:  .LBB105_2:
 ; RV64-NEXT:    vsetvli a4, zero, e64, m8, ta, mu
 ; RV64-NEXT:    vsext.vf4 v24, v8
 ; RV64-NEXT:    vsll.vi v16, v16, 3
 ; RV64-NEXT:    vsetvli zero, a3, e64, m8, ta, mu
 ; RV64-NEXT:    vluxei64.v v16, (a0), v16, v0.t
-; RV64-NEXT:    bltu a1, a2, .LBB104_4
+; RV64-NEXT:    bltu a1, a2, .LBB105_4
 ; RV64-NEXT:  # %bb.3:
 ; RV64-NEXT:    mv a1, a2
-; RV64-NEXT:  .LBB104_4:
+; RV64-NEXT:  .LBB105_4:
 ; RV64-NEXT:    vsetvli a2, zero, e64, m8, ta, mu
 ; RV64-NEXT:    vsll.vi v24, v24, 3
 ; RV64-NEXT:    vsetvli zero, a1, e64, m8, ta, mu
 ; RV64-NEXT:    vmv1r.v v0, v12
 ; RV64-NEXT:    vluxei64.v v8, (a0), v24, v0.t
 ; RV64-NEXT:    ret
   %eidxs = sext <vscale x 16 x i16> %idxs to <vscale x 16 x i64>
   %ptrs = getelementptr inbounds double, double* %base, <vscale x 16 x i64> %eidxs
   %v = call <vscale x 16 x double> @llvm.vp.gather.nxv16f64.nxv16p0f64(<vscale x 16 x double*> %ptrs, <vscale x 16 x i1> %m, i32 %evl)
   ret <vscale x 16 x double> %v
 }
 
 define <vscale x 16 x double> @vpgather_baseidx_zext_nxv16i16_nxv16f64(double* %base, <vscale x 16 x i16> %idxs, <vscale x 16 x i1> %m, i32 zeroext %evl) {
 ; RV32-LABEL: vpgather_baseidx_zext_nxv16i16_nxv16f64:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    vsetvli a2, zero, e64, m8, ta, mu
 ; RV32-NEXT:    csrr a2, vlenb
 ; RV32-NEXT:    vzext.vf4 v16, v8
 ; RV32-NEXT:    mv a3, a1
-; RV32-NEXT:    bltu a1, a2, .LBB105_2
+; RV32-NEXT:    bltu a1, a2, .LBB106_2
 ; RV32-NEXT:  # %bb.1:
 ; RV32-NEXT:    mv a3, a2
-; RV32-NEXT:  .LBB105_2:
+; RV32-NEXT:  .LBB106_2:
 ; RV32-NEXT:    li a4, 0
 ; RV32-NEXT:    vzext.vf4 v24, v10
 ; RV32-NEXT:    vsll.vi v8, v16, 3
 ; RV32-NEXT:    vsetvli zero, a3, e32, m4, ta, mu
 ; RV32-NEXT:    vncvt.x.x.w v16, v8
 ; RV32-NEXT:    vsetvli zero, zero, e64, m8, ta, mu
 ; RV32-NEXT:    vluxei32.v v8, (a0), v16, v0.t
 ; RV32-NEXT:    srli a3, a2, 3
 ; RV32-NEXT:    vsetvli a5, zero, e8, mf4, ta, mu
 ; RV32-NEXT:    sub a2, a1, a2
 ; RV32-NEXT:    vslidedown.vx v0, v0, a3
-; RV32-NEXT:    bltu a1, a2, .LBB105_4
+; RV32-NEXT:    bltu a1, a2, .LBB106_4
 ; RV32-NEXT:  # %bb.3:
 ; RV32-NEXT:    mv a4, a2
-; RV32-NEXT:  .LBB105_4:
+; RV32-NEXT:  .LBB106_4:
 ; RV32-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
 ; RV32-NEXT:    vsll.vi v16, v24, 3
 ; RV32-NEXT:    vsetvli zero, a4, e32, m4, ta, mu
 ; RV32-NEXT:    vncvt.x.x.w v24, v16
 ; RV32-NEXT:    vsetvli zero, zero, e64, m8, ta, mu
 ; RV32-NEXT:    vluxei32.v v16, (a0), v24, v0.t
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vpgather_baseidx_zext_nxv16i16_nxv16f64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vmv1r.v v12, v0
 ; RV64-NEXT:    li a3, 0
 ; RV64-NEXT:    vsetvli a2, zero, e64, m8, ta, mu
 ; RV64-NEXT:    vzext.vf4 v16, v10
 ; RV64-NEXT:    csrr a2, vlenb
 ; RV64-NEXT:    srli a5, a2, 3
 ; RV64-NEXT:    vsetvli a4, zero, e8, mf4, ta, mu
 ; RV64-NEXT:    sub a4, a1, a2
 ; RV64-NEXT:    vslidedown.vx v0, v0, a5
-; RV64-NEXT:    bltu a1, a4, .LBB105_2
+; RV64-NEXT:    bltu a1, a4, .LBB106_2
 ; RV64-NEXT:  # %bb.1:
 ; RV64-NEXT:    mv a3, a4
-; RV64-NEXT:  .LBB105_2:
+; RV64-NEXT:  .LBB106_2:
 ; RV64-NEXT:    vsetvli a4, zero, e64, m8, ta, mu
 ; RV64-NEXT:    vzext.vf4 v24, v8
 ; RV64-NEXT:    vsll.vi v16, v16, 3
 ; RV64-NEXT:    vsetvli zero, a3, e64, m8, ta, mu
 ; RV64-NEXT:    vluxei64.v v16, (a0), v16, v0.t
-; RV64-NEXT:    bltu a1, a2, .LBB105_4
+; RV64-NEXT:    bltu a1, a2, .LBB106_4
 ; RV64-NEXT:  # %bb.3:
 ; RV64-NEXT:    mv a1, a2
-; RV64-NEXT:  .LBB105_4:
+; RV64-NEXT:  .LBB106_4:
 ; RV64-NEXT:    vsetvli a2, zero, e64, m8, ta, mu
 ; RV64-NEXT:    vsll.vi v24, v24, 3
 ; RV64-NEXT:    vsetvli zero, a1, e64, m8, ta, mu
 ; RV64-NEXT:    vmv1r.v v0, v12
 ; RV64-NEXT:    vluxei64.v v8, (a0), v24, v0.t
 ; RV64-NEXT:    ret
   %eidxs = zext <vscale x 16 x i16> %idxs to <vscale x 16 x i64>
   %ptrs = getelementptr inbounds double, double* %base, <vscale x 16 x i64> %eidxs
   %v = call <vscale x 16 x double> @llvm.vp.gather.nxv16f64.nxv16p0f64(<vscale x 16 x double*> %ptrs, <vscale x 16 x i1> %m, i32 %evl)
   ret <vscale x 16 x double> %v
 }

llvm/test/CodeGen/RISCV/rvv/vpscatter-sdnode.ll

 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetvli zero, a0, e8, mf4, ta, mu
 ; RV64-NEXT:    vsoxei64.v v8, (zero), v10, v0.t
 ; RV64-NEXT:    ret
   call void @llvm.vp.scatter.nxv2i8.nxv2p0i8(<vscale x 2 x i8> %val, <vscale x 2 x i8*> %ptrs, <vscale x 2 x i1> %m, i32 %evl)
   ret void
 }
 
+declare void @llvm.vp.scatter.nxv2i7.nxv2p0i7(<vscale x 2 x i7>, <vscale x 2 x i7*>, <vscale x 2 x i1>, i32)
+
+define void @vpscatter_nxv2i7(<vscale x 2 x i7> %val, <vscale x 2 x i7*> %ptrs, <vscale x 2 x i1> %m, i32 zeroext %evl) {
+; RV32-LABEL: vpscatter_nxv2i7:
+; RV32:       # %bb.0:
+; RV32-NEXT:    vsetvli zero, a0, e8, mf4, ta, mu
+; RV32-NEXT:    vsoxei32.v v8, (zero), v9, v0.t
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vpscatter_nxv2i7:
+; RV64:       # %bb.0:
+; RV64-NEXT:    vsetvli zero, a0, e8, mf4, ta, mu
+; RV64-NEXT:    vsoxei64.v v8, (zero), v10, v0.t
+; RV64-NEXT:    ret
+  call void @llvm.vp.scatter.nxv2i7.nxv2p0i7(<vscale x 2 x i7> %val, <vscale x 2 x i7*> %ptrs, <vscale x 2 x i1> %m, i32 %evl)
+  ret void
+}
+
 define void @vpscatter_nxv2i16_truncstore_nxv2i8(<vscale x 2 x i16> %val, <vscale x 2 x i8*> %ptrs, <vscale x 2 x i1> %m, i32 zeroext %evl) {
 ; RV32-LABEL: vpscatter_nxv2i16_truncstore_nxv2i8:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    vsetvli a1, zero, e8, mf4, ta, mu
 ; RV32-NEXT:    vncvt.x.x.w v8, v8
 ; RV32-NEXT:    vsetvli zero, a0, e8, mf4, ta, mu
 ; RV32-NEXT:    vsoxei32.v v8, (zero), v9, v0.t
 ; RV32-NEXT:    ret

 declare void @llvm.vp.scatter.nxv16f64.nxv16p0f64(<vscale x 16 x double>, <vscale x 16 x double*>, <vscale x 16 x i1>, i32)
 
 define void @vpscatter_nxv16f64(<vscale x 16 x double> %val, <vscale x 16 x double*> %ptrs, <vscale x 16 x i1> %m, i32 zeroext %evl) {
 ; RV32-LABEL: vpscatter_nxv16f64:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    vl8re32.v v24, (a0)
 ; RV32-NEXT:    csrr a0, vlenb
 ; RV32-NEXT:    mv a2, a1
-; RV32-NEXT:    bltu a1, a0, .LBB95_2
+; RV32-NEXT:    bltu a1, a0, .LBB96_2
 ; RV32-NEXT:  # %bb.1:
 ; RV32-NEXT:    mv a2, a0
-; RV32-NEXT:  .LBB95_2:
+; RV32-NEXT:  .LBB96_2:
 ; RV32-NEXT:    li a3, 0
 ; RV32-NEXT:    vsetvli zero, a2, e64, m8, ta, mu
 ; RV32-NEXT:    vsoxei32.v v8, (zero), v24, v0.t
 ; RV32-NEXT:    srli a2, a0, 3
 ; RV32-NEXT:    vsetvli a4, zero, e8, mf4, ta, mu
 ; RV32-NEXT:    sub a0, a1, a0
 ; RV32-NEXT:    vslidedown.vx v0, v0, a2
-; RV32-NEXT:    bltu a1, a0, .LBB95_4
+; RV32-NEXT:    bltu a1, a0, .LBB96_4
 ; RV32-NEXT:  # %bb.3:
 ; RV32-NEXT:    mv a3, a0
-; RV32-NEXT:  .LBB95_4:
+; RV32-NEXT:  .LBB96_4:
 ; RV32-NEXT:    vsetvli zero, a3, e64, m8, ta, mu
 ; RV32-NEXT:    vsoxei32.v v16, (zero), v28, v0.t
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vpscatter_nxv16f64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    addi sp, sp, -16
 ; RV64-NEXT:    .cfi_def_cfa_offset 16
 ; RV64-NEXT:    csrr a1, vlenb
 ; RV64-NEXT:    slli a1, a1, 3
 ; RV64-NEXT:    sub sp, sp, a1
 ; RV64-NEXT:    addi a1, sp, 16
 ; RV64-NEXT:    vs8r.v v16, (a1) # Unknown-size Folded Spill
 ; RV64-NEXT:    vl8re64.v v16, (a0)
 ; RV64-NEXT:    csrr a1, vlenb
 ; RV64-NEXT:    slli a3, a1, 3
 ; RV64-NEXT:    add a0, a0, a3
 ; RV64-NEXT:    mv a3, a2
-; RV64-NEXT:    bltu a2, a1, .LBB95_2
+; RV64-NEXT:    bltu a2, a1, .LBB96_2
 ; RV64-NEXT:  # %bb.1:
 ; RV64-NEXT:    mv a3, a1
-; RV64-NEXT:  .LBB95_2:
+; RV64-NEXT:  .LBB96_2:
 ; RV64-NEXT:    li a4, 0
 ; RV64-NEXT:    vl8re64.v v24, (a0)
 ; RV64-NEXT:    vsetvli zero, a3, e64, m8, ta, mu
 ; RV64-NEXT:    vsoxei64.v v8, (zero), v16, v0.t
 ; RV64-NEXT:    srli a3, a1, 3
 ; RV64-NEXT:    vsetvli a0, zero, e8, mf4, ta, mu
 ; RV64-NEXT:    sub a0, a2, a1
 ; RV64-NEXT:    vslidedown.vx v0, v0, a3
-; RV64-NEXT:    bltu a2, a0, .LBB95_4
+; RV64-NEXT:    bltu a2, a0, .LBB96_4
 ; RV64-NEXT:  # %bb.3:
 ; RV64-NEXT:    mv a4, a0
-; RV64-NEXT:  .LBB95_4:
+; RV64-NEXT:  .LBB96_4:
 ; RV64-NEXT:    vsetvli zero, a4, e64, m8, ta, mu
 ; RV64-NEXT:    addi a0, sp, 16
 ; RV64-NEXT:    vl8re8.v v8, (a0) # Unknown-size Folded Reload
 ; RV64-NEXT:    vsoxei64.v v8, (zero), v24, v0.t
 ; RV64-NEXT:    csrr a0, vlenb
 ; RV64-NEXT:    slli a0, a0, 3
 ; RV64-NEXT:    add sp, sp, a0
 ; RV64-NEXT:    addi sp, sp, 16
 ; RV64-NEXT:    ret
   call void @llvm.vp.scatter.nxv16f64.nxv16p0f64(<vscale x 16 x double> %val, <vscale x 16 x double*> %ptrs, <vscale x 16 x i1> %m, i32 %evl)
   ret void
 }
 
 define void @vpscatter_baseidx_nxv16i16_nxv16f64(<vscale x 16 x double> %val, double* %base, <vscale x 16 x i16> %idxs, <vscale x 16 x i1> %m, i32 zeroext %evl) {
 ; RV32-LABEL: vpscatter_baseidx_nxv16i16_nxv16f64:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    vl4re16.v v4, (a1)
 ; RV32-NEXT:    csrr a1, vlenb
 ; RV32-NEXT:    mv a3, a2
-; RV32-NEXT:    bltu a2, a1, .LBB96_2
+; RV32-NEXT:    bltu a2, a1, .LBB97_2
 ; RV32-NEXT:  # %bb.1:
 ; RV32-NEXT:    mv a3, a1
-; RV32-NEXT:  .LBB96_2:
+; RV32-NEXT:  .LBB97_2:
 ; RV32-NEXT:    li a4, 0
 ; RV32-NEXT:    vsetvli a5, zero, e32, m8, ta, mu
 ; RV32-NEXT:    vsext.vf2 v24, v4
 ; RV32-NEXT:    vsll.vi v24, v24, 3
 ; RV32-NEXT:    vsetvli zero, a3, e64, m8, ta, mu
 ; RV32-NEXT:    vsoxei32.v v8, (a0), v24, v0.t
 ; RV32-NEXT:    srli a3, a1, 3
 ; RV32-NEXT:    vsetvli a5, zero, e8, mf4, ta, mu
 ; RV32-NEXT:    sub a1, a2, a1
 ; RV32-NEXT:    vslidedown.vx v0, v0, a3
-; RV32-NEXT:    bltu a2, a1, .LBB96_4
+; RV32-NEXT:    bltu a2, a1, .LBB97_4
 ; RV32-NEXT:  # %bb.3:
 ; RV32-NEXT:    mv a4, a1
-; RV32-NEXT:  .LBB96_4:
+; RV32-NEXT:  .LBB97_4:
 ; RV32-NEXT:    vsetvli zero, a4, e64, m8, ta, mu
 ; RV32-NEXT:    vsoxei32.v v16, (a0), v28, v0.t
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vpscatter_baseidx_nxv16i16_nxv16f64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vl4re16.v v4, (a1)
 ; RV64-NEXT:    csrr a1, vlenb
 ; RV64-NEXT:    mv a3, a2
-; RV64-NEXT:    bltu a2, a1, .LBB96_2
+; RV64-NEXT:    bltu a2, a1, .LBB97_2
 ; RV64-NEXT:  # %bb.1:
 ; RV64-NEXT:    mv a3, a1
-; RV64-NEXT:  .LBB96_2:
+; RV64-NEXT:  .LBB97_2:
 ; RV64-NEXT:    li a4, 0
 ; RV64-NEXT:    vsetvli a5, zero, e64, m8, ta, mu
 ; RV64-NEXT:    vsext.vf4 v24, v4
 ; RV64-NEXT:    vsll.vi v24, v24, 3
 ; RV64-NEXT:    vsetvli zero, a3, e64, m8, ta, mu
 ; RV64-NEXT:    vsoxei64.v v8, (a0), v24, v0.t
 ; RV64-NEXT:    srli a3, a1, 3
 ; RV64-NEXT:    vsetvli a5, zero, e8, mf4, ta, mu
 ; RV64-NEXT:    sub a1, a2, a1
 ; RV64-NEXT:    vslidedown.vx v0, v0, a3
-; RV64-NEXT:    bltu a2, a1, .LBB96_4
+; RV64-NEXT:    bltu a2, a1, .LBB97_4
 ; RV64-NEXT:  # %bb.3:
 ; RV64-NEXT:    mv a4, a1
-; RV64-NEXT:  .LBB96_4:
+; RV64-NEXT:  .LBB97_4:
 ; RV64-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
 ; RV64-NEXT:    vsext.vf4 v8, v6
 ; RV64-NEXT:    vsll.vi v8, v8, 3
 ; RV64-NEXT:    vsetvli zero, a4, e64, m8, ta, mu
 ; RV64-NEXT:    vsoxei64.v v16, (a0), v8, v0.t
 ; RV64-NEXT:    ret
   %ptrs = getelementptr inbounds double, double* %base, <vscale x 16 x i16> %idxs
   call void @llvm.vp.scatter.nxv16f64.nxv16p0f64(<vscale x 16 x double> %val, <vscale x 16 x double*> %ptrs, <vscale x 16 x i1> %m, i32 %evl)

 ; RV32-NEXT:    addi a1, a1, 16
 ; RV32-NEXT:    vs8r.v v16, (a1) # Unknown-size Folded Spill
 ; RV32-NEXT:    addi a1, sp, 16
 ; RV32-NEXT:    vs8r.v v8, (a1) # Unknown-size Folded Spill
 ; RV32-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
 ; RV32-NEXT:    csrr a1, vlenb
 ; RV32-NEXT:    vsext.vf4 v8, v24
 ; RV32-NEXT:    mv a3, a2
-; RV32-NEXT:    bltu a2, a1, .LBB97_2
+; RV32-NEXT:    bltu a2, a1, .LBB98_2
 ; RV32-NEXT:  # %bb.1:
 ; RV32-NEXT:    mv a3, a1
-; RV32-NEXT:  .LBB97_2:
+; RV32-NEXT:  .LBB98_2:
 ; RV32-NEXT:    li a4, 0
 ; RV32-NEXT:    vsext.vf4 v16, v26
 ; RV32-NEXT:    vsll.vi v8, v8, 3
 ; RV32-NEXT:    vsetvli zero, a3, e32, m4, ta, mu
 ; RV32-NEXT:    vncvt.x.x.w v24, v8
 ; RV32-NEXT:    vsetvli zero, zero, e64, m8, ta, mu
 ; RV32-NEXT:    addi a3, sp, 16
 ; RV32-NEXT:    vl8re8.v v8, (a3) # Unknown-size Folded Reload
 ; RV32-NEXT:    vsoxei32.v v8, (a0), v24, v0.t
 ; RV32-NEXT:    srli a3, a1, 3
 ; RV32-NEXT:    vsetvli a5, zero, e8, mf4, ta, mu
 ; RV32-NEXT:    sub a1, a2, a1
 ; RV32-NEXT:    vslidedown.vx v0, v0, a3
-; RV32-NEXT:    bltu a2, a1, .LBB97_4
+; RV32-NEXT:    bltu a2, a1, .LBB98_4
 ; RV32-NEXT:  # %bb.3:
 ; RV32-NEXT:    mv a4, a1
-; RV32-NEXT:  .LBB97_4:
+; RV32-NEXT:  .LBB98_4:
 ; RV32-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
 ; RV32-NEXT:    vsll.vi v8, v16, 3
 ; RV32-NEXT:    vsetvli zero, a4, e32, m4, ta, mu
 ; RV32-NEXT:    vncvt.x.x.w v16, v8
 ; RV32-NEXT:    vsetvli zero, zero, e64, m8, ta, mu
 ; RV32-NEXT:    csrr a1, vlenb
 ; RV32-NEXT:    slli a1, a1, 3
 ; RV32-NEXT:    add a1, sp, a1

 ; RV64-NEXT:    addi a1, a1, 16
 ; RV64-NEXT:    vs8r.v v16, (a1) # Unknown-size Folded Spill
 ; RV64-NEXT:    addi a1, sp, 16
 ; RV64-NEXT:    vs8r.v v8, (a1) # Unknown-size Folded Spill
 ; RV64-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
 ; RV64-NEXT:    csrr a1, vlenb
 ; RV64-NEXT:    vsext.vf4 v8, v24
 ; RV64-NEXT:    mv a3, a2
-; RV64-NEXT:    bltu a2, a1, .LBB97_2
+; RV64-NEXT:    bltu a2, a1, .LBB98_2
 ; RV64-NEXT:  # %bb.1:
 ; RV64-NEXT:    mv a3, a1
-; RV64-NEXT:  .LBB97_2:
+; RV64-NEXT:  .LBB98_2:
 ; RV64-NEXT:    li a4, 0
 ; RV64-NEXT:    vsext.vf4 v16, v26
 ; RV64-NEXT:    vsll.vi v8, v8, 3
 ; RV64-NEXT:    vsetvli zero, a3, e64, m8, ta, mu
 ; RV64-NEXT:    addi a3, sp, 16
 ; RV64-NEXT:    vl8re8.v v24, (a3) # Unknown-size Folded Reload
 ; RV64-NEXT:    vsoxei64.v v24, (a0), v8, v0.t
 ; RV64-NEXT:    srli a3, a1, 3
 ; RV64-NEXT:    vsetvli a5, zero, e8, mf4, ta, mu
 ; RV64-NEXT:    sub a1, a2, a1
 ; RV64-NEXT:    vslidedown.vx v0, v0, a3
-; RV64-NEXT:    bltu a2, a1, .LBB97_4
+; RV64-NEXT:    bltu a2, a1, .LBB98_4
 ; RV64-NEXT:  # %bb.3:
 ; RV64-NEXT:    mv a4, a1
-; RV64-NEXT:  .LBB97_4:
+; RV64-NEXT:  .LBB98_4:
 ; RV64-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
 ; RV64-NEXT:    vsll.vi v8, v16, 3
 ; RV64-NEXT:    vsetvli zero, a4, e64, m8, ta, mu
 ; RV64-NEXT:    csrr a1, vlenb
 ; RV64-NEXT:    slli a1, a1, 3
 ; RV64-NEXT:    add a1, sp, a1
 ; RV64-NEXT:    addi a1, a1, 16
 ; RV64-NEXT:    vl8re8.v v16, (a1) # Unknown-size Folded Reload

 ; RV32-NEXT:    addi a1, a1, 16
 ; RV32-NEXT:    vs8r.v v16, (a1) # Unknown-size Folded Spill
 ; RV32-NEXT:    addi a1, sp, 16
 ; RV32-NEXT:    vs8r.v v8, (a1) # Unknown-size Folded Spill
 ; RV32-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
 ; RV32-NEXT:    csrr a1, vlenb
 ; RV32-NEXT:    vzext.vf4 v8, v24
 ; RV32-NEXT:    mv a3, a2
-; RV32-NEXT:    bltu a2, a1, .LBB98_2
+; RV32-NEXT:    bltu a2, a1, .LBB99_2
 ; RV32-NEXT:  # %bb.1:
 ; RV32-NEXT:    mv a3, a1
-; RV32-NEXT:  .LBB98_2:
+; RV32-NEXT:  .LBB99_2:
 ; RV32-NEXT:    li a4, 0
 ; RV32-NEXT:    vzext.vf4 v16, v26
 ; RV32-NEXT:    vsll.vi v8, v8, 3
 ; RV32-NEXT:    vsetvli zero, a3, e32, m4, ta, mu
 ; RV32-NEXT:    vncvt.x.x.w v24, v8
 ; RV32-NEXT:    vsetvli zero, zero, e64, m8, ta, mu
 ; RV32-NEXT:    addi a3, sp, 16
 ; RV32-NEXT:    vl8re8.v v8, (a3) # Unknown-size Folded Reload
 ; RV32-NEXT:    vsoxei32.v v8, (a0), v24, v0.t
 ; RV32-NEXT:    srli a3, a1, 3
 ; RV32-NEXT:    vsetvli a5, zero, e8, mf4, ta, mu
 ; RV32-NEXT:    sub a1, a2, a1
 ; RV32-NEXT:    vslidedown.vx v0, v0, a3
-; RV32-NEXT:    bltu a2, a1, .LBB98_4
+; RV32-NEXT:    bltu a2, a1, .LBB99_4
 ; RV32-NEXT:  # %bb.3:
 ; RV32-NEXT:    mv a4, a1
-; RV32-NEXT:  .LBB98_4:
+; RV32-NEXT:  .LBB99_4:
 ; RV32-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
 ; RV32-NEXT:    vsll.vi v8, v16, 3
 ; RV32-NEXT:    vsetvli zero, a4, e32, m4, ta, mu
 ; RV32-NEXT:    vncvt.x.x.w v16, v8
 ; RV32-NEXT:    vsetvli zero, zero, e64, m8, ta, mu
 ; RV32-NEXT:    csrr a1, vlenb
 ; RV32-NEXT:    slli a1, a1, 3
 ; RV32-NEXT:    add a1, sp, a1

 ; RV64-NEXT:    addi a1, a1, 16
 ; RV64-NEXT:    vs8r.v v16, (a1) # Unknown-size Folded Spill
 ; RV64-NEXT:    addi a1, sp, 16
 ; RV64-NEXT:    vs8r.v v8, (a1) # Unknown-size Folded Spill
 ; RV64-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
 ; RV64-NEXT:    csrr a1, vlenb
 ; RV64-NEXT:    vzext.vf4 v8, v24
 ; RV64-NEXT:    mv a3, a2
-; RV64-NEXT:    bltu a2, a1, .LBB98_2
+; RV64-NEXT:    bltu a2, a1, .LBB99_2
 ; RV64-NEXT:  # %bb.1:
 ; RV64-NEXT:    mv a3, a1
-; RV64-NEXT:  .LBB98_2:
+; RV64-NEXT:  .LBB99_2:
 ; RV64-NEXT:    li a4, 0
 ; RV64-NEXT:    vzext.vf4 v16, v26
 ; RV64-NEXT:    vsll.vi v8, v8, 3
 ; RV64-NEXT:    vsetvli zero, a3, e64, m8, ta, mu
 ; RV64-NEXT:    addi a3, sp, 16
 ; RV64-NEXT:    vl8re8.v v24, (a3) # Unknown-size Folded Reload
 ; RV64-NEXT:    vsoxei64.v v24, (a0), v8, v0.t
 ; RV64-NEXT:    srli a3, a1, 3
 ; RV64-NEXT:    vsetvli a5, zero, e8, mf4, ta, mu
 ; RV64-NEXT:    sub a1, a2, a1
 ; RV64-NEXT:    vslidedown.vx v0, v0, a3
-; RV64-NEXT:    bltu a2, a1, .LBB98_4
+; RV64-NEXT:    bltu a2, a1, .LBB99_4
 ; RV64-NEXT:  # %bb.3:
 ; RV64-NEXT:    mv a4, a1
-; RV64-NEXT:  .LBB98_4:
+; RV64-NEXT:  .LBB99_4:
 ; RV64-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
 ; RV64-NEXT:    vsll.vi v8, v16, 3
 ; RV64-NEXT:    vsetvli zero, a4, e64, m8, ta, mu
 ; RV64-NEXT:    csrr a1, vlenb
 ; RV64-NEXT:    slli a1, a1, 3
 ; RV64-NEXT:    add a1, sp, a1
 ; RV64-NEXT:    addi a1, a1, 16
 ; RV64-NEXT:    vl8re8.v v16, (a1) # Unknown-size Folded Reload