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[AMDGPU] Mark SMEM cache invalidations as not reading memory
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Authored by foad on May 20 2022, 8:48 AM.

Details

Summary

This brings the MachineInstrs in line with the corresponding intrinsics
which have side effects but do not access memory. It also matches how
BUF cache invalidation instructions are defined.

The lit test changes are just because the machine scheduler previously
treated them like loads, and added an artificial scheduling edge from
them to the exit SU, which caused them to be scheduled earlier.

Diff Detail

Event Timeline

foad created this revision.May 20 2022, 8:48 AM
Herald added a project: Restricted Project. · View Herald TranscriptMay 20 2022, 8:48 AM
foad requested review of this revision.May 20 2022, 8:48 AM
Herald added a project: Restricted Project. · View Herald TranscriptMay 20 2022, 8:48 AM
rampitec accepted this revision.May 20 2022, 8:56 AM
This revision is now accepted and ready to land.May 20 2022, 8:56 AM
This revision was landed with ongoing or failed builds.May 20 2022, 9:20 AM
This revision was automatically updated to reflect the committed changes.