[SelectionDAGBuilder] Pass fast math flags to most of VP SDNodes.

[fakepaper56]

Summary

The patch does not pass math flags to float VPCmpIntrinsics because LLParser
could not identify float VPCmpIntrinsics as FPMathOperators.

[fakepaper56]

Rename class form [SelectionDAGBuilder] to [VP].

[craig.topper]

I would split this patch. One for vp.fcmp and one for the other operations. The LLParser issue is concerning and may delay the vp.fcmp support. That shouldn't block the other nodes.

llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

7603

If we hit this line on an FP operation with fast math flags, would we add fast math flags to an ISD::ZERO_EXTEND?

Might be safer to pass the flags to the DAG.getNode call in the default case.

llvm/test/CodeGen/RISCV/rvv/fast-math-flags-vp.ll

3 ↗

(On Diff #429415)

declartion -> declaration

[fakepaper56]

The update removes the part of vp.fcmp support and using argument of DAG.getNode to pass flags.

[fakepaper56]

llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

7603

Thank your reminder. I fix the bug in the latest update.

[craig.topper]

llvm/test/CodeGen/RISCV/pass-fast-math-flags-sdnode.ll

2

You need REQUIRES: asserts if you use -debug-only. The -debug-only option isn't available on builds without asserts.

[craig.topper]

llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

7615

Why can't we do?

SDValue Result;
SDNodeFlags SDFlags;
if (auto *FPMO = dyn_cast<FPMathOperator>(&VPIntrin))
  SDFlags.copyFMF(*FPMO);
Result = DAG.getNode(Opcode, DL, VTs, OpValues, SDFlags);

[fakepaper56]

llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

7615

getNode with SDVTList does not use SDNodeFlags directly.

SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, SDVTList VTList,
                              ArrayRef<SDValue> Ops, const SDNodeFlags Flags) {
  if (VTList.NumVTs == 1) 
    return getNode(Opcode, DL, VTList.VTs[0], Ops);

[craig.topper]

llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

7615

Can you submit a patch to fix that? It’s a bug.

[fakepaper56]

Add REQUIRES: asserts in pass-fast-math-flags-sdnode.ll.

[fakepaper56]

llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

7615

Yeah, I am willing to do that.

[fakepaper56]

After fixing getNode, pass SDNodeFlags to getNode of SDVTList version.

[craig.topper]

llvm/test/CodeGen/RISCV/pass-fast-math-flags-sdnode.ll

2

I didn't think about this before, but is it possible to use -stop-after=finalize-isel and inspect the MIR output instead? That wouldn't require an asserts build.

[fakepaper56]

llvm/test/CodeGen/RISCV/pass-fast-math-flags-sdnode.ll

2

There is no optimization of VP using fast math flags and I don't know how to make MIR print fast-math flags. The output of llc -mtriple=riscv64 -mattr=+v fa. -stop-after=finalize-isel :
%7:vrnov0 = nofpexcept PseudoVFMUL_VV_M1_MASK %8, %0, %1, $v0, killed %6, 6 /* e64 */, 1, implicit $frm

2

Could we get MIR

[craig.topper]

LGTM

llvm/test/CodeGen/RISCV/pass-fast-math-flags-sdnode.ll

2

I think we're dropping the fast math flags when we go from ISD::VP* to RISCVISD::*_VL. So my suggestion won't work without a lot more work.

We can use the debug output and REQUIRES: asserts

llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

void SelectionDAGBuilder::visitVectorPredicationIntrinsic(
   assert(EVLParamVT.isScalarInteger() && EVLParamVT.bitsGE(MVT::i32) &&
          "Unexpected target EVL type");
 
   // Request operands.
   SmallVector<SDValue, 7> OpValues;
   for (unsigned I = 0; I < VPIntrin.arg_size(); ++I) {
     auto Op = getValue(VPIntrin.getArgOperand(I));
     if (I == EVLParamPos)
       Op = DAG.getNode(ISD::ZERO_EXTEND, DL, EVLParamVT, Op);
     OpValues.push_back(Op);
   }
 
   switch (Opcode) {
   default: {
-    SDValue Result = DAG.getNode(Opcode, DL, VTs, OpValues);
+    SDNodeFlags SDFlags;
+    if (auto *FPMO = dyn_cast<FPMathOperator>(&VPIntrin))
+      SDFlags.copyFMF(*FPMO);
+    SDValue Result = DAG.getNode(Opcode, DL, VTs, OpValues, SDFlags);
     setValue(&VPIntrin, Result);
     break;
   }
   case ISD::VP_LOAD:
   case ISD::VP_GATHER:
     visitVPLoadGather(VPIntrin, ValueVTs[0], OpValues,
                       Opcode == ISD::VP_GATHER);
     break;
   case ISD::EXPERIMENTAL_VP_STRIDED_LOAD:
     visitVPStridedLoad(VPIntrin, ValueVTs[0], OpValues);
     break;

llvm/test/CodeGen/RISCV/pass-fast-math-flags-sdnode.ll

+; REQUIRES: asserts
+; RUN: llc < %s -mtriple=riscv64 -mattr=+v -debug-only=isel -o /dev/null 2>&1                        | FileCheck %s
+declare <vscale x 1 x double> @llvm.vp.fmul.nxv1f64(<vscale x 1 x double> %x, <vscale x 1 x double> %y, <vscale x 1 x i1> %m, i32 %vl)
+
+define <vscale x 1 x double> @foo(<vscale x 1 x double> %x, <vscale x 1 x double> %y, <vscale x 1 x double> %z, <vscale x 1 x i1> %m, i32 %vl) {
+; CHECK:      t14: nxv1f64 = vp_fmul nnan ninf nsz arcp contract afn reassoc t2, t4, t8, t13
+  %1 = call fast <vscale x 1 x double> @llvm.vp.fmul.nxv1f64(<vscale x 1 x double> %x, <vscale x 1 x double> %y, <vscale x 1 x i1> %m, i32 %vl)
+  ret <vscale x 1 x double> %1
+}