[NVPTX][tests] add "XFAIL: nvptx" for some tests

[i-chebykin]

Summary

Some tests failed for NVPTX target, but it seems that NVPTX will be fixed and the tests will pass.
So, just mark the tests as XFAIL

[tra]

Looks OK, though on a closer look not all the disabled tests are the fault of NVPTX. If those tests are easy to fix, I'd prefer that.
If not, I'm fine with disabling them for NVPTX, they don't seem to be particularly interesting.

llvm/test/CodeGen/Generic/addr-label.ll

6

Wrong description?
AFAICT it fails with a crash on failure to select https://godbolt.org/z/cdfE3bo4W:
Cannot select: 0x5608e9078c70: i64 = BlockAddress<@test1b, %test_label> 0

llvm/test/CodeGen/Generic/inline-asm-mem-clobber.ll

6

This test should've used CHECK-DAG as the order in which code/data is emitted is not guaranteed.
It should also have used G when it was checking for the variable name. @G is only used in a comment in the x86 assembly.

llvm/test/CodeGen/Generic/live-debug-label.ll

3

It's the test problem -- it should not have assumed basic block order.

41–44

Something like this would probably work better:

; CHECK: {{bye\.thread21|if\.then5}}:
; CHECK: DBG_LABEL !14
; Skip to the next label.
; CHECK: {{^\s+bb\.}}
; CHECK: {{bye\.thread21|if\.then5}}:
; CHECK: DBG_LABEL !14
; Skip to the next label.
; CHECK: {{^\s+bb\.}}
; CHECK-NOT: DBG_LABEL !14

[i-chebykin]

llvm/test/CodeGen/Generic/addr-label.ll

6

Right, this is a typo

llvm/test/CodeGen/Generic/live-debug-label.ll

41–44

Not sure that we can have simple test for both x86 and nvptx here
I suggest either XFAIL: nvptx or do not touch the test in this commit

[tra]

llvm/test/CodeGen/Generic/inline-asm-mem-clobber.ll

6

I think this test should be fixed instead of disabling it.

llvm/test/CodeGen/Generic/live-debug-label.ll

41–44

OK.

[i-chebykin]

I do not have commit access yet. Could someone help me to land the patch?

llvm/test/CodeGen/Generic/2009-03-17-LSR-APInt.ll

 ; RUN: llc < %s
 ; PR3806
 
+; NVPTX does not support 'alias' yet
+; XFAIL: nvptx
+
   %struct..0__pthread_mutex_s = type { i32, i32, i32, i32, i32, i32, %struct.__pthread_list_t }
   %struct.Alignment = type { i32 }
   %struct.QDesignerFormWindowInterface = type { %struct.QWidget }
   %struct.QFont = type { %struct.QFontPrivate*, i32 }
   %struct.QFontPrivate = type opaque
   %"struct.QHash<QString,QList<QAbstractExtensionFactory*> >" = type { %"struct.QHash<QString,QList<QAbstractExtensionFactory*> >::._120" }
   %"struct.QHash<QString,QList<QAbstractExtensionFactory*> >::._120" = type { %struct.QHashData* }
   %struct.QHashData = type { %"struct.QHashData::Node"*, %"struct.QHashData::Node"**, %struct.Alignment, i32, i32, i16, i16, i32, i8 }

llvm/test/CodeGen/Generic/ForceStackAlign.ll

 ; Check that stack alignment can be forced. Individual targets should test their
 ; specific implementation details.
 
 ; RUN: llc < %s -stackrealign | FileCheck %s
 ; CHECK-LABEL: @f
 ; CHECK-LABEL: @g
 
 ; Stack realignment not supported.
 ; XFAIL: sparc
 
+; NVPTX cannot select dynamic_stackalloc
+; XFAIL: nvptx
+
 define i32 @f(i8* %p) nounwind {
 entry:
   %0 = load i8, i8* %p
   %conv = sext i8 %0 to i32
   ret i32 %conv
 }
 
 define i64 @g(i32 %i) nounwind {

llvm/test/CodeGen/Generic/add-with-overflow-128.ll

 ; RUN: llc < %s
 
+; NVPTX fails to LowerFormalArguments for arg type i96
+; the arg byte size must be one of the {16, 8, 4, 2}
+; XFAIL: nvptx
+
 @ok = internal constant [4 x i8] c"%d\0A\00"
 @no = internal constant [4 x i8] c"no\0A\00"
 
 
 
 define i1 @func2(i128 zeroext %v1, i128 zeroext %v2) nounwind {
 entry:
   %t = call {i128, i1} @llvm.uadd.with.overflow.i128(i128 %v1, i128 %v2)

llvm/test/CodeGen/Generic/addr-label.ll

 ; RUN: llc %s -o - -mtriple=thumbv7-apple-darwin10
 ; RUN: llc %s -o -
 
 ; REQUIRES: arm-registered-target
 
+; NVPTX cannot select BlockAddress
+; XFAIL: nvptx
+
 ;; Reference to a label that gets deleted.
 define i8* @test1() nounwind {
 entry:
   ret i8* blockaddress(@test1b, %test_label)
 }
 
 define i32 @test1b() nounwind {
 entry:

llvm/test/CodeGen/Generic/externally_available.ll

 ; RUN: llc -verify-machine-dom-info < %s | not grep test_
 
 ; XFAIL: aix
 ; AIX system assembler default print error for undefined reference .
 ; so AIX chose to emit the available externally symbols into .s,
 ; so that users won't run into errors in situations like:
 ; clang -target powerpc-ibm-aix -xc -<<<$'extern inline __attribute__((__gnu_inline__)) void foo() {}\nvoid bar() { foo(); }' -O -Xclang -disable-llvm-passes
 
+; XFAIL: nvptx
+; unexpected emitting of the global var, while the function is not emitted as expected
+
 ; test_function should not be emitted to the .s file.
 define available_externally i32 @test_function() {
   ret i32 4
 }
 
 ; test_global should not be emitted to the .s file.
 @test_global = available_externally global i32 4
 

llvm/test/CodeGen/Generic/fpowi-promote.ll

 ; RUN: llc < %s
 
 ; PR1239
 
+; Undefined external symbol "__powisf2"
+; XFAIL: nvptx
+
 define float @test(float %tmp23302331, i32 %tmp23282329 ) {
 
 %tmp2339 = call float @llvm.powi.f32.i32( float %tmp23302331, i32 %tmp23282329 )
   ret float %tmp2339
 }
 
 declare float @llvm.powi.f32.i32(float,i32)

llvm/test/CodeGen/Generic/icmp-illegal.ll

 ; RUN: llc < %s | FileCheck %s
 
+; NVPTX fails to LowerFormalArguments for arg size > i128
+; the arg byte size must be one of the {16, 8, 4, 2}
+; XFAIL: nvptx
+
 ; CHECK-LABEL: test_ult
 define i1 @test_ult(i256 %a) nounwind {
   %1 = icmp ult i256 %a, -6432394258550908438
   ret i1 %1
 }
 
 ; CHECK-LABEL: test_ule
 define i1 @test_ule(i256 %a) nounwind {

llvm/test/CodeGen/Generic/inline-asm-mem-clobber.ll

 ; RUN: llc -O2 -no-integrated-as < %s | FileCheck %s
 
 ; XCore default subtarget does not support 8-byte alignment on stack.
 ; XFAIL: xcore
 
 @G = common global i32 0, align 4
 
 define i32 @foo(i8* %p) nounwind uwtable {
 entry:
   %p.addr = alloca i8*, align 8
   %rv = alloca i32, align 4
   store i8* %p, i8** %p.addr, align 8
   store i32 0, i32* @G, align 4
   %0 = load i8*, i8** %p.addr, align 8
 ; CHECK: blah
   %1 = call i32 asm "blah", "=r,r,~{memory}"(i8* %0) nounwind
-; CHECK: @G
+; CHECK: {{[^[:alnum:]]}}G{{[^[:alnum:]]}}
   store i32 %1, i32* %rv, align 4
   %2 = load i32, i32* %rv, align 4
   %3 = load i32, i32* @G, align 4
   %add = add nsw i32 %2, %3
   ret i32 %add
 }
 

llvm/test/CodeGen/Generic/intrinsics.ll

 ; RUN: llc < %s
 ; RUN: llc -O0 < %s
 
+; NVPTX can't select sinf(float)/sin(double)
+; XFAIL: nvptx
+
 ;; SQRT
 declare float @llvm.sqrt.f32(float)
 
 declare double @llvm.sqrt.f64(double)
 
 define double @test_sqrt(float %F) {
         %G = call float @llvm.sqrt.f32( float %F )              ; <float> [#uses=1]
         %H = fpext float %G to double           ; <double> [#uses=1]

llvm/test/CodeGen/Generic/live-debug-label.ll

 ; RUN: llc < %s -stop-after=virtregrewriter -o - | FileCheck %s
 ;
+; NVPTX produces a different order of the BBs
+; XFAIL: nvptx
+
 ; Generated with "clang++ -g -O1 -S -emit-llvm"
 ;
 ; inline bool bar(char c) {
 ;   return c >= '0' && c <= '9';
 ; }
 ;
 ; unsigned foo(const char* data,
 ;              int length,

 ;     result = 1;
 ;   }
 ; bye:
 ;   *parsing_result = result;
 ;   return result == 0 ? value : 0;
 ; }
 ;
 ; CHECK: {{^body:}}
 ; CHECK: bye.thread21:
 ; CHECK: DBG_LABEL !14
 ; CHECK: if.then5:
 ; CHECK: DBG_LABEL !14
 ; CHECK-NOT: DBG_LABEL !14
 
 $_Z3barc = comdat any
 
 ; Function Attrs: nounwind uwtable
 define dso_local i32 @_Z3fooPKciPi(i8* nocapture readonly %data, i32 %length, i32* nocapture %parsing_result) local_unnamed_addr !dbg !4 {
 entry:
   %0 = load i8, i8* %data, align 1

llvm/test/CodeGen/Generic/llc-start-stop.ll

+; NVPTX customizes the list of passes so the test cannot find what it expects
+; XFAIL: nvptx
+
 ; Note: -verify-machineinstrs is used in order to make this test compatible with EXPENSIVE_CHECKS.
 ; RUN: llc < %s -debug-pass=Structure -stop-after=loop-reduce -verify-machineinstrs -o /dev/null 2>&1 \
 ; RUN:   | FileCheck %s -check-prefix=STOP-AFTER
 ; STOP-AFTER: -loop-reduce
 ; STOP-AFTER: Dominator Tree Construction
 ; STOP-AFTER: Loop Strength Reduction
 ; STOP-AFTER-NEXT: Verify generated machine code
 ; STOP-AFTER-NEXT: MIR Printing Pass