CodeGen: Replace some uses of LLVMTargetMachine with TargetMachine

[arsenm]

Summary

All target knowledge should be in the TargetMachine base
class. LLVMTargetMachine extends with pass machinery, which most code
should not have access to.

[echristo]

llvm/include/llvm/CodeGen/MachineModuleInfo.h

127

This (and the below) with a reference are a little disturbing. (I know you didn't change it, but...)

llvm/include/llvm/Target/TargetMachine.h

137

I'm curious what this changes here versus using LLVMTargetMachine. It's been a while since I've looked.

[arsenm]

llvm/include/llvm/Target/TargetMachine.h

137

It doesn't really change anything, but this one doesn't fit the theme of the what LLVMTargetMachine adds. This is core target information and it doesn't make much since to have it in LLVMTargetMachine, which only adds pass machinery controls.

[arsenm]

ping

[MatzeB]

All target knowledge should be in the TargetMachine base class. LLVMTargetMachine extends with pass machinery, which most code should not have access to.

My understanding was that TargetMachine is the public/outside interface (for frontends etc.). And that LLVMTargetMachine is a concrete subclass for all targets implemented using lib/CodeGen. In theory you can implement a complete target from scratch without using lib/CodeGen and then you would implement TargetMachine without using LLVMTargetMachine.

So to me this change looks confusing/unnecessary, since any code within lib/CodeGen is totally free to use LLVMTargetMachine in my interpretation...

Requesting changes for clarification

[MatzeB]

llvm/include/llvm/Target/TargetMachine.h

137

This seems like an implementation detail of lib/CodeGen so I think it should stay withint LLVMTargetMachine.

[arsenm]

In D123964#3476294, @MatzeB wrote:

All target knowledge should be in the TargetMachine base class. LLVMTargetMachine extends with pass machinery, which most code should not have access to.

My understanding was that TargetMachine is the public/outside interface (for frontends etc.). And that LLVMTargetMachine is a concrete subclass for all targets implemented using lib/CodeGen

This sounds backwards to me. LLVMTargetMachine extends with pieces frontends need to use the target (e.g. createMCStreamer). TargetMachine is the base target info class codegen does use. What you're saying would make more sense if the relationship was inverted?

The current situation is that I'm not sure any code makes a practical distinction here. For example to construct a MachineModuleInfo, the existing users downcast from TargetMachine to LLVMTargetMachine

[MatzeB]

This sounds backwards to me. LLVMTargetMachine extends with pieces frontends need to use the target (e.g. createMCStreamer). TargetMachine is the base target info class codegen does use. What you're saying would make more sense if the relationship was inverted?

I remember spending quite a while wondering about this myself; I couldn't find anyone who could actually explain the TargetMachine / LLVMTargetMachine split to me.

So my reading is mostly based on the fact that the TargetRegistry API that frontends need to use to construct a target and especially the createTargetMachine() call there returns a TargetMachine and not an LLVMTargetMachine. So it seemed to me like LLVMTargetMachine was intended as an implementation detail for lib/CodeGen. You can also see clang code only dealing with llvm::TargetMachine but not LLVMTargetMachine.

I agree that this is all convoluted and not consistent and becomes in no way clear given the class names. I'm currently not aware of any code implementing a TargetMachine but not LLVMTargetMachine. So maybe we should just kill this whole discussion and merge the two classes into just TargetMachine?

It seems I actually discussed this before in https://lists.llvm.org/pipermail/llvm-dev/2017-October/thread.html#117907 and we had no opposition for moving the two classes. Seems I just never got around to actually do it...

[MatzeB]

It seems I did try to merge the two in https://reviews.llvm.org/D38489 / https://github.com/llvm/llvm-project/commit/3a9c114b2418472b16276e95d3f657735926dddb but ended up reverting in bb8507e63c42212c3753c0df069ec16a52652247 (which admittedly I'm not sure I understand the problem anymore now...)

[MatzeB]

The discussion in https://reviews.llvm.org/D38489 seems to indicate that the problem is that some users/binaries link libTarget but not libCodeGen and they expect TargetMachine to work but not LLVMTargetMachine.

[arsenm]

In D123964#3477815, @MatzeB wrote:

The discussion in https://reviews.llvm.org/D38489 seems to indicate that the problem is that some users/binaries link libTarget but not libCodeGen and they expect TargetMachine to work but not LLVMTargetMachine.

So based on the uses with libCodeGen=TargetMachine, libTarget=LLVMTargetMachine,

usesPhysRegsForValues and unqualifiedInlineAsmVariant ared used in lib/CodeGen, so belong in TargetMachine which is what this patch does. It also tightens some of the references in libCodeGen to TargetMachine, so this patch is in line with that reasoning?

[MatzeB]

No?

• TargetMachine is defined in libTarget (lib/Target/TargetMachine.cpp)
• LLVMTargetMachine is defined in libCodegen (lib/CodeGen/LLVMTargetMachine.cpp) and libCodeGen links to libTarget (but not the other way round).

[MatzeB]

Note that libTarget is not the same as actual targets like lib/Target/X86... The actual targets do link against libCodeGen... (it's all so confusing)

llvm/include/llvm/CodeGen/MachineFunction.h

 class DebugLoc;
 struct DenormalMode;
 class DIExpression;
 class DILocalVariable;
 class DILocation;
 class Function;
 class GISelChangeObserver;
 class GlobalValue;
-class LLVMTargetMachine;
 class MachineConstantPool;
 class MachineFrameInfo;
 class MachineFunction;
 class MachineJumpTableInfo;
 class MachineModuleInfo;
 class MachineRegisterInfo;
 class MCContext;
 class MCInstrDesc;
 class MCSymbol;
 class MCSection;
 class Pass;
 class PseudoSourceValueManager;
 class raw_ostream;
 class SlotIndexes;
 class StringRef;
+class TargetMachine;
 class TargetRegisterClass;
 class TargetSubtargetInfo;
 struct WasmEHFuncInfo;
 struct WinEHFuncInfo;
 
 template <> struct ilist_alloc_traits<MachineBasicBlock> {
   void deleteNode(MachineBasicBlock *MBB);
 };
struct LandingPadInfo {
   std::vector<int> TypeIds;                // List of type ids (filters negative).
 
   explicit LandingPadInfo(MachineBasicBlock *MBB)
       : LandingPadBlock(MBB) {}
 };
 
 class LLVM_EXTERNAL_VISIBILITY MachineFunction {
   Function &F;
-  const LLVMTargetMachine &Target;
+  const TargetMachine &Target;
   const TargetSubtargetInfo *STI;
   MCContext &Ctx;
   MachineModuleInfo &MMI;
 
   // RegInfo - Information about each register in use in the function.
   MachineRegisterInfo *RegInfo;
 
   // Used to keep track of target-specific per-machine function information for
public:
   /// Returns true if the function's variable locations should be tracked with
   /// instruction referencing.
   bool useDebugInstrRef() const;
 
   /// A reserved operand number representing the instructions memory operand,
   /// for instructions that have a stack spill fused into them.
   const static unsigned int DebugOperandMemNumber;
 
-  MachineFunction(Function &F, const LLVMTargetMachine &Target,
+  MachineFunction(Function &F, const TargetMachine &Target,
                   const TargetSubtargetInfo &STI, unsigned FunctionNum,
                   MachineModuleInfo &MMI);
   MachineFunction(const MachineFunction &) = delete;
   MachineFunction &operator=(const MachineFunction &) = delete;
   ~MachineFunction();
 
   /// Reset the instance as if it was just created.
   void reset() {
public:
 
   void setBBSectionsType(BasicBlockSection V) { BBSectionsType = V; }
 
   /// Assign IsBeginSection IsEndSection fields for basic blocks in this
   /// function.
   void assignBeginEndSections();
 
   /// getTarget - Return the target machine this machine code is compiled with
-  const LLVMTargetMachine &getTarget() const { return Target; }
+  const TargetMachine &getTarget() const { return Target; }
 
   /// getSubtarget - Return the subtarget for which this machine code is being
   /// compiled.
   const TargetSubtargetInfo &getSubtarget() const { return *STI; }
 
   /// getSubtarget - This method returns a pointer to the specified type of
   /// TargetSubtargetInfo.  In debug builds, it verifies that the object being
   /// returned is of the correct type.

llvm/include/llvm/CodeGen/MachineModuleInfo.h

 #include <memory>
 #include <utility>
 #include <vector>
 
 namespace llvm {
 
 class BasicBlock;
 class Function;
-class LLVMTargetMachine;
 class MachineFunction;
 class Module;
 class MCSymbol;
+class TargetMachine;
 
 //===----------------------------------------------------------------------===//
 /// This class can be derived from and used by targets to hold private
 /// target-specific information for each Module.  Objects of type are
 /// accessed/created with MachineModuleInfo::getObjFileInfo and destroyed when
 /// the MachineModuleInfo is destroyed.
 ///
 class MachineModuleInfoImpl {

 /// This class contains meta information specific to a module.  Queries can be
 /// made by different debugging and exception handling schemes and reformated
 /// for specific use.
 ///
 class MachineModuleInfo {
   friend class MachineModuleInfoWrapperPass;
   friend class MachineModuleAnalysis;
 
-  const LLVMTargetMachine &TM;
+  const TargetMachine &TM;
 
   /// This is the MCContext used for the entire code generator.
   MCContext Context;
   // This is an external context, that if assigned, will be used instead of the
   // internal context.
   MCContext *ExternalContext = nullptr;
 
   /// This is the LLVM Module being worked on.
class MachineModuleInfo {
   /// Next unique number available for a MachineFunction.
   unsigned NextFnNum = 0;
   const Function *LastRequest = nullptr; ///< Used for shortcut/cache.
   MachineFunction *LastResult = nullptr; ///< Used for shortcut/cache.
 
   MachineModuleInfo &operator=(MachineModuleInfo &&MMII) = delete;
 
 public:
-  explicit MachineModuleInfo(const LLVMTargetMachine *TM = nullptr);
+  explicit MachineModuleInfo(const TargetMachine *TM = nullptr);
 
-  explicit MachineModuleInfo(const LLVMTargetMachine *TM,
-                             MCContext *ExtContext);
+  explicit MachineModuleInfo(const TargetMachine *TM, MCContext *ExtContext);
 
   MachineModuleInfo(MachineModuleInfo &&MMII);
 
   ~MachineModuleInfo();
 
   void initialize();
   void finalize();
 
-  const LLVMTargetMachine &getTarget() const { return TM; }
+  const TargetMachine &getTarget() const { return TM; }
 
   const MCContext &getContext() const {
     return ExternalContext ? *ExternalContext : Context;
   }
   MCContext &getContext() {
     return ExternalContext ? *ExternalContext : Context;
   }
 
public:
   }
 }; // End class MachineModuleInfo
 
 class MachineModuleInfoWrapperPass : public ImmutablePass {
   MachineModuleInfo MMI;
 
 public:
   static char ID; // Pass identification, replacement for typeid
-  explicit MachineModuleInfoWrapperPass(const LLVMTargetMachine *TM = nullptr);
+  explicit MachineModuleInfoWrapperPass(const TargetMachine *TM = nullptr);
 
-  explicit MachineModuleInfoWrapperPass(const LLVMTargetMachine *TM,
+  explicit MachineModuleInfoWrapperPass(const TargetMachine *TM,
                                         MCContext *ExtContext);
 
   // Initialization and Finalization
   bool doInitialization(Module &) override;
   bool doFinalization(Module &) override;
 
   MachineModuleInfo &getMMI() { return MMI; }
   const MachineModuleInfo &getMMI() const { return MMI; }
 };
 
 /// An analysis that produces \c MachineInfo for a module.
 class MachineModuleAnalysis : public AnalysisInfoMixin<MachineModuleAnalysis> {
   friend AnalysisInfoMixin<MachineModuleAnalysis>;
   static AnalysisKey Key;
 
-  const LLVMTargetMachine *TM;
+  const TargetMachine *TM;
 
 public:
   /// Provide the result type for this analysis pass.
   using Result = MachineModuleInfo;
 
-  MachineModuleAnalysis(const LLVMTargetMachine *TM) : TM(TM) {}
+  MachineModuleAnalysis(const TargetMachine *TM) : TM(TM) {}
 
   /// Run the analysis pass and produce machine module information.
   MachineModuleInfo run(Module &M, ModuleAnalysisManager &);
 };
 
 } // end namespace llvm
 
 #endif // LLVM_CODEGEN_MACHINEMODULEINFO_H

llvm/include/llvm/CodeGen/RegisterUsageInfo.h

 #include "llvm/Pass.h"
 #include "llvm/PassRegistry.h"
 #include <cstdint>
 #include <vector>
 
 namespace llvm {
 
 class Function;
-class LLVMTargetMachine;
+class TargetMachine;
 
 class PhysicalRegisterUsageInfo : public ImmutablePass {
 public:
   static char ID;
 
   PhysicalRegisterUsageInfo() : ImmutablePass(ID) {
     PassRegistry &Registry = *PassRegistry::getPassRegistry();
     initializePhysicalRegisterUsageInfoPass(Registry);
   }
 
   /// Set TargetMachine which is used to print analysis.
-  void setTargetMachine(const LLVMTargetMachine &TM);
+  void setTargetMachine(const TargetMachine &TM);
 
   bool doInitialization(Module &M) override;
 
   bool doFinalization(Module &M) override;
 
   /// To store RegMask for given Function *.
   void storeUpdateRegUsageInfo(const Function &FP,
                                ArrayRef<uint32_t> RegMask);
 
   /// To query stored RegMask for given Function *, it will returns ane empty
   /// array if function is not known.
   ArrayRef<uint32_t> getRegUsageInfo(const Function &FP);
 
   void print(raw_ostream &OS, const Module *M = nullptr) const override;
 
 private:
   /// A Dense map from Function * to RegMask.
   /// In RegMask 0 means register used (clobbered) by function.
   /// and 1 means content of register will be preserved around function call.
   DenseMap<const Function *, std::vector<uint32_t>> RegMasks;
 
-  const LLVMTargetMachine *TM;
+  const TargetMachine *TM;
 };
 
 } // end namespace llvm
 
 #endif // LLVM_CODEGEN_REGISTERUSAGEINFO_H

llvm/include/llvm/CodeGen/ScheduleDAG.h

public:
 
     unsigned getCurCycle() const {
       return CurCycle;
     }
   };
 
   class ScheduleDAG {
   public:
-    const LLVMTargetMachine &TM;        ///< Target processor
+    const TargetMachine &TM;            ///< Target processor
     const TargetInstrInfo *TII;         ///< Target instruction information
     const TargetRegisterInfo *TRI;      ///< Target processor register info
     MachineFunction &MF;                ///< Machine function
     MachineRegisterInfo &MRI;           ///< Virtual/real register map
     std::vector<SUnit> SUnits;          ///< The scheduling units.
     SUnit EntrySU;                      ///< Special node for the region entry.
     SUnit ExitSU;                       ///< Special node for the region exit.
 

llvm/include/llvm/Target/TargetMachine.h

public:
 
   const Target &getTarget() const { return TheTarget; }
 
   const Triple &getTargetTriple() const { return TargetTriple; }
   StringRef getTargetCPU() const { return TargetCPU; }
   StringRef getTargetFeatureString() const { return TargetFS; }
   void setTargetFeatureString(StringRef FS) { TargetFS = std::string(FS); }
 
+  /// True if the target uses physical regs (as nearly all targets do). False
+  /// for stack machines such as WebAssembly and other virtual-register
+  /// machines. If true, all vregs must be allocated before PEI. If false, then
+  /// callee-save register spilling and scavenging are not needed or used. If
+  /// false, implicitly defined registers will still be assumed to be physical
+  /// registers, except that variadic defs will be allocated vregs.
+  virtual bool usesPhysRegsForValues() const { return true; }
+
   /// Virtual method implemented by subclasses that returns a reference to that
   /// target's TargetSubtargetInfo-derived member variable.
   virtual const TargetSubtargetInfo *getSubtargetImpl(const Function &) const {
     return nullptr;
   }
   virtual TargetLoweringObjectFile *getObjFileLowering() const {
     return nullptr;
   }
void getNameWithPrefix(SmallVectorImpl<char> &Name, const GlobalValue *GV,
                          Mangler &Mang, bool MayAlwaysUsePrivate = false) const;
   MCSymbol *getSymbol(const GlobalValue *GV) const;
 
   /// The integer bit size to use for SjLj based exception handling.
   static constexpr unsigned DefaultSjLjDataSize = 32;
   virtual unsigned getSjLjDataSize() const { return DefaultSjLjDataSize; }
 
   static std::pair<int, int> parseBinutilsVersion(StringRef Version);
+
+  /// The default variant to use in unqualified `asm` instructions.
+  /// If this returns 0, `asm "$(foo$|bar$)"` will evaluate to `asm "foo"`.
+  virtual int unqualifiedInlineAsmVariant() const { return 0; }
 };
 
 /// This class describes a target machine that is implemented with the LLVM
 /// target-independent code generator.
 ///
 class LLVMTargetMachine : public TargetMachine {
 protected: // Can only create subclasses.
   LLVMTargetMachine(const Target &T, StringRef DataLayoutString,
public:
   bool addAsmPrinter(PassManagerBase &PM, raw_pwrite_stream &Out,
                      raw_pwrite_stream *DwoOut, CodeGenFileType FileType,
                      MCContext &Context);
 
   Expected<std::unique_ptr<MCStreamer>>
   createMCStreamer(raw_pwrite_stream &Out, raw_pwrite_stream *DwoOut,
                    CodeGenFileType FileType, MCContext &Ctx);
 
-  /// True if the target uses physical regs (as nearly all targets do). False
-  /// for stack machines such as WebAssembly and other virtual-register
-  /// machines. If true, all vregs must be allocated before PEI. If false, then
-  /// callee-save register spilling and scavenging are not needed or used. If
-  /// false, implicitly defined registers will still be assumed to be physical
-  /// registers, except that variadic defs will be allocated vregs.
-  virtual bool usesPhysRegsForValues() const { return true; }
-
   /// True if the target wants to use interprocedural register allocation by
   /// default. The -enable-ipra flag can be used to override this.
   virtual bool useIPRA() const {
     return false;
   }
-
-  /// The default variant to use in unqualified `asm` instructions.
-  /// If this returns 0, `asm "$(foo$|bar$)"` will evaluate to `asm "foo"`.
-  virtual int unqualifiedInlineAsmVariant() const { return 0; }
 };
 
 /// Helper method for getting the code model, returning Default if
 /// CM does not have a value. The tiny and kernel models will produce
 /// an error, so targets that support them or require more complex codemodel
 /// selection logic should implement and call their own getEffectiveCodeModel.
 inline CodeModel::Model getEffectiveCodeModel(Optional<CodeModel::Model> CM,
                                               CodeModel::Model Default) {

llvm/lib/CodeGen/MIRParser/MIRParser.cpp

Function *MIRParserImpl::createDummyFunction(StringRef Name, Module &M) {
   return F;
 }
 
 bool MIRParserImpl::parseMachineFunction(Module &M, MachineModuleInfo &MMI) {
   // Parse the yaml.
   yaml::MachineFunction YamlMF;
   yaml::EmptyContext Ctx;
 
-  const LLVMTargetMachine &TM = MMI.getTarget();
+  const TargetMachine &TM = MMI.getTarget();
   YamlMF.MachineFuncInfo = std::unique_ptr<yaml::MachineFunctionInfo>(
       TM.createDefaultFuncInfoYAML());
 
   yaml::yamlize(In, YamlMF, false, Ctx);
   if (In.error())
     return true;
 
   // Search for the corresponding IR function.
void MIRParserImpl::computeFunctionProperties(MachineFunction &MF) {
   if (MRI.getNumVirtRegs() == 0)
     Properties.set(MachineFunctionProperties::Property::NoVRegs);
 }
 
 bool MIRParserImpl::initializeCallSiteInfo(
     PerFunctionMIParsingState &PFS, const yaml::MachineFunction &YamlMF) {
   MachineFunction &MF = PFS.MF;
   SMDiagnostic Error;
-  const LLVMTargetMachine &TM = MF.getTarget();
+  const TargetMachine &TM = MF.getTarget();
   for (auto YamlCSInfo : YamlMF.CallSitesInfo) {
     yaml::CallSiteInfo::MachineInstrLoc MILoc = YamlCSInfo.CallLocation;
     if (MILoc.BlockNum >= MF.size())
       return error(Twine(MF.getName()) +
                    Twine(" call instruction block out of range.") +
                    " Unable to reference bb:" + Twine(MILoc.BlockNum));
     auto CallB = std::next(MF.begin(), MILoc.BlockNum);
     if (MILoc.Offset >= CallB->size())
if (parseMachineInstructions(PFS, InsnStr, Error)) {
     return true;
   }
   PFS.SM = &SM;
 
   if (setupRegisterInfo(PFS, YamlMF))
     return true;
 
   if (YamlMF.MachineFuncInfo) {
-    const LLVMTargetMachine &TM = MF.getTarget();
+    const TargetMachine &TM = MF.getTarget();
     // Note this is called after the initial constructor of the
     // MachineFunctionInfo based on the MachineFunction, which may depend on the
     // IR.
 
     SMRange SrcRange;
     if (TM.parseMachineFunctionInfo(*YamlMF.MachineFuncInfo, PFS, Error,
                                     SrcRange)) {
       return error(Error, SrcRange);

llvm/lib/CodeGen/MachineFunction.cpp

 
 static inline unsigned getFnStackAlignment(const TargetSubtargetInfo *STI,
                                            const Function &F) {
   if (auto MA = F.getFnStackAlign())
     return MA->value();
   return STI->getFrameLowering()->getStackAlign().value();
 }
 
-MachineFunction::MachineFunction(Function &F, const LLVMTargetMachine &Target,
+MachineFunction::MachineFunction(Function &F, const TargetMachine &Target,
                                  const TargetSubtargetInfo &STI,
                                  unsigned FunctionNum, MachineModuleInfo &mmi)
     : F(F), Target(Target), STI(&STI), Ctx(mmi.getContext()), MMI(mmi) {
   FunctionNumber = FunctionNum;
   init();
 }
 
 void MachineFunction::handleInsertion(MachineInstr &MI) {

llvm/lib/CodeGen/MachineModuleInfo.cpp

: TM(std::move(MMI.TM)),
       MachineFunctions(std::move(MMI.MachineFunctions)) {
   Context.setObjectFileInfo(MMI.TM.getObjFileLowering());
   ObjFileMMI = MMI.ObjFileMMI;
   CurCallSite = MMI.CurCallSite;
   ExternalContext = MMI.ExternalContext;
   TheModule = MMI.TheModule;
 }
 
-MachineModuleInfo::MachineModuleInfo(const LLVMTargetMachine *TM)
+MachineModuleInfo::MachineModuleInfo(const TargetMachine *TM)
     : TM(*TM), Context(TM->getTargetTriple(), TM->getMCAsmInfo(),
                        TM->getMCRegisterInfo(), TM->getMCSubtargetInfo(),
                        nullptr, nullptr, false) {
   Context.setObjectFileInfo(TM->getObjFileLowering());
   initialize();
 }
 
-MachineModuleInfo::MachineModuleInfo(const LLVMTargetMachine *TM,
+MachineModuleInfo::MachineModuleInfo(const TargetMachine *TM,
                                      MCContext *ExtContext)
     : TM(*TM), Context(TM->getTargetTriple(), TM->getMCAsmInfo(),
                        TM->getMCRegisterInfo(), TM->getMCSubtargetInfo(),
                        nullptr, nullptr, false),
       ExternalContext(ExtContext) {
   Context.setObjectFileInfo(TM->getObjFileLowering());
   initialize();
 }

 
 char FreeMachineFunction::ID;
 
 FunctionPass *llvm::createFreeMachineFunctionPass() {
   return new FreeMachineFunction();
 }
 
 MachineModuleInfoWrapperPass::MachineModuleInfoWrapperPass(
-    const LLVMTargetMachine *TM)
+    const TargetMachine *TM)
     : ImmutablePass(ID), MMI(TM) {
   initializeMachineModuleInfoWrapperPassPass(*PassRegistry::getPassRegistry());
 }
 
 MachineModuleInfoWrapperPass::MachineModuleInfoWrapperPass(
-    const LLVMTargetMachine *TM, MCContext *ExtContext)
+    const TargetMachine *TM, MCContext *ExtContext)
     : ImmutablePass(ID), MMI(TM, ExtContext) {
   initializeMachineModuleInfoWrapperPassPass(*PassRegistry::getPassRegistry());
 }
 
 // Handle the Pass registration stuff necessary to use DataLayout's.
 INITIALIZE_PASS(MachineModuleInfoWrapperPass, "machinemoduleinfo",
                 "Machine Module Information", false, false)
 char MachineModuleInfoWrapperPass::ID = 0;

llvm/lib/CodeGen/RegUsageInfoCollector.cpp

static bool isCallableFunction(const MachineFunction &MF) {
   default:
     return true;
   }
 }
 
 bool RegUsageInfoCollector::runOnMachineFunction(MachineFunction &MF) {
   MachineRegisterInfo *MRI = &MF.getRegInfo();
   const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
-  const LLVMTargetMachine &TM = MF.getTarget();
+  const TargetMachine &TM = MF.getTarget();
 
   LLVM_DEBUG(dbgs() << " -------------------- " << getPassName()
                     << " -------------------- \nFunction Name : "
                     << MF.getName() << '\n');
 
   // Analyzing the register usage may be expensive on some targets.
   if (!isCallableFunction(MF)) {
     LLVM_DEBUG(dbgs() << "Not analyzing non-callable function\n");

llvm/lib/CodeGen/RegisterUsageInfo.cpp

static cl::opt<bool> DumpRegUsage(
     "print-regusage", cl::init(false), cl::Hidden,
     cl::desc("print register usage details collected for analysis."));
 
 INITIALIZE_PASS(PhysicalRegisterUsageInfo, "reg-usage-info",
                 "Register Usage Information Storage", false, true)
 
 char PhysicalRegisterUsageInfo::ID = 0;
 
-void PhysicalRegisterUsageInfo::setTargetMachine(const LLVMTargetMachine &TM) {
+void PhysicalRegisterUsageInfo::setTargetMachine(const TargetMachine &TM) {
   this->TM = &TM;
 }
 
 bool PhysicalRegisterUsageInfo::doInitialization(Module &M) {
   RegMasks.grow(M.size());
   return false;
 }
 

llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp

if (MCID.TSFlags & NVPTXII::IsTexFlag) {
     return false;
   }
 
   return false;
 }
 
 void NVPTXAsmPrinter::lowerImageHandleSymbol(unsigned Index, MCOperand &MCOp) {
   // Ewwww
-  LLVMTargetMachine &TM = const_cast<LLVMTargetMachine&>(MF->getTarget());
+  TargetMachine &TM = const_cast<TargetMachine &>(MF->getTarget());
   NVPTXTargetMachine &nvTM = static_cast<NVPTXTargetMachine&>(TM);
   const NVPTXMachineFunctionInfo *MFI = MF->getInfo<NVPTXMachineFunctionInfo>();
   const char *Sym = MFI->getImageHandleSymbol(Index);
   std::string *SymNamePtr =
     nvTM.getManagedStrPool()->getManagedString(Sym);
   MCOp = GetSymbolRef(OutContext.getOrCreateSymbol(StringRef(*SymNamePtr)));
 }