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[llvm-objdump] Implemented PrintBranchImmAsAddress for MIPS
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Authored by kpdev42 on Apr 14 2022, 1:34 AM.

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Summary

Updated MipsInstPrinter to print absolute hex offsets for branch instructions.
It is necessary to make the llvm-objdump output close to the gnu objdump output.
This implementation is based on the implementation for RISC-V.

OS Laboratory. Huawei Russian Research Institute. Saint-Petersburg

Diff Detail

Event Timeline

kpdev42 created this revision.Apr 14 2022, 1:34 AM
Herald added a project: Restricted Project. · View Herald TranscriptApr 14 2022, 1:34 AM
kpdev42 requested review of this revision.Apr 14 2022, 1:34 AM
kpdev42 updated this revision to Diff 423024.Apr 14 2022, 11:08 PM
  • Updated jal and jalx instructions
  • Fixed lld tests
  • Rebased
MaskRay added inline comments.Apr 15 2022, 12:10 AM
lld/test/ELF/mips-jalr-non-functions.s
57

b {{.*}} <untyped>

Use patterns to make test updating smooth when we need to adjust the layout.

Use this pattern for all lld/test/ELF tests.

kpdev42 updated this revision to Diff 423058.Apr 15 2022, 2:36 AM

Updated lld tests. Please note I have used the mask instead of annotated offsets. I did not use the mask where the offset value is important (relocs, etc.)

kpdev42 marked an inline comment as done.Apr 15 2022, 2:36 AM
MaskRay accepted this revision.Apr 15 2022, 9:43 AM

Looks great!

llvm/lib/Target/Mips/MCTargetDesc/MipsInstPrinter.cpp
172
247–250

The idiom is to prefer it to the conditional operator if the return value is not used.

ditto below

This revision is now accepted and ready to land.Apr 15 2022, 9:43 AM
This revision was landed with ongoing or failed builds.Apr 15 2022, 2:48 PM
This revision was automatically updated to reflect the committed changes.
sdardis added inline comments.Apr 15 2022, 4:01 PM
llvm/lib/Target/Mips/MicroMipsInstrInfo.td
1328

This line is incorrect or a spurious change. Placing this alias here would (attempt to) produce a MIPS standard encoded instruction of sll rather than a microMIPS encoded instruction.

slydiman added inline comments.Apr 16 2022, 8:03 AM
llvm/lib/Target/Mips/MicroMipsInstrInfo.td
1328

Note removing this line breakes the following tests:

llvm/test/MC/Mips/cprestore-noreorder.s
llvm/test/MC/Mips/micromips-fpu-instructions.s
llvm/test/MC/Mips/micromips-branch-fixup.s
llvm/test/MC/Mips/micromips-jump26.s
llvm/test/MC/Mips/micromips-16-bit-instructions.s
llvm/test/MC/Mips/micromips-jump-instructions.s
llvm/test/MC/Mips/micromips-branch-instructions.s
llvm/test/CodeGen/Mips/atomic.ll
llvm/test/CodeGen/Mips/llvm-ir/urem.ll
llvm/test/CodeGen/Mips/llvm-ir/srem.ll
llvm/test/CodeGen/Mips/llvm-ir/udiv.ll
llvm/test/CodeGen/Mips/llvm-ir/sdiv.ll
llvm/test/CodeGen/Mips/llvm-ir/fptosi.ll
llvm/test/CodeGen/Mips/longbranch.ll
llvm/test/CodeGen/Mips/blez_bgez.ll
llvm/test/CodeGen/Mips/micromips-mtc-mfc.ll
llvm/test/CodeGen/Mips/micromips-sizereduction/micromips-movep.ll
llvm/test/CodeGen/Mips/micromips-sizereduction/micromips-lwp-swp.ll
llvm/test/CodeGen/Mips/pseudo-jump-fill.ll

sll $zero, $zero, 0 instead of nop [0x00,0x00,0x00,0x00]