[PowerPC] map hardware loop intrinsics to PowerPC pseudo instructions.

[shchenz]

Summary

This is based on D122125. In D122125, we added a new post-isel pass to expand two new ctr loop pseudo instructions MTCTR8Pseudo and DecreaseCTR8Pseudo.

This patch maps hardware loop intrinsics loop_decrement and set_loop_iteration to the new PowerPC pseudo instructions, so that the hardware loop intrinsics will be expanded to normal cmp+branch form or ctrloop form based on the CTR register usage on MIR level.

We reuse legacy MTCTR8loop and update DecreaseCTR8Pseudo to DecreaseCTR8loop as well.

We still need another patch to remove the IR level CTR clobber check codes in PPCTargetTransformInfo.cpp

[shchenz]

gentle ping

[shchenz]

gentle ping

[shchenz]

gentle ping

[shchenz]

rebase

[shchenz]

gentle ping

[lkail]

Some llc LLVM IR tests are expected to be added and better run with -stop-after=finalize-isel so that we can observe how PPCCTR pseudos are generated.

llvm/lib/Target/PowerPC/PPCCTRLoops.cpp

10

Can we make it in another NFC patch?

[shchenz]

add some cases after ISEL

[shchenz]

Some llc LLVM IR tests are expected to be added and better run with -stop-after=finalize-isel so that we can observe how PPCCTR pseudos are generated.

Thanks for review.

I added some cases to show the change after ISEL with/without this patch. However I think for this patch, the best way to verify the functionality is that there is no ctr loop regression after this patch. Before the change, if we generate MTCTRloop, we know that it must be a CTR loop. But after the patch, it is not the case, we may revert the CTR loop pseudos to normal cmp+branch loop.

In the coming change related to Hardware Loop pass(in PPCTargetTransformInfo.cpp), I assume we should be able to generate more CTR loops as now we have more accurate info about CTR clobbers after ISEL.

llvm/lib/Target/PowerPC/PPCCTRLoops.cpp

10

Hmm, for this case, we can not rename the pseudo instruction in another NFC patch. MTCTRloop can be selected in ISEL and if we recognize MTCTRloop instead of MTCTRPseudo here, we have to also make ISEL generate DecreaseCTRPseudo too. Otherwise this is not a valid CTR loop.

[shchenz]

gentle ping.

[lkail]

LGTM as tests are added and conceptual MTCTRPseudo has been replaced by concrete MTCTRloop.

[chapuni]

llvm/lib/Target/PowerPC/PPCCTRLoops.cpp

347

Preheader lost all users with -Asserts, to cause warning.

[shchenz]

llvm/lib/Target/PowerPC/PPCCTRLoops.cpp

347

Thanks! committed 22e475f5ac237dfebbb3cd2b3306a17d3b2a53ce

llvm/lib/Target/PowerPC/PPCCTRLoops.cpp

 //===-- PPCCTRLoops.cpp - Generate CTR loops ------------------------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 // This pass generates machine instructions for the CTR loops related pseudos:
-// 1: MTCTRPseudo/DecreaseCTRPseudo
-// 2: MTCTR8Pseudo/DecreaseCTR8Pseudo
+// 1: MTCTRloop/DecreaseCTRloop
+// 2: MTCTR8loop/DecreaseCTR8loop
 //
 // If a CTR loop can be generated:
-// 1: MTCTRPseudo/MTCTR8Pseudo will be converted to "mtctr"
-// 2: DecreaseCTRPseudo/DecreaseCTR8Pseudo will be converted to "bdnz/bdz" and
+// 1: MTCTRloop/MTCTR8loop will be converted to "mtctr"
+// 2: DecreaseCTRloop/DecreaseCTR8loop will be converted to "bdnz/bdz" and
 //    its user branch instruction can be deleted.
 //
 // If a CTR loop can not be generated due to clobber of CTR:
-// 1: MTCTRPseudo/MTCTR8Pseudo can be deleted.
-// 2: DecreaseCTRPseudo/DecreaseCTR8Pseudo will be converted to "addi -1" and
+// 1: MTCTRloop/MTCTR8loop can be deleted.
+// 2: DecreaseCTRloop/DecreaseCTR8loop will be converted to "addi -1" and
 //    a "cmplwi/cmpldi".
 //
 // This pass runs just before register allocation, because we don't want
-// register allocator to allocate register for DecreaseCTRPseudo if a CTR can be
+// register allocator to allocate register for DecreaseCTRloop if a CTR can be
 // generated or if a CTR loop can not be generated, we don't have any condition
 // register for the new added "cmplwi/cmpldi".
 //
 //===----------------------------------------------------------------------===//
 
 #include "PPC.h"
 #include "PPCInstrInfo.h"
 #include "PPCSubtarget.h"
for (auto I = ML->begin(), E = ML->end(); I != E; ++I)
     Changed |= processLoop(*I);
 
   // If any inner loop is changed, outter loop must be without hardware loop
   // intrinsics.
   if (Changed)
     return true;
 
   auto IsLoopStart = [](MachineInstr &MI) {
-    return MI.getOpcode() == PPC::MTCTRPseudo ||
-           MI.getOpcode() == PPC::MTCTR8Pseudo;
+    return MI.getOpcode() == PPC::MTCTRloop ||
+           MI.getOpcode() == PPC::MTCTR8loop;
   };
 
   auto SearchForStart =
       [&IsLoopStart](MachineBasicBlock *MBB) -> MachineInstr * {
     for (auto &MI : *MBB) {
       if (IsLoopStart(MI))
         return &MI;
     }
     return nullptr;
   };
 
   MachineInstr *Start = nullptr;
   MachineInstr *Dec = nullptr;
   bool InvalidCTRLoop = false;
 
   MachineBasicBlock *Preheader = ML->getLoopPreheader();
-  // If there is no preheader for this loop, there must be no MTCTRPseudo
+  // If there is no preheader for this loop, there must be no MTCTRloop
   // either.
   if (!Preheader)
     return false;
 
   Start = SearchForStart(Preheader);
   // This is not a CTR loop candidate.
   if (!Start)
     return false;
if (isCTRClobber(&*I, /* CheckReads */ true)) {
       InvalidCTRLoop = true;
       break;
     }
 
   // Find the CTR loop components and decide whether or not to fall back to a
   // normal loop.
   for (auto *MBB : reverse(ML->getBlocks())) {
     for (auto &MI : *MBB) {
-      if (MI.getOpcode() == PPC::DecreaseCTRPseudo ||
-          MI.getOpcode() == PPC::DecreaseCTR8Pseudo)
+      if (MI.getOpcode() == PPC::DecreaseCTRloop ||
+          MI.getOpcode() == PPC::DecreaseCTR8loop)
         Dec = &MI;
       else if (!InvalidCTRLoop)
         // If any instruction clobber CTR, then we can not generate a CTR loop.
         InvalidCTRLoop |= isCTRClobber(&MI, /* CheckReads */ true);
     }
     if (Dec && InvalidCTRLoop)
       break;
   }
case PPC::BCn:
     Opcode = BDZOpcode;
     assert(!ML->contains(BrInstr->getOperand(1).getMBB()) &&
            "Invalid ctr loop!");
     break;
   default:
     llvm_unreachable("Unhandled branch user for DecreaseCTRloop.");
   }
 
-  unsigned MTCTROpcode = Is64Bit ? PPC::MTCTR8 : PPC::MTCTR;
-
-  // Generate "mtctr" in the loop preheader.
-  BuildMI(*Preheader, Start, Start->getDebugLoc(), TII->get(MTCTROpcode))
-      .addReg(Start->getOperand(0).getReg());
-
   // Generate "bdnz/bdz" in the exiting block just before the terminator.
   BuildMI(*Exiting, &*BrInstr, BrInstr->getDebugLoc(), TII->get(Opcode))
       .addMBB(BrInstr->getOperand(1).getMBB());
 
   // Remove the pseudo instructions.
-  Start->eraseFromParent();
   BrInstr->eraseFromParent();
   Dec->eraseFromParent();
 }

llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp

public:
     }
 
 // Include the pieces autogenerated from the target description.
 #include "PPCGenDAGISel.inc"
 
 private:
     bool trySETCC(SDNode *N);
     bool tryFoldSWTestBRCC(SDNode *N);
+    bool trySelectLoopCountIntrinsic(SDNode *N);
     bool tryAsSingleRLDICL(SDNode *N);
     bool tryAsSingleRLDICR(SDNode *N);
     bool tryAsSingleRLWINM(SDNode *N);
     bool tryAsSingleRLWINM8(SDNode *N);
     bool tryAsSingleRLWIMI(SDNode *N);
     bool tryAsPairOfRLDICL(SDNode *N);
     bool tryAsSingleRLDIMI(SDNode *N);
 
if (PCC) {
     SDValue Ops[] = {getI32Imm(PCC, dl), CmpLHS.getOperand(0), N->getOperand(4),
                      N->getOperand(0)};
     CurDAG->SelectNodeTo(N, PPC::BCC, MVT::Other, Ops);
     return true;
   }
   return false;
 }
 
+bool PPCDAGToDAGISel::trySelectLoopCountIntrinsic(SDNode *N) {
+  // Sometimes the promoted value of the intrinsic is ANDed by some non-zero
+  // value, for example when crbits is disabled. If so, select the
+  // loop_decrement intrinsics now.
+  ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
+  SDValue LHS = N->getOperand(2), RHS = N->getOperand(3);
+
+  if (LHS.getOpcode() != ISD::AND || !isa<ConstantSDNode>(LHS.getOperand(1)) ||
+      isNullConstant(LHS.getOperand(1)))
+    return false;
+
+  if (LHS.getOperand(0).getOpcode() != ISD::INTRINSIC_W_CHAIN ||
+      cast<ConstantSDNode>(LHS.getOperand(0).getOperand(1))->getZExtValue() !=
+          Intrinsic::loop_decrement)
+    return false;
+
+  if (!isa<ConstantSDNode>(RHS))
+    return false;
+
+  assert((CC == ISD::SETEQ || CC == ISD::SETNE) &&
+         "Counter decrement comparison is not EQ or NE");
+
+  SDValue OldDecrement = LHS.getOperand(0);
+  assert(OldDecrement.hasOneUse() && "loop decrement has more than one use!");
+
+  SDLoc DecrementLoc(OldDecrement);
+  SDValue ChainInput = OldDecrement.getOperand(0);
+  SDValue DecrementOps[] = {Subtarget->isPPC64() ? getI64Imm(1, DecrementLoc)
+                                                 : getI32Imm(1, DecrementLoc)};
+  unsigned DecrementOpcode =
+      Subtarget->isPPC64() ? PPC::DecreaseCTR8loop : PPC::DecreaseCTRloop;
+  SDNode *NewDecrement = CurDAG->getMachineNode(DecrementOpcode, DecrementLoc,
+                                                MVT::i1, DecrementOps);
+
+  unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
+  bool IsBranchOnTrue = (CC == ISD::SETEQ && Val) || (CC == ISD::SETNE && !Val);
+  unsigned Opcode = IsBranchOnTrue ? PPC::BC : PPC::BCn;
+
+  ReplaceUses(LHS.getValue(0), LHS.getOperand(1));
+  CurDAG->RemoveDeadNode(LHS.getNode());
+
+  // Mark the old loop_decrement intrinsic as dead.
+  ReplaceUses(OldDecrement.getValue(1), ChainInput);
+  CurDAG->RemoveDeadNode(OldDecrement.getNode());
+
+  CurDAG->SelectNodeTo(N, Opcode, MVT::Other, SDValue(NewDecrement, 0),
+                       N->getOperand(4), ChainInput);
+  return true;
+}
+
 bool PPCDAGToDAGISel::tryAsSingleRLWINM(SDNode *N) {
   assert(N->getOpcode() == ISD::AND && "ISD::AND SDNode expected");
   unsigned Imm;
   if (!isInt32Immediate(N->getOperand(1), Imm))
     return false;
 
   SDLoc dl(N);
   SDValue Val = N->getOperand(0);
case PPCISD::COND_BRANCH: {
     SDValue Ops[] = { Pred, N->getOperand(2), N->getOperand(3),
       N->getOperand(0), N->getOperand(4) };
     CurDAG->SelectNodeTo(N, PPC::BCC, MVT::Other, Ops);
     return;
   }
   case ISD::BR_CC: {
     if (tryFoldSWTestBRCC(N))
       return;
+    if (trySelectLoopCountIntrinsic(N))
+      return;
     ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
     unsigned PCC =
         getPredicateForSetCC(CC, N->getOperand(2).getValueType(), Subtarget);
 
     if (N->getOperand(2).getValueType() == MVT::i1) {
       unsigned Opc;
       bool Swap;
       switch (PCC) {

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

if (!N->getOperand(0).hasOneUse() &&
       }
 
       // If the user is a MFOCRF instruction, we know this is safe.
       // Otherwise we give up for right now.
       if (FlagUser->getOpcode() == PPCISD::MFOCRF)
         return SDValue(VCMPrecNode, 0);
     }
     break;
-  case ISD::BRCOND: {
-    SDValue Cond = N->getOperand(1);
-    SDValue Target = N->getOperand(2);
-
-    if (Cond.getOpcode() == ISD::INTRINSIC_W_CHAIN &&
-        cast<ConstantSDNode>(Cond.getOperand(1))->getZExtValue() ==
-          Intrinsic::loop_decrement) {
-
-      // We now need to make the intrinsic dead (it cannot be instruction
-      // selected).
-      DAG.ReplaceAllUsesOfValueWith(Cond.getValue(1), Cond.getOperand(0));
-      assert(Cond.getNode()->hasOneUse() &&
-             "Counter decrement has more than one use");
-
-      return DAG.getNode(PPCISD::BDNZ, dl, MVT::Other,
-                         N->getOperand(0), Target);
-    }
-  }
-  break;
   case ISD::BR_CC: {
     // If this is a branch on an altivec predicate comparison, lower this so
     // that we don't have to do a MFOCRF: instead, branch directly on CR6.  This
     // lowering is done pre-legalize, because the legalizer lowers the predicate
     // compare down to code that is difficult to reassemble.
     ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
     SDValue LHS = N->getOperand(2), RHS = N->getOperand(3);
 
-    // Sometimes the promoted value of the intrinsic is ANDed by some non-zero
-    // value. If so, pass-through the AND to get to the intrinsic.
-    if (LHS.getOpcode() == ISD::AND &&
-        LHS.getOperand(0).getOpcode() == ISD::INTRINSIC_W_CHAIN &&
-        cast<ConstantSDNode>(LHS.getOperand(0).getOperand(1))->getZExtValue() ==
-          Intrinsic::loop_decrement &&
-        isa<ConstantSDNode>(LHS.getOperand(1)) &&
-        !isNullConstant(LHS.getOperand(1)))
-      LHS = LHS.getOperand(0);
-
-    if (LHS.getOpcode() == ISD::INTRINSIC_W_CHAIN &&
-        cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue() ==
-          Intrinsic::loop_decrement &&
-        isa<ConstantSDNode>(RHS)) {
-      assert((CC == ISD::SETEQ || CC == ISD::SETNE) &&
-             "Counter decrement comparison is not EQ or NE");
-
-      unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
-      bool isBDNZ = (CC == ISD::SETEQ && Val) ||
-                    (CC == ISD::SETNE && !Val);
-
-      // We now need to make the intrinsic dead (it cannot be instruction
-      // selected).
-      DAG.ReplaceAllUsesOfValueWith(LHS.getValue(1), LHS.getOperand(0));
-      assert(LHS.getNode()->hasOneUse() &&
-             "Counter decrement has more than one use");
-
-      return DAG.getNode(isBDNZ ? PPCISD::BDNZ : PPCISD::BDZ, dl, MVT::Other,
-                         N->getOperand(0), N->getOperand(4));
-    }
-
     int CompareOpc;
     bool isDot;
 
     if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
         isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) &&
         getVectorCompareInfo(LHS, CompareOpc, isDot, Subtarget)) {
       assert(isDot && "Can't compare against a vector result!");
 

llvm/lib/Target/PowerPC/PPCInstr64Bit.td

 }
 let hasSideEffects = 1, Defs = [CTR8] in {
 let Pattern = [(int_set_loop_iterations i64:$rS)] in
 def MTCTR8loop : XFXForm_7_ext<31, 467, 9, (outs), (ins g8rc:$rS),
                                "mtctr $rS", IIC_SprMTSPR>,
                  PPC970_DGroup_First, PPC970_Unit_FXU;
 }
 
-
-let hasSideEffects = 1, Defs = [CTR8] in
-def MTCTR8Pseudo : PPCEmitTimePseudo<(outs), (ins g8rc:$rS), "#MTCTR8Pseudo", []>;
-
-let hasSideEffects = 1, Uses = [CTR8], Defs = [CTR8] in
-def DecreaseCTR8Pseudo : PPCEmitTimePseudo<(outs crbitrc:$rT), (ins i64imm:$stride),
-                                          "#DecreaseCTR8Pseudo", []>;
+let hasSideEffects = 1, hasNoSchedulingInfo = 1, Uses = [CTR8], Defs = [CTR8] in
+def DecreaseCTR8loop : PPCEmitTimePseudo<(outs crbitrc:$rT), (ins i64imm:$stride),
+                                        "#DecreaseCTR8loop", [(set i1:$rT, (int_loop_decrement (i64 imm:$stride)))]>;
 
 let Pattern = [(set i64:$rT, readcyclecounter)] in
 def MFTB8 : XFXForm_1_ext<31, 339, 268, (outs g8rc:$rT), (ins),
                           "mfspr $rT, 268", IIC_SprMFTB>,
             PPC970_DGroup_First, PPC970_Unit_FXU;
 // Note that encoding mftb using mfspr is now the preferred form,
 // and has been since at least ISA v2.03. The mftb instruction has
 // now been phased out. Using mfspr, however, is known not to work on

llvm/lib/Target/PowerPC/PPCInstrInfo.td

 }
 let hasSideEffects = 1, isCodeGenOnly = 1, Defs = [CTR] in {
 let Pattern = [(int_set_loop_iterations i32:$rS)] in
 def MTCTRloop : XFXForm_7_ext<31, 467, 9, (outs), (ins gprc:$rS),
                               "mtctr $rS", IIC_SprMTSPR>,
                 PPC970_DGroup_First, PPC970_Unit_FXU;
 }
 
-let hasSideEffects = 1, Defs = [CTR] in
-def MTCTRPseudo : PPCEmitTimePseudo<(outs), (ins gprc:$rS), "#MTCTRPseudo", []>;
-
-let hasSideEffects = 1, Uses = [CTR], Defs = [CTR] in
-def DecreaseCTRPseudo : PPCEmitTimePseudo<(outs crbitrc:$rT), (ins i32imm:$stride),
-                                          "#DecreaseCTRPseudo", []>;
+let hasSideEffects = 1, hasNoSchedulingInfo = 1, Uses = [CTR], Defs = [CTR] in
+def DecreaseCTRloop : PPCEmitTimePseudo<(outs crbitrc:$rT), (ins i32imm:$stride),
+                                       "#DecreaseCTRloop", [(set i1:$rT, (int_loop_decrement (i32 imm:$stride)))]>;
 
 let hasSideEffects = 0 in {
 let Defs = [LR] in {
 def MTLR  : XFXForm_7_ext<31, 467, 8, (outs), (ins gprc:$rS),
                           "mtlr $rS", IIC_SprMTSPR>,
             PPC970_DGroup_First, PPC970_Unit_FXU;
 }
 let Uses = [LR] in {

llvm/test/CodeGen/PowerPC/ctrloops-pseudo.ll

define void @test1(i32 %c) nounwind {
   ; AIX64-NEXT: {{  $}}
   ; AIX64-NEXT: bb.1.for.body:
   ; AIX64-NEXT:   successors: %bb.1(0x7c000000), %bb.2(0x04000000)
   ; AIX64-NEXT: {{  $}}
   ; AIX64-NEXT:   [[LDtoc:%[0-9]+]]:g8rc_and_g8rc_nox0 = LDtoc @a, $x2 :: (load (s64) from got)
   ; AIX64-NEXT:   [[LWZ:%[0-9]+]]:gprc = LWZ 0, [[LDtoc]] :: (volatile dereferenceable load (s32) from @a)
   ; AIX64-NEXT:   [[ADD4_:%[0-9]+]]:gprc = nsw ADD4 killed [[LWZ]], [[COPY1]]
   ; AIX64-NEXT:   STW killed [[ADD4_]], 0, [[LDtoc]] :: (volatile store (s32) into @a)
-  ; AIX64-NEXT:   BDNZ8 %bb.1, implicit-def dead $ctr8, implicit $ctr8
+  ; AIX64-NEXT:   [[DecreaseCTR8loop:%[0-9]+]]:crbitrc = DecreaseCTR8loop 1, implicit-def dead $ctr8, implicit $ctr8
+  ; AIX64-NEXT:   BC killed [[DecreaseCTR8loop]], %bb.1
   ; AIX64-NEXT:   B %bb.2
   ; AIX64-NEXT: {{  $}}
   ; AIX64-NEXT: bb.2.for.end:
   ; AIX64-NEXT:   BLR8 implicit $lr8, implicit $rm
   ; AIX32-LABEL: name: test1
   ; AIX32: bb.0.entry:
   ; AIX32-NEXT:   successors: %bb.1(0x80000000)
   ; AIX32-NEXT:   liveins: $r3
   ; AIX32-NEXT: {{  $}}
   ; AIX32-NEXT:   [[COPY:%[0-9]+]]:gprc = COPY $r3
   ; AIX32-NEXT:   [[LI:%[0-9]+]]:gprc = LI 2048
   ; AIX32-NEXT:   MTCTRloop killed [[LI]], implicit-def dead $ctr
   ; AIX32-NEXT: {{  $}}
   ; AIX32-NEXT: bb.1.for.body:
   ; AIX32-NEXT:   successors: %bb.1(0x7c000000), %bb.2(0x04000000)
   ; AIX32-NEXT: {{  $}}
   ; AIX32-NEXT:   [[LWZtoc:%[0-9]+]]:gprc_and_gprc_nor0 = LWZtoc @a, $r2 :: (load (s32) from got)
   ; AIX32-NEXT:   [[LWZ:%[0-9]+]]:gprc = LWZ 0, [[LWZtoc]] :: (volatile dereferenceable load (s32) from @a)
   ; AIX32-NEXT:   [[ADD4_:%[0-9]+]]:gprc = nsw ADD4 killed [[LWZ]], [[COPY]]
   ; AIX32-NEXT:   STW killed [[ADD4_]], 0, [[LWZtoc]] :: (volatile store (s32) into @a)
-  ; AIX32-NEXT:   BDNZ %bb.1, implicit-def dead $ctr, implicit $ctr
+  ; AIX32-NEXT:   [[DecreaseCTRloop:%[0-9]+]]:crbitrc = DecreaseCTRloop 1, implicit-def dead $ctr, implicit $ctr
+  ; AIX32-NEXT:   BC killed [[DecreaseCTRloop]], %bb.1
   ; AIX32-NEXT:   B %bb.2
   ; AIX32-NEXT: {{  $}}
   ; AIX32-NEXT: bb.2.for.end:
   ; AIX32-NEXT:   BLR implicit $lr, implicit $rm
   ; LE64-LABEL: name: test1
   ; LE64: bb.0.entry:
   ; LE64-NEXT:   successors: %bb.1(0x80000000)
   ; LE64-NEXT:   liveins: $x3
   ; LE64-NEXT: {{  $}}
   ; LE64-NEXT:   [[COPY:%[0-9]+]]:g8rc = COPY $x3
   ; LE64-NEXT:   [[COPY1:%[0-9]+]]:gprc = COPY [[COPY]].sub_32
   ; LE64-NEXT:   [[LI8_:%[0-9]+]]:g8rc = LI8 2048
   ; LE64-NEXT:   MTCTR8loop killed [[LI8_]], implicit-def dead $ctr8
   ; LE64-NEXT: {{  $}}
   ; LE64-NEXT: bb.1.for.body:
   ; LE64-NEXT:   successors: %bb.1(0x7c000000), %bb.2(0x04000000)
   ; LE64-NEXT: {{  $}}
   ; LE64-NEXT:   [[ADDIStocHA8_:%[0-9]+]]:g8rc_and_g8rc_nox0 = ADDIStocHA8 $x2, @a
   ; LE64-NEXT:   [[LDtocL:%[0-9]+]]:g8rc_and_g8rc_nox0 = LDtocL @a, killed [[ADDIStocHA8_]] :: (load (s64) from got)
   ; LE64-NEXT:   [[LWZ:%[0-9]+]]:gprc = LWZ 0, [[LDtocL]] :: (volatile dereferenceable load (s32) from @a)
   ; LE64-NEXT:   [[ADD4_:%[0-9]+]]:gprc = nsw ADD4 killed [[LWZ]], [[COPY1]]
   ; LE64-NEXT:   STW killed [[ADD4_]], 0, [[LDtocL]] :: (volatile store (s32) into @a)
-  ; LE64-NEXT:   BDNZ8 %bb.1, implicit-def dead $ctr8, implicit $ctr8
+  ; LE64-NEXT:   [[DecreaseCTR8loop:%[0-9]+]]:crbitrc = DecreaseCTR8loop 1, implicit-def dead $ctr8, implicit $ctr8
+  ; LE64-NEXT:   BC killed [[DecreaseCTR8loop]], %bb.1
   ; LE64-NEXT:   B %bb.2
   ; LE64-NEXT: {{  $}}
   ; LE64-NEXT: bb.2.for.end:
   ; LE64-NEXT:   BLR8 implicit $lr8, implicit $rm
 entry:
   br label %for.body
 
 for.body:                                         ; preds = %for.body, %entry
define void @test2(i32 %c, i32 %d) nounwind {
   ; AIX64-NEXT: {{  $}}
   ; AIX64-NEXT: bb.2.for.body:
   ; AIX64-NEXT:   successors: %bb.2(0x7c000000), %bb.3(0x04000000)
   ; AIX64-NEXT: {{  $}}
   ; AIX64-NEXT:   [[LDtoc:%[0-9]+]]:g8rc_and_g8rc_nox0 = LDtoc @a, $x2 :: (load (s64) from got)
   ; AIX64-NEXT:   [[LWZ:%[0-9]+]]:gprc = LWZ 0, [[LDtoc]] :: (volatile dereferenceable load (s32) from @a)
   ; AIX64-NEXT:   [[ADD4_:%[0-9]+]]:gprc = nsw ADD4 killed [[LWZ]], [[COPY2]]
   ; AIX64-NEXT:   STW killed [[ADD4_]], 0, [[LDtoc]] :: (volatile store (s32) into @a)
-  ; AIX64-NEXT:   BDNZ8 %bb.2, implicit-def dead $ctr8, implicit $ctr8
+  ; AIX64-NEXT:   [[DecreaseCTR8loop:%[0-9]+]]:crbitrc = DecreaseCTR8loop 1, implicit-def dead $ctr8, implicit $ctr8
+  ; AIX64-NEXT:   BC killed [[DecreaseCTR8loop]], %bb.2
   ; AIX64-NEXT:   B %bb.3
   ; AIX64-NEXT: {{  $}}
   ; AIX64-NEXT: bb.3.for.end:
   ; AIX64-NEXT:   BLR8 implicit $lr8, implicit $rm
   ; AIX32-LABEL: name: test2
   ; AIX32: bb.0.entry:
   ; AIX32-NEXT:   successors: %bb.1(0x50000000), %bb.3(0x30000000)
   ; AIX32-NEXT:   liveins: $r3, $r4
define void @test2(i32 %c, i32 %d) nounwind {
   ; AIX32-NEXT: {{  $}}
   ; AIX32-NEXT: bb.2.for.body:
   ; AIX32-NEXT:   successors: %bb.2(0x7c000000), %bb.3(0x04000000)
   ; AIX32-NEXT: {{  $}}
   ; AIX32-NEXT:   [[LWZtoc:%[0-9]+]]:gprc_and_gprc_nor0 = LWZtoc @a, $r2 :: (load (s32) from got)
   ; AIX32-NEXT:   [[LWZ:%[0-9]+]]:gprc = LWZ 0, [[LWZtoc]] :: (volatile dereferenceable load (s32) from @a)
   ; AIX32-NEXT:   [[ADD4_:%[0-9]+]]:gprc = nsw ADD4 killed [[LWZ]], [[COPY1]]
   ; AIX32-NEXT:   STW killed [[ADD4_]], 0, [[LWZtoc]] :: (volatile store (s32) into @a)
-  ; AIX32-NEXT:   BDNZ %bb.2, implicit-def dead $ctr, implicit $ctr
+  ; AIX32-NEXT:   [[DecreaseCTRloop:%[0-9]+]]:crbitrc = DecreaseCTRloop 1, implicit-def dead $ctr, implicit $ctr
+  ; AIX32-NEXT:   BC killed [[DecreaseCTRloop]], %bb.2
   ; AIX32-NEXT:   B %bb.3
   ; AIX32-NEXT: {{  $}}
   ; AIX32-NEXT: bb.3.for.end:
   ; AIX32-NEXT:   BLR implicit $lr, implicit $rm
   ; LE64-LABEL: name: test2
   ; LE64: bb.0.entry:
   ; LE64-NEXT:   successors: %bb.1(0x50000000), %bb.3(0x30000000)
   ; LE64-NEXT:   liveins: $x3, $x4
define void @test2(i32 %c, i32 %d) nounwind {
   ; LE64-NEXT: bb.2.for.body:
   ; LE64-NEXT:   successors: %bb.2(0x7c000000), %bb.3(0x04000000)
   ; LE64-NEXT: {{  $}}
   ; LE64-NEXT:   [[ADDIStocHA8_:%[0-9]+]]:g8rc_and_g8rc_nox0 = ADDIStocHA8 $x2, @a
   ; LE64-NEXT:   [[LDtocL:%[0-9]+]]:g8rc_and_g8rc_nox0 = LDtocL @a, killed [[ADDIStocHA8_]] :: (load (s64) from got)
   ; LE64-NEXT:   [[LWZ:%[0-9]+]]:gprc = LWZ 0, [[LDtocL]] :: (volatile dereferenceable load (s32) from @a)
   ; LE64-NEXT:   [[ADD4_:%[0-9]+]]:gprc = nsw ADD4 killed [[LWZ]], [[COPY2]]
   ; LE64-NEXT:   STW killed [[ADD4_]], 0, [[LDtocL]] :: (volatile store (s32) into @a)
-  ; LE64-NEXT:   BDNZ8 %bb.2, implicit-def dead $ctr8, implicit $ctr8
+  ; LE64-NEXT:   [[DecreaseCTR8loop:%[0-9]+]]:crbitrc = DecreaseCTR8loop 1, implicit-def dead $ctr8, implicit $ctr8
+  ; LE64-NEXT:   BC killed [[DecreaseCTR8loop]], %bb.2
   ; LE64-NEXT:   B %bb.3
   ; LE64-NEXT: {{  $}}
   ; LE64-NEXT: bb.3.for.end:
   ; LE64-NEXT:   BLR8 implicit $lr8, implicit $rm
 entry:
   %cmp1 = icmp sgt i32 %d, 0
   br i1 %cmp1, label %for.body, label %for.end
 
define void @test3(i32 %c, i32 %d) nounwind {
   ; AIX64-NEXT:   successors: %bb.2(0x7c000000), %bb.3(0x04000000)
   ; AIX64-NEXT: {{  $}}
   ; AIX64-NEXT:   [[PHI:%[0-9]+]]:gprc = PHI [[LI]], %bb.1, %1, %bb.2
   ; AIX64-NEXT:   [[LDtoc:%[0-9]+]]:g8rc_and_g8rc_nox0 = LDtoc @a, $x2 :: (load (s64) from got)
   ; AIX64-NEXT:   [[LWZ:%[0-9]+]]:gprc = LWZ 0, [[LDtoc]] :: (volatile dereferenceable load (s32) from @a)
   ; AIX64-NEXT:   [[ADD4_:%[0-9]+]]:gprc = ADD4 [[PHI]], killed [[LWZ]]
   ; AIX64-NEXT:   STW killed [[ADD4_]], 0, [[LDtoc]] :: (volatile store (s32) into @a)
   ; AIX64-NEXT:   [[ADD4_1:%[0-9]+]]:gprc = ADD4 [[PHI]], [[COPY2]]
-  ; AIX64-NEXT:   BDNZ8 %bb.2, implicit-def dead $ctr8, implicit $ctr8
+  ; AIX64-NEXT:   [[DecreaseCTR8loop:%[0-9]+]]:crbitrc = DecreaseCTR8loop 1, implicit-def dead $ctr8, implicit $ctr8
+  ; AIX64-NEXT:   BC killed [[DecreaseCTR8loop]], %bb.2
   ; AIX64-NEXT:   B %bb.3
   ; AIX64-NEXT: {{  $}}
   ; AIX64-NEXT: bb.3.for.end:
   ; AIX64-NEXT:   BLR8 implicit $lr8, implicit $rm
   ; AIX32-LABEL: name: test3
   ; AIX32: bb.0.entry:
   ; AIX32-NEXT:   successors: %bb.1(0x50000000), %bb.3(0x30000000)
   ; AIX32-NEXT:   liveins: $r3, $r4
define void @test3(i32 %c, i32 %d) nounwind {
   ; AIX32-NEXT:   successors: %bb.2(0x7c000000), %bb.3(0x04000000)
   ; AIX32-NEXT: {{  $}}
   ; AIX32-NEXT:   [[PHI:%[0-9]+]]:gprc = PHI [[LI]], %bb.1, %1, %bb.2
   ; AIX32-NEXT:   [[LWZtoc:%[0-9]+]]:gprc_and_gprc_nor0 = LWZtoc @a, $r2 :: (load (s32) from got)
   ; AIX32-NEXT:   [[LWZ:%[0-9]+]]:gprc = LWZ 0, [[LWZtoc]] :: (volatile dereferenceable load (s32) from @a)
   ; AIX32-NEXT:   [[ADD4_:%[0-9]+]]:gprc = ADD4 [[PHI]], killed [[LWZ]]
   ; AIX32-NEXT:   STW killed [[ADD4_]], 0, [[LWZtoc]] :: (volatile store (s32) into @a)
   ; AIX32-NEXT:   [[ADD4_1:%[0-9]+]]:gprc = ADD4 [[PHI]], [[COPY1]]
-  ; AIX32-NEXT:   BDNZ %bb.2, implicit-def dead $ctr, implicit $ctr
+  ; AIX32-NEXT:   [[DecreaseCTRloop:%[0-9]+]]:crbitrc = DecreaseCTRloop 1, implicit-def dead $ctr, implicit $ctr
+  ; AIX32-NEXT:   BC killed [[DecreaseCTRloop]], %bb.2
   ; AIX32-NEXT:   B %bb.3
   ; AIX32-NEXT: {{  $}}
   ; AIX32-NEXT: bb.3.for.end:
   ; AIX32-NEXT:   BLR implicit $lr, implicit $rm
   ; LE64-LABEL: name: test3
   ; LE64: bb.0.entry:
   ; LE64-NEXT:   successors: %bb.1(0x50000000), %bb.3(0x30000000)
   ; LE64-NEXT:   liveins: $x3, $x4
define void @test3(i32 %c, i32 %d) nounwind {
   ; LE64-NEXT: {{  $}}
   ; LE64-NEXT:   [[PHI:%[0-9]+]]:gprc = PHI [[LI]], %bb.1, %1, %bb.2
   ; LE64-NEXT:   [[ADDIStocHA8_:%[0-9]+]]:g8rc_and_g8rc_nox0 = ADDIStocHA8 $x2, @a
   ; LE64-NEXT:   [[LDtocL:%[0-9]+]]:g8rc_and_g8rc_nox0 = LDtocL @a, killed [[ADDIStocHA8_]] :: (load (s64) from got)
   ; LE64-NEXT:   [[LWZ:%[0-9]+]]:gprc = LWZ 0, [[LDtocL]] :: (volatile dereferenceable load (s32) from @a)
   ; LE64-NEXT:   [[ADD4_:%[0-9]+]]:gprc = ADD4 [[PHI]], killed [[LWZ]]
   ; LE64-NEXT:   STW killed [[ADD4_]], 0, [[LDtocL]] :: (volatile store (s32) into @a)
   ; LE64-NEXT:   [[ADD4_1:%[0-9]+]]:gprc = ADD4 [[PHI]], [[COPY2]]
-  ; LE64-NEXT:   BDNZ8 %bb.2, implicit-def dead $ctr8, implicit $ctr8
+  ; LE64-NEXT:   [[DecreaseCTR8loop:%[0-9]+]]:crbitrc = DecreaseCTR8loop 1, implicit-def dead $ctr8, implicit $ctr8
+  ; LE64-NEXT:   BC killed [[DecreaseCTR8loop]], %bb.2
   ; LE64-NEXT:   B %bb.3
   ; LE64-NEXT: {{  $}}
   ; LE64-NEXT: bb.3.for.end:
   ; LE64-NEXT:   BLR8 implicit $lr8, implicit $rm
 entry:
   %cmp1 = icmp sgt i32 %d, 0
   br i1 %cmp1, label %for.body, label %for.end
 
define i32 @test4(i32 %inp) {
   ; AIX64-NEXT:   [[INSERT_SUBREG:%[0-9]+]]:g8rc = INSERT_SUBREG [[DEF]], killed [[SUBF]], %subreg.sub_32
   ; AIX64-NEXT:   [[RLDICL:%[0-9]+]]:g8rc_and_g8rc_nox0 = RLDICL killed [[INSERT_SUBREG]], 0, 32
   ; AIX64-NEXT:   [[ADDI8_:%[0-9]+]]:g8rc = nuw nsw ADDI8 killed [[RLDICL]], 1
   ; AIX64-NEXT:   MTCTR8loop killed [[ADDI8_]], implicit-def dead $ctr8
   ; AIX64-NEXT: {{  $}}
   ; AIX64-NEXT: bb.1.for.body:
   ; AIX64-NEXT:   successors: %bb.1(0x7c000000), %bb.2(0x04000000)
   ; AIX64-NEXT: {{  $}}
-  ; AIX64-NEXT:   BDNZ8 %bb.1, implicit-def dead $ctr8, implicit $ctr8
+  ; AIX64-NEXT:   [[DecreaseCTR8loop:%[0-9]+]]:crbitrc = DecreaseCTR8loop 1, implicit-def dead $ctr8, implicit $ctr8
+  ; AIX64-NEXT:   BC killed [[DecreaseCTR8loop]], %bb.1
   ; AIX64-NEXT:   B %bb.2
   ; AIX64-NEXT: {{  $}}
   ; AIX64-NEXT: bb.2.return:
   ; AIX64-NEXT:   [[LDtoc:%[0-9]+]]:g8rc = LDtoc target-flags(ppc-lo) @tls_var, $x2 :: (load (s64) from got)
   ; AIX64-NEXT:   [[LDtoc1:%[0-9]+]]:g8rc = LDtoc target-flags(ppc-tlsgd) @tls_var, $x2 :: (load (s64) from got)
   ; AIX64-NEXT:   [[TLSGDAIX8_:%[0-9]+]]:g8rc = TLSGDAIX8 killed [[LDtoc1]], killed [[LDtoc]]
   ; AIX64-NEXT:   [[COPY2:%[0-9]+]]:gprc = COPY [[TLSGDAIX8_]].sub_32
   ; AIX64-NEXT:   [[ADD4_:%[0-9]+]]:gprc = ADD4 killed [[COPY2]], [[ISEL]]
define i32 @test4(i32 %inp) {
   ; AIX32-NEXT:   [[ISEL:%[0-9]+]]:gprc = ISEL [[COPY]], [[LI]], [[CMPWI]].sub_lt
   ; AIX32-NEXT:   [[SUBF:%[0-9]+]]:gprc_and_gprc_nor0 = SUBF [[ISEL]], [[COPY]]
   ; AIX32-NEXT:   [[ADDI:%[0-9]+]]:gprc = ADDI killed [[SUBF]], 1
   ; AIX32-NEXT:   MTCTRloop killed [[ADDI]], implicit-def dead $ctr
   ; AIX32-NEXT: {{  $}}
   ; AIX32-NEXT: bb.1.for.body:
   ; AIX32-NEXT:   successors: %bb.1(0x7c000000), %bb.2(0x04000000)
   ; AIX32-NEXT: {{  $}}
-  ; AIX32-NEXT:   BDNZ %bb.1, implicit-def dead $ctr, implicit $ctr
+  ; AIX32-NEXT:   [[DecreaseCTRloop:%[0-9]+]]:crbitrc = DecreaseCTRloop 1, implicit-def dead $ctr, implicit $ctr
+  ; AIX32-NEXT:   BC killed [[DecreaseCTRloop]], %bb.1
   ; AIX32-NEXT:   B %bb.2
   ; AIX32-NEXT: {{  $}}
   ; AIX32-NEXT: bb.2.return:
   ; AIX32-NEXT:   [[LWZtoc:%[0-9]+]]:gprc = LWZtoc target-flags(ppc-lo) @tls_var, $r2 :: (load (s32) from got)
   ; AIX32-NEXT:   [[LWZtoc1:%[0-9]+]]:gprc = LWZtoc target-flags(ppc-tlsgd) @tls_var, $r2 :: (load (s32) from got)
   ; AIX32-NEXT:   [[TLSGDAIX:%[0-9]+]]:gprc = TLSGDAIX killed [[LWZtoc1]], killed [[LWZtoc]]
   ; AIX32-NEXT:   [[ADD4_:%[0-9]+]]:gprc = ADD4 killed [[TLSGDAIX]], [[ISEL]]
   ; AIX32-NEXT:   $r3 = COPY [[ADD4_]]
define i32 @test4(i32 %inp) {
   ; LE64-NEXT:   [[INSERT_SUBREG:%[0-9]+]]:g8rc = INSERT_SUBREG [[DEF]], killed [[SUBF]], %subreg.sub_32
   ; LE64-NEXT:   [[RLDICL:%[0-9]+]]:g8rc_and_g8rc_nox0 = RLDICL killed [[INSERT_SUBREG]], 0, 32
   ; LE64-NEXT:   [[ADDI8_:%[0-9]+]]:g8rc = nuw nsw ADDI8 killed [[RLDICL]], 1
   ; LE64-NEXT:   MTCTR8loop killed [[ADDI8_]], implicit-def dead $ctr8
   ; LE64-NEXT: {{  $}}
   ; LE64-NEXT: bb.1.for.body:
   ; LE64-NEXT:   successors: %bb.1(0x7c000000), %bb.2(0x04000000)
   ; LE64-NEXT: {{  $}}
-  ; LE64-NEXT:   BDNZ8 %bb.1, implicit-def dead $ctr8, implicit $ctr8
+  ; LE64-NEXT:   [[DecreaseCTR8loop:%[0-9]+]]:crbitrc = DecreaseCTR8loop 1, implicit-def dead $ctr8, implicit $ctr8
+  ; LE64-NEXT:   BC killed [[DecreaseCTR8loop]], %bb.1
   ; LE64-NEXT:   B %bb.2
   ; LE64-NEXT: {{  $}}
   ; LE64-NEXT: bb.2.return:
   ; LE64-NEXT:   [[ADDISgotTprelHA:%[0-9]+]]:g8rc_and_g8rc_nox0 = ADDISgotTprelHA $x2, @tls_var
   ; LE64-NEXT:   [[LDgotTprelL:%[0-9]+]]:g8rc_and_g8rc_nox0 = LDgotTprelL @tls_var, killed [[ADDISgotTprelHA]]
   ; LE64-NEXT:   [[ADD8TLS:%[0-9]+]]:g8rc = ADD8TLS killed [[LDgotTprelL]], target-flags(ppc-tls) @tls_var
   ; LE64-NEXT:   [[COPY2:%[0-9]+]]:gprc = COPY [[ADD8TLS]].sub_32
   ; LE64-NEXT:   [[ADD4_:%[0-9]+]]:gprc = ADD4 killed [[COPY2]], [[ISEL]]

llvm/test/CodeGen/PowerPC/ctrloops32.mir

 # RUN: llc -ppc-asm-full-reg-names -mtriple=powerpc-ibm-aix-xcoff \
 # RUN:   -run-pass=ppc-ctrloops %s -o - -verify-machineinstrs | FileCheck %s 
 
 ---
 name:            test_success1
 # CHECK: test_success1
 
 tracksRegLiveness: true
 body:             |
   bb.0.entry:
 
     %0:gprc = LI 2048
-    ; CHECK: MTCTR
+    ; CHECK: MTCTRloop
     ; CHECK: BDNZ
     ; CHECK-NOT: ADDI
     ; CHECK-NOT: CMPLWI
     ; CHECK-NOT: BC
-    MTCTRPseudo killed %0:gprc, implicit-def dead $ctr
+    MTCTRloop killed %0:gprc, implicit-def dead $ctr
 
   bb.1:
 
-    %1:crbitrc = DecreaseCTRPseudo 1, implicit-def dead $ctr, implicit $ctr
+    %1:crbitrc = DecreaseCTRloop 1, implicit-def dead $ctr, implicit $ctr
     BC killed %1:crbitrc, %bb.1
     B %bb.2
 
   bb.2:
 
     BLR implicit $lr, implicit $rm
 ...
 ---
 name:            test_fail_clobber
 # CHECK: test_fail_clobber
 tracksRegLiveness: true
 body:             |
   bb.0.entry:
 
     %0:gprc = LI 2048
-    ; CHECK-NOT: MTCTR
+    ; CHECK-NOT: MTCTRloop
     ; CHECK-NOT: BDNZ
     ; CHECK: ADDI
     ; CHECK: CMPLWI
     ; CHECK: BC
-    MTCTRPseudo killed %0:gprc, implicit-def dead $ctr
+    MTCTRloop killed %0:gprc, implicit-def dead $ctr
 
   bb.1:
 
     INLINEASM &"", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def early-clobber $ctr
-    %1:crbitrc = DecreaseCTRPseudo 1, implicit-def dead $ctr, implicit $ctr
+    %1:crbitrc = DecreaseCTRloop 1, implicit-def dead $ctr, implicit $ctr
     BC killed %1:crbitrc, %bb.1
     B %bb.2
 
   bb.2:
 
     BLR implicit $lr, implicit $rm
 ...
 ---
 name:            test_fail_use_in_loop
 # CHECK: test_fail_use_in_loop
 tracksRegLiveness: true
 body:             |
   bb.0.entry:
 
     %0:gprc = LI 2048
-    ; CHECK-NOT: MTCTR
+    ; CHECK-NOT: MTCTRloop
     ; CHECK-NOT: BDNZ
     ; CHECK: ADDI
     ; CHECK: CMPLWI
     ; CHECK: BC
-    MTCTRPseudo killed %0:gprc, implicit-def dead $ctr
+    MTCTRloop killed %0:gprc, implicit-def dead $ctr
 
   bb.1:
 
     %1:gprc = MFCTR implicit $ctr
-    %2:crbitrc = DecreaseCTRPseudo 1, implicit-def dead $ctr, implicit $ctr
+    %2:crbitrc = DecreaseCTRloop 1, implicit-def dead $ctr, implicit $ctr
     BC killed %2:crbitrc, %bb.1
     B %bb.2
 
   bb.2:
 
     BLR implicit $lr, implicit $rm
 ...
 ---
 name:            test_fail_call_in_preheader_after_mtctr
 # CHECK: test_fail_call_in_preheader_after_mtctr
 tracksRegLiveness: true
 body:             |
   bb.0.entry:
 
     %0:gprc = LI 2048
     ; CHECK-NOT: MTCTR
     ; CHECK-NOT: BDNZ
     ; CHECK: ADDI
     ; CHECK: CMPLWI
     ; CHECK: BC
-    MTCTRPseudo killed %0:gprc, implicit-def dead $ctr
+    MTCTRloop killed %0:gprc, implicit-def dead $ctr
     BL @test_fail_use_in_loop, csr_aix32, implicit-def dead $lr, implicit $rm
 
   bb.1:
 
-    %1:crbitrc = DecreaseCTRPseudo 1, implicit-def dead $ctr, implicit $ctr
+    %1:crbitrc = DecreaseCTRloop 1, implicit-def dead $ctr, implicit $ctr
     BC killed %1:crbitrc, %bb.1
     B %bb.2
 
   bb.2:
 
     BLR implicit $lr, implicit $rm
 ...
 ---
 name:            test_succ_call_in_preheader_before_mtctr
 # CHECK: test_succ_call_in_preheader_before_mtctr
 tracksRegLiveness: true
 body:             |
   bb.0.entry:
 
     %0:gprc = LI 2048
     BL @test_fail_use_in_loop, csr_aix32, implicit-def dead $lr, implicit $rm
     ; CHECK: MTCTR
     ; CHECK: BDNZ
     ; CHECK-NOT: ADDI
     ; CHECK-NOT: CMPLWI
     ; CHECK-NOT: BC
-    MTCTRPseudo killed %0:gprc, implicit-def dead $ctr
+    MTCTRloop killed %0:gprc, implicit-def dead $ctr
 
   bb.1:
 
-    %1:crbitrc = DecreaseCTRPseudo 1, implicit-def dead $ctr, implicit $ctr
+    %1:crbitrc = DecreaseCTRloop 1, implicit-def dead $ctr, implicit $ctr
     BC killed %1:crbitrc, %bb.1
     B %bb.2
 
   bb.2:
 
     BLR implicit $lr, implicit $rm
 ...
 ---
 name:            test_fail_call_in_loop
 # CHECK: test_fail_call_in_loop
 tracksRegLiveness: true
 body:             |
   bb.0.entry:
 
     %0:gprc = LI 2048
     ; CHECK-NOT: MTCTR
     ; CHECK-NOT: BDNZ
     ; CHECK: ADDI
     ; CHECK: CMPLWI
     ; CHECK: BC
-    MTCTRPseudo killed %0:gprc, implicit-def dead $ctr
+    MTCTRloop killed %0:gprc, implicit-def dead $ctr
 
   bb.1:
 
     BL @test_fail_use_in_loop, csr_aix32, implicit-def dead $lr, implicit $rm
-    %1:crbitrc = DecreaseCTRPseudo 1, implicit-def dead $ctr, implicit $ctr
+    %1:crbitrc = DecreaseCTRloop 1, implicit-def dead $ctr, implicit $ctr
     BC killed %1:crbitrc, %bb.1
     B %bb.2
 
   bb.2:
 
     BLR implicit $lr, implicit $rm
 ...
 ---
 name:            test_fail_indirect_call_in_loop
 # CHECK: test_fail_indirect_call_in_loop
 tracksRegLiveness: true
 body:             |
   bb.0.entry:
    liveins: $r3, $r4
 
     %0:gprc = LI 2048
     ; CHECK-NOT: MTCTR
     ; CHECK-NOT: BDNZ
     ; CHECK: ADDI
     ; CHECK: CMPLWI
     ; CHECK: BC
     renamable %1:crrc = CMPLW killed renamable $r3, killed renamable $r4
     renamable %2:crbitrc = COPY %1.sub_gt
     MTLR %0:gprc, implicit-def $lr
-    MTCTRPseudo %0:gprc, implicit-def dead $ctr
+    MTCTRloop %0:gprc, implicit-def dead $ctr
 
   bb.1:
 
     BCLRL renamable %2, implicit $lr, implicit $rm
-    %3:crbitrc = DecreaseCTRPseudo 1, implicit-def dead $ctr, implicit $ctr
+    %3:crbitrc = DecreaseCTRloop 1, implicit-def dead $ctr, implicit $ctr
     BC killed %3:crbitrc, %bb.1
     B %bb.2
 
   bb.2:
 
     BLR implicit $lr, implicit $rm
 ...
 ---
 name:            test_fail_livein_preheader
 # CHECK: test_fail_livein_preheader
 tracksRegLiveness: true
 body:             |
   bb.0.entry:
     liveins: $ctr
 
     %0:gprc = LI 2048
-    ; CHECK-NOT: MTCTR
+    ; CHECK-NOT: MTCTRloop
     ; CHECK-NOT: BDNZ
     ; CHECK: ADDI
     ; CHECK: CMPLWI
     ; CHECK: BC
-    MTCTRPseudo killed %0:gprc, implicit-def dead $ctr
+    MTCTRloop killed %0:gprc, implicit-def dead $ctr
 
   bb.1:
 
-    %1:crbitrc = DecreaseCTRPseudo 1, implicit-def dead $ctr, implicit $ctr
+    %1:crbitrc = DecreaseCTRloop 1, implicit-def dead $ctr, implicit $ctr
     BC killed %1:crbitrc, %bb.1
     B %bb.2
 
   bb.2:
 
     BLR implicit $lr, implicit $rm
 ...
 ---
 name:            test_fail_def_preheader
 # CHECK: test_fail_def_preheader
 tracksRegLiveness: true
 body:             |
   bb.0.entry:
 
     INLINEASM &"", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def early-clobber $ctr
     %0:gprc = LI 2048
-    ; CHECK2-NOT: MTCTR
+    ; CHECK-NOT: MTCTRloop
     ; CHECK-NOT: BDNZ
     ; CHECK: ADDI
     ; CHECK: CMPLWI
     ; CHECK: BC
-    MTCTRPseudo killed %0:gprc, implicit-def dead $ctr
+    MTCTRloop killed %0:gprc, implicit-def dead $ctr
 
   bb.1:
 
-    %1:crbitrc = DecreaseCTRPseudo 1, implicit-def dead $ctr, implicit $ctr
+    %1:crbitrc = DecreaseCTRloop 1, implicit-def dead $ctr, implicit $ctr
     BC killed %1:crbitrc, %bb.1
     B %bb.2
 
   bb.2:
 
     BLR implicit $lr, implicit $rm
 ...
 ---
 name:            test_success_only_use_preheader
 # CHECK: test_success_only_use_preheader
 tracksRegLiveness: true
 body:             |
   bb.0.entry:
 
     %0:gprc = MFCTR implicit $ctr
     %1:gprc = LI 2048
-    ; CHECK: MTCTR
+    ; CHECK: MTCTRloop
     ; CHECK: BDNZ
     ; CHECK-NOT: ADDI
     ; CHECK-NOT: CMPLWI
     ; CHECK-NOT: BC
-    MTCTRPseudo killed %1:gprc, implicit-def dead $ctr
+    MTCTRloop killed %1:gprc, implicit-def dead $ctr
 
   bb.1:
 
-    %2:crbitrc = DecreaseCTRPseudo 1, implicit-def dead $ctr, implicit $ctr
+    %2:crbitrc = DecreaseCTRloop 1, implicit-def dead $ctr, implicit $ctr
     BC killed %2:crbitrc, %bb.1
     B %bb.2
 
   bb.2:
 
     BLR implicit $lr, implicit $rm
 ...
 ---
 name:            test_fail_use_after_mtctr
 # CHECK: test_fail_use_after_mtctr
 tracksRegLiveness: true
 body:             |
   bb.0.entry:
 
     %0:gprc = LI 2048
-    ; CHECK-NOT: MTCTR
+    ; CHECK-NOT: MTCTRloop
     ; CHECK-NOT: BDNZ
     ; CHECK: ADDI
     ; CHECK: CMPLWI
     ; CHECK: BC
-    MTCTRPseudo killed %0:gprc, implicit-def dead $ctr
+    MTCTRloop killed %0:gprc, implicit-def dead $ctr
     %1:gprc = MFCTR implicit $ctr
 
   bb.1:
 
-    %2:crbitrc = DecreaseCTRPseudo 1, implicit-def dead $ctr, implicit $ctr
+    %2:crbitrc = DecreaseCTRloop 1, implicit-def dead $ctr, implicit $ctr
     BC killed %2:crbitrc, %bb.1
     B %bb.2
 
   bb.2:
 
     BLR implicit $lr, implicit $rm
 ...
 ---
 name:            test_fail_def_after_mtctr
 # CHECK: test_fail_def_after_mtctr
 tracksRegLiveness: true
 body:             |
   bb.0.entry:
 
     %0:gprc = LI 2048
-    ; CHECK-NOT: MTCTR
+    ; CHECK-NOT: MTCTRloop
     ; CHECK-NOT: BDNZ
     ; CHECK: ADDI
     ; CHECK: CMPLWI
     ; CHECK: BC
-    MTCTRPseudo killed %0:gprc, implicit-def dead $ctr
+    MTCTRloop killed %0:gprc, implicit-def dead $ctr
     INLINEASM &"", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def early-clobber $ctr
 
   bb.1:
 
-    %2:crbitrc = DecreaseCTRPseudo 1, implicit-def dead $ctr, implicit $ctr
+    %2:crbitrc = DecreaseCTRloop 1, implicit-def dead $ctr, implicit $ctr
     BC killed %2:crbitrc, %bb.1
     B %bb.2
 
   bb.2:
 
     BLR implicit $lr, implicit $rm
 ...
 ---
 name:            test_success_def_after_loop
 # CHECK: test_success_def_after_loop
 tracksRegLiveness: true
 body:             |
   bb.0.entry:
 
     %0:gprc = LI 2048
-    ; CHECK: MTCTR
+    ; CHECK: MTCTRloop
     ; CHECK: BDNZ
     ; CHECK-NOT: ADDI
     ; CHECK-NOT: CMPLWI
     ; CHECK-NOT: BC
-    MTCTRPseudo killed %0:gprc, implicit-def dead $ctr
+    MTCTRloop killed %0:gprc, implicit-def dead $ctr
 
   bb.1:
 
-    %2:crbitrc = DecreaseCTRPseudo 1, implicit-def dead $ctr, implicit $ctr
+    %2:crbitrc = DecreaseCTRloop 1, implicit-def dead $ctr, implicit $ctr
     BC killed %2:crbitrc, %bb.1
     B %bb.2
 
   bb.2:
     INLINEASM &"", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def early-clobber $ctr
 
     BLR implicit $lr, implicit $rm
 ...

llvm/test/CodeGen/PowerPC/ctrloops64.mir

 # RUN: llc -ppc-asm-full-reg-names -mtriple=powerpc64le-unknown-linux-gnu \
 # RUN:   -run-pass=ppc-ctrloops %s -o - -verify-machineinstrs | FileCheck %s
 # RUN: llc -ppc-asm-full-reg-names -mtriple=powerpc64-ibm-aix-xcoff \
 # RUN:   -run-pass=ppc-ctrloops %s -o - -verify-machineinstrs | FileCheck %s
 
 ---
 name:            test_success1
 # CHECK: test_success1
 
 tracksRegLiveness: true
 body:             |
   bb.0.entry:
 
     %0:g8rc = LI8 2048
-    ; CHECK: MTCTR8
+    ; CHECK: MTCTR8loop
     ; CHECK: BDNZ8
     ; CHECK-NOT: ADDI8
     ; CHECK-NOT: CMPLDI
     ; CHECK-NOT: BC
-    MTCTR8Pseudo killed %0:g8rc, implicit-def dead $ctr8
+    MTCTR8loop killed %0:g8rc, implicit-def dead $ctr8
 
   bb.1:
 
-    %1:crbitrc = DecreaseCTR8Pseudo 1, implicit-def dead $ctr8, implicit $ctr8
+    %1:crbitrc = DecreaseCTR8loop 1, implicit-def dead $ctr8, implicit $ctr8
     BC killed %1:crbitrc, %bb.1
     B %bb.2
 
   bb.2:
 
     BLR8 implicit $lr8, implicit $rm
 ...
 ---
 name:            test_fail_clobber
 # CHECK: test_fail_clobber
 tracksRegLiveness: true
 body:             |
   bb.0.entry:
 
     %0:g8rc = LI8 2048
-    ; CHECK-NOT: MTCTR8
+    ; CHECK-NOT: MTCTR8loop
     ; CHECK-NOT: BDNZ8
     ; CHECK: ADDI8
     ; CHECK: CMPLDI
     ; CHECK: BC
-    MTCTR8Pseudo killed %0:g8rc, implicit-def dead $ctr8
+    MTCTR8loop killed %0:g8rc, implicit-def dead $ctr8
 
   bb.1:
 
     INLINEASM &"", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def early-clobber $ctr8
-    %1:crbitrc = DecreaseCTR8Pseudo 1, implicit-def dead $ctr8, implicit $ctr8
+    %1:crbitrc = DecreaseCTR8loop 1, implicit-def dead $ctr8, implicit $ctr8
     BC killed %1:crbitrc, %bb.1
     B %bb.2
 
   bb.2:
 
     BLR8 implicit $lr8, implicit $rm
 ...
 ---
 name:            test_fail_use_in_loop
 # CHECK: test_fail_use_in_loop
 tracksRegLiveness: true
 body:             |
   bb.0.entry:
 
     %0:g8rc = LI8 2048
-    ; CHECK-NOT: MTCTR8
+    ; CHECK-NOT: MTCTR8loop
     ; CHECK-NOT: BDNZ8
     ; CHECK: ADDI8
     ; CHECK: CMPLDI
     ; CHECK: BC
-    MTCTR8Pseudo killed %0:g8rc, implicit-def dead $ctr8
+    MTCTR8loop killed %0:g8rc, implicit-def dead $ctr8
 
   bb.1:
 
     %1:g8rc = MFCTR8 implicit $ctr8
-    %2:crbitrc = DecreaseCTR8Pseudo 1, implicit-def dead $ctr8, implicit $ctr8
+    %2:crbitrc = DecreaseCTR8loop 1, implicit-def dead $ctr8, implicit $ctr8
     BC killed %2:crbitrc, %bb.1
     B %bb.2
 
   bb.2:
 
     BLR8 implicit $lr8, implicit $rm
 ...
 ---
 name:            test_fail_call_in_preheader_after_mtctr
 # CHECK: test_fail_call_in_preheader_after_mtctr
 tracksRegLiveness: true
 body:             |
   bb.0.entry:
 
     %0:g8rc = LI8 2048
     ; CHECK-NOT: MTCTR8
     ; CHECK-NOT: BDNZ8
     ; CHECK: ADDI8
     ; CHECK: CMPLDI
     ; CHECK: BC
-    MTCTR8Pseudo killed %0:g8rc, implicit-def dead $ctr8
+    MTCTR8loop killed %0:g8rc, implicit-def dead $ctr8
     BL8 @test_fail_use_in_loop, csr_ppc64, implicit-def dead $lr8, implicit $rm
 
   bb.1:
 
-    %1:crbitrc = DecreaseCTR8Pseudo 1, implicit-def dead $ctr8, implicit $ctr8
+    %1:crbitrc = DecreaseCTR8loop 1, implicit-def dead $ctr8, implicit $ctr8
     BC killed %1:crbitrc, %bb.1
     B %bb.2
 
   bb.2:
 
     BLR8 implicit $lr8, implicit $rm
 ...
 ---
 name:            test_succ_call_in_preheader_before_mtctr
 # CHECK: test_succ_call_in_preheader_before_mtctr
 tracksRegLiveness: true
 body:             |
   bb.0.entry:
 
     %0:g8rc = LI8 2048
     BL8 @test_fail_use_in_loop, csr_ppc64, implicit-def dead $lr8, implicit $rm
     ; CHECK: MTCTR8
     ; CHECK: BDNZ8
     ; CHECK-NOT: ADDI8
     ; CHECK-NOT: CMPLDI
     ; CHECK-NOT: BC
-    MTCTR8Pseudo killed %0:g8rc, implicit-def dead $ctr8
+    MTCTR8loop killed %0:g8rc, implicit-def dead $ctr8
 
   bb.1:
 
-    %1:crbitrc = DecreaseCTR8Pseudo 1, implicit-def dead $ctr8, implicit $ctr8
+    %1:crbitrc = DecreaseCTR8loop 1, implicit-def dead $ctr8, implicit $ctr8
     BC killed %1:crbitrc, %bb.1
     B %bb.2
 
   bb.2:
 
     BLR8 implicit $lr8, implicit $rm
 ...
 ---
 name:            test_fail_call_in_loop
 # CHECK: test_fail_call_in_loop
 tracksRegLiveness: true
 body:             |
   bb.0.entry:
 
     %0:g8rc = LI8 2048
     ; CHECK-NOT: MTCTR8
     ; CHECK-NOT: BDNZ8
     ; CHECK: ADDI8
     ; CHECK: CMPLDI
     ; CHECK: BC
-    MTCTR8Pseudo killed %0:g8rc, implicit-def dead $ctr8
+    MTCTR8loop killed %0:g8rc, implicit-def dead $ctr8
 
   bb.1:
 
     BL8 @test_fail_use_in_loop, csr_ppc64, implicit-def dead $lr8, implicit $rm
-    %1:crbitrc = DecreaseCTR8Pseudo 1, implicit-def dead $ctr8, implicit $ctr8
+    %1:crbitrc = DecreaseCTR8loop 1, implicit-def dead $ctr8, implicit $ctr8
     BC killed %1:crbitrc, %bb.1
     B %bb.2
 
   bb.2:
 
     BLR8 implicit $lr8, implicit $rm
 ...
 ---
 name:            test_fail_indirect_call_in_loop
 # CHECK: test_fail_indirect_call_in_loop
 tracksRegLiveness: true
 body:             |
   bb.0.entry:
     liveins: $x3, $x4
 
     %0:g8rc = LI8 2048
     ; CHECK-NOT: MTCTR8
     ; CHECK-NOT: BDNZ8
     ; CHECK: ADDI8
     ; CHECK: CMPLDI
     ; CHECK: BC
     renamable %1:crrc = CMPLD killed renamable $x3, killed renamable $x4
     renamable %2:crbitrc = COPY %1.sub_gt
     MTLR8 %0:g8rc, implicit-def $lr8
-    MTCTR8Pseudo killed %0:g8rc, implicit-def dead $ctr8
+    MTCTR8loop killed %0:g8rc, implicit-def dead $ctr8
 
   bb.1:
 
     BCLRL renamable %2, implicit $lr, implicit $rm
-    %3:crbitrc = DecreaseCTR8Pseudo 1, implicit-def dead $ctr8, implicit $ctr8
+    %3:crbitrc = DecreaseCTR8loop 1, implicit-def dead $ctr8, implicit $ctr8
     BC killed %3:crbitrc, %bb.1
     B %bb.2
 
   bb.2:
 
     BLR8 implicit $lr8, implicit $rm
 ...
 ---
 name:            test_fail_livein_preheader
 # CHECK: test_fail_livein_preheader
 tracksRegLiveness: true
 body:             |
   bb.0.entry:
     liveins: $ctr8
 
     %0:g8rc = LI8 2048
-    ; CHECK-NOT: MTCTR8
+    ; CHECK-NOT: MTCTR8loop
     ; CHECK-NOT: BDNZ8
     ; CHECK: ADDI8
     ; CHECK: CMPLDI
     ; CHECK: BC
-    MTCTR8Pseudo killed %0:g8rc, implicit-def dead $ctr8
+    MTCTR8loop killed %0:g8rc, implicit-def dead $ctr8
 
   bb.1:
 
-    %1:crbitrc = DecreaseCTR8Pseudo 1, implicit-def dead $ctr8, implicit $ctr8
+    %1:crbitrc = DecreaseCTR8loop 1, implicit-def dead $ctr8, implicit $ctr8
     BC killed %1:crbitrc, %bb.1
     B %bb.2
 
   bb.2:
 
     BLR8 implicit $lr8, implicit $rm
 ...
 ---
 name:            test_fail_def_preheader
 # CHECK: test_fail_def_preheader
 tracksRegLiveness: true
 body:             |
   bb.0.entry:
 
     INLINEASM &"", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def early-clobber $ctr8
     %0:g8rc = LI8 2048
-    ; CHECK-NOT: MTCTR8
+    ; CHECK-NOT: MTCTR8loop
     ; CHECK-NOT: BDNZ8
     ; CHECK: ADDI8
     ; CHECK: CMPLDI
     ; CHECK: BC
-    MTCTR8Pseudo killed %0:g8rc, implicit-def dead $ctr8
+    MTCTR8loop killed %0:g8rc, implicit-def dead $ctr8
 
   bb.1:
 
-    %1:crbitrc = DecreaseCTR8Pseudo 1, implicit-def dead $ctr8, implicit $ctr8
+    %1:crbitrc = DecreaseCTR8loop 1, implicit-def dead $ctr8, implicit $ctr8
     BC killed %1:crbitrc, %bb.1
     B %bb.2
 
   bb.2:
 
     BLR8 implicit $lr8, implicit $rm
 ...
 ---
 name:            test_success_only_use_preheader
 # CHECK: test_success_only_use_preheader
 tracksRegLiveness: true
 body:             |
   bb.0.entry:
 
     %0:g8rc = MFCTR8 implicit $ctr8
     %1:g8rc = LI8 2048
-    ; CHECK: MTCTR8
+    ; CHECK: MTCTR8loop
     ; CHECK: BDNZ8
     ; CHECK-NOT: ADDI8
     ; CHECK-NOT: CMPLDI
     ; CHECK-NOT: BC
-    MTCTR8Pseudo killed %1:g8rc, implicit-def dead $ctr8
+    MTCTR8loop killed %1:g8rc, implicit-def dead $ctr8
 
   bb.1:
 
-    %2:crbitrc = DecreaseCTR8Pseudo 1, implicit-def dead $ctr8, implicit $ctr8
+    %2:crbitrc = DecreaseCTR8loop 1, implicit-def dead $ctr8, implicit $ctr8
     BC killed %2:crbitrc, %bb.1
     B %bb.2
 
   bb.2:
 
     BLR8 implicit $lr8, implicit $rm
 ...
 ---
 name:            test_fail_use_after_mtctr
 # CHECK: test_fail_use_after_mtctr
 tracksRegLiveness: true
 body:             |
   bb.0.entry:
 
     %0:g8rc = LI8 2048
-    ; CHECK-NOT: MTCTR8
+    ; CHECK-NOT: MTCTR8loop
     ; CHECK-NOT: BDNZ8
     ; CHECK: ADDI8
     ; CHECK: CMPLDI
     ; CHECK: BC
-    MTCTR8Pseudo killed %0:g8rc, implicit-def dead $ctr8
+    MTCTR8loop killed %0:g8rc, implicit-def dead $ctr8
     %1:g8rc = MFCTR8 implicit $ctr8
 
   bb.1:
 
-    %2:crbitrc = DecreaseCTR8Pseudo 1, implicit-def dead $ctr8, implicit $ctr8
+    %2:crbitrc = DecreaseCTR8loop 1, implicit-def dead $ctr8, implicit $ctr8
     BC killed %2:crbitrc, %bb.1
     B %bb.2
 
   bb.2:
 
     BLR8 implicit $lr8, implicit $rm
 ...
 ---
 name:            test_fail_def_after_mtctr
 # CHECK: test_fail_def_after_mtctr
 tracksRegLiveness: true
 body:             |
   bb.0.entry:
 
     %0:g8rc = LI8 2048
-    ; CHECK-NOT: MTCTR8
+    ; CHECK-NOT: MTCTR8loop
     ; CHECK-NOT: BDNZ8
     ; CHECK: ADDI8
     ; CHECK: CMPLDI
     ; CHECK: BC
-    MTCTR8Pseudo killed %0:g8rc, implicit-def dead $ctr8
+    MTCTR8loop killed %0:g8rc, implicit-def dead $ctr8
     INLINEASM &"", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def early-clobber $ctr8
 
   bb.1:
 
-    %2:crbitrc = DecreaseCTR8Pseudo 1, implicit-def dead $ctr8, implicit $ctr8
+    %2:crbitrc = DecreaseCTR8loop 1, implicit-def dead $ctr8, implicit $ctr8
     BC killed %2:crbitrc, %bb.1
     B %bb.2
 
   bb.2:
 
     BLR8 implicit $lr8, implicit $rm
 ...
 ---
 name:            test_success_def_after_loop
 # CHECK: test_success_def_after_loop
 tracksRegLiveness: true
 body:             |
   bb.0.entry:
 
     %0:g8rc = LI8 2048
-    ; CHECK: MTCTR8
+    ; CHECK: MTCTR8loop
     ; CHECK: BDNZ8
     ; CHECK-NOT: ADDI8
     ; CHECK-NOT: CMPLDI
     ; CHECK-NOT: BC
-    MTCTR8Pseudo killed %0:g8rc, implicit-def dead $ctr8
+    MTCTR8loop killed %0:g8rc, implicit-def dead $ctr8
 
   bb.1:
 
-    %2:crbitrc = DecreaseCTR8Pseudo 1, implicit-def dead $ctr8, implicit $ctr8
+    %2:crbitrc = DecreaseCTR8loop 1, implicit-def dead $ctr8, implicit $ctr8
     BC killed %2:crbitrc, %bb.1
     B %bb.2
 
   bb.2:
     INLINEASM &"", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def early-clobber $ctr8
 
     BLR8 implicit $lr8, implicit $rm
 ...

llvm/test/CodeGen/PowerPC/sms-phi.ll

 ; REQUIRES: asserts
 ; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -verify-machineinstrs\
 ; RUN:       -mcpu=pwr9 --ppc-enable-pipeliner -debug-only=pipeliner 2>&1 \
 ; RUN:       >/dev/null | FileCheck %s
 define dso_local void @sha512() #0 {
 ;CHECK: prolog:
-;CHECK:        %18:g8rc = ADD8 %24:g8rc, %23:g8rc
+;CHECK:        %{{[0-9]+}}:g8rc = ADD8 %{{[0-9]+}}:g8rc, %{{[0-9]+}}:g8rc
 ;CHECK: epilog:
-;CHECK:        %28:g8rc_and_g8rc_nox0 = PHI %6:g8rc_and_g8rc_nox0, %bb.3, %22:g8rc_and_g8rc_nox0, %bb.4
-;CHECK-NEXT:   %29:g8rc = PHI %12:g8rc, %bb.3, %16:g8rc, %bb.4
-;CHECK-NEXT:   %30:g8rc = PHI %15:g8rc, %bb.3, %19:g8rc, %bb.4
+;CHECK:        %{{[0-9]+}}:g8rc_and_g8rc_nox0 = PHI %{{[0-9]+}}:g8rc_and_g8rc_nox0, %bb.3, %{{[0-9]+}}:g8rc_and_g8rc_nox0, %bb.4
+;CHECK-NEXT:   %{{[0-9]+}}:g8rc = PHI %{{[0-9]+}}:g8rc, %bb.3, %{{[0-9]+}}:g8rc, %bb.4
+;CHECK-NEXT:   %{{[0-9]+}}:g8rc = PHI %{{[0-9]+}}:g8rc, %bb.3, %{{[0-9]+}}:g8rc, %bb.4
   br label %1
 
 1:                                                ; preds = %1, %0
   %2 = phi i64 [ 0, %0 ], [ %12, %1 ]
   %3 = phi i64 [ undef, %0 ], [ %11, %1 ]
   %4 = phi i64 [ undef, %0 ], [ %3, %1 ]
   %5 = getelementptr inbounds [80 x i64], [80 x i64]* null, i64 0, i64 %2
   %6 = load i64, i64* %5, align 8