[RISCV] Always select (and (srl X, C), Mask) as (srli (slli X, C2), C3).

[craig.topper]

Summary

SLLI is always compressible to C.SLLI as long as the source and dest
register is the same.

ANDI and SRLI are only compressible if the register is x8-x15. By
using SLLI we have a better chance of generating shorter code.

I had to exclude one exclusion for the BEXTI case so that it's
pattern match could still fire.

[luismarques]

LGTM.

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

if (!LeftShift && isMask_64(C1)) {
           SDNode *SRLIW = CurDAG->getMachineNode(
               RISCV::SRLIW, DL, XLenVT, SDValue(SRAIW, 0),
               CurDAG->getTargetConstant(C3 - 32, DL, XLenVT));
           ReplaceNode(Node, SRLIW);
           return;
         }
 
         // (srli (slli x, c3-c2), c3).
-        // Skip it in order to select sraiw.
+        // Skip if we could use (zext.w (sraiw X, C2)).
         bool Skip = Subtarget->hasStdExtZba() && C3 == 32 &&
                     X.getOpcode() == ISD::SIGN_EXTEND_INREG &&
                     cast<VTSDNode>(X.getOperand(1))->getVT() == MVT::i32;
-        if (OneUseOrZExtW && !IsCANDI && !Skip) {
+        // Also Skip if we can use bexti.
+        Skip |= Subtarget->hasStdExtZbs() && C3 == XLen - 1;
+        if (OneUseOrZExtW && !Skip) {
           SDNode *SLLI = CurDAG->getMachineNode(
               RISCV::SLLI, DL, XLenVT, X,
               CurDAG->getTargetConstant(C3 - C2, DL, XLenVT));
           SDNode *SRLI =
               CurDAG->getMachineNode(RISCV::SRLI, DL, XLenVT, SDValue(SLLI, 0),
                                      CurDAG->getTargetConstant(C3, DL, XLenVT));
           ReplaceNode(Node, SRLI);
           return;

llvm/test/CodeGen/RISCV/div-by-constant.ll

 define i8 @sdiv8_constant_no_srai(i8 %a) nounwind {
 ; RV32IM-LABEL: sdiv8_constant_no_srai:
 ; RV32IM:       # %bb.0:
 ; RV32IM-NEXT:    slli a0, a0, 24
 ; RV32IM-NEXT:    srai a0, a0, 24
 ; RV32IM-NEXT:    li a1, 86
 ; RV32IM-NEXT:    mul a0, a0, a1
 ; RV32IM-NEXT:    srli a1, a0, 8
-; RV32IM-NEXT:    srli a0, a0, 15
-; RV32IM-NEXT:    andi a0, a0, 1
+; RV32IM-NEXT:    slli a0, a0, 16
+; RV32IM-NEXT:    srli a0, a0, 31
 ; RV32IM-NEXT:    add a0, a1, a0
 ; RV32IM-NEXT:    ret
 ;
 ; RV32IMZB-LABEL: sdiv8_constant_no_srai:
 ; RV32IMZB:       # %bb.0:
 ; RV32IMZB-NEXT:    sext.b a0, a0
 ; RV32IMZB-NEXT:    li a1, 86
 ; RV32IMZB-NEXT:    mul a0, a0, a1
 ; RV32IMZB-NEXT:    srli a1, a0, 8
-; RV32IMZB-NEXT:    srli a0, a0, 15
-; RV32IMZB-NEXT:    andi a0, a0, 1
+; RV32IMZB-NEXT:    slli a0, a0, 16
+; RV32IMZB-NEXT:    srli a0, a0, 31
 ; RV32IMZB-NEXT:    add a0, a1, a0
 ; RV32IMZB-NEXT:    ret
 ;
 ; RV64IM-LABEL: sdiv8_constant_no_srai:
 ; RV64IM:       # %bb.0:
 ; RV64IM-NEXT:    slli a0, a0, 56
 ; RV64IM-NEXT:    srai a0, a0, 56
 ; RV64IM-NEXT:    li a1, 86
 ; RV64IM-NEXT:    mul a0, a0, a1
 ; RV64IM-NEXT:    srli a1, a0, 8
-; RV64IM-NEXT:    srli a0, a0, 15
-; RV64IM-NEXT:    andi a0, a0, 1
+; RV64IM-NEXT:    slli a0, a0, 48
+; RV64IM-NEXT:    srli a0, a0, 63
 ; RV64IM-NEXT:    add a0, a1, a0
 ; RV64IM-NEXT:    ret
 ;
 ; RV64IMZB-LABEL: sdiv8_constant_no_srai:
 ; RV64IMZB:       # %bb.0:
 ; RV64IMZB-NEXT:    sext.b a0, a0
 ; RV64IMZB-NEXT:    li a1, 86
 ; RV64IMZB-NEXT:    mul a0, a0, a1
 ; RV64IMZB-NEXT:    srli a1, a0, 8
-; RV64IMZB-NEXT:    srli a0, a0, 15
-; RV64IMZB-NEXT:    andi a0, a0, 1
+; RV64IMZB-NEXT:    slli a0, a0, 48
+; RV64IMZB-NEXT:    srli a0, a0, 63
 ; RV64IMZB-NEXT:    add a0, a1, a0
 ; RV64IMZB-NEXT:    ret
   %1 = sdiv i8 %a, 3
   ret i8 %1
 }
 
 define i8 @sdiv8_constant_srai(i8 %a) nounwind {
 ; RV32IM-LABEL: sdiv8_constant_srai:
 ; RV32IM:       # %bb.0:
 ; RV32IM-NEXT:    slli a0, a0, 24
 ; RV32IM-NEXT:    srai a0, a0, 24
 ; RV32IM-NEXT:    li a1, 103
 ; RV32IM-NEXT:    mul a0, a0, a1
 ; RV32IM-NEXT:    srai a1, a0, 9
-; RV32IM-NEXT:    srli a0, a0, 15
-; RV32IM-NEXT:    andi a0, a0, 1
+; RV32IM-NEXT:    slli a0, a0, 16
+; RV32IM-NEXT:    srli a0, a0, 31
 ; RV32IM-NEXT:    add a0, a1, a0
 ; RV32IM-NEXT:    ret
 ;
 ; RV32IMZB-LABEL: sdiv8_constant_srai:
 ; RV32IMZB:       # %bb.0:
 ; RV32IMZB-NEXT:    sext.b a0, a0
 ; RV32IMZB-NEXT:    li a1, 103
 ; RV32IMZB-NEXT:    mul a0, a0, a1
 ; RV32IMZB-NEXT:    srai a1, a0, 9
-; RV32IMZB-NEXT:    srli a0, a0, 15
-; RV32IMZB-NEXT:    andi a0, a0, 1
+; RV32IMZB-NEXT:    slli a0, a0, 16
+; RV32IMZB-NEXT:    srli a0, a0, 31
 ; RV32IMZB-NEXT:    add a0, a1, a0
 ; RV32IMZB-NEXT:    ret
 ;
 ; RV64IM-LABEL: sdiv8_constant_srai:
 ; RV64IM:       # %bb.0:
 ; RV64IM-NEXT:    slli a0, a0, 56
 ; RV64IM-NEXT:    srai a0, a0, 56
 ; RV64IM-NEXT:    li a1, 103
 ; RV64IM-NEXT:    mul a0, a0, a1
 ; RV64IM-NEXT:    srai a1, a0, 9
-; RV64IM-NEXT:    srli a0, a0, 15
-; RV64IM-NEXT:    andi a0, a0, 1
+; RV64IM-NEXT:    slli a0, a0, 48
+; RV64IM-NEXT:    srli a0, a0, 63
 ; RV64IM-NEXT:    add a0, a1, a0
 ; RV64IM-NEXT:    ret
 ;
 ; RV64IMZB-LABEL: sdiv8_constant_srai:
 ; RV64IMZB:       # %bb.0:
 ; RV64IMZB-NEXT:    sext.b a0, a0
 ; RV64IMZB-NEXT:    li a1, 103
 ; RV64IMZB-NEXT:    mul a0, a0, a1
 ; RV64IMZB-NEXT:    srai a1, a0, 9
-; RV64IMZB-NEXT:    srli a0, a0, 15
-; RV64IMZB-NEXT:    andi a0, a0, 1
+; RV64IMZB-NEXT:    slli a0, a0, 48
+; RV64IMZB-NEXT:    srli a0, a0, 63
 ; RV64IMZB-NEXT:    add a0, a1, a0
 ; RV64IMZB-NEXT:    ret
   %1 = sdiv i8 %a, 5
   ret i8 %1
 }
 
 define i8 @sdiv8_constant_add_srai(i8 %a) nounwind {
 ; RV32IM-LABEL: sdiv8_constant_add_srai:

llvm/test/CodeGen/RISCV/div.ll

 ;
 ; RV32IM-LABEL: sdiv8_constant:
 ; RV32IM:       # %bb.0:
 ; RV32IM-NEXT:    slli a0, a0, 24
 ; RV32IM-NEXT:    srai a0, a0, 24
 ; RV32IM-NEXT:    li a1, 103
 ; RV32IM-NEXT:    mul a0, a0, a1
 ; RV32IM-NEXT:    srai a1, a0, 9
-; RV32IM-NEXT:    srli a0, a0, 15
-; RV32IM-NEXT:    andi a0, a0, 1
+; RV32IM-NEXT:    slli a0, a0, 16
+; RV32IM-NEXT:    srli a0, a0, 31
 ; RV32IM-NEXT:    add a0, a1, a0
 ; RV32IM-NEXT:    ret
 ;
 ; RV64I-LABEL: sdiv8_constant:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    slli a0, a0, 56
 ; RV64I-NEXT:    srai a0, a0, 56
 ; RV64I-NEXT:    li a1, 5
 ; RV64I-NEXT:    call __divdi3@plt
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
 ;
 ; RV64IM-LABEL: sdiv8_constant:
 ; RV64IM:       # %bb.0:
 ; RV64IM-NEXT:    slli a0, a0, 56
 ; RV64IM-NEXT:    srai a0, a0, 56
 ; RV64IM-NEXT:    li a1, 103
 ; RV64IM-NEXT:    mul a0, a0, a1
 ; RV64IM-NEXT:    srai a1, a0, 9
-; RV64IM-NEXT:    srli a0, a0, 15
-; RV64IM-NEXT:    andi a0, a0, 1
+; RV64IM-NEXT:    slli a0, a0, 48
+; RV64IM-NEXT:    srli a0, a0, 63
 ; RV64IM-NEXT:    add a0, a1, a0
 ; RV64IM-NEXT:    ret
   %1 = sdiv i8 %a, 5
   ret i8 %1
 }
 
 define i8 @sdiv8_pow2(i8 %a) nounwind {
 ; RV32I-LABEL: sdiv8_pow2:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    slli a1, a0, 24
 ; RV32I-NEXT:    srai a1, a1, 24
-; RV32I-NEXT:    srli a1, a1, 12
-; RV32I-NEXT:    andi a1, a1, 7
+; RV32I-NEXT:    slli a1, a1, 17
+; RV32I-NEXT:    srli a1, a1, 29
 ; RV32I-NEXT:    add a0, a0, a1
 ; RV32I-NEXT:    slli a0, a0, 24
 ; RV32I-NEXT:    srai a0, a0, 27
 ; RV32I-NEXT:    ret
 ;
 ; RV32IM-LABEL: sdiv8_pow2:
 ; RV32IM:       # %bb.0:
 ; RV32IM-NEXT:    slli a1, a0, 24
 ; RV32IM-NEXT:    srai a1, a1, 24
-; RV32IM-NEXT:    srli a1, a1, 12
-; RV32IM-NEXT:    andi a1, a1, 7
+; RV32IM-NEXT:    slli a1, a1, 17
+; RV32IM-NEXT:    srli a1, a1, 29
 ; RV32IM-NEXT:    add a0, a0, a1
 ; RV32IM-NEXT:    slli a0, a0, 24
 ; RV32IM-NEXT:    srai a0, a0, 27
 ; RV32IM-NEXT:    ret
 ;
 ; RV64I-LABEL: sdiv8_pow2:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    slli a1, a0, 56
 ; RV64I-NEXT:    srai a1, a1, 56
-; RV64I-NEXT:    srli a1, a1, 12
-; RV64I-NEXT:    andi a1, a1, 7
+; RV64I-NEXT:    slli a1, a1, 49
+; RV64I-NEXT:    srli a1, a1, 61
 ; RV64I-NEXT:    addw a0, a0, a1
 ; RV64I-NEXT:    slli a0, a0, 56
 ; RV64I-NEXT:    srai a0, a0, 59
 ; RV64I-NEXT:    ret
 ;
 ; RV64IM-LABEL: sdiv8_pow2:
 ; RV64IM:       # %bb.0:
 ; RV64IM-NEXT:    slli a1, a0, 56
 ; RV64IM-NEXT:    srai a1, a1, 56
-; RV64IM-NEXT:    srli a1, a1, 12
-; RV64IM-NEXT:    andi a1, a1, 7
+; RV64IM-NEXT:    slli a1, a1, 49
+; RV64IM-NEXT:    srli a1, a1, 61
 ; RV64IM-NEXT:    addw a0, a0, a1
 ; RV64IM-NEXT:    slli a0, a0, 56
 ; RV64IM-NEXT:    srai a0, a0, 59
 ; RV64IM-NEXT:    ret
   %1 = sdiv i8 %a, 8
   ret i8 %1
 }
 
; RV64IM-NEXT:    ret
   ret i16 %1
 }
 
 define i16 @sdiv16_pow2(i16 %a) nounwind {
 ; RV32I-LABEL: sdiv16_pow2:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    slli a1, a0, 16
 ; RV32I-NEXT:    srai a1, a1, 16
-; RV32I-NEXT:    srli a1, a1, 28
-; RV32I-NEXT:    andi a1, a1, 7
+; RV32I-NEXT:    slli a1, a1, 1
+; RV32I-NEXT:    srli a1, a1, 29
 ; RV32I-NEXT:    add a0, a0, a1
 ; RV32I-NEXT:    slli a0, a0, 16
 ; RV32I-NEXT:    srai a0, a0, 19
 ; RV32I-NEXT:    ret
 ;
 ; RV32IM-LABEL: sdiv16_pow2:
 ; RV32IM:       # %bb.0:
 ; RV32IM-NEXT:    slli a1, a0, 16
 ; RV32IM-NEXT:    srai a1, a1, 16
-; RV32IM-NEXT:    srli a1, a1, 28
-; RV32IM-NEXT:    andi a1, a1, 7
+; RV32IM-NEXT:    slli a1, a1, 1
+; RV32IM-NEXT:    srli a1, a1, 29
 ; RV32IM-NEXT:    add a0, a0, a1
 ; RV32IM-NEXT:    slli a0, a0, 16
 ; RV32IM-NEXT:    srai a0, a0, 19
 ; RV32IM-NEXT:    ret
 ;
 ; RV64I-LABEL: sdiv16_pow2:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    slli a1, a0, 48
 ; RV64I-NEXT:    srai a1, a1, 48
-; RV64I-NEXT:    srli a1, a1, 28
-; RV64I-NEXT:    andi a1, a1, 7
+; RV64I-NEXT:    slli a1, a1, 33
+; RV64I-NEXT:    srli a1, a1, 61
 ; RV64I-NEXT:    addw a0, a0, a1
 ; RV64I-NEXT:    slli a0, a0, 48
 ; RV64I-NEXT:    srai a0, a0, 51
 ; RV64I-NEXT:    ret
 ;
 ; RV64IM-LABEL: sdiv16_pow2:
 ; RV64IM:       # %bb.0:
 ; RV64IM-NEXT:    slli a1, a0, 48
 ; RV64IM-NEXT:    srai a1, a1, 48
-; RV64IM-NEXT:    srli a1, a1, 28
-; RV64IM-NEXT:    andi a1, a1, 7
+; RV64IM-NEXT:    slli a1, a1, 33
+; RV64IM-NEXT:    srli a1, a1, 61
 ; RV64IM-NEXT:    addw a0, a0, a1
 ; RV64IM-NEXT:    slli a0, a0, 48
 ; RV64IM-NEXT:    srai a0, a0, 51
 ; RV64IM-NEXT:    ret
   %1 = sdiv i16 %a, 8
   ret i16 %1
 }
 

llvm/test/CodeGen/RISCV/rv32zbb-zbp-zbkb.ll

 ; This test is presented here in case future expansions of the Bitmanip
 ; extensions introduce instructions suitable for this pattern.
 
 declare i64 @llvm.fshl.i64(i64, i64, i64)
 
 define i64 @rol_i64(i64 %a, i64 %b) nounwind {
 ; RV32I-LABEL: rol_i64:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    srli a3, a2, 5
-; RV32I-NEXT:    andi a3, a3, 1
+; RV32I-NEXT:    slli a3, a2, 26
+; RV32I-NEXT:    srli a3, a3, 31
 ; RV32I-NEXT:    mv a4, a1
 ; RV32I-NEXT:    bnez a3, .LBB7_2
 ; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    mv a4, a0
 ; RV32I-NEXT:  .LBB7_2:
 ; RV32I-NEXT:    sll a5, a4, a2
 ; RV32I-NEXT:    bnez a3, .LBB7_4
 ; RV32I-NEXT:  # %bb.3:
 ; RV32I-NEXT:    mv a0, a1
 ; RV32I-NEXT:  .LBB7_4:
 ; RV32I-NEXT:    srli a1, a0, 1
 ; RV32I-NEXT:    not a6, a2
 ; RV32I-NEXT:    srl a1, a1, a6
 ; RV32I-NEXT:    or a3, a5, a1
 ; RV32I-NEXT:    sll a0, a0, a2
 ; RV32I-NEXT:    srli a1, a4, 1
 ; RV32I-NEXT:    srl a1, a1, a6
 ; RV32I-NEXT:    or a1, a0, a1
 ; RV32I-NEXT:    mv a0, a3
 ; RV32I-NEXT:    ret
 ;
 ; RV32ZBB-ZBP-ZBKB-LABEL: rol_i64:
 ; RV32ZBB-ZBP-ZBKB:       # %bb.0:
-; RV32ZBB-ZBP-ZBKB-NEXT:    srli a3, a2, 5
-; RV32ZBB-ZBP-ZBKB-NEXT:    andi a3, a3, 1
+; RV32ZBB-ZBP-ZBKB-NEXT:    slli a3, a2, 26
+; RV32ZBB-ZBP-ZBKB-NEXT:    srli a3, a3, 31
 ; RV32ZBB-ZBP-ZBKB-NEXT:    mv a4, a1
 ; RV32ZBB-ZBP-ZBKB-NEXT:    bnez a3, .LBB7_2
 ; RV32ZBB-ZBP-ZBKB-NEXT:  # %bb.1:
 ; RV32ZBB-ZBP-ZBKB-NEXT:    mv a4, a0
 ; RV32ZBB-ZBP-ZBKB-NEXT:  .LBB7_2:
 ; RV32ZBB-ZBP-ZBKB-NEXT:    sll a5, a4, a2
 ; RV32ZBB-ZBP-ZBKB-NEXT:    bnez a3, .LBB7_4
 ; RV32ZBB-ZBP-ZBKB-NEXT:  # %bb.3:

llvm/test/CodeGen/RISCV/rv32zbs.ll

; RV32ZBS-NEXT:    ret
   %shr = lshr i64 %a, %conv
   %and1 = and i64 %shr, 1
   ret i64 %and1
 }
 
 define i32 @bexti_i32(i32 %a) nounwind {
 ; RV32I-LABEL: bexti_i32:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    srli a0, a0, 5
-; RV32I-NEXT:    andi a0, a0, 1
+; RV32I-NEXT:    slli a0, a0, 26
+; RV32I-NEXT:    srli a0, a0, 31
 ; RV32I-NEXT:    ret
 ;
 ; RV32ZBS-LABEL: bexti_i32:
 ; RV32ZBS:       # %bb.0:
 ; RV32ZBS-NEXT:    bexti a0, a0, 5
 ; RV32ZBS-NEXT:    ret
   %shr = lshr i32 %a, 5
   %and = and i32 %shr, 1
   ret i32 %and
 }
 
 define i64 @bexti_i64(i64 %a) nounwind {
 ; RV32I-LABEL: bexti_i64:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    srli a0, a0, 5
-; RV32I-NEXT:    andi a0, a0, 1
+; RV32I-NEXT:    slli a0, a0, 26
+; RV32I-NEXT:    srli a0, a0, 31
 ; RV32I-NEXT:    li a1, 0
 ; RV32I-NEXT:    ret
 ;
 ; RV32ZBS-LABEL: bexti_i64:
 ; RV32ZBS:       # %bb.0:
 ; RV32ZBS-NEXT:    bexti a0, a0, 5
 ; RV32ZBS-NEXT:    li a1, 0
 ; RV32ZBS-NEXT:    ret

llvm/test/CodeGen/RISCV/rv32zbt.ll

 ; This test is presented here in case future expansions of the Bitmanip
 ; extensions introduce instructions that can match more efficiently this pattern.
 
 declare i64 @llvm.fshl.i64(i64, i64, i64)
 
 define i64 @fshl_i64(i64 %a, i64 %b, i64 %c) nounwind {
 ; RV32I-LABEL: fshl_i64:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    srli a5, a4, 5
-; RV32I-NEXT:    andi a6, a5, 1
+; RV32I-NEXT:    slli a5, a4, 26
+; RV32I-NEXT:    srli a6, a5, 31
 ; RV32I-NEXT:    mv a5, a3
 ; RV32I-NEXT:    bnez a6, .LBB36_2
 ; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    mv a5, a0
 ; RV32I-NEXT:  .LBB36_2:
 ; RV32I-NEXT:    sll a7, a5, a4
 ; RV32I-NEXT:    bnez a6, .LBB36_4
 ; RV32I-NEXT:  # %bb.3:

 ; RV32I-NEXT:    srli a1, a5, 1
 ; RV32I-NEXT:    srl a1, a1, a3
 ; RV32I-NEXT:    or a1, a0, a1
 ; RV32I-NEXT:    mv a0, a2
 ; RV32I-NEXT:    ret
 ;
 ; RV32ZBT-LABEL: fshl_i64:
 ; RV32ZBT:       # %bb.0:
-; RV32ZBT-NEXT:    srli a5, a4, 5
-; RV32ZBT-NEXT:    andi a5, a5, 1
+; RV32ZBT-NEXT:    slli a5, a4, 26
+; RV32ZBT-NEXT:    srli a5, a5, 31
 ; RV32ZBT-NEXT:    cmov a2, a5, a2, a3
 ; RV32ZBT-NEXT:    cmov a3, a5, a3, a0
 ; RV32ZBT-NEXT:    andi a4, a4, 31
 ; RV32ZBT-NEXT:    fsl a2, a3, a2, a4
 ; RV32ZBT-NEXT:    cmov a0, a5, a0, a1
 ; RV32ZBT-NEXT:    fsl a1, a0, a3, a4
 ; RV32ZBT-NEXT:    mv a0, a2
 ; RV32ZBT-NEXT:    ret

llvm/test/CodeGen/RISCV/rv64zbs.ll

; RV64ZBS-NEXT:    ret
   %shr = lshr i64 %a, %b
   %and1 = and i64 %shr, 1
   ret i64 %and1
 }
 
 define signext i32 @bexti_i32(i32 signext %a) nounwind {
 ; RV64I-LABEL: bexti_i32:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    srli a0, a0, 5
-; RV64I-NEXT:    andi a0, a0, 1
+; RV64I-NEXT:    slli a0, a0, 58
+; RV64I-NEXT:    srli a0, a0, 63
 ; RV64I-NEXT:    ret
 ;
 ; RV64ZBS-LABEL: bexti_i32:
 ; RV64ZBS:       # %bb.0:
 ; RV64ZBS-NEXT:    bexti a0, a0, 5
 ; RV64ZBS-NEXT:    ret
   %shr = lshr i32 %a, 5
   %and = and i32 %shr, 1
   ret i32 %and
 }
 
 define i64 @bexti_i64(i64 %a) nounwind {
 ; RV64I-LABEL: bexti_i64:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    srli a0, a0, 5
-; RV64I-NEXT:    andi a0, a0, 1
+; RV64I-NEXT:    slli a0, a0, 58
+; RV64I-NEXT:    srli a0, a0, 63
 ; RV64I-NEXT:    ret
 ;
 ; RV64ZBS-LABEL: bexti_i64:
 ; RV64ZBS:       # %bb.0:
 ; RV64ZBS-NEXT:    bexti a0, a0, 5
 ; RV64ZBS-NEXT:    ret
   %shr = lshr i64 %a, 5
   %and = and i64 %shr, 1

llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll

; RV64MV-NEXT:    ret
   ret i1 %cmp
 }
 
 define i1 @test_srem_pow2_setne(i6 %X) nounwind {
 ; RV32-LABEL: test_srem_pow2_setne:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    slli a1, a0, 26
 ; RV32-NEXT:    srai a1, a1, 26
-; RV32-NEXT:    srli a1, a1, 9
-; RV32-NEXT:    andi a1, a1, 3
+; RV32-NEXT:    slli a1, a1, 21
+; RV32-NEXT:    srli a1, a1, 30
 ; RV32-NEXT:    add a1, a0, a1
 ; RV32-NEXT:    andi a1, a1, 60
 ; RV32-NEXT:    sub a0, a0, a1
 ; RV32-NEXT:    andi a0, a0, 63
 ; RV32-NEXT:    snez a0, a0
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: test_srem_pow2_setne:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    slli a1, a0, 58
 ; RV64-NEXT:    srai a1, a1, 58
-; RV64-NEXT:    srli a1, a1, 9
-; RV64-NEXT:    andi a1, a1, 3
+; RV64-NEXT:    slli a1, a1, 53
+; RV64-NEXT:    srli a1, a1, 62
 ; RV64-NEXT:    addw a1, a0, a1
 ; RV64-NEXT:    andi a1, a1, 60
 ; RV64-NEXT:    subw a0, a0, a1
 ; RV64-NEXT:    andi a0, a0, 63
 ; RV64-NEXT:    snez a0, a0
 ; RV64-NEXT:    ret
 ;
 ; RV32M-LABEL: test_srem_pow2_setne:
 ; RV32M:       # %bb.0:
 ; RV32M-NEXT:    slli a1, a0, 26
 ; RV32M-NEXT:    srai a1, a1, 26
-; RV32M-NEXT:    srli a1, a1, 9
-; RV32M-NEXT:    andi a1, a1, 3
+; RV32M-NEXT:    slli a1, a1, 21
+; RV32M-NEXT:    srli a1, a1, 30
 ; RV32M-NEXT:    add a1, a0, a1
 ; RV32M-NEXT:    andi a1, a1, 60
 ; RV32M-NEXT:    sub a0, a0, a1
 ; RV32M-NEXT:    andi a0, a0, 63
 ; RV32M-NEXT:    snez a0, a0
 ; RV32M-NEXT:    ret
 ;
 ; RV64M-LABEL: test_srem_pow2_setne:
 ; RV64M:       # %bb.0:
 ; RV64M-NEXT:    slli a1, a0, 58
 ; RV64M-NEXT:    srai a1, a1, 58
-; RV64M-NEXT:    srli a1, a1, 9
-; RV64M-NEXT:    andi a1, a1, 3
+; RV64M-NEXT:    slli a1, a1, 53
+; RV64M-NEXT:    srli a1, a1, 62
 ; RV64M-NEXT:    addw a1, a0, a1
 ; RV64M-NEXT:    andi a1, a1, 60
 ; RV64M-NEXT:    subw a0, a0, a1
 ; RV64M-NEXT:    andi a0, a0, 63
 ; RV64M-NEXT:    snez a0, a0
 ; RV64M-NEXT:    ret
 ;
 ; RV32MV-LABEL: test_srem_pow2_setne:
 ; RV32MV:       # %bb.0:
 ; RV32MV-NEXT:    slli a1, a0, 26
 ; RV32MV-NEXT:    srai a1, a1, 26
-; RV32MV-NEXT:    srli a1, a1, 9
-; RV32MV-NEXT:    andi a1, a1, 3
+; RV32MV-NEXT:    slli a1, a1, 21
+; RV32MV-NEXT:    srli a1, a1, 30
 ; RV32MV-NEXT:    add a1, a0, a1
 ; RV32MV-NEXT:    andi a1, a1, 60
 ; RV32MV-NEXT:    sub a0, a0, a1
 ; RV32MV-NEXT:    andi a0, a0, 63
 ; RV32MV-NEXT:    snez a0, a0
 ; RV32MV-NEXT:    ret
 ;
 ; RV64MV-LABEL: test_srem_pow2_setne:
 ; RV64MV:       # %bb.0:
 ; RV64MV-NEXT:    slli a1, a0, 58
 ; RV64MV-NEXT:    srai a1, a1, 58
-; RV64MV-NEXT:    srli a1, a1, 9
-; RV64MV-NEXT:    andi a1, a1, 3
+; RV64MV-NEXT:    slli a1, a1, 53
+; RV64MV-NEXT:    srli a1, a1, 62
 ; RV64MV-NEXT:    addw a1, a0, a1
 ; RV64MV-NEXT:    andi a1, a1, 60
 ; RV64MV-NEXT:    subw a0, a0, a1
 ; RV64MV-NEXT:    andi a0, a0, 63
 ; RV64MV-NEXT:    snez a0, a0
 ; RV64MV-NEXT:    ret
   %srem = srem i6 %X, 4
   %cmp = icmp ne i6 %srem, 0

 ; RV32-NEXT:    lw a0, 4(a0)
 ; RV32-NEXT:    lbu a1, 12(s0)
 ; RV32-NEXT:    lw a2, 8(s0)
 ; RV32-NEXT:    andi a3, a0, 1
 ; RV32-NEXT:    neg s1, a3
 ; RV32-NEXT:    slli a3, a1, 30
 ; RV32-NEXT:    srli a4, a2, 2
 ; RV32-NEXT:    or s2, a4, a3
-; RV32-NEXT:    srli a1, a1, 2
-; RV32-NEXT:    andi a1, a1, 1
+; RV32-NEXT:    slli a1, a1, 29
+; RV32-NEXT:    srli a1, a1, 31
 ; RV32-NEXT:    neg s3, a1
 ; RV32-NEXT:    slli a1, a2, 31
 ; RV32-NEXT:    srli a0, a0, 1
 ; RV32-NEXT:    or a0, a0, a1
 ; RV32-NEXT:    lw s4, 0(s0)
-; RV32-NEXT:    srli a1, a2, 1
-; RV32-NEXT:    andi a1, a1, 1
+; RV32-NEXT:    slli a1, a2, 30
+; RV32-NEXT:    srli a1, a1, 31
 ; RV32-NEXT:    neg a1, a1
 ; RV32-NEXT:    li a2, 7
 ; RV32-NEXT:    li a3, 0
 ; RV32-NEXT:    call __moddi3@plt
 ; RV32-NEXT:    mv s5, a0
 ; RV32-NEXT:    mv s6, a1
 ; RV32-NEXT:    li a2, -5
 ; RV32-NEXT:    li a3, -1

 ; RV32M-NEXT:    lw a0, 4(a0)
 ; RV32M-NEXT:    lbu a1, 12(s0)
 ; RV32M-NEXT:    lw a2, 8(s0)
 ; RV32M-NEXT:    andi a3, a0, 1
 ; RV32M-NEXT:    neg s1, a3
 ; RV32M-NEXT:    slli a3, a1, 30
 ; RV32M-NEXT:    srli a4, a2, 2
 ; RV32M-NEXT:    or s2, a4, a3
-; RV32M-NEXT:    srli a1, a1, 2
-; RV32M-NEXT:    andi a1, a1, 1
+; RV32M-NEXT:    slli a1, a1, 29
+; RV32M-NEXT:    srli a1, a1, 31
 ; RV32M-NEXT:    neg s3, a1
 ; RV32M-NEXT:    slli a1, a2, 31
 ; RV32M-NEXT:    srli a0, a0, 1
 ; RV32M-NEXT:    or a0, a0, a1
 ; RV32M-NEXT:    lw s4, 0(s0)
-; RV32M-NEXT:    srli a1, a2, 1
-; RV32M-NEXT:    andi a1, a1, 1
+; RV32M-NEXT:    slli a1, a2, 30
+; RV32M-NEXT:    srli a1, a1, 31
 ; RV32M-NEXT:    neg a1, a1
 ; RV32M-NEXT:    li a2, 7
 ; RV32M-NEXT:    li a3, 0
 ; RV32M-NEXT:    call __moddi3@plt
 ; RV32M-NEXT:    mv s5, a0
 ; RV32M-NEXT:    mv s6, a1
 ; RV32M-NEXT:    li a2, -5
 ; RV32M-NEXT:    li a3, -1

 ; RV32MV-NEXT:    andi sp, sp, -32
 ; RV32MV-NEXT:    mv s2, a0
 ; RV32MV-NEXT:    lw a0, 8(a0)
 ; RV32MV-NEXT:    lw a1, 4(s2)
 ; RV32MV-NEXT:    slli a2, a0, 31
 ; RV32MV-NEXT:    srli a3, a1, 1
 ; RV32MV-NEXT:    or s3, a3, a2
 ; RV32MV-NEXT:    lbu a2, 12(s2)
-; RV32MV-NEXT:    srli a3, a0, 1
-; RV32MV-NEXT:    andi a3, a3, 1
+; RV32MV-NEXT:    slli a3, a0, 30
+; RV32MV-NEXT:    srli a3, a3, 31
 ; RV32MV-NEXT:    neg s4, a3
 ; RV32MV-NEXT:    slli a3, a2, 30
 ; RV32MV-NEXT:    srli a0, a0, 2
 ; RV32MV-NEXT:    or s5, a0, a3
-; RV32MV-NEXT:    srli a0, a2, 2
-; RV32MV-NEXT:    andi a2, a0, 1
+; RV32MV-NEXT:    slli a0, a2, 29
+; RV32MV-NEXT:    srli a2, a0, 31
 ; RV32MV-NEXT:    lw a0, 0(s2)
 ; RV32MV-NEXT:    neg s6, a2
 ; RV32MV-NEXT:    andi a1, a1, 1
 ; RV32MV-NEXT:    neg a1, a1
 ; RV32MV-NEXT:    li a2, 6
 ; RV32MV-NEXT:    li a3, 0
 ; RV32MV-NEXT:    call __moddi3@plt
 ; RV32MV-NEXT:    sw a1, 36(sp)

 ; RV64MV-NEXT:    srli a1, a1, 31
 ; RV64MV-NEXT:    vand.vx v8, v8, a1
 ; RV64MV-NEXT:    vmsne.vv v0, v8, v10
 ; RV64MV-NEXT:    vmv.v.i v8, 0
 ; RV64MV-NEXT:    vmerge.vim v8, v8, -1, v0
 ; RV64MV-NEXT:    vsetivli zero, 1, e64, m2, ta, mu
 ; RV64MV-NEXT:    vslidedown.vi v10, v8, 2
 ; RV64MV-NEXT:    vmv.x.s a2, v10
-; RV64MV-NEXT:    srli a3, a2, 30
-; RV64MV-NEXT:    andi a3, a3, 7
+; RV64MV-NEXT:    slli a3, a2, 31
+; RV64MV-NEXT:    srli a3, a3, 61
 ; RV64MV-NEXT:    sb a3, 12(a0)
 ; RV64MV-NEXT:    slli a2, a2, 2
 ; RV64MV-NEXT:    vslidedown.vi v10, v8, 1
 ; RV64MV-NEXT:    vmv.x.s a3, v10
 ; RV64MV-NEXT:    and a3, a3, a1
 ; RV64MV-NEXT:    srli a4, a3, 31
 ; RV64MV-NEXT:    or a2, a4, a2
 ; RV64MV-NEXT:    sw a2, 8(a0)

llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll

 ; RV32-NEXT:    call __mulsi3@plt
 ; RV32-NEXT:    addi a0, a0, -1463
 ; RV32-NEXT:    andi a0, a0, 2047
 ; RV32-NEXT:    sltiu a0, a0, 293
 ; RV32-NEXT:    xori a0, a0, 1
 ; RV32-NEXT:    neg a1, s3
 ; RV32-NEXT:    neg a0, a0
 ; RV32-NEXT:    neg a2, s1
-; RV32-NEXT:    srli a2, a2, 10
-; RV32-NEXT:    andi a2, a2, 1
+; RV32-NEXT:    slli a2, a2, 21
+; RV32-NEXT:    srli a2, a2, 31
 ; RV32-NEXT:    sb a2, 4(s0)
 ; RV32-NEXT:    andi a1, a1, 2047
 ; RV32-NEXT:    andi a0, a0, 2047
 ; RV32-NEXT:    slli a0, a0, 11
 ; RV32-NEXT:    or a0, a1, a0
 ; RV32-NEXT:    slli a1, s1, 22
 ; RV32-NEXT:    sub a0, a0, a1
 ; RV32-NEXT:    sw a0, 0(s0)

 ; RV32M-NEXT:    mul a3, a3, a4
 ; RV32M-NEXT:    addi a3, a3, -1463
 ; RV32M-NEXT:    andi a3, a3, 2047
 ; RV32M-NEXT:    sltiu a3, a3, 293
 ; RV32M-NEXT:    xori a3, a3, 1
 ; RV32M-NEXT:    neg a2, a2
 ; RV32M-NEXT:    neg a3, a3
 ; RV32M-NEXT:    neg a4, a1
-; RV32M-NEXT:    srli a4, a4, 10
-; RV32M-NEXT:    andi a4, a4, 1
+; RV32M-NEXT:    slli a4, a4, 21
+; RV32M-NEXT:    srli a4, a4, 31
 ; RV32M-NEXT:    sb a4, 4(a0)
 ; RV32M-NEXT:    andi a2, a2, 2047
 ; RV32M-NEXT:    andi a3, a3, 2047
 ; RV32M-NEXT:    slli a3, a3, 11
 ; RV32M-NEXT:    or a2, a2, a3
 ; RV32M-NEXT:    slli a1, a1, 22
 ; RV32M-NEXT:    sub a1, a2, a1
 ; RV32M-NEXT:    sw a1, 0(a0)

 ; RV32MV-NEXT:    vsrl.vv v8, v8, v11
 ; RV32MV-NEXT:    vor.vv v8, v8, v9
 ; RV32MV-NEXT:    vand.vx v8, v8, a1
 ; RV32MV-NEXT:    vmsltu.vv v0, v12, v8
 ; RV32MV-NEXT:    vmerge.vim v8, v10, -1, v0
 ; RV32MV-NEXT:    vsetivli zero, 1, e16, mf2, ta, mu
 ; RV32MV-NEXT:    vslidedown.vi v9, v8, 2
 ; RV32MV-NEXT:    vmv.x.s a1, v9
-; RV32MV-NEXT:    srli a2, a1, 10
-; RV32MV-NEXT:    andi a2, a2, 1
+; RV32MV-NEXT:    slli a2, a1, 21
+; RV32MV-NEXT:    srli a2, a2, 31
 ; RV32MV-NEXT:    sb a2, 4(a0)
 ; RV32MV-NEXT:    vmv.x.s a2, v8
 ; RV32MV-NEXT:    andi a2, a2, 2047
 ; RV32MV-NEXT:    vslidedown.vi v8, v8, 1
 ; RV32MV-NEXT:    vmv.x.s a3, v8
 ; RV32MV-NEXT:    andi a3, a3, 2047
 ; RV32MV-NEXT:    slli a3, a3, 11
 ; RV32MV-NEXT:    or a2, a2, a3