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Differential D123256

[TargetLowering][RISCV] Allow truncation when checking if the arguments of a setcc are splats.
ClosedPublic

Authored by craig.topper on Apr 6 2022, 2:27 PM.

Details

Reviewers
spatel
frasercrmck
Commits
rG28cb508195be: [TargetLowering][RISCV] Allow truncation when checking if the arguments of a…
Summary

We're just trying to canonicalize here and won't be using the constant
value returned.

The attached test changes are because we were previously commuting
a seteq X, (splat_vector 0) because we also have (sub 0, X). The
0 is larger than the element type so we don't detect it as a splat
without the AllowTruncation flag. By preventing the commute we are
able to match it to the vmseq.vx instruction during isel. We only
look for constants on the RHS in isel.

Diff Detail

Unit TestsFailed

TimeTest
60,040 msx64 debian > MLIR.Examples/standalone::test.toy
60,160 msx64 debian > ThreadSanitizer-x86_64.ThreadSanitizer-x86_64::restore_stack.cpp
60,110 msx64 debian > libFuzzer.libFuzzer::large.test

Event Timeline

craig.topper created this revision.Apr 6 2022, 2:27 PM
Herald added a project: Restricted Project. · View Herald TranscriptApr 6 2022, 2:27 PM
Herald added subscribers: sunshaoce, VincentWu, luke957 and 28 others. · View Herald Transcript
craig.topper requested review of this revision.Apr 6 2022, 2:27 PM
Herald added a project: Restricted Project. · View Herald TranscriptApr 6 2022, 2:27 PM
Herald added subscribers: • pcwang-thead, eopXD, MaskRay. · View Herald Transcript
craig.topper retitled this revision from [TargetLowering][RISCV] Allow truncation if the arguments of a setcc are splats. to [TargetLowering][RISCV] Allow truncation when checking if the arguments of a setcc are splats..Apr 6 2022, 2:34 PM
craig.topper mentioned this in D123255: [RISCV] Add more .vx patterns for VLMax integer setccs..
Harbormaster completed remote builds in B158341: Diff 421014.Apr 6 2022, 4:16 PM
spatel accepted this revision.Apr 11 2022, 9:01 AM

I don't know enough to comment on the test diffs, but the code change LGTM.

This revision is now accepted and ready to land.Apr 11 2022, 9:01 AM
This revision was landed with ongoing or failed builds.Apr 11 2022, 9:50 AM
Closed by commit rG28cb508195be: [TargetLowering][RISCV] Allow truncation when checking if the arguments of a… (authored by craig.topper). · Explain Why
This revision was automatically updated to reflect the committed changes.
craig.topper added a commit: rG28cb508195be: [TargetLowering][RISCV] Allow truncation when checking if the arguments of a….

Revision Contents

PathSize
llvm/
lib/
CodeGen/
SelectionDAG/
10 lines
test/
CodeGen/
RISCV/
rvv/
340 lines

Diff 421014

llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
//===-- TargetLowering.cpp - Implement the TargetLowering class -----------===// //===-- TargetLowering.cpp - Implement the TargetLowering class -----------===//
Lint: Lint
Inline Actions

clang-format not found in user’s local PATH; not linting file.

Lint: Lint: clang-format not found in user’s local PATH; not linting file.
// //
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information. // See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// //
▲ Show 20 Lines • Show All 3,873 Lines • ▼ Show 20 LinesSDValue TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
SelectionDAG &DAG = DCI.DAG; SelectionDAG &DAG = DCI.DAG;
const DataLayout &Layout = DAG.getDataLayout(); const DataLayout &Layout = DAG.getDataLayout();
EVT OpVT = N0.getValueType(); EVT OpVT = N0.getValueType();
// Constant fold or commute setcc. // Constant fold or commute setcc.
if (SDValue Fold = DAG.FoldSetCC(VT, N0, N1, Cond, dl)) if (SDValue Fold = DAG.FoldSetCC(VT, N0, N1, Cond, dl))
return Fold; return Fold;
bool N0ConstOrSplat =
isConstOrConstSplat(N0, /*AllowUndefs*/ false, /*AllowTruncate*/ true);
bool N1ConstOrSplat =
isConstOrConstSplat(N1, /*AllowUndefs*/ false, /*AllowTruncate*/ true);
// Ensure that the constant occurs on the RHS and fold constant comparisons. // Ensure that the constant occurs on the RHS and fold constant comparisons.
// TODO: Handle non-splat vector constants. All undef causes trouble. // TODO: Handle non-splat vector constants. All undef causes trouble.
// FIXME: We can't yet fold constant scalable vector splats, so avoid an // FIXME: We can't yet fold constant scalable vector splats, so avoid an
// infinite loop here when we encounter one. // infinite loop here when we encounter one.
ISD::CondCode SwappedCC = ISD::getSetCCSwappedOperands(Cond); ISD::CondCode SwappedCC = ISD::getSetCCSwappedOperands(Cond);
if (isConstOrConstSplat(N0) && if (N0ConstOrSplat && (!OpVT.isScalableVector() || !N1ConstOrSplat) &&
(!OpVT.isScalableVector() || !isConstOrConstSplat(N1)) &&
(DCI.isBeforeLegalizeOps() || (DCI.isBeforeLegalizeOps() ||
isCondCodeLegal(SwappedCC, N0.getSimpleValueType()))) isCondCodeLegal(SwappedCC, N0.getSimpleValueType())))
return DAG.getSetCC(dl, VT, N1, N0, SwappedCC); return DAG.getSetCC(dl, VT, N1, N0, SwappedCC);
// If we have a subtract with the same 2 non-constant operands as this setcc // If we have a subtract with the same 2 non-constant operands as this setcc
// -- but in reverse order -- then try to commute the operands of this setcc // -- but in reverse order -- then try to commute the operands of this setcc
// to match. A matching pair of setcc (cmp) and sub may be combined into 1 // to match. A matching pair of setcc (cmp) and sub may be combined into 1
// instruction on some targets. // instruction on some targets.
if (!isConstOrConstSplat(N0) && !isConstOrConstSplat(N1) && if (!N0ConstOrSplat && !N1ConstOrSplat &&
(DCI.isBeforeLegalizeOps() || (DCI.isBeforeLegalizeOps() ||
isCondCodeLegal(SwappedCC, N0.getSimpleValueType())) && isCondCodeLegal(SwappedCC, N0.getSimpleValueType())) &&
DAG.doesNodeExist(ISD::SUB, DAG.getVTList(OpVT), {N1, N0}) && DAG.doesNodeExist(ISD::SUB, DAG.getVTList(OpVT), {N1, N0}) &&
!DAG.doesNodeExist(ISD::SUB, DAG.getVTList(OpVT), {N0, N1})) !DAG.doesNodeExist(ISD::SUB, DAG.getVTList(OpVT), {N0, N1}))
return DAG.getSetCC(dl, VT, N1, N0, SwappedCC); return DAG.getSetCC(dl, VT, N1, N0, SwappedCC);
if (SDValue V = foldSetCCWithRotate(VT, N0, N1, Cond, dl, DAG)) if (SDValue V = foldSetCCWithRotate(VT, N0, N1, Cond, dl, DAG))
return V; return V;
▲ Show 20 Lines • Show All 5,419 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/cttz-sdnode.ll

Show First 20 Lines • Show All 44 Lines • ▼ Show 20 Lines
; RV64I-NEXT: vsrl.vi v9, v8, 4 ; RV64I-NEXT: vsrl.vi v9, v8, 4
; RV64I-NEXT: vadd.vv v8, v8, v9 ; RV64I-NEXT: vadd.vv v8, v8, v9
; RV64I-NEXT: vand.vi v8, v8, 15 ; RV64I-NEXT: vand.vi v8, v8, 15
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV32D-LABEL: cttz_nxv1i8: ; RV32D-LABEL: cttz_nxv1i8:
; RV32D: # %bb.0: ; RV32D: # %bb.0:
; RV32D-NEXT: vsetvli a0, zero, e8, mf8, ta, mu ; RV32D-NEXT: vsetvli a0, zero, e8, mf8, ta, mu
; RV32D-NEXT: vmv.v.i v9, 0
; RV32D-NEXT: vmseq.vv v0, v9, v8
; RV32D-NEXT: vrsub.vi v9, v8, 0 ; RV32D-NEXT: vrsub.vi v9, v8, 0
; RV32D-NEXT: vand.vv v8, v8, v9 ; RV32D-NEXT: vand.vv v9, v8, v9
; RV32D-NEXT: vsetvli zero, zero, e32, mf2, ta, mu ; RV32D-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; RV32D-NEXT: vzext.vf4 v9, v8 ; RV32D-NEXT: vzext.vf4 v10, v9
; RV32D-NEXT: vfcvt.f.xu.v v8, v9 ; RV32D-NEXT: vfcvt.f.xu.v v9, v10
; RV32D-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; RV32D-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; RV32D-NEXT: vnsrl.wi v8, v8, 23 ; RV32D-NEXT: vnsrl.wi v9, v9, 23
; RV32D-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; RV32D-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; RV32D-NEXT: vncvt.x.x.w v8, v8 ; RV32D-NEXT: vncvt.x.x.w v9, v9
; RV32D-NEXT: li a0, 127 ; RV32D-NEXT: li a0, 127
; RV32D-NEXT: vsub.vx v8, v8, a0 ; RV32D-NEXT: vmseq.vi v0, v8, 0
; RV32D-NEXT: vsub.vx v8, v9, a0
; RV32D-NEXT: vmerge.vim v8, v8, 8, v0 ; RV32D-NEXT: vmerge.vim v8, v8, 8, v0
; RV32D-NEXT: ret ; RV32D-NEXT: ret
; ;
; RV64D-LABEL: cttz_nxv1i8: ; RV64D-LABEL: cttz_nxv1i8:
; RV64D: # %bb.0: ; RV64D: # %bb.0:
; RV64D-NEXT: vsetvli a0, zero, e8, mf8, ta, mu ; RV64D-NEXT: vsetvli a0, zero, e8, mf8, ta, mu
; RV64D-NEXT: vmv.v.i v9, 0
; RV64D-NEXT: vmseq.vv v0, v9, v8
; RV64D-NEXT: vrsub.vi v9, v8, 0 ; RV64D-NEXT: vrsub.vi v9, v8, 0
; RV64D-NEXT: vand.vv v8, v8, v9 ; RV64D-NEXT: vand.vv v9, v8, v9
; RV64D-NEXT: vsetvli zero, zero, e32, mf2, ta, mu ; RV64D-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; RV64D-NEXT: vzext.vf4 v9, v8 ; RV64D-NEXT: vzext.vf4 v10, v9
; RV64D-NEXT: vfcvt.f.xu.v v8, v9 ; RV64D-NEXT: vfcvt.f.xu.v v9, v10
; RV64D-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; RV64D-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; RV64D-NEXT: vnsrl.wi v8, v8, 23 ; RV64D-NEXT: vnsrl.wi v9, v9, 23
; RV64D-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; RV64D-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; RV64D-NEXT: vncvt.x.x.w v8, v8 ; RV64D-NEXT: vncvt.x.x.w v9, v9
; RV64D-NEXT: li a0, 127 ; RV64D-NEXT: li a0, 127
; RV64D-NEXT: vsub.vx v8, v8, a0 ; RV64D-NEXT: vmseq.vi v0, v8, 0
; RV64D-NEXT: vsub.vx v8, v9, a0
; RV64D-NEXT: vmerge.vim v8, v8, 8, v0 ; RV64D-NEXT: vmerge.vim v8, v8, 8, v0
; RV64D-NEXT: ret ; RV64D-NEXT: ret
%a = call <vscale x 1 x i8> @llvm.cttz.nxv1i8(<vscale x 1 x i8> %va, i1 false) %a = call <vscale x 1 x i8> @llvm.cttz.nxv1i8(<vscale x 1 x i8> %va, i1 false)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 1 x i8> @llvm.cttz.nxv1i8(<vscale x 1 x i8>, i1) declare <vscale x 1 x i8> @llvm.cttz.nxv1i8(<vscale x 1 x i8>, i1)
define <vscale x 2 x i8> @cttz_nxv2i8(<vscale x 2 x i8> %va) { define <vscale x 2 x i8> @cttz_nxv2i8(<vscale x 2 x i8> %va) {
Show All 37 Lines
; RV64I-NEXT: vsrl.vi v9, v8, 4 ; RV64I-NEXT: vsrl.vi v9, v8, 4
; RV64I-NEXT: vadd.vv v8, v8, v9 ; RV64I-NEXT: vadd.vv v8, v8, v9
; RV64I-NEXT: vand.vi v8, v8, 15 ; RV64I-NEXT: vand.vi v8, v8, 15
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV32D-LABEL: cttz_nxv2i8: ; RV32D-LABEL: cttz_nxv2i8:
; RV32D: # %bb.0: ; RV32D: # %bb.0:
; RV32D-NEXT: vsetvli a0, zero, e8, mf4, ta, mu ; RV32D-NEXT: vsetvli a0, zero, e8, mf4, ta, mu
; RV32D-NEXT: vmv.v.i v9, 0
; RV32D-NEXT: vmseq.vv v0, v9, v8
; RV32D-NEXT: vrsub.vi v9, v8, 0 ; RV32D-NEXT: vrsub.vi v9, v8, 0
; RV32D-NEXT: vand.vv v8, v8, v9 ; RV32D-NEXT: vand.vv v9, v8, v9
; RV32D-NEXT: vsetvli zero, zero, e32, m1, ta, mu ; RV32D-NEXT: vsetvli zero, zero, e32, m1, ta, mu
; RV32D-NEXT: vzext.vf4 v9, v8 ; RV32D-NEXT: vzext.vf4 v10, v9
; RV32D-NEXT: vfcvt.f.xu.v v8, v9 ; RV32D-NEXT: vfcvt.f.xu.v v9, v10
; RV32D-NEXT: vsetvli zero, zero, e16, mf2, ta, mu ; RV32D-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
; RV32D-NEXT: vnsrl.wi v8, v8, 23 ; RV32D-NEXT: vnsrl.wi v9, v9, 23
; RV32D-NEXT: vsetvli zero, zero, e8, mf4, ta, mu ; RV32D-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
; RV32D-NEXT: vncvt.x.x.w v8, v8 ; RV32D-NEXT: vncvt.x.x.w v9, v9
; RV32D-NEXT: li a0, 127 ; RV32D-NEXT: li a0, 127
; RV32D-NEXT: vsub.vx v8, v8, a0 ; RV32D-NEXT: vmseq.vi v0, v8, 0
; RV32D-NEXT: vsub.vx v8, v9, a0
; RV32D-NEXT: vmerge.vim v8, v8, 8, v0 ; RV32D-NEXT: vmerge.vim v8, v8, 8, v0
; RV32D-NEXT: ret ; RV32D-NEXT: ret
; ;
; RV64D-LABEL: cttz_nxv2i8: ; RV64D-LABEL: cttz_nxv2i8:
; RV64D: # %bb.0: ; RV64D: # %bb.0:
; RV64D-NEXT: vsetvli a0, zero, e8, mf4, ta, mu ; RV64D-NEXT: vsetvli a0, zero, e8, mf4, ta, mu
; RV64D-NEXT: vmv.v.i v9, 0
; RV64D-NEXT: vmseq.vv v0, v9, v8
; RV64D-NEXT: vrsub.vi v9, v8, 0 ; RV64D-NEXT: vrsub.vi v9, v8, 0
; RV64D-NEXT: vand.vv v8, v8, v9 ; RV64D-NEXT: vand.vv v9, v8, v9
; RV64D-NEXT: vsetvli zero, zero, e32, m1, ta, mu ; RV64D-NEXT: vsetvli zero, zero, e32, m1, ta, mu
; RV64D-NEXT: vzext.vf4 v9, v8 ; RV64D-NEXT: vzext.vf4 v10, v9
; RV64D-NEXT: vfcvt.f.xu.v v8, v9 ; RV64D-NEXT: vfcvt.f.xu.v v9, v10
; RV64D-NEXT: vsetvli zero, zero, e16, mf2, ta, mu ; RV64D-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
; RV64D-NEXT: vnsrl.wi v8, v8, 23 ; RV64D-NEXT: vnsrl.wi v9, v9, 23
; RV64D-NEXT: vsetvli zero, zero, e8, mf4, ta, mu ; RV64D-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
; RV64D-NEXT: vncvt.x.x.w v8, v8 ; RV64D-NEXT: vncvt.x.x.w v9, v9
; RV64D-NEXT: li a0, 127 ; RV64D-NEXT: li a0, 127
; RV64D-NEXT: vsub.vx v8, v8, a0 ; RV64D-NEXT: vmseq.vi v0, v8, 0
; RV64D-NEXT: vsub.vx v8, v9, a0
; RV64D-NEXT: vmerge.vim v8, v8, 8, v0 ; RV64D-NEXT: vmerge.vim v8, v8, 8, v0
; RV64D-NEXT: ret ; RV64D-NEXT: ret
%a = call <vscale x 2 x i8> @llvm.cttz.nxv2i8(<vscale x 2 x i8> %va, i1 false) %a = call <vscale x 2 x i8> @llvm.cttz.nxv2i8(<vscale x 2 x i8> %va, i1 false)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
declare <vscale x 2 x i8> @llvm.cttz.nxv2i8(<vscale x 2 x i8>, i1) declare <vscale x 2 x i8> @llvm.cttz.nxv2i8(<vscale x 2 x i8>, i1)
define <vscale x 4 x i8> @cttz_nxv4i8(<vscale x 4 x i8> %va) { define <vscale x 4 x i8> @cttz_nxv4i8(<vscale x 4 x i8> %va) {
Show All 37 Lines
; RV64I-NEXT: vsrl.vi v9, v8, 4 ; RV64I-NEXT: vsrl.vi v9, v8, 4
; RV64I-NEXT: vadd.vv v8, v8, v9 ; RV64I-NEXT: vadd.vv v8, v8, v9
; RV64I-NEXT: vand.vi v8, v8, 15 ; RV64I-NEXT: vand.vi v8, v8, 15
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV32D-LABEL: cttz_nxv4i8: ; RV32D-LABEL: cttz_nxv4i8:
; RV32D: # %bb.0: ; RV32D: # %bb.0:
; RV32D-NEXT: vsetvli a0, zero, e8, mf2, ta, mu ; RV32D-NEXT: vsetvli a0, zero, e8, mf2, ta, mu
; RV32D-NEXT: vmv.v.i v9, 0
; RV32D-NEXT: vmseq.vv v0, v9, v8
; RV32D-NEXT: vrsub.vi v9, v8, 0 ; RV32D-NEXT: vrsub.vi v9, v8, 0
; RV32D-NEXT: vand.vv v8, v8, v9 ; RV32D-NEXT: vand.vv v9, v8, v9
; RV32D-NEXT: vsetvli zero, zero, e32, m2, ta, mu ; RV32D-NEXT: vsetvli zero, zero, e32, m2, ta, mu
; RV32D-NEXT: vzext.vf4 v10, v8 ; RV32D-NEXT: vzext.vf4 v10, v9
; RV32D-NEXT: vfcvt.f.xu.v v8, v10 ; RV32D-NEXT: vfcvt.f.xu.v v10, v10
; RV32D-NEXT: vsetvli zero, zero, e16, m1, ta, mu ; RV32D-NEXT: vsetvli zero, zero, e16, m1, ta, mu
; RV32D-NEXT: vnsrl.wi v10, v8, 23 ; RV32D-NEXT: vnsrl.wi v9, v10, 23
; RV32D-NEXT: vsetvli zero, zero, e8, mf2, ta, mu ; RV32D-NEXT: vsetvli zero, zero, e8, mf2, ta, mu
; RV32D-NEXT: vncvt.x.x.w v8, v10 ; RV32D-NEXT: vncvt.x.x.w v9, v9
; RV32D-NEXT: li a0, 127 ; RV32D-NEXT: li a0, 127
; RV32D-NEXT: vsub.vx v8, v8, a0 ; RV32D-NEXT: vmseq.vi v0, v8, 0
; RV32D-NEXT: vsub.vx v8, v9, a0
; RV32D-NEXT: vmerge.vim v8, v8, 8, v0 ; RV32D-NEXT: vmerge.vim v8, v8, 8, v0
; RV32D-NEXT: ret ; RV32D-NEXT: ret
; ;
; RV64D-LABEL: cttz_nxv4i8: ; RV64D-LABEL: cttz_nxv4i8:
; RV64D: # %bb.0: ; RV64D: # %bb.0:
; RV64D-NEXT: vsetvli a0, zero, e8, mf2, ta, mu ; RV64D-NEXT: vsetvli a0, zero, e8, mf2, ta, mu
; RV64D-NEXT: vmv.v.i v9, 0
; RV64D-NEXT: vmseq.vv v0, v9, v8
; RV64D-NEXT: vrsub.vi v9, v8, 0 ; RV64D-NEXT: vrsub.vi v9, v8, 0
; RV64D-NEXT: vand.vv v8, v8, v9 ; RV64D-NEXT: vand.vv v9, v8, v9
; RV64D-NEXT: vsetvli zero, zero, e32, m2, ta, mu ; RV64D-NEXT: vsetvli zero, zero, e32, m2, ta, mu
; RV64D-NEXT: vzext.vf4 v10, v8 ; RV64D-NEXT: vzext.vf4 v10, v9
; RV64D-NEXT: vfcvt.f.xu.v v8, v10 ; RV64D-NEXT: vfcvt.f.xu.v v10, v10
; RV64D-NEXT: vsetvli zero, zero, e16, m1, ta, mu ; RV64D-NEXT: vsetvli zero, zero, e16, m1, ta, mu
; RV64D-NEXT: vnsrl.wi v10, v8, 23 ; RV64D-NEXT: vnsrl.wi v9, v10, 23
; RV64D-NEXT: vsetvli zero, zero, e8, mf2, ta, mu ; RV64D-NEXT: vsetvli zero, zero, e8, mf2, ta, mu
; RV64D-NEXT: vncvt.x.x.w v8, v10 ; RV64D-NEXT: vncvt.x.x.w v9, v9
; RV64D-NEXT: li a0, 127 ; RV64D-NEXT: li a0, 127
; RV64D-NEXT: vsub.vx v8, v8, a0 ; RV64D-NEXT: vmseq.vi v0, v8, 0
; RV64D-NEXT: vsub.vx v8, v9, a0
; RV64D-NEXT: vmerge.vim v8, v8, 8, v0 ; RV64D-NEXT: vmerge.vim v8, v8, 8, v0
; RV64D-NEXT: ret ; RV64D-NEXT: ret
%a = call <vscale x 4 x i8> @llvm.cttz.nxv4i8(<vscale x 4 x i8> %va, i1 false) %a = call <vscale x 4 x i8> @llvm.cttz.nxv4i8(<vscale x 4 x i8> %va, i1 false)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
declare <vscale x 4 x i8> @llvm.cttz.nxv4i8(<vscale x 4 x i8>, i1) declare <vscale x 4 x i8> @llvm.cttz.nxv4i8(<vscale x 4 x i8>, i1)
define <vscale x 8 x i8> @cttz_nxv8i8(<vscale x 8 x i8> %va) { define <vscale x 8 x i8> @cttz_nxv8i8(<vscale x 8 x i8> %va) {
Show All 37 Lines
; RV64I-NEXT: vsrl.vi v9, v8, 4 ; RV64I-NEXT: vsrl.vi v9, v8, 4
; RV64I-NEXT: vadd.vv v8, v8, v9 ; RV64I-NEXT: vadd.vv v8, v8, v9
; RV64I-NEXT: vand.vi v8, v8, 15 ; RV64I-NEXT: vand.vi v8, v8, 15
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV32D-LABEL: cttz_nxv8i8: ; RV32D-LABEL: cttz_nxv8i8:
; RV32D: # %bb.0: ; RV32D: # %bb.0:
; RV32D-NEXT: vsetvli a0, zero, e8, m1, ta, mu ; RV32D-NEXT: vsetvli a0, zero, e8, m1, ta, mu
; RV32D-NEXT: vmv.v.i v9, 0
; RV32D-NEXT: vmseq.vv v0, v9, v8
; RV32D-NEXT: vrsub.vi v9, v8, 0 ; RV32D-NEXT: vrsub.vi v9, v8, 0
; RV32D-NEXT: vand.vv v8, v8, v9 ; RV32D-NEXT: vand.vv v9, v8, v9
; RV32D-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; RV32D-NEXT: vsetvli zero, zero, e32, m4, ta, mu
; RV32D-NEXT: vzext.vf4 v12, v8 ; RV32D-NEXT: vzext.vf4 v12, v9
; RV32D-NEXT: vfcvt.f.xu.v v8, v12 ; RV32D-NEXT: vfcvt.f.xu.v v12, v12
; RV32D-NEXT: vsetvli zero, zero, e16, m2, ta, mu ; RV32D-NEXT: vsetvli zero, zero, e16, m2, ta, mu
; RV32D-NEXT: vnsrl.wi v12, v8, 23 ; RV32D-NEXT: vnsrl.wi v10, v12, 23
; RV32D-NEXT: vsetvli zero, zero, e8, m1, ta, mu ; RV32D-NEXT: vsetvli zero, zero, e8, m1, ta, mu
; RV32D-NEXT: vncvt.x.x.w v8, v12 ; RV32D-NEXT: vncvt.x.x.w v9, v10
; RV32D-NEXT: li a0, 127 ; RV32D-NEXT: li a0, 127
; RV32D-NEXT: vsub.vx v8, v8, a0 ; RV32D-NEXT: vmseq.vi v0, v8, 0
; RV32D-NEXT: vsub.vx v8, v9, a0
; RV32D-NEXT: vmerge.vim v8, v8, 8, v0 ; RV32D-NEXT: vmerge.vim v8, v8, 8, v0
; RV32D-NEXT: ret ; RV32D-NEXT: ret
; ;
; RV64D-LABEL: cttz_nxv8i8: ; RV64D-LABEL: cttz_nxv8i8:
; RV64D: # %bb.0: ; RV64D: # %bb.0:
; RV64D-NEXT: vsetvli a0, zero, e8, m1, ta, mu ; RV64D-NEXT: vsetvli a0, zero, e8, m1, ta, mu
; RV64D-NEXT: vmv.v.i v9, 0
; RV64D-NEXT: vmseq.vv v0, v9, v8
; RV64D-NEXT: vrsub.vi v9, v8, 0 ; RV64D-NEXT: vrsub.vi v9, v8, 0
; RV64D-NEXT: vand.vv v8, v8, v9 ; RV64D-NEXT: vand.vv v9, v8, v9
; RV64D-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; RV64D-NEXT: vsetvli zero, zero, e32, m4, ta, mu
; RV64D-NEXT: vzext.vf4 v12, v8 ; RV64D-NEXT: vzext.vf4 v12, v9
; RV64D-NEXT: vfcvt.f.xu.v v8, v12 ; RV64D-NEXT: vfcvt.f.xu.v v12, v12
; RV64D-NEXT: vsetvli zero, zero, e16, m2, ta, mu ; RV64D-NEXT: vsetvli zero, zero, e16, m2, ta, mu
; RV64D-NEXT: vnsrl.wi v12, v8, 23 ; RV64D-NEXT: vnsrl.wi v10, v12, 23
; RV64D-NEXT: vsetvli zero, zero, e8, m1, ta, mu ; RV64D-NEXT: vsetvli zero, zero, e8, m1, ta, mu
; RV64D-NEXT: vncvt.x.x.w v8, v12 ; RV64D-NEXT: vncvt.x.x.w v9, v10
; RV64D-NEXT: li a0, 127 ; RV64D-NEXT: li a0, 127
; RV64D-NEXT: vsub.vx v8, v8, a0 ; RV64D-NEXT: vmseq.vi v0, v8, 0
; RV64D-NEXT: vsub.vx v8, v9, a0
; RV64D-NEXT: vmerge.vim v8, v8, 8, v0 ; RV64D-NEXT: vmerge.vim v8, v8, 8, v0
; RV64D-NEXT: ret ; RV64D-NEXT: ret
%a = call <vscale x 8 x i8> @llvm.cttz.nxv8i8(<vscale x 8 x i8> %va, i1 false) %a = call <vscale x 8 x i8> @llvm.cttz.nxv8i8(<vscale x 8 x i8> %va, i1 false)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.cttz.nxv8i8(<vscale x 8 x i8>, i1) declare <vscale x 8 x i8> @llvm.cttz.nxv8i8(<vscale x 8 x i8>, i1)
define <vscale x 16 x i8> @cttz_nxv16i8(<vscale x 16 x i8> %va) { define <vscale x 16 x i8> @cttz_nxv16i8(<vscale x 16 x i8> %va) {
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; RV64I-NEXT: vsrl.vi v10, v8, 4 ; RV64I-NEXT: vsrl.vi v10, v8, 4
; RV64I-NEXT: vadd.vv v8, v8, v10 ; RV64I-NEXT: vadd.vv v8, v8, v10
; RV64I-NEXT: vand.vi v8, v8, 15 ; RV64I-NEXT: vand.vi v8, v8, 15
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV32D-LABEL: cttz_nxv16i8: ; RV32D-LABEL: cttz_nxv16i8:
; RV32D: # %bb.0: ; RV32D: # %bb.0:
; RV32D-NEXT: vsetvli a0, zero, e8, m2, ta, mu ; RV32D-NEXT: vsetvli a0, zero, e8, m2, ta, mu
; RV32D-NEXT: vmv.v.i v10, 0
; RV32D-NEXT: vmseq.vv v0, v10, v8
; RV32D-NEXT: vrsub.vi v10, v8, 0 ; RV32D-NEXT: vrsub.vi v10, v8, 0
; RV32D-NEXT: vand.vv v8, v8, v10 ; RV32D-NEXT: vand.vv v10, v8, v10
; RV32D-NEXT: vsetvli zero, zero, e32, m8, ta, mu ; RV32D-NEXT: vsetvli zero, zero, e32, m8, ta, mu
; RV32D-NEXT: vzext.vf4 v16, v8 ; RV32D-NEXT: vzext.vf4 v16, v10
; RV32D-NEXT: vfcvt.f.xu.v v8, v16 ; RV32D-NEXT: vfcvt.f.xu.v v16, v16
; RV32D-NEXT: vsetvli zero, zero, e16, m4, ta, mu ; RV32D-NEXT: vsetvli zero, zero, e16, m4, ta, mu
; RV32D-NEXT: vnsrl.wi v16, v8, 23 ; RV32D-NEXT: vnsrl.wi v12, v16, 23
; RV32D-NEXT: vsetvli zero, zero, e8, m2, ta, mu ; RV32D-NEXT: vsetvli zero, zero, e8, m2, ta, mu
; RV32D-NEXT: vncvt.x.x.w v8, v16 ; RV32D-NEXT: vncvt.x.x.w v10, v12
; RV32D-NEXT: li a0, 127 ; RV32D-NEXT: li a0, 127
; RV32D-NEXT: vsub.vx v8, v8, a0 ; RV32D-NEXT: vmseq.vi v0, v8, 0
; RV32D-NEXT: vsub.vx v8, v10, a0
; RV32D-NEXT: vmerge.vim v8, v8, 8, v0 ; RV32D-NEXT: vmerge.vim v8, v8, 8, v0
; RV32D-NEXT: ret ; RV32D-NEXT: ret
; ;
; RV64D-LABEL: cttz_nxv16i8: ; RV64D-LABEL: cttz_nxv16i8:
; RV64D: # %bb.0: ; RV64D: # %bb.0:
; RV64D-NEXT: vsetvli a0, zero, e8, m2, ta, mu ; RV64D-NEXT: vsetvli a0, zero, e8, m2, ta, mu
; RV64D-NEXT: vmv.v.i v10, 0
; RV64D-NEXT: vmseq.vv v0, v10, v8
; RV64D-NEXT: vrsub.vi v10, v8, 0 ; RV64D-NEXT: vrsub.vi v10, v8, 0
; RV64D-NEXT: vand.vv v8, v8, v10 ; RV64D-NEXT: vand.vv v10, v8, v10
; RV64D-NEXT: vsetvli zero, zero, e32, m8, ta, mu ; RV64D-NEXT: vsetvli zero, zero, e32, m8, ta, mu
; RV64D-NEXT: vzext.vf4 v16, v8 ; RV64D-NEXT: vzext.vf4 v16, v10
; RV64D-NEXT: vfcvt.f.xu.v v8, v16 ; RV64D-NEXT: vfcvt.f.xu.v v16, v16
; RV64D-NEXT: vsetvli zero, zero, e16, m4, ta, mu ; RV64D-NEXT: vsetvli zero, zero, e16, m4, ta, mu
; RV64D-NEXT: vnsrl.wi v16, v8, 23 ; RV64D-NEXT: vnsrl.wi v12, v16, 23
; RV64D-NEXT: vsetvli zero, zero, e8, m2, ta, mu ; RV64D-NEXT: vsetvli zero, zero, e8, m2, ta, mu
; RV64D-NEXT: vncvt.x.x.w v8, v16 ; RV64D-NEXT: vncvt.x.x.w v10, v12
; RV64D-NEXT: li a0, 127 ; RV64D-NEXT: li a0, 127
; RV64D-NEXT: vsub.vx v8, v8, a0 ; RV64D-NEXT: vmseq.vi v0, v8, 0
; RV64D-NEXT: vsub.vx v8, v10, a0
; RV64D-NEXT: vmerge.vim v8, v8, 8, v0 ; RV64D-NEXT: vmerge.vim v8, v8, 8, v0
; RV64D-NEXT: ret ; RV64D-NEXT: ret
%a = call <vscale x 16 x i8> @llvm.cttz.nxv16i8(<vscale x 16 x i8> %va, i1 false) %a = call <vscale x 16 x i8> @llvm.cttz.nxv16i8(<vscale x 16 x i8> %va, i1 false)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
declare <vscale x 16 x i8> @llvm.cttz.nxv16i8(<vscale x 16 x i8>, i1) declare <vscale x 16 x i8> @llvm.cttz.nxv16i8(<vscale x 16 x i8>, i1)
define <vscale x 32 x i8> @cttz_nxv32i8(<vscale x 32 x i8> %va) { define <vscale x 32 x i8> @cttz_nxv32i8(<vscale x 32 x i8> %va) {
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; RV64I-NEXT: li a0, 257 ; RV64I-NEXT: li a0, 257
; RV64I-NEXT: vmul.vx v8, v8, a0 ; RV64I-NEXT: vmul.vx v8, v8, a0
; RV64I-NEXT: vsrl.vi v8, v8, 8 ; RV64I-NEXT: vsrl.vi v8, v8, 8
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV32D-LABEL: cttz_nxv1i16: ; RV32D-LABEL: cttz_nxv1i16:
; RV32D: # %bb.0: ; RV32D: # %bb.0:
; RV32D-NEXT: vsetvli a0, zero, e16, mf4, ta, mu ; RV32D-NEXT: vsetvli a0, zero, e16, mf4, ta, mu
; RV32D-NEXT: vmv.v.i v9, 0
; RV32D-NEXT: vmseq.vv v0, v9, v8
; RV32D-NEXT: vrsub.vi v9, v8, 0 ; RV32D-NEXT: vrsub.vi v9, v8, 0
; RV32D-NEXT: vand.vv v8, v8, v9 ; RV32D-NEXT: vand.vv v9, v8, v9
; RV32D-NEXT: vfwcvt.f.xu.v v9, v8 ; RV32D-NEXT: vfwcvt.f.xu.v v10, v9
; RV32D-NEXT: vnsrl.wi v8, v9, 23 ; RV32D-NEXT: vnsrl.wi v9, v10, 23
; RV32D-NEXT: li a0, 127 ; RV32D-NEXT: li a0, 127
; RV32D-NEXT: vsub.vx v8, v8, a0 ; RV32D-NEXT: vsub.vx v9, v9, a0
; RV32D-NEXT: vmseq.vi v0, v8, 0
; RV32D-NEXT: li a0, 16 ; RV32D-NEXT: li a0, 16
; RV32D-NEXT: vmerge.vxm v8, v8, a0, v0 ; RV32D-NEXT: vmerge.vxm v8, v9, a0, v0
; RV32D-NEXT: ret ; RV32D-NEXT: ret
; ;
; RV64D-LABEL: cttz_nxv1i16: ; RV64D-LABEL: cttz_nxv1i16:
; RV64D: # %bb.0: ; RV64D: # %bb.0:
; RV64D-NEXT: vsetvli a0, zero, e16, mf4, ta, mu ; RV64D-NEXT: vsetvli a0, zero, e16, mf4, ta, mu
; RV64D-NEXT: vmv.v.i v9, 0
; RV64D-NEXT: vmseq.vv v0, v9, v8
; RV64D-NEXT: vrsub.vi v9, v8, 0 ; RV64D-NEXT: vrsub.vi v9, v8, 0
; RV64D-NEXT: vand.vv v8, v8, v9 ; RV64D-NEXT: vand.vv v9, v8, v9
; RV64D-NEXT: vfwcvt.f.xu.v v9, v8 ; RV64D-NEXT: vfwcvt.f.xu.v v10, v9
; RV64D-NEXT: vnsrl.wi v8, v9, 23 ; RV64D-NEXT: vnsrl.wi v9, v10, 23
; RV64D-NEXT: li a0, 127 ; RV64D-NEXT: li a0, 127
; RV64D-NEXT: vsub.vx v8, v8, a0 ; RV64D-NEXT: vsub.vx v9, v9, a0
; RV64D-NEXT: vmseq.vi v0, v8, 0
; RV64D-NEXT: li a0, 16 ; RV64D-NEXT: li a0, 16
; RV64D-NEXT: vmerge.vxm v8, v8, a0, v0 ; RV64D-NEXT: vmerge.vxm v8, v9, a0, v0
; RV64D-NEXT: ret ; RV64D-NEXT: ret
%a = call <vscale x 1 x i16> @llvm.cttz.nxv1i16(<vscale x 1 x i16> %va, i1 false) %a = call <vscale x 1 x i16> @llvm.cttz.nxv1i16(<vscale x 1 x i16> %va, i1 false)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 1 x i16> @llvm.cttz.nxv1i16(<vscale x 1 x i16>, i1) declare <vscale x 1 x i16> @llvm.cttz.nxv1i16(<vscale x 1 x i16>, i1)
define <vscale x 2 x i16> @cttz_nxv2i16(<vscale x 2 x i16> %va) { define <vscale x 2 x i16> @cttz_nxv2i16(<vscale x 2 x i16> %va) {
; RV32I-LABEL: cttz_nxv2i16: ; RV32I-LABEL: cttz_nxv2i16:
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; RV64I-NEXT: li a0, 257 ; RV64I-NEXT: li a0, 257
; RV64I-NEXT: vmul.vx v8, v8, a0 ; RV64I-NEXT: vmul.vx v8, v8, a0
; RV64I-NEXT: vsrl.vi v8, v8, 8 ; RV64I-NEXT: vsrl.vi v8, v8, 8
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV32D-LABEL: cttz_nxv2i16: ; RV32D-LABEL: cttz_nxv2i16:
; RV32D: # %bb.0: ; RV32D: # %bb.0:
; RV32D-NEXT: vsetvli a0, zero, e16, mf2, ta, mu ; RV32D-NEXT: vsetvli a0, zero, e16, mf2, ta, mu
; RV32D-NEXT: vmv.v.i v9, 0
; RV32D-NEXT: vmseq.vv v0, v9, v8
; RV32D-NEXT: vrsub.vi v9, v8, 0 ; RV32D-NEXT: vrsub.vi v9, v8, 0
; RV32D-NEXT: vand.vv v8, v8, v9 ; RV32D-NEXT: vand.vv v9, v8, v9
; RV32D-NEXT: vfwcvt.f.xu.v v9, v8 ; RV32D-NEXT: vfwcvt.f.xu.v v10, v9
; RV32D-NEXT: vnsrl.wi v8, v9, 23 ; RV32D-NEXT: vnsrl.wi v9, v10, 23
; RV32D-NEXT: li a0, 127 ; RV32D-NEXT: li a0, 127
; RV32D-NEXT: vsub.vx v8, v8, a0 ; RV32D-NEXT: vsub.vx v9, v9, a0
; RV32D-NEXT: vmseq.vi v0, v8, 0
; RV32D-NEXT: li a0, 16 ; RV32D-NEXT: li a0, 16
; RV32D-NEXT: vmerge.vxm v8, v8, a0, v0 ; RV32D-NEXT: vmerge.vxm v8, v9, a0, v0
; RV32D-NEXT: ret ; RV32D-NEXT: ret
; ;
; RV64D-LABEL: cttz_nxv2i16: ; RV64D-LABEL: cttz_nxv2i16:
; RV64D: # %bb.0: ; RV64D: # %bb.0:
; RV64D-NEXT: vsetvli a0, zero, e16, mf2, ta, mu ; RV64D-NEXT: vsetvli a0, zero, e16, mf2, ta, mu
; RV64D-NEXT: vmv.v.i v9, 0
; RV64D-NEXT: vmseq.vv v0, v9, v8
; RV64D-NEXT: vrsub.vi v9, v8, 0 ; RV64D-NEXT: vrsub.vi v9, v8, 0
; RV64D-NEXT: vand.vv v8, v8, v9 ; RV64D-NEXT: vand.vv v9, v8, v9
; RV64D-NEXT: vfwcvt.f.xu.v v9, v8 ; RV64D-NEXT: vfwcvt.f.xu.v v10, v9
; RV64D-NEXT: vnsrl.wi v8, v9, 23 ; RV64D-NEXT: vnsrl.wi v9, v10, 23
; RV64D-NEXT: li a0, 127 ; RV64D-NEXT: li a0, 127
; RV64D-NEXT: vsub.vx v8, v8, a0 ; RV64D-NEXT: vsub.vx v9, v9, a0
; RV64D-NEXT: vmseq.vi v0, v8, 0
; RV64D-NEXT: li a0, 16 ; RV64D-NEXT: li a0, 16
; RV64D-NEXT: vmerge.vxm v8, v8, a0, v0 ; RV64D-NEXT: vmerge.vxm v8, v9, a0, v0
; RV64D-NEXT: ret ; RV64D-NEXT: ret
%a = call <vscale x 2 x i16> @llvm.cttz.nxv2i16(<vscale x 2 x i16> %va, i1 false) %a = call <vscale x 2 x i16> @llvm.cttz.nxv2i16(<vscale x 2 x i16> %va, i1 false)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.cttz.nxv2i16(<vscale x 2 x i16>, i1) declare <vscale x 2 x i16> @llvm.cttz.nxv2i16(<vscale x 2 x i16>, i1)
define <vscale x 4 x i16> @cttz_nxv4i16(<vscale x 4 x i16> %va) { define <vscale x 4 x i16> @cttz_nxv4i16(<vscale x 4 x i16> %va) {
; RV32I-LABEL: cttz_nxv4i16: ; RV32I-LABEL: cttz_nxv4i16:
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; RV64I-NEXT: li a0, 257 ; RV64I-NEXT: li a0, 257
; RV64I-NEXT: vmul.vx v8, v8, a0 ; RV64I-NEXT: vmul.vx v8, v8, a0
; RV64I-NEXT: vsrl.vi v8, v8, 8 ; RV64I-NEXT: vsrl.vi v8, v8, 8
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV32D-LABEL: cttz_nxv4i16: ; RV32D-LABEL: cttz_nxv4i16:
; RV32D: # %bb.0: ; RV32D: # %bb.0:
; RV32D-NEXT: vsetvli a0, zero, e16, m1, ta, mu ; RV32D-NEXT: vsetvli a0, zero, e16, m1, ta, mu
; RV32D-NEXT: vmv.v.i v9, 0
; RV32D-NEXT: vmseq.vv v0, v9, v8
; RV32D-NEXT: vrsub.vi v9, v8, 0 ; RV32D-NEXT: vrsub.vi v9, v8, 0
; RV32D-NEXT: vand.vv v8, v8, v9 ; RV32D-NEXT: vand.vv v9, v8, v9
; RV32D-NEXT: vfwcvt.f.xu.v v10, v8 ; RV32D-NEXT: vfwcvt.f.xu.v v10, v9
; RV32D-NEXT: vnsrl.wi v8, v10, 23 ; RV32D-NEXT: vnsrl.wi v9, v10, 23
; RV32D-NEXT: li a0, 127 ; RV32D-NEXT: li a0, 127
; RV32D-NEXT: vsub.vx v8, v8, a0 ; RV32D-NEXT: vsub.vx v9, v9, a0
; RV32D-NEXT: vmseq.vi v0, v8, 0
; RV32D-NEXT: li a0, 16 ; RV32D-NEXT: li a0, 16
; RV32D-NEXT: vmerge.vxm v8, v8, a0, v0 ; RV32D-NEXT: vmerge.vxm v8, v9, a0, v0
; RV32D-NEXT: ret ; RV32D-NEXT: ret
; ;
; RV64D-LABEL: cttz_nxv4i16: ; RV64D-LABEL: cttz_nxv4i16:
; RV64D: # %bb.0: ; RV64D: # %bb.0:
; RV64D-NEXT: vsetvli a0, zero, e16, m1, ta, mu ; RV64D-NEXT: vsetvli a0, zero, e16, m1, ta, mu
; RV64D-NEXT: vmv.v.i v9, 0
; RV64D-NEXT: vmseq.vv v0, v9, v8
; RV64D-NEXT: vrsub.vi v9, v8, 0 ; RV64D-NEXT: vrsub.vi v9, v8, 0
; RV64D-NEXT: vand.vv v8, v8, v9 ; RV64D-NEXT: vand.vv v9, v8, v9
; RV64D-NEXT: vfwcvt.f.xu.v v10, v8 ; RV64D-NEXT: vfwcvt.f.xu.v v10, v9
; RV64D-NEXT: vnsrl.wi v8, v10, 23 ; RV64D-NEXT: vnsrl.wi v9, v10, 23
; RV64D-NEXT: li a0, 127 ; RV64D-NEXT: li a0, 127
; RV64D-NEXT: vsub.vx v8, v8, a0 ; RV64D-NEXT: vsub.vx v9, v9, a0
; RV64D-NEXT: vmseq.vi v0, v8, 0
; RV64D-NEXT: li a0, 16 ; RV64D-NEXT: li a0, 16
; RV64D-NEXT: vmerge.vxm v8, v8, a0, v0 ; RV64D-NEXT: vmerge.vxm v8, v9, a0, v0
; RV64D-NEXT: ret ; RV64D-NEXT: ret
%a = call <vscale x 4 x i16> @llvm.cttz.nxv4i16(<vscale x 4 x i16> %va, i1 false) %a = call <vscale x 4 x i16> @llvm.cttz.nxv4i16(<vscale x 4 x i16> %va, i1 false)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.cttz.nxv4i16(<vscale x 4 x i16>, i1) declare <vscale x 4 x i16> @llvm.cttz.nxv4i16(<vscale x 4 x i16>, i1)
define <vscale x 8 x i16> @cttz_nxv8i16(<vscale x 8 x i16> %va) { define <vscale x 8 x i16> @cttz_nxv8i16(<vscale x 8 x i16> %va) {
; RV32I-LABEL: cttz_nxv8i16: ; RV32I-LABEL: cttz_nxv8i16:
▲ Show 20 Lines • Show All 50 Lines • ▼ Show 20 Lines
; RV64I-NEXT: li a0, 257 ; RV64I-NEXT: li a0, 257
; RV64I-NEXT: vmul.vx v8, v8, a0 ; RV64I-NEXT: vmul.vx v8, v8, a0
; RV64I-NEXT: vsrl.vi v8, v8, 8 ; RV64I-NEXT: vsrl.vi v8, v8, 8
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV32D-LABEL: cttz_nxv8i16: ; RV32D-LABEL: cttz_nxv8i16:
; RV32D: # %bb.0: ; RV32D: # %bb.0:
; RV32D-NEXT: vsetvli a0, zero, e16, m2, ta, mu ; RV32D-NEXT: vsetvli a0, zero, e16, m2, ta, mu
; RV32D-NEXT: vmv.v.i v10, 0
; RV32D-NEXT: vmseq.vv v0, v10, v8
; RV32D-NEXT: vrsub.vi v10, v8, 0 ; RV32D-NEXT: vrsub.vi v10, v8, 0
; RV32D-NEXT: vand.vv v8, v8, v10 ; RV32D-NEXT: vand.vv v10, v8, v10
; RV32D-NEXT: vfwcvt.f.xu.v v12, v8 ; RV32D-NEXT: vfwcvt.f.xu.v v12, v10
; RV32D-NEXT: vnsrl.wi v8, v12, 23 ; RV32D-NEXT: vnsrl.wi v10, v12, 23
; RV32D-NEXT: li a0, 127 ; RV32D-NEXT: li a0, 127
; RV32D-NEXT: vsub.vx v8, v8, a0 ; RV32D-NEXT: vsub.vx v10, v10, a0
; RV32D-NEXT: vmseq.vi v0, v8, 0
; RV32D-NEXT: li a0, 16 ; RV32D-NEXT: li a0, 16
; RV32D-NEXT: vmerge.vxm v8, v8, a0, v0 ; RV32D-NEXT: vmerge.vxm v8, v10, a0, v0
; RV32D-NEXT: ret ; RV32D-NEXT: ret
; ;
; RV64D-LABEL: cttz_nxv8i16: ; RV64D-LABEL: cttz_nxv8i16:
; RV64D: # %bb.0: ; RV64D: # %bb.0:
; RV64D-NEXT: vsetvli a0, zero, e16, m2, ta, mu ; RV64D-NEXT: vsetvli a0, zero, e16, m2, ta, mu
; RV64D-NEXT: vmv.v.i v10, 0
; RV64D-NEXT: vmseq.vv v0, v10, v8
; RV64D-NEXT: vrsub.vi v10, v8, 0 ; RV64D-NEXT: vrsub.vi v10, v8, 0
; RV64D-NEXT: vand.vv v8, v8, v10 ; RV64D-NEXT: vand.vv v10, v8, v10
; RV64D-NEXT: vfwcvt.f.xu.v v12, v8 ; RV64D-NEXT: vfwcvt.f.xu.v v12, v10
; RV64D-NEXT: vnsrl.wi v8, v12, 23 ; RV64D-NEXT: vnsrl.wi v10, v12, 23
; RV64D-NEXT: li a0, 127 ; RV64D-NEXT: li a0, 127
; RV64D-NEXT: vsub.vx v8, v8, a0 ; RV64D-NEXT: vsub.vx v10, v10, a0
; RV64D-NEXT: vmseq.vi v0, v8, 0
; RV64D-NEXT: li a0, 16 ; RV64D-NEXT: li a0, 16
; RV64D-NEXT: vmerge.vxm v8, v8, a0, v0 ; RV64D-NEXT: vmerge.vxm v8, v10, a0, v0
; RV64D-NEXT: ret ; RV64D-NEXT: ret
%a = call <vscale x 8 x i16> @llvm.cttz.nxv8i16(<vscale x 8 x i16> %va, i1 false) %a = call <vscale x 8 x i16> @llvm.cttz.nxv8i16(<vscale x 8 x i16> %va, i1 false)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.cttz.nxv8i16(<vscale x 8 x i16>, i1) declare <vscale x 8 x i16> @llvm.cttz.nxv8i16(<vscale x 8 x i16>, i1)
define <vscale x 16 x i16> @cttz_nxv16i16(<vscale x 16 x i16> %va) { define <vscale x 16 x i16> @cttz_nxv16i16(<vscale x 16 x i16> %va) {
; RV32I-LABEL: cttz_nxv16i16: ; RV32I-LABEL: cttz_nxv16i16:
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; RV64I-NEXT: li a0, 257 ; RV64I-NEXT: li a0, 257
; RV64I-NEXT: vmul.vx v8, v8, a0 ; RV64I-NEXT: vmul.vx v8, v8, a0
; RV64I-NEXT: vsrl.vi v8, v8, 8 ; RV64I-NEXT: vsrl.vi v8, v8, 8
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV32D-LABEL: cttz_nxv16i16: ; RV32D-LABEL: cttz_nxv16i16:
; RV32D: # %bb.0: ; RV32D: # %bb.0:
; RV32D-NEXT: vsetvli a0, zero, e16, m4, ta, mu ; RV32D-NEXT: vsetvli a0, zero, e16, m4, ta, mu
; RV32D-NEXT: vmv.v.i v12, 0
; RV32D-NEXT: vmseq.vv v0, v12, v8
; RV32D-NEXT: vrsub.vi v12, v8, 0 ; RV32D-NEXT: vrsub.vi v12, v8, 0
; RV32D-NEXT: vand.vv v8, v8, v12 ; RV32D-NEXT: vand.vv v12, v8, v12
; RV32D-NEXT: vfwcvt.f.xu.v v16, v8 ; RV32D-NEXT: vfwcvt.f.xu.v v16, v12
; RV32D-NEXT: vnsrl.wi v8, v16, 23 ; RV32D-NEXT: vnsrl.wi v12, v16, 23
; RV32D-NEXT: li a0, 127 ; RV32D-NEXT: li a0, 127
; RV32D-NEXT: vsub.vx v8, v8, a0 ; RV32D-NEXT: vsub.vx v12, v12, a0
; RV32D-NEXT: vmseq.vi v0, v8, 0
; RV32D-NEXT: li a0, 16 ; RV32D-NEXT: li a0, 16
; RV32D-NEXT: vmerge.vxm v8, v8, a0, v0 ; RV32D-NEXT: vmerge.vxm v8, v12, a0, v0
; RV32D-NEXT: ret ; RV32D-NEXT: ret
; ;
; RV64D-LABEL: cttz_nxv16i16: ; RV64D-LABEL: cttz_nxv16i16:
; RV64D: # %bb.0: ; RV64D: # %bb.0:
; RV64D-NEXT: vsetvli a0, zero, e16, m4, ta, mu ; RV64D-NEXT: vsetvli a0, zero, e16, m4, ta, mu
; RV64D-NEXT: vmv.v.i v12, 0
; RV64D-NEXT: vmseq.vv v0, v12, v8
; RV64D-NEXT: vrsub.vi v12, v8, 0 ; RV64D-NEXT: vrsub.vi v12, v8, 0
; RV64D-NEXT: vand.vv v8, v8, v12 ; RV64D-NEXT: vand.vv v12, v8, v12
; RV64D-NEXT: vfwcvt.f.xu.v v16, v8 ; RV64D-NEXT: vfwcvt.f.xu.v v16, v12
; RV64D-NEXT: vnsrl.wi v8, v16, 23 ; RV64D-NEXT: vnsrl.wi v12, v16, 23
; RV64D-NEXT: li a0, 127 ; RV64D-NEXT: li a0, 127
; RV64D-NEXT: vsub.vx v8, v8, a0 ; RV64D-NEXT: vsub.vx v12, v12, a0
; RV64D-NEXT: vmseq.vi v0, v8, 0
; RV64D-NEXT: li a0, 16 ; RV64D-NEXT: li a0, 16
; RV64D-NEXT: vmerge.vxm v8, v8, a0, v0 ; RV64D-NEXT: vmerge.vxm v8, v12, a0, v0
; RV64D-NEXT: ret ; RV64D-NEXT: ret
%a = call <vscale x 16 x i16> @llvm.cttz.nxv16i16(<vscale x 16 x i16> %va, i1 false) %a = call <vscale x 16 x i16> @llvm.cttz.nxv16i16(<vscale x 16 x i16> %va, i1 false)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.cttz.nxv16i16(<vscale x 16 x i16>, i1) declare <vscale x 16 x i16> @llvm.cttz.nxv16i16(<vscale x 16 x i16>, i1)
define <vscale x 32 x i16> @cttz_nxv32i16(<vscale x 32 x i16> %va) { define <vscale x 32 x i16> @cttz_nxv32i16(<vscale x 32 x i16> %va) {
; RV32-LABEL: cttz_nxv32i16: ; RV32-LABEL: cttz_nxv32i16:
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; RV32D-NEXT: vmseq.vi v0, v8, 0 ; RV32D-NEXT: vmseq.vi v0, v8, 0
; RV32D-NEXT: li a0, 32 ; RV32D-NEXT: li a0, 32
; RV32D-NEXT: vmerge.vxm v8, v9, a0, v0 ; RV32D-NEXT: vmerge.vxm v8, v9, a0, v0
; RV32D-NEXT: ret ; RV32D-NEXT: ret
; ;
; RV64D-LABEL: cttz_nxv1i32: ; RV64D-LABEL: cttz_nxv1i32:
; RV64D: # %bb.0: ; RV64D: # %bb.0:
; RV64D-NEXT: vsetvli a0, zero, e32, mf2, ta, mu ; RV64D-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
; RV64D-NEXT: vmv.v.i v9, 0
; RV64D-NEXT: vmseq.vv v0, v9, v8
; RV64D-NEXT: vrsub.vi v9, v8, 0 ; RV64D-NEXT: vrsub.vi v9, v8, 0
; RV64D-NEXT: vand.vv v8, v8, v9 ; RV64D-NEXT: vand.vv v9, v8, v9
; RV64D-NEXT: vfwcvt.f.xu.v v9, v8 ; RV64D-NEXT: vfwcvt.f.xu.v v10, v9
; RV64D-NEXT: li a0, 52 ; RV64D-NEXT: li a0, 52
; RV64D-NEXT: vsetvli zero, zero, e64, m1, ta, mu ; RV64D-NEXT: vsetvli zero, zero, e64, m1, ta, mu
; RV64D-NEXT: vsrl.vx v8, v9, a0 ; RV64D-NEXT: vsrl.vx v9, v10, a0
; RV64D-NEXT: vsetvli zero, zero, e32, mf2, ta, mu ; RV64D-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; RV64D-NEXT: vncvt.x.x.w v8, v8 ; RV64D-NEXT: vncvt.x.x.w v9, v9
; RV64D-NEXT: li a0, 1023 ; RV64D-NEXT: li a0, 1023
; RV64D-NEXT: vsub.vx v8, v8, a0 ; RV64D-NEXT: vsub.vx v9, v9, a0
; RV64D-NEXT: vmseq.vi v0, v8, 0
; RV64D-NEXT: li a0, 32 ; RV64D-NEXT: li a0, 32
; RV64D-NEXT: vmerge.vxm v8, v8, a0, v0 ; RV64D-NEXT: vmerge.vxm v8, v9, a0, v0
; RV64D-NEXT: ret ; RV64D-NEXT: ret
%a = call <vscale x 1 x i32> @llvm.cttz.nxv1i32(<vscale x 1 x i32> %va, i1 false) %a = call <vscale x 1 x i32> @llvm.cttz.nxv1i32(<vscale x 1 x i32> %va, i1 false)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 1 x i32> @llvm.cttz.nxv1i32(<vscale x 1 x i32>, i1) declare <vscale x 1 x i32> @llvm.cttz.nxv1i32(<vscale x 1 x i32>, i1)
define <vscale x 2 x i32> @cttz_nxv2i32(<vscale x 2 x i32> %va) { define <vscale x 2 x i32> @cttz_nxv2i32(<vscale x 2 x i32> %va) {
; RV32I-LABEL: cttz_nxv2i32: ; RV32I-LABEL: cttz_nxv2i32:
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; RV32D-NEXT: vmseq.vi v0, v8, 0 ; RV32D-NEXT: vmseq.vi v0, v8, 0
; RV32D-NEXT: li a0, 32 ; RV32D-NEXT: li a0, 32
; RV32D-NEXT: vmerge.vxm v8, v9, a0, v0 ; RV32D-NEXT: vmerge.vxm v8, v9, a0, v0
; RV32D-NEXT: ret ; RV32D-NEXT: ret
; ;
; RV64D-LABEL: cttz_nxv2i32: ; RV64D-LABEL: cttz_nxv2i32:
; RV64D: # %bb.0: ; RV64D: # %bb.0:
; RV64D-NEXT: vsetvli a0, zero, e32, m1, ta, mu ; RV64D-NEXT: vsetvli a0, zero, e32, m1, ta, mu
; RV64D-NEXT: vmv.v.i v9, 0
; RV64D-NEXT: vmseq.vv v0, v9, v8
; RV64D-NEXT: vrsub.vi v9, v8, 0 ; RV64D-NEXT: vrsub.vi v9, v8, 0
; RV64D-NEXT: vand.vv v8, v8, v9 ; RV64D-NEXT: vand.vv v9, v8, v9
; RV64D-NEXT: vfwcvt.f.xu.v v10, v8 ; RV64D-NEXT: vfwcvt.f.xu.v v10, v9
; RV64D-NEXT: li a0, 52 ; RV64D-NEXT: li a0, 52
; RV64D-NEXT: vsetvli zero, zero, e64, m2, ta, mu ; RV64D-NEXT: vsetvli zero, zero, e64, m2, ta, mu
; RV64D-NEXT: vsrl.vx v8, v10, a0 ; RV64D-NEXT: vsrl.vx v10, v10, a0
; RV64D-NEXT: vsetvli zero, zero, e32, m1, ta, mu ; RV64D-NEXT: vsetvli zero, zero, e32, m1, ta, mu
; RV64D-NEXT: vncvt.x.x.w v10, v8 ; RV64D-NEXT: vncvt.x.x.w v9, v10
; RV64D-NEXT: li a0, 1023 ; RV64D-NEXT: li a0, 1023
; RV64D-NEXT: vsub.vx v8, v10, a0 ; RV64D-NEXT: vsub.vx v9, v9, a0
; RV64D-NEXT: vmseq.vi v0, v8, 0
; RV64D-NEXT: li a0, 32 ; RV64D-NEXT: li a0, 32
; RV64D-NEXT: vmerge.vxm v8, v8, a0, v0 ; RV64D-NEXT: vmerge.vxm v8, v9, a0, v0
; RV64D-NEXT: ret ; RV64D-NEXT: ret
%a = call <vscale x 2 x i32> @llvm.cttz.nxv2i32(<vscale x 2 x i32> %va, i1 false) %a = call <vscale x 2 x i32> @llvm.cttz.nxv2i32(<vscale x 2 x i32> %va, i1 false)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.cttz.nxv2i32(<vscale x 2 x i32>, i1) declare <vscale x 2 x i32> @llvm.cttz.nxv2i32(<vscale x 2 x i32>, i1)
define <vscale x 4 x i32> @cttz_nxv4i32(<vscale x 4 x i32> %va) { define <vscale x 4 x i32> @cttz_nxv4i32(<vscale x 4 x i32> %va) {
; RV32I-LABEL: cttz_nxv4i32: ; RV32I-LABEL: cttz_nxv4i32:
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; RV32D-NEXT: vmseq.vi v0, v8, 0 ; RV32D-NEXT: vmseq.vi v0, v8, 0
; RV32D-NEXT: li a0, 32 ; RV32D-NEXT: li a0, 32
; RV32D-NEXT: vmerge.vxm v8, v10, a0, v0 ; RV32D-NEXT: vmerge.vxm v8, v10, a0, v0
; RV32D-NEXT: ret ; RV32D-NEXT: ret
; ;
; RV64D-LABEL: cttz_nxv4i32: ; RV64D-LABEL: cttz_nxv4i32:
; RV64D: # %bb.0: ; RV64D: # %bb.0:
; RV64D-NEXT: vsetvli a0, zero, e32, m2, ta, mu ; RV64D-NEXT: vsetvli a0, zero, e32, m2, ta, mu
; RV64D-NEXT: vmv.v.i v10, 0
; RV64D-NEXT: vmseq.vv v0, v10, v8
; RV64D-NEXT: vrsub.vi v10, v8, 0 ; RV64D-NEXT: vrsub.vi v10, v8, 0
; RV64D-NEXT: vand.vv v8, v8, v10 ; RV64D-NEXT: vand.vv v10, v8, v10
; RV64D-NEXT: vfwcvt.f.xu.v v12, v8 ; RV64D-NEXT: vfwcvt.f.xu.v v12, v10
; RV64D-NEXT: li a0, 52 ; RV64D-NEXT: li a0, 52
; RV64D-NEXT: vsetvli zero, zero, e64, m4, ta, mu ; RV64D-NEXT: vsetvli zero, zero, e64, m4, ta, mu
; RV64D-NEXT: vsrl.vx v8, v12, a0 ; RV64D-NEXT: vsrl.vx v12, v12, a0
; RV64D-NEXT: vsetvli zero, zero, e32, m2, ta, mu ; RV64D-NEXT: vsetvli zero, zero, e32, m2, ta, mu
; RV64D-NEXT: vncvt.x.x.w v12, v8 ; RV64D-NEXT: vncvt.x.x.w v10, v12
; RV64D-NEXT: li a0, 1023 ; RV64D-NEXT: li a0, 1023
; RV64D-NEXT: vsub.vx v8, v12, a0 ; RV64D-NEXT: vsub.vx v10, v10, a0
; RV64D-NEXT: vmseq.vi v0, v8, 0
; RV64D-NEXT: li a0, 32 ; RV64D-NEXT: li a0, 32
; RV64D-NEXT: vmerge.vxm v8, v8, a0, v0 ; RV64D-NEXT: vmerge.vxm v8, v10, a0, v0
; RV64D-NEXT: ret ; RV64D-NEXT: ret
%a = call <vscale x 4 x i32> @llvm.cttz.nxv4i32(<vscale x 4 x i32> %va, i1 false) %a = call <vscale x 4 x i32> @llvm.cttz.nxv4i32(<vscale x 4 x i32> %va, i1 false)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.cttz.nxv4i32(<vscale x 4 x i32>, i1) declare <vscale x 4 x i32> @llvm.cttz.nxv4i32(<vscale x 4 x i32>, i1)
define <vscale x 8 x i32> @cttz_nxv8i32(<vscale x 8 x i32> %va) { define <vscale x 8 x i32> @cttz_nxv8i32(<vscale x 8 x i32> %va) {
; RV32I-LABEL: cttz_nxv8i32: ; RV32I-LABEL: cttz_nxv8i32:
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; RV32D-NEXT: vmseq.vi v0, v8, 0 ; RV32D-NEXT: vmseq.vi v0, v8, 0
; RV32D-NEXT: li a0, 32 ; RV32D-NEXT: li a0, 32
; RV32D-NEXT: vmerge.vxm v8, v12, a0, v0 ; RV32D-NEXT: vmerge.vxm v8, v12, a0, v0
; RV32D-NEXT: ret ; RV32D-NEXT: ret
; ;
; RV64D-LABEL: cttz_nxv8i32: ; RV64D-LABEL: cttz_nxv8i32:
; RV64D: # %bb.0: ; RV64D: # %bb.0:
; RV64D-NEXT: vsetvli a0, zero, e32, m4, ta, mu ; RV64D-NEXT: vsetvli a0, zero, e32, m4, ta, mu
; RV64D-NEXT: vmv.v.i v12, 0
; RV64D-NEXT: vmseq.vv v0, v12, v8
; RV64D-NEXT: vrsub.vi v12, v8, 0 ; RV64D-NEXT: vrsub.vi v12, v8, 0
; RV64D-NEXT: vand.vv v8, v8, v12 ; RV64D-NEXT: vand.vv v12, v8, v12
; RV64D-NEXT: vfwcvt.f.xu.v v16, v8 ; RV64D-NEXT: vfwcvt.f.xu.v v16, v12
; RV64D-NEXT: li a0, 52 ; RV64D-NEXT: li a0, 52
; RV64D-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; RV64D-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV64D-NEXT: vsrl.vx v8, v16, a0 ; RV64D-NEXT: vsrl.vx v16, v16, a0
; RV64D-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; RV64D-NEXT: vsetvli zero, zero, e32, m4, ta, mu
; RV64D-NEXT: vncvt.x.x.w v16, v8 ; RV64D-NEXT: vncvt.x.x.w v12, v16
; RV64D-NEXT: li a0, 1023 ; RV64D-NEXT: li a0, 1023
; RV64D-NEXT: vsub.vx v8, v16, a0 ; RV64D-NEXT: vsub.vx v12, v12, a0
; RV64D-NEXT: vmseq.vi v0, v8, 0
; RV64D-NEXT: li a0, 32 ; RV64D-NEXT: li a0, 32
; RV64D-NEXT: vmerge.vxm v8, v8, a0, v0 ; RV64D-NEXT: vmerge.vxm v8, v12, a0, v0
; RV64D-NEXT: ret ; RV64D-NEXT: ret
%a = call <vscale x 8 x i32> @llvm.cttz.nxv8i32(<vscale x 8 x i32> %va, i1 false) %a = call <vscale x 8 x i32> @llvm.cttz.nxv8i32(<vscale x 8 x i32> %va, i1 false)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.cttz.nxv8i32(<vscale x 8 x i32>, i1) declare <vscale x 8 x i32> @llvm.cttz.nxv8i32(<vscale x 8 x i32>, i1)
define <vscale x 16 x i32> @cttz_nxv16i32(<vscale x 16 x i32> %va) { define <vscale x 16 x i32> @cttz_nxv16i32(<vscale x 16 x i32> %va) {
; RV32-LABEL: cttz_nxv16i32: ; RV32-LABEL: cttz_nxv16i32:
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