[RISCV] Add more .vx patterns for VLMax integer setccs.

[craig.topper]

Summary

This patch synchronizes the structure of the templates with those
in RISCVInstrInfoVVLPatterns.td so that we get patterns with .vx
on the left hand side.

[craig.topper]

llvm/test/CodeGen/RISCV/rvv/cttz-sdnode.ll

53

This was bad canonicalization of a splat with 0 which should stay on the RHS. I've posted D123256 to fix the canonicalization.

[rogfer01]

LGTM. Thanks for the cleanup @craig.topper !

llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td

 
 //===----------------------------------------------------------------------===//
 // Helpers to define the SDNode patterns.
 //===----------------------------------------------------------------------===//
 
 def rvv_vnot : PatFrag<(ops node:$in),
                        (xor node:$in, (riscv_vmset_vl (XLenVT srcvalue)))>;
 
-class SwapHelper<dag Prefix, dag A, dag B, dag Suffix, bit swap> {
-   dag Value = !con(Prefix, !if(swap, B, A), !if(swap, A, B), Suffix);
-}
-
 multiclass VPatUSLoadStoreSDNode<ValueType type,
                                  int log2sew,
                                  LMULInfo vlmul,
                                  OutPatFrag avl,
                                  VReg reg_class,
                                  int sew = !shl(1, log2sew)>
 {
   defvar load_instr = !cast<Instruction>("PseudoVLE"#sew#"_V_"#vlmul.MX);
foreach fvti = AllFloatVectors in
     def : Pat<(fvti.Vector (vop (fvti.Vector (SplatFPOp fvti.Scalar:$rs2)),
                                 (fvti.Vector fvti.RegClass:$rs1))),
               (!cast<Instruction>(instruction_name#"_V"#fvti.ScalarSuffix#"_"#fvti.LMul.MX)
                            fvti.RegClass:$rs1,
                            (fvti.Scalar fvti.ScalarRegClass:$rs2),
                            fvti.AVL, fvti.Log2SEW)>;
 }
 
-multiclass VPatIntegerSetCCSDNode_VV<CondCode cc,
-                                     string instruction_name,
-                                     bit swap = 0> {
+multiclass VPatIntegerSetCCSDNode_VV<string instruction_name,
+                                     CondCode cc> {
   foreach vti = AllIntegerVectors in {
     defvar instruction = !cast<Instruction>(instruction_name#"_VV_"#vti.LMul.MX);
     def : Pat<(vti.Mask (setcc (vti.Vector vti.RegClass:$rs1),
                                (vti.Vector vti.RegClass:$rs2), cc)),
-              SwapHelper<(instruction),
-                         (instruction vti.RegClass:$rs1),
-                         (instruction vti.RegClass:$rs2),
-                         (instruction vti.AVL, vti.Log2SEW),
-                         swap>.Value>;
+              (instruction vti.RegClass:$rs1, vti.RegClass:$rs2, vti.AVL,
+              vti.Log2SEW)>;
+  }
+}
+
+multiclass VPatIntegerSetCCSDNode_VV_Swappable<string instruction_name,
+                                               CondCode cc, CondCode invcc>
+    : VPatIntegerSetCCSDNode_VV<instruction_name, cc> {
+  foreach vti = AllIntegerVectors in {
+    defvar instruction = !cast<Instruction>(instruction_name#"_VV_"#vti.LMul.MX);
+    def : Pat<(vti.Mask (setcc (vti.Vector vti.RegClass:$rs2),
+                               (vti.Vector vti.RegClass:$rs1), invcc)),
+              (instruction vti.RegClass:$rs1, vti.RegClass:$rs2, vti.AVL,
+              vti.Log2SEW)>;
   }
 }
 
-multiclass VPatIntegerSetCCSDNode_XI<CondCode cc,
+multiclass VPatIntegerSetCCSDNode_XI<
                                      string instruction_name,
+                                     CondCode cc,
                                      string kind,
                                      ComplexPattern SplatPatKind,
-                                     DAGOperand xop_kind,
-                                     bit swap = 0> {
+                                     DAGOperand xop_kind> {
   foreach vti = AllIntegerVectors in {
     defvar instruction = !cast<Instruction>(instruction_name#_#kind#_#vti.LMul.MX);
     def : Pat<(vti.Mask (setcc (vti.Vector vti.RegClass:$rs1),
                                (vti.Vector (SplatPatKind xop_kind:$rs2)), cc)),
-              SwapHelper<(instruction),
-                         (instruction vti.RegClass:$rs1),
-                         (instruction xop_kind:$rs2),
-                         (instruction vti.AVL, vti.Log2SEW),
-                         swap>.Value>;
+              (instruction vti.RegClass:$rs1, xop_kind:$rs2, vti.AVL, vti.Log2SEW)>;
   }
 }
 
-multiclass VPatIntegerSetCCSDNode_VV_VX_VI<CondCode cc,
-                                           string instruction_name,
-                                           bit swap = 0> {
-  defm : VPatIntegerSetCCSDNode_VV<cc, instruction_name, swap>;
-  defm : VPatIntegerSetCCSDNode_XI<cc, instruction_name, "VX",
-                                   SplatPat, GPR, swap>;
-  defm : VPatIntegerSetCCSDNode_XI<cc, instruction_name, "VI",
-                                   SplatPat_simm5, simm5, swap>;
+multiclass VPatIntegerSetCCSDNode_XI_Swappable<string instruction_name,
+                                               CondCode cc, CondCode invcc,
+                                               string kind,
+                                               ComplexPattern SplatPatKind,
+                                               DAGOperand xop_kind>
+    : VPatIntegerSetCCSDNode_XI<instruction_name, cc, kind, SplatPatKind,
+                                xop_kind> {
+  foreach vti = AllIntegerVectors in {
+    defvar instruction = !cast<Instruction>(instruction_name#_#kind#_#vti.LMul.MX);
+    def : Pat<(vti.Mask (setcc (vti.Vector vti.RegClass:$rs1),
+                               (vti.Vector (SplatPatKind xop_kind:$rs2)), cc)),
+              (instruction vti.RegClass:$rs1, xop_kind:$rs2, vti.AVL, vti.Log2SEW)>;
+    def : Pat<(vti.Mask (setcc (vti.Vector (SplatPatKind xop_kind:$rs2)),
+                               (vti.Vector vti.RegClass:$rs1), invcc)),
+              (instruction vti.RegClass:$rs1, xop_kind:$rs2, vti.AVL, vti.Log2SEW)>;
   }
-
-multiclass VPatIntegerSetCCSDNode_VV_VX<CondCode cc,
-                                        string instruction_name,
-                                        bit swap = 0> {
-  defm : VPatIntegerSetCCSDNode_VV<cc, instruction_name, swap>;
-  defm : VPatIntegerSetCCSDNode_XI<cc, instruction_name, "VX",
-                                   SplatPat, GPR, swap>;
 }
 
-multiclass VPatIntegerSetCCSDNode_VX_VI<CondCode cc,
-                                        string instruction_name,
-                                        bit swap = 0> {
-  defm : VPatIntegerSetCCSDNode_XI<cc, instruction_name, "VX",
-                                   SplatPat, GPR, swap>;
-  defm : VPatIntegerSetCCSDNode_XI<cc, instruction_name, "VI",
-                                   SplatPat_simm5, simm5, swap>;
-}
+multiclass VPatIntegerSetCCSDNode_VX_Swappable<string instruction_name,
+                                               CondCode cc, CondCode invcc>
+    : VPatIntegerSetCCSDNode_XI_Swappable<instruction_name, cc, invcc, "VX",
+                                          SplatPat, GPR>;
+
+multiclass VPatIntegerSetCCSDNode_VI<string instruction_name, CondCode cc>
+    : VPatIntegerSetCCSDNode_XI<instruction_name, cc, "VI", SplatPat_simm5, simm5>;
 
-multiclass VPatIntegerSetCCSDNode_VIPlus1<CondCode cc, string instruction_name,
+multiclass VPatIntegerSetCCSDNode_VIPlus1<string instruction_name, CondCode cc,
                                           ComplexPattern splatpat_kind> {
   foreach vti = AllIntegerVectors in {
     defvar instruction = !cast<Instruction>(instruction_name#"_VI_"#vti.LMul.MX);
     def : Pat<(vti.Mask (setcc (vti.Vector vti.RegClass:$rs1),
                                (vti.Vector (splatpat_kind simm5:$rs2)),
                                cc)),
               (instruction vti.RegClass:$rs1, (DecImm simm5:$rs2),
                            vti.AVL, vti.Log2SEW)>;
foreach vti = AllIntegerVectors in {
   def : Pat<(shl (vti.Vector vti.RegClass:$rs1),
                  (vti.Vector (riscv_vmv_v_x_vl (vti.Vector undef), 1, (XLenVT srcvalue)))),
             (!cast<Instruction>("PseudoVADD_VV_"# vti.LMul.MX)
                  vti.RegClass:$rs1, vti.RegClass:$rs1, vti.AVL, vti.Log2SEW)>;
 
 }
 
 // 12.8. Vector Integer Comparison Instructions
-defm : VPatIntegerSetCCSDNode_VV_VX_VI<SETEQ,  "PseudoVMSEQ">;
-defm : VPatIntegerSetCCSDNode_VV_VX_VI<SETNE,  "PseudoVMSNE">;
+defm : VPatIntegerSetCCSDNode_VV<"PseudoVMSEQ", SETEQ>;
+defm : VPatIntegerSetCCSDNode_VV<"PseudoVMSNE", SETNE>;
 
-defm : VPatIntegerSetCCSDNode_VV_VX<SETLT,  "PseudoVMSLT">;
-defm : VPatIntegerSetCCSDNode_VV_VX<SETULT, "PseudoVMSLTU">;
-defm : VPatIntegerSetCCSDNode_VIPlus1<SETLT, "PseudoVMSLE",
+defm : VPatIntegerSetCCSDNode_VV_Swappable<"PseudoVMSLT",  SETLT, SETGT>;
+defm : VPatIntegerSetCCSDNode_VV_Swappable<"PseudoVMSLTU", SETULT, SETUGT>;
+defm : VPatIntegerSetCCSDNode_VV_Swappable<"PseudoVMSLE",  SETLE,  SETGE>;
+defm : VPatIntegerSetCCSDNode_VV_Swappable<"PseudoVMSLEU", SETULE, SETUGE>;
+
+defm : VPatIntegerSetCCSDNode_VX_Swappable<"PseudoVMSEQ",  SETEQ,  SETEQ>;
+defm : VPatIntegerSetCCSDNode_VX_Swappable<"PseudoVMSNE",  SETNE,  SETNE>;
+defm : VPatIntegerSetCCSDNode_VX_Swappable<"PseudoVMSLT",  SETLT,  SETGT>;
+defm : VPatIntegerSetCCSDNode_VX_Swappable<"PseudoVMSLTU", SETULT, SETUGT>;
+defm : VPatIntegerSetCCSDNode_VX_Swappable<"PseudoVMSLE",  SETLE,  SETGE>;
+defm : VPatIntegerSetCCSDNode_VX_Swappable<"PseudoVMSLEU", SETULE, SETUGE>;
+defm : VPatIntegerSetCCSDNode_VX_Swappable<"PseudoVMSGT",  SETGT,  SETLT>;
+defm : VPatIntegerSetCCSDNode_VX_Swappable<"PseudoVMSGTU", SETUGT, SETULT>;
+// There is no VMSGE(U)_VX instruction
+
+defm : VPatIntegerSetCCSDNode_VI<"PseudoVMSEQ",  SETEQ>;
+defm : VPatIntegerSetCCSDNode_VI<"PseudoVMSNE",  SETNE>;
+defm : VPatIntegerSetCCSDNode_VI<"PseudoVMSLE",  SETLE>;
+defm : VPatIntegerSetCCSDNode_VI<"PseudoVMSLEU", SETULE>;
+defm : VPatIntegerSetCCSDNode_VI<"PseudoVMSGT",  SETGT>;
+defm : VPatIntegerSetCCSDNode_VI<"PseudoVMSGTU", SETUGT>;
+
+defm : VPatIntegerSetCCSDNode_VIPlus1<"PseudoVMSLE", SETLT,
                                       SplatPat_simm5_plus1_nonzero>;
-defm : VPatIntegerSetCCSDNode_VIPlus1<SETULT, "PseudoVMSLEU",
+defm : VPatIntegerSetCCSDNode_VIPlus1<"PseudoVMSLEU", SETULT,
                                       SplatPat_simm5_plus1_nonzero>;
-
-defm : VPatIntegerSetCCSDNode_VV<SETGT,  "PseudoVMSLT", /*swap*/1>;
-defm : VPatIntegerSetCCSDNode_VV<SETUGT, "PseudoVMSLTU", /*swap*/1>;
-defm : VPatIntegerSetCCSDNode_VX_VI<SETGT,  "PseudoVMSGT">;
-defm : VPatIntegerSetCCSDNode_VX_VI<SETUGT, "PseudoVMSGTU">;
-
-defm : VPatIntegerSetCCSDNode_VV_VX_VI<SETLE,  "PseudoVMSLE">;
-defm : VPatIntegerSetCCSDNode_VV_VX_VI<SETULE, "PseudoVMSLEU">;
-
-defm : VPatIntegerSetCCSDNode_VV<SETGE,  "PseudoVMSLE", /*swap*/1>;
-defm : VPatIntegerSetCCSDNode_VV<SETUGE, "PseudoVMSLEU", /*swap*/1>;
-defm : VPatIntegerSetCCSDNode_VIPlus1<SETGE, "PseudoVMSGT",
+defm : VPatIntegerSetCCSDNode_VIPlus1<"PseudoVMSGT", SETGE,
                                       SplatPat_simm5_plus1>;
-defm : VPatIntegerSetCCSDNode_VIPlus1<SETUGE, "PseudoVMSGTU",
+defm : VPatIntegerSetCCSDNode_VIPlus1<"PseudoVMSGTU", SETUGE,
                                       SplatPat_simm5_plus1_nonzero>;
 
 // 12.9. Vector Integer Min/Max Instructions
 defm : VPatBinarySDNode_VV_VX<umin, "PseudoVMINU">;
 defm : VPatBinarySDNode_VV_VX<smin, "PseudoVMIN">;
 defm : VPatBinarySDNode_VV_VX<umax, "PseudoVMAXU">;
 defm : VPatBinarySDNode_VV_VX<smax, "PseudoVMAX">;
 

llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td

def : Pat<(vti.Mask (riscv_setcc_vl (vti.Vector vti.RegClass:$rs1),
                          (vti.Mask (IMPLICIT_DEF)),
                          vti.RegClass:$rs1,
                          vti.RegClass:$rs2,
                          (vti.Mask V0), GPR:$vl, vti.Log2SEW)>;
 }
 
 // Inherits from VPatIntegerSetCCVL_VV and adds a pattern with operands swapped.
 multiclass VPatIntegerSetCCVL_VV_Swappable<VTypeInfo vti, string instruction_name,
-                                           CondCode cc, CondCode invcc> :
-  VPatIntegerSetCCVL_VV<vti, instruction_name, cc> {
+                                           CondCode cc, CondCode invcc>
+    : VPatIntegerSetCCVL_VV<vti, instruction_name, cc> {
   def : Pat<(vti.Mask (riscv_setcc_vl (vti.Vector vti.RegClass:$rs2),
                                       vti.RegClass:$rs1, invcc,
                                       (vti.Mask true_mask),
                                       VLOpFrag)),
             (!cast<Instruction>(instruction_name#"_VV_"#vti.LMul.MX)
                          vti.RegClass:$rs1, vti.RegClass:$rs2, GPR:$vl,
                          vti.Log2SEW)>;
   def : Pat<(vti.Mask (riscv_setcc_vl (vti.Vector vti.RegClass:$rs2),

llvm/test/CodeGen/RISCV/rvv/cttz-sdnode.ll

 ; RV64I-NEXT:    vsrl.vi v9, v8, 4
 ; RV64I-NEXT:    vadd.vv v8, v8, v9
 ; RV64I-NEXT:    vand.vi v8, v8, 15
 ; RV64I-NEXT:    ret
 ;
 ; RV32D-LABEL: cttz_nxv1i8:
 ; RV32D:       # %bb.0:
 ; RV32D-NEXT:    vsetvli a0, zero, e8, mf8, ta, mu
-; RV32D-NEXT:    vmv.v.i v9, 0
-; RV32D-NEXT:    vmseq.vv v0, v9, v8
+; RV32D-NEXT:    vmseq.vx v0, v8, zero
 ; RV32D-NEXT:    vrsub.vi v9, v8, 0
 ; RV32D-NEXT:    vand.vv v8, v8, v9
 ; RV32D-NEXT:    vsetvli zero, zero, e32, mf2, ta, mu
 ; RV32D-NEXT:    vzext.vf4 v9, v8
 ; RV32D-NEXT:    vfcvt.f.xu.v v8, v9
 ; RV32D-NEXT:    vsetvli zero, zero, e16, mf4, ta, mu
 ; RV32D-NEXT:    vnsrl.wi v8, v8, 23
 ; RV32D-NEXT:    vsetvli zero, zero, e8, mf8, ta, mu
 ; RV32D-NEXT:    vncvt.x.x.w v8, v8
 ; RV32D-NEXT:    li a0, 127
 ; RV32D-NEXT:    vsub.vx v8, v8, a0
 ; RV32D-NEXT:    vmerge.vim v8, v8, 8, v0
 ; RV32D-NEXT:    ret
 ;
 ; RV64D-LABEL: cttz_nxv1i8:
 ; RV64D:       # %bb.0:
 ; RV64D-NEXT:    vsetvli a0, zero, e8, mf8, ta, mu
-; RV64D-NEXT:    vmv.v.i v9, 0
-; RV64D-NEXT:    vmseq.vv v0, v9, v8
+; RV64D-NEXT:    vmseq.vx v0, v8, zero
 ; RV64D-NEXT:    vrsub.vi v9, v8, 0
 ; RV64D-NEXT:    vand.vv v8, v8, v9
 ; RV64D-NEXT:    vsetvli zero, zero, e32, mf2, ta, mu
 ; RV64D-NEXT:    vzext.vf4 v9, v8
 ; RV64D-NEXT:    vfcvt.f.xu.v v8, v9
 ; RV64D-NEXT:    vsetvli zero, zero, e16, mf4, ta, mu
 ; RV64D-NEXT:    vnsrl.wi v8, v8, 23
 ; RV64D-NEXT:    vsetvli zero, zero, e8, mf8, ta, mu

 ; RV64I-NEXT:    vsrl.vi v9, v8, 4
 ; RV64I-NEXT:    vadd.vv v8, v8, v9
 ; RV64I-NEXT:    vand.vi v8, v8, 15
 ; RV64I-NEXT:    ret
 ;
 ; RV32D-LABEL: cttz_nxv2i8:
 ; RV32D:       # %bb.0:
 ; RV32D-NEXT:    vsetvli a0, zero, e8, mf4, ta, mu
-; RV32D-NEXT:    vmv.v.i v9, 0
-; RV32D-NEXT:    vmseq.vv v0, v9, v8
+; RV32D-NEXT:    vmseq.vx v0, v8, zero
 ; RV32D-NEXT:    vrsub.vi v9, v8, 0
 ; RV32D-NEXT:    vand.vv v8, v8, v9
 ; RV32D-NEXT:    vsetvli zero, zero, e32, m1, ta, mu
 ; RV32D-NEXT:    vzext.vf4 v9, v8
 ; RV32D-NEXT:    vfcvt.f.xu.v v8, v9
 ; RV32D-NEXT:    vsetvli zero, zero, e16, mf2, ta, mu
 ; RV32D-NEXT:    vnsrl.wi v8, v8, 23
 ; RV32D-NEXT:    vsetvli zero, zero, e8, mf4, ta, mu
 ; RV32D-NEXT:    vncvt.x.x.w v8, v8
 ; RV32D-NEXT:    li a0, 127
 ; RV32D-NEXT:    vsub.vx v8, v8, a0
 ; RV32D-NEXT:    vmerge.vim v8, v8, 8, v0
 ; RV32D-NEXT:    ret
 ;
 ; RV64D-LABEL: cttz_nxv2i8:
 ; RV64D:       # %bb.0:
 ; RV64D-NEXT:    vsetvli a0, zero, e8, mf4, ta, mu
-; RV64D-NEXT:    vmv.v.i v9, 0
-; RV64D-NEXT:    vmseq.vv v0, v9, v8
+; RV64D-NEXT:    vmseq.vx v0, v8, zero
 ; RV64D-NEXT:    vrsub.vi v9, v8, 0
 ; RV64D-NEXT:    vand.vv v8, v8, v9
 ; RV64D-NEXT:    vsetvli zero, zero, e32, m1, ta, mu
 ; RV64D-NEXT:    vzext.vf4 v9, v8
 ; RV64D-NEXT:    vfcvt.f.xu.v v8, v9
 ; RV64D-NEXT:    vsetvli zero, zero, e16, mf2, ta, mu
 ; RV64D-NEXT:    vnsrl.wi v8, v8, 23
 ; RV64D-NEXT:    vsetvli zero, zero, e8, mf4, ta, mu

 ; RV64I-NEXT:    vsrl.vi v9, v8, 4
 ; RV64I-NEXT:    vadd.vv v8, v8, v9
 ; RV64I-NEXT:    vand.vi v8, v8, 15
 ; RV64I-NEXT:    ret
 ;
 ; RV32D-LABEL: cttz_nxv4i8:
 ; RV32D:       # %bb.0:
 ; RV32D-NEXT:    vsetvli a0, zero, e8, mf2, ta, mu
-; RV32D-NEXT:    vmv.v.i v9, 0
-; RV32D-NEXT:    vmseq.vv v0, v9, v8
+; RV32D-NEXT:    vmseq.vx v0, v8, zero
 ; RV32D-NEXT:    vrsub.vi v9, v8, 0
 ; RV32D-NEXT:    vand.vv v8, v8, v9
 ; RV32D-NEXT:    vsetvli zero, zero, e32, m2, ta, mu
 ; RV32D-NEXT:    vzext.vf4 v10, v8
 ; RV32D-NEXT:    vfcvt.f.xu.v v8, v10
 ; RV32D-NEXT:    vsetvli zero, zero, e16, m1, ta, mu
 ; RV32D-NEXT:    vnsrl.wi v10, v8, 23
 ; RV32D-NEXT:    vsetvli zero, zero, e8, mf2, ta, mu
 ; RV32D-NEXT:    vncvt.x.x.w v8, v10
 ; RV32D-NEXT:    li a0, 127
 ; RV32D-NEXT:    vsub.vx v8, v8, a0
 ; RV32D-NEXT:    vmerge.vim v8, v8, 8, v0
 ; RV32D-NEXT:    ret
 ;
 ; RV64D-LABEL: cttz_nxv4i8:
 ; RV64D:       # %bb.0:
 ; RV64D-NEXT:    vsetvli a0, zero, e8, mf2, ta, mu
-; RV64D-NEXT:    vmv.v.i v9, 0
-; RV64D-NEXT:    vmseq.vv v0, v9, v8
+; RV64D-NEXT:    vmseq.vx v0, v8, zero
 ; RV64D-NEXT:    vrsub.vi v9, v8, 0
 ; RV64D-NEXT:    vand.vv v8, v8, v9
 ; RV64D-NEXT:    vsetvli zero, zero, e32, m2, ta, mu
 ; RV64D-NEXT:    vzext.vf4 v10, v8
 ; RV64D-NEXT:    vfcvt.f.xu.v v8, v10
 ; RV64D-NEXT:    vsetvli zero, zero, e16, m1, ta, mu
 ; RV64D-NEXT:    vnsrl.wi v10, v8, 23
 ; RV64D-NEXT:    vsetvli zero, zero, e8, mf2, ta, mu

 ; RV64I-NEXT:    vsrl.vi v9, v8, 4
 ; RV64I-NEXT:    vadd.vv v8, v8, v9
 ; RV64I-NEXT:    vand.vi v8, v8, 15
 ; RV64I-NEXT:    ret
 ;
 ; RV32D-LABEL: cttz_nxv8i8:
 ; RV32D:       # %bb.0:
 ; RV32D-NEXT:    vsetvli a0, zero, e8, m1, ta, mu
-; RV32D-NEXT:    vmv.v.i v9, 0
-; RV32D-NEXT:    vmseq.vv v0, v9, v8
+; RV32D-NEXT:    vmseq.vx v0, v8, zero
 ; RV32D-NEXT:    vrsub.vi v9, v8, 0
 ; RV32D-NEXT:    vand.vv v8, v8, v9
 ; RV32D-NEXT:    vsetvli zero, zero, e32, m4, ta, mu
 ; RV32D-NEXT:    vzext.vf4 v12, v8
 ; RV32D-NEXT:    vfcvt.f.xu.v v8, v12
 ; RV32D-NEXT:    vsetvli zero, zero, e16, m2, ta, mu
 ; RV32D-NEXT:    vnsrl.wi v12, v8, 23
 ; RV32D-NEXT:    vsetvli zero, zero, e8, m1, ta, mu
 ; RV32D-NEXT:    vncvt.x.x.w v8, v12
 ; RV32D-NEXT:    li a0, 127
 ; RV32D-NEXT:    vsub.vx v8, v8, a0
 ; RV32D-NEXT:    vmerge.vim v8, v8, 8, v0
 ; RV32D-NEXT:    ret
 ;
 ; RV64D-LABEL: cttz_nxv8i8:
 ; RV64D:       # %bb.0:
 ; RV64D-NEXT:    vsetvli a0, zero, e8, m1, ta, mu
-; RV64D-NEXT:    vmv.v.i v9, 0
-; RV64D-NEXT:    vmseq.vv v0, v9, v8
+; RV64D-NEXT:    vmseq.vx v0, v8, zero
 ; RV64D-NEXT:    vrsub.vi v9, v8, 0
 ; RV64D-NEXT:    vand.vv v8, v8, v9
 ; RV64D-NEXT:    vsetvli zero, zero, e32, m4, ta, mu
 ; RV64D-NEXT:    vzext.vf4 v12, v8
 ; RV64D-NEXT:    vfcvt.f.xu.v v8, v12
 ; RV64D-NEXT:    vsetvli zero, zero, e16, m2, ta, mu
 ; RV64D-NEXT:    vnsrl.wi v12, v8, 23
 ; RV64D-NEXT:    vsetvli zero, zero, e8, m1, ta, mu

 ; RV64I-NEXT:    vsrl.vi v10, v8, 4
 ; RV64I-NEXT:    vadd.vv v8, v8, v10
 ; RV64I-NEXT:    vand.vi v8, v8, 15
 ; RV64I-NEXT:    ret
 ;
 ; RV32D-LABEL: cttz_nxv16i8:
 ; RV32D:       # %bb.0:
 ; RV32D-NEXT:    vsetvli a0, zero, e8, m2, ta, mu
-; RV32D-NEXT:    vmv.v.i v10, 0
-; RV32D-NEXT:    vmseq.vv v0, v10, v8
+; RV32D-NEXT:    vmseq.vx v0, v8, zero
 ; RV32D-NEXT:    vrsub.vi v10, v8, 0
 ; RV32D-NEXT:    vand.vv v8, v8, v10
 ; RV32D-NEXT:    vsetvli zero, zero, e32, m8, ta, mu
 ; RV32D-NEXT:    vzext.vf4 v16, v8
 ; RV32D-NEXT:    vfcvt.f.xu.v v8, v16
 ; RV32D-NEXT:    vsetvli zero, zero, e16, m4, ta, mu
 ; RV32D-NEXT:    vnsrl.wi v16, v8, 23
 ; RV32D-NEXT:    vsetvli zero, zero, e8, m2, ta, mu
 ; RV32D-NEXT:    vncvt.x.x.w v8, v16
 ; RV32D-NEXT:    li a0, 127
 ; RV32D-NEXT:    vsub.vx v8, v8, a0
 ; RV32D-NEXT:    vmerge.vim v8, v8, 8, v0
 ; RV32D-NEXT:    ret
 ;
 ; RV64D-LABEL: cttz_nxv16i8:
 ; RV64D:       # %bb.0:
 ; RV64D-NEXT:    vsetvli a0, zero, e8, m2, ta, mu
-; RV64D-NEXT:    vmv.v.i v10, 0
-; RV64D-NEXT:    vmseq.vv v0, v10, v8
+; RV64D-NEXT:    vmseq.vx v0, v8, zero
 ; RV64D-NEXT:    vrsub.vi v10, v8, 0
 ; RV64D-NEXT:    vand.vv v8, v8, v10
 ; RV64D-NEXT:    vsetvli zero, zero, e32, m8, ta, mu
 ; RV64D-NEXT:    vzext.vf4 v16, v8
 ; RV64D-NEXT:    vfcvt.f.xu.v v8, v16
 ; RV64D-NEXT:    vsetvli zero, zero, e16, m4, ta, mu
 ; RV64D-NEXT:    vnsrl.wi v16, v8, 23
 ; RV64D-NEXT:    vsetvli zero, zero, e8, m2, ta, mu

 ; RV64I-NEXT:    li a0, 257
 ; RV64I-NEXT:    vmul.vx v8, v8, a0
 ; RV64I-NEXT:    vsrl.vi v8, v8, 8
 ; RV64I-NEXT:    ret
 ;
 ; RV32D-LABEL: cttz_nxv1i16:
 ; RV32D:       # %bb.0:
 ; RV32D-NEXT:    vsetvli a0, zero, e16, mf4, ta, mu
-; RV32D-NEXT:    vmv.v.i v9, 0
-; RV32D-NEXT:    vmseq.vv v0, v9, v8
+; RV32D-NEXT:    vmseq.vx v0, v8, zero
 ; RV32D-NEXT:    vrsub.vi v9, v8, 0
 ; RV32D-NEXT:    vand.vv v8, v8, v9
 ; RV32D-NEXT:    vfwcvt.f.xu.v v9, v8
 ; RV32D-NEXT:    vnsrl.wi v8, v9, 23
 ; RV32D-NEXT:    li a0, 127
 ; RV32D-NEXT:    vsub.vx v8, v8, a0
 ; RV32D-NEXT:    li a0, 16
 ; RV32D-NEXT:    vmerge.vxm v8, v8, a0, v0
 ; RV32D-NEXT:    ret
 ;
 ; RV64D-LABEL: cttz_nxv1i16:
 ; RV64D:       # %bb.0:
 ; RV64D-NEXT:    vsetvli a0, zero, e16, mf4, ta, mu
-; RV64D-NEXT:    vmv.v.i v9, 0
-; RV64D-NEXT:    vmseq.vv v0, v9, v8
+; RV64D-NEXT:    vmseq.vx v0, v8, zero
 ; RV64D-NEXT:    vrsub.vi v9, v8, 0
 ; RV64D-NEXT:    vand.vv v8, v8, v9
 ; RV64D-NEXT:    vfwcvt.f.xu.v v9, v8
 ; RV64D-NEXT:    vnsrl.wi v8, v9, 23
 ; RV64D-NEXT:    li a0, 127
 ; RV64D-NEXT:    vsub.vx v8, v8, a0
 ; RV64D-NEXT:    li a0, 16
 ; RV64D-NEXT:    vmerge.vxm v8, v8, a0, v0

 ; RV64I-NEXT:    li a0, 257
 ; RV64I-NEXT:    vmul.vx v8, v8, a0
 ; RV64I-NEXT:    vsrl.vi v8, v8, 8
 ; RV64I-NEXT:    ret
 ;
 ; RV32D-LABEL: cttz_nxv2i16:
 ; RV32D:       # %bb.0:
 ; RV32D-NEXT:    vsetvli a0, zero, e16, mf2, ta, mu
-; RV32D-NEXT:    vmv.v.i v9, 0
-; RV32D-NEXT:    vmseq.vv v0, v9, v8
+; RV32D-NEXT:    vmseq.vx v0, v8, zero
 ; RV32D-NEXT:    vrsub.vi v9, v8, 0
 ; RV32D-NEXT:    vand.vv v8, v8, v9
 ; RV32D-NEXT:    vfwcvt.f.xu.v v9, v8
 ; RV32D-NEXT:    vnsrl.wi v8, v9, 23
 ; RV32D-NEXT:    li a0, 127
 ; RV32D-NEXT:    vsub.vx v8, v8, a0
 ; RV32D-NEXT:    li a0, 16
 ; RV32D-NEXT:    vmerge.vxm v8, v8, a0, v0
 ; RV32D-NEXT:    ret
 ;
 ; RV64D-LABEL: cttz_nxv2i16:
 ; RV64D:       # %bb.0:
 ; RV64D-NEXT:    vsetvli a0, zero, e16, mf2, ta, mu
-; RV64D-NEXT:    vmv.v.i v9, 0
-; RV64D-NEXT:    vmseq.vv v0, v9, v8
+; RV64D-NEXT:    vmseq.vx v0, v8, zero
 ; RV64D-NEXT:    vrsub.vi v9, v8, 0
 ; RV64D-NEXT:    vand.vv v8, v8, v9
 ; RV64D-NEXT:    vfwcvt.f.xu.v v9, v8
 ; RV64D-NEXT:    vnsrl.wi v8, v9, 23
 ; RV64D-NEXT:    li a0, 127
 ; RV64D-NEXT:    vsub.vx v8, v8, a0
 ; RV64D-NEXT:    li a0, 16
 ; RV64D-NEXT:    vmerge.vxm v8, v8, a0, v0

 ; RV64I-NEXT:    li a0, 257
 ; RV64I-NEXT:    vmul.vx v8, v8, a0
 ; RV64I-NEXT:    vsrl.vi v8, v8, 8
 ; RV64I-NEXT:    ret
 ;
 ; RV32D-LABEL: cttz_nxv4i16:
 ; RV32D:       # %bb.0:
 ; RV32D-NEXT:    vsetvli a0, zero, e16, m1, ta, mu
-; RV32D-NEXT:    vmv.v.i v9, 0
-; RV32D-NEXT:    vmseq.vv v0, v9, v8
+; RV32D-NEXT:    vmseq.vx v0, v8, zero
 ; RV32D-NEXT:    vrsub.vi v9, v8, 0
 ; RV32D-NEXT:    vand.vv v8, v8, v9
 ; RV32D-NEXT:    vfwcvt.f.xu.v v10, v8
 ; RV32D-NEXT:    vnsrl.wi v8, v10, 23
 ; RV32D-NEXT:    li a0, 127
 ; RV32D-NEXT:    vsub.vx v8, v8, a0
 ; RV32D-NEXT:    li a0, 16
 ; RV32D-NEXT:    vmerge.vxm v8, v8, a0, v0
 ; RV32D-NEXT:    ret
 ;
 ; RV64D-LABEL: cttz_nxv4i16:
 ; RV64D:       # %bb.0:
 ; RV64D-NEXT:    vsetvli a0, zero, e16, m1, ta, mu
-; RV64D-NEXT:    vmv.v.i v9, 0
-; RV64D-NEXT:    vmseq.vv v0, v9, v8
+; RV64D-NEXT:    vmseq.vx v0, v8, zero
 ; RV64D-NEXT:    vrsub.vi v9, v8, 0
 ; RV64D-NEXT:    vand.vv v8, v8, v9
 ; RV64D-NEXT:    vfwcvt.f.xu.v v10, v8
 ; RV64D-NEXT:    vnsrl.wi v8, v10, 23
 ; RV64D-NEXT:    li a0, 127
 ; RV64D-NEXT:    vsub.vx v8, v8, a0
 ; RV64D-NEXT:    li a0, 16
 ; RV64D-NEXT:    vmerge.vxm v8, v8, a0, v0

 ; RV64I-NEXT:    li a0, 257
 ; RV64I-NEXT:    vmul.vx v8, v8, a0
 ; RV64I-NEXT:    vsrl.vi v8, v8, 8
 ; RV64I-NEXT:    ret
 ;
 ; RV32D-LABEL: cttz_nxv8i16:
 ; RV32D:       # %bb.0:
 ; RV32D-NEXT:    vsetvli a0, zero, e16, m2, ta, mu
-; RV32D-NEXT:    vmv.v.i v10, 0
-; RV32D-NEXT:    vmseq.vv v0, v10, v8
+; RV32D-NEXT:    vmseq.vx v0, v8, zero
 ; RV32D-NEXT:    vrsub.vi v10, v8, 0
 ; RV32D-NEXT:    vand.vv v8, v8, v10
 ; RV32D-NEXT:    vfwcvt.f.xu.v v12, v8
 ; RV32D-NEXT:    vnsrl.wi v8, v12, 23
 ; RV32D-NEXT:    li a0, 127
 ; RV32D-NEXT:    vsub.vx v8, v8, a0
 ; RV32D-NEXT:    li a0, 16
 ; RV32D-NEXT:    vmerge.vxm v8, v8, a0, v0
 ; RV32D-NEXT:    ret
 ;
 ; RV64D-LABEL: cttz_nxv8i16:
 ; RV64D:       # %bb.0:
 ; RV64D-NEXT:    vsetvli a0, zero, e16, m2, ta, mu
-; RV64D-NEXT:    vmv.v.i v10, 0
-; RV64D-NEXT:    vmseq.vv v0, v10, v8
+; RV64D-NEXT:    vmseq.vx v0, v8, zero
 ; RV64D-NEXT:    vrsub.vi v10, v8, 0
 ; RV64D-NEXT:    vand.vv v8, v8, v10
 ; RV64D-NEXT:    vfwcvt.f.xu.v v12, v8
 ; RV64D-NEXT:    vnsrl.wi v8, v12, 23
 ; RV64D-NEXT:    li a0, 127
 ; RV64D-NEXT:    vsub.vx v8, v8, a0
 ; RV64D-NEXT:    li a0, 16
 ; RV64D-NEXT:    vmerge.vxm v8, v8, a0, v0

 ; RV64I-NEXT:    li a0, 257
 ; RV64I-NEXT:    vmul.vx v8, v8, a0
 ; RV64I-NEXT:    vsrl.vi v8, v8, 8
 ; RV64I-NEXT:    ret
 ;
 ; RV32D-LABEL: cttz_nxv16i16:
 ; RV32D:       # %bb.0:
 ; RV32D-NEXT:    vsetvli a0, zero, e16, m4, ta, mu
-; RV32D-NEXT:    vmv.v.i v12, 0
-; RV32D-NEXT:    vmseq.vv v0, v12, v8
+; RV32D-NEXT:    vmseq.vx v0, v8, zero
 ; RV32D-NEXT:    vrsub.vi v12, v8, 0
 ; RV32D-NEXT:    vand.vv v8, v8, v12
 ; RV32D-NEXT:    vfwcvt.f.xu.v v16, v8
 ; RV32D-NEXT:    vnsrl.wi v8, v16, 23
 ; RV32D-NEXT:    li a0, 127
 ; RV32D-NEXT:    vsub.vx v8, v8, a0
 ; RV32D-NEXT:    li a0, 16
 ; RV32D-NEXT:    vmerge.vxm v8, v8, a0, v0
 ; RV32D-NEXT:    ret
 ;
 ; RV64D-LABEL: cttz_nxv16i16:
 ; RV64D:       # %bb.0:
 ; RV64D-NEXT:    vsetvli a0, zero, e16, m4, ta, mu
-; RV64D-NEXT:    vmv.v.i v12, 0
-; RV64D-NEXT:    vmseq.vv v0, v12, v8
+; RV64D-NEXT:    vmseq.vx v0, v8, zero
 ; RV64D-NEXT:    vrsub.vi v12, v8, 0
 ; RV64D-NEXT:    vand.vv v8, v8, v12
 ; RV64D-NEXT:    vfwcvt.f.xu.v v16, v8
 ; RV64D-NEXT:    vnsrl.wi v8, v16, 23
 ; RV64D-NEXT:    li a0, 127
 ; RV64D-NEXT:    vsub.vx v8, v8, a0
 ; RV64D-NEXT:    li a0, 16
 ; RV64D-NEXT:    vmerge.vxm v8, v8, a0, v0

 ; RV32D-NEXT:    vmseq.vi v0, v8, 0
 ; RV32D-NEXT:    li a0, 32
 ; RV32D-NEXT:    vmerge.vxm v8, v9, a0, v0
 ; RV32D-NEXT:    ret
 ;
 ; RV64D-LABEL: cttz_nxv1i32:
 ; RV64D:       # %bb.0:
 ; RV64D-NEXT:    vsetvli a0, zero, e32, mf2, ta, mu
-; RV64D-NEXT:    vmv.v.i v9, 0
-; RV64D-NEXT:    vmseq.vv v0, v9, v8
+; RV64D-NEXT:    vmseq.vx v0, v8, zero
 ; RV64D-NEXT:    vrsub.vi v9, v8, 0
 ; RV64D-NEXT:    vand.vv v8, v8, v9
 ; RV64D-NEXT:    vfwcvt.f.xu.v v9, v8
 ; RV64D-NEXT:    li a0, 52
 ; RV64D-NEXT:    vsetvli zero, zero, e64, m1, ta, mu
 ; RV64D-NEXT:    vsrl.vx v8, v9, a0
 ; RV64D-NEXT:    vsetvli zero, zero, e32, mf2, ta, mu
 ; RV64D-NEXT:    vncvt.x.x.w v8, v8

 ; RV32D-NEXT:    vmseq.vi v0, v8, 0
 ; RV32D-NEXT:    li a0, 32
 ; RV32D-NEXT:    vmerge.vxm v8, v9, a0, v0
 ; RV32D-NEXT:    ret
 ;
 ; RV64D-LABEL: cttz_nxv2i32:
 ; RV64D:       # %bb.0:
 ; RV64D-NEXT:    vsetvli a0, zero, e32, m1, ta, mu
-; RV64D-NEXT:    vmv.v.i v9, 0
-; RV64D-NEXT:    vmseq.vv v0, v9, v8
+; RV64D-NEXT:    vmseq.vx v0, v8, zero
 ; RV64D-NEXT:    vrsub.vi v9, v8, 0
 ; RV64D-NEXT:    vand.vv v8, v8, v9
 ; RV64D-NEXT:    vfwcvt.f.xu.v v10, v8
 ; RV64D-NEXT:    li a0, 52
 ; RV64D-NEXT:    vsetvli zero, zero, e64, m2, ta, mu
 ; RV64D-NEXT:    vsrl.vx v8, v10, a0
 ; RV64D-NEXT:    vsetvli zero, zero, e32, m1, ta, mu
 ; RV64D-NEXT:    vncvt.x.x.w v10, v8

 ; RV32D-NEXT:    vmseq.vi v0, v8, 0
 ; RV32D-NEXT:    li a0, 32
 ; RV32D-NEXT:    vmerge.vxm v8, v10, a0, v0
 ; RV32D-NEXT:    ret
 ;
 ; RV64D-LABEL: cttz_nxv4i32:
 ; RV64D:       # %bb.0:
 ; RV64D-NEXT:    vsetvli a0, zero, e32, m2, ta, mu
-; RV64D-NEXT:    vmv.v.i v10, 0
-; RV64D-NEXT:    vmseq.vv v0, v10, v8
+; RV64D-NEXT:    vmseq.vx v0, v8, zero
 ; RV64D-NEXT:    vrsub.vi v10, v8, 0
 ; RV64D-NEXT:    vand.vv v8, v8, v10
 ; RV64D-NEXT:    vfwcvt.f.xu.v v12, v8
 ; RV64D-NEXT:    li a0, 52
 ; RV64D-NEXT:    vsetvli zero, zero, e64, m4, ta, mu
 ; RV64D-NEXT:    vsrl.vx v8, v12, a0
 ; RV64D-NEXT:    vsetvli zero, zero, e32, m2, ta, mu
 ; RV64D-NEXT:    vncvt.x.x.w v12, v8

 ; RV32D-NEXT:    vmseq.vi v0, v8, 0
 ; RV32D-NEXT:    li a0, 32
 ; RV32D-NEXT:    vmerge.vxm v8, v12, a0, v0
 ; RV32D-NEXT:    ret
 ;
 ; RV64D-LABEL: cttz_nxv8i32:
 ; RV64D:       # %bb.0:
 ; RV64D-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
-; RV64D-NEXT:    vmv.v.i v12, 0
-; RV64D-NEXT:    vmseq.vv v0, v12, v8
+; RV64D-NEXT:    vmseq.vx v0, v8, zero
 ; RV64D-NEXT:    vrsub.vi v12, v8, 0
 ; RV64D-NEXT:    vand.vv v8, v8, v12
 ; RV64D-NEXT:    vfwcvt.f.xu.v v16, v8
 ; RV64D-NEXT:    li a0, 52
 ; RV64D-NEXT:    vsetvli zero, zero, e64, m8, ta, mu
 ; RV64D-NEXT:    vsrl.vx v8, v16, a0
 ; RV64D-NEXT:    vsetvli zero, zero, e32, m4, ta, mu
 ; RV64D-NEXT:    vncvt.x.x.w v16, v8

llvm/test/CodeGen/RISCV/rvv/setcc-integer.ll

; CHECK-NEXT:    ret
   %vc = icmp eq <vscale x 8 x i8> %va, %splat
   ret <vscale x 8 x i1> %vc
 }
 
 define <vscale x 8 x i1> @icmp_eq_xv_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {
 ; CHECK-LABEL: icmp_eq_xv_nxv8i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a1, zero, e8, m1, ta, mu
-; CHECK-NEXT:    vmv.v.x v9, a0
-; CHECK-NEXT:    vmseq.vv v0, v9, v8
+; CHECK-NEXT:    vmseq.vx v0, v8, a0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0
   %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
   %vc = icmp eq <vscale x 8 x i8> %splat, %va
   ret <vscale x 8 x i1> %vc
 }
 
 define <vscale x 8 x i1> @icmp_eq_vi_nxv8i8_0(<vscale x 8 x i8> %va) {
; CHECK-NEXT:    ret
   %vc = icmp ne <vscale x 8 x i8> %va, %splat
   ret <vscale x 8 x i1> %vc
 }
 
 define <vscale x 8 x i1> @icmp_ne_xv_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {
 ; CHECK-LABEL: icmp_ne_xv_nxv8i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a1, zero, e8, m1, ta, mu
-; CHECK-NEXT:    vmv.v.x v9, a0
-; CHECK-NEXT:    vmsne.vv v0, v9, v8
+; CHECK-NEXT:    vmsne.vx v0, v8, a0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0
   %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
   %vc = icmp ne <vscale x 8 x i8> %splat, %va
   ret <vscale x 8 x i1> %vc
 }
 
 define <vscale x 8 x i1> @icmp_ne_vi_nxv8i8_0(<vscale x 8 x i8> %va) {
; CHECK-NEXT:    ret
   %vc = icmp ugt <vscale x 8 x i8> %va, %splat
   ret <vscale x 8 x i1> %vc
 }
 
 define <vscale x 8 x i1> @icmp_ugt_xv_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {
 ; CHECK-LABEL: icmp_ugt_xv_nxv8i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a1, zero, e8, m1, ta, mu
-; CHECK-NEXT:    vmv.v.x v9, a0
-; CHECK-NEXT:    vmsltu.vv v0, v8, v9
+; CHECK-NEXT:    vmsltu.vx v0, v8, a0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0
   %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
   %vc = icmp ugt <vscale x 8 x i8> %splat, %va
   ret <vscale x 8 x i1> %vc
 }
 
 define <vscale x 8 x i1> @icmp_ugt_vi_nxv8i8_0(<vscale x 8 x i8> %va) {
; CHECK-NEXT:    ret
   %vc = icmp uge <vscale x 8 x i8> %va, %splat
   ret <vscale x 8 x i1> %vc
 }
 
 define <vscale x 8 x i1> @icmp_uge_xv_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {
 ; CHECK-LABEL: icmp_uge_xv_nxv8i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a1, zero, e8, m1, ta, mu
-; CHECK-NEXT:    vmv.v.x v9, a0
-; CHECK-NEXT:    vmsleu.vv v0, v8, v9
+; CHECK-NEXT:    vmsleu.vx v0, v8, a0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0
   %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
   %vc = icmp uge <vscale x 8 x i8> %splat, %va
   ret <vscale x 8 x i1> %vc
 }
 
 define <vscale x 8 x i1> @icmp_uge_vi_nxv8i8_0(<vscale x 8 x i8> %va) {
; CHECK-NEXT:    ret
   %vc = icmp ult <vscale x 8 x i8> %va, %splat
   ret <vscale x 8 x i1> %vc
 }
 
 define <vscale x 8 x i1> @icmp_ult_xv_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {
 ; CHECK-LABEL: icmp_ult_xv_nxv8i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a1, zero, e8, m1, ta, mu
-; CHECK-NEXT:    vmv.v.x v9, a0
-; CHECK-NEXT:    vmsltu.vv v0, v9, v8
+; CHECK-NEXT:    vmsgtu.vx v0, v8, a0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0
   %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
   %vc = icmp ult <vscale x 8 x i8> %splat, %va
   ret <vscale x 8 x i1> %vc
 }
 
 define <vscale x 8 x i1> @icmp_ult_vi_nxv8i8_0(<vscale x 8 x i8> %va) {
; CHECK-NEXT:    ret
   %vc = icmp sgt <vscale x 8 x i8> %va, %splat
   ret <vscale x 8 x i1> %vc
 }
 
 define <vscale x 8 x i1> @icmp_sgt_xv_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {
 ; CHECK-LABEL: icmp_sgt_xv_nxv8i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a1, zero, e8, m1, ta, mu
-; CHECK-NEXT:    vmv.v.x v9, a0
-; CHECK-NEXT:    vmslt.vv v0, v8, v9
+; CHECK-NEXT:    vmslt.vx v0, v8, a0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0
   %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
   %vc = icmp sgt <vscale x 8 x i8> %splat, %va
   ret <vscale x 8 x i1> %vc
 }
 
 define <vscale x 8 x i1> @icmp_sgt_vi_nxv8i8_0(<vscale x 8 x i8> %va) {
; CHECK-NEXT:    ret
   %vc = icmp sge <vscale x 8 x i8> %va, %splat
   ret <vscale x 8 x i1> %vc
 }
 
 define <vscale x 8 x i1> @icmp_sge_xv_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {
 ; CHECK-LABEL: icmp_sge_xv_nxv8i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a1, zero, e8, m1, ta, mu
-; CHECK-NEXT:    vmv.v.x v9, a0
-; CHECK-NEXT:    vmsle.vv v0, v8, v9
+; CHECK-NEXT:    vmsle.vx v0, v8, a0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0
   %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
   %vc = icmp sge <vscale x 8 x i8> %splat, %va
   ret <vscale x 8 x i1> %vc
 }
 
 define <vscale x 8 x i1> @icmp_sge_vi_nxv8i8_0(<vscale x 8 x i8> %va) {
; CHECK-NEXT:    ret
   %vc = icmp slt <vscale x 8 x i8> %va, %splat
   ret <vscale x 8 x i1> %vc
 }
 
 define <vscale x 8 x i1> @icmp_slt_xv_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {
 ; CHECK-LABEL: icmp_slt_xv_nxv8i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a1, zero, e8, m1, ta, mu
-; CHECK-NEXT:    vmv.v.x v9, a0
-; CHECK-NEXT:    vmslt.vv v0, v9, v8
+; CHECK-NEXT:    vmsgt.vx v0, v8, a0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0
   %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
   %vc = icmp slt <vscale x 8 x i8> %splat, %va
   ret <vscale x 8 x i1> %vc
 }
 
 define <vscale x 8 x i1> @icmp_slt_vi_nxv8i8_0(<vscale x 8 x i8> %va) {
; CHECK-NEXT:    ret
   %vc = icmp eq <vscale x 8 x i16> %va, %splat
   ret <vscale x 8 x i1> %vc
 }
 
 define <vscale x 8 x i1> @icmp_eq_xv_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {
 ; CHECK-LABEL: icmp_eq_xv_nxv8i16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a1, zero, e16, m2, ta, mu
-; CHECK-NEXT:    vmv.v.x v10, a0
-; CHECK-NEXT:    vmseq.vv v0, v10, v8
+; CHECK-NEXT:    vmseq.vx v0, v8, a0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0
   %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
   %vc = icmp eq <vscale x 8 x i16> %splat, %va
   ret <vscale x 8 x i1> %vc
 }
 
 define <vscale x 8 x i1> @icmp_eq_vi_nxv8i16_0(<vscale x 8 x i16> %va) {
; CHECK-NEXT:    ret
   %vc = icmp ne <vscale x 8 x i16> %va, %splat
   ret <vscale x 8 x i1> %vc
 }
 
 define <vscale x 8 x i1> @icmp_ne_xv_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {
 ; CHECK-LABEL: icmp_ne_xv_nxv8i16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a1, zero, e16, m2, ta, mu
-; CHECK-NEXT:    vmv.v.x v10, a0
-; CHECK-NEXT:    vmsne.vv v0, v10, v8
+; CHECK-NEXT:    vmsne.vx v0, v8, a0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0
   %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
   %vc = icmp ne <vscale x 8 x i16> %splat, %va
   ret <vscale x 8 x i1> %vc
 }
 
 define <vscale x 8 x i1> @icmp_ne_vi_nxv8i16_0(<vscale x 8 x i16> %va) {
; CHECK-NEXT:    ret
   %vc = icmp ugt <vscale x 8 x i16> %va, %splat
   ret <vscale x 8 x i1> %vc
 }
 
 define <vscale x 8 x i1> @icmp_ugt_xv_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {
 ; CHECK-LABEL: icmp_ugt_xv_nxv8i16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a1, zero, e16, m2, ta, mu
-; CHECK-NEXT:    vmv.v.x v10, a0
-; CHECK-NEXT:    vmsltu.vv v0, v8, v10
+; CHECK-NEXT:    vmsltu.vx v0, v8, a0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0
   %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
   %vc = icmp ugt <vscale x 8 x i16> %splat, %va
   ret <vscale x 8 x i1> %vc
 }
 
 define <vscale x 8 x i1> @icmp_ugt_vi_nxv8i16_0(<vscale x 8 x i16> %va) {
; CHECK-NEXT:    ret
   %vc = icmp uge <vscale x 8 x i16> %va, %splat
   ret <vscale x 8 x i1> %vc
 }
 
 define <vscale x 8 x i1> @icmp_uge_xv_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {
 ; CHECK-LABEL: icmp_uge_xv_nxv8i16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a1, zero, e16, m2, ta, mu
-; CHECK-NEXT:    vmv.v.x v10, a0
-; CHECK-NEXT:    vmsleu.vv v0, v8, v10
+; CHECK-NEXT:    vmsleu.vx v0, v8, a0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0
   %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
   %vc = icmp uge <vscale x 8 x i16> %splat, %va
   ret <vscale x 8 x i1> %vc
 }
 
 define <vscale x 8 x i1> @icmp_uge_vi_nxv8i16_0(<vscale x 8 x i16> %va) {
; CHECK-NEXT:    ret
   %vc = icmp ult <vscale x 8 x i16> %va, %splat
   ret <vscale x 8 x i1> %vc
 }
 
 define <vscale x 8 x i1> @icmp_ult_xv_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {
 ; CHECK-LABEL: icmp_ult_xv_nxv8i16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a1, zero, e16, m2, ta, mu
-; CHECK-NEXT:    vmv.v.x v10, a0
-; CHECK-NEXT:    vmsltu.vv v0, v10, v8
+; CHECK-NEXT:    vmsgtu.vx v0, v8, a0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0
   %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
   %vc = icmp ult <vscale x 8 x i16> %splat, %va
   ret <vscale x 8 x i1> %vc
 }
 
 define <vscale x 8 x i1> @icmp_ult_vi_nxv8i16_0(<vscale x 8 x i16> %va) {
; CHECK-NEXT:    ret
   %vc = icmp sgt <vscale x 8 x i16> %va, %splat
   ret <vscale x 8 x i1> %vc
 }
 
 define <vscale x 8 x i1> @icmp_sgt_xv_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {
 ; CHECK-LABEL: icmp_sgt_xv_nxv8i16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a1, zero, e16, m2, ta, mu
-; CHECK-NEXT:    vmv.v.x v10, a0
-; CHECK-NEXT:    vmslt.vv v0, v8, v10
+; CHECK-NEXT:    vmslt.vx v0, v8, a0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0
   %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
   %vc = icmp sgt <vscale x 8 x i16> %splat, %va
   ret <vscale x 8 x i1> %vc
 }
 
 define <vscale x 8 x i1> @icmp_sgt_vi_nxv8i16_0(<vscale x 8 x i16> %va) {
; CHECK-NEXT:    ret
   %vc = icmp sge <vscale x 8 x i16> %va, %splat
   ret <vscale x 8 x i1> %vc
 }
 
 define <vscale x 8 x i1> @icmp_sge_xv_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {
 ; CHECK-LABEL: icmp_sge_xv_nxv8i16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a1, zero, e16, m2, ta, mu
-; CHECK-NEXT:    vmv.v.x v10, a0
-; CHECK-NEXT:    vmsle.vv v0, v8, v10
+; CHECK-NEXT:    vmsle.vx v0, v8, a0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0
   %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
   %vc = icmp sge <vscale x 8 x i16> %splat, %va
   ret <vscale x 8 x i1> %vc
 }
 
 define <vscale x 8 x i1> @icmp_sge_vi_nxv8i16_0(<vscale x 8 x i16> %va) {
; CHECK-NEXT:    ret
   %vc = icmp slt <vscale x 8 x i16> %va, %splat
   ret <vscale x 8 x i1> %vc
 }
 
 define <vscale x 8 x i1> @icmp_slt_xv_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {
 ; CHECK-LABEL: icmp_slt_xv_nxv8i16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a1, zero, e16, m2, ta, mu
-; CHECK-NEXT:    vmv.v.x v10, a0
-; CHECK-NEXT:    vmslt.vv v0, v10, v8
+; CHECK-NEXT:    vmsgt.vx v0, v8, a0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0
   %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
   %vc = icmp slt <vscale x 8 x i16> %splat, %va
   ret <vscale x 8 x i1> %vc
 }
 
 define <vscale x 8 x i1> @icmp_slt_vi_nxv8i16_0(<vscale x 8 x i16> %va) {
; CHECK-NEXT:    ret
   %vc = icmp eq <vscale x 8 x i32> %va, %splat
   ret <vscale x 8 x i1> %vc
 }
 
 define <vscale x 8 x i1> @icmp_eq_xv_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {
 ; CHECK-LABEL: icmp_eq_xv_nxv8i32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
-; CHECK-NEXT:    vmv.v.x v12, a0
-; CHECK-NEXT:    vmseq.vv v0, v12, v8
+; CHECK-NEXT:    vmseq.vx v0, v8, a0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
   %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
   %vc = icmp eq <vscale x 8 x i32> %splat, %va
   ret <vscale x 8 x i1> %vc
 }
 
 define <vscale x 8 x i1> @icmp_eq_vi_nxv8i32_0(<vscale x 8 x i32> %va) {
; CHECK-NEXT:    ret
   %vc = icmp ne <vscale x 8 x i32> %va, %splat
   ret <vscale x 8 x i1> %vc
 }
 
 define <vscale x 8 x i1> @icmp_ne_xv_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {
 ; CHECK-LABEL: icmp_ne_xv_nxv8i32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
-; CHECK-NEXT:    vmv.v.x v12, a0
-; CHECK-NEXT:    vmsne.vv v0, v12, v8
+; CHECK-NEXT:    vmsne.vx v0, v8, a0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
   %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
   %vc = icmp ne <vscale x 8 x i32> %splat, %va
   ret <vscale x 8 x i1> %vc
 }
 
 define <vscale x 8 x i1> @icmp_ne_vi_nxv8i32_0(<vscale x 8 x i32> %va) {
; CHECK-NEXT:    ret
   %vc = icmp ugt <vscale x 8 x i32> %va, %splat
   ret <vscale x 8 x i1> %vc
 }
 
 define <vscale x 8 x i1> @icmp_ugt_xv_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {
 ; CHECK-LABEL: icmp_ugt_xv_nxv8i32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
-; CHECK-NEXT:    vmv.v.x v12, a0
-; CHECK-NEXT:    vmsltu.vv v0, v8, v12
+; CHECK-NEXT:    vmsltu.vx v0, v8, a0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
   %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
   %vc = icmp ugt <vscale x 8 x i32> %splat, %va
   ret <vscale x 8 x i1> %vc
 }
 
 define <vscale x 8 x i1> @icmp_ugt_vi_nxv8i32_0(<vscale x 8 x i32> %va) {
; CHECK-NEXT:    ret
   %vc = icmp uge <vscale x 8 x i32> %va, %splat
   ret <vscale x 8 x i1> %vc
 }
 
 define <vscale x 8 x i1> @icmp_uge_xv_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {
 ; CHECK-LABEL: icmp_uge_xv_nxv8i32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
-; CHECK-NEXT:    vmv.v.x v12, a0
-; CHECK-NEXT:    vmsleu.vv v0, v8, v12
+; CHECK-NEXT:    vmsleu.vx v0, v8, a0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
   %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
   %vc = icmp uge <vscale x 8 x i32> %splat, %va
   ret <vscale x 8 x i1> %vc
 }
 
 define <vscale x 8 x i1> @icmp_uge_vi_nxv8i32_0(<vscale x 8 x i32> %va) {
; CHECK-NEXT:    ret
   %vc = icmp ult <vscale x 8 x i32> %va, %splat
   ret <vscale x 8 x i1> %vc
 }
 
 define <vscale x 8 x i1> @icmp_ult_xv_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {
 ; CHECK-LABEL: icmp_ult_xv_nxv8i32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
-; CHECK-NEXT:    vmv.v.x v12, a0
-; CHECK-NEXT:    vmsltu.vv v0, v12, v8
+; CHECK-NEXT:    vmsgtu.vx v0, v8, a0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
   %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
   %vc = icmp ult <vscale x 8 x i32> %splat, %va
   ret <vscale x 8 x i1> %vc
 }
 
 define <vscale x 8 x i1> @icmp_ult_vi_nxv8i32_0(<vscale x 8 x i32> %va) {
; CHECK-NEXT:    ret
   %vc = icmp sgt <vscale x 8 x i32> %va, %splat
   ret <vscale x 8 x i1> %vc
 }
 
 define <vscale x 8 x i1> @icmp_sgt_xv_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {
 ; CHECK-LABEL: icmp_sgt_xv_nxv8i32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
-; CHECK-NEXT:    vmv.v.x v12, a0
-; CHECK-NEXT:    vmslt.vv v0, v8, v12
+; CHECK-NEXT:    vmslt.vx v0, v8, a0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
   %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
   %vc = icmp sgt <vscale x 8 x i32> %splat, %va
   ret <vscale x 8 x i1> %vc
 }
 
 define <vscale x 8 x i1> @icmp_sgt_vi_nxv8i32_0(<vscale x 8 x i32> %va) {
; CHECK-NEXT:    ret
   %vc = icmp sge <vscale x 8 x i32> %va, %splat
   ret <vscale x 8 x i1> %vc
 }
 
 define <vscale x 8 x i1> @icmp_sge_xv_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {
 ; CHECK-LABEL: icmp_sge_xv_nxv8i32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
-; CHECK-NEXT:    vmv.v.x v12, a0
-; CHECK-NEXT:    vmsle.vv v0, v8, v12
+; CHECK-NEXT:    vmsle.vx v0, v8, a0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
   %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
   %vc = icmp sge <vscale x 8 x i32> %splat, %va
   ret <vscale x 8 x i1> %vc
 }
 
 define <vscale x 8 x i1> @icmp_sge_vi_nxv8i32_0(<vscale x 8 x i32> %va) {
; CHECK-NEXT:    ret
   %vc = icmp slt <vscale x 8 x i32> %va, %splat
   ret <vscale x 8 x i1> %vc
 }
 
 define <vscale x 8 x i1> @icmp_slt_xv_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {
 ; CHECK-LABEL: icmp_slt_xv_nxv8i32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
-; CHECK-NEXT:    vmv.v.x v12, a0
-; CHECK-NEXT:    vmslt.vv v0, v12, v8
+; CHECK-NEXT:    vmsgt.vx v0, v8, a0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
   %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
   %vc = icmp slt <vscale x 8 x i32> %splat, %va
   ret <vscale x 8 x i1> %vc
 }
 
 define <vscale x 8 x i1> @icmp_slt_vi_nxv8i32_0(<vscale x 8 x i32> %va) {

 ; RV32-NEXT:    vlse64.v v16, (a0), zero
 ; RV32-NEXT:    vmseq.vv v0, v16, v8
 ; RV32-NEXT:    addi sp, sp, 16
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: icmp_eq_xv_nxv8i64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
-; RV64-NEXT:    vmv.v.x v16, a0
-; RV64-NEXT:    vmseq.vv v0, v16, v8
+; RV64-NEXT:    vmseq.vx v0, v8, a0
 ; RV64-NEXT:    ret
   %head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
   %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
   %vc = icmp eq <vscale x 8 x i64> %splat, %va
   ret <vscale x 8 x i1> %vc
 }
 
 define <vscale x 8 x i1> @icmp_eq_vi_nxv8i64_0(<vscale x 8 x i64> %va) {

 ; RV32-NEXT:    vlse64.v v16, (a0), zero
 ; RV32-NEXT:    vmsne.vv v0, v16, v8
 ; RV32-NEXT:    addi sp, sp, 16
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: icmp_ne_xv_nxv8i64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
-; RV64-NEXT:    vmv.v.x v16, a0
-; RV64-NEXT:    vmsne.vv v0, v16, v8
+; RV64-NEXT:    vmsne.vx v0, v8, a0
 ; RV64-NEXT:    ret
   %head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
   %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
   %vc = icmp ne <vscale x 8 x i64> %splat, %va
   ret <vscale x 8 x i1> %vc
 }
 
 define <vscale x 8 x i1> @icmp_ne_vi_nxv8i64_0(<vscale x 8 x i64> %va) {

 ; RV32-NEXT:    vlse64.v v16, (a0), zero
 ; RV32-NEXT:    vmsltu.vv v0, v8, v16
 ; RV32-NEXT:    addi sp, sp, 16
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: icmp_ugt_xv_nxv8i64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
-; RV64-NEXT:    vmv.v.x v16, a0
-; RV64-NEXT:    vmsltu.vv v0, v8, v16
+; RV64-NEXT:    vmsltu.vx v0, v8, a0
 ; RV64-NEXT:    ret
   %head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
   %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
   %vc = icmp ugt <vscale x 8 x i64> %splat, %va
   ret <vscale x 8 x i1> %vc
 }
 
 define <vscale x 8 x i1> @icmp_ugt_vi_nxv8i64_0(<vscale x 8 x i64> %va) {

 ; RV32-NEXT:    vlse64.v v16, (a0), zero
 ; RV32-NEXT:    vmsleu.vv v0, v8, v16
 ; RV32-NEXT:    addi sp, sp, 16
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: icmp_uge_xv_nxv8i64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
-; RV64-NEXT:    vmv.v.x v16, a0
-; RV64-NEXT:    vmsleu.vv v0, v8, v16
+; RV64-NEXT:    vmsleu.vx v0, v8, a0
 ; RV64-NEXT:    ret
   %head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
   %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
   %vc = icmp uge <vscale x 8 x i64> %splat, %va
   ret <vscale x 8 x i1> %vc
 }
 
 define <vscale x 8 x i1> @icmp_uge_vi_nxv8i64_0(<vscale x 8 x i64> %va) {

 ; RV32-NEXT:    vlse64.v v16, (a0), zero
 ; RV32-NEXT:    vmsltu.vv v0, v16, v8
 ; RV32-NEXT:    addi sp, sp, 16
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: icmp_ult_xv_nxv8i64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
-; RV64-NEXT:    vmv.v.x v16, a0
-; RV64-NEXT:    vmsltu.vv v0, v16, v8
+; RV64-NEXT:    vmsgtu.vx v0, v8, a0
 ; RV64-NEXT:    ret
   %head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
   %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
   %vc = icmp ult <vscale x 8 x i64> %splat, %va
   ret <vscale x 8 x i1> %vc
 }
 
 define <vscale x 8 x i1> @icmp_ult_vi_nxv8i64_0(<vscale x 8 x i64> %va) {

 ; RV32-NEXT:    vlse64.v v16, (a0), zero
 ; RV32-NEXT:    vmslt.vv v0, v8, v16
 ; RV32-NEXT:    addi sp, sp, 16
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: icmp_sgt_xv_nxv8i64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
-; RV64-NEXT:    vmv.v.x v16, a0
-; RV64-NEXT:    vmslt.vv v0, v8, v16
+; RV64-NEXT:    vmslt.vx v0, v8, a0
 ; RV64-NEXT:    ret
   %head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
   %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
   %vc = icmp sgt <vscale x 8 x i64> %splat, %va
   ret <vscale x 8 x i1> %vc
 }
 
 define <vscale x 8 x i1> @icmp_sgt_vi_nxv8i64_0(<vscale x 8 x i64> %va) {

 ; RV32-NEXT:    vlse64.v v16, (a0), zero
 ; RV32-NEXT:    vmsle.vv v0, v8, v16
 ; RV32-NEXT:    addi sp, sp, 16
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: icmp_sge_xv_nxv8i64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
-; RV64-NEXT:    vmv.v.x v16, a0
-; RV64-NEXT:    vmsle.vv v0, v8, v16
+; RV64-NEXT:    vmsle.vx v0, v8, a0
 ; RV64-NEXT:    ret
   %head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
   %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
   %vc = icmp sge <vscale x 8 x i64> %splat, %va
   ret <vscale x 8 x i1> %vc
 }
 
 define <vscale x 8 x i1> @icmp_sge_vi_nxv8i64_0(<vscale x 8 x i64> %va) {

 ; RV32-NEXT:    vlse64.v v16, (a0), zero
 ; RV32-NEXT:    vmslt.vv v0, v16, v8
 ; RV32-NEXT:    addi sp, sp, 16
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: icmp_slt_xv_nxv8i64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
-; RV64-NEXT:    vmv.v.x v16, a0
-; RV64-NEXT:    vmslt.vv v0, v16, v8
+; RV64-NEXT:    vmsgt.vx v0, v8, a0
 ; RV64-NEXT:    ret
   %head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
   %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
   %vc = icmp slt <vscale x 8 x i64> %splat, %va
   ret <vscale x 8 x i1> %vc
 }
 
 define <vscale x 8 x i1> @icmp_slt_vi_nxv8i64_0(<vscale x 8 x i64> %va) {