[AArch64] Refactor shouldExpandAtomicRMWInIR [NFC]

[tmatheson]

Summary

Convert to a sequence of early returns to make the logic easier to follow.

[efriedma]

The logic is basically the following:

1. If we can use LSE, return "none" and let isel lower it.
2. If we can use outlined atomic helpers, return "none" and let SelectionDAG generate the outlined call.
3. If we can use LLSC, use LLSC expansion
4. If we can use cmpxchg, use cmpxchg expansion
5. If we can't use any of the above, we... crash? Really, we shouldn't get here; we should call setMaxAtomicSizeInBitsSupported() and let AtomicExpand handle it.

The proposed refactoring seems to make it harder to understand this.

If you want to separate out "can use LSE" and "can use outlined atomic helpers" into separate functions/lambas, that would be an improvement, I guess.

[tmatheson]

Sorry I forgot to follow this up sooner. Looking at it again I think you are right so will drop this patch.

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

 }
 
 // For the real atomic operations, we have ldxr/stxr up to 128 bits,
 TargetLowering::AtomicExpansionKind
 AArch64TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
   if (AI->isFloatingPointOperation())
     return AtomicExpansionKind::CmpXChg;
 
+  // At -O0, fast-regalloc cannot cope with the live vregs necessary to
+  // implement atomicrmw without spilling. If the target address is also on the
+  // stack and close enough to the spill slot, this can lead to a situation
+  // where the monitor always gets cleared and the atomic operation can never
+  // succeed. So at -O0 lower this operation to a CAS loop.
+  auto OptLevelDefault = getTargetMachine().getOptLevel() == CodeGenOpt::None
+                             ? AtomicExpansionKind::CmpXChg
+                             : AtomicExpansionKind::LLSC;
+
   unsigned Size = AI->getType()->getPrimitiveSizeInBits();
   if (Size > 128) return AtomicExpansionKind::None;
 
-  // Nand is not supported in LSE.
   // Leave 128 bits to LLSC or CmpXChg.
-  if (AI->getOperation() != AtomicRMWInst::Nand && Size < 128) {
-    if (Subtarget->hasLSE())
-      return AtomicExpansionKind::None;
-    if (Subtarget->outlineAtomics()) {
-      // [U]Min/[U]Max RWM atomics are used in __sync_fetch_ libcalls so far.
-      // Don't outline them unless
-      // (1) high level <atomic> support approved:
-      //   http://www.open-std.org/jtc1/sc22/wg21/docs/papers/2020/p0493r1.pdf
-      // (2) low level libgcc and compiler-rt support implemented by:
-      //   min/max outline atomics helpers
-      if (AI->getOperation() != AtomicRMWInst::Min &&
-          AI->getOperation() != AtomicRMWInst::Max &&
-          AI->getOperation() != AtomicRMWInst::UMin &&
-          AI->getOperation() != AtomicRMWInst::UMax) {
-        return AtomicExpansionKind::None;
-      }
+  if (Size == 128)
+    return OptLevelDefault;
+
+  // Nand is not supported in LSE.
+  if (AI->getOperation() == AtomicRMWInst::Nand)
+    return OptLevelDefault;
+
+  if (Subtarget->hasLSE()) {
+    assert(AI->getOperation() != AtomicRMWInst::Nand);
+    assert(Size < 128);
+  }
+
+    assert(AI->getOperation() != AtomicRMWInst::Nand);
+    assert(Size < 128);
+    assert(!Subtarget->hasLSE());
+    if (AI->getOperation() == AtomicRMWInst::Min ||
+        AI->getOperation() == AtomicRMWInst::Max ||
+        AI->getOperation() == AtomicRMWInst::UMin ||
+        AI->getOperation() == AtomicRMWInst::UMax) {
+      return OptLevelDefault;
     }
+    return AtomicExpansionKind::None;
   }
 
-  // At -O0, fast-regalloc cannot cope with the live vregs necessary to
-  // implement atomicrmw without spilling. If the target address is also on the
-  // stack and close enough to the spill slot, this can lead to a situation
-  // where the monitor always gets cleared and the atomic operation can never
-  // succeed. So at -O0 lower this operation to a CAS loop.
-  if (getTargetMachine().getOptLevel() == CodeGenOpt::None)
-    return AtomicExpansionKind::CmpXChg;
-
-  return AtomicExpansionKind::LLSC;
+  return OptLevelDefault;
 }
 
 TargetLowering::AtomicExpansionKind
 AArch64TargetLowering::shouldExpandAtomicCmpXchgInIR(
     AtomicCmpXchgInst *AI) const {
   // If subtarget has LSE, leave cmpxchg intact for codegen.
   if (Subtarget->hasLSE() || Subtarget->outlineAtomics())
     return AtomicExpansionKind::None;