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Differential D122651

[RISCV] [NFC] Add immediate version of the test for icmp Instruction
ClosedPublic

Authored by Miss_Grape on Mar 29 2022, 6:13 AM.

Details

Reviewers
craig.topper
benshi001
Commits
rG7f817658980e: [RISCV][NFC] Add immediate tests for the icmp instruction

Diff Detail

Event Timeline

Miss_Grape created this revision.Mar 29 2022, 6:13 AM
Herald added a project: Restricted Project. · View Herald TranscriptMar 29 2022, 6:13 AM
Herald added subscribers: sunshaoce, VincentWu, luke957 and 28 others. · View Herald Transcript
Miss_Grape requested review of this revision.Mar 29 2022, 6:13 AM
Herald added a project: Restricted Project. · View Herald TranscriptMar 29 2022, 6:13 AM
Herald added subscribers: llvm-commits, • pcwang-thead, eopXD and 2 others. · View Herald Transcript
craig.topper added inline comments.Mar 29 2022, 10:19 AM
llvm/test/CodeGen/RISCV/i32-icmp.ll
677

Why is there an extra underscore on the end of this test name?

llvm/test/CodeGen/RISCV/i64-icmp.ll
695

Same here

craig.topper accepted this revision.Mar 29 2022, 3:06 PM

LGTM if you remove those extra underscores in my other comments.

This revision is now accepted and ready to land.Mar 29 2022, 3:06 PM
Miss_Grape updated this revision to Diff 419033.Mar 29 2022, 6:57 PM

Updata tests

llvm/test/CodeGen/RISCV/i32-icmp.ll
677

removed extra underscore

llvm/test/CodeGen/RISCV/i64-icmp.ll
695

done

Miss_Grape updated this revision to Diff 419035.Mar 29 2022, 7:00 PM
This revision was landed with ongoing or failed builds.Mar 29 2022, 8:04 PM
Closed by commit rG7f817658980e: [RISCV][NFC] Add immediate tests for the icmp instruction (authored by Miss_Grape, committed by benshi001). · Explain Why
This revision was automatically updated to reflect the committed changes.
benshi001 added a commit: rG7f817658980e: [RISCV][NFC] Add immediate tests for the icmp instruction.
Herald added a subscriber: hiraditya. · View Herald TranscriptMar 29 2022, 8:04 PM
Harbormaster completed remote builds in B156875: Diff 419035.Mar 30 2022, 1:04 PM

Revision Contents

PathSize
llvm/
test/
CodeGen/
RISCV/
377 lines
701 lines

Diff 419033

llvm/test/CodeGen/RISCV/i32-icmp.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV32I ; RUN: | FileCheck %s -check-prefix=RV32I
; TODO: check the generated instructions for the equivalent of seqz, snez,
; sltz, sgtz map to something simple
define i32 @icmp_eq(i32 %a, i32 %b) nounwind { define i32 @icmp_eq(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: icmp_eq: ; RV32I-LABEL: icmp_eq:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: xor a0, a0, a1 ; RV32I-NEXT: xor a0, a0, a1
; RV32I-NEXT: seqz a0, a0 ; RV32I-NEXT: seqz a0, a0
; RV32I-NEXT: ret ; RV32I-NEXT: ret
%1 = icmp eq i32 %a, %b %1 = icmp eq i32 %a, %b
%2 = zext i1 %1 to i32 %2 = zext i1 %1 to i32
ret i32 %2 ret i32 %2
} }
define i32 @icmp_eq_constant(i32 %a) nounwind { define i32 @icmp_eq_constant(i32 %a) nounwind {
; RV32I-LABEL: icmp_eq_constant: ; RV32I-LABEL: icmp_eq_constant:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi a0, a0, -42 ; RV32I-NEXT: addi a0, a0, -42
; RV32I-NEXT: seqz a0, a0 ; RV32I-NEXT: seqz a0, a0
; RV32I-NEXT: ret ; RV32I-NEXT: ret
%1 = icmp eq i32 %a, 42 %1 = icmp eq i32 %a, 42
%2 = zext i1 %1 to i32 %2 = zext i1 %1 to i32
ret i32 %2 ret i32 %2
} }
define i32 @icmp_eq_constant_2049(i32 %a) nounwind {
; RV32I-LABEL: icmp_eq_constant_2049:
; RV32I: # %bb.0:
; RV32I-NEXT: lui a1, 1
; RV32I-NEXT: addi a1, a1, -2047
; RV32I-NEXT: xor a0, a0, a1
; RV32I-NEXT: seqz a0, a0
; RV32I-NEXT: ret
%1 = icmp eq i32 %a, 2049
%2 = zext i1 %1 to i32
ret i32 %2
}
define i32 @icmp_eq_constant_2048(i32 %a) nounwind { define i32 @icmp_eq_constant_2048(i32 %a) nounwind {
; RV32I-LABEL: icmp_eq_constant_2048: ; RV32I-LABEL: icmp_eq_constant_2048:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi a0, a0, -2048 ; RV32I-NEXT: addi a0, a0, -2048
; RV32I-NEXT: seqz a0, a0 ; RV32I-NEXT: seqz a0, a0
; RV32I-NEXT: ret ; RV32I-NEXT: ret
%1 = icmp eq i32 %a, 2048 %1 = icmp eq i32 %a, 2048
%2 = zext i1 %1 to i32 %2 = zext i1 %1 to i32
▲ Show 20 Lines • Show All 50 Lines • ▼ Show 20 Lines
; RV32I-NEXT: addi a0, a0, -42 ; RV32I-NEXT: addi a0, a0, -42
; RV32I-NEXT: snez a0, a0 ; RV32I-NEXT: snez a0, a0
; RV32I-NEXT: ret ; RV32I-NEXT: ret
%1 = icmp ne i32 %a, 42 %1 = icmp ne i32 %a, 42
%2 = zext i1 %1 to i32 %2 = zext i1 %1 to i32
ret i32 %2 ret i32 %2
} }
define i32 @icmp_ne_constant_2049(i32 %a) nounwind {
; RV32I-LABEL: icmp_ne_constant_2049:
; RV32I: # %bb.0:
; RV32I-NEXT: lui a1, 1
; RV32I-NEXT: addi a1, a1, -2047
; RV32I-NEXT: xor a0, a0, a1
; RV32I-NEXT: snez a0, a0
; RV32I-NEXT: ret
%1 = icmp ne i32 %a, 2049
%2 = zext i1 %1 to i32
ret i32 %2
}
define i32 @icmp_ne_constant_2048(i32 %a) nounwind { define i32 @icmp_ne_constant_2048(i32 %a) nounwind {
; RV32I-LABEL: icmp_ne_constant_2048: ; RV32I-LABEL: icmp_ne_constant_2048:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi a0, a0, -2048 ; RV32I-NEXT: addi a0, a0, -2048
; RV32I-NEXT: snez a0, a0 ; RV32I-NEXT: snez a0, a0
; RV32I-NEXT: ret ; RV32I-NEXT: ret
%1 = icmp ne i32 %a, 2048 %1 = icmp ne i32 %a, 2048
%2 = zext i1 %1 to i32 %2 = zext i1 %1 to i32
ret i32 %2 ret i32 %2
} }
define i32 @icmp_ne_constant_neg_2048(i32 %a) nounwind { define i32 @icmp_ne_constant_neg_2048(i32 %a) nounwind {
; RV32I-LABEL: icmp_ne_constant_neg_2048: ; RV32I-LABEL: icmp_ne_constant_neg_2048:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: li a1, -2048 ; RV32I-NEXT: li a1, -2048
; RV32I-NEXT: xor a0, a0, a1 ; RV32I-NEXT: xor a0, a0, a1
; RV32I-NEXT: snez a0, a0 ; RV32I-NEXT: snez a0, a0
; RV32I-NEXT: ret ; RV32I-NEXT: ret
%1 = icmp ne i32 %a, -2048 %1 = icmp ne i32 %a, -2048
%2 = zext i1 %1 to i32 %2 = zext i1 %1 to i32
ret i32 %2 ret i32 %2
} }
define i32 @icmp_ne_constant_neg_2047(i32 %a) nounwind {
; RV32I-LABEL: icmp_ne_constant_neg_2047:
; RV32I: # %bb.0:
; RV32I-NEXT: addi a0, a0, 2047
; RV32I-NEXT: snez a0, a0
; RV32I-NEXT: ret
%1 = icmp ne i32 %a, -2047
%2 = zext i1 %1 to i32
ret i32 %2
}
define i32 @icmp_nez(i32 %a) nounwind { define i32 @icmp_nez(i32 %a) nounwind {
; RV32I-LABEL: icmp_nez: ; RV32I-LABEL: icmp_nez:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: snez a0, a0 ; RV32I-NEXT: snez a0, a0
; RV32I-NEXT: ret ; RV32I-NEXT: ret
%1 = icmp ne i32 %a, 0 %1 = icmp ne i32 %a, 0
%2 = zext i1 %1 to i32 %2 = zext i1 %1 to i32
ret i32 %2 ret i32 %2
▲ Show 20 Lines • Show All 72 Lines • ▼ Show 20 Lines
; RV32I-NEXT: sltu a0, a0, a1 ; RV32I-NEXT: sltu a0, a0, a1
; RV32I-NEXT: xori a0, a0, 1 ; RV32I-NEXT: xori a0, a0, 1
; RV32I-NEXT: ret ; RV32I-NEXT: ret
%1 = icmp uge i32 %a, %b %1 = icmp uge i32 %a, %b
%2 = zext i1 %1 to i32 %2 = zext i1 %1 to i32
ret i32 %2 ret i32 %2
} }
define i32 @icmp_uge_constant_zero(i32 %a) nounwind {
; RV32I-LABEL: icmp_uge_constant_zero:
; RV32I: # %bb.0:
; RV32I-NEXT: li a0, 1
; RV32I-NEXT: ret
%1 = icmp uge i32 %a, 0
%2 = zext i1 %1 to i32
ret i32 %2
}
define i32 @icmp_uge_constant_2047(i32 %a) nounwind {
; RV32I-LABEL: icmp_uge_constant_2047:
; RV32I: # %bb.0:
; RV32I-NEXT: sltiu a0, a0, 2047
; RV32I-NEXT: xori a0, a0, 1
; RV32I-NEXT: ret
%1 = icmp uge i32 %a, 2047
%2 = zext i1 %1 to i32
ret i32 %2
}
define i32 @icmp_uge_constant_2048(i32 %a) nounwind {
; RV32I-LABEL: icmp_uge_constant_2048:
; RV32I: # %bb.0:
; RV32I-NEXT: li a1, 2047
; RV32I-NEXT: sltu a0, a1, a0
; RV32I-NEXT: ret
%1 = icmp uge i32 %a, 2048
%2 = zext i1 %1 to i32
ret i32 %2
}
define i32 @icmp_uge_constant_neg_2048(i32 %a) nounwind {
; RV32I-LABEL: icmp_uge_constant_neg_2048:
; RV32I: # %bb.0:
; RV32I-NEXT: sltiu a0, a0, -2048
; RV32I-NEXT: xori a0, a0, 1
; RV32I-NEXT: ret
; 4294965248 signed extend is -2048
%1 = icmp uge i32 %a, 4294965248
%2 = zext i1 %1 to i32
ret i32 %2
}
define i32 @icmp_uge_constant_neg_2049(i32 %a) nounwind {
; RV32I-LABEL: icmp_uge_constant_neg_2049:
; RV32I: # %bb.0:
; RV32I-NEXT: lui a1, 1048575
; RV32I-NEXT: addi a1, a1, 2046
; RV32I-NEXT: sltu a0, a1, a0
; RV32I-NEXT: ret
; 4294965247 signed extend is -2049
%1 = icmp uge i32 %a, 4294965247
%2 = zext i1 %1 to i32
ret i32 %2
}
define i32 @icmp_ult(i32 %a, i32 %b) nounwind { define i32 @icmp_ult(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: icmp_ult: ; RV32I-LABEL: icmp_ult:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: sltu a0, a0, a1 ; RV32I-NEXT: sltu a0, a0, a1
; RV32I-NEXT: ret ; RV32I-NEXT: ret
%1 = icmp ult i32 %a, %b %1 = icmp ult i32 %a, %b
%2 = zext i1 %1 to i32 %2 = zext i1 %1 to i32
ret i32 %2 ret i32 %2
} }
define i32 @icmp_ult_constant_zero(i32 %a) nounwind {
; RV32I-LABEL: icmp_ult_constant_zero:
; RV32I: # %bb.0:
; RV32I-NEXT: li a0, 0
; RV32I-NEXT: ret
%1 = icmp ult i32 %a, 0
%2 = zext i1 %1 to i32
ret i32 %2
}
define i32 @icmp_ult_constant_2047(i32 %a) nounwind {
; RV32I-LABEL: icmp_ult_constant_2047:
; RV32I: # %bb.0:
; RV32I-NEXT: sltiu a0, a0, 2047
; RV32I-NEXT: ret
%1 = icmp ult i32 %a, 2047
%2 = zext i1 %1 to i32
ret i32 %2
}
define i32 @icmp_ult_constant_2048(i32 %a) nounwind {
; RV32I-LABEL: icmp_ult_constant_2048:
; RV32I: # %bb.0:
; RV32I-NEXT: srli a0, a0, 11
; RV32I-NEXT: seqz a0, a0
; RV32I-NEXT: ret
%1 = icmp ult i32 %a, 2048
%2 = zext i1 %1 to i32
ret i32 %2
}
define i32 @icmp_ult_constant_neg_2048(i32 %a) nounwind {
; RV32I-LABEL: icmp_ult_constant_neg_2048:
; RV32I: # %bb.0:
; RV32I-NEXT: sltiu a0, a0, -2048
; RV32I-NEXT: ret
; 4294965248 signed extend is -2048
%1 = icmp ult i32 %a, 4294965248
%2 = zext i1 %1 to i32
ret i32 %2
}
define i32 @icmp_ult_constant_neg_2049(i32 %a) nounwind {
; RV32I-LABEL: icmp_ult_constant_neg_2049:
; RV32I: # %bb.0:
; RV32I-NEXT: lui a1, 1048575
; RV32I-NEXT: addi a1, a1, 2047
; RV32I-NEXT: sltu a0, a0, a1
; RV32I-NEXT: ret
; 4294965247 signed extend is -2049
%1 = icmp ult i32 %a, 4294965247
%2 = zext i1 %1 to i32
ret i32 %2
}
define i32 @icmp_ule(i32 %a, i32 %b) nounwind { define i32 @icmp_ule(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: icmp_ule: ; RV32I-LABEL: icmp_ule:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: sltu a0, a1, a0 ; RV32I-NEXT: sltu a0, a1, a0
; RV32I-NEXT: xori a0, a0, 1 ; RV32I-NEXT: xori a0, a0, 1
; RV32I-NEXT: ret ; RV32I-NEXT: ret
%1 = icmp ule i32 %a, %b %1 = icmp ule i32 %a, %b
%2 = zext i1 %1 to i32 %2 = zext i1 %1 to i32
ret i32 %2 ret i32 %2
} }
define i32 @icmp_sgt(i32 %a, i32 %b) nounwind { define i32 @icmp_ule_constant_zero(i32 %a) nounwind {
; RV32I-LABEL: icmp_sgt: ; RV32I-LABEL: icmp_ule_constant_zero:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: slt a0, a1, a0 ; RV32I-NEXT: seqz a0, a0
; RV32I-NEXT: ret ; RV32I-NEXT: ret
%1 = icmp sgt i32 %a, %b %1 = icmp ule i32 %a, 0
%2 = zext i1 %1 to i32 %2 = zext i1 %1 to i32
ret i32 %2 ret i32 %2
} }
define i32 @icmp_sgt_constant(i32 %a) nounwind { define i32 @icmp_ule_constant_2046(i32 %a) nounwind {
; RV32I-LABEL: icmp_sgt_constant: ; RV32I-LABEL: icmp_ule_constant_2046:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: slti a0, a0, 6 ; RV32I-NEXT: sltiu a0, a0, 2047
; RV32I-NEXT: xori a0, a0, 1 ; RV32I-NEXT: ret
%1 = icmp ule i32 %a, 2046
%2 = zext i1 %1 to i32
ret i32 %2
}
define i32 @icmp_ule_constant_2047(i32 %a) nounwind {
; RV32I-LABEL: icmp_ule_constant_2047:
; RV32I: # %bb.0:
; RV32I-NEXT: srli a0, a0, 11
; RV32I-NEXT: seqz a0, a0
; RV32I-NEXT: ret
%1 = icmp ule i32 %a, 2047
%2 = zext i1 %1 to i32
ret i32 %2
}
define i32 @icmp_ule_constant_neg_2049(i32 %a) nounwind {
; RV32I-LABEL: icmp_ule_constant_neg_2049:
; RV32I: # %bb.0:
; RV32I-NEXT: sltiu a0, a0, -2048
; RV32I-NEXT: ret
; 4294965247 signed extend is -2049
%1 = icmp ule i32 %a, 4294965247
%2 = zext i1 %1 to i32
ret i32 %2
}
define i32 @icmp_ule_constant_neg_2050(i32 %a) nounwind {
; RV32I-LABEL: icmp_ule_constant_neg_2050:
; RV32I: # %bb.0:
; RV32I-NEXT: lui a1, 1048575
; RV32I-NEXT: addi a1, a1, 2047
; RV32I-NEXT: sltu a0, a0, a1
; RV32I-NEXT: ret ; RV32I-NEXT: ret
%1 = icmp sgt i32 %a, 5 ; 4294965246 signed extend is -2050
%1 = icmp ule i32 %a, 4294965246
%2 = zext i1 %1 to i32
ret i32 %2
}
define i32 @icmp_sgt(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: icmp_sgt:
; RV32I: # %bb.0:
; RV32I-NEXT: slt a0, a1, a0
; RV32I-NEXT: ret
%1 = icmp sgt i32 %a, %b
%2 = zext i1 %1 to i32 %2 = zext i1 %1 to i32
ret i32 %2 ret i32 %2
} }
define i32 @icmp_sgt_constant_zero(i32 %a) nounwind { define i32 @icmp_sgt_constant_zero(i32 %a) nounwind {
; RV32I-LABEL: icmp_sgt_constant_zero: ; RV32I-LABEL: icmp_sgt_constant_zero:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: sgtz a0, a0 ; RV32I-NEXT: sgtz a0, a0
▲ Show 20 Lines • Show All 54 Lines • ▼ Show 20 Lines
; RV32I-NEXT: slt a0, a0, a1 ; RV32I-NEXT: slt a0, a0, a1
; RV32I-NEXT: xori a0, a0, 1 ; RV32I-NEXT: xori a0, a0, 1
; RV32I-NEXT: ret ; RV32I-NEXT: ret
%1 = icmp sge i32 %a, %b %1 = icmp sge i32 %a, %b
%2 = zext i1 %1 to i32 %2 = zext i1 %1 to i32
ret i32 %2 ret i32 %2
} }
define i32 @icmp_sge_constant_zero(i32 %a) nounwind {
; RV32I-LABEL: icmp_sge_constant_zero:
; RV32I: # %bb.0:
; RV32I-NEXT: not a0, a0
; RV32I-NEXT: srli a0, a0, 31
; RV32I-NEXT: ret
%1 = icmp sge i32 %a, 0
%2 = zext i1 %1 to i32
ret i32 %2
}
define i32 @icmp_sge_constant_2047(i32 %a) nounwind {
; RV32I-LABEL: icmp_sge_constant_2047:
; RV32I: # %bb.0:
; RV32I-NEXT: slti a0, a0, 2047
; RV32I-NEXT: xori a0, a0, 1
; RV32I-NEXT: ret
%1 = icmp sge i32 %a, 2047
%2 = zext i1 %1 to i32
ret i32 %2
}
define i32 @icmp_sge_constant_2048(i32 %a) nounwind {
; RV32I-LABEL: icmp_sge_constant_2048:
; RV32I: # %bb.0:
; RV32I-NEXT: li a1, 2047
; RV32I-NEXT: slt a0, a1, a0
; RV32I-NEXT: ret
%1 = icmp sge i32 %a, 2048
%2 = zext i1 %1 to i32
ret i32 %2
}
define i32 @icmp_sge_constant_neg_2047(i32 %a) nounwind {
; RV32I-LABEL: icmp_sge_constant_neg_2047:
; RV32I: # %bb.0:
; RV32I-NEXT: slti a0, a0, -2047
; RV32I-NEXT: xori a0, a0, 1
; RV32I-NEXT: ret
%1 = icmp sge i32 %a, -2047
%2 = zext i1 %1 to i32
ret i32 %2
}
define i32 @icmp_sge_constant_neg_2048(i32 %a) nounwind {
; RV32I-LABEL: icmp_sge_constant_neg_2048:
; RV32I: # %bb.0:
; RV32I-NEXT: not a0, a0
; RV32I-NEXT: srli a0, a0, 31
; RV32I-NEXT: ret
%1 = icmp sge i32 %a, 0
%2 = zext i1 %1 to i32
ret i32 %2
}
define i32 @icmp_slt(i32 %a, i32 %b) nounwind { define i32 @icmp_slt(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: icmp_slt: ; RV32I-LABEL: icmp_slt:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: slt a0, a0, a1 ; RV32I-NEXT: slt a0, a0, a1
; RV32I-NEXT: ret ; RV32I-NEXT: ret
%1 = icmp slt i32 %a, %b %1 = icmp slt i32 %a, %b
%2 = zext i1 %1 to i32 %2 = zext i1 %1 to i32
ret i32 %2 ret i32 %2
} }
define i32 @icmp_slt_constant_zero(i32 %a) nounwind {
; RV32I-LABEL: icmp_slt_constant_zero:
; RV32I: # %bb.0:
; RV32I-NEXT: srli a0, a0, 31
; RV32I-NEXT: ret
%1 = icmp slt i32 %a, 0
%2 = zext i1 %1 to i32
ret i32 %2
}
define i32 @icmp_slt_constant_2047(i32 %a) nounwind {
; RV32I-LABEL: icmp_slt_constant_2047:
; RV32I: # %bb.0:
; RV32I-NEXT: slti a0, a0, 2047
; RV32I-NEXT: ret
%1 = icmp slt i32 %a, 2047
%2 = zext i1 %1 to i32
ret i32 %2
}
define i32 @icmp_slt_constant_2048(i32 %a) nounwind {
; RV32I-LABEL: icmp_slt_constant_2048:
; RV32I: # %bb.0:
; RV32I-NEXT: lui a1, 1
; RV32I-NEXT: addi a1, a1, -2048
; RV32I-NEXT: slt a0, a0, a1
; RV32I-NEXT: ret
%1 = icmp slt i32 %a, 2048
%2 = zext i1 %1 to i32
ret i32 %2
}
define i32 @icmp_slt_constant_neg_2048(i32 %a) nounwind {
; RV32I-LABEL: icmp_slt_constant_neg_2048:
; RV32I: # %bb.0:
; RV32I-NEXT: slti a0, a0, -2048
; RV32I-NEXT: ret
%1 = icmp slt i32 %a, -2048
%2 = zext i1 %1 to i32
ret i32 %2
}
define i32 @icmp_slt_constant_neg_2049(i32 %a) nounwind {
; RV32I-LABEL: icmp_slt_constant_neg_2049:
; RV32I: # %bb.0:
; RV32I-NEXT: lui a1, 1048575
; RV32I-NEXT: addi a1, a1, 2047
; RV32I-NEXT: slt a0, a0, a1
; RV32I-NEXT: ret
%1 = icmp slt i32 %a, -2049
%2 = zext i1 %1 to i32
ret i32 %2
}
define i32 @icmp_sle(i32 %a, i32 %b) nounwind { define i32 @icmp_sle(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: icmp_sle: ; RV32I-LABEL: icmp_sle:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: slt a0, a1, a0 ; RV32I-NEXT: slt a0, a1, a0
; RV32I-NEXT: xori a0, a0, 1 ; RV32I-NEXT: xori a0, a0, 1
; RV32I-NEXT: ret ; RV32I-NEXT: ret
%1 = icmp sle i32 %a, %b %1 = icmp sle i32 %a, %b
%2 = zext i1 %1 to i32 %2 = zext i1 %1 to i32
ret i32 %2 ret i32 %2
} }
; TODO: check variants with an immediate? define i32 @icmp_sle_constant_zero(i32 %a) nounwind {
; RV32I-LABEL: icmp_sle_constant_zero:
; RV32I: # %bb.0:
; RV32I-NEXT: slti a0, a0, 1
; RV32I-NEXT: ret
%1 = icmp sle i32 %a, 0
%2 = zext i1 %1 to i32
ret i32 %2
}
define i32 @icmp_sle_constant_2046(i32 %a) nounwind {
; RV32I-LABEL: icmp_sle_constant_2046:
; RV32I: # %bb.0:
; RV32I-NEXT: slti a0, a0, 2047
; RV32I-NEXT: ret
%1 = icmp sle i32 %a, 2046
%2 = zext i1 %1 to i32
ret i32 %2
}
define i32 @icmp_sle_constant_2047(i32 %a) nounwind {
; RV32I-LABEL: icmp_sle_constant_2047:
; RV32I: # %bb.0:
; RV32I-NEXT: lui a1, 1
; RV32I-NEXT: addi a1, a1, -2048
; RV32I-NEXT: slt a0, a0, a1
; RV32I-NEXT: ret
%1 = icmp sle i32 %a, 2047
%2 = zext i1 %1 to i32
ret i32 %2
}
define i32 @icmp_sle_constant_neg_2049(i32 %a) nounwind {
; RV32I-LABEL: icmp_sle_constant_neg_2049:
; RV32I: # %bb.0:
; RV32I-NEXT: slti a0, a0, -2048
; RV32I-NEXT: ret
%1 = icmp sle i32 %a, -2049
%2 = zext i1 %1 to i32
ret i32 %2
}
define i32 @icmp_sle_constant_neg_2050(i32 %a) nounwind {
craig.topperUnsubmitted
Not Done
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Why is there an extra underscore on the end of this test name?

craig.topper: Why is there an extra underscore on the end of this test name?
Miss_GrapeAuthorUnsubmitted
Done
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removed extra underscore

Miss_Grape: removed extra underscore
; RV32I-LABEL: icmp_sle_constant_neg_2050_:
; RV32I: # %bb.0:
; RV32I-NEXT: lui a1, 1048575
; RV32I-NEXT: addi a1, a1, 2047
; RV32I-NEXT: slt a0, a0, a1
; RV32I-NEXT: ret
%1 = icmp sle i32 %a, -2050
%2 = zext i1 %1 to i32
ret i32 %2
}

llvm/test/CodeGen/RISCV/i64-icmp.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV64I
define i64 @icmp_eq(i64 %a, i64 %b) nounwind {
; RV64I-LABEL: icmp_eq:
; RV64I: # %bb.0:
; RV64I-NEXT: xor a0, a0, a1
; RV64I-NEXT: seqz a0, a0
; RV64I-NEXT: ret
%1 = icmp eq i64 %a, %b
%2 = zext i1 %1 to i64
ret i64 %2
}
define i64 @icmp_eq_constant(i64 %a) nounwind {
; RV64I-LABEL: icmp_eq_constant:
; RV64I: # %bb.0:
; RV64I-NEXT: addi a0, a0, -42
; RV64I-NEXT: seqz a0, a0
; RV64I-NEXT: ret
%1 = icmp eq i64 %a, 42
%2 = zext i1 %1 to i64
ret i64 %2
}
define i64 @icmp_eq_constant_2049(i64 %a) nounwind {
; RV64I-LABEL: icmp_eq_constant_2049:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, 1
; RV64I-NEXT: addiw a1, a1, -2047
; RV64I-NEXT: xor a0, a0, a1
; RV64I-NEXT: seqz a0, a0
; RV64I-NEXT: ret
%1 = icmp eq i64 %a, 2049
%2 = zext i1 %1 to i64
ret i64 %2
}
define i64 @icmp_eq_constant_2048(i64 %a) nounwind {
; RV64I-LABEL: icmp_eq_constant_2048:
; RV64I: # %bb.0:
; RV64I-NEXT: addi a0, a0, -2048
; RV64I-NEXT: seqz a0, a0
; RV64I-NEXT: ret
%1 = icmp eq i64 %a, 2048
%2 = zext i1 %1 to i64
ret i64 %2
}
define i64 @icmp_eq_constant_neg_2048(i64 %a) nounwind {
; RV64I-LABEL: icmp_eq_constant_neg_2048:
; RV64I: # %bb.0:
; RV64I-NEXT: li a1, -2048
; RV64I-NEXT: xor a0, a0, a1
; RV64I-NEXT: seqz a0, a0
; RV64I-NEXT: ret
%1 = icmp eq i64 %a, -2048
%2 = zext i1 %1 to i64
ret i64 %2
}
define i64 @icmp_eq_constant_neg_2047(i64 %a) nounwind {
; RV64I-LABEL: icmp_eq_constant_neg_2047:
; RV64I: # %bb.0:
; RV64I-NEXT: addi a0, a0, 2047
; RV64I-NEXT: seqz a0, a0
; RV64I-NEXT: ret
%1 = icmp eq i64 %a, -2047
%2 = zext i1 %1 to i64
ret i64 %2
}
define i64 @icmp_eqz(i64 %a) nounwind {
; RV64I-LABEL: icmp_eqz:
; RV64I: # %bb.0:
; RV64I-NEXT: seqz a0, a0
; RV64I-NEXT: ret
%1 = icmp eq i64 %a, 0
%2 = zext i1 %1 to i64
ret i64 %2
}
define i64 @icmp_ne(i64 %a, i64 %b) nounwind {
; RV64I-LABEL: icmp_ne:
; RV64I: # %bb.0:
; RV64I-NEXT: xor a0, a0, a1
; RV64I-NEXT: snez a0, a0
; RV64I-NEXT: ret
%1 = icmp ne i64 %a, %b
%2 = zext i1 %1 to i64
ret i64 %2
}
define i64 @icmp_ne_constant(i64 %a) nounwind {
; RV64I-LABEL: icmp_ne_constant:
; RV64I: # %bb.0:
; RV64I-NEXT: addi a0, a0, -42
; RV64I-NEXT: snez a0, a0
; RV64I-NEXT: ret
%1 = icmp ne i64 %a, 42
%2 = zext i1 %1 to i64
ret i64 %2
}
define i64 @icmp_ne_constant_2049(i64 %a) nounwind {
; RV64I-LABEL: icmp_ne_constant_2049:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, 1
; RV64I-NEXT: addiw a1, a1, -2047
; RV64I-NEXT: xor a0, a0, a1
; RV64I-NEXT: snez a0, a0
; RV64I-NEXT: ret
%1 = icmp ne i64 %a, 2049
%2 = zext i1 %1 to i64
ret i64 %2
}
define i64 @icmp_ne_constant_2048(i64 %a) nounwind {
; RV64I-LABEL: icmp_ne_constant_2048:
; RV64I: # %bb.0:
; RV64I-NEXT: addi a0, a0, -2048
; RV64I-NEXT: snez a0, a0
; RV64I-NEXT: ret
%1 = icmp ne i64 %a, 2048
%2 = zext i1 %1 to i64
ret i64 %2
}
define i64 @icmp_ne_constant_neg_2048(i64 %a) nounwind {
; RV64I-LABEL: icmp_ne_constant_neg_2048:
; RV64I: # %bb.0:
; RV64I-NEXT: li a1, -2048
; RV64I-NEXT: xor a0, a0, a1
; RV64I-NEXT: snez a0, a0
; RV64I-NEXT: ret
%1 = icmp ne i64 %a, -2048
%2 = zext i1 %1 to i64
ret i64 %2
}
define i64 @icmp_ne_constant_neg_2047(i64 %a) nounwind {
; RV64I-LABEL: icmp_ne_constant_neg_2047:
; RV64I: # %bb.0:
; RV64I-NEXT: addi a0, a0, 2047
; RV64I-NEXT: snez a0, a0
; RV64I-NEXT: ret
%1 = icmp ne i64 %a, -2047
%2 = zext i1 %1 to i64
ret i64 %2
}
define i64 @icmp_nez(i64 %a) nounwind {
; RV64I-LABEL: icmp_nez:
; RV64I: # %bb.0:
; RV64I-NEXT: snez a0, a0
; RV64I-NEXT: ret
%1 = icmp ne i64 %a, 0
%2 = zext i1 %1 to i64
ret i64 %2
}
define i64 @icmp_ugt(i64 %a, i64 %b) nounwind {
; RV64I-LABEL: icmp_ugt:
; RV64I: # %bb.0:
; RV64I-NEXT: sltu a0, a1, a0
; RV64I-NEXT: ret
%1 = icmp ugt i64 %a, %b
%2 = zext i1 %1 to i64
ret i64 %2
}
define i64 @icmp_ugt_constant_zero(i64 %a) nounwind {
; RV64I-LABEL: icmp_ugt_constant_zero:
; RV64I: # %bb.0:
; RV64I-NEXT: snez a0, a0
; RV64I-NEXT: ret
%1 = icmp ugt i64 %a, 0
%2 = zext i1 %1 to i64
ret i64 %2
}
define i64 @icmp_ugt_constant_2047(i64 %a) nounwind {
; RV64I-LABEL: icmp_ugt_constant_2047:
; RV64I: # %bb.0:
; RV64I-NEXT: li a1, 2047
; RV64I-NEXT: sltu a0, a1, a0
; RV64I-NEXT: ret
%1 = icmp ugt i64 %a, 2047
%2 = zext i1 %1 to i64
ret i64 %2
}
define i64 @icmp_ugt_constant_2046(i64 %a) nounwind {
; RV64I-LABEL: icmp_ugt_constant_2046:
; RV64I: # %bb.0:
; RV64I-NEXT: sltiu a0, a0, 2047
; RV64I-NEXT: xori a0, a0, 1
; RV64I-NEXT: ret
%1 = icmp ugt i64 %a, 2046
%2 = zext i1 %1 to i64
ret i64 %2
}
define i64 @icmp_ugt_constant_neg_2049(i64 %a) nounwind {
; RV64I-LABEL: icmp_ugt_constant_neg_2049:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, 1046527
; RV64I-NEXT: slli a1, a1, 20
; RV64I-NEXT: srli a1, a1, 32
; RV64I-NEXT: sltu a0, a1, a0
; RV64I-NEXT: ret
; 4294965247 signed extend is -2049
%1 = icmp ugt i64 %a, 4294965247
%2 = zext i1 %1 to i64
ret i64 %2
}
define i64 @icmp_ugt_constant_neg_2050(i64 %a) nounwind {
; RV64I-LABEL: icmp_ugt_constant_neg_2050:
; RV64I: # %bb.0:
; RV64I-NEXT: li a1, -1025
; RV64I-NEXT: slli a1, a1, 33
; RV64I-NEXT: srli a1, a1, 32
; RV64I-NEXT: sltu a0, a1, a0
; RV64I-NEXT: ret
; 4294965246 signed extend is -2050
%1 = icmp ugt i64 %a, 4294965246
%2 = zext i1 %1 to i64
ret i64 %2
}
define i64 @icmp_uge(i64 %a, i64 %b) nounwind {
; RV64I-LABEL: icmp_uge:
; RV64I: # %bb.0:
; RV64I-NEXT: sltu a0, a0, a1
; RV64I-NEXT: xori a0, a0, 1
; RV64I-NEXT: ret
%1 = icmp uge i64 %a, %b
%2 = zext i1 %1 to i64
ret i64 %2
}
define i64 @icmp_uge_constant_zero(i64 %a) nounwind {
; RV64I-LABEL: icmp_uge_constant_zero:
; RV64I: # %bb.0:
; RV64I-NEXT: li a0, 1
; RV64I-NEXT: ret
%1 = icmp uge i64 %a, 0
%2 = zext i1 %1 to i64
ret i64 %2
}
define i64 @icmp_uge_constant_2047(i64 %a) nounwind {
; RV64I-LABEL: icmp_uge_constant_2047:
; RV64I: # %bb.0:
; RV64I-NEXT: sltiu a0, a0, 2047
; RV64I-NEXT: xori a0, a0, 1
; RV64I-NEXT: ret
%1 = icmp uge i64 %a, 2047
%2 = zext i1 %1 to i64
ret i64 %2
}
define i64 @icmp_uge_constant_2048(i64 %a) nounwind {
; RV64I-LABEL: icmp_uge_constant_2048:
; RV64I: # %bb.0:
; RV64I-NEXT: li a1, 2047
; RV64I-NEXT: sltu a0, a1, a0
; RV64I-NEXT: ret
%1 = icmp uge i64 %a, 2048
%2 = zext i1 %1 to i64
ret i64 %2
}
define i64 @icmp_uge_constant_neg_2048(i64 %a) nounwind {
; RV64I-LABEL: icmp_uge_constant_neg_2048:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, 1046527
; RV64I-NEXT: slli a1, a1, 20
; RV64I-NEXT: srli a1, a1, 32
; RV64I-NEXT: sltu a0, a1, a0
; RV64I-NEXT: ret
; 4294965248 signed extend is -2048
%1 = icmp uge i64 %a, 4294965248
%2 = zext i1 %1 to i64
ret i64 %2
}
define i64 @icmp_uge_constant_neg_2049(i64 %a) nounwind {
; RV64I-LABEL: icmp_uge_constant_neg_2049:
; RV64I: # %bb.0:
; RV64I-NEXT: li a1, -1025
; RV64I-NEXT: slli a1, a1, 33
; RV64I-NEXT: srli a1, a1, 32
; RV64I-NEXT: sltu a0, a1, a0
; RV64I-NEXT: ret
; 4294965247 signed extend is -2049
%1 = icmp uge i64 %a, 4294965247
%2 = zext i1 %1 to i64
ret i64 %2
}
define i64 @icmp_ult(i64 %a, i64 %b) nounwind {
; RV64I-LABEL: icmp_ult:
; RV64I: # %bb.0:
; RV64I-NEXT: sltu a0, a0, a1
; RV64I-NEXT: ret
%1 = icmp ult i64 %a, %b
%2 = zext i1 %1 to i64
ret i64 %2
}
define i64 @icmp_ult_constant_zero(i64 %a) nounwind {
; RV64I-LABEL: icmp_ult_constant_zero:
; RV64I: # %bb.0:
; RV64I-NEXT: li a0, 0
; RV64I-NEXT: ret
%1 = icmp ult i64 %a, 0
%2 = zext i1 %1 to i64
ret i64 %2
}
define i64 @icmp_ult_constant_2047(i64 %a) nounwind {
; RV64I-LABEL: icmp_ult_constant_2047:
; RV64I: # %bb.0:
; RV64I-NEXT: sltiu a0, a0, 2047
; RV64I-NEXT: ret
%1 = icmp ult i64 %a, 2047
%2 = zext i1 %1 to i64
ret i64 %2
}
define i64 @icmp_ult_constant_2048(i64 %a) nounwind {
; RV64I-LABEL: icmp_ult_constant_2048:
; RV64I: # %bb.0:
; RV64I-NEXT: srli a0, a0, 11
; RV64I-NEXT: seqz a0, a0
; RV64I-NEXT: ret
%1 = icmp ult i64 %a, 2048
%2 = zext i1 %1 to i64
ret i64 %2
}
define i64 @icmp_ult_constant_neg_2048(i64 %a) nounwind {
; RV64I-LABEL: icmp_ult_constant_neg_2048:
; RV64I: # %bb.0:
; RV64I-NEXT: li a1, 1
; RV64I-NEXT: slli a1, a1, 32
; RV64I-NEXT: addi a1, a1, -2048
; RV64I-NEXT: sltu a0, a0, a1
; RV64I-NEXT: ret
; 4294965248 signed extend is -2048
%1 = icmp ult i64 %a, 4294965248
%2 = zext i1 %1 to i64
ret i64 %2
}
define i64 @icmp_ult_constant_neg_2049(i64 %a) nounwind {
; RV64I-LABEL: icmp_ult_constant_neg_2049:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, 1046527
; RV64I-NEXT: slli a1, a1, 20
; RV64I-NEXT: srli a1, a1, 32
; RV64I-NEXT: sltu a0, a0, a1
; RV64I-NEXT: ret
; 4294965247 signed extend is -2049
%1 = icmp ult i64 %a, 4294965247
%2 = zext i1 %1 to i64
ret i64 %2
}
define i64 @icmp_ule(i64 %a, i64 %b) nounwind {
; RV64I-LABEL: icmp_ule:
; RV64I: # %bb.0:
; RV64I-NEXT: sltu a0, a1, a0
; RV64I-NEXT: xori a0, a0, 1
; RV64I-NEXT: ret
%1 = icmp ule i64 %a, %b
%2 = zext i1 %1 to i64
ret i64 %2
}
define i64 @icmp_ule_constant_zero(i64 %a) nounwind {
; RV64I-LABEL: icmp_ule_constant_zero:
; RV64I: # %bb.0:
; RV64I-NEXT: seqz a0, a0
; RV64I-NEXT: ret
%1 = icmp ule i64 %a, 0
%2 = zext i1 %1 to i64
ret i64 %2
}
define i64 @icmp_ule_constant_2046(i64 %a) nounwind {
; RV64I-LABEL: icmp_ule_constant_2046:
; RV64I: # %bb.0:
; RV64I-NEXT: sltiu a0, a0, 2047
; RV64I-NEXT: ret
%1 = icmp ule i64 %a, 2046
%2 = zext i1 %1 to i64
ret i64 %2
}
define i64 @icmp_ule_constant_2047(i64 %a) nounwind {
; RV64I-LABEL: icmp_ule_constant_2047:
; RV64I: # %bb.0:
; RV64I-NEXT: srli a0, a0, 11
; RV64I-NEXT: seqz a0, a0
; RV64I-NEXT: ret
%1 = icmp ule i64 %a, 2047
%2 = zext i1 %1 to i64
ret i64 %2
}
define i64 @icmp_ule_constant_neg_2049(i64 %a) nounwind {
; RV64I-LABEL: icmp_ule_constant_neg_2049:
; RV64I: # %bb.0:
; RV64I-NEXT: li a1, 1
; RV64I-NEXT: slli a1, a1, 32
; RV64I-NEXT: addi a1, a1, -2048
; RV64I-NEXT: sltu a0, a0, a1
; RV64I-NEXT: ret
; 4294965247 signed extend is -2049
%1 = icmp ule i64 %a, 4294965247
%2 = zext i1 %1 to i64
ret i64 %2
}
define i64 @icmp_ule_constant_neg_2050(i64 %a) nounwind {
; RV64I-LABEL: icmp_ule_constant_neg_2050:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, 1046527
; RV64I-NEXT: slli a1, a1, 20
; RV64I-NEXT: srli a1, a1, 32
; RV64I-NEXT: sltu a0, a0, a1
; RV64I-NEXT: ret
; 4294965246 signed extend is -2050
%1 = icmp ule i64 %a, 4294965246
%2 = zext i1 %1 to i64
ret i64 %2
}
define i64 @icmp_sgt(i64 %a, i64 %b) nounwind {
; RV64I-LABEL: icmp_sgt:
; RV64I: # %bb.0:
; RV64I-NEXT: slt a0, a1, a0
; RV64I-NEXT: ret
%1 = icmp sgt i64 %a, %b
%2 = zext i1 %1 to i64
ret i64 %2
}
define i64 @icmp_sgt_constant_zero(i64 %a) nounwind {
; RV64I-LABEL: icmp_sgt_constant_zero:
; RV64I: # %bb.0:
; RV64I-NEXT: sgtz a0, a0
; RV64I-NEXT: ret
%1 = icmp sgt i64 %a, 0
%2 = zext i1 %1 to i64
ret i64 %2
}
define i64 @icmp_sgt_constant_2046(i64 %a) nounwind {
; RV64I-LABEL: icmp_sgt_constant_2046:
; RV64I: # %bb.0:
; RV64I-NEXT: slti a0, a0, 2047
; RV64I-NEXT: xori a0, a0, 1
; RV64I-NEXT: ret
%1 = icmp sgt i64 %a, 2046
%2 = zext i1 %1 to i64
ret i64 %2
}
define i64 @icmp_sgt_constant_2047(i64 %a) nounwind {
; RV64I-LABEL: icmp_sgt_constant_2047:
; RV64I: # %bb.0:
; RV64I-NEXT: li a1, 2047
; RV64I-NEXT: slt a0, a1, a0
; RV64I-NEXT: ret
%1 = icmp sgt i64 %a, 2047
%2 = zext i1 %1 to i64
ret i64 %2
}
define i64 @icmp_sgt_constant_neg_2049(i64 %a) nounwind {
; RV64I-LABEL: icmp_sgt_constant_neg_2049:
; RV64I: # %bb.0:
; RV64I-NEXT: slti a0, a0, -2048
; RV64I-NEXT: xori a0, a0, 1
; RV64I-NEXT: ret
%1 = icmp sgt i64 %a, -2049
%2 = zext i1 %1 to i64
ret i64 %2
}
define i64 @icmp_sgt_constant_neg_2050(i64 %a) nounwind {
; RV64I-LABEL: icmp_sgt_constant_neg_2050:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, 1048575
; RV64I-NEXT: addiw a1, a1, 2046
; RV64I-NEXT: slt a0, a1, a0
; RV64I-NEXT: ret
%1 = icmp sgt i64 %a, -2050
%2 = zext i1 %1 to i64
ret i64 %2
}
define i64 @icmp_sge(i64 %a, i64 %b) nounwind {
; RV64I-LABEL: icmp_sge:
; RV64I: # %bb.0:
; RV64I-NEXT: slt a0, a0, a1
; RV64I-NEXT: xori a0, a0, 1
; RV64I-NEXT: ret
%1 = icmp sge i64 %a, %b
%2 = zext i1 %1 to i64
ret i64 %2
}
define i64 @icmp_sge_constant_zero(i64 %a) nounwind {
; RV64I-LABEL: icmp_sge_constant_zero:
; RV64I: # %bb.0:
; RV64I-NEXT: not a0, a0
; RV64I-NEXT: srli a0, a0, 63
; RV64I-NEXT: ret
%1 = icmp sge i64 %a, 0
%2 = zext i1 %1 to i64
ret i64 %2
}
define i64 @icmp_sge_constant_2047(i64 %a) nounwind {
; RV64I-LABEL: icmp_sge_constant_2047:
; RV64I: # %bb.0:
; RV64I-NEXT: slti a0, a0, 2047
; RV64I-NEXT: xori a0, a0, 1
; RV64I-NEXT: ret
%1 = icmp sge i64 %a, 2047
%2 = zext i1 %1 to i64
ret i64 %2
}
define i64 @icmp_sge_constant_2048(i64 %a) nounwind {
; RV64I-LABEL: icmp_sge_constant_2048:
; RV64I: # %bb.0:
; RV64I-NEXT: li a1, 2047
; RV64I-NEXT: slt a0, a1, a0
; RV64I-NEXT: ret
%1 = icmp sge i64 %a, 2048
%2 = zext i1 %1 to i64
ret i64 %2
}
define i64 @icmp_sge_constant_neg_2047(i64 %a) nounwind {
; RV64I-LABEL: icmp_sge_constant_neg_2047:
; RV64I: # %bb.0:
; RV64I-NEXT: slti a0, a0, -2047
; RV64I-NEXT: xori a0, a0, 1
; RV64I-NEXT: ret
%1 = icmp sge i64 %a, -2047
%2 = zext i1 %1 to i64
ret i64 %2
}
define i64 @icmp_sge_constant_neg_2048(i64 %a) nounwind {
; RV64I-LABEL: icmp_sge_constant_neg_2048:
; RV64I: # %bb.0:
; RV64I-NEXT: not a0, a0
; RV64I-NEXT: srli a0, a0, 63
; RV64I-NEXT: ret
%1 = icmp sge i64 %a, 0
%2 = zext i1 %1 to i64
ret i64 %2
}
define i64 @icmp_slt(i64 %a, i64 %b) nounwind {
; RV64I-LABEL: icmp_slt:
; RV64I: # %bb.0:
; RV64I-NEXT: slt a0, a0, a1
; RV64I-NEXT: ret
%1 = icmp slt i64 %a, %b
%2 = zext i1 %1 to i64
ret i64 %2
}
define i64 @icmp_slt_constant_zero(i64 %a) nounwind {
; RV64I-LABEL: icmp_slt_constant_zero:
; RV64I: # %bb.0:
; RV64I-NEXT: srli a0, a0, 63
; RV64I-NEXT: ret
%1 = icmp slt i64 %a, 0
%2 = zext i1 %1 to i64
ret i64 %2
}
define i64 @icmp_slt_constant_2047(i64 %a) nounwind {
; RV64I-LABEL: icmp_slt_constant_2047:
; RV64I: # %bb.0:
; RV64I-NEXT: slti a0, a0, 2047
; RV64I-NEXT: ret
%1 = icmp slt i64 %a, 2047
%2 = zext i1 %1 to i64
ret i64 %2
}
define i64 @icmp_slt_constant_2048(i64 %a) nounwind {
; RV64I-LABEL: icmp_slt_constant_2048:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, 1
; RV64I-NEXT: addiw a1, a1, -2048
; RV64I-NEXT: slt a0, a0, a1
; RV64I-NEXT: ret
%1 = icmp slt i64 %a, 2048
%2 = zext i1 %1 to i64
ret i64 %2
}
define i64 @icmp_slt_constant_neg_2048(i64 %a) nounwind {
; RV64I-LABEL: icmp_slt_constant_neg_2048:
; RV64I: # %bb.0:
; RV64I-NEXT: slti a0, a0, -2048
; RV64I-NEXT: ret
%1 = icmp slt i64 %a, -2048
%2 = zext i1 %1 to i64
ret i64 %2
}
define i64 @icmp_slt_constant_neg_2049(i64 %a) nounwind {
; RV64I-LABEL: icmp_slt_constant_neg_2049:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, 1048575
; RV64I-NEXT: addiw a1, a1, 2047
; RV64I-NEXT: slt a0, a0, a1
; RV64I-NEXT: ret
%1 = icmp slt i64 %a, -2049
%2 = zext i1 %1 to i64
ret i64 %2
}
define i64 @icmp_sle(i64 %a, i64 %b) nounwind {
; RV64I-LABEL: icmp_sle:
; RV64I: # %bb.0:
; RV64I-NEXT: slt a0, a1, a0
; RV64I-NEXT: xori a0, a0, 1
; RV64I-NEXT: ret
%1 = icmp sle i64 %a, %b
%2 = zext i1 %1 to i64
ret i64 %2
}
define i64 @icmp_sle_constant_zero(i64 %a) nounwind {
; RV64I-LABEL: icmp_sle_constant_zero:
; RV64I: # %bb.0:
; RV64I-NEXT: slti a0, a0, 1
; RV64I-NEXT: ret
%1 = icmp sle i64 %a, 0
%2 = zext i1 %1 to i64
ret i64 %2
}
define i64 @icmp_sle_constant_2046(i64 %a) nounwind {
; RV64I-LABEL: icmp_sle_constant_2046:
; RV64I: # %bb.0:
; RV64I-NEXT: slti a0, a0, 2047
; RV64I-NEXT: ret
%1 = icmp sle i64 %a, 2046
%2 = zext i1 %1 to i64
ret i64 %2
}
define i64 @icmp_sle_constant_2047(i64 %a) nounwind {
; RV64I-LABEL: icmp_sle_constant_2047:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, 1
; RV64I-NEXT: addiw a1, a1, -2048
; RV64I-NEXT: slt a0, a0, a1
; RV64I-NEXT: ret
%1 = icmp sle i64 %a, 2047
%2 = zext i1 %1 to i64
ret i64 %2
}
define i64 @icmp_sle_constant_neg_2049(i64 %a) nounwind {
; RV64I-LABEL: icmp_sle_constant_neg_2049:
; RV64I: # %bb.0:
; RV64I-NEXT: slti a0, a0, -2048
; RV64I-NEXT: ret
%1 = icmp sle i64 %a, -2049
%2 = zext i1 %1 to i64
ret i64 %2
}
define i64 @icmp_sle_constant_neg_2050(i64 %a) nounwind {
; RV64I-LABEL: icmp_sle_constant_neg_2050:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, 1048575
; RV64I-NEXT: addiw a1, a1, 2047
craig.topperUnsubmitted
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Same here

craig.topper: Same here
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done

Miss_Grape: done
; RV64I-NEXT: slt a0, a0, a1
; RV64I-NEXT: ret
%1 = icmp sle i64 %a, -2050
%2 = zext i1 %1 to i64
ret i64 %2
}