[RISCV] Add CMOV isel pattern for (select (setgt X, Imm), Y, Z)

[benshi001]

You need more cases to show the advantage of your change.

[Miss_Grape]

Update tests

[Miss_Grape]

In D122644#3413901, @benshi001 wrote:

You need more cases to show the advantage of your change.

Done

[craig.topper]

llvm/test/CodeGen/RISCV/select-cc.ll

127

This doesn't look like it's doing what it was supposed to do. The immediate is in a register.

[Miss_Grape]

llvm/test/CodeGen/RISCV/select-cc.ll

127

1024 used twice， whicn used sgt and ugt. I changed the immediate value of ugt to 2046

[Miss_Grape]

Update the test case

[craig.topper]

LGTM

llvm/lib/Target/RISCV/RISCVInstrInfoZb.td

def : Pat<(select (XLenVT (setuge GPR:$x, GPR:$y)), GPR:$rs3, GPR:$rs1),
           (CMOV GPR:$rs1, (SLTU GPR:$x, GPR:$y), GPR:$rs3)>;
 def : Pat<(select (XLenVT (setule GPR:$y, GPR:$x)), GPR:$rs3, GPR:$rs1),
           (CMOV GPR:$rs1, (SLTU GPR:$x, GPR:$y), GPR:$rs3)>;
 def : Pat<(select (XLenVT (setge GPR:$x, GPR:$y)), GPR:$rs3, GPR:$rs1),
           (CMOV GPR:$rs1, (SLT GPR:$x, GPR:$y), GPR:$rs3)>;
 def : Pat<(select (XLenVT (setle GPR:$y, GPR:$x)), GPR:$rs3, GPR:$rs1),
           (CMOV GPR:$rs1, (SLT GPR:$x, GPR:$y), GPR:$rs3)>;
 
-// setge X, 0 is canonicalized to setgt X, -1.
-// FIXME: This can be generalized to more immediates by using SLTI.
-def : Pat<(select (XLenVT (setgt GPR:$x, -1)), GPR:$rs3, GPR:$rs1),
-          (CMOV GPR:$rs1, (SLT GPR:$x, X0), GPR:$rs3)>;
+// setge X, Imm is canonicalized to setgt X, (Imm - 1).
+def : Pat<(select (XLenVT (setgt GPR:$x, simm12_minus1_nonzero:$imm)), GPR:$rs3, GPR:$rs1),
+          (CMOV GPR:$rs1, (SLTI GPR:$x, (ImmPlus1 simm12_minus1_nonzero:$imm)), GPR:$rs3)>;
+def : Pat<(select (XLenVT (setugt GPR:$x, simm12_minus1_nonzero:$imm)), GPR:$rs3, GPR:$rs1),
+          (CMOV GPR:$rs1, (SLTIU GPR:$x, (ImmPlus1 simm12_minus1_nonzero:$imm)), GPR:$rs3)>;
 
 def : Pat<(select GPR:$rs2, GPR:$rs1, GPR:$rs3),
           (CMOV GPR:$rs1, GPR:$rs2, GPR:$rs3)>;
 } // Predicates = [HasStdExtZbt]
 
 let Predicates = [HasStdExtZbt] in {
 def : Pat<(riscv_fsl GPR:$rs1, GPR:$rs3, GPR:$rs2),
           (FSL GPR:$rs1, GPR:$rs2, GPR:$rs3)>;

llvm/test/CodeGen/RISCV/rv32zbt.ll

 ; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    mv a0, a2
 ; RV32I-NEXT:  .LBB16_2:
 ; RV32I-NEXT:    ret
 ;
 ; RV32ZBT-LABEL: cmov_sgt_i32_constant_2046:
 ; RV32ZBT:       # %bb.0:
 ; RV32ZBT-NEXT:    slti a1, a1, 2047
-; RV32ZBT-NEXT:    xori a1, a1, 1
-; RV32ZBT-NEXT:    cmov a0, a1, a0, a2
+; RV32ZBT-NEXT:    cmov a0, a1, a2, a0
 ; RV32ZBT-NEXT:    ret
   %tobool = icmp sgt i32 %b, 2046
   %cond = select i1 %tobool, i32 %a, i32 %c
   ret i32 %cond
 }
 
 define i32 @cmov_sgt_i32_constant_neg_2049(i32 %a, i32 %b, i32 %c) nounwind {
 ; RV32I-LABEL: cmov_sgt_i32_constant_neg_2049:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    lui a3, 1048575
 ; RV32I-NEXT:    addi a3, a3, 2047
 ; RV32I-NEXT:    blt a3, a1, .LBB17_2
 ; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    mv a0, a2
 ; RV32I-NEXT:  .LBB17_2:
 ; RV32I-NEXT:    ret
 ;
 ; RV32ZBT-LABEL: cmov_sgt_i32_constant_neg_2049:
 ; RV32ZBT:       # %bb.0:
 ; RV32ZBT-NEXT:    slti a1, a1, -2048
-; RV32ZBT-NEXT:    xori a1, a1, 1
-; RV32ZBT-NEXT:    cmov a0, a1, a0, a2
+; RV32ZBT-NEXT:    cmov a0, a1, a2, a0
 ; RV32ZBT-NEXT:    ret
   %tobool = icmp sgt i32 %b, -2049
   %cond = select i1 %tobool, i32 %a, i32 %c
   ret i32 %cond
 }
 
 define i32 @cmov_sge_i32(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
 ; RV32I-LABEL: cmov_sge_i32:

 ; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    mv a0, a2
 ; RV32I-NEXT:  .LBB19_2:
 ; RV32I-NEXT:    ret
 ;
 ; RV32ZBT-LABEL: cmov_sge_i32_constant_2047:
 ; RV32ZBT:       # %bb.0:
 ; RV32ZBT-NEXT:    slti a1, a1, 2047
-; RV32ZBT-NEXT:    xori a1, a1, 1
-; RV32ZBT-NEXT:    cmov a0, a1, a0, a2
+; RV32ZBT-NEXT:    cmov a0, a1, a2, a0
 ; RV32ZBT-NEXT:    ret
   %tobool = icmp sge i32 %b, 2047
   %cond = select i1 %tobool, i32 %a, i32 %c
   ret i32 %cond
 }
 
 define i32 @cmov_sge_i32_constant_neg_2048(i32 %a, i32 %b, i32 %c) nounwind {
 ; RV32I-LABEL: cmov_sge_i32_constant_neg_2048:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    lui a3, 1048575
 ; RV32I-NEXT:    addi a3, a3, 2047
 ; RV32I-NEXT:    blt a3, a1, .LBB20_2
 ; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    mv a0, a2
 ; RV32I-NEXT:  .LBB20_2:
 ; RV32I-NEXT:    ret
 ;
 ; RV32ZBT-LABEL: cmov_sge_i32_constant_neg_2048:
 ; RV32ZBT:       # %bb.0:
 ; RV32ZBT-NEXT:    slti a1, a1, -2048
-; RV32ZBT-NEXT:    xori a1, a1, 1
-; RV32ZBT-NEXT:    cmov a0, a1, a0, a2
+; RV32ZBT-NEXT:    cmov a0, a1, a2, a0
 ; RV32ZBT-NEXT:    ret
   %tobool = icmp sge i32 %b, -2048
   %cond = select i1 %tobool, i32 %a, i32 %c
   ret i32 %cond
 }
 
 define i32 @cmov_ule_i32(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
 ; RV32I-LABEL: cmov_ule_i32:

 ; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    mv a0, a2
 ; RV32I-NEXT:  .LBB25_2:
 ; RV32I-NEXT:    ret
 ;
 ; RV32ZBT-LABEL: cmov_ugt_i32_constant_2046:
 ; RV32ZBT:       # %bb.0:
 ; RV32ZBT-NEXT:    sltiu a1, a1, 2047
-; RV32ZBT-NEXT:    xori a1, a1, 1
-; RV32ZBT-NEXT:    cmov a0, a1, a0, a2
+; RV32ZBT-NEXT:    cmov a0, a1, a2, a0
 ; RV32ZBT-NEXT:    ret
   %tobool = icmp ugt i32 %b, 2046
   %cond = select i1 %tobool, i32 %a, i32 %c
   ret i32 %cond
 }
 
 define i32 @cmov_ugt_i32_constant_neg_2049(i32 %a, i32 %b, i32 %c) nounwind {
 ; RV32I-LABEL: cmov_ugt_i32_constant_neg_2049:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    lui a3, 1048575
 ; RV32I-NEXT:    addi a3, a3, 2047
 ; RV32I-NEXT:    bltu a3, a1, .LBB26_2
 ; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    mv a0, a2
 ; RV32I-NEXT:  .LBB26_2:
 ; RV32I-NEXT:    ret
 ;
 ; RV32ZBT-LABEL: cmov_ugt_i32_constant_neg_2049:
 ; RV32ZBT:       # %bb.0:
 ; RV32ZBT-NEXT:    sltiu a1, a1, -2048
-; RV32ZBT-NEXT:    xori a1, a1, 1
-; RV32ZBT-NEXT:    cmov a0, a1, a0, a2
+; RV32ZBT-NEXT:    cmov a0, a1, a2, a0
 ; RV32ZBT-NEXT:    ret
   %tobool = icmp ugt i32 %b, 4294965247
   %cond = select i1 %tobool, i32 %a, i32 %c
   ret i32 %cond
 }
 
 define i32 @cmov_uge_i32(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
 ; RV32I-LABEL: cmov_uge_i32:

 ; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    mv a0, a2
 ; RV32I-NEXT:  .LBB28_2:
 ; RV32I-NEXT:    ret
 ;
 ; RV32ZBT-LABEL: cmov_uge_i32_constant_2047:
 ; RV32ZBT:       # %bb.0:
 ; RV32ZBT-NEXT:    sltiu a1, a1, 2047
-; RV32ZBT-NEXT:    xori a1, a1, 1
-; RV32ZBT-NEXT:    cmov a0, a1, a0, a2
+; RV32ZBT-NEXT:    cmov a0, a1, a2, a0
 ; RV32ZBT-NEXT:    ret
   %tobool = icmp uge i32 %b, 2047
   %cond = select i1 %tobool, i32 %a, i32 %c
   ret i32 %cond
 }
 
 define i32 @cmov_uge_i32_constant_neg_2048(i32 %a, i32 %b, i32 %c) nounwind {
 ; RV32I-LABEL: cmov_uge_i32_constant_neg_2048:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    lui a3, 1048575
 ; RV32I-NEXT:    addi a3, a3, 2047
 ; RV32I-NEXT:    bltu a3, a1, .LBB29_2
 ; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    mv a0, a2
 ; RV32I-NEXT:  .LBB29_2:
 ; RV32I-NEXT:    ret
 ;
 ; RV32ZBT-LABEL: cmov_uge_i32_constant_neg_2048:
 ; RV32ZBT:       # %bb.0:
 ; RV32ZBT-NEXT:    sltiu a1, a1, -2048
-; RV32ZBT-NEXT:    xori a1, a1, 1
-; RV32ZBT-NEXT:    cmov a0, a1, a0, a2
+; RV32ZBT-NEXT:    cmov a0, a1, a2, a0
 ; RV32ZBT-NEXT:    ret
   %tobool = icmp uge i32 %b, 4294965248
   %cond = select i1 %tobool, i32 %a, i32 %c
   ret i32 %cond
 }
 
 define i64 @cmov_i64(i64 %a, i64 %b, i64 %c) nounwind {
 ; RV32I-LABEL: cmov_i64:

llvm/test/CodeGen/RISCV/rv64zbt.ll

 ; RV64I-NEXT:  # %bb.1:
 ; RV64I-NEXT:    mv a0, a2
 ; RV64I-NEXT:  .LBB20_2:
 ; RV64I-NEXT:    ret
 ;
 ; RV64ZBT-LABEL: cmov_sgt_i64_constant_2046:
 ; RV64ZBT:       # %bb.0:
 ; RV64ZBT-NEXT:    slti a1, a1, 2047
-; RV64ZBT-NEXT:    xori a1, a1, 1
-; RV64ZBT-NEXT:    cmov a0, a1, a0, a2
+; RV64ZBT-NEXT:    cmov a0, a1, a2, a0
 ; RV64ZBT-NEXT:    ret
   %tobool = icmp sgt i64 %b, 2046
   %cond = select i1 %tobool, i64 %a, i64 %c
   ret i64 %cond
 }
 
 define i64 @cmov_sgt_i64_constant_neg_2049(i64 %a, i64 %b, i64 %c) nounwind {
 ; RV64I-LABEL: cmov_sgt_i64_constant_neg_2049:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    lui a3, 1048575
 ; RV64I-NEXT:    addiw a3, a3, 2047
 ; RV64I-NEXT:    blt a3, a1, .LBB21_2
 ; RV64I-NEXT:  # %bb.1:
 ; RV64I-NEXT:    mv a0, a2
 ; RV64I-NEXT:  .LBB21_2:
 ; RV64I-NEXT:    ret
 ;
 ; RV64ZBT-LABEL: cmov_sgt_i64_constant_neg_2049:
 ; RV64ZBT:       # %bb.0:
 ; RV64ZBT-NEXT:    slti a1, a1, -2048
-; RV64ZBT-NEXT:    xori a1, a1, 1
-; RV64ZBT-NEXT:    cmov a0, a1, a0, a2
+; RV64ZBT-NEXT:    cmov a0, a1, a2, a0
 ; RV64ZBT-NEXT:    ret
   %tobool = icmp sgt i64 %b, -2049
   %cond = select i1 %tobool, i64 %a, i64 %c
   ret i64 %cond
 }
 
 define i64 @cmov_sge_i64(i64 %a, i64 %b, i64 %c, i64 %d) nounwind {
 ; RV64I-LABEL: cmov_sge_i64:

 ; RV64I-NEXT:  # %bb.1:
 ; RV64I-NEXT:    mv a0, a2
 ; RV64I-NEXT:  .LBB23_2:
 ; RV64I-NEXT:    ret
 ;
 ; RV64ZBT-LABEL: cmov_sge_i64_constant_2047:
 ; RV64ZBT:       # %bb.0:
 ; RV64ZBT-NEXT:    slti a1, a1, 2047
-; RV64ZBT-NEXT:    xori a1, a1, 1
-; RV64ZBT-NEXT:    cmov a0, a1, a0, a2
+; RV64ZBT-NEXT:    cmov a0, a1, a2, a0
 ; RV64ZBT-NEXT:    ret
   %tobool = icmp sge i64 %b, 2047
   %cond = select i1 %tobool, i64 %a, i64 %c
   ret i64 %cond
 }
 
 define i64 @cmov_sge_i64_constant_neg_2048(i64 %a, i64 %b, i64 %c) nounwind {
 ; RV64I-LABEL: cmov_sge_i64_constant_neg_2048:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    lui a3, 1048575
 ; RV64I-NEXT:    addiw a3, a3, 2047
 ; RV64I-NEXT:    blt a3, a1, .LBB24_2
 ; RV64I-NEXT:  # %bb.1:
 ; RV64I-NEXT:    mv a0, a2
 ; RV64I-NEXT:  .LBB24_2:
 ; RV64I-NEXT:    ret
 ;
 ; RV64ZBT-LABEL: cmov_sge_i64_constant_neg_2048:
 ; RV64ZBT:       # %bb.0:
 ; RV64ZBT-NEXT:    slti a1, a1, -2048
-; RV64ZBT-NEXT:    xori a1, a1, 1
-; RV64ZBT-NEXT:    cmov a0, a1, a0, a2
+; RV64ZBT-NEXT:    cmov a0, a1, a2, a0
 ; RV64ZBT-NEXT:    ret
   %tobool = icmp sge i64 %b, -2048
   %cond = select i1 %tobool, i64 %a, i64 %c
   ret i64 %cond
 }
 
 define i64 @cmov_ule_i64(i64 %a, i64 %b, i64 %c, i64 %d) nounwind {
 ; RV64I-LABEL: cmov_ule_i64:

 ; RV64I-NEXT:  # %bb.1:
 ; RV64I-NEXT:    mv a0, a2
 ; RV64I-NEXT:  .LBB29_2:
 ; RV64I-NEXT:    ret
 ;
 ; RV64ZBT-LABEL: cmov_ugt_i64_constant_2046:
 ; RV64ZBT:       # %bb.0:
 ; RV64ZBT-NEXT:    sltiu a1, a1, 2047
-; RV64ZBT-NEXT:    xori a1, a1, 1
-; RV64ZBT-NEXT:    cmov a0, a1, a0, a2
+; RV64ZBT-NEXT:    cmov a0, a1, a2, a0
 ; RV64ZBT-NEXT:    ret
   %tobool = icmp ugt i64 %b, 2046
   %cond = select i1 %tobool, i64 %a, i64 %c
   ret i64 %cond
 }
 
 define i64 @cmov_ugt_i64_constant_neg_2049(i64 %a, i64 %b, i64 %c) nounwind {
 ; RV64I-LABEL: cmov_ugt_i64_constant_neg_2049:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    lui a3, 1048575
 ; RV64I-NEXT:    addiw a3, a3, 2047
 ; RV64I-NEXT:    bltu a3, a1, .LBB30_2
 ; RV64I-NEXT:  # %bb.1:
 ; RV64I-NEXT:    mv a0, a2
 ; RV64I-NEXT:  .LBB30_2:
 ; RV64I-NEXT:    ret
 ;
 ; RV64ZBT-LABEL: cmov_ugt_i64_constant_neg_2049:
 ; RV64ZBT:       # %bb.0:
 ; RV64ZBT-NEXT:    sltiu a1, a1, -2048
-; RV64ZBT-NEXT:    xori a1, a1, 1
-; RV64ZBT-NEXT:    cmov a0, a1, a0, a2
+; RV64ZBT-NEXT:    cmov a0, a1, a2, a0
 ; RV64ZBT-NEXT:    ret
   %tobool = icmp ugt i64 %b, 18446744073709549567
   %cond = select i1 %tobool, i64 %a, i64 %c
   ret i64 %cond
 }
 
 define i64 @cmov_uge_i64(i64 %a, i64 %b, i64 %c, i64 %d) nounwind {
 ; RV64I-LABEL: cmov_uge_i64:

 ; RV64I-NEXT:  # %bb.1:
 ; RV64I-NEXT:    mv a0, a2
 ; RV64I-NEXT:  .LBB32_2:
 ; RV64I-NEXT:    ret
 ;
 ; RV64ZBT-LABEL: cmov_uge_i64_constant_2047:
 ; RV64ZBT:       # %bb.0:
 ; RV64ZBT-NEXT:    sltiu a1, a1, 2047
-; RV64ZBT-NEXT:    xori a1, a1, 1
-; RV64ZBT-NEXT:    cmov a0, a1, a0, a2
+; RV64ZBT-NEXT:    cmov a0, a1, a2, a0
 ; RV64ZBT-NEXT:    ret
   %tobool = icmp uge i64 %b, 2047
   %cond = select i1 %tobool, i64 %a, i64 %c
   ret i64 %cond
 }
 
 define i64 @cmov_uge_i64_constant_neg_2048(i64 %a, i64 %b, i64 %c) nounwind {
 ; RV64I-LABEL: cmov_uge_i64_constant_neg_2048:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    lui a3, 1048575
 ; RV64I-NEXT:    addiw a3, a3, 2047
 ; RV64I-NEXT:    bltu a3, a1, .LBB33_2
 ; RV64I-NEXT:  # %bb.1:
 ; RV64I-NEXT:    mv a0, a2
 ; RV64I-NEXT:  .LBB33_2:
 ; RV64I-NEXT:    ret
 ;
 ; RV64ZBT-LABEL: cmov_uge_i64_constant_neg_2048:
 ; RV64ZBT:       # %bb.0:
 ; RV64ZBT-NEXT:    sltiu a1, a1, -2048
-; RV64ZBT-NEXT:    xori a1, a1, 1
-; RV64ZBT-NEXT:    cmov a0, a1, a0, a2
+; RV64ZBT-NEXT:    cmov a0, a1, a2, a0
 ; RV64ZBT-NEXT:    ret
   %tobool = icmp uge i64 %b, 18446744073709549568
   %cond = select i1 %tobool, i64 %a, i64 %c
   ret i64 %cond
 }
 
 declare i32 @llvm.fshl.i32(i32, i32, i32)
 

llvm/test/CodeGen/RISCV/select-cc.ll

 ; RV32I-NEXT:  # %bb.19:
 ; RV32I-NEXT:    mv a0, a2
 ; RV32I-NEXT:  .LBB0_20:
 ; RV32I-NEXT:    lw a2, 0(a1)
 ; RV32I-NEXT:    blez a2, .LBB0_22
 ; RV32I-NEXT:  # %bb.21:
 ; RV32I-NEXT:    mv a0, a2
 ; RV32I-NEXT:  .LBB0_22:
-; RV32I-NEXT:    lw a1, 0(a1)
+; RV32I-NEXT:    lw a3, 0(a1)
 ; RV32I-NEXT:    bgez a2, .LBB0_24
 ; RV32I-NEXT:  # %bb.23:
-; RV32I-NEXT:    mv a0, a1
+; RV32I-NEXT:    mv a0, a3
 ; RV32I-NEXT:  .LBB0_24:
+; RV32I-NEXT:    lw a3, 0(a1)
+; RV32I-NEXT:    li a4, 1024
+; RV32I-NEXT:    blt a4, a3, .LBB0_26
+; RV32I-NEXT:  # %bb.25:
+; RV32I-NEXT:    mv a0, a3
+; RV32I-NEXT:  .LBB0_26:
+; RV32I-NEXT:    lw a1, 0(a1)
+; RV32I-NEXT:    li a3, 2046
+; RV32I-NEXT:    bltu a3, a2, .LBB0_28
+; RV32I-NEXT:  # %bb.27:
+; RV32I-NEXT:    mv a0, a1
+; RV32I-NEXT:  .LBB0_28:
 ; RV32I-NEXT:    ret
 ;
 ; RV32IBT-LABEL: foo:
 ; RV32IBT:       # %bb.0:
 ; RV32IBT-NEXT:    lw a2, 0(a1)
 ; RV32IBT-NEXT:    lw a3, 0(a1)
 ; RV32IBT-NEXT:    xor a4, a0, a2
 ; RV32IBT-NEXT:    cmov a0, a4, a2, a0

 ; RV32IBT-NEXT:    lw a3, 0(a1)
 ; RV32IBT-NEXT:    slt a4, a2, a0
 ; RV32IBT-NEXT:    cmov a0, a4, a0, a2
 ; RV32IBT-NEXT:    lw a2, 0(a1)
 ; RV32IBT-NEXT:    slt a4, a0, a3
 ; RV32IBT-NEXT:    cmov a0, a4, a3, a0
 ; RV32IBT-NEXT:    lw a3, 0(a1)
 ; RV32IBT-NEXT:    slt a4, a0, a2
+; RV32IBT-NEXT:    lw a5, 0(a1)
 ; RV32IBT-NEXT:    cmov a0, a4, a0, a2
+; RV32IBT-NEXT:    slt a2, a3, a0
+; RV32IBT-NEXT:    cmov a0, a2, a3, a0
+; RV32IBT-NEXT:    slti a2, a5, 1
+; RV32IBT-NEXT:    lw a3, 0(a1)
+; RV32IBT-NEXT:    cmov a0, a2, a0, a5
 ; RV32IBT-NEXT:    lw a2, 0(a1)
-; RV32IBT-NEXT:    slt a4, a3, a0
+; RV32IBT-NEXT:    slti a4, a5, 0
 ; RV32IBT-NEXT:    cmov a0, a4, a3, a0
 ; RV32IBT-NEXT:    lw a1, 0(a1)
-; RV32IBT-NEXT:    slti a3, a2, 1
-; RV32IBT-NEXT:    cmov a0, a3, a0, a2
-; RV32IBT-NEXT:    sltz a2, a2
+; RV32IBT-NEXT:    slti a3, a2, 1025
+; RV32IBT-NEXT:    cmov a0, a3, a2, a0
+; RV32IBT-NEXT:    sltiu a2, a5, 2047
 ; RV32IBT-NEXT:    cmov a0, a2, a1, a0
 ; RV32IBT-NEXT:    ret
   %val1 = load volatile i32, i32* %b
   %tst1 = icmp eq i32 %a, %val1
   %val2 = select i1 %tst1, i32 %a, i32 %val1
 
   %val3 = load volatile i32, i32* %b
   %tst2 = icmp ne i32 %val2, %val3
   %val4 = select i1 %tst2, i32 %val2, i32 %val3
; RV32IBT-NEXT:    ret
   %val21 = load volatile i32, i32* %b
   %tst11 = icmp slt i32 %val21, 1
   %val22 = select i1 %tst11, i32 %val20, i32 %val21
 
   %val23 = load volatile i32, i32* %b
   %tst12 = icmp sgt i32 %val21, -1
   %val24 = select i1 %tst12, i32 %val22, i32 %val23
 
-  ret i32 %val24
+  %val25 = load volatile i32, i32* %b
+  %tst13 = icmp sgt i32 %val25, 1024
+  %val26 = select i1 %tst13, i32 %val24, i32 %val25
+
+  %val27 = load volatile i32, i32* %b
+  %tst14 = icmp ugt i32 %val21, 2046
+  %val28 = select i1 %tst14, i32 %val26, i32 %val27
+  ret i32 %val28
 }
 
 ; Test that we can ComputeNumSignBits across basic blocks when the live out is
 ; RISCVISD::SELECT_CC. There should be no slli+srai or sext.h in the output.
 define signext i16 @numsignbits(i16 signext %0, i16 signext %1, i16 signext %2, i16 signext %3) nounwind {
 ; RV32I-LABEL: numsignbits:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16