[RISCV] Add CMOV isel pattern for (select (setgt X, Imm), Y, Z)

[benshi001]

You need more cases to show the advantage of your change.

[Miss_Grape]

Update tests

[Miss_Grape]

In D122644#3413901, @benshi001 wrote:

You need more cases to show the advantage of your change.

Done

[craig.topper]

llvm/test/CodeGen/RISCV/select-cc.ll

109

This doesn't look like it's doing what it was supposed to do. The immediate is in a register.

[Miss_Grape]

llvm/test/CodeGen/RISCV/select-cc.ll

109

1024 used twice， whicn used sgt and ugt. I changed the immediate value of ugt to 2046

[Miss_Grape]

Update the test case

[craig.topper]

LGTM

llvm/lib/Target/RISCV/RISCVInstrInfo.td

 
 // Standalone (codegen-only) immleaf patterns.
 
 // A 12-bit signed immediate plus one where the imm range will be [-2047, 2048].
 def simm12_plus1 : ImmLeaf<XLenVT,
   [{return (isInt<12>(Imm) && Imm != -2048) || Imm == 2048;}]>;
 
 // A 12-bit signed immediate sub one and exclude zero
-def simm12_sub1_nonzero : PatLeaf<(imm), [{
+def simm12_minus1_nonzero : PatLeaf<(imm), [{
   if (!N->hasOneUse())
     return false;
   // The immediate operand must be in range [-2049, 0) or (0, 2046].
   int64_t Imm = N->getSExtValue();
   return (Imm >= -2049 && Imm < 0) || (Imm > 0 && Imm <= 2046);
 }]>;
 
 // A 6-bit constant greater than 32.

 def : Pat<(setne GPR:$rs1, simm12_plus1:$imm12),
           (SLTU X0, (ADDI GPR:$rs1, (NegImm simm12_plus1:$imm12)))>;
 def : Pat<(setugt GPR:$rs1, GPR:$rs2), (SLTU GPR:$rs2, GPR:$rs1)>;
 def : Pat<(setuge GPR:$rs1, GPR:$rs2), (XORI (SLTU GPR:$rs1, GPR:$rs2), 1)>;
 def : Pat<(setule GPR:$rs1, GPR:$rs2), (XORI (SLTU GPR:$rs2, GPR:$rs1), 1)>;
 def : Pat<(setgt GPR:$rs1, GPR:$rs2), (SLT GPR:$rs2, GPR:$rs1)>;
 def : Pat<(setge GPR:$rs1, GPR:$rs2), (XORI (SLT GPR:$rs1, GPR:$rs2), 1)>;
 def : Pat<(setle GPR:$rs1, GPR:$rs2), (XORI (SLT GPR:$rs2, GPR:$rs1), 1)>;
-def : Pat<(setgt GPR:$rs1, simm12_sub1_nonzero:$imm),
-          (XORI (SLTI GPR:$rs1, (ImmPlus1 simm12_sub1_nonzero:$imm)), 1)>;
-def : Pat<(setugt GPR:$rs1, simm12_sub1_nonzero:$imm),
-          (XORI (SLTIU GPR:$rs1, (ImmPlus1 simm12_sub1_nonzero:$imm)), 1)>;
+def : Pat<(setgt GPR:$rs1, simm12_minus1_nonzero:$imm),
+          (XORI (SLTI GPR:$rs1, (ImmPlus1 simm12_minus1_nonzero:$imm)), 1)>;
+def : Pat<(setugt GPR:$rs1, simm12_minus1_nonzero:$imm),
+          (XORI (SLTIU GPR:$rs1, (ImmPlus1 simm12_minus1_nonzero:$imm)), 1)>;
 
 def IntCCtoRISCVCC : SDNodeXForm<riscv_selectcc, [{
   ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
   RISCVCC::CondCode BrCC = getRISCVCCForIntCC(CC);
   return CurDAG->getTargetConstant(BrCC, SDLoc(N), Subtarget->getXLenVT());
 }]>;
 
 def riscv_selectcc_frag : PatFrag<(ops node:$lhs, node:$rhs, node:$cc,

llvm/lib/Target/RISCV/RISCVInstrInfoZb.td

def : Pat<(select (XLenVT (setuge GPR:$x, GPR:$y)), GPR:$rs3, GPR:$rs1),
           (CMOV GPR:$rs1, (SLTU GPR:$x, GPR:$y), GPR:$rs3)>;
 def : Pat<(select (XLenVT (setule GPR:$y, GPR:$x)), GPR:$rs3, GPR:$rs1),
           (CMOV GPR:$rs1, (SLTU GPR:$x, GPR:$y), GPR:$rs3)>;
 def : Pat<(select (XLenVT (setge GPR:$x, GPR:$y)), GPR:$rs3, GPR:$rs1),
           (CMOV GPR:$rs1, (SLT GPR:$x, GPR:$y), GPR:$rs3)>;
 def : Pat<(select (XLenVT (setle GPR:$y, GPR:$x)), GPR:$rs3, GPR:$rs1),
           (CMOV GPR:$rs1, (SLT GPR:$x, GPR:$y), GPR:$rs3)>;
 
-// setge X, 0 is canonicalized to setgt X, -1.
-// FIXME: This can be generalized to more immediates by using SLTI.
-def : Pat<(select (XLenVT (setgt GPR:$x, -1)), GPR:$rs3, GPR:$rs1),
-          (CMOV GPR:$rs1, (SLT GPR:$x, X0), GPR:$rs3)>;
+// setge X, Imm is canonicalized to setgt X, (Imm - 1).
+def : Pat<(select (XLenVT (setgt GPR:$x, simm12_minus1_nonzero:$imm)), GPR:$rs3, GPR:$rs1),
+          (CMOV GPR:$rs1, (SLTI GPR:$x, (ImmPlus1 simm12_minus1_nonzero:$imm)), GPR:$rs3)>;
+def : Pat<(select (XLenVT (setugt GPR:$x, simm12_minus1_nonzero:$imm)), GPR:$rs3, GPR:$rs1),
+          (CMOV GPR:$rs1, (SLTIU GPR:$x, (ImmPlus1 simm12_minus1_nonzero:$imm)), GPR:$rs3)>;
 
 def : Pat<(select GPR:$rs2, GPR:$rs1, GPR:$rs3),
           (CMOV GPR:$rs1, GPR:$rs2, GPR:$rs3)>;
 } // Predicates = [HasStdExtZbt]
 
 let Predicates = [HasStdExtZbt] in {
 def : Pat<(riscv_fsl GPR:$rs1, GPR:$rs3, GPR:$rs2),
           (FSL GPR:$rs1, GPR:$rs2, GPR:$rs3)>;

llvm/test/CodeGen/RISCV/select-cc.ll

 ; RV32IBT-NEXT:    slt a4, a0, a2
 ; RV32IBT-NEXT:    cmov a0, a4, a0, a2
 ; RV32IBT-NEXT:    lw a2, 0(a1)
 ; RV32IBT-NEXT:    slt a4, a3, a0
 ; RV32IBT-NEXT:    cmov a0, a4, a3, a0
 ; RV32IBT-NEXT:    lw a1, 0(a1)
 ; RV32IBT-NEXT:    slti a3, a2, 1
 ; RV32IBT-NEXT:    cmov a0, a3, a0, a2
-; RV32IBT-NEXT:    sltz a2, a2
+; RV32IBT-NEXT:    slti a2, a2, 0
 ; RV32IBT-NEXT:    cmov a0, a2, a1, a0
 ; RV32IBT-NEXT:    ret
   %val1 = load volatile i32, i32* %b
   %tst1 = icmp eq i32 %a, %val1
   %val2 = select i1 %tst1, i32 %a, i32 %val1
 
   %val3 = load volatile i32, i32* %b
   %tst2 = icmp ne i32 %val2, %val3
   %val4 = select i1 %tst2, i32 %val2, i32 %val3