[AArch64] Set MaxBytesForLoopAlignment for more targets

[NickGuy]

Summary

Further implementation of D114590 for the AArch64 backend. Specifying the max padding allowed for loop alignment for further AArch64 targets.

[dmgreen]

Adding a MaxBytesForLoopAlignment without a PrefLoopLogAlignment doesn't seem to make a lot of sense. I don't think it would do much on its own. Can this add sensible values for PrefLoopLogAlignment at the same time?

It could then extend the test in D114879 for all the CPUs added, to show it's tested.

llvm/lib/Target/AArch64/AArch64Subtarget.cpp

117–124

These should be added too if they can be. They may need to be split into separate case blocks, if the A510 is different to the others now.

[dmgreen]

llvm/lib/Target/AArch64/AArch64Subtarget.cpp

82

This needn't be set if there is no PrefLoopLogAlignment set too.

Either that, or it can be treated like a CortexA53/A55 below by adding it to the same case block.

llvm/test/CodeGen/AArch64/aarch64-p2align-max-bytes-neoverse.ll

9

Should this be checking for 4, 8? Can we add some of the other cpus like A53 and A55 too?

[NickGuy]

llvm/lib/Target/AArch64/AArch64Subtarget.cpp

82

I missed that when adding the others, now added.

llvm/test/CodeGen/AArch64/aarch64-p2align-max-bytes-neoverse.ll

9

Fixed, and added more of the effected cpus.

[dmgreen]

Thanks. LGTM

llvm/lib/Target/AArch64/AArch64Subtarget.cpp

82

I would fold this into the CortexA53 block. The cpus in those blocks are similar, and I dont believe there is any reason to treat them differently for function alignment.

llvm/lib/Target/AArch64/AArch64Subtarget.cpp

void AArch64Subtarget::initializeProperties() {
   // features.
   switch (ARMProcFamily) {
   case Others:
     break;
   case Carmel:
     CacheLineSize = 64;
     break;
   case CortexA35:
+    MaxBytesForLoopAlignment = 8;
     break;
   case CortexA53:
   case CortexA55:
     PrefFunctionLogAlignment = 4;
+    PrefLoopLogAlignment = 4;
+    MaxBytesForLoopAlignment = 8;
     break;
   case CortexA57:
     MaxInterleaveFactor = 4;
     PrefFunctionLogAlignment = 4;
+    PrefLoopLogAlignment = 4;
+    MaxBytesForLoopAlignment = 8;
     break;
   case CortexA65:
     PrefFunctionLogAlignment = 3;
     break;
   case CortexA72:
   case CortexA73:
   case CortexA75:
+    PrefFunctionLogAlignment = 4;
+    PrefLoopLogAlignment = 4;
+    MaxBytesForLoopAlignment = 8;
+    break;
   case CortexA76:
   case CortexA77:
   case CortexA78:
   case CortexA78C:
   case CortexR82:
   case CortexX1:
   case CortexX1C:
     PrefFunctionLogAlignment = 4;
+    PrefLoopLogAlignment = 5;
+    MaxBytesForLoopAlignment = 16;
     break;
   case CortexA510:
+    PrefFunctionLogAlignment = 4;
+    VScaleForTuning = 1;
+    PrefLoopLogAlignment = 4;
+    MaxBytesForLoopAlignment = 8;
+    break;
   case CortexA710:
   case CortexX2:
     PrefFunctionLogAlignment = 4;
     VScaleForTuning = 1;
+    PrefLoopLogAlignment = 5;
+    MaxBytesForLoopAlignment = 16;
     break;
   case A64FX:
     CacheLineSize = 256;
     PrefFunctionLogAlignment = 3;
     PrefLoopLogAlignment = 2;
     MaxInterleaveFactor = 4;
     PrefetchDistance = 128;
     MinPrefetchStride = 1024;

llvm/test/CodeGen/AArch64/aarch64-p2align-max-bytes-neoverse.ll

-; RUN: llc -mtriple=aarch64-none-linux-gnu -align-loops=32 < %s -o -| FileCheck %s --check-prefixes=CHECK,CHECK-DEFAULT
-; RUN: llc -mtriple=aarch64-none-linux-gnu -mcpu=neoverse-n1 < %s -o -| FileCheck %s --check-prefixes=CHECK,CHECK-N1
+; RUN: llc -mtriple=aarch64-none-linux-gnu -align-loops=32   < %s -o -| FileCheck %s --check-prefixes=CHECK,CHECK-DEFAULT
+; RUN: llc -mtriple=aarch64-none-linux-gnu -mcpu=neoverse-n1 < %s -o -| FileCheck %s --check-prefixes=CHECK,CHECK-16
+; RUN: llc -mtriple=aarch64-none-linux-gnu -mcpu=neoverse-n2 < %s -o -| FileCheck %s --check-prefixes=CHECK,CHECK-16
+; RUN: llc -mtriple=aarch64-none-linux-gnu -mcpu=neoverse-v1 < %s -o -| FileCheck %s --check-prefixes=CHECK,CHECK-16
+; RUN: llc -mtriple=aarch64-none-linux-gnu -mcpu=cortex-x2   < %s -o -| FileCheck %s --check-prefixes=CHECK,CHECK-16
+; RUN: llc -mtriple=aarch64-none-linux-gnu -mcpu=cortex-a710 < %s -o -| FileCheck %s --check-prefixes=CHECK,CHECK-16
+; RUN: llc -mtriple=aarch64-none-linux-gnu -mcpu=cortex-x1   < %s -o -| FileCheck %s --check-prefixes=CHECK,CHECK-8
+; RUN: llc -mtriple=aarch64-none-linux-gnu -mcpu=cortex-a75  < %s -o -| FileCheck %s --check-prefixes=CHECK,CHECK-8
+; RUN: llc -mtriple=aarch64-none-linux-gnu -mcpu=cortex-a510 < %s -o -| FileCheck %s --check-prefixes=CHECK,CHECK-8
 
 define i32 @a(i32 %x, i32* nocapture readonly %y, i32* nocapture readonly %z) {
 ; CHECK-DEFAULT:    .p2align 5
-; CHECK-N1:         .p2align 5, 0x0, 16
+; CHECK-8:          .p2align 5, 0x0, 8
+; CHECK-16:         .p2align 5, 0x0, 16
 ; CHECK-NEXT:       .LBB0_5: // %vector.body
 ; CHECK-DEFAULT:    .p2align 5
-; CHECK-N1:         .p2align 5, 0x0, 16
+; CHECK-8:          .p2align 5, 0x0, 8
+; CHECK-16:         .p2align 5, 0x0, 16
 ; CHECK-NEXT:       .LBB0_8: // %for.body
 entry:
   %cmp10 = icmp sgt i32 %x, 0
   br i1 %cmp10, label %for.body.preheader, label %for.cond.cleanup
 
 for.body.preheader:                               ; preds = %entry
   %wide.trip.count = zext i32 %x to i64
   %min.iters.check = icmp ult i32 %x, 8

llvm/test/CodeGen/AArch64/merge-store-dependency.ll

 ; A53-NEXT:    bl fcntl
 ; A53-NEXT:    adrp x9, gv0
 ; A53-NEXT:    add x9, x9, :lo12:gv0
 ; A53-NEXT:    cmp x19, x9
 ; A53-NEXT:    b.eq .LBB0_4
 ; A53-NEXT:  // %bb.1:
 ; A53-NEXT:    ldr w8, [x19]
 ; A53-NEXT:    ldr w9, [x9]
+; A53-NEXT:    .p2align 4, 0x0, 8
 ; A53-NEXT:  .LBB0_2: // %while.body.i.split.ver.us
 ; A53-NEXT:    // =>This Inner Loop Header: Depth=1
 ; A53-NEXT:    lsl w9, w9, #1
 ; A53-NEXT:    cmp w9, w8
 ; A53-NEXT:    b.le .LBB0_2
 ; A53-NEXT:  // %bb.3: // %while.end.i
 ; A53-NEXT:    bl foo
 ; A53-NEXT:    adrp x8, gv1
 ; A53-NEXT:    str x0, [x8, :lo12:gv1]
 ; A53-NEXT:    ldp x30, x19, [sp], #16 // 16-byte Folded Reload
 ; A53-NEXT:    ret
+; A53-NEXT:    .p2align 4, 0x0, 8
 ; A53-NEXT:  .LBB0_4: // %while.body.i.split
 ; A53-NEXT:    // =>This Inner Loop Header: Depth=1
 ; A53-NEXT:    b .LBB0_4
 entry:
   %0 = bitcast %struct1* %fde to i8*
   tail call void @llvm.memset.p0i8.i64(i8* align 8 %0, i8 0, i64 40, i1 false)
   %state = getelementptr inbounds %struct1, %struct1* %fde, i64 0, i32 4
   store i16 256, i16* %state, align 8