[AMDGPU] [NFC] Introduce subtargets check for MI hardware.

[foad]

I think predicate methods in GCNSubtarget should name particular features, like "hasAGPRs" and "hasAGPRToAGPRCopies" (probably not the best names because I don't know much about GFX90x features).

[rampitec]

llvm/lib/Target/AMDGPU/GCNSubtarget.h

997

It is a no action todo for now. You can just remove it.

[hsmhsm]

Fix review comments by Stas.

[rampitec]

What's the reason behind this? You are not even using it.

[hsmhsm]

In D122367#3407538, @rampitec wrote:

What's the reason behind this? You are not even using it.

I thought, it would be bit cleaner to use, for example ST.isGFX908Subtarget() compared to ST.hasMAIInsts() && !ST.hasGFX90AInsts().

So, if think, it does not make much sense, then I will ignore this patch, and abandon it.

llvm/lib/Target/AMDGPU/GCNSubtarget.h

public:
   bool needsAlignedVGPRs() const { return GFX90AInsts; }
 
   bool hasPackedTID() const { return HasPackedTID; }
 
   // GFX940 is a derivation to GFX90A. hasGFX940Insts() being true implies that
   // hasGFX90AInsts is also true.
   bool hasGFX940Insts() const { return GFX940Insts; }
 
+  bool isGFX908Subtarget() const { return HasMAIInsts && !GFX90AInsts; };
+
+  bool isGFX90ASubtarget() const { return GFX90AInsts && !GFX940Insts; };
+
+  bool isGFX940Subtarget() const { return GFX940Insts; };
+
   /// Return the maximum number of waves per SIMD for kernels using \p SGPRs
   /// SGPRs
   unsigned getOccupancyWithNumSGPRs(unsigned SGPRs) const;
 
   /// Return the maximum number of waves per SIMD for kernels using \p VGPRs
   /// VGPRs
   unsigned getOccupancyWithNumVGPRs(unsigned VGPRs) const;
 

llvm/lib/Target/AMDGPU/SIInstrInfo.cpp

 static void indirectCopyToAGPR(const SIInstrInfo &TII,
                                MachineBasicBlock &MBB,
                                MachineBasicBlock::iterator MI,
                                const DebugLoc &DL, MCRegister DestReg,
                                MCRegister SrcReg, bool KillSrc,
                                RegScavenger &RS,
                                Register ImpDefSuperReg = Register(),
                                Register ImpUseSuperReg = Register()) {
-  assert((TII.getSubtarget().hasMAIInsts() &&
-          !TII.getSubtarget().hasGFX90AInsts()) &&
+  assert(TII.getSubtarget().isGFX908Subtarget() &&
          "Expected GFX908 subtarget.");
 
   assert((AMDGPU::SReg_32RegClass.contains(SrcReg) ||
           AMDGPU::AGPR_32RegClass.contains(SrcReg)) &&
          "Source register of the copy should be either an SGPR or an AGPR.");
 
   assert(AMDGPU::AGPR_32RegClass.contains(DestReg) &&
          "Destination register of the copy should be an AGPR.");

llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp

BitVector SIRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
 
   for (unsigned i = MaxNumAGPRs; i < TotalNumVGPRs; ++i) {
     unsigned Reg = AMDGPU::AGPR_32RegClass.getRegister(i);
     reserveRegisterTuples(Reserved, Reg);
   }
 
   // On GFX908, in order to guarantee copying between AGPRs, we need a scratch
   // VGPR available at all times.
-  if (ST.hasMAIInsts() && !ST.hasGFX90AInsts()) {
+  if (ST.isGFX908Subtarget()) {
     reserveRegisterTuples(Reserved, AMDGPU::VGPR32);
   }
 
   for (auto Reg : MFI->WWMReservedRegs) {
     reserveRegisterTuples(Reserved, Reg.first);
   }
 
   // FIXME: Stop using reserved registers for this.