This is an archive of the discontinued LLVM Phabricator instance.

Differential D121570

[X86] Fix cosmetic issues in instruction mnemonics
ClosedPublic

Authored by Amir on Mar 13 2022, 10:58 PM.

Details

Reviewers
skan
MaskRay
craig.topper
GGanesh
Commits
rG842fa38dbeb7: [X86] Fix cosmetic issues in instruction mnemonics
Summary
  • Remove spurious } in invlpgb mnemonic
  • Add \t between mnemonic and operands for ud1 instructions

Diff Detail

Event Timeline

Amir created this revision.Mar 13 2022, 10:58 PM
Herald added a project: Restricted Project. · View Herald TranscriptMar 13 2022, 10:58 PM
Herald added subscribers: pengfei, hiraditya. · View Herald Transcript
Amir published this revision for review.Mar 13 2022, 11:07 PM
Herald added a project: Restricted Project. · View Herald TranscriptMar 13 2022, 11:07 PM
Herald added a subscriber: llvm-commits. · View Herald Transcript
Amir added a child revision: D121571: [TableGen] X86 mnemonic tables backend.Mar 13 2022, 11:11 PM
craig.topper accepted this revision.Mar 13 2022, 11:14 PM

LGTM

This revision is now accepted and ready to land.Mar 13 2022, 11:14 PM
Harbormaster completed remote builds in B154044: Diff 415007.Mar 13 2022, 11:34 PM
skan accepted this revision.Mar 14 2022, 12:14 AM

LGTM

This revision was landed with ongoing or failed builds.Mar 14 2022, 12:29 PM
Closed by commit rG842fa38dbeb7: [X86] Fix cosmetic issues in instruction mnemonics (authored by Amir). · Explain Why
This revision was automatically updated to reflect the committed changes.
Amir added a commit: rG842fa38dbeb7: [X86] Fix cosmetic issues in instruction mnemonics.

Revision Contents

PathSize
llvm/
lib/
Target/
X86/
2 lines
12 lines

Diff 415186

llvm/lib/Target/X86/X86InstrInfo.td

Show First 20 Lines • Show All 2,933 Lines • ▼ Show 20 Lines
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// INVLPGB Instruction // INVLPGB Instruction
// OPCODE 0F 01 FE // OPCODE 0F 01 FE
// //
let SchedRW = [WriteSystem] in { let SchedRW = [WriteSystem] in {
let Uses = [EAX, EDX] in let Uses = [EAX, EDX] in
def INVLPGB32 : I<0x01, MRM_FE, (outs), (ins), def INVLPGB32 : I<0x01, MRM_FE, (outs), (ins),
"invlpgb}", []>, "invlpgb", []>,
PS, Requires<[Not64BitMode]>; PS, Requires<[Not64BitMode]>;
let Uses = [RAX, EDX] in let Uses = [RAX, EDX] in
def INVLPGB64 : I<0x01, MRM_FE, (outs), (ins), def INVLPGB64 : I<0x01, MRM_FE, (outs), (ins),
"invlpgb", []>, "invlpgb", []>,
PS, Requires<[In64BitMode]>; PS, Requires<[In64BitMode]>;
} // SchedRW } // SchedRW
def : InstAlias<"invlpgb\t{%eax, %edx|eax, edx}", (INVLPGB32)>, Requires<[Not64BitMode]>; def : InstAlias<"invlpgb\t{%eax, %edx|eax, edx}", (INVLPGB32)>, Requires<[Not64BitMode]>;
▲ Show 20 Lines • Show All 796 Lines • Show Last 20 Lines

llvm/lib/Target/X86/X86InstrSystem.td

Show All 19 Lines
def RDTSCP : I<0x01, MRM_F9, (outs), (ins), "rdtscp", []>, TB; def RDTSCP : I<0x01, MRM_F9, (outs), (ins), "rdtscp", []>, TB;
// CPU flow control instructions // CPU flow control instructions
let mayLoad = 1, mayStore = 0, hasSideEffects = 1, isTrap = 1 in { let mayLoad = 1, mayStore = 0, hasSideEffects = 1, isTrap = 1 in {
def TRAP : I<0x0B, RawFrm, (outs), (ins), "ud2", [(trap)]>, TB; def TRAP : I<0x0B, RawFrm, (outs), (ins), "ud2", [(trap)]>, TB;
def UD1Wm : I<0xB9, MRMSrcMem, (outs), (ins GR16:$src1, i16mem:$src2), def UD1Wm : I<0xB9, MRMSrcMem, (outs), (ins GR16:$src1, i16mem:$src2),
"ud1{w} {$src2, $src1|$src1, $src2}", []>, TB, OpSize16; "ud1{w}\t{$src2, $src1|$src1, $src2}", []>, TB, OpSize16;
def UD1Lm : I<0xB9, MRMSrcMem, (outs), (ins GR32:$src1, i32mem:$src2), def UD1Lm : I<0xB9, MRMSrcMem, (outs), (ins GR32:$src1, i32mem:$src2),
"ud1{l} {$src2, $src1|$src1, $src2}", []>, TB, OpSize32; "ud1{l}\t{$src2, $src1|$src1, $src2}", []>, TB, OpSize32;
def UD1Qm : RI<0xB9, MRMSrcMem, (outs), (ins GR64:$src1, i64mem:$src2), def UD1Qm : RI<0xB9, MRMSrcMem, (outs), (ins GR64:$src1, i64mem:$src2),
"ud1{q} {$src2, $src1|$src1, $src2}", []>, TB; "ud1{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
def UD1Wr : I<0xB9, MRMSrcReg, (outs), (ins GR16:$src1, GR16:$src2), def UD1Wr : I<0xB9, MRMSrcReg, (outs), (ins GR16:$src1, GR16:$src2),
"ud1{w} {$src2, $src1|$src1, $src2}", []>, TB, OpSize16; "ud1{w}\t{$src2, $src1|$src1, $src2}", []>, TB, OpSize16;
def UD1Lr : I<0xB9, MRMSrcReg, (outs), (ins GR32:$src1, GR32:$src2), def UD1Lr : I<0xB9, MRMSrcReg, (outs), (ins GR32:$src1, GR32:$src2),
"ud1{l} {$src2, $src1|$src1, $src2}", []>, TB, OpSize32; "ud1{l}\t{$src2, $src1|$src1, $src2}", []>, TB, OpSize32;
def UD1Qr : RI<0xB9, MRMSrcReg, (outs), (ins GR64:$src1, GR64:$src2), def UD1Qr : RI<0xB9, MRMSrcReg, (outs), (ins GR64:$src1, GR64:$src2),
"ud1{q} {$src2, $src1|$src1, $src2}", []>, TB; "ud1{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
} }
let isTerminator = 1 in let isTerminator = 1 in
def HLT : I<0xF4, RawFrm, (outs), (ins), "hlt", []>; def HLT : I<0xF4, RawFrm, (outs), (ins), "hlt", []>;
def RSM : I<0xAA, RawFrm, (outs), (ins), "rsm", []>, TB; def RSM : I<0xAA, RawFrm, (outs), (ins), "rsm", []>, TB;
// Interrupt and SysCall Instructions. // Interrupt and SysCall Instructions.
let Uses = [EFLAGS] in let Uses = [EFLAGS] in
▲ Show 20 Lines • Show All 707 Lines • Show Last 20 Lines