[AArch64] Concat zip1 and zip2 is a wider zip1

[dmgreen]

Summary

Given concat(zip1(a, b), zip2(a, b)), we can convert that to a 128bit zip1(a, b) if we widen a and b out first.

Fixes #54226

[efriedma]

This combine seems a little fragile; I'd prefer a solution where generate the zip1 earlier. I'm concerned some combine will hide the specific concat(zip1, zip2) pattern this patch checks for.

But not sure hard that would be; the current patch is clearly an improvement, in any case.

[efriedma]

For example, consider the following, based on a testcase from https://github.com/llvm/llvm-project/issues/54226

u16 zip3(u8 a, u8 b) {
    char z;
    return u16{
        a[0],b[0],
        a[1],b[1],
        a[2],b[2],
        a[3],b[3],
        a[4],b[4],
        a[5],b[5],
        a[6],b[6],
        a[7],z
    };
}

[dmgreen]

@efriedma I wrote this quickly and didn't have a lot of time to look into doing it differently. I got another report of the same thing. What do you think about getting this version in? It seems like a simple improvement, especially from intrinsic code which is unlikely to include undef. And for test like @combine2_v8i16 they already include the concat from the beginning in a separate shuffle. The patch still applies as-is (with updated tests), and I could add a new test for the extra case you mention with a FIXME comment?

[efriedma]

Sure, that's fine.

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

if (N00->getOpcode() == ISD::EXTRACT_SUBVECTOR &&
 
         if (N00Index == N01Index && N10Index == N11Index && N00Index == 0 &&
             N10Index == N00VT.getVectorNumElements())
           return DAG.getNode(N0Opc, dl, VT, N00Source, N01Source);
       }
     }
   }
 
+  // concat(zip1(a, b), zip2(a, b)) is zip1(a, b)
+  if (N->getNumOperands() == 2 && N0Opc == AArch64ISD::ZIP1 &&
+      N1Opc == AArch64ISD::ZIP2 && N0.getOperand(0) == N1.getOperand(0) &&
+      N0.getOperand(1) == N1.getOperand(1)) {
+    SDValue E0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, N0.getOperand(0),
+                             DAG.getUNDEF(N0.getValueType()));
+    SDValue E1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, N0.getOperand(1),
+                             DAG.getUNDEF(N0.getValueType()));
+    return DAG.getNode(AArch64ISD::ZIP1, dl, VT, E0, E1);
+  }
+
   // If we see a (concat_vectors (v1x64 A), (v1x64 A)) it's really a vector
   // splat. The indexed instructions are going to be expecting a DUPLANE64, so
   // canonicalise to that.
   if (N->getNumOperands() == 2 && N0 == N1 && VT.getVectorNumElements() == 2) {
     assert(VT.getScalarSizeInBits() == 64);
     return DAG.getNode(AArch64ISD::DUPLANE64, dl, VT, WidenVector(N0, DAG),
                        DAG.getConstant(0, dl, MVT::i64));
   }

llvm/test/CodeGen/AArch64/arm64-zip.ll

; CHECK-NEXT:    ret
   %tmp4 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 8, i32 24, i32 9, i32 undef, i32 10, i32 26, i32 11, i32 27, i32 12, i32 28, i32 13, i32 undef, i32 14, i32 30, i32 undef, i32 31>
   %tmp5 = add <16 x i8> %tmp3, %tmp4
   ret <16 x i8> %tmp5
 }
 
 define <16 x i8> @combine_v16i8(<8 x i8> %0, <8 x i8> %1) {
 ; CHECK-LABEL: combine_v16i8:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    zip2.8b v2, v0, v1
-; CHECK-NEXT:    zip1.8b v0, v0, v1
-; CHECK-NEXT:    mov.d v0[1], v2[0]
+; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT:    // kill: def $d1 killed $d1 def $q1
+; CHECK-NEXT:    zip1.16b v0, v0, v1
 ; CHECK-NEXT:    ret
   %3 = shufflevector <8 x i8> %0, <8 x i8> %1, <16 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11, i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>
   ret <16 x i8> %3
 }
 
 define <16 x i8> @combine2_v16i8(<8 x i8> %0, <8 x i8> %1) {
 ; CHECK-LABEL: combine2_v16i8:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    zip1.8b v2, v0, v1
-; CHECK-NEXT:    zip2.8b v0, v0, v1
-; CHECK-NEXT:    mov.d v2[1], v0[0]
-; CHECK-NEXT:    mov.16b v0, v2
+; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT:    // kill: def $d1 killed $d1 def $q1
+; CHECK-NEXT:    zip1.16b v0, v0, v1
 ; CHECK-NEXT:    ret
   %3 = shufflevector <8 x i8> %0, <8 x i8> %1, <8 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11>
   %4 = shufflevector <8 x i8> %0, <8 x i8> %1, <8 x i32> <i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>
   %5 = shufflevector <8 x i8> %3, <8 x i8> %4, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
   ret <16 x i8> %5
 }
 
 define <8 x i16> @combine_v8i16(<4 x i16> %0, <4 x i16> %1) {
 ; CHECK-LABEL: combine_v8i16:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    zip2.4h v2, v0, v1
-; CHECK-NEXT:    zip1.4h v0, v0, v1
-; CHECK-NEXT:    mov.d v0[1], v2[0]
+; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT:    // kill: def $d1 killed $d1 def $q1
+; CHECK-NEXT:    zip1.8h v0, v0, v1
 ; CHECK-NEXT:    ret
   %3 = shufflevector <4 x i16> %0, <4 x i16> %1, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>
   ret <8 x i16> %3
 }
 
 define <8 x i16> @combine2_v8i16(<4 x i16> %0, <4 x i16> %1) {
 ; CHECK-LABEL: combine2_v8i16:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    zip1.4h v2, v0, v1
-; CHECK-NEXT:    zip2.4h v0, v0, v1
-; CHECK-NEXT:    mov.d v2[1], v0[0]
-; CHECK-NEXT:    mov.16b v0, v2
+; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT:    // kill: def $d1 killed $d1 def $q1
+; CHECK-NEXT:    zip1.8h v0, v0, v1
 ; CHECK-NEXT:    ret
   %3 = shufflevector <4 x i16> %0, <4 x i16> %1, <4 x i32> <i32 0, i32 4, i32 1, i32 5>
   %4 = shufflevector <4 x i16> %0, <4 x i16> %1, <4 x i32> <i32 2, i32 6, i32 3, i32 7>
   %5 = shufflevector <4 x i16> %3, <4 x i16> %4, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
   ret <8 x i16> %5
 }
 
 define <4 x i32> @combine_v4i32(<2 x i32> %0, <2 x i32> %1) {
 ; CHECK-LABEL: combine_v4i32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    zip2.2s v2, v0, v1
-; CHECK-NEXT:    zip1.2s v0, v0, v1
-; CHECK-NEXT:    mov.d v0[1], v2[0]
+; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT:    // kill: def $d1 killed $d1 def $q1
+; CHECK-NEXT:    zip1.4s v0, v0, v1
 ; CHECK-NEXT:    ret
   %3 = shufflevector <2 x i32> %0, <2 x i32> %1, <4 x i32> <i32 0, i32 2, i32 1, i32 3>
   ret <4 x i32> %3
 }
 
 define <4 x i32> @combine2_v4i32(<2 x i32> %0, <2 x i32> %1) {
 ; CHECK-LABEL: combine2_v4i32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    zip1.2s v2, v0, v1
-; CHECK-NEXT:    zip2.2s v0, v0, v1
-; CHECK-NEXT:    mov.d v2[1], v0[0]
-; CHECK-NEXT:    mov.16b v0, v2
+; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT:    // kill: def $d1 killed $d1 def $q1
+; CHECK-NEXT:    zip1.4s v0, v0, v1
 ; CHECK-NEXT:    ret
   %3 = shufflevector <2 x i32> %0, <2 x i32> %1, <2 x i32> <i32 0, i32 2>
   %4 = shufflevector <2 x i32> %0, <2 x i32> %1, <2 x i32> <i32 1, i32 3>
   %5 = shufflevector <2 x i32> %3, <2 x i32> %4, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
   ret <4 x i32> %5
 }
 
 define <16 x i8> @combine_v16i8_undef(<8 x i8> %0, <8 x i8> %1) {
 ; CHECK-LABEL: combine_v16i8_undef:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    zip2.8b v2, v0, v1
-; CHECK-NEXT:    zip1.8b v0, v0, v1
-; CHECK-NEXT:    mov.d v0[1], v2[0]
+; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT:    // kill: def $d1 killed $d1 def $q1
+; CHECK-NEXT:    zip1.16b v0, v0, v1
 ; CHECK-NEXT:    ret
   %3 = shufflevector <8 x i8> %0, <8 x i8> %1, <16 x i32> <i32 0, i32 undef, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11, i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>
   ret <16 x i8> %3
 }
 
 define <16 x i8> @combine2_v16i8_undef(<8 x i8> %0, <8 x i8> %1) {
 ; CHECK-LABEL: combine2_v16i8_undef:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    zip1.8b v2, v0, v1
-; CHECK-NEXT:    zip2.8b v0, v0, v1
-; CHECK-NEXT:    mov.d v2[1], v0[0]
-; CHECK-NEXT:    mov.16b v0, v2
+; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT:    // kill: def $d1 killed $d1 def $q1
+; CHECK-NEXT:    zip1.16b v0, v0, v1
 ; CHECK-NEXT:    ret
   %3 = shufflevector <8 x i8> %0, <8 x i8> %1, <8 x i32> <i32 0, i32 undef, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11>
   %4 = shufflevector <8 x i8> %0, <8 x i8> %1, <8 x i32> <i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>
   %5 = shufflevector <8 x i8> %3, <8 x i8> %4, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
   ret <16 x i8> %5
 }
 
 define <8 x i16> @combine_v8i16_undef(<4 x i16> %0, <4 x i16> %1) {
 ; CHECK-LABEL: combine_v8i16_undef:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    zip2.4h v2, v0, v1
-; CHECK-NEXT:    zip1.4h v0, v0, v1
-; CHECK-NEXT:    mov.d v0[1], v2[0]
+; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT:    // kill: def $d1 killed $d1 def $q1
+; CHECK-NEXT:    zip1.8h v0, v0, v1
 ; CHECK-NEXT:    ret
   %3 = shufflevector <4 x i16> %0, <4 x i16> %1, <8 x i32> <i32 0, i32 undef, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>
   ret <8 x i16> %3
 }
 
 ; FIXME: This could be zip1 too, 8,0,9,1... pattern is handled
 define <16 x i8> @combine_v8i16_8first(<8 x i8> %0, <8 x i8> %1) {
 ; CHECK-LABEL: combine_v8i16_8first:

llvm/test/CodeGen/AArch64/complex-deinterleaving-mixed-cases.ll

 ; CHECK-NEXT:    zip2 v4.2s, v2.2s, v3.2s
 ; CHECK-NEXT:    zip1 v1.2s, v1.2s, v5.2s
 ; CHECK-NEXT:    zip1 v2.2s, v2.2s, v3.2s
 ; CHECK-NEXT:    fmul v5.2s, v4.2s, v0.2s
 ; CHECK-NEXT:    fmul v3.2s, v1.2s, v4.2s
 ; CHECK-NEXT:    fneg v4.2s, v5.2s
 ; CHECK-NEXT:    fmla v3.2s, v0.2s, v2.2s
 ; CHECK-NEXT:    fmla v4.2s, v1.2s, v2.2s
-; CHECK-NEXT:    zip2 v1.2s, v4.2s, v3.2s
-; CHECK-NEXT:    zip1 v0.2s, v4.2s, v3.2s
-; CHECK-NEXT:    mov v0.d[1], v1.d[0]
+; CHECK-NEXT:    zip1 v0.4s, v4.4s, v3.4s
 ; CHECK-NEXT:    ret
 entry:
   %0 = fsub fast <4 x float> %b, %c
   %1 = shufflevector <4 x float> %0, <4 x float> poison, <2 x i32> <i32 0, i32 2>
   %strided.vec58 = shufflevector <4 x float> %c, <4 x float> poison, <2 x i32> <i32 0, i32 2>
   %strided.vec59 = shufflevector <4 x float> %c, <4 x float> poison, <2 x i32> <i32 1, i32 3>
   %2 = fmul fast <2 x float> %1, %strided.vec59
   %3 = fsub fast <4 x float> %b, %a

 ; CHECK-NEXT:    fmla v4.2s, v2.2s, v1.2s
 ; CHECK-NEXT:    fmul v1.2s, v1.2s, v5.2s
 ; CHECK-NEXT:    fmul v3.2s, v4.2s, v7.2s
 ; CHECK-NEXT:    fmla v1.2s, v2.2s, v6.2s
 ; CHECK-NEXT:    fmul v2.2s, v4.2s, v0.2s
 ; CHECK-NEXT:    fneg v3.2s, v3.2s
 ; CHECK-NEXT:    fmla v2.2s, v7.2s, v1.2s
 ; CHECK-NEXT:    fmla v3.2s, v0.2s, v1.2s
-; CHECK-NEXT:    zip2 v1.2s, v3.2s, v2.2s
-; CHECK-NEXT:    zip1 v0.2s, v3.2s, v2.2s
-; CHECK-NEXT:    mov v0.d[1], v1.d[0]
+; CHECK-NEXT:    zip1 v0.4s, v3.4s, v2.4s
 ; CHECK-NEXT:    ret
 entry:
   %strided.vec = shufflevector <4 x float> %c, <4 x float> poison, <2 x i32> <i32 0, i32 2>
   %strided.vec81 = shufflevector <4 x float> %c, <4 x float> poison, <2 x i32> <i32 1, i32 3>
   %strided.vec83 = shufflevector <4 x float> %b, <4 x float> poison, <2 x i32> <i32 0, i32 2>
   %strided.vec84 = shufflevector <4 x float> %b, <4 x float> poison, <2 x i32> <i32 1, i32 3>
   %0 = fmul fast <2 x float> %strided.vec84, %strided.vec
   %1 = fmul fast <2 x float> %strided.vec83, %strided.vec81

 ; CHECK-NEXT:    fmov d3, d7
 ; CHECK-NEXT:    fmov d16, d6
 ; CHECK-NEXT:    fmls v7.2s, v0.2s, v2.2s
 ; CHECK-NEXT:    fmla v6.2s, v0.2s, v4.2s
 ; CHECK-NEXT:    fmls v3.2s, v0.2s, v1.2s
 ; CHECK-NEXT:    fmla v16.2s, v0.2s, v5.2s
 ; CHECK-NEXT:    fsub v0.2s, v7.2s, v16.2s
 ; CHECK-NEXT:    fadd v1.2s, v6.2s, v3.2s
-; CHECK-NEXT:    zip2 v2.2s, v0.2s, v1.2s
-; CHECK-NEXT:    zip1 v0.2s, v0.2s, v1.2s
-; CHECK-NEXT:    mov v0.d[1], v2.d[0]
+; CHECK-NEXT:    zip1 v0.4s, v0.4s, v1.4s
 ; CHECK-NEXT:    ret
 entry:
   %ar = shufflevector <4 x float> %a, <4 x float> poison, <2 x i32> <i32 0, i32 2>
   %ai = shufflevector <4 x float> %a, <4 x float> poison, <2 x i32> <i32 1, i32 3>
   %br = shufflevector <4 x float> %b, <4 x float> poison, <2 x i32> <i32 0, i32 2>
   %bi = shufflevector <4 x float> %b, <4 x float> poison, <2 x i32> <i32 1, i32 3>
   %cr = shufflevector <4 x float> %c, <4 x float> poison, <2 x i32> <i32 0, i32 2>
   %ci = shufflevector <4 x float> %c, <4 x float> poison, <2 x i32> <i32 1, i32 3>

 ; CHECK-NEXT:    fneg v1.2s, v3.2s
 ; CHECK-NEXT:    fmul v3.2s, v2.2s, v4.2s
 ; CHECK-NEXT:    fmla v1.2s, v0.2s, v5.2s
 ; CHECK-NEXT:    fmul v5.2s, v2.2s, v0.2s
 ; CHECK-NEXT:    fneg v3.2s, v3.2s
 ; CHECK-NEXT:    fmla v5.2s, v4.2s, v1.2s
 ; CHECK-NEXT:    fmla v3.2s, v0.2s, v1.2s
 ; CHECK-NEXT:    mov v1.d[1], v2.d[0]
-; CHECK-NEXT:    zip2 v4.2s, v3.2s, v5.2s
-; CHECK-NEXT:    zip1 v0.2s, v3.2s, v5.2s
+; CHECK-NEXT:    zip1 v0.4s, v3.4s, v5.4s
 ; CHECK-NEXT:    str q1, [x0]
-; CHECK-NEXT:    mov v0.d[1], v4.d[0]
 ; CHECK-NEXT:    ret
 entry:
   %strided.vec = shufflevector <4 x float> %a, <4 x float> poison, <2 x i32> <i32 0, i32 2>
   %strided.vec35 = shufflevector <4 x float> %a, <4 x float> poison, <2 x i32> <i32 1, i32 3>
   %strided.vec37 = shufflevector <4 x float> %b, <4 x float> poison, <2 x i32> <i32 0, i32 2>
   %strided.vec38 = shufflevector <4 x float> %b, <4 x float> poison, <2 x i32> <i32 1, i32 3>
   %0 = fmul fast <2 x float> %strided.vec37, %strided.vec
   %1 = fmul fast <2 x float> %strided.vec38, %strided.vec35

llvm/test/CodeGen/AArch64/complex-deinterleaving-uniform-cases.ll

 ; CHECK-NEXT:    zip2 v0.2s, v0.2s, v2.2s
 ; CHECK-NEXT:    zip2 v5.2s, v1.2s, v3.2s
 ; CHECK-NEXT:    zip1 v1.2s, v1.2s, v3.2s
 ; CHECK-NEXT:    fmul v2.2s, v5.2s, v4.2s
 ; CHECK-NEXT:    fmul v3.2s, v1.2s, v4.2s
 ; CHECK-NEXT:    fmul v4.2s, v0.2s, v5.2s
 ; CHECK-NEXT:    fmla v2.2s, v0.2s, v1.2s
 ; CHECK-NEXT:    fsub v0.2s, v3.2s, v4.2s
-; CHECK-NEXT:    zip2 v1.2s, v0.2s, v2.2s
-; CHECK-NEXT:    zip1 v0.2s, v0.2s, v2.2s
-; CHECK-NEXT:    mov v0.d[1], v1.d[0]
+; CHECK-NEXT:    zip1 v0.4s, v0.4s, v2.4s
 ; CHECK-NEXT:    ret
 entry:
   %strided.vec = shufflevector <4 x float> %a, <4 x float> poison, <2 x i32> <i32 0, i32 2>
   %strided.vec17 = shufflevector <4 x float> %a, <4 x float> poison, <2 x i32> <i32 1, i32 3>
   %strided.vec19 = shufflevector <4 x float> %b, <4 x float> poison, <2 x i32> <i32 0, i32 2>
   %strided.vec20 = shufflevector <4 x float> %b, <4 x float> poison, <2 x i32> <i32 1, i32 3>
   %0 = fmul fast <2 x float> %strided.vec20, %strided.vec
   %1 = fmul fast <2 x float> %strided.vec19, %strided.vec17

 ; CHECK-NEXT:    ext v2.16b, v0.16b, v0.16b, #8
 ; CHECK-NEXT:    ext v3.16b, v1.16b, v1.16b, #8
 ; CHECK-NEXT:    zip1 v4.2s, v0.2s, v2.2s
 ; CHECK-NEXT:    zip2 v0.2s, v0.2s, v2.2s
 ; CHECK-NEXT:    zip1 v2.2s, v1.2s, v3.2s
 ; CHECK-NEXT:    zip2 v1.2s, v1.2s, v3.2s
 ; CHECK-NEXT:    fadd v1.2s, v1.2s, v4.2s
 ; CHECK-NEXT:    fsub v0.2s, v0.2s, v2.2s
-; CHECK-NEXT:    zip2 v2.2s, v1.2s, v0.2s
-; CHECK-NEXT:    zip1 v0.2s, v1.2s, v0.2s
-; CHECK-NEXT:    mov v0.d[1], v2.d[0]
+; CHECK-NEXT:    zip1 v0.4s, v1.4s, v0.4s
 ; CHECK-NEXT:    ret
 entry:
   %strided.vec = shufflevector <4 x float> %a, <4 x float> poison, <2 x i32> <i32 0, i32 2>
   %strided.vec17 = shufflevector <4 x float> %a, <4 x float> poison, <2 x i32> <i32 1, i32 3>
   %strided.vec19 = shufflevector <4 x float> %b, <4 x float> poison, <2 x i32> <i32 0, i32 2>
   %strided.vec20 = shufflevector <4 x float> %b, <4 x float> poison, <2 x i32> <i32 1, i32 3>
   %0 = fadd fast <2 x float> %strided.vec20, %strided.vec
   %1 = fsub fast <2 x float> %strided.vec17, %strided.vec19

 ; CHECK-NEXT:    ext v2.16b, v0.16b, v0.16b, #8
 ; CHECK-NEXT:    ext v3.16b, v1.16b, v1.16b, #8
 ; CHECK-NEXT:    zip1 v4.2s, v0.2s, v2.2s
 ; CHECK-NEXT:    zip2 v0.2s, v0.2s, v2.2s
 ; CHECK-NEXT:    zip1 v2.2s, v1.2s, v3.2s
 ; CHECK-NEXT:    zip2 v1.2s, v1.2s, v3.2s
 ; CHECK-NEXT:    fsub v1.2s, v4.2s, v1.2s
 ; CHECK-NEXT:    fadd v0.2s, v0.2s, v2.2s
-; CHECK-NEXT:    zip2 v2.2s, v1.2s, v0.2s
-; CHECK-NEXT:    zip1 v0.2s, v1.2s, v0.2s
-; CHECK-NEXT:    mov v0.d[1], v2.d[0]
+; CHECK-NEXT:    zip1 v0.4s, v1.4s, v0.4s
 ; CHECK-NEXT:    ret
 entry:
   %a.real = shufflevector <4 x float> %a, <4 x float> poison, <2 x i32> <i32 0, i32 2>
   %a.imag = shufflevector <4 x float> %a, <4 x float> poison, <2 x i32> <i32 1, i32 3>
   %b.real = shufflevector <4 x float> %b, <4 x float> poison, <2 x i32> <i32 0, i32 2>
   %b.imag = shufflevector <4 x float> %b, <4 x float> poison, <2 x i32> <i32 1, i32 3>
   %0 = fsub fast <2 x float> %a.real, %b.imag
   %1 = fadd fast <2 x float> %a.imag, %b.real