This is an archive of the discontinued LLVM Phabricator instance.

Differential D121039

[LegalizeTypes][ARM][X86] Change ExpandIntRes_ABS to use sra+xor+sub.
ClosedPublic

Authored by craig.topper on Mar 4 2022, 6:58 PM.

Details

Reviewers
RKSimon
spatel
Commits
rG8e132c5c1d4c: [LegalizeTypes][ARM][X86] Change ExpandIntRes_ABS to use sra+xor+sub.
Summary

Previously we used sra+add+xor if ADDCARRY is supported. This changes
to sra+xor+sub is SUBCARRY is available.

This is consistent with the recent change to the default expansion
in LegalizeDAG.

Diff Detail

Event Timeline

craig.topper created this revision.Mar 4 2022, 6:58 PM
Herald added a project: Restricted Project. · View Herald TranscriptMar 4 2022, 6:58 PM
Herald added subscribers: pengfei, dmgreen, hiraditya and 2 others. · View Herald Transcript
craig.topper requested review of this revision.Mar 4 2022, 6:58 PM
Herald added a project: Restricted Project. · View Herald TranscriptMar 4 2022, 6:58 PM
Harbormaster completed remote builds in B152707: Diff 413186.Mar 4 2022, 7:21 PM
RKSimon accepted this revision.Mar 7 2022, 7:19 AM

LGTM

This revision is now accepted and ready to land.Mar 7 2022, 7:19 AM
This revision was landed with ongoing or failed builds.Mar 7 2022, 11:28 AM
Closed by commit rG8e132c5c1d4c: [LegalizeTypes][ARM][X86] Change ExpandIntRes_ABS to use sra+xor+sub. (authored by craig.topper). · Explain Why
This revision was automatically updated to reflect the committed changes.
craig.topper added a commit: rG8e132c5c1d4c: [LegalizeTypes][ARM][X86] Change ExpandIntRes_ABS to use sra+xor+sub..

Revision Contents

PathSize
llvm/
lib/
CodeGen/
SelectionDAG/
18 lines
test/
CodeGen/
ARM/
6 lines
Thumb2/
20 lines
68 lines
X86/
37 lines
37 lines
50 lines
tools/
UpdateTestChecks/
update_llc_test_checks/
Inputs/
6 lines

Diff 413568

llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp

Show First 20 Lines • Show All 3,126 Lines • ▼ Show 20 Lines
void DAGTypeLegalizer::ExpandIntRes_ABS(SDNode *N, SDValue &Lo, SDValue &Hi) { void DAGTypeLegalizer::ExpandIntRes_ABS(SDNode *N, SDValue &Lo, SDValue &Hi) {
SDLoc dl(N); SDLoc dl(N);
SDValue N0 = N->getOperand(0); SDValue N0 = N->getOperand(0);
GetExpandedInteger(N0, Lo, Hi); GetExpandedInteger(N0, Lo, Hi);
EVT NVT = Lo.getValueType(); EVT NVT = Lo.getValueType();
// If we have ADDCARRY, use the expanded form of the sra+add+xor sequence we // If we have SUBCARRY, use the expanded form of the sra+xor+sub sequence we
// use in LegalizeDAG. The ADD part of the expansion is based on // use in LegalizeDAG. The SUB part of the expansion is based on
// ExpandIntRes_ADDSUB which also uses ADDCARRY/UADDO after checking that // ExpandIntRes_ADDSUB which also uses SUBCARRY/USUBO after checking that
// ADDCARRY is LegalOrCustom. Each of the pieces here can be further expanded // SUBCARRY is LegalOrCustom. Each of the pieces here can be further expanded
// if needed. Shift expansion has a special case for filling with sign bits // if needed. Shift expansion has a special case for filling with sign bits
// so that we will only end up with one SRA. // so that we will only end up with one SRA.
bool HasAddCarry = TLI.isOperationLegalOrCustom( bool HasSubCarry = TLI.isOperationLegalOrCustom(
ISD::ADDCARRY, TLI.getTypeToExpandTo(*DAG.getContext(), NVT)); ISD::SUBCARRY, TLI.getTypeToExpandTo(*DAG.getContext(), NVT));
if (HasAddCarry) { if (HasSubCarry) {
EVT ShiftAmtTy = TLI.getShiftAmountTy(NVT, DAG.getDataLayout()); EVT ShiftAmtTy = TLI.getShiftAmountTy(NVT, DAG.getDataLayout());
SDValue Sign = SDValue Sign =
DAG.getNode(ISD::SRA, dl, NVT, Hi, DAG.getNode(ISD::SRA, dl, NVT, Hi,
DAG.getConstant(NVT.getSizeInBits() - 1, dl, ShiftAmtTy)); DAG.getConstant(NVT.getSizeInBits() - 1, dl, ShiftAmtTy));
SDVTList VTList = DAG.getVTList(NVT, getSetCCResultType(NVT)); SDVTList VTList = DAG.getVTList(NVT, getSetCCResultType(NVT));
Lo = DAG.getNode(ISD::UADDO, dl, VTList, Lo, Sign);
Hi = DAG.getNode(ISD::ADDCARRY, dl, VTList, Hi, Sign, Lo.getValue(1));
Lo = DAG.getNode(ISD::XOR, dl, NVT, Lo, Sign); Lo = DAG.getNode(ISD::XOR, dl, NVT, Lo, Sign);
Hi = DAG.getNode(ISD::XOR, dl, NVT, Hi, Sign); Hi = DAG.getNode(ISD::XOR, dl, NVT, Hi, Sign);
Lo = DAG.getNode(ISD::USUBO, dl, VTList, Lo, Sign);
Hi = DAG.getNode(ISD::SUBCARRY, dl, VTList, Hi, Sign, Lo.getValue(1));
return; return;
} }
// abs(HiLo) -> (Hi < 0 ? -HiLo : HiLo) // abs(HiLo) -> (Hi < 0 ? -HiLo : HiLo)
EVT VT = N->getValueType(0); EVT VT = N->getValueType(0);
SDValue Neg = DAG.getNode(ISD::SUB, dl, VT, SDValue Neg = DAG.getNode(ISD::SUB, dl, VT,
DAG.getConstant(0, dl, VT), N0); DAG.getConstant(0, dl, VT), N0);
SDValue NegLo, NegHi; SDValue NegLo, NegHi;
▲ Show 20 Lines • Show All 2,165 Lines • Show Last 20 Lines

llvm/test/CodeGen/ARM/iabs.ll

Show All 30 Lines; CHECK-NEXT: bx
%sub1 = sub nsw i32 0, %sub %sub1 = sub nsw i32 0, %sub
%cond = select i1 %cmp, i32 %sub, i32 %sub1 %cond = select i1 %cmp, i32 %sub, i32 %sub1
ret i32 %cond ret i32 %cond
} }
define i64 @test3(i64 %a) { define i64 @test3(i64 %a) {
; CHECK-LABEL: test3: ; CHECK-LABEL: test3:
; CHECK: @ %bb.0: ; CHECK: @ %bb.0:
; CHECK-NEXT: adds r0, r0, r1, asr #31
; CHECK-NEXT: adc r2, r1, r1, asr #31
; CHECK-NEXT: eor r0, r0, r1, asr #31 ; CHECK-NEXT: eor r0, r0, r1, asr #31
; CHECK-NEXT: eor r1, r2, r1, asr #31 ; CHECK-NEXT: eor r2, r1, r1, asr #31
; CHECK-NEXT: subs r0, r0, r1, asr #31
; CHECK-NEXT: sbc r1, r2, r1, asr #31
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
%tmp1neg = sub i64 0, %a %tmp1neg = sub i64 0, %a
%b = icmp sgt i64 %a, -1 %b = icmp sgt i64 %a, -1
%abs = select i1 %b, i64 %a, i64 %tmp1neg %abs = select i1 %b, i64 %a, i64 %tmp1neg
ret i64 %abs ret i64 %abs
} }

llvm/test/CodeGen/Thumb2/mve-abs.ll

Show All 35 Linesentry:
%2 = select <4 x i1> %0, <4 x i32> %1, <4 x i32> %s1 %2 = select <4 x i1> %0, <4 x i32> %1, <4 x i32> %s1
ret <4 x i32> %2 ret <4 x i32> %2
} }
define arm_aapcs_vfpcc <2 x i64> @abs_v2i64(<2 x i64> %s1) { define arm_aapcs_vfpcc <2 x i64> @abs_v2i64(<2 x i64> %s1) {
; CHECK-LABEL: abs_v2i64: ; CHECK-LABEL: abs_v2i64:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov r0, r1, d1 ; CHECK-NEXT: vmov r0, r1, d1
; CHECK-NEXT: vmov r3, r2, d0
; CHECK-NEXT: adds.w r0, r0, r1, asr #31
; CHECK-NEXT: adc.w r12, r1, r1, asr #31
; CHECK-NEXT: adds.w r3, r3, r2, asr #31
; CHECK-NEXT: eor.w r0, r0, r1, asr #31 ; CHECK-NEXT: eor.w r0, r0, r1, asr #31
; CHECK-NEXT: eor.w r3, r3, r2, asr #31 ; CHECK-NEXT: eor.w r2, r1, r1, asr #31
; CHECK-NEXT: vmov q0[2], q0[0], r3, r0 ; CHECK-NEXT: subs.w r0, r0, r1, asr #31
; CHECK-NEXT: eor.w r0, r12, r1, asr #31 ; CHECK-NEXT: sbc.w r1, r2, r1, asr #31
; CHECK-NEXT: adc.w r1, r2, r2, asr #31 ; CHECK-NEXT: vmov r2, r3, d0
; CHECK-NEXT: eor.w r1, r1, r2, asr #31 ; CHECK-NEXT: eor.w r2, r2, r3, asr #31
; CHECK-NEXT: vmov q0[3], q0[1], r1, r0 ; CHECK-NEXT: subs.w r2, r2, r3, asr #31
; CHECK-NEXT: vmov q0[2], q0[0], r2, r0
; CHECK-NEXT: eor.w r0, r3, r3, asr #31
; CHECK-NEXT: sbc.w r0, r0, r3, asr #31
; CHECK-NEXT: vmov q0[3], q0[1], r0, r1
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = icmp slt <2 x i64> %s1, zeroinitializer %0 = icmp slt <2 x i64> %s1, zeroinitializer
%1 = sub nsw <2 x i64> zeroinitializer, %s1 %1 = sub nsw <2 x i64> zeroinitializer, %s1
%2 = select <2 x i1> %0, <2 x i64> %1, <2 x i64> %s1 %2 = select <2 x i1> %0, <2 x i64> %1, <2 x i64> %s1
ret <2 x i64> %2 ret <2 x i64> %2
} }

llvm/test/CodeGen/Thumb2/mve-vabdus.ll

Show First 20 Lines • Show All 97 Lines • ▼ Show 20 Lines; CHECK-NEXT: bx lr
%s = select <4 x i1> %c, <4 x i64> %add1, <4 x i64> %add2 %s = select <4 x i1> %c, <4 x i64> %add1, <4 x i64> %add2
%result = trunc <4 x i64> %s to <4 x i32> %result = trunc <4 x i64> %s to <4 x i32>
ret <4 x i32> %result ret <4 x i32> %result
} }
define arm_aapcs_vfpcc <2 x i32> @vabd_v2s32(<2 x i32> %src1, <2 x i32> %src2) { define arm_aapcs_vfpcc <2 x i32> @vabd_v2s32(<2 x i32> %src1, <2 x i32> %src2) {
; CHECK-LABEL: vabd_v2s32: ; CHECK-LABEL: vabd_v2s32:
; CHECK: @ %bb.0: ; CHECK: @ %bb.0:
; CHECK-NEXT: .save {r7, lr}
; CHECK-NEXT: push {r7, lr}
; CHECK-NEXT: vmov r0, s2 ; CHECK-NEXT: vmov r0, s2
; CHECK-NEXT: vmov r2, s6 ; CHECK-NEXT: vmov r2, s6
; CHECK-NEXT: vmov r3, s0
; CHECK-NEXT: asrs r1, r0, #31 ; CHECK-NEXT: asrs r1, r0, #31
; CHECK-NEXT: subs r0, r0, r2 ; CHECK-NEXT: subs r0, r0, r2
; CHECK-NEXT: sbc.w r1, r1, r2, asr #31 ; CHECK-NEXT: sbc.w r1, r1, r2, asr #31
; CHECK-NEXT: asrs r2, r3, #31 ; CHECK-NEXT: eor.w r0, r0, r1, asr #31
; CHECK-NEXT: adds.w r0, r0, r1, asr #31 ; CHECK-NEXT: eor.w r2, r1, r1, asr #31
; CHECK-NEXT: eor.w lr, r0, r1, asr #31 ; CHECK-NEXT: subs.w r0, r0, r1, asr #31
; CHECK-NEXT: vmov r0, s4 ; CHECK-NEXT: sbc.w r12, r2, r1, asr #31
; CHECK-NEXT: adc.w r12, r1, r1, asr #31 ; CHECK-NEXT: vmov r2, s0
; CHECK-NEXT: eor.w r1, r12, r1, asr #31 ; CHECK-NEXT: vmov r1, s4
; CHECK-NEXT: subs r3, r3, r0 ; CHECK-NEXT: asrs r3, r2, #31
; CHECK-NEXT: sbc.w r0, r2, r0, asr #31 ; CHECK-NEXT: subs r2, r2, r1
; CHECK-NEXT: adds.w r2, r3, r0, asr #31 ; CHECK-NEXT: sbc.w r1, r3, r1, asr #31
; CHECK-NEXT: eor.w r2, r2, r0, asr #31 ; CHECK-NEXT: eor.w r2, r2, r1, asr #31
; CHECK-NEXT: vmov q0[2], q0[0], r2, lr ; CHECK-NEXT: subs.w r2, r2, r1, asr #31
; CHECK-NEXT: adc.w r2, r0, r0, asr #31 ; CHECK-NEXT: vmov q0[2], q0[0], r2, r0
; CHECK-NEXT: eor.w r0, r2, r0, asr #31 ; CHECK-NEXT: eor.w r0, r1, r1, asr #31
; CHECK-NEXT: vmov q0[3], q0[1], r0, r1 ; CHECK-NEXT: sbc.w r0, r0, r1, asr #31
; CHECK-NEXT: pop {r7, pc} ; CHECK-NEXT: vmov q0[3], q0[1], r0, r12
; CHECK-NEXT: bx lr
%sextsrc1 = sext <2 x i32> %src1 to <2 x i64> %sextsrc1 = sext <2 x i32> %src1 to <2 x i64>
%sextsrc2 = sext <2 x i32> %src2 to <2 x i64> %sextsrc2 = sext <2 x i32> %src2 to <2 x i64>
%add1 = sub <2 x i64> %sextsrc1, %sextsrc2 %add1 = sub <2 x i64> %sextsrc1, %sextsrc2
%add2 = sub <2 x i64> zeroinitializer, %add1 %add2 = sub <2 x i64> zeroinitializer, %add1
%c = icmp sge <2 x i64> %add1, zeroinitializer %c = icmp sge <2 x i64> %add1, zeroinitializer
%s = select <2 x i1> %c, <2 x i64> %add1, <2 x i64> %add2 %s = select <2 x i1> %c, <2 x i64> %add1, <2 x i64> %add2
%result = trunc <2 x i64> %s to <2 x i32> %result = trunc <2 x i64> %s to <2 x i32>
ret <2 x i32> %result ret <2 x i32> %result
▲ Show 20 Lines • Show All 110 Lines • ▼ Show 20 Lines; CHECK-NEXT: bx lr
%s = select <4 x i1> %c, <4 x i64> %add1, <4 x i64> %add2 %s = select <4 x i1> %c, <4 x i64> %add1, <4 x i64> %add2
%result = trunc <4 x i64> %s to <4 x i32> %result = trunc <4 x i64> %s to <4 x i32>
ret <4 x i32> %result ret <4 x i32> %result
} }
define arm_aapcs_vfpcc <2 x i32> @vabd_v2u32(<2 x i32> %src1, <2 x i32> %src2) { define arm_aapcs_vfpcc <2 x i32> @vabd_v2u32(<2 x i32> %src1, <2 x i32> %src2) {
; CHECK-LABEL: vabd_v2u32: ; CHECK-LABEL: vabd_v2u32:
; CHECK: @ %bb.0: ; CHECK: @ %bb.0:
; CHECK-NEXT: .save {r4, lr} ; CHECK-NEXT: .save {r7, lr}
; CHECK-NEXT: push {r4, lr} ; CHECK-NEXT: push {r7, lr}
; CHECK-NEXT: vmov.i64 q2, #0xffffffff ; CHECK-NEXT: vmov.i64 q2, #0xffffffff
; CHECK-NEXT: vand q1, q1, q2 ; CHECK-NEXT: vand q1, q1, q2
; CHECK-NEXT: vand q0, q0, q2 ; CHECK-NEXT: vand q0, q0, q2
; CHECK-NEXT: vmov r0, r1, d3 ; CHECK-NEXT: vmov r0, r1, d3
; CHECK-NEXT: vmov r2, r3, d1 ; CHECK-NEXT: vmov r2, r3, d1
; CHECK-NEXT: subs r0, r2, r0 ; CHECK-NEXT: subs r0, r2, r0
; CHECK-NEXT: sbc.w r1, r3, r1 ; CHECK-NEXT: sbc.w r1, r3, r1
; CHECK-NEXT: vmov r3, r2, d2 ; CHECK-NEXT: eor.w r0, r0, r1, asr #31
; CHECK-NEXT: adds.w r0, r0, r1, asr #31 ; CHECK-NEXT: eor.w r2, r1, r1, asr #31
; CHECK-NEXT: eor.w lr, r0, r1, asr #31 ; CHECK-NEXT: subs.w lr, r0, r1, asr #31
; CHECK-NEXT: vmov r0, r4, d0 ; CHECK-NEXT: sbc.w r12, r2, r1, asr #31
; CHECK-NEXT: adc.w r12, r1, r1, asr #31 ; CHECK-NEXT: vmov r2, r3, d2
; CHECK-NEXT: subs r0, r0, r3 ; CHECK-NEXT: vmov r1, r0, d0
; CHECK-NEXT: sbc.w r2, r4, r2 ; CHECK-NEXT: subs r1, r1, r2
; CHECK-NEXT: adds.w r0, r0, r2, asr #31 ; CHECK-NEXT: sbcs r0, r3
; CHECK-NEXT: eor.w r0, r0, r2, asr #31 ; CHECK-NEXT: eor.w r1, r1, r0, asr #31
; CHECK-NEXT: vmov q0[2], q0[0], r0, lr ; CHECK-NEXT: subs.w r1, r1, r0, asr #31
; CHECK-NEXT: eor.w r0, r12, r1, asr #31 ; CHECK-NEXT: vmov q0[2], q0[0], r1, lr
; CHECK-NEXT: adc.w r1, r2, r2, asr #31 ; CHECK-NEXT: eor.w r1, r0, r0, asr #31
; CHECK-NEXT: eor.w r1, r1, r2, asr #31 ; CHECK-NEXT: sbc.w r0, r1, r0, asr #31
; CHECK-NEXT: vmov q0[3], q0[1], r1, r0 ; CHECK-NEXT: vmov q0[3], q0[1], r0, r12
; CHECK-NEXT: pop {r4, pc} ; CHECK-NEXT: pop {r7, pc}
%zextsrc1 = zext <2 x i32> %src1 to <2 x i64> %zextsrc1 = zext <2 x i32> %src1 to <2 x i64>
%zextsrc2 = zext <2 x i32> %src2 to <2 x i64> %zextsrc2 = zext <2 x i32> %src2 to <2 x i64>
%add1 = sub <2 x i64> %zextsrc1, %zextsrc2 %add1 = sub <2 x i64> %zextsrc1, %zextsrc2
%add2 = sub <2 x i64> zeroinitializer, %add1 %add2 = sub <2 x i64> zeroinitializer, %add1
%c = icmp sge <2 x i64> %add1, zeroinitializer %c = icmp sge <2 x i64> %add1, zeroinitializer
%s = select <2 x i1> %c, <2 x i64> %add1, <2 x i64> %add2 %s = select <2 x i1> %c, <2 x i64> %add1, <2 x i64> %add2
%result = trunc <2 x i64> %s to <2 x i32> %result = trunc <2 x i64> %s to <2 x i32>
ret <2 x i32> %result ret <2 x i32> %result
▲ Show 20 Lines • Show All 349 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/abs.ll

Show First 20 Lines • Show All 113 Lines • ▼ Show 20 Lines
; X64-NEXT: cmovsq %rdi, %rax ; X64-NEXT: cmovsq %rdi, %rax
; X64-NEXT: retq ; X64-NEXT: retq
; ;
; X86-LABEL: test_i64: ; X86-LABEL: test_i64:
; X86: # %bb.0: ; X86: # %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %edx ; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-NEXT: movl %edx, %ecx ; X86-NEXT: movl %edx, %ecx
; X86-NEXT: sarl $31, %ecx ; X86-NEXT: sarl $31, %ecx
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: addl %ecx, %eax
; X86-NEXT: adcl %ecx, %edx
; X86-NEXT: xorl %ecx, %edx ; X86-NEXT: xorl %ecx, %edx
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: xorl %ecx, %eax ; X86-NEXT: xorl %ecx, %eax
; X86-NEXT: subl %ecx, %eax
; X86-NEXT: sbbl %ecx, %edx
; X86-NEXT: retl ; X86-NEXT: retl
%r = call i64 @llvm.abs.i64(i64 %a, i1 false) %r = call i64 @llvm.abs.i64(i64 %a, i1 false)
ret i64 %r ret i64 %r
} }
define i128 @test_i128(i128 %a) nounwind { define i128 @test_i128(i128 %a) nounwind {
; X64-LABEL: test_i128: ; X64-LABEL: test_i128:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: movq %rdi, %rax
; X64-NEXT: movq %rsi, %rdx ; X64-NEXT: movq %rsi, %rdx
; X64-NEXT: sarq $63, %rdx ; X64-NEXT: movq %rdi, %rax
; X64-NEXT: addq %rdx, %rax ; X64-NEXT: movq %rsi, %rcx
; X64-NEXT: adcq %rdx, %rsi ; X64-NEXT: sarq $63, %rcx
; X64-NEXT: xorq %rdx, %rax ; X64-NEXT: xorq %rcx, %rdx
; X64-NEXT: xorq %rsi, %rdx ; X64-NEXT: xorq %rcx, %rax
; X64-NEXT: subq %rcx, %rax
; X64-NEXT: sbbq %rcx, %rdx
; X64-NEXT: retq ; X64-NEXT: retq
; ;
; X86-LABEL: test_i128: ; X86-LABEL: test_i128:
; X86: # %bb.0: ; X86: # %bb.0:
; X86-NEXT: pushl %ebx ; X86-NEXT: pushl %ebx
; X86-NEXT: pushl %edi ; X86-NEXT: pushl %edi
; X86-NEXT: pushl %esi ; X86-NEXT: pushl %esi
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: movl %ecx, %edx ; X86-NEXT: movl %ecx, %edx
; X86-NEXT: sarl $31, %edx ; X86-NEXT: sarl $31, %edx
; X86-NEXT: xorl %edx, %ecx
; X86-NEXT: movl {{[0-9]+}}(%esp), %esi ; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-NEXT: addl %edx, %esi ; X86-NEXT: xorl %edx, %esi
; X86-NEXT: movl {{[0-9]+}}(%esp), %edi ; X86-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-NEXT: adcl %edx, %edi ; X86-NEXT: xorl %edx, %edi
; X86-NEXT: movl {{[0-9]+}}(%esp), %ebx ; X86-NEXT: movl {{[0-9]+}}(%esp), %ebx
; X86-NEXT: adcl %edx, %ebx
; X86-NEXT: adcl %edx, %ecx
; X86-NEXT: xorl %edx, %ecx
; X86-NEXT: xorl %edx, %ebx ; X86-NEXT: xorl %edx, %ebx
; X86-NEXT: xorl %edx, %edi ; X86-NEXT: subl %edx, %ebx
; X86-NEXT: xorl %edx, %esi ; X86-NEXT: sbbl %edx, %edi
; X86-NEXT: movl %esi, (%eax) ; X86-NEXT: sbbl %edx, %esi
; X86-NEXT: sbbl %edx, %ecx
; X86-NEXT: movl %ebx, (%eax)
; X86-NEXT: movl %edi, 4(%eax) ; X86-NEXT: movl %edi, 4(%eax)
; X86-NEXT: movl %ebx, 8(%eax) ; X86-NEXT: movl %esi, 8(%eax)
; X86-NEXT: movl %ecx, 12(%eax) ; X86-NEXT: movl %ecx, 12(%eax)
; X86-NEXT: popl %esi ; X86-NEXT: popl %esi
; X86-NEXT: popl %edi ; X86-NEXT: popl %edi
; X86-NEXT: popl %ebx ; X86-NEXT: popl %ebx
; X86-NEXT: retl $4 ; X86-NEXT: retl $4
%r = call i128 @llvm.abs.i128(i128 %a, i1 false) %r = call i128 @llvm.abs.i128(i128 %a, i1 false)
ret i128 %r ret i128 %r
} }
▲ Show 20 Lines • Show All 438 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/iabs.ll

Show First 20 Lines • Show All 95 Lines • ▼ Show 20 Lines
} }
define i64 @test_i64(i64 %a) nounwind { define i64 @test_i64(i64 %a) nounwind {
; X86-LABEL: test_i64: ; X86-LABEL: test_i64:
; X86: # %bb.0: ; X86: # %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %edx ; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-NEXT: movl %edx, %ecx ; X86-NEXT: movl %edx, %ecx
; X86-NEXT: sarl $31, %ecx ; X86-NEXT: sarl $31, %ecx
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: addl %ecx, %eax
; X86-NEXT: adcl %ecx, %edx
; X86-NEXT: xorl %ecx, %edx ; X86-NEXT: xorl %ecx, %edx
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: xorl %ecx, %eax ; X86-NEXT: xorl %ecx, %eax
; X86-NEXT: subl %ecx, %eax
; X86-NEXT: sbbl %ecx, %edx
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-LABEL: test_i64: ; X64-LABEL: test_i64:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: movq %rdi, %rax ; X64-NEXT: movq %rdi, %rax
; X64-NEXT: negq %rax ; X64-NEXT: negq %rax
; X64-NEXT: cmovsq %rdi, %rax ; X64-NEXT: cmovsq %rdi, %rax
; X64-NEXT: retq ; X64-NEXT: retq
%tmp1neg = sub i64 0, %a %tmp1neg = sub i64 0, %a
%b = icmp sgt i64 %a, -1 %b = icmp sgt i64 %a, -1
%abs = select i1 %b, i64 %a, i64 %tmp1neg %abs = select i1 %b, i64 %a, i64 %tmp1neg
ret i64 %abs ret i64 %abs
} }
define i128 @test_i128(i128 %a) nounwind { define i128 @test_i128(i128 %a) nounwind {
; X86-LABEL: test_i128: ; X86-LABEL: test_i128:
; X86: # %bb.0: ; X86: # %bb.0:
; X86-NEXT: pushl %ebx ; X86-NEXT: pushl %ebx
; X86-NEXT: pushl %edi ; X86-NEXT: pushl %edi
; X86-NEXT: pushl %esi ; X86-NEXT: pushl %esi
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: movl %ecx, %edx ; X86-NEXT: movl %ecx, %edx
; X86-NEXT: sarl $31, %edx ; X86-NEXT: sarl $31, %edx
; X86-NEXT: xorl %edx, %ecx
; X86-NEXT: movl {{[0-9]+}}(%esp), %esi ; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-NEXT: addl %edx, %esi ; X86-NEXT: xorl %edx, %esi
; X86-NEXT: movl {{[0-9]+}}(%esp), %edi ; X86-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-NEXT: adcl %edx, %edi ; X86-NEXT: xorl %edx, %edi
; X86-NEXT: movl {{[0-9]+}}(%esp), %ebx ; X86-NEXT: movl {{[0-9]+}}(%esp), %ebx
; X86-NEXT: adcl %edx, %ebx
; X86-NEXT: adcl %edx, %ecx
; X86-NEXT: xorl %edx, %ecx
; X86-NEXT: xorl %edx, %ebx ; X86-NEXT: xorl %edx, %ebx
; X86-NEXT: xorl %edx, %edi ; X86-NEXT: subl %edx, %ebx
; X86-NEXT: xorl %edx, %esi ; X86-NEXT: sbbl %edx, %edi
; X86-NEXT: movl %esi, (%eax) ; X86-NEXT: sbbl %edx, %esi
; X86-NEXT: sbbl %edx, %ecx
; X86-NEXT: movl %ebx, (%eax)
; X86-NEXT: movl %edi, 4(%eax) ; X86-NEXT: movl %edi, 4(%eax)
; X86-NEXT: movl %ebx, 8(%eax) ; X86-NEXT: movl %esi, 8(%eax)
; X86-NEXT: movl %ecx, 12(%eax) ; X86-NEXT: movl %ecx, 12(%eax)
; X86-NEXT: popl %esi ; X86-NEXT: popl %esi
; X86-NEXT: popl %edi ; X86-NEXT: popl %edi
; X86-NEXT: popl %ebx ; X86-NEXT: popl %ebx
; X86-NEXT: retl $4 ; X86-NEXT: retl $4
; ;
; X64-LABEL: test_i128: ; X64-LABEL: test_i128:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: movq %rdi, %rax
; X64-NEXT: movq %rsi, %rdx ; X64-NEXT: movq %rsi, %rdx
; X64-NEXT: sarq $63, %rdx ; X64-NEXT: movq %rdi, %rax
; X64-NEXT: addq %rdx, %rax ; X64-NEXT: movq %rsi, %rcx
; X64-NEXT: adcq %rdx, %rsi ; X64-NEXT: sarq $63, %rcx
; X64-NEXT: xorq %rdx, %rax ; X64-NEXT: xorq %rcx, %rdx
; X64-NEXT: xorq %rsi, %rdx ; X64-NEXT: xorq %rcx, %rax
; X64-NEXT: subq %rcx, %rax
; X64-NEXT: sbbq %rcx, %rdx
; X64-NEXT: retq ; X64-NEXT: retq
%tmp1neg = sub i128 0, %a %tmp1neg = sub i128 0, %a
%b = icmp sgt i128 %a, -1 %b = icmp sgt i128 %a, -1
%abs = select i1 %b, i128 %a, i128 %tmp1neg %abs = select i1 %b, i128 %a, i128 %tmp1neg
ret i128 %abs ret i128 %abs
} }

llvm/test/CodeGen/X86/neg-abs.ll

Show First 20 Lines • Show All 227 Lines • ▼ Show 20 Lines
; X86: # %bb.0: ; X86: # %bb.0:
; X86-NEXT: pushl %edi ; X86-NEXT: pushl %edi
; X86-NEXT: pushl %esi ; X86-NEXT: pushl %esi
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: movl {{[0-9]+}}(%esp), %edx ; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: movl %ecx, %esi ; X86-NEXT: movl %ecx, %esi
; X86-NEXT: sarl $31, %esi ; X86-NEXT: sarl $31, %esi
; X86-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-NEXT: addl %esi, %edi
; X86-NEXT: adcl %esi, %ecx
; X86-NEXT: xorl %esi, %ecx ; X86-NEXT: xorl %esi, %ecx
; X86-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-NEXT: xorl %esi, %edi ; X86-NEXT: xorl %esi, %edi
; X86-NEXT: subl %esi, %edi
; X86-NEXT: sbbl %esi, %ecx
; X86-NEXT: subl %edi, %eax ; X86-NEXT: subl %edi, %eax
; X86-NEXT: sbbl %ecx, %edx ; X86-NEXT: sbbl %ecx, %edx
; X86-NEXT: popl %esi ; X86-NEXT: popl %esi
; X86-NEXT: popl %edi ; X86-NEXT: popl %edi
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-LABEL: sub_abs_i64: ; X64-LABEL: sub_abs_i64:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: movq %rdi, %rax ; X64-NEXT: movq %rdi, %rax
; X64-NEXT: negq %rax ; X64-NEXT: negq %rax
; X64-NEXT: cmovnsq %rdi, %rax ; X64-NEXT: cmovnsq %rdi, %rax
; X64-NEXT: addq %rsi, %rax ; X64-NEXT: addq %rsi, %rax
; X64-NEXT: retq ; X64-NEXT: retq
%abs = tail call i64 @llvm.abs.i64(i64 %x, i1 false) %abs = tail call i64 @llvm.abs.i64(i64 %x, i1 false)
%neg = sub i64 %y, %abs %neg = sub i64 %y, %abs
ret i64 %neg ret i64 %neg
} }
define i128 @sub_abs_i128(i128 %x, i128 %y) nounwind { define i128 @sub_abs_i128(i128 %x, i128 %y) nounwind {
; X86-LABEL: sub_abs_i128: ; X86-LABEL: sub_abs_i128:
; X86: # %bb.0: ; X86: # %bb.0:
; X86-NEXT: pushl %edi ; X86-NEXT: pushl %edi
; X86-NEXT: pushl %esi ; X86-NEXT: pushl %esi
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: movl %eax, %ecx ; X86-NEXT: movl %eax, %edx
; X86-NEXT: sarl $31, %ecx ; X86-NEXT: sarl $31, %edx
; X86-NEXT: movl {{[0-9]+}}(%esp), %edx ; X86-NEXT: xorl %edx, %eax
; X86-NEXT: addl %ecx, %edx ; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: xorl %edx, %ecx
; X86-NEXT: movl {{[0-9]+}}(%esp), %esi ; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-NEXT: adcl %ecx, %esi ; X86-NEXT: xorl %edx, %esi
; X86-NEXT: movl {{[0-9]+}}(%esp), %edi ; X86-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-NEXT: adcl %ecx, %edi ; X86-NEXT: xorl %edx, %edi
; X86-NEXT: adcl %ecx, %eax ; X86-NEXT: subl %edx, %edi
; X86-NEXT: xorl %ecx, %eax ; X86-NEXT: sbbl %edx, %esi
; X86-NEXT: xorl %ecx, %edi ; X86-NEXT: sbbl %edx, %ecx
; X86-NEXT: xorl %ecx, %esi ; X86-NEXT: sbbl %edx, %eax
; X86-NEXT: xorl %ecx, %edx
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: subl %edx, %ecx
; X86-NEXT: movl {{[0-9]+}}(%esp), %edx ; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-NEXT: sbbl %esi, %edx ; X86-NEXT: subl %edi, %edx
; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-NEXT: sbbl %edi, %esi
; X86-NEXT: movl {{[0-9]+}}(%esp), %edi ; X86-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-NEXT: sbbl %eax, %edi ; X86-NEXT: sbbl %esi, %edi
; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-NEXT: sbbl %ecx, %esi
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: sbbl %eax, %ecx
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: movl %ecx, (%eax) ; X86-NEXT: movl %edx, (%eax)
; X86-NEXT: movl %edx, 4(%eax) ; X86-NEXT: movl %edi, 4(%eax)
; X86-NEXT: movl %esi, 8(%eax) ; X86-NEXT: movl %esi, 8(%eax)
; X86-NEXT: movl %edi, 12(%eax) ; X86-NEXT: movl %ecx, 12(%eax)
; X86-NEXT: popl %esi ; X86-NEXT: popl %esi
; X86-NEXT: popl %edi ; X86-NEXT: popl %edi
; X86-NEXT: retl $4 ; X86-NEXT: retl $4
; ;
; X64-LABEL: sub_abs_i128: ; X64-LABEL: sub_abs_i128:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: movq %rdx, %rax ; X64-NEXT: movq %rdx, %rax
; X64-NEXT: movq %rsi, %rdx ; X64-NEXT: movq %rsi, %rdx
; X64-NEXT: sarq $63, %rdx ; X64-NEXT: sarq $63, %rdx
; X64-NEXT: addq %rdx, %rdi
; X64-NEXT: adcq %rdx, %rsi
; X64-NEXT: xorq %rdx, %rsi ; X64-NEXT: xorq %rdx, %rsi
; X64-NEXT: xorq %rdx, %rdi ; X64-NEXT: xorq %rdx, %rdi
; X64-NEXT: subq %rdx, %rdi
; X64-NEXT: sbbq %rdx, %rsi
; X64-NEXT: subq %rdi, %rax ; X64-NEXT: subq %rdi, %rax
; X64-NEXT: sbbq %rsi, %rcx ; X64-NEXT: sbbq %rsi, %rcx
; X64-NEXT: movq %rcx, %rdx ; X64-NEXT: movq %rcx, %rdx
; X64-NEXT: retq ; X64-NEXT: retq
%abs = tail call i128 @llvm.abs.i128(i128 %x, i1 false) %abs = tail call i128 @llvm.abs.i128(i128 %x, i1 false)
%neg = sub i128 %y, %abs %neg = sub i128 %y, %abs
ret i128 %neg ret i128 %neg
} }

llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/basic.ll.expected

Show First 20 Lines • Show All 89 Lines • ▼ Show 20 Lines
} }
define i64 @test_i64(i64 %a) nounwind { define i64 @test_i64(i64 %a) nounwind {
; X86-LABEL: test_i64: ; X86-LABEL: test_i64:
; X86: # %bb.0: ; X86: # %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %edx ; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-NEXT: movl %edx, %ecx ; X86-NEXT: movl %edx, %ecx
; X86-NEXT: sarl $31, %ecx ; X86-NEXT: sarl $31, %ecx
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: addl %ecx, %eax
; X86-NEXT: adcl %ecx, %edx
; X86-NEXT: xorl %ecx, %edx ; X86-NEXT: xorl %ecx, %edx
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: xorl %ecx, %eax ; X86-NEXT: xorl %ecx, %eax
; X86-NEXT: subl %ecx, %eax
; X86-NEXT: sbbl %ecx, %edx
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-LABEL: test_i64: ; X64-LABEL: test_i64:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: movq %rdi, %rax ; X64-NEXT: movq %rdi, %rax
; X64-NEXT: negq %rax ; X64-NEXT: negq %rax
; X64-NEXT: cmovsq %rdi, %rax ; X64-NEXT: cmovsq %rdi, %rax
; X64-NEXT: retq ; X64-NEXT: retq
%tmp1neg = sub i64 0, %a %tmp1neg = sub i64 0, %a
%b = icmp sgt i64 %a, -1 %b = icmp sgt i64 %a, -1
%abs = select i1 %b, i64 %a, i64 %tmp1neg %abs = select i1 %b, i64 %a, i64 %tmp1neg
ret i64 %abs ret i64 %abs
} }