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Differential D120855

[AMDGPU] gfx940 uses new names for coherency bits
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Authored by rampitec on Mar 2 2022, 4:13 PM.

Details

Reviewers
kzhuravl
msearles
Commits
rG8992b50e2f25: [AMDGPU] gfx940 uses new names for coherency bits

Diff Detail

Unit TestsFailed

TimeTest
60,040 msx64 debian > Clang.CodeGen/RISCV/rvv-intrinsics::vloxseg.c
60,120 msx64 debian > Clang.CodeGen/RISCV/rvv-intrinsics::vluxseg.c
60,040 msx64 debian > Clang.CodeGen/RISCV/rvv-intrinsics-overloaded::vloxseg.c
60,070 msx64 debian > Clang.CodeGen/RISCV/rvv-intrinsics-overloaded::vluxseg.c
60,260 msx64 debian > Clang.Driver::arm-cortex-cpus.c
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Event Timeline

rampitec created this revision.Mar 2 2022, 4:13 PM
Herald added a project: Restricted Project. · View Herald TranscriptMar 2 2022, 4:13 PM
Herald added subscribers: foad, kerbowa, hiraditya and 7 others. · View Herald Transcript
rampitec requested review of this revision.Mar 2 2022, 4:13 PM
Herald added a project: Restricted Project. · View Herald TranscriptMar 2 2022, 4:13 PM
Herald added a subscriber: wdng. · View Herald Transcript
rampitec added a parent revision: D120769: [AMDGPU] gfx940: support V_FMAMK_F32 and V_FMAAK_F32.Mar 2 2022, 4:13 PM
Harbormaster completed remote builds in B152266: Diff 412572.Mar 2 2022, 4:49 PM
critson added a subscriber: critson.Mar 2 2022, 8:04 PM
critson added inline comments.
llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
4263

This code looks odd because from the naming alone I would expect isGFX90A and isGFX940 to be mutually exclusive.
Should those test really be named hasGFX90A_Insts, or be actually made exclusive?

rampitec added inline comments.Mar 2 2022, 9:47 PM
llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
4263

This is true, but this is all across the MC layer and many places above it, not just for this target. It can use a separate and massive cleanup, not simply changing this line.

rampitec updated this revision to Diff 412780.Mar 3 2022, 11:06 AM

Rebased.

Harbormaster completed remote builds in B152423: Diff 412780.Mar 3 2022, 11:53 AM
rampitec added a child revision: D121023: [AMDGPU] Add v_mov_b64 gfx940 opcode.Mar 4 2022, 1:45 PM
kzhuravl accepted this revision.Mar 7 2022, 10:23 AM

Other than a TODO comment, LGTM, thanks

llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
4263

Can we add a TODO mentioning that this needs a cleanup?

This revision is now accepted and ready to land.Mar 7 2022, 10:23 AM
rampitec updated this revision to Diff 413549.Mar 7 2022, 10:29 AM
rampitec marked an inline comment as done.

Added TODO at isGFX90A() declaration.

Harbormaster completed remote builds in B152977: Diff 413549.Mar 7 2022, 11:04 AM
This revision was landed with ongoing or failed builds.Mar 7 2022, 11:50 AM
Closed by commit rG8992b50e2f25: [AMDGPU] gfx940 uses new names for coherency bits (authored by rampitec). · Explain Why
This revision was automatically updated to reflect the committed changes.
rampitec added a commit: rG8992b50e2f25: [AMDGPU] gfx940 uses new names for coherency bits.

Revision Contents

PathSize
llvm/
lib/
Target/
AMDGPU/
AsmParser/
31 lines
MCTargetDesc/
8 lines
3 lines
Utils/
1 line
4 lines
test/
MC/
AMDGPU/
42 lines
19 lines
Disassembler/
AMDGPU/
21 lines

Diff 412572

llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 1,384 Lines • ▼ Show 20 Linespublic:
bool isGFX9() const { bool isGFX9() const {
return AMDGPU::isGFX9(getSTI()); return AMDGPU::isGFX9(getSTI());
} }
bool isGFX90A() const { bool isGFX90A() const {
return AMDGPU::isGFX90A(getSTI()); return AMDGPU::isGFX90A(getSTI());
} }
bool isGFX940() const {
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-  bool isGFX940() const {
-    return AMDGPU::isGFX940(getSTI());
-  }
+  bool isGFX940() const { return AMDGPU::isGFX940(getSTI()); }
Lint: Pre-merge checks: clang-format: please reformat the code ``` - bool isGFX940() const { - return AMDGPU…
return AMDGPU::isGFX940(getSTI());
}
bool isGFX9Plus() const { bool isGFX9Plus() const {
return AMDGPU::isGFX9Plus(getSTI()); return AMDGPU::isGFX9Plus(getSTI());
} }
bool isGFX10() const { bool isGFX10() const {
return AMDGPU::isGFX10(getSTI()); return AMDGPU::isGFX10(getSTI());
} }
▲ Show 20 Lines • Show All 2,850 Lines • ▼ Show 20 Linesbool AMDGPUAsmParser::validateCoherencyBits(const MCInst &Inst,
uint64_t TSFlags = MII.get(Inst.getOpcode()).TSFlags; uint64_t TSFlags = MII.get(Inst.getOpcode()).TSFlags;
if ((TSFlags & (SIInstrFlags::SMRD)) && if ((TSFlags & (SIInstrFlags::SMRD)) &&
(CPol & ~(AMDGPU::CPol::GLC | AMDGPU::CPol::DLC))) { (CPol & ~(AMDGPU::CPol::GLC | AMDGPU::CPol::DLC))) {
Error(IDLoc, "invalid cache policy for SMRD instruction"); Error(IDLoc, "invalid cache policy for SMRD instruction");
return false; return false;
} }
if (isGFX90A() && (CPol & CPol::SCC)) { if (isGFX90A() && !isGFX940() && (CPol & CPol::SCC)) {
critsonUnsubmitted
Not Done
ReplyInline Actions

This code looks odd because from the naming alone I would expect isGFX90A and isGFX940 to be mutually exclusive.
Should those test really be named hasGFX90A_Insts, or be actually made exclusive?

critson: This code looks odd because from the naming alone I would expect isGFX90A and isGFX940 to be…
rampitecAuthorUnsubmitted
Done
ReplyInline Actions

This is true, but this is all across the MC layer and many places above it, not just for this target. It can use a separate and massive cleanup, not simply changing this line.

rampitec: This is true, but this is all across the MC layer and many places above it, not just for this…
kzhuravlUnsubmitted
Done
ReplyInline Actions

Can we add a TODO mentioning that this needs a cleanup?

kzhuravl: Can we add a TODO mentioning that this needs a cleanup?
SMLoc S = getImmLoc(AMDGPUOperand::ImmTyCPol, Operands); SMLoc S = getImmLoc(AMDGPUOperand::ImmTyCPol, Operands);
StringRef CStr(S.getPointer()); StringRef CStr(S.getPointer());
S = SMLoc::getFromPointer(&CStr.data()[CStr.find("scc")]); S = SMLoc::getFromPointer(&CStr.data()[CStr.find("scc")]);
Error(S, "scc is not supported on this GPU"); Error(S, "scc is not supported on this GPU");
return false; return false;
} }
if (!(TSFlags & (SIInstrFlags::IsAtomicNoRet | SIInstrFlags::IsAtomicRet))) if (!(TSFlags & (SIInstrFlags::IsAtomicNoRet | SIInstrFlags::IsAtomicRet)))
return true; return true;
if (TSFlags & SIInstrFlags::IsAtomicRet) { if (TSFlags & SIInstrFlags::IsAtomicRet) {
if (!(TSFlags & SIInstrFlags::MIMG) && !(CPol & CPol::GLC)) { if (!(TSFlags & SIInstrFlags::MIMG) && !(CPol & CPol::GLC)) {
Error(IDLoc, "instruction must use glc"); Error(IDLoc, isGFX940() ? "instruction must use sc0"
: "instruction must use glc");
return false; return false;
} }
} else { } else {
if (CPol & CPol::GLC) { if (CPol & CPol::GLC) {
SMLoc S = getImmLoc(AMDGPUOperand::ImmTyCPol, Operands); SMLoc S = getImmLoc(AMDGPUOperand::ImmTyCPol, Operands);
StringRef CStr(S.getPointer()); StringRef CStr(S.getPointer());
S = SMLoc::getFromPointer(&CStr.data()[CStr.find("glc")]); S = SMLoc::getFromPointer(&CStr.data()[CStr.find("glc")]);
Error(S, "instruction must not use glc"); Error(S, isGFX940() ? "instruction must not use sc0"
: "instruction must not use glc");
return false; return false;
} }
} }
return true; return true;
} }
bool AMDGPUAsmParser::validateInstruction(const MCInst &Inst, bool AMDGPUAsmParser::validateInstruction(const MCInst &Inst,
▲ Show 20 Lines • Show All 1,332 Lines • ▼ Show 20 Lines
} }
OperandMatchResultTy OperandMatchResultTy
AMDGPUAsmParser::parseCPol(OperandVector &Operands) { AMDGPUAsmParser::parseCPol(OperandVector &Operands) {
unsigned CPolOn = 0; unsigned CPolOn = 0;
unsigned CPolOff = 0; unsigned CPolOff = 0;
SMLoc S = getLoc(); SMLoc S = getLoc();
if (trySkipId("glc")) StringRef Mnemo = ((AMDGPUOperand &)*Operands[0]).getToken();
if (isGFX940() && !Mnemo.startswith("s_")) {
if (trySkipId("sc0"))
CPolOn = AMDGPU::CPol::SC0;
else if (trySkipId("nosc0"))
CPolOff = AMDGPU::CPol::SC0;
else if (trySkipId("nt"))
CPolOn = AMDGPU::CPol::NT;
else if (trySkipId("nont"))
CPolOff = AMDGPU::CPol::NT;
else if (trySkipId("sc1"))
CPolOn = AMDGPU::CPol::SC1;
else if (trySkipId("nosc1"))
CPolOff = AMDGPU::CPol::SC1;
else
return MatchOperand_NoMatch;
}
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-  }
-  else if (trySkipId("glc"))
+  } else if (trySkipId("glc"))
Lint: Pre-merge checks: clang-format: please reformat the code ``` - } - else if (trySkipId("glc")) + } else if…
else if (trySkipId("glc"))
CPolOn = AMDGPU::CPol::GLC; CPolOn = AMDGPU::CPol::GLC;
else if (trySkipId("noglc")) else if (trySkipId("noglc"))
CPolOff = AMDGPU::CPol::GLC; CPolOff = AMDGPU::CPol::GLC;
else if (trySkipId("slc")) else if (trySkipId("slc"))
CPolOn = AMDGPU::CPol::SLC; CPolOn = AMDGPU::CPol::SLC;
else if (trySkipId("noslc")) else if (trySkipId("noslc"))
CPolOff = AMDGPU::CPol::SLC; CPolOff = AMDGPU::CPol::SLC;
else if (trySkipId("dlc")) else if (trySkipId("dlc"))
▲ Show 20 Lines • Show All 2,819 Lines • Show Last 20 Lines

llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp

Show First 20 Lines • Show All 200 Lines • ▼ Show 20 Linesvoid AMDGPUInstPrinter::printGDS(const MCInst *MI, unsigned OpNo,
const MCSubtargetInfo &STI, raw_ostream &O) { const MCSubtargetInfo &STI, raw_ostream &O) {
printNamedBit(MI, OpNo, O, "gds"); printNamedBit(MI, OpNo, O, "gds");
} }
void AMDGPUInstPrinter::printCPol(const MCInst *MI, unsigned OpNo, void AMDGPUInstPrinter::printCPol(const MCInst *MI, unsigned OpNo,
const MCSubtargetInfo &STI, raw_ostream &O) { const MCSubtargetInfo &STI, raw_ostream &O) {
auto Imm = MI->getOperand(OpNo).getImm(); auto Imm = MI->getOperand(OpNo).getImm();
if (Imm & CPol::GLC) if (Imm & CPol::GLC)
O << " glc"; O << ((AMDGPU::isGFX940(STI) &&
!(MII.get(MI->getOpcode()).TSFlags & SIInstrFlags::SMRD)) ? " sc0"
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-           !(MII.get(MI->getOpcode()).TSFlags & SIInstrFlags::SMRD)) ? " sc0"
-                                                                     : " glc");
+           !(MII.get(MI->getOpcode()).TSFlags & SIInstrFlags::SMRD))
+              ? " sc0"
+              : " glc");
Lint: Pre-merge checks: clang-format: please reformat the code ``` - !(MII.get(MI->getOpcode()).TSFlags &…
: " glc");
if (Imm & CPol::SLC) if (Imm & CPol::SLC)
O << " slc"; O << (AMDGPU::isGFX940(STI) ? " nt" : " slc");
if ((Imm & CPol::DLC) && AMDGPU::isGFX10Plus(STI)) if ((Imm & CPol::DLC) && AMDGPU::isGFX10Plus(STI))
O << " dlc"; O << " dlc";
if ((Imm & CPol::SCC) && AMDGPU::isGFX90A(STI)) if ((Imm & CPol::SCC) && AMDGPU::isGFX90A(STI))
O << " scc"; O << (AMDGPU::isGFX940(STI) ? " sc1" : " scc");
if (Imm & ~CPol::ALL) if (Imm & ~CPol::ALL)
O << " /* unexpected cache policy bit */"; O << " /* unexpected cache policy bit */";
} }
void AMDGPUInstPrinter::printSWZ(const MCInst *MI, unsigned OpNo, void AMDGPUInstPrinter::printSWZ(const MCInst *MI, unsigned OpNo,
const MCSubtargetInfo &STI, raw_ostream &O) { const MCSubtargetInfo &STI, raw_ostream &O) {
} }
▲ Show 20 Lines • Show All 1,237 Lines • Show Last 20 Lines

llvm/lib/Target/AMDGPU/SIDefines.h

Show First 20 Lines • Show All 288 Lines • ▼ Show 20 Lines
namespace AMDGPU { namespace AMDGPU {
namespace CPol { namespace CPol {
enum CPol { enum CPol {
GLC = 1, GLC = 1,
SLC = 2, SLC = 2,
DLC = 4, DLC = 4,
SCC = 16, SCC = 16,
SC0 = GLC,
SC1 = SCC,
NT = SLC,
ALL = GLC | SLC | DLC | SCC ALL = GLC | SLC | DLC | SCC
}; };
} // namespace CPol } // namespace CPol
namespace SendMsg { // Encoding of SIMM16 used in s_sendmsg* insns. namespace SendMsg { // Encoding of SIMM16 used in s_sendmsg* insns.
enum Id { // Message ID, width(4) [3:0]. enum Id { // Message ID, width(4) [3:0].
▲ Show 20 Lines • Show All 628 Lines • Show Last 20 Lines

llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h

Show First 20 Lines • Show All 774 Lines • ▼ Show 20 Lines
bool isGFX9Plus(const MCSubtargetInfo &STI); bool isGFX9Plus(const MCSubtargetInfo &STI);
bool isGFX10(const MCSubtargetInfo &STI); bool isGFX10(const MCSubtargetInfo &STI);
bool isGFX10Plus(const MCSubtargetInfo &STI); bool isGFX10Plus(const MCSubtargetInfo &STI);
bool isGCN3Encoding(const MCSubtargetInfo &STI); bool isGCN3Encoding(const MCSubtargetInfo &STI);
bool isGFX10_AEncoding(const MCSubtargetInfo &STI); bool isGFX10_AEncoding(const MCSubtargetInfo &STI);
bool isGFX10_BEncoding(const MCSubtargetInfo &STI); bool isGFX10_BEncoding(const MCSubtargetInfo &STI);
bool hasGFX10_3Insts(const MCSubtargetInfo &STI); bool hasGFX10_3Insts(const MCSubtargetInfo &STI);
bool isGFX90A(const MCSubtargetInfo &STI); bool isGFX90A(const MCSubtargetInfo &STI);
bool isGFX940(const MCSubtargetInfo &STI);
bool hasArchitectedFlatScratch(const MCSubtargetInfo &STI); bool hasArchitectedFlatScratch(const MCSubtargetInfo &STI);
bool hasMAIInsts(const MCSubtargetInfo &STI); bool hasMAIInsts(const MCSubtargetInfo &STI);
int getTotalNumVGPRs(bool has90AInsts, int32_t ArgNumAGPR, int32_t ArgNumVGPR); int getTotalNumVGPRs(bool has90AInsts, int32_t ArgNumAGPR, int32_t ArgNumVGPR);
/// Is Reg - scalar register /// Is Reg - scalar register
bool isSGPR(unsigned Reg, const MCRegisterInfo* TRI); bool isSGPR(unsigned Reg, const MCRegisterInfo* TRI);
/// If \p Reg is a pseudo reg, return the correct hardware register given /// If \p Reg is a pseudo reg, return the correct hardware register given
▲ Show 20 Lines • Show All 261 Lines • Show Last 20 Lines

llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp

Show First 20 Lines • Show All 1,524 Lines • ▼ Show 20 Lines
bool hasGFX10_3Insts(const MCSubtargetInfo &STI) { bool hasGFX10_3Insts(const MCSubtargetInfo &STI) {
return STI.getFeatureBits()[AMDGPU::FeatureGFX10_3Insts]; return STI.getFeatureBits()[AMDGPU::FeatureGFX10_3Insts];
} }
bool isGFX90A(const MCSubtargetInfo &STI) { bool isGFX90A(const MCSubtargetInfo &STI) {
return STI.getFeatureBits()[AMDGPU::FeatureGFX90AInsts]; return STI.getFeatureBits()[AMDGPU::FeatureGFX90AInsts];
} }
bool isGFX940(const MCSubtargetInfo &STI) {
return STI.getFeatureBits()[AMDGPU::FeatureGFX940Insts];
}
bool hasArchitectedFlatScratch(const MCSubtargetInfo &STI) { bool hasArchitectedFlatScratch(const MCSubtargetInfo &STI) {
return STI.getFeatureBits()[AMDGPU::FeatureArchitectedFlatScratch]; return STI.getFeatureBits()[AMDGPU::FeatureArchitectedFlatScratch];
} }
bool hasMAIInsts(const MCSubtargetInfo &STI) { bool hasMAIInsts(const MCSubtargetInfo &STI) {
return STI.getFeatureBits()[AMDGPU::FeatureMAIInsts]; return STI.getFeatureBits()[AMDGPU::FeatureMAIInsts];
} }
▲ Show 20 Lines • Show All 575 Lines • Show Last 20 Lines

llvm/test/MC/AMDGPU/gfx940_asm_features.s

// RUN: llvm-mc -arch=amdgcn -mcpu=gfx940 -show-encoding %s | FileCheck --check-prefix=GFX940 --strict-whitespace %s // RUN: llvm-mc -arch=amdgcn -mcpu=gfx940 -show-encoding %s | FileCheck --check-prefix=GFX940 --strict-whitespace %s
// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx90a %s 2>&1 | FileCheck --check-prefixes=GFX90A --implicit-check-not=error: %s // RUN: not llvm-mc -arch=amdgcn -mcpu=gfx90a %s 2>&1 | FileCheck --check-prefixes=NOT-GFX940,GFX90A --implicit-check-not=error: %s
// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 %s 2>&1 | FileCheck --check-prefixes=NOT-GFX940 --implicit-check-not=error: %s
// NOT-GFX940: error: invalid operand for instruction
// GFX940: global_load_dword v2, v[2:3], off sc0 ; encoding: [0x00,0x80,0x51,0xdc,0x02,0x00,0x7f,0x02]
global_load_dword v2, v[2:3], off sc0
// NOT-GFX940: error: invalid operand for instruction
// GFX940: global_load_dword v2, v[2:3], off ; encoding: [0x00,0x80,0x50,0xdc,0x02,0x00,0x7f,0x02]
global_load_dword v2, v[2:3], off nosc0
// NOT-GFX940: error: invalid operand for instruction
// GFX940: global_load_dword v2, v[2:3], off sc1 ; encoding: [0x00,0x80,0x50,0xde,0x02,0x00,0x7f,0x02]
global_load_dword v2, v[2:3], off sc1
// NOT-GFX940: error: invalid operand for instruction
// GFX940: global_load_dword v2, v[2:3], off ; encoding: [0x00,0x80,0x50,0xdc,0x02,0x00,0x7f,0x02]
global_load_dword v2, v[2:3], off nosc1
// NOT-GFX940: error: invalid operand for instruction
// GFX940: global_load_dword v2, v[2:3], off nt ; encoding: [0x00,0x80,0x52,0xdc,0x02,0x00,0x7f,0x02]
global_load_dword v2, v[2:3], off nt
// NOT-GFX940: error: invalid operand for instruction
// GFX940: global_load_dword v2, v[2:3], off ; encoding: [0x00,0x80,0x50,0xdc,0x02,0x00,0x7f,0x02]
global_load_dword v2, v[2:3], off nont
// GFX940: s_load_dword s2, s[2:3], 0x0 glc ; encoding: [0x81,0x00,0x03,0xc0,0x00,0x00,0x00,0x00]
s_load_dword s2, s[2:3], 0x0 glc
// NOT-GFX940: error: invalid operand for instruction
// GFX940: buffer_load_dword v5, off, s[8:11], s3 sc0 nt sc1 ; encoding: [0x00,0xc0,0x52,0xe0,0x00,0x05,0x02,0x03]
buffer_load_dword v5, off, s[8:11], s3 sc0 nt sc1
// NOT-GFX940: error: invalid operand for instruction
// GFX940: buffer_atomic_swap v5, off, s[8:11], s3 sc0 ; encoding: [0x00,0x40,0x00,0xe1,0x00,0x05,0x02,0x03]
buffer_atomic_swap v5, off, s[8:11], s3 sc0
// NOT-GFX940: error: invalid operand for instruction
// GFX940: buffer_atomic_swap v5, off, s[8:11], s3 nt ; encoding: [0x00,0x00,0x02,0xe1,0x00,0x05,0x02,0x03]
buffer_atomic_swap v5, off, s[8:11], s3 nt
// GFX90A: error: instruction not supported on this GPU // GFX90A: error: instruction not supported on this GPU
// GFX940: v_fmamk_f32 v0, v2, 0x42c80000, v3 ; encoding: [0x02,0x07,0x00,0x2e,0x00,0x00,0xc8,0x42] // GFX940: v_fmamk_f32 v0, v2, 0x42c80000, v3 ; encoding: [0x02,0x07,0x00,0x2e,0x00,0x00,0xc8,0x42]
v_fmamk_f32 v0, v2, 100.0, v3 v_fmamk_f32 v0, v2, 100.0, v3
// GFX90A: error: instruction not supported on this GPU // GFX90A: error: instruction not supported on this GPU
// GFX940: v_fmaak_f32 v0, v2, v3, 0x42c80000 ; encoding: [0x02,0x07,0x00,0x30,0x00,0x00,0xc8,0x42] // GFX940: v_fmaak_f32 v0, v2, v3, 0x42c80000 ; encoding: [0x02,0x07,0x00,0x30,0x00,0x00,0xc8,0x42]
v_fmaak_f32 v0, v2, v3, 100.0 v_fmaak_f32 v0, v2, v3, 100.0

llvm/test/MC/AMDGPU/gfx940_err.s

  • This file was added.
// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx940 %s 2>&1 | FileCheck --check-prefix=GFX940 --implicit-check-not=error: %s
global_load_dword v2, v[2:3], off glc
// GFX940: error: invalid operand for instruction
global_load_dword v2, v[2:3], off slc
// GFX940: error: invalid operand for instruction
global_load_dword v2, v[2:3], off scc
// GFX940: error: invalid operand for instruction
s_load_dword s2, s[2:3], 0x0 sc0
// GFX940: error: invalid operand for instruction
buffer_atomic_swap v5, off, s[8:11], s3 glc
// GFX940: error: invalid operand for instruction
buffer_atomic_swap v5, off, s[8:11], s3 slc
// GFX940: error: invalid operand for instruction

llvm/test/MC/Disassembler/AMDGPU/gfx940_dasm_features.txt

# RUN: llvm-mc -arch=amdgcn -mcpu=gfx940 -disassemble -show-encoding %s | FileCheck -strict-whitespace --check-prefix=GFX940 %s # RUN: llvm-mc -arch=amdgcn -mcpu=gfx940 -disassemble -show-encoding %s | FileCheck -strict-whitespace --check-prefix=GFX940 %s
# GFX940: global_load_dword v2, v[2:3], off sc0 ; encoding: [0x00,0x80,0x51,0xdc,0x02,0x00,0x7f,0x02]
0x00,0x80,0x51,0xdc,0x02,0x00,0x7f,0x02
# GFX940: global_load_dword v2, v[2:3], off sc1 ; encoding: [0x00,0x80,0x50,0xde,0x02,0x00,0x7f,0x02]
0x00,0x80,0x50,0xde,0x02,0x00,0x7f,0x02
# GFX940: global_load_dword v2, v[2:3], off nt ; encoding: [0x00,0x80,0x52,0xdc,0x02,0x00,0x7f,0x02]
0x00,0x80,0x52,0xdc,0x02,0x00,0x7f,0x02
# GFX940: s_load_dword s2, s[2:3], 0x0 glc ; encoding: [0x81,0x00,0x03,0xc0,0x00,0x00,0x00,0x00]
0x81,0x00,0x03,0xc0,0x00,0x00,0x00,0x00
# GFX940: buffer_load_dword v5, off, s[8:11], s3 sc0 nt sc1 ; encoding: [0x00,0xc0,0x52,0xe0,0x00,0x05,0x02,0x03]
0x00,0xc0,0x52,0xe0,0x00,0x05,0x02,0x03
# GFX940: buffer_atomic_swap v5, off, s[8:11], s3 sc0 ; encoding: [0x00,0x40,0x00,0xe1,0x00,0x05,0x02,0x03]
0x00,0x40,0x00,0xe1,0x00,0x05,0x02,0x03
# GFX940: buffer_atomic_swap v5, off, s[8:11], s3 nt ; encoding: [0x00,0x00,0x02,0xe1,0x00,0x05,0x02,0x03]
0x00,0x00,0x02,0xe1,0x00,0x05,0x02,0x03
# GFX940: v_fmamk_f32 v0, v2, 0x42c80000, v3 ; encoding: [0x02,0x07,0x00,0x2e,0x00,0x00,0xc8,0x42] # GFX940: v_fmamk_f32 v0, v2, 0x42c80000, v3 ; encoding: [0x02,0x07,0x00,0x2e,0x00,0x00,0xc8,0x42]
0x02,0x07,0x00,0x2e,0x00,0x00,0xc8,0x42 0x02,0x07,0x00,0x2e,0x00,0x00,0xc8,0x42
# GFX940: v_fmaak_f32 v0, v2, v3, 0x42c80000 ; encoding: [0x02,0x07,0x00,0x30,0x00,0x00,0xc8,0x42] # GFX940: v_fmaak_f32 v0, v2, v3, 0x42c80000 ; encoding: [0x02,0x07,0x00,0x30,0x00,0x00,0xc8,0x42]
0x02,0x07,0x00,0x30,0x00,0x00,0xc8,0x42 0x02,0x07,0x00,0x30,0x00,0x00,0xc8,0x42