[AMDGPU] gfx940 uses new names for coherency bits

[critson]

llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

4264

This code looks odd because from the naming alone I would expect isGFX90A and isGFX940 to be mutually exclusive.
Should those test really be named hasGFX90A_Insts, or be actually made exclusive?

[rampitec]

llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

4264

This is true, but this is all across the MC layer and many places above it, not just for this target. It can use a separate and massive cleanup, not simply changing this line.

[rampitec]

Rebased.

[kzhuravl]

Other than a TODO comment, LGTM, thanks

llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

4264

Can we add a TODO mentioning that this needs a cleanup?

[rampitec]

Added TODO at isGFX90A() declaration.

llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

public:
   bool isVI() const {
     return AMDGPU::isVI(getSTI());
   }
 
   bool isGFX9() const {
     return AMDGPU::isGFX9(getSTI());
   }
 
+  // TODO: isGFX90A is also true for GFX940. We need to clean it.
   bool isGFX90A() const {
     return AMDGPU::isGFX90A(getSTI());
   }
 
+  bool isGFX940() const {
+    return AMDGPU::isGFX940(getSTI());
+  }
+
   bool isGFX9Plus() const {
     return AMDGPU::isGFX9Plus(getSTI());
   }
 
   bool isGFX10() const {
     return AMDGPU::isGFX10(getSTI());
   }
 
bool AMDGPUAsmParser::validateCoherencyBits(const MCInst &Inst,
 
   uint64_t TSFlags = MII.get(Inst.getOpcode()).TSFlags;
   if ((TSFlags & (SIInstrFlags::SMRD)) &&
       (CPol & ~(AMDGPU::CPol::GLC | AMDGPU::CPol::DLC))) {
     Error(IDLoc, "invalid cache policy for SMRD instruction");
     return false;
   }
 
-  if (isGFX90A() && (CPol & CPol::SCC)) {
+  if (isGFX90A() && !isGFX940() && (CPol & CPol::SCC)) {
     SMLoc S = getImmLoc(AMDGPUOperand::ImmTyCPol, Operands);
     StringRef CStr(S.getPointer());
     S = SMLoc::getFromPointer(&CStr.data()[CStr.find("scc")]);
     Error(S, "scc is not supported on this GPU");
     return false;
   }
 
   if (!(TSFlags & (SIInstrFlags::IsAtomicNoRet | SIInstrFlags::IsAtomicRet)))
     return true;
 
   if (TSFlags & SIInstrFlags::IsAtomicRet) {
     if (!(TSFlags & SIInstrFlags::MIMG) && !(CPol & CPol::GLC)) {
-      Error(IDLoc, "instruction must use glc");
+      Error(IDLoc, isGFX940() ? "instruction must use sc0"
+                              : "instruction must use glc");
       return false;
     }
   } else {
     if (CPol & CPol::GLC) {
       SMLoc S = getImmLoc(AMDGPUOperand::ImmTyCPol, Operands);
       StringRef CStr(S.getPointer());
       S = SMLoc::getFromPointer(&CStr.data()[CStr.find("glc")]);
-      Error(S, "instruction must not use glc");
+      Error(S, isGFX940() ? "instruction must not use sc0"
+                          : "instruction must not use glc");
       return false;
     }
   }
 
   return true;
 }
 
 bool AMDGPUAsmParser::validateInstruction(const MCInst &Inst,

 }
 
 OperandMatchResultTy
 AMDGPUAsmParser::parseCPol(OperandVector &Operands) {
   unsigned CPolOn = 0;
   unsigned CPolOff = 0;
   SMLoc S = getLoc();
 
-  if (trySkipId("glc"))
+  StringRef Mnemo = ((AMDGPUOperand &)*Operands[0]).getToken();
+  if (isGFX940() && !Mnemo.startswith("s_")) {
+    if (trySkipId("sc0"))
+      CPolOn = AMDGPU::CPol::SC0;
+    else if (trySkipId("nosc0"))
+      CPolOff = AMDGPU::CPol::SC0;
+    else if (trySkipId("nt"))
+      CPolOn = AMDGPU::CPol::NT;
+    else if (trySkipId("nont"))
+      CPolOff = AMDGPU::CPol::NT;
+    else if (trySkipId("sc1"))
+      CPolOn = AMDGPU::CPol::SC1;
+    else if (trySkipId("nosc1"))
+      CPolOff = AMDGPU::CPol::SC1;
+    else
+      return MatchOperand_NoMatch;
+  }
+  else if (trySkipId("glc"))
     CPolOn = AMDGPU::CPol::GLC;
   else if (trySkipId("noglc"))
     CPolOff = AMDGPU::CPol::GLC;
   else if (trySkipId("slc"))
     CPolOn = AMDGPU::CPol::SLC;
   else if (trySkipId("noslc"))
     CPolOff = AMDGPU::CPol::SLC;
   else if (trySkipId("dlc"))

llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp

void AMDGPUInstPrinter::printGDS(const MCInst *MI, unsigned OpNo,
                                  const MCSubtargetInfo &STI, raw_ostream &O) {
   printNamedBit(MI, OpNo, O, "gds");
 }
 
 void AMDGPUInstPrinter::printCPol(const MCInst *MI, unsigned OpNo,
                                   const MCSubtargetInfo &STI, raw_ostream &O) {
   auto Imm = MI->getOperand(OpNo).getImm();
   if (Imm & CPol::GLC)
-    O << " glc";
+    O << ((AMDGPU::isGFX940(STI) &&
+           !(MII.get(MI->getOpcode()).TSFlags & SIInstrFlags::SMRD)) ? " sc0"
+                                                                     : " glc");
   if (Imm & CPol::SLC)
-    O << " slc";
+    O << (AMDGPU::isGFX940(STI) ? " nt" : " slc");
   if ((Imm & CPol::DLC) && AMDGPU::isGFX10Plus(STI))
     O << " dlc";
   if ((Imm & CPol::SCC) && AMDGPU::isGFX90A(STI))
-    O << " scc";
+    O << (AMDGPU::isGFX940(STI) ? " sc1" : " scc");
   if (Imm & ~CPol::ALL)
     O << " /* unexpected cache policy bit */";
 }
 
 void AMDGPUInstPrinter::printSWZ(const MCInst *MI, unsigned OpNo,
                                  const MCSubtargetInfo &STI, raw_ostream &O) {
 }
 

llvm/lib/Target/AMDGPU/SIDefines.h

 namespace AMDGPU {
 namespace CPol {
 
 enum CPol {
   GLC = 1,
   SLC = 2,
   DLC = 4,
   SCC = 16,
+  SC0 = GLC,
+  SC1 = SCC,
+  NT = SLC,
   ALL = GLC | SLC | DLC | SCC
 };
 
 } // namespace CPol
 
 namespace SendMsg { // Encoding of SIMM16 used in s_sendmsg* insns.
 
 enum Id { // Message ID, width(4) [3:0].

llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h

 bool isGFX9Plus(const MCSubtargetInfo &STI);
 bool isGFX10(const MCSubtargetInfo &STI);
 bool isGFX10Plus(const MCSubtargetInfo &STI);
 bool isGCN3Encoding(const MCSubtargetInfo &STI);
 bool isGFX10_AEncoding(const MCSubtargetInfo &STI);
 bool isGFX10_BEncoding(const MCSubtargetInfo &STI);
 bool hasGFX10_3Insts(const MCSubtargetInfo &STI);
 bool isGFX90A(const MCSubtargetInfo &STI);
+bool isGFX940(const MCSubtargetInfo &STI);
 bool hasArchitectedFlatScratch(const MCSubtargetInfo &STI);
 bool hasMAIInsts(const MCSubtargetInfo &STI);
 int getTotalNumVGPRs(bool has90AInsts, int32_t ArgNumAGPR, int32_t ArgNumVGPR);
 
 /// Is Reg - scalar register
 bool isSGPR(unsigned Reg, const MCRegisterInfo* TRI);
 
 /// If \p Reg is a pseudo reg, return the correct hardware register given

llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp

 bool hasGFX10_3Insts(const MCSubtargetInfo &STI) {
   return STI.getFeatureBits()[AMDGPU::FeatureGFX10_3Insts];
 }
 
 bool isGFX90A(const MCSubtargetInfo &STI) {
   return STI.getFeatureBits()[AMDGPU::FeatureGFX90AInsts];
 }
 
+bool isGFX940(const MCSubtargetInfo &STI) {
+  return STI.getFeatureBits()[AMDGPU::FeatureGFX940Insts];
+}
+
 bool hasArchitectedFlatScratch(const MCSubtargetInfo &STI) {
   return STI.getFeatureBits()[AMDGPU::FeatureArchitectedFlatScratch];
 }
 
 bool hasMAIInsts(const MCSubtargetInfo &STI) {
   return STI.getFeatureBits()[AMDGPU::FeatureMAIInsts];
 }
 

llvm/test/MC/AMDGPU/gfx940_asm_features.s

 // RUN: llvm-mc -arch=amdgcn -mcpu=gfx940 -show-encoding %s | FileCheck --check-prefix=GFX940 --strict-whitespace %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx90a %s 2>&1 | FileCheck --check-prefixes=GFX90A --implicit-check-not=error: %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx90a %s 2>&1 | FileCheck --check-prefixes=NOT-GFX940,GFX90A --implicit-check-not=error: %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 %s 2>&1 | FileCheck --check-prefixes=NOT-GFX940 --implicit-check-not=error: %s
+
+// NOT-GFX940: error: invalid operand for instruction
+// GFX940: global_load_dword v2, v[2:3], off sc0   ; encoding: [0x00,0x80,0x51,0xdc,0x02,0x00,0x7f,0x02]
+global_load_dword v2, v[2:3], off sc0
+
+// NOT-GFX940: error: invalid operand for instruction
+// GFX940: global_load_dword v2, v[2:3], off       ; encoding: [0x00,0x80,0x50,0xdc,0x02,0x00,0x7f,0x02]
+global_load_dword v2, v[2:3], off nosc0
+
+// NOT-GFX940: error: invalid operand for instruction
+// GFX940: global_load_dword v2, v[2:3], off sc1   ; encoding: [0x00,0x80,0x50,0xde,0x02,0x00,0x7f,0x02]
+global_load_dword v2, v[2:3], off sc1
+
+// NOT-GFX940: error: invalid operand for instruction
+// GFX940: global_load_dword v2, v[2:3], off       ; encoding: [0x00,0x80,0x50,0xdc,0x02,0x00,0x7f,0x02]
+global_load_dword v2, v[2:3], off nosc1
+
+// NOT-GFX940: error: invalid operand for instruction
+// GFX940: global_load_dword v2, v[2:3], off nt    ; encoding: [0x00,0x80,0x52,0xdc,0x02,0x00,0x7f,0x02]
+global_load_dword v2, v[2:3], off nt
+
+// NOT-GFX940: error: invalid operand for instruction
+// GFX940: global_load_dword v2, v[2:3], off       ; encoding: [0x00,0x80,0x50,0xdc,0x02,0x00,0x7f,0x02]
+global_load_dword v2, v[2:3], off nont
+
+// GFX940: s_load_dword s2, s[2:3], 0x0 glc        ; encoding: [0x81,0x00,0x03,0xc0,0x00,0x00,0x00,0x00]
+s_load_dword s2, s[2:3], 0x0 glc
+
+// NOT-GFX940: error: invalid operand for instruction
+// GFX940: buffer_load_dword v5, off, s[8:11], s3 sc0 nt sc1 ; encoding: [0x00,0xc0,0x52,0xe0,0x00,0x05,0x02,0x03]
+buffer_load_dword v5, off, s[8:11], s3 sc0 nt sc1
+
+// NOT-GFX940: error: invalid operand for instruction
+// GFX940: buffer_atomic_swap v5, off, s[8:11], s3 sc0 ; encoding: [0x00,0x40,0x00,0xe1,0x00,0x05,0x02,0x03]
+buffer_atomic_swap v5, off, s[8:11], s3 sc0
+
+// NOT-GFX940: error: invalid operand for instruction
+// GFX940: buffer_atomic_swap v5, off, s[8:11], s3 nt ; encoding: [0x00,0x00,0x02,0xe1,0x00,0x05,0x02,0x03]
+buffer_atomic_swap v5, off, s[8:11], s3 nt
 
 // GFX90A: error: instruction not supported on this GPU
 // GFX940: v_fmamk_f32 v0, v2, 0x42c80000, v3      ; encoding: [0x02,0x07,0x00,0x2e,0x00,0x00,0xc8,0x42]
 v_fmamk_f32 v0, v2, 100.0, v3
 
 // GFX90A: error: instruction not supported on this GPU
 // GFX940: v_fmaak_f32 v0, v2, v3, 0x42c80000      ; encoding: [0x02,0x07,0x00,0x30,0x00,0x00,0xc8,0x42]
 v_fmaak_f32 v0, v2, v3, 100.0

llvm/test/MC/AMDGPU/gfx940_err.s

 v_madak_f32 v0, v1, v2, 0
 // GFX940: error: instruction not supported on this GPU
 
 v_madmk_f32 v0, v1, 0, v2
 // GFX940: error: instruction not supported on this GPU
 
 v_mad_legacy_f32 v0, v1, v2, v3
 // GFX940: error: instruction not supported on this GPU
+
+global_load_dword v2, v[2:3], off glc
+// GFX940: error: invalid operand for instruction
+
+global_load_dword v2, v[2:3], off slc
+// GFX940: error: invalid operand for instruction
+
+global_load_dword v2, v[2:3], off scc
+// GFX940: error: invalid operand for instruction
+
+s_load_dword s2, s[2:3], 0x0 sc0
+// GFX940: error: invalid operand for instruction
+
+buffer_atomic_swap v5, off, s[8:11], s3 glc
+// GFX940: error: invalid operand for instruction
+
+buffer_atomic_swap v5, off, s[8:11], s3 slc
+// GFX940: error: invalid operand for instruction

llvm/test/MC/Disassembler/AMDGPU/gfx940_dasm_features.txt

 # RUN: llvm-mc -arch=amdgcn -mcpu=gfx940 -disassemble -show-encoding %s | FileCheck -strict-whitespace --check-prefix=GFX940 %s
 
+# GFX940: global_load_dword v2, v[2:3], off sc0   ; encoding: [0x00,0x80,0x51,0xdc,0x02,0x00,0x7f,0x02]
+0x00,0x80,0x51,0xdc,0x02,0x00,0x7f,0x02
+
+# GFX940: global_load_dword v2, v[2:3], off sc1   ; encoding: [0x00,0x80,0x50,0xde,0x02,0x00,0x7f,0x02]
+0x00,0x80,0x50,0xde,0x02,0x00,0x7f,0x02
+
+# GFX940: global_load_dword v2, v[2:3], off nt    ; encoding: [0x00,0x80,0x52,0xdc,0x02,0x00,0x7f,0x02]
+0x00,0x80,0x52,0xdc,0x02,0x00,0x7f,0x02
+
+# GFX940: s_load_dword s2, s[2:3], 0x0 glc        ; encoding: [0x81,0x00,0x03,0xc0,0x00,0x00,0x00,0x00]
+0x81,0x00,0x03,0xc0,0x00,0x00,0x00,0x00
+
+# GFX940: buffer_load_dword v5, off, s[8:11], s3 sc0 nt sc1 ; encoding: [0x00,0xc0,0x52,0xe0,0x00,0x05,0x02,0x03]
+0x00,0xc0,0x52,0xe0,0x00,0x05,0x02,0x03
+
+# GFX940: buffer_atomic_swap v5, off, s[8:11], s3 sc0 ; encoding: [0x00,0x40,0x00,0xe1,0x00,0x05,0x02,0x03]
+0x00,0x40,0x00,0xe1,0x00,0x05,0x02,0x03
+
+# GFX940: buffer_atomic_swap v5, off, s[8:11], s3 nt ; encoding: [0x00,0x00,0x02,0xe1,0x00,0x05,0x02,0x03]
+0x00,0x00,0x02,0xe1,0x00,0x05,0x02,0x03
+
 # GFX940: v_fmamk_f32 v0, v2, 0x42c80000, v3      ; encoding: [0x02,0x07,0x00,0x2e,0x00,0x00,0xc8,0x42]
 0x02,0x07,0x00,0x2e,0x00,0x00,0xc8,0x42
 
 # GFX940: v_fmaak_f32 v0, v2, v3, 0x42c80000      ; encoding: [0x02,0x07,0x00,0x30,0x00,0x00,0xc8,0x42]
 0x02,0x07,0x00,0x30,0x00,0x00,0xc8,0x42