[AArch64][SME] Add addsvl and addspl instructions

[HsiangKai]

Summary

This patch adds support for the following SME instructions:

• ADDSPL, ADDSVL

The reference can be found here:
https://developer.arm.com/documentation/ddi0602/2021-12

llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td

 //
 //===----------------------------------------------------------------------===//
 
 //===----------------------------------------------------------------------===//
 // Add vector elements horizontally or vertically to ZA tile.
 //===----------------------------------------------------------------------===//
 
 let Predicates = [HasSME] in {
+def ADDSPL_XXI : sve_int_arith_vl<0b1, "addspl", /*streaming_sve=*/0b1>;
+def ADDSVL_XXI : sve_int_arith_vl<0b0, "addsvl", /*streaming_sve=*/0b1>;
+
 def ADDHA_MPPZ_S : sme_add_vector_to_tile_u32<0b0, "addha">;
 def ADDVA_MPPZ_S : sme_add_vector_to_tile_u32<0b1, "addva">;
 }
 
 let Predicates = [HasSMEI64] in {
 def ADDHA_MPPZ_D : sme_add_vector_to_tile_u64<0b0, "addha">;
 def ADDVA_MPPZ_D : sme_add_vector_to_tile_u64<0b1, "addva">;
 }

llvm/lib/Target/AArch64/SVEInstrFormats.td

multiclass sve2_fp_mla_long<bits<2> opc, string asm, SDPatternOperator op> {
   def NAME : sve2_fp_mla_long<opc, asm>;
   def : SVE_3_Op_Pat<nxv4f32, op, nxv4f32, nxv8f16, nxv8f16, !cast<Instruction>(NAME)>;
 }
 
 //===----------------------------------------------------------------------===//
 // SVE Stack Allocation Group
 //===----------------------------------------------------------------------===//
 
-class sve_int_arith_vl<bit opc, string asm>
+class sve_int_arith_vl<bit opc, string asm, bit streaming_sve = 0b0>
 : I<(outs GPR64sp:$Rd), (ins GPR64sp:$Rn, simm6_32b:$imm6),
   asm, "\t$Rd, $Rn, $imm6",
   "",
   []>, Sched<[]> {
   bits<5> Rd;
   bits<5> Rn;
   bits<6> imm6;
   let Inst{31-23} = 0b000001000;
   let Inst{22}    = opc;
   let Inst{21}    = 0b1;
   let Inst{20-16} = Rn;
-  let Inst{15-11} = 0b01010;
+  let Inst{15-12} = 0b0101;
+  let Inst{11}    = streaming_sve;
   let Inst{10-5}  = imm6;
   let Inst{4-0}   = Rd;
 }
 
 class sve_int_read_vl_a<bit op, bits<5> opc2, string asm>
 : I<(outs GPR64:$Rd), (ins simm6_32b:$imm6),
   asm, "\t$Rd, $imm6",
   "",

llvm/test/MC/AArch64/SME/addspl-diagnostics.s

+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme  2>&1 < %s| FileCheck %s
+
+// Immediate out of upper bound [-32, 31].
+addspl x19, x14, #32
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-32, 31].
+// CHECK-NEXT: addspl x19, x14, #32
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// addspl requires an immediate, not a register.
+addspl x19, x14, x15
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-32, 31].
+// CHECK-NEXT: addspl x19, x14, x15
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SME/addspl.s

+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme < %s \
+// RUN:        | llvm-objdump -d --mattr=+sme - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+addspl   x21, x21, #0
+// CHECK-INST: addspl   x21, x21, #0
+// CHECK-ENCODING: [0x15,0x58,0x75,0x04]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 15 58 75 04 <unknown>
+
+addspl   x23, x8, #-1
+// CHECK-INST: addspl   x23, x8, #-1
+// CHECK-ENCODING: [0xf7,0x5f,0x68,0x04]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: f7 5f 68 04 <unknown>
+
+addspl   sp, sp, #31
+// CHECK-INST: addspl   sp, sp, #31
+// CHECK-ENCODING: [0xff,0x5b,0x7f,0x04]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: ff 5b 7f 04 <unknown>
+
+addspl   x0, x0, #-32
+// CHECK-INST: addspl   x0, x0, #-32
+// CHECK-ENCODING: [0x00,0x5c,0x60,0x04]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 00 5c 60 04 <unknown>

llvm/test/MC/AArch64/SME/addsvl-diagnostics.s

+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme  2>&1 < %s| FileCheck %s
+
+// Immediate out of upper bound [-32, 31].
+addsvl x3, x5, #32
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-32, 31].
+// CHECK-NEXT: addsvl x3, x5, #32
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// addsvl requires an immediate, not a register.
+addsvl x3, x5, x6
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-32, 31].
+// CHECK-NEXT: addsvl x3, x5, x6
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SME/addsvl.s

+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme < %s \
+// RUN:        | llvm-objdump -d --mattr=+sme - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+addsvl   x21, x21, #0
+// CHECK-INST: addsvl   x21, x21, #0
+// CHECK-ENCODING: [0x15,0x58,0x35,0x04]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 15 58 35 04 <unknown>
+
+addsvl   x23, x8, #-1
+// CHECK-INST: addsvl   x23, x8, #-1
+// CHECK-ENCODING: [0xf7,0x5f,0x28,0x04]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: f7 5f 28 04 <unknown>
+
+addsvl   sp, sp, #31
+// CHECK-INST: addsvl   sp, sp, #31
+// CHECK-ENCODING: [0xff,0x5b,0x3f,0x04]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: ff 5b 3f 04 <unknown>
+
+addsvl   x0, x0, #-32
+// CHECK-INST: addsvl   x0, x0, #-32
+// CHECK-ENCODING: [0x00,0x5c,0x20,0x04]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 00 5c 20 04 <unknown>