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Differential D120388

[RISCV] Add more test for GORCI aliaes in Zbp extension
ClosedPublic

Authored by Jimerlife on Feb 22 2022, 11:22 PM.

Details

Reviewers
craig.topper
benshi001
asb
frasercrmck
Commits
rG3497124771aa: [RISCV] Add more test for GORCI aliaes in Zbp extension
Summary

Supplement tests for some aliaes of gorci.
RV32:
add orc4.h/orc2.h in rv32zbp.ll
add orc.h/orc16/orc8/orc4/orc2/orc in rv32zbp-intrinsic.ll

RV64:
add orc4.h/orc2.h in rv64zbp.ll
add orc.h/orc32/orc16/orc8/orc4/orc2/orc/orc16.w/orc8.w/orc4.w/orc2.w/orc.w in rv64zbp-intrinsic.ll

Diff Detail

Event Timeline

Jimerlife created this revision.Feb 22 2022, 11:22 PM
Herald added subscribers: VincentWu, luke957, achieveartificialintelligence and 24 others. · View Herald TranscriptFeb 22 2022, 11:22 PM
Jimerlife requested review of this revision.Feb 22 2022, 11:22 PM
Herald added subscribers: llvm-commits, • pcwang-thead, eopXD and 2 others. · View Herald TranscriptFeb 22 2022, 11:22 PM
craig.topper accepted this revision.Feb 22 2022, 11:35 PM

LGTM

This revision is now accepted and ready to land.Feb 22 2022, 11:35 PM
This revision was landed with ongoing or failed builds.Feb 23 2022, 12:03 AM
Closed by commit rG3497124771aa: [RISCV] Add more test for GORCI aliaes in Zbp extension (authored by Jimerlife, committed by benshi001). · Explain Why
This revision was automatically updated to reflect the committed changes.
benshi001 added a commit: rG3497124771aa: [RISCV] Add more test for GORCI aliaes in Zbp extension.
Harbormaster completed remote builds in B151001: Diff 410720.Feb 23 2022, 12:12 AM

Revision Contents

PathSize
llvm/
test/
CodeGen/
RISCV/
54 lines
240 lines
108 lines
485 lines

Diff 410724

llvm/test/CodeGen/RISCV/rv32zbp-intrinsic.ll

Show First 20 Lines • Show All 101 Lines • ▼ Show 20 Lines
; RV32ZBP-LABEL: gorci32: ; RV32ZBP-LABEL: gorci32:
; RV32ZBP: # %bb.0: ; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: gorci a0, a0, 13 ; RV32ZBP-NEXT: gorci a0, a0, 13
; RV32ZBP-NEXT: ret ; RV32ZBP-NEXT: ret
%tmp = call i32 @llvm.riscv.gorc.i32(i32 %a, i32 13) %tmp = call i32 @llvm.riscv.gorc.i32(i32 %a, i32 13)
ret i32 %tmp ret i32 %tmp
} }
define i32 @orchi32(i32 %a) nounwind {
; RV32ZBP-LABEL: orchi32:
; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: orc.h a0, a0
; RV32ZBP-NEXT: ret
%tmp = call i32 @llvm.riscv.gorc.i32(i32 %a, i32 15)
ret i32 %tmp
}
define i32 @orc16i32(i32 %a) nounwind {
; RV32ZBP-LABEL: orc16i32:
; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: orc16 a0, a0
; RV32ZBP-NEXT: ret
%tmp = call i32 @llvm.riscv.gorc.i32(i32 %a, i32 16)
ret i32 %tmp
}
define i32 @orc8i32(i32 %a) nounwind {
; RV32ZBP-LABEL: orc8i32:
; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: orc8 a0, a0
; RV32ZBP-NEXT: ret
%tmp = call i32 @llvm.riscv.gorc.i32(i32 %a, i32 24)
ret i32 %tmp
}
define i32 @orc4i32(i32 %a) nounwind {
; RV32ZBP-LABEL: orc4i32:
; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: orc4 a0, a0
; RV32ZBP-NEXT: ret
%tmp = call i32 @llvm.riscv.gorc.i32(i32 %a, i32 28)
ret i32 %tmp
}
define i32 @orc2i32(i32 %a) nounwind {
; RV32ZBP-LABEL: orc2i32:
; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: orc2 a0, a0
; RV32ZBP-NEXT: ret
%tmp = call i32 @llvm.riscv.gorc.i32(i32 %a, i32 30)
ret i32 %tmp
}
define i32 @orci32(i32 %a) nounwind {
; RV32ZBP-LABEL: orci32:
; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: orc a0, a0
; RV32ZBP-NEXT: ret
%tmp = call i32 @llvm.riscv.gorc.i32(i32 %a, i32 31)
ret i32 %tmp
}
declare i32 @llvm.riscv.shfl.i32(i32 %a, i32 %b) declare i32 @llvm.riscv.shfl.i32(i32 %a, i32 %b)
define i32 @shfl32(i32 %a, i32 %b) nounwind { define i32 @shfl32(i32 %a, i32 %b) nounwind {
; RV32ZBP-LABEL: shfl32: ; RV32ZBP-LABEL: shfl32:
; RV32ZBP: # %bb.0: ; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: shfl a0, a0, a1 ; RV32ZBP-NEXT: shfl a0, a0, a1
; RV32ZBP-NEXT: ret ; RV32ZBP-NEXT: ret
%tmp = call i32 @llvm.riscv.shfl.i32(i32 %a, i32 %b) %tmp = call i32 @llvm.riscv.shfl.i32(i32 %a, i32 %b)
▲ Show 20 Lines • Show All 264 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rv32zbp.ll

Show First 20 Lines • Show All 692 Lines • ▼ Show 20 Lines; RV32ZBP-NEXT: ret
%shl = and i64 %and, -71777214294589696 %shl = and i64 %and, -71777214294589696
%and1 = lshr i64 %a, 8 %and1 = lshr i64 %a, 8
%shr = and i64 %and1, 71777214294589695 %shr = and i64 %and1, 71777214294589695
%or = or i64 %shr, %a %or = or i64 %shr, %a
%or2 = or i64 %or, %shl %or2 = or i64 %or, %shl
ret i64 %or2 ret i64 %or2
} }
define i32 @gorc12_i32(i32 %a) nounwind {
; RV32I-LABEL: gorc12_i32:
; RV32I: # %bb.0:
; RV32I-NEXT: slli a1, a0, 4
; RV32I-NEXT: lui a2, 986895
; RV32I-NEXT: addi a2, a2, 240
; RV32I-NEXT: and a1, a1, a2
; RV32I-NEXT: srli a2, a0, 4
; RV32I-NEXT: lui a3, 61681
; RV32I-NEXT: addi a3, a3, -241
; RV32I-NEXT: and a2, a2, a3
; RV32I-NEXT: or a0, a2, a0
; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: slli a1, a0, 8
; RV32I-NEXT: lui a2, 1044496
; RV32I-NEXT: addi a2, a2, -256
; RV32I-NEXT: and a1, a1, a2
; RV32I-NEXT: srli a2, a0, 8
; RV32I-NEXT: lui a3, 4080
; RV32I-NEXT: addi a3, a3, 255
; RV32I-NEXT: and a2, a2, a3
; RV32I-NEXT: or a0, a2, a0
; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: ret
;
; RV32ZBP-LABEL: gorc12_i32:
; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: orc4.h a0, a0
; RV32ZBP-NEXT: ret
%and1 = shl i32 %a, 4
%shl1 = and i32 %and1, -252645136
%and1b = lshr i32 %a, 4
%shr1 = and i32 %and1b, 252645135
%or1 = or i32 %shr1, %a
%or1b = or i32 %or1, %shl1
%and2 = shl i32 %or1b, 8
%shl2 = and i32 %and2, -16711936
%and2b = lshr i32 %or1b, 8
%shr2 = and i32 %and2b, 16711935
%or2 = or i32 %shr2, %or1b
%or2b = or i32 %or2, %shl2
ret i32 %or2b
}
define i64 @gorc12_i64(i64 %a) nounwind {
; RV32I-LABEL: gorc12_i64:
; RV32I: # %bb.0:
; RV32I-NEXT: slli a2, a1, 4
; RV32I-NEXT: slli a3, a0, 4
; RV32I-NEXT: lui a4, 986895
; RV32I-NEXT: addi a4, a4, 240
; RV32I-NEXT: and a3, a3, a4
; RV32I-NEXT: and a2, a2, a4
; RV32I-NEXT: srli a4, a0, 4
; RV32I-NEXT: srli a5, a1, 4
; RV32I-NEXT: lui a6, 61681
; RV32I-NEXT: addi a6, a6, -241
; RV32I-NEXT: and a5, a5, a6
; RV32I-NEXT: and a4, a4, a6
; RV32I-NEXT: or a0, a4, a0
; RV32I-NEXT: or a1, a5, a1
; RV32I-NEXT: or a1, a1, a2
; RV32I-NEXT: or a0, a0, a3
; RV32I-NEXT: slli a2, a0, 8
; RV32I-NEXT: slli a3, a1, 8
; RV32I-NEXT: lui a4, 1044496
; RV32I-NEXT: addi a4, a4, -256
; RV32I-NEXT: and a3, a3, a4
; RV32I-NEXT: and a2, a2, a4
; RV32I-NEXT: srli a4, a1, 8
; RV32I-NEXT: srli a5, a0, 8
; RV32I-NEXT: lui a6, 4080
; RV32I-NEXT: addi a6, a6, 255
; RV32I-NEXT: and a5, a5, a6
; RV32I-NEXT: and a4, a4, a6
; RV32I-NEXT: or a1, a4, a1
; RV32I-NEXT: or a0, a5, a0
; RV32I-NEXT: or a0, a0, a2
; RV32I-NEXT: or a1, a1, a3
; RV32I-NEXT: ret
;
; RV32ZBP-LABEL: gorc12_i64:
; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: orc4.h a0, a0
; RV32ZBP-NEXT: orc4.h a1, a1
; RV32ZBP-NEXT: ret
%and1 = shl i64 %a, 4
%shl1 = and i64 %and1, -1085102592571150096
%and1b = lshr i64 %a, 4
%shr1 = and i64 %and1b, 1085102592571150095
%or1 = or i64 %shr1, %a
%or1b = or i64 %or1, %shl1
%and2 = shl i64 %or1b, 8
%shl2 = and i64 %and2, -71777214294589696
%and2b = lshr i64 %or1b, 8
%shr2 = and i64 %and2b, 71777214294589695
%or2 = or i64 %shr2, %or1b
%or2b = or i64 %or2, %shl2
ret i64 %or2b
}
define i32 @gorc14_i32(i32 %a) nounwind {
; RV32I-LABEL: gorc14_i32:
; RV32I: # %bb.0:
; RV32I-NEXT: slli a1, a0, 2
; RV32I-NEXT: lui a2, 838861
; RV32I-NEXT: addi a2, a2, -820
; RV32I-NEXT: and a1, a1, a2
; RV32I-NEXT: srli a2, a0, 2
; RV32I-NEXT: lui a3, 209715
; RV32I-NEXT: addi a3, a3, 819
; RV32I-NEXT: and a2, a2, a3
; RV32I-NEXT: or a0, a2, a0
; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: slli a1, a0, 4
; RV32I-NEXT: lui a2, 986895
; RV32I-NEXT: addi a2, a2, 240
; RV32I-NEXT: and a1, a1, a2
; RV32I-NEXT: srli a2, a0, 4
; RV32I-NEXT: lui a3, 61681
; RV32I-NEXT: addi a3, a3, -241
; RV32I-NEXT: and a2, a2, a3
; RV32I-NEXT: or a0, a2, a0
; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: slli a1, a0, 8
; RV32I-NEXT: lui a2, 1044496
; RV32I-NEXT: addi a2, a2, -256
; RV32I-NEXT: and a1, a1, a2
; RV32I-NEXT: srli a2, a0, 8
; RV32I-NEXT: lui a3, 4080
; RV32I-NEXT: addi a3, a3, 255
; RV32I-NEXT: and a2, a2, a3
; RV32I-NEXT: or a0, a2, a0
; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: ret
;
; RV32ZBP-LABEL: gorc14_i32:
; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: orc2.h a0, a0
; RV32ZBP-NEXT: ret
%and1 = shl i32 %a, 2
%shl1 = and i32 %and1, -858993460
%and1b = lshr i32 %a, 2
%shr1 = and i32 %and1b, 858993459
%or1 = or i32 %shr1, %a
%or1b = or i32 %or1, %shl1
%and2 = shl i32 %or1b, 4
%shl2 = and i32 %and2, -252645136
%and2b = lshr i32 %or1b, 4
%shr2 = and i32 %and2b, 252645135
%or2 = or i32 %shr2, %or1b
%or2b = or i32 %or2, %shl2
%and3 = shl i32 %or2b, 8
%shl3 = and i32 %and3, -16711936
%and3b = lshr i32 %or2b, 8
%shr3 = and i32 %and3b, 16711935
%or3 = or i32 %shr3, %or2b
%or3b = or i32 %or3, %shl3
ret i32 %or3b
}
define i64 @gorc14_i64(i64 %a) nounwind {
; RV32I-LABEL: gorc14_i64:
; RV32I: # %bb.0:
; RV32I-NEXT: slli a2, a0, 2
; RV32I-NEXT: slli a3, a1, 2
; RV32I-NEXT: lui a4, 838861
; RV32I-NEXT: addi a4, a4, -820
; RV32I-NEXT: and a3, a3, a4
; RV32I-NEXT: and a2, a2, a4
; RV32I-NEXT: srli a4, a1, 2
; RV32I-NEXT: srli a5, a0, 2
; RV32I-NEXT: lui a6, 209715
; RV32I-NEXT: addi a6, a6, 819
; RV32I-NEXT: and a5, a5, a6
; RV32I-NEXT: and a4, a4, a6
; RV32I-NEXT: or a1, a4, a1
; RV32I-NEXT: or a0, a5, a0
; RV32I-NEXT: or a0, a0, a2
; RV32I-NEXT: or a1, a1, a3
; RV32I-NEXT: slli a2, a1, 4
; RV32I-NEXT: slli a3, a0, 4
; RV32I-NEXT: lui a4, 986895
; RV32I-NEXT: addi a4, a4, 240
; RV32I-NEXT: and a3, a3, a4
; RV32I-NEXT: and a2, a2, a4
; RV32I-NEXT: srli a4, a0, 4
; RV32I-NEXT: srli a5, a1, 4
; RV32I-NEXT: lui a6, 61681
; RV32I-NEXT: addi a6, a6, -241
; RV32I-NEXT: and a5, a5, a6
; RV32I-NEXT: and a4, a4, a6
; RV32I-NEXT: or a0, a4, a0
; RV32I-NEXT: or a1, a5, a1
; RV32I-NEXT: or a1, a1, a2
; RV32I-NEXT: or a0, a0, a3
; RV32I-NEXT: slli a2, a0, 8
; RV32I-NEXT: slli a3, a1, 8
; RV32I-NEXT: lui a4, 1044496
; RV32I-NEXT: addi a4, a4, -256
; RV32I-NEXT: and a3, a3, a4
; RV32I-NEXT: and a2, a2, a4
; RV32I-NEXT: srli a4, a1, 8
; RV32I-NEXT: srli a5, a0, 8
; RV32I-NEXT: lui a6, 4080
; RV32I-NEXT: addi a6, a6, 255
; RV32I-NEXT: and a5, a5, a6
; RV32I-NEXT: and a4, a4, a6
; RV32I-NEXT: or a1, a4, a1
; RV32I-NEXT: or a0, a5, a0
; RV32I-NEXT: or a0, a0, a2
; RV32I-NEXT: or a1, a1, a3
; RV32I-NEXT: ret
;
; RV32ZBP-LABEL: gorc14_i64:
; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: orc2.h a0, a0
; RV32ZBP-NEXT: orc2.h a1, a1
; RV32ZBP-NEXT: ret
%and1 = shl i64 %a, 2
%shl1 = and i64 %and1, -3689348814741910324
%and1b = lshr i64 %a, 2
%shr1 = and i64 %and1b, 3689348814741910323
%or1 = or i64 %shr1, %a
%or1b = or i64 %or1, %shl1
%and2 = shl i64 %or1b, 4
%shl2 = and i64 %and2, -1085102592571150096
%and2b = lshr i64 %or1b, 4
%shr2 = and i64 %and2b, 1085102592571150095
%or2 = or i64 %shr2, %or1b
%or2b = or i64 %or2, %shl2
%and3 = shl i64 %or2b, 8
%shl3 = and i64 %and3, -71777214294589696
%and3b = lshr i64 %or2b, 8
%shr3 = and i64 %and3b, 71777214294589695
%or3 = or i64 %shr3, %or2b
%or3b = or i64 %or3, %shl3
ret i64 %or3b
}
define i32 @gorc16_i32(i32 %a) nounwind { define i32 @gorc16_i32(i32 %a) nounwind {
; RV32I-LABEL: gorc16_i32: ; RV32I-LABEL: gorc16_i32:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: slli a1, a0, 16 ; RV32I-NEXT: slli a1, a0, 16
; RV32I-NEXT: srli a2, a0, 16 ; RV32I-NEXT: srli a2, a0, 16
; RV32I-NEXT: or a0, a2, a0 ; RV32I-NEXT: or a0, a2, a0
; RV32I-NEXT: or a0, a0, a1 ; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: ret ; RV32I-NEXT: ret
▲ Show 20 Lines • Show All 2,467 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rv64zbp-intrinsic.ll

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; RV64ZBP-LABEL: gorci64: ; RV64ZBP-LABEL: gorci64:
; RV64ZBP: # %bb.0: ; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: gorci a0, a0, 13 ; RV64ZBP-NEXT: gorci a0, a0, 13
; RV64ZBP-NEXT: ret ; RV64ZBP-NEXT: ret
%tmp = call i64 @llvm.riscv.gorc.i64(i64 %a, i64 13) %tmp = call i64 @llvm.riscv.gorc.i64(i64 %a, i64 13)
ret i64 %tmp ret i64 %tmp
} }
define i64 @orchi64(i64 %a) nounwind {
; RV64ZBP-LABEL: orchi64:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: orc.h a0, a0
; RV64ZBP-NEXT: ret
%tmp = call i64 @llvm.riscv.gorc.i64(i64 %a, i64 15)
ret i64 %tmp
}
define i64 @orc16wi64(i64 %a) nounwind {
; RV64ZBP-LABEL: orc16wi64:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: orc16.w a0, a0
; RV64ZBP-NEXT: ret
%tmp = call i64 @llvm.riscv.gorc.i64(i64 %a, i64 16)
ret i64 %tmp
}
define i64 @orc8wi64(i64 %a) nounwind {
; RV64ZBP-LABEL: orc8wi64:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: orc8.w a0, a0
; RV64ZBP-NEXT: ret
%tmp = call i64 @llvm.riscv.gorc.i64(i64 %a, i64 24)
ret i64 %tmp
}
define i64 @orc4wi64(i64 %a) nounwind {
; RV64ZBP-LABEL: orc4wi64:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: orc4.w a0, a0
; RV64ZBP-NEXT: ret
%tmp = call i64 @llvm.riscv.gorc.i64(i64 %a, i64 28)
ret i64 %tmp
}
define i64 @orc2wi64(i64 %a) nounwind {
; RV64ZBP-LABEL: orc2wi64:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: orc2.w a0, a0
; RV64ZBP-NEXT: ret
%tmp = call i64 @llvm.riscv.gorc.i64(i64 %a, i64 30)
ret i64 %tmp
}
define i64 @orcwi64(i64 %a) nounwind {
; RV64ZBP-LABEL: orcwi64:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: orc.w a0, a0
; RV64ZBP-NEXT: ret
%tmp = call i64 @llvm.riscv.gorc.i64(i64 %a, i64 31)
ret i64 %tmp
}
define i64 @orc32i64(i64 %a) nounwind {
; RV64ZBP-LABEL: orc32i64:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: orc32 a0, a0
; RV64ZBP-NEXT: ret
%tmp = call i64 @llvm.riscv.gorc.i64(i64 %a, i64 32)
ret i64 %tmp
}
define i64 @orc16i64(i64 %a) nounwind {
; RV64ZBP-LABEL: orc16i64:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: orc16 a0, a0
; RV64ZBP-NEXT: ret
%tmp = call i64 @llvm.riscv.gorc.i64(i64 %a, i64 48)
ret i64 %tmp
}
define i64 @orc8i64(i64 %a) nounwind {
; RV64ZBP-LABEL: orc8i64:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: orc8 a0, a0
; RV64ZBP-NEXT: ret
%tmp = call i64 @llvm.riscv.gorc.i64(i64 %a, i64 56)
ret i64 %tmp
}
define i64 @orc4i64(i64 %a) nounwind {
; RV64ZBP-LABEL: orc4i64:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: orc4 a0, a0
; RV64ZBP-NEXT: ret
%tmp = call i64 @llvm.riscv.gorc.i64(i64 %a, i64 60)
ret i64 %tmp
}
define i64 @orc2i64(i64 %a) nounwind {
; RV64ZBP-LABEL: orc2i64:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: orc2 a0, a0
; RV64ZBP-NEXT: ret
%tmp = call i64 @llvm.riscv.gorc.i64(i64 %a, i64 62)
ret i64 %tmp
}
define i64 @orci64(i64 %a) nounwind {
; RV64ZBP-LABEL: orci64:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: orc a0, a0
; RV64ZBP-NEXT: ret
%tmp = call i64 @llvm.riscv.gorc.i64(i64 %a, i64 63)
ret i64 %tmp
}
declare i64 @llvm.riscv.shfl.i64(i64 %a, i64 %b) declare i64 @llvm.riscv.shfl.i64(i64 %a, i64 %b)
define i64 @shfl64(i64 %a, i64 %b) nounwind { define i64 @shfl64(i64 %a, i64 %b) nounwind {
; RV64ZBP-LABEL: shfl64: ; RV64ZBP-LABEL: shfl64:
; RV64ZBP: # %bb.0: ; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: shfl a0, a0, a1 ; RV64ZBP-NEXT: shfl a0, a0, a1
; RV64ZBP-NEXT: ret ; RV64ZBP-NEXT: ret
%tmp = call i64 @llvm.riscv.shfl.i64(i64 %a, i64 %b) %tmp = call i64 @llvm.riscv.shfl.i64(i64 %a, i64 %b)
▲ Show 20 Lines • Show All 329 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rv64zbp.ll

Show First 20 Lines • Show All 607 Lines • ▼ Show 20 Lines; RV64ZBP-NEXT: ret
%shl = and i64 %and, -71777214294589696 %shl = and i64 %and, -71777214294589696
%and1 = lshr i64 %a, 8 %and1 = lshr i64 %a, 8
%shr = and i64 %and1, 71777214294589695 %shr = and i64 %and1, 71777214294589695
%or = or i64 %shr, %a %or = or i64 %shr, %a
%or2 = or i64 %or, %shl %or2 = or i64 %or, %shl
ret i64 %or2 ret i64 %or2
} }
define signext i32 @gorc12_i32(i32 signext %a) nounwind {
; RV64I-LABEL: gorc12_i32:
; RV64I: # %bb.0:
; RV64I-NEXT: slliw a1, a0, 4
; RV64I-NEXT: lui a2, 986895
; RV64I-NEXT: addiw a2, a2, 240
; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: srli a2, a0, 4
; RV64I-NEXT: lui a3, 61681
; RV64I-NEXT: addiw a3, a3, -241
; RV64I-NEXT: and a2, a2, a3
; RV64I-NEXT: or a0, a2, a0
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: slliw a1, a0, 8
; RV64I-NEXT: lui a2, 1044496
; RV64I-NEXT: addiw a2, a2, -256
; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: srli a2, a0, 8
; RV64I-NEXT: lui a3, 4080
; RV64I-NEXT: addiw a3, a3, 255
; RV64I-NEXT: and a2, a2, a3
; RV64I-NEXT: or a0, a2, a0
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret
;
; RV64ZBP-LABEL: gorc12_i32:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: gorciw a0, a0, 12
; RV64ZBP-NEXT: ret
%and1 = shl i32 %a, 4
%shl1 = and i32 %and1, -252645136
%and1b = lshr i32 %a, 4
%shr1 = and i32 %and1b, 252645135
%or1 = or i32 %shr1, %a
%or1b = or i32 %or1, %shl1
%and2 = shl i32 %or1b, 8
%shl2 = and i32 %and2, -16711936
%and2b = lshr i32 %or1b, 8
%shr2 = and i32 %and2b, 16711935
%or2 = or i32 %shr2, %or1b
%or2b = or i32 %or2, %shl2
ret i32 %or2b
}
define i64 @gorc12_i64(i64 %a) nounwind {
; RV64I-LABEL: gorc12_i64:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, %hi(.LCPI17_0)
; RV64I-NEXT: ld a1, %lo(.LCPI17_0)(a1)
; RV64I-NEXT: lui a2, %hi(.LCPI17_1)
; RV64I-NEXT: ld a2, %lo(.LCPI17_1)(a2)
; RV64I-NEXT: slli a3, a0, 4
; RV64I-NEXT: and a1, a3, a1
; RV64I-NEXT: srli a3, a0, 4
; RV64I-NEXT: and a2, a3, a2
; RV64I-NEXT: or a0, a2, a0
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: lui a1, %hi(.LCPI17_2)
; RV64I-NEXT: ld a1, %lo(.LCPI17_2)(a1)
; RV64I-NEXT: lui a2, %hi(.LCPI17_3)
; RV64I-NEXT: ld a2, %lo(.LCPI17_3)(a2)
; RV64I-NEXT: slli a3, a0, 8
; RV64I-NEXT: and a1, a3, a1
; RV64I-NEXT: srli a3, a0, 8
; RV64I-NEXT: and a2, a3, a2
; RV64I-NEXT: or a0, a2, a0
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret
;
; RV64ZBP-LABEL: gorc12_i64:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: orc4.h a0, a0
; RV64ZBP-NEXT: ret
%and1 = shl i64 %a, 4
%shl1 = and i64 %and1, -1085102592571150096
%and1b = lshr i64 %a, 4
%shr1 = and i64 %and1b, 1085102592571150095
%or1 = or i64 %shr1, %a
%or1b = or i64 %or1, %shl1
%and2 = shl i64 %or1b, 8
%shl2 = and i64 %and2, -71777214294589696
%and2b = lshr i64 %or1b, 8
%shr2 = and i64 %and2b, 71777214294589695
%or2 = or i64 %shr2, %or1b
%or2b = or i64 %or2, %shl2
ret i64 %or2b
}
define signext i32 @gorc14_i32(i32 signext %a) nounwind {
; RV64I-LABEL: gorc14_i32:
; RV64I: # %bb.0:
; RV64I-NEXT: slliw a1, a0, 2
; RV64I-NEXT: lui a2, 838861
; RV64I-NEXT: addiw a2, a2, -820
; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: srli a2, a0, 2
; RV64I-NEXT: lui a3, 209715
; RV64I-NEXT: addiw a3, a3, 819
; RV64I-NEXT: and a2, a2, a3
; RV64I-NEXT: or a0, a2, a0
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: slliw a1, a0, 4
; RV64I-NEXT: lui a2, 986895
; RV64I-NEXT: addiw a2, a2, 240
; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: srli a2, a0, 4
; RV64I-NEXT: lui a3, 61681
; RV64I-NEXT: addiw a3, a3, -241
; RV64I-NEXT: and a2, a2, a3
; RV64I-NEXT: or a0, a2, a0
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: slli a1, a0, 8
; RV64I-NEXT: lui a2, 1044496
; RV64I-NEXT: addiw a2, a2, -256
; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: srli a2, a0, 8
; RV64I-NEXT: lui a3, 4080
; RV64I-NEXT: addiw a3, a3, 255
; RV64I-NEXT: and a2, a2, a3
; RV64I-NEXT: or a0, a2, a0
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: sext.w a0, a0
; RV64I-NEXT: ret
;
; RV64ZBP-LABEL: gorc14_i32:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: gorciw a0, a0, 14
; RV64ZBP-NEXT: ret
%and1 = shl i32 %a, 2
%shl1 = and i32 %and1, -858993460
%and1b = lshr i32 %a, 2
%shr1 = and i32 %and1b, 858993459
%or1 = or i32 %shr1, %a
%or1b = or i32 %or1, %shl1
%and2 = shl i32 %or1b, 4
%shl2 = and i32 %and2, -252645136
%and2b = lshr i32 %or1b, 4
%shr2 = and i32 %and2b, 252645135
%or2 = or i32 %shr2, %or1b
%or2b = or i32 %or2, %shl2
%and3 = shl i32 %or2b, 8
%shl3 = and i32 %and3, -16711936
%and3b = lshr i32 %or2b, 8
%shr3 = and i32 %and3b, 16711935
%or3 = or i32 %shr3, %or2b
%or3b = or i32 %or3, %shl3
ret i32 %or3b
}
define i64 @gorc14_i64(i64 %a) nounwind {
; RV64I-LABEL: gorc14_i64:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, %hi(.LCPI19_0)
; RV64I-NEXT: ld a1, %lo(.LCPI19_0)(a1)
; RV64I-NEXT: lui a2, %hi(.LCPI19_1)
; RV64I-NEXT: ld a2, %lo(.LCPI19_1)(a2)
; RV64I-NEXT: slli a3, a0, 2
; RV64I-NEXT: and a1, a3, a1
; RV64I-NEXT: srli a3, a0, 2
; RV64I-NEXT: and a2, a3, a2
; RV64I-NEXT: or a0, a2, a0
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: lui a1, %hi(.LCPI19_2)
; RV64I-NEXT: ld a1, %lo(.LCPI19_2)(a1)
; RV64I-NEXT: lui a2, %hi(.LCPI19_3)
; RV64I-NEXT: ld a2, %lo(.LCPI19_3)(a2)
; RV64I-NEXT: slli a3, a0, 4
; RV64I-NEXT: and a1, a3, a1
; RV64I-NEXT: srli a3, a0, 4
; RV64I-NEXT: and a2, a3, a2
; RV64I-NEXT: or a0, a2, a0
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: lui a1, %hi(.LCPI19_4)
; RV64I-NEXT: ld a1, %lo(.LCPI19_4)(a1)
; RV64I-NEXT: lui a2, %hi(.LCPI19_5)
; RV64I-NEXT: ld a2, %lo(.LCPI19_5)(a2)
; RV64I-NEXT: slli a3, a0, 8
; RV64I-NEXT: and a1, a3, a1
; RV64I-NEXT: srli a3, a0, 8
; RV64I-NEXT: and a2, a3, a2
; RV64I-NEXT: or a0, a2, a0
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret
;
; RV64ZBP-LABEL: gorc14_i64:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: orc2.h a0, a0
; RV64ZBP-NEXT: ret
%and1 = shl i64 %a, 2
%shl1 = and i64 %and1, -3689348814741910324
%and1b = lshr i64 %a, 2
%shr1 = and i64 %and1b, 3689348814741910323
%or1 = or i64 %shr1, %a
%or1b = or i64 %or1, %shl1
%and2 = shl i64 %or1b, 4
%shl2 = and i64 %and2, -1085102592571150096
%and2b = lshr i64 %or1b, 4
%shr2 = and i64 %and2b, 1085102592571150095
%or2 = or i64 %shr2, %or1b
%or2b = or i64 %or2, %shl2
%and3 = shl i64 %or2b, 8
%shl3 = and i64 %and3, -71777214294589696
%and3b = lshr i64 %or2b, 8
%shr3 = and i64 %and3b, 71777214294589695
%or3 = or i64 %shr3, %or2b
%or3b = or i64 %or3, %shl3
ret i64 %or3b
}
define signext i32 @gorc16_i32(i32 signext %a) nounwind { define signext i32 @gorc16_i32(i32 signext %a) nounwind {
; RV64I-LABEL: gorc16_i32: ; RV64I-LABEL: gorc16_i32:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: slliw a1, a0, 16 ; RV64I-NEXT: slliw a1, a0, 16
; RV64I-NEXT: srliw a2, a0, 16 ; RV64I-NEXT: srliw a2, a0, 16
; RV64I-NEXT: or a0, a2, a0 ; RV64I-NEXT: or a0, a2, a0
; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
▲ Show 20 Lines • Show All 136 Lines • ▼ Show 20 Lines; RV64ZBP-NEXT: ret
%or2b = or i32 %or2, %shl2 %or2b = or i32 %or2, %shl2
ret i32 %or2b ret i32 %or2b
} }
; gorc2, gorc2 -> gorc2 ; gorc2, gorc2 -> gorc2
define i64 @gorc2b_i64(i64 %a) nounwind { define i64 @gorc2b_i64(i64 %a) nounwind {
; RV64I-LABEL: gorc2b_i64: ; RV64I-LABEL: gorc2b_i64:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, %hi(.LCPI22_0) ; RV64I-NEXT: lui a1, %hi(.LCPI26_0)
; RV64I-NEXT: ld a1, %lo(.LCPI22_0)(a1) ; RV64I-NEXT: ld a1, %lo(.LCPI26_0)(a1)
; RV64I-NEXT: lui a2, %hi(.LCPI22_1) ; RV64I-NEXT: lui a2, %hi(.LCPI26_1)
; RV64I-NEXT: ld a2, %lo(.LCPI22_1)(a2) ; RV64I-NEXT: ld a2, %lo(.LCPI26_1)(a2)
; RV64I-NEXT: slli a3, a0, 2 ; RV64I-NEXT: slli a3, a0, 2
; RV64I-NEXT: and a3, a3, a1 ; RV64I-NEXT: and a3, a3, a1
; RV64I-NEXT: srli a4, a0, 2 ; RV64I-NEXT: srli a4, a0, 2
; RV64I-NEXT: and a4, a4, a2 ; RV64I-NEXT: and a4, a4, a2
; RV64I-NEXT: or a0, a4, a0 ; RV64I-NEXT: or a0, a4, a0
; RV64I-NEXT: or a0, a0, a3 ; RV64I-NEXT: or a0, a0, a3
; RV64I-NEXT: slli a3, a0, 2 ; RV64I-NEXT: slli a3, a0, 2
; RV64I-NEXT: and a1, a3, a1 ; RV64I-NEXT: and a1, a3, a1
▲ Show 20 Lines • Show All 79 Lines • ▼ Show 20 Lines; RV64ZBP-NEXT: ret
%or3b = or i32 %or3, %shl3 %or3b = or i32 %or3, %shl3
ret i32 %or3b ret i32 %or3b
} }
; gorc1, gorc2, gorc1 -> gorc2 ; gorc1, gorc2, gorc1 -> gorc2
define i64 @gorc3b_i64(i64 %a) nounwind { define i64 @gorc3b_i64(i64 %a) nounwind {
; RV64I-LABEL: gorc3b_i64: ; RV64I-LABEL: gorc3b_i64:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, %hi(.LCPI24_0) ; RV64I-NEXT: lui a1, %hi(.LCPI28_0)
; RV64I-NEXT: ld a1, %lo(.LCPI24_0)(a1) ; RV64I-NEXT: ld a1, %lo(.LCPI28_0)(a1)
; RV64I-NEXT: lui a2, %hi(.LCPI24_1) ; RV64I-NEXT: lui a2, %hi(.LCPI28_1)
; RV64I-NEXT: ld a2, %lo(.LCPI24_1)(a2) ; RV64I-NEXT: ld a2, %lo(.LCPI28_1)(a2)
; RV64I-NEXT: slli a3, a0, 1 ; RV64I-NEXT: slli a3, a0, 1
; RV64I-NEXT: and a3, a3, a1 ; RV64I-NEXT: and a3, a3, a1
; RV64I-NEXT: srli a4, a0, 1 ; RV64I-NEXT: srli a4, a0, 1
; RV64I-NEXT: and a4, a4, a2 ; RV64I-NEXT: and a4, a4, a2
; RV64I-NEXT: or a0, a4, a0 ; RV64I-NEXT: or a0, a4, a0
; RV64I-NEXT: or a0, a0, a3 ; RV64I-NEXT: or a0, a0, a3
; RV64I-NEXT: lui a3, %hi(.LCPI24_2) ; RV64I-NEXT: lui a3, %hi(.LCPI28_2)
; RV64I-NEXT: ld a3, %lo(.LCPI24_2)(a3) ; RV64I-NEXT: ld a3, %lo(.LCPI28_2)(a3)
; RV64I-NEXT: lui a4, %hi(.LCPI24_3) ; RV64I-NEXT: lui a4, %hi(.LCPI28_3)
; RV64I-NEXT: ld a4, %lo(.LCPI24_3)(a4) ; RV64I-NEXT: ld a4, %lo(.LCPI28_3)(a4)
; RV64I-NEXT: slli a5, a0, 2 ; RV64I-NEXT: slli a5, a0, 2
; RV64I-NEXT: and a3, a5, a3 ; RV64I-NEXT: and a3, a5, a3
; RV64I-NEXT: srli a5, a0, 2 ; RV64I-NEXT: srli a5, a0, 2
; RV64I-NEXT: and a4, a5, a4 ; RV64I-NEXT: and a4, a5, a4
; RV64I-NEXT: or a0, a4, a0 ; RV64I-NEXT: or a0, a4, a0
; RV64I-NEXT: or a0, a0, a3 ; RV64I-NEXT: or a0, a0, a3
; RV64I-NEXT: slli a3, a0, 1 ; RV64I-NEXT: slli a3, a0, 1
; RV64I-NEXT: and a1, a3, a1 ; RV64I-NEXT: and a1, a3, a1
▲ Show 20 Lines • Show All 88 Lines • ▼ Show 20 Lines; RV64ZBP-NEXT: ret
%shr = and i32 %and1, 1431655765 %shr = and i32 %and1, 1431655765
%or = or i32 %shl, %shr %or = or i32 %shl, %shr
ret i32 %or ret i32 %or
} }
define i64 @grev1_i64(i64 %a) nounwind { define i64 @grev1_i64(i64 %a) nounwind {
; RV64I-LABEL: grev1_i64: ; RV64I-LABEL: grev1_i64:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, %hi(.LCPI28_0) ; RV64I-NEXT: lui a1, %hi(.LCPI32_0)
; RV64I-NEXT: ld a1, %lo(.LCPI28_0)(a1) ; RV64I-NEXT: ld a1, %lo(.LCPI32_0)(a1)
; RV64I-NEXT: lui a2, %hi(.LCPI28_1) ; RV64I-NEXT: lui a2, %hi(.LCPI32_1)
; RV64I-NEXT: ld a2, %lo(.LCPI28_1)(a2) ; RV64I-NEXT: ld a2, %lo(.LCPI32_1)(a2)
; RV64I-NEXT: slli a3, a0, 1 ; RV64I-NEXT: slli a3, a0, 1
; RV64I-NEXT: and a1, a3, a1 ; RV64I-NEXT: and a1, a3, a1
; RV64I-NEXT: srli a0, a0, 1 ; RV64I-NEXT: srli a0, a0, 1
; RV64I-NEXT: and a0, a0, a2 ; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64ZBP-LABEL: grev1_i64: ; RV64ZBP-LABEL: grev1_i64:
Show All 32 Lines; RV64ZBP-NEXT: ret
%shr = and i32 %and1, 858993459 %shr = and i32 %and1, 858993459
%or = or i32 %shl, %shr %or = or i32 %shl, %shr
ret i32 %or ret i32 %or
} }
define i64 @grev2_i64(i64 %a) nounwind { define i64 @grev2_i64(i64 %a) nounwind {
; RV64I-LABEL: grev2_i64: ; RV64I-LABEL: grev2_i64:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, %hi(.LCPI30_0) ; RV64I-NEXT: lui a1, %hi(.LCPI34_0)
; RV64I-NEXT: ld a1, %lo(.LCPI30_0)(a1) ; RV64I-NEXT: ld a1, %lo(.LCPI34_0)(a1)
; RV64I-NEXT: lui a2, %hi(.LCPI30_1) ; RV64I-NEXT: lui a2, %hi(.LCPI34_1)
; RV64I-NEXT: ld a2, %lo(.LCPI30_1)(a2) ; RV64I-NEXT: ld a2, %lo(.LCPI34_1)(a2)
; RV64I-NEXT: slli a3, a0, 2 ; RV64I-NEXT: slli a3, a0, 2
; RV64I-NEXT: and a1, a3, a1 ; RV64I-NEXT: and a1, a3, a1
; RV64I-NEXT: srli a0, a0, 2 ; RV64I-NEXT: srli a0, a0, 2
; RV64I-NEXT: and a0, a0, a2 ; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64ZBP-LABEL: grev2_i64: ; RV64ZBP-LABEL: grev2_i64:
▲ Show 20 Lines • Show All 46 Lines • ▼ Show 20 Lines; RV64ZBP-NEXT: ret
%shr2 = and i32 %and2b, 858993459 %shr2 = and i32 %and2b, 858993459
%or2 = or i32 %shl2, %shr2 %or2 = or i32 %shl2, %shr2
ret i32 %or2 ret i32 %or2
} }
define i64 @grev3_i64(i64 %a) nounwind { define i64 @grev3_i64(i64 %a) nounwind {
; RV64I-LABEL: grev3_i64: ; RV64I-LABEL: grev3_i64:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, %hi(.LCPI32_0) ; RV64I-NEXT: lui a1, %hi(.LCPI36_0)
; RV64I-NEXT: ld a1, %lo(.LCPI32_0)(a1) ; RV64I-NEXT: ld a1, %lo(.LCPI36_0)(a1)
; RV64I-NEXT: lui a2, %hi(.LCPI32_1) ; RV64I-NEXT: lui a2, %hi(.LCPI36_1)
; RV64I-NEXT: ld a2, %lo(.LCPI32_1)(a2) ; RV64I-NEXT: ld a2, %lo(.LCPI36_1)(a2)
; RV64I-NEXT: slli a3, a0, 1 ; RV64I-NEXT: slli a3, a0, 1
; RV64I-NEXT: and a1, a3, a1 ; RV64I-NEXT: and a1, a3, a1
; RV64I-NEXT: srli a0, a0, 1 ; RV64I-NEXT: srli a0, a0, 1
; RV64I-NEXT: and a0, a0, a2 ; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: lui a1, %hi(.LCPI32_2) ; RV64I-NEXT: lui a1, %hi(.LCPI36_2)
; RV64I-NEXT: ld a1, %lo(.LCPI32_2)(a1) ; RV64I-NEXT: ld a1, %lo(.LCPI36_2)(a1)
; RV64I-NEXT: lui a2, %hi(.LCPI32_3) ; RV64I-NEXT: lui a2, %hi(.LCPI36_3)
; RV64I-NEXT: ld a2, %lo(.LCPI32_3)(a2) ; RV64I-NEXT: ld a2, %lo(.LCPI36_3)(a2)
; RV64I-NEXT: slli a3, a0, 2 ; RV64I-NEXT: slli a3, a0, 2
; RV64I-NEXT: and a1, a3, a1 ; RV64I-NEXT: and a1, a3, a1
; RV64I-NEXT: srli a0, a0, 2 ; RV64I-NEXT: srli a0, a0, 2
; RV64I-NEXT: and a0, a0, a2 ; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64ZBP-LABEL: grev3_i64: ; RV64ZBP-LABEL: grev3_i64:
Show All 37 Lines; RV64ZBP-NEXT: ret
%shr = and i32 %and1, 252645135 %shr = and i32 %and1, 252645135
%or = or i32 %shl, %shr %or = or i32 %shl, %shr
ret i32 %or ret i32 %or
} }
define i64 @grev4_i64(i64 %a) nounwind { define i64 @grev4_i64(i64 %a) nounwind {
; RV64I-LABEL: grev4_i64: ; RV64I-LABEL: grev4_i64:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, %hi(.LCPI34_0) ; RV64I-NEXT: lui a1, %hi(.LCPI38_0)
; RV64I-NEXT: ld a1, %lo(.LCPI34_0)(a1) ; RV64I-NEXT: ld a1, %lo(.LCPI38_0)(a1)
; RV64I-NEXT: lui a2, %hi(.LCPI34_1) ; RV64I-NEXT: lui a2, %hi(.LCPI38_1)
; RV64I-NEXT: ld a2, %lo(.LCPI34_1)(a2) ; RV64I-NEXT: ld a2, %lo(.LCPI38_1)(a2)
; RV64I-NEXT: slli a3, a0, 4 ; RV64I-NEXT: slli a3, a0, 4
; RV64I-NEXT: and a1, a3, a1 ; RV64I-NEXT: and a1, a3, a1
; RV64I-NEXT: srli a0, a0, 4 ; RV64I-NEXT: srli a0, a0, 4
; RV64I-NEXT: and a0, a0, a2 ; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64ZBP-LABEL: grev4_i64: ; RV64ZBP-LABEL: grev4_i64:
▲ Show 20 Lines • Show All 46 Lines • ▼ Show 20 Lines; RV64ZBP-NEXT: ret
%shr2 = and i32 %and2b, 252645135 %shr2 = and i32 %and2b, 252645135
%or2 = or i32 %shl2, %shr2 %or2 = or i32 %shl2, %shr2
ret i32 %or2 ret i32 %or2
} }
define i64 @grev5_i64(i64 %a) nounwind { define i64 @grev5_i64(i64 %a) nounwind {
; RV64I-LABEL: grev5_i64: ; RV64I-LABEL: grev5_i64:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, %hi(.LCPI36_0) ; RV64I-NEXT: lui a1, %hi(.LCPI40_0)
; RV64I-NEXT: ld a1, %lo(.LCPI36_0)(a1) ; RV64I-NEXT: ld a1, %lo(.LCPI40_0)(a1)
; RV64I-NEXT: lui a2, %hi(.LCPI36_1) ; RV64I-NEXT: lui a2, %hi(.LCPI40_1)
; RV64I-NEXT: ld a2, %lo(.LCPI36_1)(a2) ; RV64I-NEXT: ld a2, %lo(.LCPI40_1)(a2)
; RV64I-NEXT: slli a3, a0, 1 ; RV64I-NEXT: slli a3, a0, 1
; RV64I-NEXT: and a1, a3, a1 ; RV64I-NEXT: and a1, a3, a1
; RV64I-NEXT: srli a0, a0, 1 ; RV64I-NEXT: srli a0, a0, 1
; RV64I-NEXT: and a0, a0, a2 ; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: lui a1, %hi(.LCPI36_2) ; RV64I-NEXT: lui a1, %hi(.LCPI40_2)
; RV64I-NEXT: ld a1, %lo(.LCPI36_2)(a1) ; RV64I-NEXT: ld a1, %lo(.LCPI40_2)(a1)
; RV64I-NEXT: lui a2, %hi(.LCPI36_3) ; RV64I-NEXT: lui a2, %hi(.LCPI40_3)
; RV64I-NEXT: ld a2, %lo(.LCPI36_3)(a2) ; RV64I-NEXT: ld a2, %lo(.LCPI40_3)(a2)
; RV64I-NEXT: slli a3, a0, 4 ; RV64I-NEXT: slli a3, a0, 4
; RV64I-NEXT: and a1, a3, a1 ; RV64I-NEXT: and a1, a3, a1
; RV64I-NEXT: srli a0, a0, 4 ; RV64I-NEXT: srli a0, a0, 4
; RV64I-NEXT: and a0, a0, a2 ; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64ZBP-LABEL: grev5_i64: ; RV64ZBP-LABEL: grev5_i64:
▲ Show 20 Lines • Show All 52 Lines • ▼ Show 20 Lines; RV64ZBP-NEXT: ret
%shr2 = and i32 %and2b, 252645135 %shr2 = and i32 %and2b, 252645135
%or2 = or i32 %shl2, %shr2 %or2 = or i32 %shl2, %shr2
ret i32 %or2 ret i32 %or2
} }
define i64 @grev6_i64(i64 %a) nounwind { define i64 @grev6_i64(i64 %a) nounwind {
; RV64I-LABEL: grev6_i64: ; RV64I-LABEL: grev6_i64:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, %hi(.LCPI38_0) ; RV64I-NEXT: lui a1, %hi(.LCPI42_0)
; RV64I-NEXT: ld a1, %lo(.LCPI38_0)(a1) ; RV64I-NEXT: ld a1, %lo(.LCPI42_0)(a1)
; RV64I-NEXT: lui a2, %hi(.LCPI38_1) ; RV64I-NEXT: lui a2, %hi(.LCPI42_1)
; RV64I-NEXT: ld a2, %lo(.LCPI38_1)(a2) ; RV64I-NEXT: ld a2, %lo(.LCPI42_1)(a2)
; RV64I-NEXT: slli a3, a0, 2 ; RV64I-NEXT: slli a3, a0, 2
; RV64I-NEXT: and a1, a3, a1 ; RV64I-NEXT: and a1, a3, a1
; RV64I-NEXT: srli a0, a0, 2 ; RV64I-NEXT: srli a0, a0, 2
; RV64I-NEXT: and a0, a0, a2 ; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: lui a1, %hi(.LCPI38_2) ; RV64I-NEXT: lui a1, %hi(.LCPI42_2)
; RV64I-NEXT: ld a1, %lo(.LCPI38_2)(a1) ; RV64I-NEXT: ld a1, %lo(.LCPI42_2)(a1)
; RV64I-NEXT: lui a2, %hi(.LCPI38_3) ; RV64I-NEXT: lui a2, %hi(.LCPI42_3)
; RV64I-NEXT: ld a2, %lo(.LCPI38_3)(a2) ; RV64I-NEXT: ld a2, %lo(.LCPI42_3)(a2)
; RV64I-NEXT: slli a3, a0, 4 ; RV64I-NEXT: slli a3, a0, 4
; RV64I-NEXT: and a1, a3, a1 ; RV64I-NEXT: and a1, a3, a1
; RV64I-NEXT: srli a0, a0, 4 ; RV64I-NEXT: srli a0, a0, 4
; RV64I-NEXT: and a0, a0, a2 ; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64ZBP-LABEL: grev6_i64: ; RV64ZBP-LABEL: grev6_i64:
▲ Show 20 Lines • Show All 65 Lines • ▼ Show 20 Lines; RV64ZBP-NEXT: ret
%shr3 = and i32 %and3b, 252645135 %shr3 = and i32 %and3b, 252645135
%or3 = or i32 %shl3, %shr3 %or3 = or i32 %shl3, %shr3
ret i32 %or3 ret i32 %or3
} }
define i64 @grev7_i64(i64 %a) nounwind { define i64 @grev7_i64(i64 %a) nounwind {
; RV64I-LABEL: grev7_i64: ; RV64I-LABEL: grev7_i64:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, %hi(.LCPI40_0) ; RV64I-NEXT: lui a1, %hi(.LCPI44_0)
; RV64I-NEXT: ld a1, %lo(.LCPI40_0)(a1) ; RV64I-NEXT: ld a1, %lo(.LCPI44_0)(a1)
; RV64I-NEXT: lui a2, %hi(.LCPI40_1) ; RV64I-NEXT: lui a2, %hi(.LCPI44_1)
; RV64I-NEXT: ld a2, %lo(.LCPI40_1)(a2) ; RV64I-NEXT: ld a2, %lo(.LCPI44_1)(a2)
; RV64I-NEXT: slli a3, a0, 1 ; RV64I-NEXT: slli a3, a0, 1
; RV64I-NEXT: and a1, a3, a1 ; RV64I-NEXT: and a1, a3, a1
; RV64I-NEXT: srli a0, a0, 1 ; RV64I-NEXT: srli a0, a0, 1
; RV64I-NEXT: and a0, a0, a2 ; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: lui a1, %hi(.LCPI40_2) ; RV64I-NEXT: lui a1, %hi(.LCPI44_2)
; RV64I-NEXT: ld a1, %lo(.LCPI40_2)(a1) ; RV64I-NEXT: ld a1, %lo(.LCPI44_2)(a1)
; RV64I-NEXT: lui a2, %hi(.LCPI40_3) ; RV64I-NEXT: lui a2, %hi(.LCPI44_3)
; RV64I-NEXT: ld a2, %lo(.LCPI40_3)(a2) ; RV64I-NEXT: ld a2, %lo(.LCPI44_3)(a2)
; RV64I-NEXT: slli a3, a0, 2 ; RV64I-NEXT: slli a3, a0, 2
; RV64I-NEXT: and a1, a3, a1 ; RV64I-NEXT: and a1, a3, a1
; RV64I-NEXT: srli a0, a0, 2 ; RV64I-NEXT: srli a0, a0, 2
; RV64I-NEXT: and a0, a0, a2 ; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: lui a1, %hi(.LCPI40_4) ; RV64I-NEXT: lui a1, %hi(.LCPI44_4)
; RV64I-NEXT: ld a1, %lo(.LCPI40_4)(a1) ; RV64I-NEXT: ld a1, %lo(.LCPI44_4)(a1)
; RV64I-NEXT: lui a2, %hi(.LCPI40_5) ; RV64I-NEXT: lui a2, %hi(.LCPI44_5)
; RV64I-NEXT: ld a2, %lo(.LCPI40_5)(a2) ; RV64I-NEXT: ld a2, %lo(.LCPI44_5)(a2)
; RV64I-NEXT: slli a3, a0, 4 ; RV64I-NEXT: slli a3, a0, 4
; RV64I-NEXT: and a1, a3, a1 ; RV64I-NEXT: and a1, a3, a1
; RV64I-NEXT: srli a0, a0, 4 ; RV64I-NEXT: srli a0, a0, 4
; RV64I-NEXT: and a0, a0, a2 ; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64ZBP-LABEL: grev7_i64: ; RV64ZBP-LABEL: grev7_i64:
▲ Show 20 Lines • Show All 42 Lines • ▼ Show 20 Lines; RV64ZBP-NEXT: ret
%shr = and i32 %and1, 16711935 %shr = and i32 %and1, 16711935
%or = or i32 %shl, %shr %or = or i32 %shl, %shr
ret i32 %or ret i32 %or
} }
define i64 @grev8_i64(i64 %a) nounwind { define i64 @grev8_i64(i64 %a) nounwind {
; RV64I-LABEL: grev8_i64: ; RV64I-LABEL: grev8_i64:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, %hi(.LCPI42_0) ; RV64I-NEXT: lui a1, %hi(.LCPI46_0)
; RV64I-NEXT: ld a1, %lo(.LCPI42_0)(a1) ; RV64I-NEXT: ld a1, %lo(.LCPI46_0)(a1)
; RV64I-NEXT: lui a2, %hi(.LCPI42_1) ; RV64I-NEXT: lui a2, %hi(.LCPI46_1)
; RV64I-NEXT: ld a2, %lo(.LCPI42_1)(a2) ; RV64I-NEXT: ld a2, %lo(.LCPI46_1)(a2)
; RV64I-NEXT: slli a3, a0, 8 ; RV64I-NEXT: slli a3, a0, 8
; RV64I-NEXT: and a1, a3, a1 ; RV64I-NEXT: and a1, a3, a1
; RV64I-NEXT: srli a0, a0, 8 ; RV64I-NEXT: srli a0, a0, 8
; RV64I-NEXT: and a0, a0, a2 ; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64ZBP-LABEL: grev8_i64: ; RV64ZBP-LABEL: grev8_i64:
▲ Show 20 Lines • Show All 46 Lines • ▼ Show 20 Lines; RV64ZBP-NEXT: ret
%shr2 = and i32 %and2b, 16711935 %shr2 = and i32 %and2b, 16711935
%or2 = or i32 %shl2, %shr2 %or2 = or i32 %shl2, %shr2
ret i32 %or2 ret i32 %or2
} }
define i64 @grev12_i64(i64 %a) nounwind { define i64 @grev12_i64(i64 %a) nounwind {
; RV64I-LABEL: grev12_i64: ; RV64I-LABEL: grev12_i64:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, %hi(.LCPI44_0) ; RV64I-NEXT: lui a1, %hi(.LCPI48_0)
; RV64I-NEXT: ld a1, %lo(.LCPI44_0)(a1) ; RV64I-NEXT: ld a1, %lo(.LCPI48_0)(a1)
; RV64I-NEXT: lui a2, %hi(.LCPI44_1) ; RV64I-NEXT: lui a2, %hi(.LCPI48_1)
; RV64I-NEXT: ld a2, %lo(.LCPI44_1)(a2) ; RV64I-NEXT: ld a2, %lo(.LCPI48_1)(a2)
; RV64I-NEXT: slli a3, a0, 4 ; RV64I-NEXT: slli a3, a0, 4
; RV64I-NEXT: and a1, a3, a1 ; RV64I-NEXT: and a1, a3, a1
; RV64I-NEXT: srli a0, a0, 4 ; RV64I-NEXT: srli a0, a0, 4
; RV64I-NEXT: and a0, a0, a2 ; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: lui a1, %hi(.LCPI44_2) ; RV64I-NEXT: lui a1, %hi(.LCPI48_2)
; RV64I-NEXT: ld a1, %lo(.LCPI44_2)(a1) ; RV64I-NEXT: ld a1, %lo(.LCPI48_2)(a1)
; RV64I-NEXT: lui a2, %hi(.LCPI44_3) ; RV64I-NEXT: lui a2, %hi(.LCPI48_3)
; RV64I-NEXT: ld a2, %lo(.LCPI44_3)(a2) ; RV64I-NEXT: ld a2, %lo(.LCPI48_3)(a2)
; RV64I-NEXT: slli a3, a0, 8 ; RV64I-NEXT: slli a3, a0, 8
; RV64I-NEXT: and a1, a3, a1 ; RV64I-NEXT: and a1, a3, a1
; RV64I-NEXT: srli a0, a0, 8 ; RV64I-NEXT: srli a0, a0, 8
; RV64I-NEXT: and a0, a0, a2 ; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64ZBP-LABEL: grev12_i64: ; RV64ZBP-LABEL: grev12_i64:
▲ Show 20 Lines • Show All 65 Lines • ▼ Show 20 Lines; RV64ZBP-NEXT: ret
%shr3 = and i32 %and3b, 16711935 %shr3 = and i32 %and3b, 16711935
%or3 = or i32 %shl3, %shr3 %or3 = or i32 %shl3, %shr3
ret i32 %or3 ret i32 %or3
} }
define i64 @grev14_i64(i64 %a) nounwind { define i64 @grev14_i64(i64 %a) nounwind {
; RV64I-LABEL: grev14_i64: ; RV64I-LABEL: grev14_i64:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, %hi(.LCPI46_0) ; RV64I-NEXT: lui a1, %hi(.LCPI50_0)
; RV64I-NEXT: ld a1, %lo(.LCPI46_0)(a1) ; RV64I-NEXT: ld a1, %lo(.LCPI50_0)(a1)
; RV64I-NEXT: lui a2, %hi(.LCPI46_1) ; RV64I-NEXT: lui a2, %hi(.LCPI50_1)
; RV64I-NEXT: ld a2, %lo(.LCPI46_1)(a2) ; RV64I-NEXT: ld a2, %lo(.LCPI50_1)(a2)
; RV64I-NEXT: slli a3, a0, 2 ; RV64I-NEXT: slli a3, a0, 2
; RV64I-NEXT: and a1, a3, a1 ; RV64I-NEXT: and a1, a3, a1
; RV64I-NEXT: srli a0, a0, 2 ; RV64I-NEXT: srli a0, a0, 2
; RV64I-NEXT: and a0, a0, a2 ; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: lui a1, %hi(.LCPI46_2) ; RV64I-NEXT: lui a1, %hi(.LCPI50_2)
; RV64I-NEXT: ld a1, %lo(.LCPI46_2)(a1) ; RV64I-NEXT: ld a1, %lo(.LCPI50_2)(a1)
; RV64I-NEXT: lui a2, %hi(.LCPI46_3) ; RV64I-NEXT: lui a2, %hi(.LCPI50_3)
; RV64I-NEXT: ld a2, %lo(.LCPI46_3)(a2) ; RV64I-NEXT: ld a2, %lo(.LCPI50_3)(a2)
; RV64I-NEXT: slli a3, a0, 4 ; RV64I-NEXT: slli a3, a0, 4
; RV64I-NEXT: and a1, a3, a1 ; RV64I-NEXT: and a1, a3, a1
; RV64I-NEXT: srli a0, a0, 4 ; RV64I-NEXT: srli a0, a0, 4
; RV64I-NEXT: and a0, a0, a2 ; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: lui a1, %hi(.LCPI46_4) ; RV64I-NEXT: lui a1, %hi(.LCPI50_4)
; RV64I-NEXT: ld a1, %lo(.LCPI46_4)(a1) ; RV64I-NEXT: ld a1, %lo(.LCPI50_4)(a1)
; RV64I-NEXT: lui a2, %hi(.LCPI46_5) ; RV64I-NEXT: lui a2, %hi(.LCPI50_5)
; RV64I-NEXT: ld a2, %lo(.LCPI46_5)(a2) ; RV64I-NEXT: ld a2, %lo(.LCPI50_5)(a2)
; RV64I-NEXT: slli a3, a0, 8 ; RV64I-NEXT: slli a3, a0, 8
; RV64I-NEXT: and a1, a3, a1 ; RV64I-NEXT: and a1, a3, a1
; RV64I-NEXT: srli a0, a0, 8 ; RV64I-NEXT: srli a0, a0, 8
; RV64I-NEXT: and a0, a0, a2 ; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64ZBP-LABEL: grev14_i64: ; RV64ZBP-LABEL: grev14_i64:
▲ Show 20 Lines • Show All 156 Lines • ▼ Show 20 Lines; RV64ZBP-NEXT: ret
%shr1 = and i32 %and1b, 1431655765 %shr1 = and i32 %and1b, 1431655765
%or1 = or i32 %shl1, %shr1 %or1 = or i32 %shl1, %shr1
ret i32 %or1 ret i32 %or1
} }
define i64 @grev3b_i64(i64 %a) nounwind { define i64 @grev3b_i64(i64 %a) nounwind {
; RV64I-LABEL: grev3b_i64: ; RV64I-LABEL: grev3b_i64:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, %hi(.LCPI53_0) ; RV64I-NEXT: lui a1, %hi(.LCPI57_0)
; RV64I-NEXT: ld a1, %lo(.LCPI53_0)(a1) ; RV64I-NEXT: ld a1, %lo(.LCPI57_0)(a1)
; RV64I-NEXT: lui a2, %hi(.LCPI53_1) ; RV64I-NEXT: lui a2, %hi(.LCPI57_1)
; RV64I-NEXT: ld a2, %lo(.LCPI53_1)(a2) ; RV64I-NEXT: ld a2, %lo(.LCPI57_1)(a2)
; RV64I-NEXT: slli a3, a0, 2 ; RV64I-NEXT: slli a3, a0, 2
; RV64I-NEXT: and a1, a3, a1 ; RV64I-NEXT: and a1, a3, a1
; RV64I-NEXT: srli a0, a0, 2 ; RV64I-NEXT: srli a0, a0, 2
; RV64I-NEXT: and a0, a0, a2 ; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: lui a1, %hi(.LCPI53_2) ; RV64I-NEXT: lui a1, %hi(.LCPI57_2)
; RV64I-NEXT: ld a1, %lo(.LCPI53_2)(a1) ; RV64I-NEXT: ld a1, %lo(.LCPI57_2)(a1)
; RV64I-NEXT: lui a2, %hi(.LCPI53_3) ; RV64I-NEXT: lui a2, %hi(.LCPI57_3)
; RV64I-NEXT: ld a2, %lo(.LCPI53_3)(a2) ; RV64I-NEXT: ld a2, %lo(.LCPI57_3)(a2)
; RV64I-NEXT: slli a3, a0, 1 ; RV64I-NEXT: slli a3, a0, 1
; RV64I-NEXT: and a1, a3, a1 ; RV64I-NEXT: and a1, a3, a1
; RV64I-NEXT: srli a0, a0, 1 ; RV64I-NEXT: srli a0, a0, 1
; RV64I-NEXT: and a0, a0, a2 ; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64ZBP-LABEL: grev3b_i64: ; RV64ZBP-LABEL: grev3b_i64:
▲ Show 20 Lines • Show All 63 Lines • ▼ Show 20 Lines; RV64ZBP-NEXT: ret
%or3 = or i32 %shl3, %shr3 %or3 = or i32 %shl3, %shr3
ret i32 %or3 ret i32 %or3
} }
; grev1, grev2, grev1 -> grev2 ; grev1, grev2, grev1 -> grev2
define i64 @grev2b_i64(i64 %a) nounwind { define i64 @grev2b_i64(i64 %a) nounwind {
; RV64I-LABEL: grev2b_i64: ; RV64I-LABEL: grev2b_i64:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, %hi(.LCPI55_0) ; RV64I-NEXT: lui a1, %hi(.LCPI59_0)
; RV64I-NEXT: ld a1, %lo(.LCPI55_0)(a1) ; RV64I-NEXT: ld a1, %lo(.LCPI59_0)(a1)
; RV64I-NEXT: lui a2, %hi(.LCPI55_1) ; RV64I-NEXT: lui a2, %hi(.LCPI59_1)
; RV64I-NEXT: ld a2, %lo(.LCPI55_1)(a2) ; RV64I-NEXT: ld a2, %lo(.LCPI59_1)(a2)
; RV64I-NEXT: slli a3, a0, 1 ; RV64I-NEXT: slli a3, a0, 1
; RV64I-NEXT: and a3, a3, a1 ; RV64I-NEXT: and a3, a3, a1
; RV64I-NEXT: srli a0, a0, 1 ; RV64I-NEXT: srli a0, a0, 1
; RV64I-NEXT: and a0, a0, a2 ; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: or a0, a3, a0 ; RV64I-NEXT: or a0, a3, a0
; RV64I-NEXT: lui a3, %hi(.LCPI55_2) ; RV64I-NEXT: lui a3, %hi(.LCPI59_2)
; RV64I-NEXT: ld a3, %lo(.LCPI55_2)(a3) ; RV64I-NEXT: ld a3, %lo(.LCPI59_2)(a3)
; RV64I-NEXT: lui a4, %hi(.LCPI55_3) ; RV64I-NEXT: lui a4, %hi(.LCPI59_3)
; RV64I-NEXT: ld a4, %lo(.LCPI55_3)(a4) ; RV64I-NEXT: ld a4, %lo(.LCPI59_3)(a4)
; RV64I-NEXT: slli a5, a0, 2 ; RV64I-NEXT: slli a5, a0, 2
; RV64I-NEXT: and a3, a5, a3 ; RV64I-NEXT: and a3, a5, a3
; RV64I-NEXT: srli a0, a0, 2 ; RV64I-NEXT: srli a0, a0, 2
; RV64I-NEXT: and a0, a0, a4 ; RV64I-NEXT: and a0, a0, a4
; RV64I-NEXT: or a0, a3, a0 ; RV64I-NEXT: or a0, a3, a0
; RV64I-NEXT: slli a3, a0, 1 ; RV64I-NEXT: slli a3, a0, 1
; RV64I-NEXT: and a1, a3, a1 ; RV64I-NEXT: and a1, a3, a1
; RV64I-NEXT: srli a0, a0, 1 ; RV64I-NEXT: srli a0, a0, 1
▲ Show 20 Lines • Show All 82 Lines • ▼ Show 20 Lines; RV64ZBP-NEXT: ret
%or4 = or i32 %shl4, %shr4 %or4 = or i32 %shl4, %shr4
ret i32 %or4 ret i32 %or4
} }
; grev1, grev2, grev1, grev2 -> identity ; grev1, grev2, grev1, grev2 -> identity
define i64 @grev0_i64(i64 %a) nounwind { define i64 @grev0_i64(i64 %a) nounwind {
; RV64I-LABEL: grev0_i64: ; RV64I-LABEL: grev0_i64:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, %hi(.LCPI57_0) ; RV64I-NEXT: lui a1, %hi(.LCPI61_0)
; RV64I-NEXT: ld a1, %lo(.LCPI57_0)(a1) ; RV64I-NEXT: ld a1, %lo(.LCPI61_0)(a1)
; RV64I-NEXT: lui a2, %hi(.LCPI57_1) ; RV64I-NEXT: lui a2, %hi(.LCPI61_1)
; RV64I-NEXT: ld a2, %lo(.LCPI57_1)(a2) ; RV64I-NEXT: ld a2, %lo(.LCPI61_1)(a2)
; RV64I-NEXT: slli a3, a0, 1 ; RV64I-NEXT: slli a3, a0, 1
; RV64I-NEXT: and a3, a3, a1 ; RV64I-NEXT: and a3, a3, a1
; RV64I-NEXT: srli a0, a0, 1 ; RV64I-NEXT: srli a0, a0, 1
; RV64I-NEXT: and a0, a0, a2 ; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: or a0, a3, a0 ; RV64I-NEXT: or a0, a3, a0
; RV64I-NEXT: lui a3, %hi(.LCPI57_2) ; RV64I-NEXT: lui a3, %hi(.LCPI61_2)
; RV64I-NEXT: ld a3, %lo(.LCPI57_2)(a3) ; RV64I-NEXT: ld a3, %lo(.LCPI61_2)(a3)
; RV64I-NEXT: lui a4, %hi(.LCPI57_3) ; RV64I-NEXT: lui a4, %hi(.LCPI61_3)
; RV64I-NEXT: ld a4, %lo(.LCPI57_3)(a4) ; RV64I-NEXT: ld a4, %lo(.LCPI61_3)(a4)
; RV64I-NEXT: slli a5, a0, 2 ; RV64I-NEXT: slli a5, a0, 2
; RV64I-NEXT: and a5, a5, a3 ; RV64I-NEXT: and a5, a5, a3
; RV64I-NEXT: srli a0, a0, 2 ; RV64I-NEXT: srli a0, a0, 2
; RV64I-NEXT: and a0, a0, a4 ; RV64I-NEXT: and a0, a0, a4
; RV64I-NEXT: or a0, a5, a0 ; RV64I-NEXT: or a0, a5, a0
; RV64I-NEXT: slli a5, a0, 1 ; RV64I-NEXT: slli a5, a0, 1
; RV64I-NEXT: and a1, a5, a1 ; RV64I-NEXT: and a1, a5, a1
; RV64I-NEXT: srli a0, a0, 1 ; RV64I-NEXT: srli a0, a0, 1
▲ Show 20 Lines • Show All 378 Lines • ▼ Show 20 Lines
; RV64I-NEXT: srliw a4, a0, 24 ; RV64I-NEXT: srliw a4, a0, 24
; RV64I-NEXT: slli a4, a4, 32 ; RV64I-NEXT: slli a4, a4, 32
; RV64I-NEXT: or a2, a2, a4 ; RV64I-NEXT: or a2, a2, a4
; RV64I-NEXT: slli a4, a0, 40 ; RV64I-NEXT: slli a4, a0, 40
; RV64I-NEXT: slli a3, a3, 48 ; RV64I-NEXT: slli a3, a3, 48
; RV64I-NEXT: and a3, a4, a3 ; RV64I-NEXT: and a3, a4, a3
; RV64I-NEXT: slli a0, a0, 56 ; RV64I-NEXT: slli a0, a0, 56
; RV64I-NEXT: or a0, a0, a3 ; RV64I-NEXT: or a0, a0, a3
; RV64I-NEXT: lui a3, %hi(.LCPI68_0) ; RV64I-NEXT: lui a3, %hi(.LCPI72_0)
; RV64I-NEXT: ld a3, %lo(.LCPI68_0)(a3) ; RV64I-NEXT: ld a3, %lo(.LCPI72_0)(a3)
; RV64I-NEXT: or a0, a0, a2 ; RV64I-NEXT: or a0, a0, a2
; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: srli a1, a0, 4 ; RV64I-NEXT: srli a1, a0, 4
; RV64I-NEXT: and a1, a1, a3 ; RV64I-NEXT: and a1, a1, a3
; RV64I-NEXT: and a0, a0, a3 ; RV64I-NEXT: and a0, a0, a3
; RV64I-NEXT: lui a2, %hi(.LCPI68_1) ; RV64I-NEXT: lui a2, %hi(.LCPI72_1)
; RV64I-NEXT: ld a2, %lo(.LCPI68_1)(a2) ; RV64I-NEXT: ld a2, %lo(.LCPI72_1)(a2)
; RV64I-NEXT: slli a0, a0, 4 ; RV64I-NEXT: slli a0, a0, 4
; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: srli a1, a0, 2 ; RV64I-NEXT: srli a1, a0, 2
; RV64I-NEXT: and a1, a1, a2 ; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: and a0, a0, a2 ; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: lui a2, %hi(.LCPI68_2) ; RV64I-NEXT: lui a2, %hi(.LCPI72_2)
; RV64I-NEXT: ld a2, %lo(.LCPI68_2)(a2) ; RV64I-NEXT: ld a2, %lo(.LCPI72_2)(a2)
; RV64I-NEXT: slli a0, a0, 2 ; RV64I-NEXT: slli a0, a0, 2
; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: srli a1, a0, 1 ; RV64I-NEXT: srli a1, a0, 1
; RV64I-NEXT: and a1, a1, a2 ; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: and a0, a0, a2 ; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: slli a0, a0, 1 ; RV64I-NEXT: slli a0, a0, 1
; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
▲ Show 20 Lines • Show All 91 Lines • ▼ Show 20 Lines; RV64ZBP-NEXT: ret
%1 = call i32 @llvm.bitreverse.i32(i32 %a) %1 = call i32 @llvm.bitreverse.i32(i32 %a)
%2 = call i32 @llvm.bswap.i32(i32 %1) %2 = call i32 @llvm.bswap.i32(i32 %1)
ret i32 %2 ret i32 %2
} }
define i64 @bitreverse_bswap_i64(i64 %a) { define i64 @bitreverse_bswap_i64(i64 %a) {
; RV64I-LABEL: bitreverse_bswap_i64: ; RV64I-LABEL: bitreverse_bswap_i64:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, %hi(.LCPI72_0) ; RV64I-NEXT: lui a1, %hi(.LCPI76_0)
; RV64I-NEXT: ld a1, %lo(.LCPI72_0)(a1) ; RV64I-NEXT: ld a1, %lo(.LCPI76_0)(a1)
; RV64I-NEXT: srli a2, a0, 4 ; RV64I-NEXT: srli a2, a0, 4
; RV64I-NEXT: and a2, a2, a1 ; RV64I-NEXT: and a2, a2, a1
; RV64I-NEXT: and a0, a0, a1 ; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: lui a1, %hi(.LCPI72_1) ; RV64I-NEXT: lui a1, %hi(.LCPI76_1)
; RV64I-NEXT: ld a1, %lo(.LCPI72_1)(a1) ; RV64I-NEXT: ld a1, %lo(.LCPI76_1)(a1)
; RV64I-NEXT: slli a0, a0, 4 ; RV64I-NEXT: slli a0, a0, 4
; RV64I-NEXT: or a0, a2, a0 ; RV64I-NEXT: or a0, a2, a0
; RV64I-NEXT: srli a2, a0, 2 ; RV64I-NEXT: srli a2, a0, 2
; RV64I-NEXT: and a2, a2, a1 ; RV64I-NEXT: and a2, a2, a1
; RV64I-NEXT: and a0, a0, a1 ; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: lui a1, %hi(.LCPI72_2) ; RV64I-NEXT: lui a1, %hi(.LCPI76_2)
; RV64I-NEXT: ld a1, %lo(.LCPI72_2)(a1) ; RV64I-NEXT: ld a1, %lo(.LCPI76_2)(a1)
; RV64I-NEXT: slli a0, a0, 2 ; RV64I-NEXT: slli a0, a0, 2
; RV64I-NEXT: or a0, a2, a0 ; RV64I-NEXT: or a0, a2, a0
; RV64I-NEXT: srli a2, a0, 1 ; RV64I-NEXT: srli a2, a0, 1
; RV64I-NEXT: and a2, a2, a1 ; RV64I-NEXT: and a2, a2, a1
; RV64I-NEXT: and a0, a0, a1 ; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: slli a0, a0, 1 ; RV64I-NEXT: slli a0, a0, 1
; RV64I-NEXT: or a0, a2, a0 ; RV64I-NEXT: or a0, a2, a0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
Show All 37 Lines; RV64ZBP-NEXT: ret
%and2 = and i32 %shr, 572662306 %and2 = and i32 %shr, 572662306
%or3 = or i32 %or, %and2 %or3 = or i32 %or, %and2
ret i32 %or3 ret i32 %or3
} }
define i64 @shfl1_i64(i64 %a, i64 %b) nounwind { define i64 @shfl1_i64(i64 %a, i64 %b) nounwind {
; RV64I-LABEL: shfl1_i64: ; RV64I-LABEL: shfl1_i64:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, %hi(.LCPI74_1) ; RV64I-NEXT: lui a1, %hi(.LCPI78_1)
; RV64I-NEXT: ld a1, %lo(.LCPI74_1)(a1) ; RV64I-NEXT: ld a1, %lo(.LCPI78_1)(a1)
; RV64I-NEXT: lui a2, %hi(.LCPI74_0) ; RV64I-NEXT: lui a2, %hi(.LCPI78_0)
; RV64I-NEXT: ld a2, %lo(.LCPI74_0)(a2) ; RV64I-NEXT: ld a2, %lo(.LCPI78_0)(a2)
; RV64I-NEXT: slli a3, a0, 1 ; RV64I-NEXT: slli a3, a0, 1
; RV64I-NEXT: and a1, a3, a1 ; RV64I-NEXT: and a1, a3, a1
; RV64I-NEXT: lui a3, %hi(.LCPI74_2) ; RV64I-NEXT: lui a3, %hi(.LCPI78_2)
; RV64I-NEXT: ld a3, %lo(.LCPI74_2)(a3) ; RV64I-NEXT: ld a3, %lo(.LCPI78_2)(a3)
; RV64I-NEXT: and a2, a0, a2 ; RV64I-NEXT: and a2, a0, a2
; RV64I-NEXT: or a1, a2, a1 ; RV64I-NEXT: or a1, a2, a1
; RV64I-NEXT: srli a0, a0, 1 ; RV64I-NEXT: srli a0, a0, 1
; RV64I-NEXT: and a0, a0, a3 ; RV64I-NEXT: and a0, a0, a3
; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64ZBP-LABEL: shfl1_i64: ; RV64ZBP-LABEL: shfl1_i64:
Show All 40 Lines; RV64ZBP-NEXT: ret
%and2 = and i32 %shr, 202116108 %and2 = and i32 %shr, 202116108
%or3 = or i32 %and2, %or %or3 = or i32 %and2, %or
ret i32 %or3 ret i32 %or3
} }
define i64 @shfl2_i64(i64 %a, i64 %b) nounwind { define i64 @shfl2_i64(i64 %a, i64 %b) nounwind {
; RV64I-LABEL: shfl2_i64: ; RV64I-LABEL: shfl2_i64:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, %hi(.LCPI76_1) ; RV64I-NEXT: lui a1, %hi(.LCPI80_1)
; RV64I-NEXT: ld a1, %lo(.LCPI76_1)(a1) ; RV64I-NEXT: ld a1, %lo(.LCPI80_1)(a1)
; RV64I-NEXT: lui a2, %hi(.LCPI76_0) ; RV64I-NEXT: lui a2, %hi(.LCPI80_0)
; RV64I-NEXT: ld a2, %lo(.LCPI76_0)(a2) ; RV64I-NEXT: ld a2, %lo(.LCPI80_0)(a2)
; RV64I-NEXT: slli a3, a0, 2 ; RV64I-NEXT: slli a3, a0, 2
; RV64I-NEXT: and a1, a3, a1 ; RV64I-NEXT: and a1, a3, a1
; RV64I-NEXT: lui a3, %hi(.LCPI76_2) ; RV64I-NEXT: lui a3, %hi(.LCPI80_2)
; RV64I-NEXT: ld a3, %lo(.LCPI76_2)(a3) ; RV64I-NEXT: ld a3, %lo(.LCPI80_2)(a3)
; RV64I-NEXT: and a2, a0, a2 ; RV64I-NEXT: and a2, a0, a2
; RV64I-NEXT: or a1, a2, a1 ; RV64I-NEXT: or a1, a2, a1
; RV64I-NEXT: srli a0, a0, 2 ; RV64I-NEXT: srli a0, a0, 2
; RV64I-NEXT: and a0, a0, a3 ; RV64I-NEXT: and a0, a0, a3
; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64ZBP-LABEL: shfl2_i64: ; RV64ZBP-LABEL: shfl2_i64:
Show All 40 Lines; RV64ZBP-NEXT: ret
%or = or i32 %and2, %and %or = or i32 %and2, %and
%or3 = or i32 %or, %and1 %or3 = or i32 %or, %and1
ret i32 %or3 ret i32 %or3
} }
define i64 @shfl4_i64(i64 %a, i64 %b) nounwind { define i64 @shfl4_i64(i64 %a, i64 %b) nounwind {
; RV64I-LABEL: shfl4_i64: ; RV64I-LABEL: shfl4_i64:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, %hi(.LCPI78_0) ; RV64I-NEXT: lui a1, %hi(.LCPI82_0)
; RV64I-NEXT: ld a1, %lo(.LCPI78_0)(a1) ; RV64I-NEXT: ld a1, %lo(.LCPI82_0)(a1)
; RV64I-NEXT: lui a2, %hi(.LCPI78_1) ; RV64I-NEXT: lui a2, %hi(.LCPI82_1)
; RV64I-NEXT: ld a2, %lo(.LCPI78_1)(a2) ; RV64I-NEXT: ld a2, %lo(.LCPI82_1)(a2)
; RV64I-NEXT: slli a3, a0, 4 ; RV64I-NEXT: slli a3, a0, 4
; RV64I-NEXT: lui a4, %hi(.LCPI78_2) ; RV64I-NEXT: lui a4, %hi(.LCPI82_2)
; RV64I-NEXT: ld a4, %lo(.LCPI78_2)(a4) ; RV64I-NEXT: ld a4, %lo(.LCPI82_2)(a4)
; RV64I-NEXT: and a2, a3, a2 ; RV64I-NEXT: and a2, a3, a2
; RV64I-NEXT: and a1, a0, a1 ; RV64I-NEXT: and a1, a0, a1
; RV64I-NEXT: srli a0, a0, 4 ; RV64I-NEXT: srli a0, a0, 4
; RV64I-NEXT: and a0, a0, a4 ; RV64I-NEXT: and a0, a0, a4
; RV64I-NEXT: or a0, a2, a0 ; RV64I-NEXT: or a0, a2, a0
; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
▲ Show 20 Lines • Show All 185 Lines • Show Last 20 Lines