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Differential D120304

[RISCV] Supplement more tests for GREVI aliaes in Zbp extension
ClosedPublic

Authored by Jimerlife on Feb 21 2022, 11:42 PM.

Details

Reviewers
craig.topper
asb
benshi001
frasercrmck
Commits
rG7abcb7ba87b1: [RISCV] Supplement more tests for GREVI aliaes in Zbp extension
Summary

Supplement tests for some aliaes of grevi.
RV32:
add rev4.h/rev2.h in rv32zbp.ll
add rev/rev2/rev4/rev8/rev16 in rv32zbp-intrinsic.ll

RV64:
add rev4.h/rev2.h in rv64zbp.ll
add rev.h/rev/rev2/rev4/rev8/rev16/rev32/rev.w/rev2.w/rev4.w/rev8.w/rev16.w in rv64zbp-intrinsic.ll

Diff Detail

Event Timeline

Jimerlife created this revision.Feb 21 2022, 11:42 PM
Herald added subscribers: VincentWu, luke957, achieveartificialintelligence and 24 others. · View Herald TranscriptFeb 21 2022, 11:42 PM
Jimerlife requested review of this revision.Feb 21 2022, 11:42 PM
Herald added subscribers: llvm-commits, • pcwang-thead, eopXD and 2 others. · View Herald TranscriptFeb 21 2022, 11:42 PM
Harbormaster completed remote builds in B150816: Diff 410459.Feb 22 2022, 12:23 AM
craig.topper accepted this revision.Feb 22 2022, 10:05 PM

LGTM

This revision is now accepted and ready to land.Feb 22 2022, 10:05 PM
This revision was landed with ongoing or failed builds.Feb 22 2022, 10:17 PM
Closed by commit rG7abcb7ba87b1: [RISCV] Supplement more tests for GREVI aliaes in Zbp extension (authored by Jimerlife, committed by benshi001). · Explain Why
This revision was automatically updated to reflect the committed changes.
benshi001 added a commit: rG7abcb7ba87b1: [RISCV] Supplement more tests for GREVI aliaes in Zbp extension.

Revision Contents

PathSize
llvm/
test/
CodeGen/
RISCV/
45 lines
94 lines
108 lines
296 lines

Diff 410711

llvm/test/CodeGen/RISCV/rv32zbp-intrinsic.ll

Show All 26 Lines
; RV32ZBP-LABEL: grevi32: ; RV32ZBP-LABEL: grevi32:
; RV32ZBP: # %bb.0: ; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: grevi a0, a0, 13 ; RV32ZBP-NEXT: grevi a0, a0, 13
; RV32ZBP-NEXT: ret ; RV32ZBP-NEXT: ret
%tmp = call i32 @llvm.riscv.grev.i32(i32 %a, i32 13) %tmp = call i32 @llvm.riscv.grev.i32(i32 %a, i32 13)
ret i32 %tmp ret i32 %tmp
} }
define i32 @revi32(i32 %a) nounwind {
; RV32ZBP-LABEL: revi32:
; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: rev a0, a0
; RV32ZBP-NEXT: ret
%tmp = call i32 @llvm.riscv.grev.i32(i32 %a, i32 31)
ret i32 %tmp
}
define i32 @rev2i32(i32 %a) nounwind {
; RV32ZBP-LABEL: rev2i32:
; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: rev2 a0, a0
; RV32ZBP-NEXT: ret
%tmp = call i32 @llvm.riscv.grev.i32(i32 %a, i32 30)
ret i32 %tmp
}
define i32 @rev4i32(i32 %a) nounwind {
; RV32ZBP-LABEL: rev4i32:
; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: rev4 a0, a0
; RV32ZBP-NEXT: ret
%tmp = call i32 @llvm.riscv.grev.i32(i32 %a, i32 28)
ret i32 %tmp
}
define i32 @rev8i32(i32 %a) nounwind {
; RV32ZBP-LABEL: rev8i32:
; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: rev8 a0, a0
; RV32ZBP-NEXT: ret
%tmp = call i32 @llvm.riscv.grev.i32(i32 %a, i32 24)
ret i32 %tmp
}
define i32 @rev16i32(i32 %a) nounwind {
; RV32ZBP-LABEL: rev16i32:
; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: rev16 a0, a0
; RV32ZBP-NEXT: ret
%tmp = call i32 @llvm.riscv.grev.i32(i32 %a, i32 16)
ret i32 %tmp
}
declare i32 @llvm.riscv.gorc.i32(i32 %a, i32 %b) declare i32 @llvm.riscv.gorc.i32(i32 %a, i32 %b)
define i32 @gorc32(i32 %a, i32 %b) nounwind { define i32 @gorc32(i32 %a, i32 %b) nounwind {
; RV32ZBP-LABEL: gorc32: ; RV32ZBP-LABEL: gorc32:
; RV32ZBP: # %bb.0: ; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: gorc a0, a0, a1 ; RV32ZBP-NEXT: gorc a0, a0, a1
; RV32ZBP-NEXT: ret ; RV32ZBP-NEXT: ret
%tmp = call i32 @llvm.riscv.gorc.i32(i32 %a, i32 %b) %tmp = call i32 @llvm.riscv.gorc.i32(i32 %a, i32 %b)
▲ Show 20 Lines • Show All 294 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rv32zbp.ll

Show First 20 Lines • Show All 1,601 Lines • ▼ Show 20 Lines; RV32ZBP-NEXT: ret
%and = shl i32 %a, 8 %and = shl i32 %a, 8
%shl = and i32 %and, -16711936 %shl = and i32 %and, -16711936
%and1 = lshr i32 %a, 8 %and1 = lshr i32 %a, 8
%shr = and i32 %and1, 16711935 %shr = and i32 %and1, 16711935
%or = or i32 %shl, %shr %or = or i32 %shl, %shr
ret i32 %or ret i32 %or
} }
define i32 @grev12_i32(i32 %a) nounwind {
; RV32I-LABEL: grev12_i32:
; RV32I: # %bb.0:
; RV32I-NEXT: slli a1, a0, 4
; RV32I-NEXT: lui a2, 986895
; RV32I-NEXT: addi a2, a2, 240
; RV32I-NEXT: and a1, a1, a2
; RV32I-NEXT: srli a0, a0, 4
; RV32I-NEXT: lui a2, 61681
; RV32I-NEXT: addi a2, a2, -241
; RV32I-NEXT: and a0, a0, a2
; RV32I-NEXT: or a0, a1, a0
; RV32I-NEXT: slli a1, a0, 8
; RV32I-NEXT: lui a2, 1044496
; RV32I-NEXT: addi a2, a2, -256
; RV32I-NEXT: and a1, a1, a2
; RV32I-NEXT: srli a0, a0, 8
; RV32I-NEXT: lui a2, 4080
; RV32I-NEXT: addi a2, a2, 255
; RV32I-NEXT: and a0, a0, a2
; RV32I-NEXT: or a0, a1, a0
; RV32I-NEXT: ret
;
; RV32ZBP-LABEL: grev12_i32:
; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: rev4.h a0, a0
; RV32ZBP-NEXT: ret
%and1 = shl i32 %a, 4
%shl1 = and i32 %and1, -252645136
%and1b = lshr i32 %a, 4
%shr1 = and i32 %and1b, 252645135
%or1 = or i32 %shl1, %shr1
%and2 = shl i32 %or1, 8
%shl2 = and i32 %and2, -16711936
%and2b = lshr i32 %or1, 8
%shr2 = and i32 %and2b, 16711935
%or2 = or i32 %shl2, %shr2
ret i32 %or2
}
define i32 @grev14_i32(i32 %a) nounwind {
; RV32I-LABEL: grev14_i32:
; RV32I: # %bb.0:
; RV32I-NEXT: slli a1, a0, 2
; RV32I-NEXT: lui a2, 838861
; RV32I-NEXT: addi a2, a2, -820
; RV32I-NEXT: and a1, a1, a2
; RV32I-NEXT: srli a0, a0, 2
; RV32I-NEXT: lui a2, 209715
; RV32I-NEXT: addi a2, a2, 819
; RV32I-NEXT: and a0, a0, a2
; RV32I-NEXT: or a0, a1, a0
; RV32I-NEXT: slli a1, a0, 4
; RV32I-NEXT: lui a2, 986895
; RV32I-NEXT: addi a2, a2, 240
; RV32I-NEXT: and a1, a1, a2
; RV32I-NEXT: srli a0, a0, 4
; RV32I-NEXT: lui a2, 61681
; RV32I-NEXT: addi a2, a2, -241
; RV32I-NEXT: and a0, a0, a2
; RV32I-NEXT: or a0, a1, a0
; RV32I-NEXT: slli a1, a0, 8
; RV32I-NEXT: lui a2, 1044496
; RV32I-NEXT: addi a2, a2, -256
; RV32I-NEXT: and a1, a1, a2
; RV32I-NEXT: srli a0, a0, 8
; RV32I-NEXT: lui a2, 4080
; RV32I-NEXT: addi a2, a2, 255
; RV32I-NEXT: and a0, a0, a2
; RV32I-NEXT: or a0, a1, a0
; RV32I-NEXT: ret
;
; RV32ZBP-LABEL: grev14_i32:
; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: rev2.h a0, a0
; RV32ZBP-NEXT: ret
%and1 = shl i32 %a, 2
%shl1 = and i32 %and1, -858993460
%and1b = lshr i32 %a, 2
%shr1 = and i32 %and1b, 858993459
%or1 = or i32 %shl1, %shr1
%and2 = shl i32 %or1, 4
%shl2 = and i32 %and2, -252645136
%and2b = lshr i32 %or1, 4
%shr2 = and i32 %and2b, 252645135
%or2 = or i32 %shl2, %shr2
%and3 = shl i32 %or2, 8
%shl3 = and i32 %and3, -16711936
%and3b = lshr i32 %or2, 8
%shr3 = and i32 %and3b, 16711935
%or3 = or i32 %shl3, %shr3
ret i32 %or3
}
define i64 @grev8_i64(i64 %a) nounwind { define i64 @grev8_i64(i64 %a) nounwind {
; RV32I-LABEL: grev8_i64: ; RV32I-LABEL: grev8_i64:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: slli a2, a0, 8 ; RV32I-NEXT: slli a2, a0, 8
; RV32I-NEXT: slli a3, a1, 8 ; RV32I-NEXT: slli a3, a1, 8
; RV32I-NEXT: lui a4, 1044496 ; RV32I-NEXT: lui a4, 1044496
; RV32I-NEXT: addi a4, a4, -256 ; RV32I-NEXT: addi a4, a4, -256
; RV32I-NEXT: and a3, a3, a4 ; RV32I-NEXT: and a3, a3, a4
▲ Show 20 Lines • Show All 1,464 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rv64zbp-intrinsic.ll

Show First 20 Lines • Show All 336 Lines • ▼ Show 20 Lines
; RV64ZBP-LABEL: grevi64: ; RV64ZBP-LABEL: grevi64:
; RV64ZBP: # %bb.0: ; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: grevi a0, a0, 13 ; RV64ZBP-NEXT: grevi a0, a0, 13
; RV64ZBP-NEXT: ret ; RV64ZBP-NEXT: ret
%tmp = call i64 @llvm.riscv.grev.i64(i64 %a, i64 13) %tmp = call i64 @llvm.riscv.grev.i64(i64 %a, i64 13)
ret i64 %tmp ret i64 %tmp
} }
define i64 @revhwi64(i64 %a) nounwind {
; RV64ZBP-LABEL: revhwi64:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: rev.h a0, a0
; RV64ZBP-NEXT: ret
%tmp = call i64 @llvm.riscv.grev.i64(i64 %a, i64 15)
ret i64 %tmp
}
define i64 @rev16wi64(i64 %a) nounwind {
; RV64ZBP-LABEL: rev16wi64:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: rev16.w a0, a0
; RV64ZBP-NEXT: ret
%tmp = call i64 @llvm.riscv.grev.i64(i64 %a, i64 16)
ret i64 %tmp
}
define i64 @rev8wi64(i64 %a) nounwind {
; RV64ZBP-LABEL: rev8wi64:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: rev8.w a0, a0
; RV64ZBP-NEXT: ret
%tmp = call i64 @llvm.riscv.grev.i64(i64 %a, i64 24)
ret i64 %tmp
}
define i64 @rev4wi64(i64 %a) nounwind {
; RV64ZBP-LABEL: rev4wi64:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: rev4.w a0, a0
; RV64ZBP-NEXT: ret
%tmp = call i64 @llvm.riscv.grev.i64(i64 %a, i64 28)
ret i64 %tmp
}
define i64 @rev2wi64(i64 %a) nounwind {
; RV64ZBP-LABEL: rev2wi64:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: rev2.w a0, a0
; RV64ZBP-NEXT: ret
%tmp = call i64 @llvm.riscv.grev.i64(i64 %a, i64 30)
ret i64 %tmp
}
define i64 @revwi64(i64 %a) nounwind {
; RV64ZBP-LABEL: revwi64:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: rev.w a0, a0
; RV64ZBP-NEXT: ret
%tmp = call i64 @llvm.riscv.grev.i64(i64 %a, i64 31)
ret i64 %tmp
}
define i64 @rev32i64(i64 %a) nounwind {
; RV64ZBP-LABEL: rev32i64:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: rev32 a0, a0
; RV64ZBP-NEXT: ret
%tmp = call i64 @llvm.riscv.grev.i64(i64 %a, i64 32)
ret i64 %tmp
}
define i64 @rev16i64(i64 %a) nounwind {
; RV64ZBP-LABEL: rev16i64:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: rev16 a0, a0
; RV64ZBP-NEXT: ret
%tmp = call i64 @llvm.riscv.grev.i64(i64 %a, i64 48)
ret i64 %tmp
}
define i64 @rev8i64(i64 %a) nounwind {
; RV64ZBP-LABEL: rev8i64:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: rev8 a0, a0
; RV64ZBP-NEXT: ret
%tmp = call i64 @llvm.riscv.grev.i64(i64 %a, i64 56)
ret i64 %tmp
}
define i64 @rev4i64(i64 %a) nounwind {
; RV64ZBP-LABEL: rev4i64:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: rev4 a0, a0
; RV64ZBP-NEXT: ret
%tmp = call i64 @llvm.riscv.grev.i64(i64 %a, i64 60)
ret i64 %tmp
}
define i64 @rev2i64(i64 %a) nounwind {
; RV64ZBP-LABEL: rev2i64:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: rev2 a0, a0
; RV64ZBP-NEXT: ret
%tmp = call i64 @llvm.riscv.grev.i64(i64 %a, i64 62)
ret i64 %tmp
}
define i64 @revi64(i64 %a) nounwind {
; RV64ZBP-LABEL: revi64:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: rev a0, a0
; RV64ZBP-NEXT: ret
%tmp = call i64 @llvm.riscv.grev.i64(i64 %a, i64 63)
ret i64 %tmp
}
declare i64 @llvm.riscv.gorc.i64(i64 %a, i64 %b) declare i64 @llvm.riscv.gorc.i64(i64 %a, i64 %b)
define i64 @gorc64(i64 %a, i64 %b) nounwind { define i64 @gorc64(i64 %a, i64 %b) nounwind {
; RV64ZBP-LABEL: gorc64: ; RV64ZBP-LABEL: gorc64:
; RV64ZBP: # %bb.0: ; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: gorc a0, a0, a1 ; RV64ZBP-NEXT: gorc a0, a0, a1
; RV64ZBP-NEXT: ret ; RV64ZBP-NEXT: ret
%tmp = call i64 @llvm.riscv.gorc.i64(i64 %a, i64 %b) %tmp = call i64 @llvm.riscv.gorc.i64(i64 %a, i64 %b)
▲ Show 20 Lines • Show All 361 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rv64zbp.ll

Show First 20 Lines • Show All 1,504 Lines • ▼ Show 20 Lines; RV64ZBP-NEXT: ret
%and = shl i64 %a, 8 %and = shl i64 %a, 8
%shl = and i64 %and, -71777214294589696 %shl = and i64 %and, -71777214294589696
%and1 = lshr i64 %a, 8 %and1 = lshr i64 %a, 8
%shr = and i64 %and1, 71777214294589695 %shr = and i64 %and1, 71777214294589695
%or = or i64 %shl, %shr %or = or i64 %shl, %shr
ret i64 %or ret i64 %or
} }
define signext i32 @grev12_i32(i32 signext %a) nounwind {
; RV64I-LABEL: grev12_i32:
; RV64I: # %bb.0:
; RV64I-NEXT: slliw a1, a0, 4
; RV64I-NEXT: lui a2, 986895
; RV64I-NEXT: addiw a2, a2, 240
; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: srli a0, a0, 4
; RV64I-NEXT: lui a2, 61681
; RV64I-NEXT: addiw a2, a2, -241
; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: slliw a1, a0, 8
; RV64I-NEXT: lui a2, 1044496
; RV64I-NEXT: addiw a2, a2, -256
; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: srli a0, a0, 8
; RV64I-NEXT: lui a2, 4080
; RV64I-NEXT: addiw a2, a2, 255
; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret
;
; RV64ZBP-LABEL: grev12_i32:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: greviw a0, a0, 12
; RV64ZBP-NEXT: ret
%and1 = shl i32 %a, 4
%shl1 = and i32 %and1, -252645136
%and1b = lshr i32 %a, 4
%shr1 = and i32 %and1b, 252645135
%or1 = or i32 %shl1, %shr1
%and2 = shl i32 %or1, 8
%shl2 = and i32 %and2, -16711936
%and2b = lshr i32 %or1, 8
%shr2 = and i32 %and2b, 16711935
%or2 = or i32 %shl2, %shr2
ret i32 %or2
}
define i64 @grev12_i64(i64 %a) nounwind {
; RV64I-LABEL: grev12_i64:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, %hi(.LCPI44_0)
; RV64I-NEXT: ld a1, %lo(.LCPI44_0)(a1)
; RV64I-NEXT: lui a2, %hi(.LCPI44_1)
; RV64I-NEXT: ld a2, %lo(.LCPI44_1)(a2)
; RV64I-NEXT: slli a3, a0, 4
; RV64I-NEXT: and a1, a3, a1
; RV64I-NEXT: srli a0, a0, 4
; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: lui a1, %hi(.LCPI44_2)
; RV64I-NEXT: ld a1, %lo(.LCPI44_2)(a1)
; RV64I-NEXT: lui a2, %hi(.LCPI44_3)
; RV64I-NEXT: ld a2, %lo(.LCPI44_3)(a2)
; RV64I-NEXT: slli a3, a0, 8
; RV64I-NEXT: and a1, a3, a1
; RV64I-NEXT: srli a0, a0, 8
; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret
;
; RV64ZBP-LABEL: grev12_i64:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: rev4.h a0, a0
; RV64ZBP-NEXT: ret
%and1 = shl i64 %a, 4
%shl1 = and i64 %and1, -1085102592571150096
%and1b = lshr i64 %a, 4
%shr1 = and i64 %and1b, 1085102592571150095
%or1 = or i64 %shl1, %shr1
%and2 = shl i64 %or1, 8
%shl2 = and i64 %and2, -71777214294589696
%and2b = lshr i64 %or1, 8
%shr2 = and i64 %and2b, 71777214294589695
%or2 = or i64 %shl2, %shr2
ret i64 %or2
}
define signext i32 @grev14_i32(i32 signext %a) nounwind {
; RV64I-LABEL: grev14_i32:
; RV64I: # %bb.0:
; RV64I-NEXT: slliw a1, a0, 2
; RV64I-NEXT: lui a2, 838861
; RV64I-NEXT: addiw a2, a2, -820
; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: srli a0, a0, 2
; RV64I-NEXT: lui a2, 209715
; RV64I-NEXT: addiw a2, a2, 819
; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: slliw a1, a0, 4
; RV64I-NEXT: lui a2, 986895
; RV64I-NEXT: addiw a2, a2, 240
; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: srli a0, a0, 4
; RV64I-NEXT: lui a2, 61681
; RV64I-NEXT: addiw a2, a2, -241
; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: slliw a1, a0, 8
; RV64I-NEXT: lui a2, 1044496
; RV64I-NEXT: addiw a2, a2, -256
; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: srli a0, a0, 8
; RV64I-NEXT: lui a2, 4080
; RV64I-NEXT: addiw a2, a2, 255
; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret
;
; RV64ZBP-LABEL: grev14_i32:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: greviw a0, a0, 14
; RV64ZBP-NEXT: ret
%and1 = shl i32 %a, 2
%shl1 = and i32 %and1, -858993460
%and1b = lshr i32 %a, 2
%shr1 = and i32 %and1b, 858993459
%or1 = or i32 %shl1, %shr1
%and2 = shl i32 %or1, 4
%shl2 = and i32 %and2, -252645136
%and2b = lshr i32 %or1, 4
%shr2 = and i32 %and2b, 252645135
%or2 = or i32 %shl2, %shr2
%and3 = shl i32 %or2, 8
%shl3 = and i32 %and3, -16711936
%and3b = lshr i32 %or2, 8
%shr3 = and i32 %and3b, 16711935
%or3 = or i32 %shl3, %shr3
ret i32 %or3
}
define i64 @grev14_i64(i64 %a) nounwind {
; RV64I-LABEL: grev14_i64:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, %hi(.LCPI46_0)
; RV64I-NEXT: ld a1, %lo(.LCPI46_0)(a1)
; RV64I-NEXT: lui a2, %hi(.LCPI46_1)
; RV64I-NEXT: ld a2, %lo(.LCPI46_1)(a2)
; RV64I-NEXT: slli a3, a0, 2
; RV64I-NEXT: and a1, a3, a1
; RV64I-NEXT: srli a0, a0, 2
; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: lui a1, %hi(.LCPI46_2)
; RV64I-NEXT: ld a1, %lo(.LCPI46_2)(a1)
; RV64I-NEXT: lui a2, %hi(.LCPI46_3)
; RV64I-NEXT: ld a2, %lo(.LCPI46_3)(a2)
; RV64I-NEXT: slli a3, a0, 4
; RV64I-NEXT: and a1, a3, a1
; RV64I-NEXT: srli a0, a0, 4
; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: lui a1, %hi(.LCPI46_4)
; RV64I-NEXT: ld a1, %lo(.LCPI46_4)(a1)
; RV64I-NEXT: lui a2, %hi(.LCPI46_5)
; RV64I-NEXT: ld a2, %lo(.LCPI46_5)(a2)
; RV64I-NEXT: slli a3, a0, 8
; RV64I-NEXT: and a1, a3, a1
; RV64I-NEXT: srli a0, a0, 8
; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret
;
; RV64ZBP-LABEL: grev14_i64:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: rev2.h a0, a0
; RV64ZBP-NEXT: ret
%and1 = shl i64 %a, 2
%shl1 = and i64 %and1, -3689348814741910324
%and1b = lshr i64 %a, 2
%shr1 = and i64 %and1b, 3689348814741910323
%or1 = or i64 %shl1, %shr1
%and2 = shl i64 %or1, 4
%shl2 = and i64 %and2, -1085102592571150096
%and2b = lshr i64 %or1, 4
%shr2 = and i64 %and2b, 1085102592571150095
%or2 = or i64 %shl2, %shr2
%and3 = shl i64 %or2, 8
%shl3 = and i64 %and3, -71777214294589696
%and3b = lshr i64 %or2, 8
%shr3 = and i64 %and3b, 71777214294589695
%or3 = or i64 %shl3, %shr3
ret i64 %or3
}
define signext i32 @grev16_i32(i32 signext %a) nounwind { define signext i32 @grev16_i32(i32 signext %a) nounwind {
; RV64I-LABEL: grev16_i32: ; RV64I-LABEL: grev16_i32:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: srliw a1, a0, 16 ; RV64I-NEXT: srliw a1, a0, 16
; RV64I-NEXT: slliw a0, a0, 16 ; RV64I-NEXT: slliw a0, a0, 16
; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
▲ Show 20 Lines • Show All 127 Lines • ▼ Show 20 Lines; RV64ZBP-NEXT: ret
%shr1 = and i32 %and1b, 1431655765 %shr1 = and i32 %and1b, 1431655765
%or1 = or i32 %shl1, %shr1 %or1 = or i32 %shl1, %shr1
ret i32 %or1 ret i32 %or1
} }
define i64 @grev3b_i64(i64 %a) nounwind { define i64 @grev3b_i64(i64 %a) nounwind {
; RV64I-LABEL: grev3b_i64: ; RV64I-LABEL: grev3b_i64:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, %hi(.LCPI49_0) ; RV64I-NEXT: lui a1, %hi(.LCPI53_0)
; RV64I-NEXT: ld a1, %lo(.LCPI49_0)(a1) ; RV64I-NEXT: ld a1, %lo(.LCPI53_0)(a1)
; RV64I-NEXT: lui a2, %hi(.LCPI49_1) ; RV64I-NEXT: lui a2, %hi(.LCPI53_1)
; RV64I-NEXT: ld a2, %lo(.LCPI49_1)(a2) ; RV64I-NEXT: ld a2, %lo(.LCPI53_1)(a2)
; RV64I-NEXT: slli a3, a0, 2 ; RV64I-NEXT: slli a3, a0, 2
; RV64I-NEXT: and a1, a3, a1 ; RV64I-NEXT: and a1, a3, a1
; RV64I-NEXT: srli a0, a0, 2 ; RV64I-NEXT: srli a0, a0, 2
; RV64I-NEXT: and a0, a0, a2 ; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: lui a1, %hi(.LCPI49_2) ; RV64I-NEXT: lui a1, %hi(.LCPI53_2)
; RV64I-NEXT: ld a1, %lo(.LCPI49_2)(a1) ; RV64I-NEXT: ld a1, %lo(.LCPI53_2)(a1)
; RV64I-NEXT: lui a2, %hi(.LCPI49_3) ; RV64I-NEXT: lui a2, %hi(.LCPI53_3)
; RV64I-NEXT: ld a2, %lo(.LCPI49_3)(a2) ; RV64I-NEXT: ld a2, %lo(.LCPI53_3)(a2)
; RV64I-NEXT: slli a3, a0, 1 ; RV64I-NEXT: slli a3, a0, 1
; RV64I-NEXT: and a1, a3, a1 ; RV64I-NEXT: and a1, a3, a1
; RV64I-NEXT: srli a0, a0, 1 ; RV64I-NEXT: srli a0, a0, 1
; RV64I-NEXT: and a0, a0, a2 ; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64ZBP-LABEL: grev3b_i64: ; RV64ZBP-LABEL: grev3b_i64:
▲ Show 20 Lines • Show All 63 Lines • ▼ Show 20 Lines; RV64ZBP-NEXT: ret
%or3 = or i32 %shl3, %shr3 %or3 = or i32 %shl3, %shr3
ret i32 %or3 ret i32 %or3
} }
; grev1, grev2, grev1 -> grev2 ; grev1, grev2, grev1 -> grev2
define i64 @grev2b_i64(i64 %a) nounwind { define i64 @grev2b_i64(i64 %a) nounwind {
; RV64I-LABEL: grev2b_i64: ; RV64I-LABEL: grev2b_i64:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, %hi(.LCPI51_0) ; RV64I-NEXT: lui a1, %hi(.LCPI55_0)
; RV64I-NEXT: ld a1, %lo(.LCPI51_0)(a1) ; RV64I-NEXT: ld a1, %lo(.LCPI55_0)(a1)
; RV64I-NEXT: lui a2, %hi(.LCPI51_1) ; RV64I-NEXT: lui a2, %hi(.LCPI55_1)
; RV64I-NEXT: ld a2, %lo(.LCPI51_1)(a2) ; RV64I-NEXT: ld a2, %lo(.LCPI55_1)(a2)
; RV64I-NEXT: slli a3, a0, 1 ; RV64I-NEXT: slli a3, a0, 1
; RV64I-NEXT: and a3, a3, a1 ; RV64I-NEXT: and a3, a3, a1
; RV64I-NEXT: srli a0, a0, 1 ; RV64I-NEXT: srli a0, a0, 1
; RV64I-NEXT: and a0, a0, a2 ; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: or a0, a3, a0 ; RV64I-NEXT: or a0, a3, a0
; RV64I-NEXT: lui a3, %hi(.LCPI51_2) ; RV64I-NEXT: lui a3, %hi(.LCPI55_2)
; RV64I-NEXT: ld a3, %lo(.LCPI51_2)(a3) ; RV64I-NEXT: ld a3, %lo(.LCPI55_2)(a3)
; RV64I-NEXT: lui a4, %hi(.LCPI51_3) ; RV64I-NEXT: lui a4, %hi(.LCPI55_3)
; RV64I-NEXT: ld a4, %lo(.LCPI51_3)(a4) ; RV64I-NEXT: ld a4, %lo(.LCPI55_3)(a4)
; RV64I-NEXT: slli a5, a0, 2 ; RV64I-NEXT: slli a5, a0, 2
; RV64I-NEXT: and a3, a5, a3 ; RV64I-NEXT: and a3, a5, a3
; RV64I-NEXT: srli a0, a0, 2 ; RV64I-NEXT: srli a0, a0, 2
; RV64I-NEXT: and a0, a0, a4 ; RV64I-NEXT: and a0, a0, a4
; RV64I-NEXT: or a0, a3, a0 ; RV64I-NEXT: or a0, a3, a0
; RV64I-NEXT: slli a3, a0, 1 ; RV64I-NEXT: slli a3, a0, 1
; RV64I-NEXT: and a1, a3, a1 ; RV64I-NEXT: and a1, a3, a1
; RV64I-NEXT: srli a0, a0, 1 ; RV64I-NEXT: srli a0, a0, 1
▲ Show 20 Lines • Show All 82 Lines • ▼ Show 20 Lines; RV64ZBP-NEXT: ret
%or4 = or i32 %shl4, %shr4 %or4 = or i32 %shl4, %shr4
ret i32 %or4 ret i32 %or4
} }
; grev1, grev2, grev1, grev2 -> identity ; grev1, grev2, grev1, grev2 -> identity
define i64 @grev0_i64(i64 %a) nounwind { define i64 @grev0_i64(i64 %a) nounwind {
; RV64I-LABEL: grev0_i64: ; RV64I-LABEL: grev0_i64:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, %hi(.LCPI53_0) ; RV64I-NEXT: lui a1, %hi(.LCPI57_0)
; RV64I-NEXT: ld a1, %lo(.LCPI53_0)(a1) ; RV64I-NEXT: ld a1, %lo(.LCPI57_0)(a1)
; RV64I-NEXT: lui a2, %hi(.LCPI53_1) ; RV64I-NEXT: lui a2, %hi(.LCPI57_1)
; RV64I-NEXT: ld a2, %lo(.LCPI53_1)(a2) ; RV64I-NEXT: ld a2, %lo(.LCPI57_1)(a2)
; RV64I-NEXT: slli a3, a0, 1 ; RV64I-NEXT: slli a3, a0, 1
; RV64I-NEXT: and a3, a3, a1 ; RV64I-NEXT: and a3, a3, a1
; RV64I-NEXT: srli a0, a0, 1 ; RV64I-NEXT: srli a0, a0, 1
; RV64I-NEXT: and a0, a0, a2 ; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: or a0, a3, a0 ; RV64I-NEXT: or a0, a3, a0
; RV64I-NEXT: lui a3, %hi(.LCPI53_2) ; RV64I-NEXT: lui a3, %hi(.LCPI57_2)
; RV64I-NEXT: ld a3, %lo(.LCPI53_2)(a3) ; RV64I-NEXT: ld a3, %lo(.LCPI57_2)(a3)
; RV64I-NEXT: lui a4, %hi(.LCPI53_3) ; RV64I-NEXT: lui a4, %hi(.LCPI57_3)
; RV64I-NEXT: ld a4, %lo(.LCPI53_3)(a4) ; RV64I-NEXT: ld a4, %lo(.LCPI57_3)(a4)
; RV64I-NEXT: slli a5, a0, 2 ; RV64I-NEXT: slli a5, a0, 2
; RV64I-NEXT: and a5, a5, a3 ; RV64I-NEXT: and a5, a5, a3
; RV64I-NEXT: srli a0, a0, 2 ; RV64I-NEXT: srli a0, a0, 2
; RV64I-NEXT: and a0, a0, a4 ; RV64I-NEXT: and a0, a0, a4
; RV64I-NEXT: or a0, a5, a0 ; RV64I-NEXT: or a0, a5, a0
; RV64I-NEXT: slli a5, a0, 1 ; RV64I-NEXT: slli a5, a0, 1
; RV64I-NEXT: and a1, a5, a1 ; RV64I-NEXT: and a1, a5, a1
; RV64I-NEXT: srli a0, a0, 1 ; RV64I-NEXT: srli a0, a0, 1
▲ Show 20 Lines • Show All 378 Lines • ▼ Show 20 Lines
; RV64I-NEXT: srliw a4, a0, 24 ; RV64I-NEXT: srliw a4, a0, 24
; RV64I-NEXT: slli a4, a4, 32 ; RV64I-NEXT: slli a4, a4, 32
; RV64I-NEXT: or a2, a2, a4 ; RV64I-NEXT: or a2, a2, a4
; RV64I-NEXT: slli a4, a0, 40 ; RV64I-NEXT: slli a4, a0, 40
; RV64I-NEXT: slli a3, a3, 48 ; RV64I-NEXT: slli a3, a3, 48
; RV64I-NEXT: and a3, a4, a3 ; RV64I-NEXT: and a3, a4, a3
; RV64I-NEXT: slli a0, a0, 56 ; RV64I-NEXT: slli a0, a0, 56
; RV64I-NEXT: or a0, a0, a3 ; RV64I-NEXT: or a0, a0, a3
; RV64I-NEXT: lui a3, %hi(.LCPI64_0) ; RV64I-NEXT: lui a3, %hi(.LCPI68_0)
; RV64I-NEXT: ld a3, %lo(.LCPI64_0)(a3) ; RV64I-NEXT: ld a3, %lo(.LCPI68_0)(a3)
; RV64I-NEXT: or a0, a0, a2 ; RV64I-NEXT: or a0, a0, a2
; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: srli a1, a0, 4 ; RV64I-NEXT: srli a1, a0, 4
; RV64I-NEXT: and a1, a1, a3 ; RV64I-NEXT: and a1, a1, a3
; RV64I-NEXT: and a0, a0, a3 ; RV64I-NEXT: and a0, a0, a3
; RV64I-NEXT: lui a2, %hi(.LCPI64_1) ; RV64I-NEXT: lui a2, %hi(.LCPI68_1)
; RV64I-NEXT: ld a2, %lo(.LCPI64_1)(a2) ; RV64I-NEXT: ld a2, %lo(.LCPI68_1)(a2)
; RV64I-NEXT: slli a0, a0, 4 ; RV64I-NEXT: slli a0, a0, 4
; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: srli a1, a0, 2 ; RV64I-NEXT: srli a1, a0, 2
; RV64I-NEXT: and a1, a1, a2 ; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: and a0, a0, a2 ; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: lui a2, %hi(.LCPI64_2) ; RV64I-NEXT: lui a2, %hi(.LCPI68_2)
; RV64I-NEXT: ld a2, %lo(.LCPI64_2)(a2) ; RV64I-NEXT: ld a2, %lo(.LCPI68_2)(a2)
; RV64I-NEXT: slli a0, a0, 2 ; RV64I-NEXT: slli a0, a0, 2
; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: srli a1, a0, 1 ; RV64I-NEXT: srli a1, a0, 1
; RV64I-NEXT: and a1, a1, a2 ; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: and a0, a0, a2 ; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: slli a0, a0, 1 ; RV64I-NEXT: slli a0, a0, 1
; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
▲ Show 20 Lines • Show All 91 Lines • ▼ Show 20 Lines; RV64ZBP-NEXT: ret
%1 = call i32 @llvm.bitreverse.i32(i32 %a) %1 = call i32 @llvm.bitreverse.i32(i32 %a)
%2 = call i32 @llvm.bswap.i32(i32 %1) %2 = call i32 @llvm.bswap.i32(i32 %1)
ret i32 %2 ret i32 %2
} }
define i64 @bitreverse_bswap_i64(i64 %a) { define i64 @bitreverse_bswap_i64(i64 %a) {
; RV64I-LABEL: bitreverse_bswap_i64: ; RV64I-LABEL: bitreverse_bswap_i64:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, %hi(.LCPI68_0) ; RV64I-NEXT: lui a1, %hi(.LCPI72_0)
; RV64I-NEXT: ld a1, %lo(.LCPI68_0)(a1) ; RV64I-NEXT: ld a1, %lo(.LCPI72_0)(a1)
; RV64I-NEXT: srli a2, a0, 4 ; RV64I-NEXT: srli a2, a0, 4
; RV64I-NEXT: and a2, a2, a1 ; RV64I-NEXT: and a2, a2, a1
; RV64I-NEXT: and a0, a0, a1 ; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: lui a1, %hi(.LCPI68_1) ; RV64I-NEXT: lui a1, %hi(.LCPI72_1)
; RV64I-NEXT: ld a1, %lo(.LCPI68_1)(a1) ; RV64I-NEXT: ld a1, %lo(.LCPI72_1)(a1)
; RV64I-NEXT: slli a0, a0, 4 ; RV64I-NEXT: slli a0, a0, 4
; RV64I-NEXT: or a0, a2, a0 ; RV64I-NEXT: or a0, a2, a0
; RV64I-NEXT: srli a2, a0, 2 ; RV64I-NEXT: srli a2, a0, 2
; RV64I-NEXT: and a2, a2, a1 ; RV64I-NEXT: and a2, a2, a1
; RV64I-NEXT: and a0, a0, a1 ; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: lui a1, %hi(.LCPI68_2) ; RV64I-NEXT: lui a1, %hi(.LCPI72_2)
; RV64I-NEXT: ld a1, %lo(.LCPI68_2)(a1) ; RV64I-NEXT: ld a1, %lo(.LCPI72_2)(a1)
; RV64I-NEXT: slli a0, a0, 2 ; RV64I-NEXT: slli a0, a0, 2
; RV64I-NEXT: or a0, a2, a0 ; RV64I-NEXT: or a0, a2, a0
; RV64I-NEXT: srli a2, a0, 1 ; RV64I-NEXT: srli a2, a0, 1
; RV64I-NEXT: and a2, a2, a1 ; RV64I-NEXT: and a2, a2, a1
; RV64I-NEXT: and a0, a0, a1 ; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: slli a0, a0, 1 ; RV64I-NEXT: slli a0, a0, 1
; RV64I-NEXT: or a0, a2, a0 ; RV64I-NEXT: or a0, a2, a0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
Show All 37 Lines; RV64ZBP-NEXT: ret
%and2 = and i32 %shr, 572662306 %and2 = and i32 %shr, 572662306
%or3 = or i32 %or, %and2 %or3 = or i32 %or, %and2
ret i32 %or3 ret i32 %or3
} }
define i64 @shfl1_i64(i64 %a, i64 %b) nounwind { define i64 @shfl1_i64(i64 %a, i64 %b) nounwind {
; RV64I-LABEL: shfl1_i64: ; RV64I-LABEL: shfl1_i64:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, %hi(.LCPI70_1) ; RV64I-NEXT: lui a1, %hi(.LCPI74_1)
; RV64I-NEXT: ld a1, %lo(.LCPI70_1)(a1) ; RV64I-NEXT: ld a1, %lo(.LCPI74_1)(a1)
; RV64I-NEXT: lui a2, %hi(.LCPI70_0) ; RV64I-NEXT: lui a2, %hi(.LCPI74_0)
; RV64I-NEXT: ld a2, %lo(.LCPI70_0)(a2) ; RV64I-NEXT: ld a2, %lo(.LCPI74_0)(a2)
; RV64I-NEXT: slli a3, a0, 1 ; RV64I-NEXT: slli a3, a0, 1
; RV64I-NEXT: and a1, a3, a1 ; RV64I-NEXT: and a1, a3, a1
; RV64I-NEXT: lui a3, %hi(.LCPI70_2) ; RV64I-NEXT: lui a3, %hi(.LCPI74_2)
; RV64I-NEXT: ld a3, %lo(.LCPI70_2)(a3) ; RV64I-NEXT: ld a3, %lo(.LCPI74_2)(a3)
; RV64I-NEXT: and a2, a0, a2 ; RV64I-NEXT: and a2, a0, a2
; RV64I-NEXT: or a1, a2, a1 ; RV64I-NEXT: or a1, a2, a1
; RV64I-NEXT: srli a0, a0, 1 ; RV64I-NEXT: srli a0, a0, 1
; RV64I-NEXT: and a0, a0, a3 ; RV64I-NEXT: and a0, a0, a3
; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64ZBP-LABEL: shfl1_i64: ; RV64ZBP-LABEL: shfl1_i64:
Show All 40 Lines; RV64ZBP-NEXT: ret
%and2 = and i32 %shr, 202116108 %and2 = and i32 %shr, 202116108
%or3 = or i32 %and2, %or %or3 = or i32 %and2, %or
ret i32 %or3 ret i32 %or3
} }
define i64 @shfl2_i64(i64 %a, i64 %b) nounwind { define i64 @shfl2_i64(i64 %a, i64 %b) nounwind {
; RV64I-LABEL: shfl2_i64: ; RV64I-LABEL: shfl2_i64:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, %hi(.LCPI72_1) ; RV64I-NEXT: lui a1, %hi(.LCPI76_1)
; RV64I-NEXT: ld a1, %lo(.LCPI72_1)(a1) ; RV64I-NEXT: ld a1, %lo(.LCPI76_1)(a1)
; RV64I-NEXT: lui a2, %hi(.LCPI72_0) ; RV64I-NEXT: lui a2, %hi(.LCPI76_0)
; RV64I-NEXT: ld a2, %lo(.LCPI72_0)(a2) ; RV64I-NEXT: ld a2, %lo(.LCPI76_0)(a2)
; RV64I-NEXT: slli a3, a0, 2 ; RV64I-NEXT: slli a3, a0, 2
; RV64I-NEXT: and a1, a3, a1 ; RV64I-NEXT: and a1, a3, a1
; RV64I-NEXT: lui a3, %hi(.LCPI72_2) ; RV64I-NEXT: lui a3, %hi(.LCPI76_2)
; RV64I-NEXT: ld a3, %lo(.LCPI72_2)(a3) ; RV64I-NEXT: ld a3, %lo(.LCPI76_2)(a3)
; RV64I-NEXT: and a2, a0, a2 ; RV64I-NEXT: and a2, a0, a2
; RV64I-NEXT: or a1, a2, a1 ; RV64I-NEXT: or a1, a2, a1
; RV64I-NEXT: srli a0, a0, 2 ; RV64I-NEXT: srli a0, a0, 2
; RV64I-NEXT: and a0, a0, a3 ; RV64I-NEXT: and a0, a0, a3
; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64ZBP-LABEL: shfl2_i64: ; RV64ZBP-LABEL: shfl2_i64:
Show All 40 Lines; RV64ZBP-NEXT: ret
%or = or i32 %and2, %and %or = or i32 %and2, %and
%or3 = or i32 %or, %and1 %or3 = or i32 %or, %and1
ret i32 %or3 ret i32 %or3
} }
define i64 @shfl4_i64(i64 %a, i64 %b) nounwind { define i64 @shfl4_i64(i64 %a, i64 %b) nounwind {
; RV64I-LABEL: shfl4_i64: ; RV64I-LABEL: shfl4_i64:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, %hi(.LCPI74_0) ; RV64I-NEXT: lui a1, %hi(.LCPI78_0)
; RV64I-NEXT: ld a1, %lo(.LCPI74_0)(a1) ; RV64I-NEXT: ld a1, %lo(.LCPI78_0)(a1)
; RV64I-NEXT: lui a2, %hi(.LCPI74_1) ; RV64I-NEXT: lui a2, %hi(.LCPI78_1)
; RV64I-NEXT: ld a2, %lo(.LCPI74_1)(a2) ; RV64I-NEXT: ld a2, %lo(.LCPI78_1)(a2)
; RV64I-NEXT: slli a3, a0, 4 ; RV64I-NEXT: slli a3, a0, 4
; RV64I-NEXT: lui a4, %hi(.LCPI74_2) ; RV64I-NEXT: lui a4, %hi(.LCPI78_2)
; RV64I-NEXT: ld a4, %lo(.LCPI74_2)(a4) ; RV64I-NEXT: ld a4, %lo(.LCPI78_2)(a4)
; RV64I-NEXT: and a2, a3, a2 ; RV64I-NEXT: and a2, a3, a2
; RV64I-NEXT: and a1, a0, a1 ; RV64I-NEXT: and a1, a0, a1
; RV64I-NEXT: srli a0, a0, 4 ; RV64I-NEXT: srli a0, a0, 4
; RV64I-NEXT: and a0, a0, a4 ; RV64I-NEXT: and a0, a0, a4
; RV64I-NEXT: or a0, a2, a0 ; RV64I-NEXT: or a0, a2, a0
; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
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