[StableHashing] Hash vregs with multiple defs

[foad]

Summary

This allows stableHashValue to be used on Machine IR that is
not in SSA form.

[arsenm]

llvm/lib/CodeGen/MachineStableHash.cpp

69

If this only uses the opcode, won't it collide if you have multiple defs of the same register by the same opcode?

[foad]

llvm/lib/CodeGen/MachineStableHash.cpp

69

You'd get collisions anyway if different instructions with the same opcode define the register, but that was presumably by design, to make the hashing more stable somehow. I don't see how having multiple defs with the same opcode makes it any worse.

[arsenm]

LGTM. I guess this is only used for naming anyway right now

[kyulee]

Stable hash was designed to infer the machine instructions that are likely to be identical so that we can optimistically outline them.
I don't have a strong suggestion on how to interpret this in the presence of virtual registers (before RA).
But by taking all their defs into account, it appears the hash is likely to be more unique than before.
Is there any specific use case or reason to enhance this collision?

[foad]

In D120121#3332296, @kyulee wrote:

Is there any specific use case or reason to enhance this collision?

See D120124: I want to use this as a quick hash for MachineFunctions (either before or after SSA, before or after regalloc) to detect which FunctionPasses modify them.

[kyulee]

In D120121#3332320, @foad wrote:

In D120121#3332296, @kyulee wrote:

Is there any specific use case or reason to enhance this collision?

See D120124: I want to use this as a quick hash for MachineFunctions (either before or after SSA, before or after regalloc) to detect which FunctionPasses modify them.

Got it. Thanks!

llvm/lib/CodeGen/MachineStableHash.cpp

STATISTIC(StableHashBailingMetadataUnsupported,
           "Number of encountered unsupported MachineOperands that were "
           "Metadata of an unsupported kind while computing stable hashes");
 
 stable_hash llvm::stableHashValue(const MachineOperand &MO) {
   switch (MO.getType()) {
   case MachineOperand::MO_Register:
     if (Register::isVirtualRegister(MO.getReg())) {
       const MachineRegisterInfo &MRI = MO.getParent()->getMF()->getRegInfo();
-      return MRI.getVRegDef(MO.getReg())->getOpcode();
+      SmallVector<unsigned> DefOpcodes;
+      for (auto &Def : MRI.def_instructions(MO.getReg()))
+        DefOpcodes.push_back(Def.getOpcode());
+      return hash_combine_range(DefOpcodes.begin(), DefOpcodes.end());
     }
 
     // Register operands don't have target flags.
     return stable_hash_combine(MO.getType(), MO.getReg(), MO.getSubReg(),
                                MO.isDef());
   case MachineOperand::MO_Immediate:
     return stable_hash_combine(MO.getType(), MO.getTargetFlags(), MO.getImm());
   case MachineOperand::MO_CImmediate: