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Differential D120112

Teach the AArch64 backend to instruction select the BCAX instruction.
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Authored by resistor on Feb 18 2022, 12:16 AM.

Details

Reviewers
dmgreen
Commits
rGd7105e76319c: Teach the AArch64 backend to instruction select the BCAX instruction.

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Event Timeline

resistor created this revision.Feb 18 2022, 12:16 AM
Herald added subscribers: hiraditya, kristof.beyls. · View Herald TranscriptFeb 18 2022, 12:16 AM
resistor requested review of this revision.Feb 18 2022, 12:16 AM
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Harbormaster completed remote builds in B150387: Diff 409868.Feb 18 2022, 1:11 AM
dmgreen added a subscriber: dmgreen.Feb 21 2022, 12:17 AM

You have the operands in the wrong order,

resistor updated this revision to Diff 410447.Feb 21 2022, 9:57 PM

Fix operand order.

resistor added a comment.Feb 21 2022, 9:57 PM
In D120112#3334823, @dmgreen wrote:

You have the operands in the wrong order,

Fixed, thanks!

Harbormaster completed remote builds in B150807: Diff 410447.Feb 21 2022, 10:42 PM
dmgreen accepted this revision.Feb 23 2022, 2:21 AM

Thanks. Can you add an v2i64 test?

Other than that, LGTM

This revision is now accepted and ready to land.Feb 23 2022, 2:21 AM
This revision was landed with ongoing or failed builds.Feb 23 2022, 3:59 PM
Closed by commit rGd7105e76319c: Teach the AArch64 backend to instruction select the BCAX instruction. (authored by resistor). · Explain Why
This revision was automatically updated to reflect the committed changes.
resistor added a commit: rGd7105e76319c: Teach the AArch64 backend to instruction select the BCAX instruction..

Revision Contents

PathSize
llvm/
lib/
Target/
AArch64/
9 lines
test/
CodeGen/
AArch64/
71 lines

Diff 410963

llvm/lib/Target/AArch64/AArch64InstrInfo.td

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 1,018 Lines • ▼ Show 20 Linesclass EOR3_pattern<ValueType VecTy>
: Pat<(xor (xor (VecTy V128:$Vn), (VecTy V128:$Vm)), (VecTy V128:$Va)), : Pat<(xor (xor (VecTy V128:$Vn), (VecTy V128:$Vm)), (VecTy V128:$Va)),
(EOR3 (VecTy V128:$Vn), (VecTy V128:$Vm), (VecTy V128:$Va))>; (EOR3 (VecTy V128:$Vn), (VecTy V128:$Vm), (VecTy V128:$Va))>;
def : EOR3_pattern<v16i8>; def : EOR3_pattern<v16i8>;
def : EOR3_pattern<v8i16>; def : EOR3_pattern<v8i16>;
def : EOR3_pattern<v4i32>; def : EOR3_pattern<v4i32>;
def : EOR3_pattern<v2i64>; def : EOR3_pattern<v2i64>;
class BCAX_pattern<ValueType VecTy>
: Pat<(xor (VecTy V128:$Vn), (and (VecTy V128:$Vm), (vnot (VecTy V128:$Va)))),
(BCAX (VecTy V128:$Vn), (VecTy V128:$Vm), (VecTy V128:$Va))>;
def : BCAX_pattern<v16i8>;
def : BCAX_pattern<v8i16>;
def : BCAX_pattern<v4i32>;
def : BCAX_pattern<v2i64>;
def : SHA3_pattern<BCAX, int_aarch64_crypto_bcaxu, v16i8>; def : SHA3_pattern<BCAX, int_aarch64_crypto_bcaxu, v16i8>;
def : SHA3_pattern<BCAX, int_aarch64_crypto_bcaxu, v8i16>; def : SHA3_pattern<BCAX, int_aarch64_crypto_bcaxu, v8i16>;
def : SHA3_pattern<BCAX, int_aarch64_crypto_bcaxu, v4i32>; def : SHA3_pattern<BCAX, int_aarch64_crypto_bcaxu, v4i32>;
def : SHA3_pattern<BCAX, int_aarch64_crypto_bcaxu, v2i64>; def : SHA3_pattern<BCAX, int_aarch64_crypto_bcaxu, v2i64>;
def : SHA3_pattern<EOR3, int_aarch64_crypto_eor3s, v16i8>; def : SHA3_pattern<EOR3, int_aarch64_crypto_eor3s, v16i8>;
def : SHA3_pattern<EOR3, int_aarch64_crypto_eor3s, v8i16>; def : SHA3_pattern<EOR3, int_aarch64_crypto_eor3s, v8i16>;
def : SHA3_pattern<EOR3, int_aarch64_crypto_eor3s, v4i32>; def : SHA3_pattern<EOR3, int_aarch64_crypto_eor3s, v4i32>;
▲ Show 20 Lines • Show All 7,326 Lines • Show Last 20 Lines

llvm/test/CodeGen/AArch64/bcax.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --extra_scrub
; RUN: llc -mtriple=aarch64-none-eabi -mattr=+sha3 < %s | FileCheck --check-prefix=SHA3 %s
; RUN: llc -mtriple=aarch64-none-eabi -mattr=-sha3 < %s | FileCheck --check-prefix=NOSHA3 %s
define <2 x i64> @bcax_64x2(<2 x i64> %0, <2 x i64> %1, <2 x i64> %2) {
; SHA3-LABEL: bcax_64x2:
; SHA3: // %bb.0:
; SHA3-NEXT: bcax v0.16b, v2.16b, v0.16b, v1.16b
; SHA3-NEXT: ret
;
; NOSHA3-LABEL: bcax_64x2:
; NOSHA3: // %bb.0:
; NOSHA3-NEXT: bic v0.16b, v0.16b, v1.16b
; NOSHA3-NEXT: eor v0.16b, v0.16b, v2.16b
; NOSHA3-NEXT: ret
%4 = xor <2 x i64> %1, <i64 -1, i64 -1>
%5 = and <2 x i64> %4, %0
%6 = xor <2 x i64> %5, %2
ret <2 x i64> %6
}
define <4 x i32> @bcax_32x4(<4 x i32> %0, <4 x i32> %1, <4 x i32> %2) {
; SHA3-LABEL: bcax_32x4:
; SHA3: // %bb.0:
; SHA3-NEXT: bcax v0.16b, v2.16b, v0.16b, v1.16b
; SHA3-NEXT: ret
;
; NOSHA3-LABEL: bcax_32x4:
; NOSHA3: // %bb.0:
; NOSHA3-NEXT: bic v0.16b, v0.16b, v1.16b
; NOSHA3-NEXT: eor v0.16b, v0.16b, v2.16b
; NOSHA3-NEXT: ret
%4 = xor <4 x i32> %1, <i32 -1, i32 -1, i32 -1, i32 -1>
%5 = and <4 x i32> %4, %0
%6 = xor <4 x i32> %5, %2
ret <4 x i32> %6
}
define <8 x i16> @bcax_16x8(<8 x i16> %0, <8 x i16> %1, <8 x i16> %2) {
; SHA3-LABEL: bcax_16x8:
; SHA3: // %bb.0:
; SHA3-NEXT: bcax v0.16b, v2.16b, v0.16b, v1.16b
; SHA3-NEXT: ret
;
; NOSHA3-LABEL: bcax_16x8:
; NOSHA3: // %bb.0:
; NOSHA3-NEXT: bic v0.16b, v0.16b, v1.16b
; NOSHA3-NEXT: eor v0.16b, v0.16b, v2.16b
; NOSHA3-NEXT: ret
%4 = xor <8 x i16> %1, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
%5 = and <8 x i16> %4, %0
%6 = xor <8 x i16> %5, %2
ret <8 x i16> %6
}
define <16 x i8> @bcax_8x16(<16 x i8> %0, <16 x i8> %1, <16 x i8> %2) {
; SHA3-LABEL: bcax_8x16:
; SHA3: // %bb.0:
; SHA3-NEXT: bcax v0.16b, v2.16b, v0.16b, v1.16b
; SHA3-NEXT: ret
;
; NOSHA3-LABEL: bcax_8x16:
; NOSHA3: // %bb.0:
; NOSHA3-NEXT: bic v0.16b, v0.16b, v1.16b
; NOSHA3-NEXT: eor v0.16b, v0.16b, v2.16b
; NOSHA3-NEXT: ret
%4 = xor <16 x i8> %1, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
%5 = and <16 x i8> %4, %0
%6 = xor <16 x i8> %5, %2
ret <16 x i8> %6
}