[RISCV][NFC] Add sched for some instructions in Zb extension

[Jimerlife]

Summary

1. add sched to brev8, zip and unzip instruction

[craig.topper]

llvm/lib/Target/RISCV/RISCVInstrInfoZb.td

602

This change isn't mentioned in the title or the description.

[craig.topper]

llvm/lib/Target/RISCV/RISCVInstrInfoZb.td

860

Is this not a functional change for RV64 because ZIP_RV32 will put 0b01111 in bits 24:20 which matches the 15 that was requested in the pattern?

[Jimerlife]

llvm/lib/Target/RISCV/RISCVInstrInfoZb.td

860

This change will not affect RV64. where defined ZIP_RV32 and UNZIP_RV32 also add "IsRV32" constrain.

[craig.topper]

llvm/lib/Target/RISCV/RISCVInstrInfoZb.td

860

Without this patch isel will pick these instructions on rv64. The IsRV32 on the instructions only affects the assembler or disassembler.

We need to understand what really happens on RV64 so I know if this needs to be bacported to LLVM 14

[Jimerlife]

llvm/lib/Target/RISCV/RISCVInstrInfoZb.td

860

OK, I will remove this change and keep adding only sched in this patch.

[Jimerlife]

only add sched for instructions

[craig.topper]

LGTM

[craig.topper]

llvm/lib/Target/RISCV/RISCVInstrInfoZb.td

860

I investigated this, the use of i32 in the pattern prevents it from matching on RV64. So there was no issue. Still a good idea to use IsRV32. I'll go ahead and commit that. Thanks for spotting it.

llvm/lib/Target/RISCV/RISCVInstrInfoZb.td

 } // Predicates = [HasStdExtZbbOrZbpOrZbkb, IsRV64]
 
 let Predicates = [HasStdExtZbbOrZbp] in {
 def ORC_B : RVBUnary<0b0010100, 0b00111, 0b101, OPC_OP_IMM, "orc.b">,
             Sched<[WriteORCB, ReadORCB]>;
 } // Predicates = [HasStdExtZbbOrZbp]
 
 let Predicates = [HasStdExtZbpOrZbkb] in 
-def BREV8 : RVBUnary<0b0110100, 0b00111, 0b101, OPC_OP_IMM, "brev8">;
+def BREV8 : RVBUnary<0b0110100, 0b00111, 0b101, OPC_OP_IMM, "brev8">,
+            Sched<[]>;
 
 let Predicates = [HasStdExtZbpOrZbkb, IsRV32] in {
-def ZIP_RV32   : RVBUnary<0b0000100, 0b01111, 0b001, OPC_OP_IMM, "zip">;
-def UNZIP_RV32 : RVBUnary<0b0000100, 0b01111, 0b101, OPC_OP_IMM, "unzip">;
+def ZIP_RV32   : RVBUnary<0b0000100, 0b01111, 0b001, OPC_OP_IMM, "zip">,
+                 Sched<[]>;
+def UNZIP_RV32 : RVBUnary<0b0000100, 0b01111, 0b101, OPC_OP_IMM, "unzip">,
+                 Sched<[]>;
 } // Predicates = [HasStdExtZbpOrZbkb, IsRV32]
 
 
 //===----------------------------------------------------------------------===//
 // Pseudo Instructions
 //===----------------------------------------------------------------------===//
 
 let Predicates = [HasStdExtZba, IsRV64] in {

 }
 
 let Predicates = [HasStdExtZbpOrZbkb] in {
 // We treat brev8 as a separate instruction, so match it directly. We also
 // use this for brev8 when lowering bitreverse with Zbkb.
 def : Pat<(riscv_grev GPR:$rs1, 7), (BREV8 GPR:$rs1)>;
 }
 
 let Predicates = [HasStdExtZbpOrZbkb, IsRV32] in {
 // We treat zip and unzip as separate instructions, so match it directly.
 def : Pat<(i32 (riscv_shfl GPR:$rs1, 15)), (ZIP_RV32 GPR:$rs1)>;
 def : Pat<(i32 (riscv_unshfl GPR:$rs1, 15)), (UNZIP_RV32 GPR:$rs1)>;
 }
 
 let Predicates = [HasStdExtZbp] in {
 def : PatGprGpr<riscv_grev, GREV>;
 def : PatGprGpr<riscv_gorc, GORC>;