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[TableGen][AMDGPU] Allow empty register classes
ClosedPublic

Authored by foad on Feb 11 2022, 8:58 AM.

Details

Summary

Remove ARTIFICIAL_VGPR which only existed to make VReg_1 not empty.

Diff Detail

Event Timeline

foad created this revision.Feb 11 2022, 8:58 AM
foad requested review of this revision.Feb 11 2022, 8:58 AM
Herald added a project: Restricted Project. · View Herald TranscriptFeb 11 2022, 8:58 AM
arsenm added inline comments.Feb 11 2022, 8:58 AM
llvm/test/CodeGen/AMDGPU/accvgpr-copy.mir
411–413

Looks like something went wrong or you're missing one of my recent patches

foad added inline comments.Feb 11 2022, 9:04 AM
llvm/test/CodeGen/AMDGPU/accvgpr-copy.mir
411–413

Oh yes, I was going to explain... This is because indirectCopyToAGPR does this, which depends on the internal register numbering, which has changed because ARTIFICIAL_VGPR was removed:

// Registers in the sequence are allocated contiguously so we can just
// use register number to pick one of three round-robin temps.
unsigned RegNo = DestReg % 3;
arsenm accepted this revision.Feb 11 2022, 9:07 AM
This revision is now accepted and ready to land.Feb 11 2022, 9:07 AM
This revision was landed with ongoing or failed builds.Feb 11 2022, 9:30 AM
This revision was automatically updated to reflect the committed changes.

Nice cleanup :)

llvm/utils/TableGen/RegisterInfoEmitter.cpp
1051–1065

Whitespace looks off. Is this using tabs?

foad added inline comments.Feb 15 2022, 5:35 AM
llvm/utils/TableGen/RegisterInfoEmitter.cpp
1051–1065

It looks OK to me. There are no tabs.