[nfc][regalloc] Make the max inference cutoff configurable

[mtrofin]

Summary

Added a flag to make configurable the number of interferences after
which we 'bail out' and treat a set of intervals as un-evictable. Also
using it on the ML side, as it turns out to be a good control for
compile-time.

With this configurable, we can do a bit of trial and error and see if
bumping it has any effect on heuristic/policy quality.

[mstorsjo]

llvm/lib/CodeGen/MLRegallocEvictAdvisor.cpp

63

This broke compilation for me:

../lib/CodeGen/MLRegallocEvictAdvisor.cpp: In member function ‘bool {anonymous}::MLEvictAdvisor::loadInterferenceFeatures(llvm::LiveInterval&, llvm::MCRegister, bool, const SmallVirtRegSet&, {anonymous}::FeaturesListNormalizer&, size_t) const’:
../lib/CodeGen/MLRegallocEvictAdvisor.cpp:549:50: error: ‘EvictInterferenceCutoff’ was not declared in this scope
  549 |     const auto &IFIntervals = Q.interferingVRegs(EvictInterferenceCutof );
      |                                                  ^~~~~~~~~~~~~~~~~~~~~~
../lib/CodeGen/MLRegallocEvictAdvisor.cpp: At global scope:

I guess that's because EvictInterferenceCutoff is declared within an ifdef that isn't taken in my build configuration.

[ronlieb]

seeing same breakage on https://lab.llvm.org/buildbot/#/builders/165/builds/14870
and https://lab.llvm.org/buildbot/#/builders/193/builds/5889

[mtrofin]

just sent the fix.

llvm/lib/CodeGen/MLRegallocEvictAdvisor.cpp

 static cl::opt<std::string> TrainingLog(
     "regalloc-training-log", cl::Hidden,
     cl::desc("Training log for the register allocator eviction model"));
 
 static cl::opt<std::string> ModelUnderTraining(
     "regalloc-model", cl::Hidden,
     cl::desc("The model being trained for register allocation eviction"));
 
+extern cl::opt<unsigned> EvictInterferenceCutoff;
+
 #endif // #ifdef LLVM_HAVE_TF_API
 
 /// The score injection pass.
 /// This pass calculates the score for a function and inserts it in the log, but
 /// this happens only in development mode. It's a no-op otherwise.
 namespace llvm {
 class RegAllocScoring : public MachineFunctionPass {
 public:
   static char ID;
bool MLEvictAdvisor::loadInterferenceFeatures(
   // The cascade tracking is the same as in the default advisor
   unsigned Cascade = RA.getExtraInfo().getCascadeOrCurrentNext(VirtReg.reg());
 
   SmallVector<LiveInterval *, MaxInterferences> InterferingIntervals;
   for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) {
     LiveIntervalUnion::Query &Q = Matrix->query(VirtReg, *Units);
     // Different from the default heuristic, we don't make any assumptions about
     // what having more than 10 results in the query may mean.
-    const auto &IFIntervals = Q.interferingVRegs();
+    const auto &IFIntervals = Q.interferingVRegs(EvictInterferenceCutoff);
     if (IFIntervals.empty() && InterferingIntervals.empty())
       continue;
+    if (IFIntervals.size() >= EvictInterferenceCutoff)
+      return false;
     InterferingIntervals.append(IFIntervals.begin(), IFIntervals.end());
     for (LiveInterval *Intf : reverse(IFIntervals)) {
       assert(Register::isVirtualRegister(Intf->reg()) &&
              "Only expecting virtual register interference from query");
       // This is the same set of legality checks as in the default case: don't
       // try to evict fixed regs or 'done' ones. Also don't break cascades,
       // except in the urgent case, with the same nuances used in the default
       // heuristic.

llvm/lib/CodeGen/RegAllocEvictionAdvisor.cpp

cl::values(
                    "development", "for training")));
 
 static cl::opt<bool> EnableLocalReassignment(
     "enable-local-reassign", cl::Hidden,
     cl::desc("Local reassignment can yield better allocation decisions, but "
              "may be compile time intensive"),
     cl::init(false));
 
+cl::opt<unsigned> EvictInterferenceCutoff(
+    "regalloc-eviction-max-interference-cutoff", cl::Hidden,
+    cl::desc("Number of interferences after which we declare "
+             "an interference unevictable and bail out. This "
+             "is a compilation cost-saving consideration. To "
+             "disable, pass a very large number."),
+    cl::init(10));
+
 #define DEBUG_TYPE "regalloc"
 #ifdef LLVM_HAVE_TF_AOT_REGALLOCEVICTMODEL
 #define LLVM_HAVE_TF_AOT
 #endif
 
 char RegAllocEvictionAdvisorAnalysis::ID = 0;
 INITIALIZE_PASS(RegAllocEvictionAdvisorAnalysis, "regalloc-evict",
                 "Regalloc eviction policy", false, true)
bool DefaultEvictionAdvisor::canEvictInterferenceBasedOnCost(
   // This works out so a register without a cascade number is allowed to evict
   // anything, and it can be evicted by anything.
   unsigned Cascade = RA.getExtraInfo().getCascadeOrCurrentNext(VirtReg.reg());
 
   EvictionCost Cost;
   for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) {
     LiveIntervalUnion::Query &Q = Matrix->query(VirtReg, *Units);
     // If there is 10 or more interferences, chances are one is heavier.
-    const auto &Interferences = Q.interferingVRegs(10);
-    if (Interferences.size() >= 10)
+    const auto &Interferences = Q.interferingVRegs(EvictInterferenceCutoff);
+    if (Interferences.size() >= EvictInterferenceCutoff)
       return false;
 
     // Check if any interfering live range is heavier than MaxWeight.
     for (LiveInterval *Intf : reverse(Interferences)) {
       assert(Register::isVirtualRegister(Intf->reg()) &&
              "Only expecting virtual register interference from query");
 
       // Do not allow eviction of a virtual register if we are in the middle