[AArch64] Adjust aarch64 constrained intrinsics tests and un-XFAIL

[john.brawn]

Summary

Remove the checking of the generated asm, as that's already tested elsewhere, and adjust some tests that were expecting the wrong intrinsic to be generated.

[fhahn]

Does this clang test actually need to check the generated assembly? Shouldn't it be enough to check that the correct intrinsics are generated?

[john.brawn]

In D118259#3275297, @fhahn wrote:

Does this clang test actually need to check the generated assembly? Shouldn't it be enough to check that the correct intrinsics are generated?

I could remove the CHECK-ASM checks, but the other xyz-constrained.c tests (including non-aarch64 ones) all do this and it feels a bit weird to just do that to this test.

[john.brawn]

Ping.

[john.brawn]

Ping.

[fhahn]

In D118259#3343554, @john.brawn wrote:

In D118259#3275297, @fhahn wrote:

Does this clang test actually need to check the generated assembly? Shouldn't it be enough to check that the correct intrinsics are generated?

I could remove the CHECK-ASM checks, but the other xyz-constrained.c tests (including non-aarch64 ones) all do this and it feels a bit weird to just do that to this test.

I guess the question is if there is a convincing reason to check the assembly in this test? Unless it is required for the test, checking for assembly makes the test more fragile than they need to be. Also, is there any difference in the generated IR between X86 and AArch64? If not, the tests should probably be unified.

[john.brawn]

llvm/test/CodeGen/AArch64/fp-intrinsics-vector.ll is testing the asm generation, so it probably is fine to remove that here so I will. This test is specifically testing arm_neon.h intrinsics though, so wouldn't make sense unifying with other architectures.

[kpn]

It's been a while, but I think the aarch64-neon-intrinsics-constrained.c test is trimmed down from the aarch64-neon-intrinsics.c test. Shouldn't the constrained and non-constrained end-to-end tests be treated the same?

[fhahn]

In D118259#3389235, @kpn wrote:

It's been a while, but I think the aarch64-neon-intrinsics-constrained.c test is trimmed down from the aarch64-neon-intrinsics.c test. Shouldn't the constrained and non-constrained end-to-end tests be treated the same?

Are you referring to https://github.com/llvm/llvm-project/blob/main/clang/test/CodeGen/aarch64-neon-intrinsics.c? This one doesn't check assembly.

[kpn]

In D118259#3389246, @fhahn wrote:

In D118259#3389235, @kpn wrote:

It's been a while, but I think the aarch64-neon-intrinsics-constrained.c test is trimmed down from the aarch64-neon-intrinsics.c test. Shouldn't the constrained and non-constrained end-to-end tests be treated the same?

Are you referring to https://github.com/llvm/llvm-project/blob/main/clang/test/CodeGen/aarch64-neon-intrinsics.c? This one doesn't check assembly.

Ah, well, I guess that wasn't it, then. It's been a while, and I've been all over the place.

A clang-only test that just tests for the correct IR being emitted won't trigger the failures in the backend. An LLVM-only test that starts from that IR can show those failures, but it also runs the risk over time of getting out of sync with the IR emitted by clang. An end-to-end test will always be in sync, and it will show those failures that I ran into plus anything else that crops up over time. If there's another way, or if there is another approach, then it might be possible there's a way to get all the testing done without running into those issues. I just don't know what it is.

[john.brawn]

Also adjust aarch64-v8.2a-fp16-intrinsics-constrained.c in this patch (was previously done in
D115620) and remove the checks of the generated asm.

[kpn]

I trust you on the instruction set changes. LGTM.

clang/test/CodeGen/aarch64-neon-intrinsics-constrained.c

 // RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon \
 // RUN:     -fallow-half-arguments-and-returns -S -disable-O0-optnone \
 // RUN:  -flax-vector-conversions=none -emit-llvm -o - %s | opt -S -mem2reg \
-// RUN: | FileCheck --check-prefix=COMMON --check-prefix=COMMONIR --check-prefix=UNCONSTRAINED %s
+// RUN: | FileCheck --check-prefixes=COMMON,COMMONIR,UNCONSTRAINED %s
 // RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon \
 // RUN:     -fallow-half-arguments-and-returns -S -disable-O0-optnone \
-// RUN:  -ffp-exception-behavior=strict \
+// RUN:  -ffp-exception-behavior=strict -fexperimental-strict-floating-point \
 // RUN:  -flax-vector-conversions=none -emit-llvm -o - %s | opt -S -mem2reg \
-// RUN: | FileCheck --check-prefix=COMMON --check-prefix=COMMONIR --check-prefix=CONSTRAINED %s
+// RUN: | FileCheck --check-prefixes=COMMON,COMMONIR,CONSTRAINED %s
 // RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon \
 // RUN:     -fallow-half-arguments-and-returns -S -disable-O0-optnone \
 // RUN:  -flax-vector-conversions=none -o - %s \
-// RUN: | FileCheck --check-prefix=COMMON --check-prefix=CHECK-ASM %s
+// RUN: | FileCheck --check-prefixes=COMMON,CHECK-ASM,CHECK-ASM-UNCONSTRAINED %s
 // RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon \
 // RUN:     -fallow-half-arguments-and-returns -S -disable-O0-optnone \
-// RUN:  -ffp-exception-behavior=strict \
+// RUN:  -ffp-exception-behavior=strict -fexperimental-strict-floating-point \
 // RUN:  -flax-vector-conversions=none -o - %s \
-// RUN: | FileCheck --check-prefix=COMMON --check-prefix=CHECK-ASM %s
+// RUN: | FileCheck --check-prefixes=COMMON,CHECK-ASM,CHECK-ASM-CONSTRAINED %s
 
 // REQUIRES: aarch64-registered-target
 
-// Fails during instruction selection:
-// XFAIL: *
-
 // Test new aarch64 intrinsics and types but constrained
 
 #include <arm_neon.h>
 
 // COMMON-LABEL: test_vadd_f32
 // UNCONSTRAINED: [[ADD_I:%.*]] = fadd <2 x float> %v1, %v2
 // CONSTRAINED:   [[ADD_I:%.*]] = call <2 x float> @llvm.experimental.constrained.fadd.v2f32(<2 x float> %v1, <2 x float> %v2, metadata !"round.tonearest", metadata !"fpexcept.strict")
 // CHECK-ASM:     fadd v{{[0-9]+}}.2s, v{{[0-9]+}}.2s, v{{[0-9]+}}.2s

 // COMMONIR:      ret <2 x float> [[DIV_I]]
 float32x2_t test_vdiv_f32(float32x2_t v1, float32x2_t v2) {
   return vdiv_f32(v1, v2);
 }
 
 // COMMON-LABEL: test_vceq_f32
 // UNCONSTRAINED: [[CMP_I:%.*]] = fcmp oeq <2 x float> %v1, %v2
 // CONSTRAINED:   [[CMP_I:%.*]] = call <2 x i1> @llvm.experimental.constrained.fcmp.v2f32(<2 x float> %v1, <2 x float> %v2, metadata !"oeq", metadata !"fpexcept.strict")
-// CHECK-ASM:     fcmeq v{{[0-9]+}}.2s, v{{[0-9]+}}.2s, v{{[0-9]+}}.2s
+// CHECK-ASM-UNCONSTRAINED: fcmeq v{{[0-9]+}}.2s, v{{[0-9]+}}.2s, v{{[0-9]+}}.2s
+// CHECK-ASM-CONSTRAINED: fcmp s{{[0-9]+}}, s{{[0-9]+}}
+// CHECK-ASM-CONSTRAINED: fcmp s{{[0-9]+}}, s{{[0-9]+}}
 // COMMONIR:      [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i32>
 // COMMONIR:      ret <2 x i32> [[SEXT_I]]
 uint32x2_t test_vceq_f32(float32x2_t v1, float32x2_t v2) {
   return vceq_f32(v1, v2);
 }
 
 // COMMON-LABEL: test_vceq_f64
 // UNCONSTRAINED: [[CMP_I:%.*]] = fcmp oeq <1 x double> %a, %b
 // CONSTRAINED:   [[CMP_I:%.*]] = call <1 x i1> @llvm.experimental.constrained.fcmp.v1f64(<1 x double> %a, <1 x double> %b, metadata !"oeq", metadata !"fpexcept.strict")
 // CHECK-ASM:     fcmp d{{[0-9]+}}, d{{[0-9]+}}
 // CHECK-ASM-NEXT:cset {{w[0-9]+}}, eq
 // COMMONIR:      [[SEXT_I:%.*]] = sext <1 x i1> [[CMP_I]] to <1 x i64>
 // COMMONIR:      ret <1 x i64> [[SEXT_I]]
 uint64x1_t test_vceq_f64(float64x1_t a, float64x1_t b) {
   return vceq_f64(a, b);
 }
 
 // COMMON-LABEL: test_vceqq_f32
 // UNCONSTRAINED: [[CMP_I:%.*]] = fcmp oeq <4 x float> %v1, %v2
 // CONSTRAINED:   [[CMP_I:%.*]] = call <4 x i1> @llvm.experimental.constrained.fcmp.v4f32(<4 x float> %v1, <4 x float> %v2, metadata !"oeq", metadata !"fpexcept.strict")
-// CHECK-ASM:     fcmeq v{{[0-9]+}}.4s, v{{[0-9]+}}.4s, v{{[0-9]+}}.4s
+// CHECK-ASM-UNCONSTRAINED: fcmeq v{{[0-9]+}}.4s, v{{[0-9]+}}.4s, v{{[0-9]+}}.4s
+// CHECK-ASM-CONSTRAINED: fcmp s{{[0-9]+}}, s{{[0-9]+}}
+// CHECK-ASM-CONSTRAINED: fcmp s{{[0-9]+}}, s{{[0-9]+}}
+// CHECK-ASM-CONSTRAINED: fcmp s{{[0-9]+}}, s{{[0-9]+}}
+// CHECK-ASM-CONSTRAINED: fcmp s{{[0-9]+}}, s{{[0-9]+}}
 // COMMONIR:      [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i32>
 // COMMONIR:      ret <4 x i32> [[SEXT_I]]
 uint32x4_t test_vceqq_f32(float32x4_t v1, float32x4_t v2) {
   return vceqq_f32(v1, v2);
 }
 
 // COMMON-LABEL: test_vceqq_f64
 // UNCONSTRAINED: [[CMP_I:%.*]] = fcmp oeq <2 x double> %v1, %v2
 // CONSTRAINED:   [[CMP_I:%.*]] = call <2 x i1> @llvm.experimental.constrained.fcmp.v2f64(<2 x double> %v1, <2 x double> %v2, metadata !"oeq", metadata !"fpexcept.strict")
-// CHECK-ASM:     fcmeq v{{[0-9]+}}.2d, v{{[0-9]+}}.2d, v{{[0-9]+}}.2d
+// CHECK-ASM-UNCONSTRAINED: fcmeq v{{[0-9]+}}.2d, v{{[0-9]+}}.2d, v{{[0-9]+}}.2d
+// CHECK-ASM-CONSTRAINED: fcmp d{{[0-9]+}}, d{{[0-9]+}}
+// CHECK-ASM-CONSTRAINED: fcmp d{{[0-9]+}}, d{{[0-9]+}}
 // COMMONIR:      [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i64>
 // COMMONIR:      ret <2 x i64> [[SEXT_I]]
 uint64x2_t test_vceqq_f64(float64x2_t v1, float64x2_t v2) {
   return vceqq_f64(v1, v2);
 }
 
 // COMMON-LABEL: test_vcge_f32
 // UNCONSTRAINED: [[CMP_I:%.*]] = fcmp oge <2 x float> %v1, %v2
 // CONSTRAINED:   [[CMP_I:%.*]] = call <2 x i1> @llvm.experimental.constrained.fcmps.v2f32(<2 x float> %v1, <2 x float> %v2, metadata !"oge", metadata !"fpexcept.strict")
-// CHECK-ASM:     fcmge v{{[0-9]+}}.2s, v{{[0-9]+}}.2s, v{{[0-9]+}}.2s
+// CHECK-ASM-UNCONSTRAINED: fcmge v{{[0-9]+}}.2s, v{{[0-9]+}}.2s, v{{[0-9]+}}.2s
+// CHECK-ASM-CONSTRAINED: fcmpe s{{[0-9]+}}, s{{[0-9]+}}
+// CHECK-ASM-CONSTRAINED: fcmpe s{{[0-9]+}}, s{{[0-9]+}}
 // COMMONIR:      [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i32>
 // COMMONIR:      ret <2 x i32> [[SEXT_I]]
 uint32x2_t test_vcge_f32(float32x2_t v1, float32x2_t v2) {
   return vcge_f32(v1, v2);
 }
 
 // COMMON-LABEL: test_vcge_f64
 // UNCONSTRAINED: [[CMP_I:%.*]] = fcmp oge <1 x double> %a, %b
 // CONSTRAINED:   [[CMP_I:%.*]] = call <1 x i1> @llvm.experimental.constrained.fcmps.v1f64(<1 x double> %a, <1 x double> %b, metadata !"oge", metadata !"fpexcept.strict")
-// CHECK-ASM:     fcmp d{{[0-9]+}}, d{{[0-9]+}}
+// CHECK-ASM-UNCONSTRAINED: fcmp d{{[0-9]+}}, d{{[0-9]+}}
+// CHECK-ASM-CONSTRAINED: fcmpe d{{[0-9]+}}, d{{[0-9]+}}
 // CHECK-ASM-NEXT:cset {{w[0-9]+}}, ge
 // COMMONIR:      [[SEXT_I:%.*]] = sext <1 x i1> [[CMP_I]] to <1 x i64>
 // COMMONIR:      ret <1 x i64> [[SEXT_I]]
 uint64x1_t test_vcge_f64(float64x1_t a, float64x1_t b) {
   return vcge_f64(a, b);
 }
 
 // COMMON-LABEL: test_vcgeq_f32
 // UNCONSTRAINED: [[CMP_I:%.*]] = fcmp oge <4 x float> %v1, %v2
 // CONSTRAINED:   [[CMP_I:%.*]] = call <4 x i1> @llvm.experimental.constrained.fcmps.v4f32(<4 x float> %v1, <4 x float> %v2, metadata !"oge", metadata !"fpexcept.strict")
-// CHECK-ASM:     fcmge v{{[0-9]+}}.4s, v{{[0-9]+}}.4s, v{{[0-9]+}}.4s
+// CHECK-ASM-UNCONSTRAINED: fcmge v{{[0-9]+}}.4s, v{{[0-9]+}}.4s, v{{[0-9]+}}.4s
+// CHECK-ASM-CONSTRAINED: fcmpe s{{[0-9]+}}, s{{[0-9]+}}
+// CHECK-ASM-CONSTRAINED: fcmpe s{{[0-9]+}}, s{{[0-9]+}}
+// CHECK-ASM-CONSTRAINED: fcmpe s{{[0-9]+}}, s{{[0-9]+}}
+// CHECK-ASM-CONSTRAINED: fcmpe s{{[0-9]+}}, s{{[0-9]+}}
 // COMMONIR:      [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i32>
 // COMMONIR:      ret <4 x i32> [[SEXT_I]]
 uint32x4_t test_vcgeq_f32(float32x4_t v1, float32x4_t v2) {
   return vcgeq_f32(v1, v2);
 }
 
 // COMMON-LABEL: test_vcgeq_f64
 // UNCONSTRAINED: [[CMP_I:%.*]] = fcmp oge <2 x double> %v1, %v2
 // CONSTRAINED:   [[CMP_I:%.*]] = call <2 x i1> @llvm.experimental.constrained.fcmps.v2f64(<2 x double> %v1, <2 x double> %v2, metadata !"oge", metadata !"fpexcept.strict")
-// CHECK-ASM:     fcmge v{{[0-9]+}}.2d, v{{[0-9]+}}.2d, v{{[0-9]+}}.2d
+// CHECK-ASM-UNCONSTRAINED: fcmge v{{[0-9]+}}.2d, v{{[0-9]+}}.2d, v{{[0-9]+}}.2d
+// CHECK-ASM-CONSTRAINED: fcmpe d{{[0-9]+}}, d{{[0-9]+}}
+// CHECK-ASM-CONSTRAINED: fcmpe d{{[0-9]+}}, d{{[0-9]+}}
 // COMMONIR:      [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i64>
 // COMMONIR:      ret <2 x i64> [[SEXT_I]]
 uint64x2_t test_vcgeq_f64(float64x2_t v1, float64x2_t v2) {
   return vcgeq_f64(v1, v2);
 }
 
 // COMMON-LABEL: test_vcle_f32
 // UNCONSTRAINED: [[CMP_I:%.*]] = fcmp ole <2 x float> %v1, %v2
 // CONSTRAINED:   [[CMP_I:%.*]] = call <2 x i1> @llvm.experimental.constrained.fcmps.v2f32(<2 x float> %v1, <2 x float> %v2, metadata !"ole", metadata !"fpexcept.strict")
-// CHECK-ASM:     fcmge v{{[0-9]+}}.2s, v{{[0-9]+}}.2s, v{{[0-9]+}}.2s
+// CHECK-ASM-UNCONSTRAINED: fcmge v{{[0-9]+}}.2s, v{{[0-9]+}}.2s, v{{[0-9]+}}.2s
+// CHECK-ASM-CONSTRAINED: fcmpe s{{[0-9]+}}, s{{[0-9]+}}
+// CHECK-ASM-CONSTRAINED: fcmpe s{{[0-9]+}}, s{{[0-9]+}}
 // COMMONIR:      [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i32>
 // COMMONIR:      ret <2 x i32> [[SEXT_I]]
 uint32x2_t test_vcle_f32(float32x2_t v1, float32x2_t v2) {
   return vcle_f32(v1, v2);
 }
 
 // COMMON-LABEL: test_vcle_f64
 // UNCONSTRAINED: [[CMP_I:%.*]] = fcmp ole <1 x double> %a, %b
 // CONSTRAINED:   [[CMP_I:%.*]] = call <1 x i1> @llvm.experimental.constrained.fcmps.v1f64(<1 x double> %a, <1 x double> %b, metadata !"ole", metadata !"fpexcept.strict")
-// CHECK-ASM:     fcmp d{{[0-9]+}}, d{{[0-9]+}}
+// CHECK-ASM-UNCONSTRAINED: fcmp d{{[0-9]+}}, d{{[0-9]+}}
+// CHECK-ASM-CONSTRAINED: fcmpe d{{[0-9]+}}, d{{[0-9]+}}
 // CHECK-ASM-NEXT:cset {{w[0-9]+}}, ls
 // COMMONIR:      [[SEXT_I:%.*]] = sext <1 x i1> [[CMP_I]] to <1 x i64>
 // COMMONIR:      ret <1 x i64> [[SEXT_I]]
 uint64x1_t test_vcle_f64(float64x1_t a, float64x1_t b) {
   return vcle_f64(a, b);
 }
 
 // COMMON-LABEL: test_vcleq_f32
 // UNCONSTRAINED: [[CMP_I:%.*]] = fcmp ole <4 x float> %v1, %v2
 // CONSTRAINED:   [[CMP_I:%.*]] = call <4 x i1> @llvm.experimental.constrained.fcmps.v4f32(<4 x float> %v1, <4 x float> %v2, metadata !"ole", metadata !"fpexcept.strict")
-// CHECK-ASM:     fcmge v{{[0-9]+}}.4s, v{{[0-9]+}}.4s, v{{[0-9]+}}.4s
+// CHECK-ASM-UNCONSTRAINED: fcmge v{{[0-9]+}}.4s, v{{[0-9]+}}.4s, v{{[0-9]+}}.4s
+// CHECK-ASM-CONSTRAINED: fcmpe s{{[0-9]+}}, s{{[0-9]+}}
+// CHECK-ASM-CONSTRAINED: fcmpe s{{[0-9]+}}, s{{[0-9]+}}
+// CHECK-ASM-CONSTRAINED: fcmpe s{{[0-9]+}}, s{{[0-9]+}}
+// CHECK-ASM-CONSTRAINED: fcmpe s{{[0-9]+}}, s{{[0-9]+}}
 // COMMONIR:      [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i32>
 // COMMONIR:      ret <4 x i32> [[SEXT_I]]
 uint32x4_t test_vcleq_f32(float32x4_t v1, float32x4_t v2) {
   return vcleq_f32(v1, v2);
 }
 
 // COMMON-LABEL: test_vcleq_f64
 // UNCONSTRAINED: [[CMP_I:%.*]] = fcmp ole <2 x double> %v1, %v2
 // CONSTRAINED:   [[CMP_I:%.*]] = call <2 x i1> @llvm.experimental.constrained.fcmps.v2f64(<2 x double> %v1, <2 x double> %v2, metadata !"ole", metadata !"fpexcept.strict")
-// CHECK-ASM:     fcmge v{{[0-9]+}}.2d, v{{[0-9]+}}.2d, v{{[0-9]+}}.2d
+// CHECK-ASM-UNCONSTRAINED: fcmge v{{[0-9]+}}.2d, v{{[0-9]+}}.2d, v{{[0-9]+}}.2d
+// CHECK-ASM-CONSTRAINED: fcmpe d{{[0-9]+}}, d{{[0-9]+}}
+// CHECK-ASM-CONSTRAINED: fcmpe d{{[0-9]+}}, d{{[0-9]+}}
 // COMMONIR:      [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i64>
 // COMMONIR:      ret <2 x i64> [[SEXT_I]]
 uint64x2_t test_vcleq_f64(float64x2_t v1, float64x2_t v2) {
   return vcleq_f64(v1, v2);
 }
 
 // COMMON-LABEL: test_vcgt_f32
 // UNCONSTRAINED: [[CMP_I:%.*]] = fcmp ogt <2 x float> %v1, %v2
 // CONSTRAINED:   [[CMP_I:%.*]] = call <2 x i1> @llvm.experimental.constrained.fcmps.v2f32(<2 x float> %v1, <2 x float> %v2, metadata !"ogt", metadata !"fpexcept.strict")
-// CHECK-ASM:     fcmgt v{{[0-9]+}}.2s, v{{[0-9]+}}.2s, v{{[0-9]+}}.2s
+// CHECK-ASM-UNCONSTRAINED: fcmgt v{{[0-9]+}}.2s, v{{[0-9]+}}.2s, v{{[0-9]+}}.2s
+// CHECK-ASM-CONSTRAINED: fcmpe s{{[0-9]+}}, s{{[0-9]+}}
+// CHECK-ASM-CONSTRAINED: fcmpe s{{[0-9]+}}, s{{[0-9]+}}
 // COMMONIR:      [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i32>
 // COMMONIR:      ret <2 x i32> [[SEXT_I]]
 uint32x2_t test_vcgt_f32(float32x2_t v1, float32x2_t v2) {
   return vcgt_f32(v1, v2);
 }
 
 // COMMON-LABEL: test_vcgt_f64
 // UNCONSTRAINED: [[CMP_I:%.*]] = fcmp ogt <1 x double> %a, %b
 // CONSTRAINED:   [[CMP_I:%.*]] = call <1 x i1> @llvm.experimental.constrained.fcmps.v1f64(<1 x double> %a, <1 x double> %b, metadata !"ogt", metadata !"fpexcept.strict")
-// CHECK-ASM:     fcmp d{{[0-9]+}}, d{{[0-9]+}}
+// CHECK-ASM-UNCONSTRAINED: fcmp d{{[0-9]+}}, d{{[0-9]+}}
+// CHECK-ASM-CONSTRAINED: fcmpe d{{[0-9]+}}, d{{[0-9]+}}
 // CHECK-ASM-NEXT:cset {{w[0-9]+}}, gt
 // COMMONIR:      [[SEXT_I:%.*]] = sext <1 x i1> [[CMP_I]] to <1 x i64>
 // COMMONIR:      ret <1 x i64> [[SEXT_I]]
 uint64x1_t test_vcgt_f64(float64x1_t a, float64x1_t b) {
   return vcgt_f64(a, b);
 }
 
 // COMMON-LABEL: test_vcgtq_f32
 // UNCONSTRAINED: [[CMP_I:%.*]] = fcmp ogt <4 x float> %v1, %v2
 // CONSTRAINED:   [[CMP_I:%.*]] = call <4 x i1> @llvm.experimental.constrained.fcmps.v4f32(<4 x float> %v1, <4 x float> %v2, metadata !"ogt", metadata !"fpexcept.strict")
-// CHECK-ASM:     fcmgt v{{[0-9]+}}.4s, v{{[0-9]+}}.4s, v{{[0-9]+}}.4s
+// CHECK-ASM-UNCONSTRAINED: fcmgt v{{[0-9]+}}.4s, v{{[0-9]+}}.4s, v{{[0-9]+}}.4s
+// CHECK-ASM-CONSTRAINED: fcmpe s{{[0-9]+}}, s{{[0-9]+}}
+// CHECK-ASM-CONSTRAINED: fcmpe s{{[0-9]+}}, s{{[0-9]+}}
+// CHECK-ASM-CONSTRAINED: fcmpe s{{[0-9]+}}, s{{[0-9]+}}
+// CHECK-ASM-CONSTRAINED: fcmpe s{{[0-9]+}}, s{{[0-9]+}}
 // COMMONIR:      [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i32>
 // COMMONIR:      ret <4 x i32> [[SEXT_I]]
 uint32x4_t test_vcgtq_f32(float32x4_t v1, float32x4_t v2) {
   return vcgtq_f32(v1, v2);
 }
 
 // COMMON-LABEL: test_vcgtq_f64
 // UNCONSTRAINED: [[CMP_I:%.*]] = fcmp ogt <2 x double> %v1, %v2
 // CONSTRAINED:   [[CMP_I:%.*]] = call <2 x i1> @llvm.experimental.constrained.fcmps.v2f64(<2 x double> %v1, <2 x double> %v2, metadata !"ogt", metadata !"fpexcept.strict")
-// CHECK-ASM:     fcmgt v{{[0-9]+}}.2d, v{{[0-9]+}}.2d, v{{[0-9]+}}.2d
+// CHECK-ASM-UNCONSTRAINED: fcmgt v{{[0-9]+}}.2d, v{{[0-9]+}}.2d, v{{[0-9]+}}.2d
+// CHECK-ASM-CONSTRAINED: fcmpe d{{[0-9]+}}, d{{[0-9]+}}
+// CHECK-ASM-CONSTRAINED: fcmpe d{{[0-9]+}}, d{{[0-9]+}}
 // COMMONIR:      [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i64>
 // COMMONIR:      ret <2 x i64> [[SEXT_I]]
 uint64x2_t test_vcgtq_f64(float64x2_t v1, float64x2_t v2) {
   return vcgtq_f64(v1, v2);
 }
 
 // COMMON-LABEL: test_vclt_f32
 // UNCONSTRAINED: [[CMP_I:%.*]] = fcmp olt <2 x float> %v1, %v2
 // CONSTRAINED:   [[CMP_I:%.*]] = call <2 x i1> @llvm.experimental.constrained.fcmps.v2f32(<2 x float> %v1, <2 x float> %v2, metadata !"olt", metadata !"fpexcept.strict")
-// CHECK-ASM:     fcmgt v{{[0-9]+}}.2s, v{{[0-9]+}}.2s, v{{[0-9]+}}.2s
+// CHECK-ASM-UNCONSTRAINED: fcmgt v{{[0-9]+}}.2s, v{{[0-9]+}}.2s, v{{[0-9]+}}.2s
+// CHECK-ASM-CONSTRAINED: fcmpe s{{[0-9]+}}, s{{[0-9]+}}
+// CHECK-ASM-CONSTRAINED: fcmpe s{{[0-9]+}}, s{{[0-9]+}}
 // COMMONIR:      [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i32>
 // COMMONIR:      ret <2 x i32> [[SEXT_I]]
 uint32x2_t test_vclt_f32(float32x2_t v1, float32x2_t v2) {
   return vclt_f32(v1, v2);
 }
 
 // COMMON-LABEL: test_vclt_f64
 // UNCONSTRAINED: [[CMP_I:%.*]] = fcmp olt <1 x double> %a, %b
 // CONSTRAINED:   [[CMP_I:%.*]] = call <1 x i1> @llvm.experimental.constrained.fcmps.v1f64(<1 x double> %a, <1 x double> %b, metadata !"olt", metadata !"fpexcept.strict")
-// CHECK-ASM:     fcmp d{{[0-9]+}}, d{{[0-9]+}}
+// CHECK-ASM-UNCONSTRAINED: fcmp d{{[0-9]+}}, d{{[0-9]+}}
+// CHECK-ASM-CONSTRAINED: fcmpe d{{[0-9]+}}, d{{[0-9]+}}
 // CHECK-ASM-NEXT:cset {{w[0-9]+}}, mi
 // COMMONIR:      [[SEXT_I:%.*]] = sext <1 x i1> [[CMP_I]] to <1 x i64>
 // COMMONIR:      ret <1 x i64> [[SEXT_I]]
 uint64x1_t test_vclt_f64(float64x1_t a, float64x1_t b) {
   return vclt_f64(a, b);
 }
 
 // COMMON-LABEL: test_vcltq_f32
 // UNCONSTRAINED: [[CMP_I:%.*]] = fcmp olt <4 x float> %v1, %v2
 // CONSTRAINED:   [[CMP_I:%.*]] = call <4 x i1> @llvm.experimental.constrained.fcmps.v4f32(<4 x float> %v1, <4 x float> %v2, metadata !"olt", metadata !"fpexcept.strict")
-// CHECK-ASM:     fcmgt v{{[0-9]+}}.4s, v{{[0-9]+}}.4s, v{{[0-9]+}}.4s
+// CHECK-ASM-UNCONSTRAINED: fcmgt v{{[0-9]+}}.4s, v{{[0-9]+}}.4s, v{{[0-9]+}}.4s
+// CHECK-ASM-CONSTRAINED: fcmpe s{{[0-9]+}}, s{{[0-9]+}}
+// CHECK-ASM-CONSTRAINED: fcmpe s{{[0-9]+}}, s{{[0-9]+}}
+// CHECK-ASM-CONSTRAINED: fcmpe s{{[0-9]+}}, s{{[0-9]+}}
+// CHECK-ASM-CONSTRAINED: fcmpe s{{[0-9]+}}, s{{[0-9]+}}
 // COMMONIR:      [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i32>
 // COMMONIR:      ret <4 x i32> [[SEXT_I]]
 uint32x4_t test_vcltq_f32(float32x4_t v1, float32x4_t v2) {
   return vcltq_f32(v1, v2);
 }
 
 // COMMON-LABEL: test_vcltq_f64
 // UNCONSTRAINED: [[CMP_I:%.*]] = fcmp olt <2 x double> %v1, %v2
 // CONSTRAINED:   [[CMP_I:%.*]] = call <2 x i1> @llvm.experimental.constrained.fcmps.v2f64(<2 x double> %v1, <2 x double> %v2, metadata !"olt", metadata !"fpexcept.strict")
-// CHECK-ASM:     fcmgt v{{[0-9]+}}.2d, v{{[0-9]+}}.2d, v{{[0-9]+}}.2d
+// CHECK-ASM-UNCONSTRAINED: fcmgt v{{[0-9]+}}.2d, v{{[0-9]+}}.2d, v{{[0-9]+}}.2d
+// CHECK-ASM-CONSTRAINED: fcmpe d{{[0-9]+}}, d{{[0-9]+}}
+// CHECK-ASM-CONSTRAINED: fcmpe d{{[0-9]+}}, d{{[0-9]+}}
 // COMMONIR:      [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i64>
 // COMMONIR:      ret <2 x i64> [[SEXT_I]]
 uint64x2_t test_vcltq_f64(float64x2_t v1, float64x2_t v2) {
   return vcltq_f64(v1, v2);
 }
 
 // COMMON-LABEL: test_vpadds_f32
 // COMMONIR:      [[LANE0_I:%.*]] = extractelement <2 x float> %a, i64 0
 // COMMONIR:      [[LANE1_I:%.*]] = extractelement <2 x float> %a, i64 1
 // UNCONSTRAINED: [[VPADDD_I:%.*]] = fadd float [[LANE0_I]], [[LANE1_I]]
 // CONSTRAINED:   [[VPADDD_I:%.*]] = call float @llvm.experimental.constrained.fadd.f32(float [[LANE0_I]], float [[LANE1_I]], metadata !"round.tonearest", metadata !"fpexcept.strict"
-// CHECK-ASM:     fadd s{{[0-9]+}}, s{{[0-9]+}}, s{{[0-9]+}}
+// CHECK-ASM:     faddp s{{[0-9]+}}, v{{[0-9]+}}.2s
 // COMMONIR:      ret float [[VPADDD_I]]
 float32_t test_vpadds_f32(float32x2_t a) {
   return vpadds_f32(a);
 }
 
 // COMMON-LABEL: test_vpaddd_f64
 // COMMONIR:      [[LANE0_I:%.*]] = extractelement <2 x double> %a, i64 0
 // COMMONIR:      [[LANE1_I:%.*]] = extractelement <2 x double> %a, i64 1
 // UNCONSTRAINED: [[VPADDD_I:%.*]] = fadd double [[LANE0_I]], [[LANE1_I]]
 // CONSTRAINED:   [[VPADDD_I:%.*]] = call double @llvm.experimental.constrained.fadd.f64(double [[LANE0_I]], double [[LANE1_I]], metadata !"round.tonearest", metadata !"fpexcept.strict")
 // CHECK-ASM:     faddp d{{[0-9]+}}, v{{[0-9]+}}.2d
 // COMMONIR:      ret double [[VPADDD_I]]
 float64_t test_vpaddd_f64(float64x2_t a) {
   return vpaddd_f64(a);
 }
 
 // COMMON-LABEL: test_vcvts_f32_s32
 // UNCONSTRAINED: [[TMP0:%.*]] = sitofp i32 %a to float
 // CONSTRAINED:   [[TMP0:%.*]] = call float @llvm.experimental.constrained.sitofp.f32.i32(i32 %a, metadata !"round.tonearest", metadata !"fpexcept.strict")
-// CHECK-ASM:     scvtf s{{[0-9]+}}, w{{[0-9]+}}
+// CHECK-ASM:     scvtf s{{[0-9]+}}, {{s|w}}{{[0-9]+}}
 // COMMONIR:      ret float [[TMP0]]
 float32_t test_vcvts_f32_s32(int32_t a) {
   return vcvts_f32_s32(a);
 }
 
 // COMMON-LABEL: test_vcvtd_f64_s64
 // UNCONSTRAINED: [[TMP0:%.*]] = sitofp i64 %a to double
 // CONSTRAINED:   [[TMP0:%.*]] = call double @llvm.experimental.constrained.sitofp.f64.i64(i64 %a, metadata !"round.tonearest", metadata !"fpexcept.strict")
-// CHECK-ASM:     scvtf d{{[0-9]}}, x{{[0-9]+}}
+// CHECK-ASM:     scvtf d{{[0-9]}}, {{d|x}}{{[0-9]+}}
 // COMMONIR:      ret double [[TMP0]]
 float64_t test_vcvtd_f64_s64(int64_t a) {
   return vcvtd_f64_s64(a);
 }
 
 // COMMON-LABEL: test_vcvts_f32_u32
 // UNCONSTRAINED: [[TMP0:%.*]] = uitofp i32 %a to float
 // CONSTRAINED:   [[TMP0:%.*]] = call float @llvm.experimental.constrained.uitofp.f32.i32(i32 %a, metadata !"round.tonearest", metadata !"fpexcept.strict")
-// CHECK-ASM:     ucvtf s{{[0-9]+}}, w{{[0-9]+}}
+// CHECK-ASM:     ucvtf s{{[0-9]+}}, {{s|w}}{{[0-9]+}}
 // COMMONIR:      ret float [[TMP0]]
 float32_t test_vcvts_f32_u32(uint32_t a) {
   return vcvts_f32_u32(a);
 }
 
 // XXX should verify the type of registers
 // COMMON-LABEL: test_vcvtd_f64_u64
 // UNCONSTRAINED: [[TMP0:%.*]] = uitofp i64 %a to double
 // CONSTRAINED:   [[TMP0:%.*]] = call double @llvm.experimental.constrained.uitofp.f64.i64(i64 %a, metadata !"round.tonearest", metadata !"fpexcept.strict")
-// CHECK-ASM:     ucvtf d{{[0-9]}}, x{{[0-9]+}}
+// CHECK-ASM:     ucvtf d{{[0-9]}}, {{d|x}}{{[0-9]+}}
 // COMMONIR:      ret double [[TMP0]]
 float64_t test_vcvtd_f64_u64(uint64_t a) {
   return vcvtd_f64_u64(a);
 }
 
 // COMMON-LABEL: test_vceqs_f32
 // UNCONSTRAINED: [[TMP0:%.*]] = fcmp oeq float %a, %b
 // CONSTRAINED:   [[TMP0:%.*]] = call i1 @llvm.experimental.constrained.fcmp.f32(float %a, float %b, metadata !"oeq", metadata !"fpexcept.strict")

 // COMMONIR:      ret i64 [[VCEQZ_I]]
 uint64_t test_vceqzd_f64(float64_t a) {
   return (uint64_t)vceqzd_f64(a);
 }
 
 // COMMON-LABEL: test_vcges_f32
 // UNCONSTRAINED: [[TMP0:%.*]] = fcmp oge float %a, %b
 // CONSTRAINED:   [[TMP0:%.*]] = call i1 @llvm.experimental.constrained.fcmps.f32(float %a, float %b, metadata !"oge", metadata !"fpexcept.strict")
-// CHECK-ASM:     fcmp s{{[0-9]+}}, s{{[0-9]+}}
+// CHECK-ASM-UNCONSTRAINED: fcmp s{{[0-9]+}}, s{{[0-9]+}}
+// CHECK-ASM-CONSTRAINED: fcmpe s{{[0-9]+}}, s{{[0-9]+}}
 // CHECK-ASM-NEXT:cset {{w[0-9]+}}, ge
 // COMMONIR:      [[VCMPD_I:%.*]] = sext i1 [[TMP0]] to i32
 // COMMONIR:      ret i32 [[VCMPD_I]]
 uint32_t test_vcges_f32(float32_t a, float32_t b) {
   return (uint32_t)vcges_f32(a, b);
 }
 
 // COMMON-LABEL: test_vcged_f64
 // UNCONSTRAINED: [[TMP0:%.*]] = fcmp oge double %a, %b
 // CONSTRAINED:   [[TMP0:%.*]] = call i1 @llvm.experimental.constrained.fcmps.f64(double %a, double %b, metadata !"oge", metadata !"fpexcept.strict")
-// CHECK-ASM:     fcmp d{{[0-9]+}}, d{{[0-9]+}}
+// CHECK-ASM-UNCONSTRAINED: fcmp d{{[0-9]+}}, d{{[0-9]+}}
+// CHECK-ASM-CONSTRAINED: fcmpe d{{[0-9]+}}, d{{[0-9]+}}
 // CHECK-ASM-NEXT:cset {{w[0-9]+}}, ge
 // COMMONIR:      [[VCMPD_I:%.*]] = sext i1 [[TMP0]] to i64
 // COMMONIR:      ret i64 [[VCMPD_I]]
 uint64_t test_vcged_f64(float64_t a, float64_t b) {
   return (uint64_t)vcged_f64(a, b);
 }
 
 // COMMON-LABEL: test_vcgezs_f32
 // UNCONSTRAINED: [[TMP0:%.*]] = fcmp oge float %a, 0.000000e+00
 // CONSTRAINED:   [[TMP0:%.*]] = call i1 @llvm.experimental.constrained.fcmps.f32(float %a, float 0.000000e+00, metadata !"oge", metadata !"fpexcept.strict")
-// CHECK-ASM:     fcmp s{{[0-9]+}}, #0.0
+// CHECK-ASM-UNCONSTRAINED: fcmp s{{[0-9]+}}, #0.0
+// CHECK-ASM-CONSTRAINED: fcmpe s{{[0-9]+}}, #0.0
 // CHECK-ASM-NEXT:cset {{w[0-9]+}}, ge
 // COMMONIR:      [[VCGEZ_I:%.*]] = sext i1 [[TMP0]] to i32
 // COMMONIR:      ret i32 [[VCGEZ_I]]
 uint32_t test_vcgezs_f32(float32_t a) {
   return (uint32_t)vcgezs_f32(a);
 }
 
 // COMMON-LABEL: test_vcgezd_f64
 // UNCONSTRAINED: [[TMP0:%.*]] = fcmp oge double %a, 0.000000e+00
 // CONSTRAINED:   [[TMP0:%.*]] = call i1 @llvm.experimental.constrained.fcmps.f64(double %a, double 0.000000e+00, metadata !"oge", metadata !"fpexcept.strict")
-// CHECK-ASM:     fcmp d{{[0-9]+}}, #0.0
+// CHECK-ASM-UNCONSTRAINED: fcmp d{{[0-9]+}}, #0.0
+// CHECK-ASM-CONSTRAINED: fcmpe d{{[0-9]+}}, #0.0
 // CHECK-ASM-NEXT:cset {{w[0-9]+}}, ge
 // COMMONIR:      [[VCGEZ_I:%.*]] = sext i1 [[TMP0]] to i64
 // COMMONIR:      ret i64 [[VCGEZ_I]]
 uint64_t test_vcgezd_f64(float64_t a) {
   return (uint64_t)vcgezd_f64(a);
 }
 
 // COMMON-LABEL: test_vcgts_f32
 // UNCONSTRAINED: [[TMP0:%.*]] = fcmp ogt float %a, %b
 // CONSTRAINED:   [[TMP0:%.*]] = call i1 @llvm.experimental.constrained.fcmps.f32(float %a, float %b, metadata !"ogt", metadata !"fpexcept.strict")
-// CHECK-ASM:     fcmp s{{[0-9]+}}, s{{[0-9]+}}
+// CHECK-ASM-UNCONSTRAINED: fcmp s{{[0-9]+}}, s{{[0-9]+}}
+// CHECK-ASM-CONSTRAINED: fcmpe s{{[0-9]+}}, s{{[0-9]+}}
 // CHECK-ASM-NEXT:cset {{w[0-9]+}}, gt
 // COMMONIR:      [[VCMPD_I:%.*]] = sext i1 [[TMP0]] to i32
 // COMMONIR:      ret i32 [[VCMPD_I]]
 uint32_t test_vcgts_f32(float32_t a, float32_t b) {
   return (uint32_t)vcgts_f32(a, b);
 }
 
 // COMMON-LABEL: test_vcgtd_f64
 // UNCONSTRAINED: [[TMP0:%.*]] = fcmp ogt double %a, %b
 // CONSTRAINED:   [[TMP0:%.*]] = call i1 @llvm.experimental.constrained.fcmps.f64(double %a, double %b, metadata !"ogt", metadata !"fpexcept.strict")
-// CHECK-ASM:     fcmp d{{[0-9]+}}, d{{[0-9]+}}
+// CHECK-ASM-UNCONSTRAINED: fcmp d{{[0-9]+}}, d{{[0-9]+}}
+// CHECK-ASM-CONSTRAINED: fcmpe d{{[0-9]+}}, d{{[0-9]+}}
 // CHECK-ASM-NEXT:cset {{w[0-9]+}}, gt
 // COMMONIR:      [[VCMPD_I:%.*]] = sext i1 [[TMP0]] to i64
 // COMMONIR:      ret i64 [[VCMPD_I]]
 uint64_t test_vcgtd_f64(float64_t a, float64_t b) {
   return (uint64_t)vcgtd_f64(a, b);
 }
 
 // COMMON-LABEL: test_vcgtzs_f32
 // UNCONSTRAINED: [[TMP0:%.*]] = fcmp ogt float %a, 0.000000e+00
 // CONSTRAINED:   [[TMP0:%.*]] = call i1 @llvm.experimental.constrained.fcmps.f32(float %a, float 0.000000e+00, metadata !"ogt", metadata !"fpexcept.strict")
-// CHECK-ASM:     fcmp s{{[0-9]+}}, #0.0
+// CHECK-ASM-UNCONSTRAINED: fcmp s{{[0-9]+}}, #0.0
+// CHECK-ASM-CONSTRAINED: fcmpe s{{[0-9]+}}, #0.0
 // CHECK-ASM-NEXT:cset {{w[0-9]+}}, gt
 // COMMONIR:      [[VCGTZ_I:%.*]] = sext i1 [[TMP0]] to i32
 // COMMONIR:      ret i32 [[VCGTZ_I]]
 uint32_t test_vcgtzs_f32(float32_t a) {
   return (uint32_t)vcgtzs_f32(a);
 }
 
 // COMMON-LABEL: test_vcgtzd_f64
 // UNCONSTRAINED: [[TMP0:%.*]] = fcmp ogt double %a, 0.000000e+00
 // CONSTRAINED:   [[TMP0:%.*]] = call i1 @llvm.experimental.constrained.fcmps.f64(double %a, double 0.000000e+00, metadata !"ogt", metadata !"fpexcept.strict")
-// CHECK-ASM:     fcmp d{{[0-9]+}}, #0.0
+// CHECK-ASM-UNCONSTRAINED: fcmp d{{[0-9]+}}, #0.0
+// CHECK-ASM-CONSTRAINED: fcmpe d{{[0-9]+}}, #0.0
 // CHECK-ASM-NEXT:cset {{w[0-9]+}}, gt
 // COMMONIR:      [[VCGTZ_I:%.*]] = sext i1 [[TMP0]] to i64
 // COMMONIR:      ret i64 [[VCGTZ_I]]
 uint64_t test_vcgtzd_f64(float64_t a) {
   return (uint64_t)vcgtzd_f64(a);
 }
 
 // COMMON-LABEL: test_vcles_f32
 // UNCONSTRAINED: [[TMP0:%.*]] = fcmp ole float %a, %b
 // CONSTRAINED:   [[TMP0:%.*]] = call i1 @llvm.experimental.constrained.fcmps.f32(float %a, float %b, metadata !"ole", metadata !"fpexcept.strict")
-// CHECK-ASM:     fcmp s{{[0-9]+}}, s{{[0-9]+}}
+// CHECK-ASM-UNCONSTRAINED: fcmp s{{[0-9]+}}, s{{[0-9]+}}
+// CHECK-ASM-CONSTRAINED: fcmpe s{{[0-9]+}}, s{{[0-9]+}}
 // CHECK-ASM-NEXT:cset {{w[0-9]+}}, ls
 // COMMONIR:      [[VCMPD_I:%.*]] = sext i1 [[TMP0]] to i32
 // COMMONIR:      ret i32 [[VCMPD_I]]
 uint32_t test_vcles_f32(float32_t a, float32_t b) {
   return (uint32_t)vcles_f32(a, b);
 }
 
 // COMMON-LABEL: test_vcled_f64
 // UNCONSTRAINED: [[TMP0:%.*]] = fcmp ole double %a, %b
 // CONSTRAINED:   [[TMP0:%.*]] = call i1 @llvm.experimental.constrained.fcmps.f64(double %a, double %b, metadata !"ole", metadata !"fpexcept.strict")
-// CHECK-ASM:     fcmp d{{[0-9]+}}, d{{[0-9]+}}
+// CHECK-ASM-UNCONSTRAINED: fcmp d{{[0-9]+}}, d{{[0-9]+}}
+// CHECK-ASM-CONSTRAINED: fcmpe d{{[0-9]+}}, d{{[0-9]+}}
 // CHECK-ASM-NEXT:cset {{w[0-9]+}}, ls
 // COMMONIR:      [[VCMPD_I:%.*]] = sext i1 [[TMP0]] to i64
 // COMMONIR:      ret i64 [[VCMPD_I]]
 uint64_t test_vcled_f64(float64_t a, float64_t b) {
   return (uint64_t)vcled_f64(a, b);
 }
 
 // COMMON-LABEL: test_vclezs_f32
 // UNCONSTRAINED: [[TMP0:%.*]] = fcmp ole float %a, 0.000000e+00
 // CONSTRAINED:   [[TMP0:%.*]] = call i1 @llvm.experimental.constrained.fcmps.f32(float %a, float 0.000000e+00, metadata !"ole", metadata !"fpexcept.strict")
-// CHECK-ASM:     fcmp s{{[0-9]+}}, #0.0
+// CHECK-ASM-UNCONSTRAINED: fcmp s{{[0-9]+}}, #0.0
+// CHECK-ASM-CONSTRAINED: fcmpe s{{[0-9]+}}, #0.0
 // CHECK-ASM-NEXT:cset {{w[0-9]+}}, ls
 // COMMONIR:      [[VCLEZ_I:%.*]] = sext i1 [[TMP0]] to i32
 // COMMONIR:      ret i32 [[VCLEZ_I]]
 uint32_t test_vclezs_f32(float32_t a) {
   return (uint32_t)vclezs_f32(a);
 }
 
 // COMMON-LABEL: test_vclezd_f64
 // UNCONSTRAINED: [[TMP0:%.*]] = fcmp ole double %a, 0.000000e+00
 // CONSTRAINED:   [[TMP0:%.*]] = call i1 @llvm.experimental.constrained.fcmps.f64(double %a, double 0.000000e+00, metadata !"ole", metadata !"fpexcept.strict")
-// CHECK-ASM:     fcmp d{{[0-9]+}}, #0.0
+// CHECK-ASM-UNCONSTRAINED: fcmp d{{[0-9]+}}, #0.0
+// CHECK-ASM-CONSTRAINED: fcmpe d{{[0-9]+}}, #0.0
 // CHECK-ASM-NEXT:cset {{w[0-9]+}}, ls
 // COMMONIR:      [[VCLEZ_I:%.*]] = sext i1 [[TMP0]] to i64
 // COMMONIR:      ret i64 [[VCLEZ_I]]
 uint64_t test_vclezd_f64(float64_t a) {
   return (uint64_t)vclezd_f64(a);
 }
 
 // COMMON-LABEL: test_vclts_f32
 // UNCONSTRAINED: [[TMP0:%.*]] = fcmp olt float %a, %b
 // CONSTRAINED:   [[TMP0:%.*]] = call i1 @llvm.experimental.constrained.fcmps.f32(float %a, float %b, metadata !"olt", metadata !"fpexcept.strict")
-// CHECK-ASM:     fcmp s{{[0-9]+}}, s{{[0-9]+}}
+// CHECK-ASM-UNCONSTRAINED: fcmp s{{[0-9]+}}, s{{[0-9]+}}
+// CHECK-ASM-CONSTRAINED: fcmpe s{{[0-9]+}}, s{{[0-9]+}}
 // CHECK-ASM-NEXT:cset {{w[0-9]+}}, mi
 // COMMONIR:      [[VCMPD_I:%.*]] = sext i1 [[TMP0]] to i32
 // COMMONIR:      ret i32 [[VCMPD_I]]
 uint32_t test_vclts_f32(float32_t a, float32_t b) {
   return (uint32_t)vclts_f32(a, b);
 }
 
 // COMMON-LABEL: test_vcltd_f64
 // UNCONSTRAINED: [[TMP0:%.*]] = fcmp olt double %a, %b
 // CONSTRAINED:   [[TMP0:%.*]] = call i1 @llvm.experimental.constrained.fcmps.f64(double %a, double %b, metadata !"olt", metadata !"fpexcept.strict")
-// CHECK-ASM:     fcmp d{{[0-9]+}}, d{{[0-9]+}}
+// CHECK-ASM-UNCONSTRAINED: fcmp d{{[0-9]+}}, d{{[0-9]+}}
+// CHECK-ASM-CONSTRAINED: fcmpe d{{[0-9]+}}, d{{[0-9]+}}
 // CHECK-ASM-NEXT:cset {{w[0-9]+}}, mi
 // COMMONIR:      [[VCMPD_I:%.*]] = sext i1 [[TMP0]] to i64
 // COMMONIR:      ret i64 [[VCMPD_I]]
 uint64_t test_vcltd_f64(float64_t a, float64_t b) {
   return (uint64_t)vcltd_f64(a, b);
 }
 
 // COMMON-LABEL: test_vcltzs_f32
 // UNCONSTRAINED: [[TMP0:%.*]] = fcmp olt float %a, 0.000000e+00
 // CONSTRAINED:   [[TMP0:%.*]] = call i1 @llvm.experimental.constrained.fcmps.f32(float %a, float 0.000000e+00, metadata !"olt", metadata !"fpexcept.strict")
-// CHECK-ASM:     fcmp s{{[0-9]+}}, #0.0
+// CHECK-ASM-UNCONSTRAINED: fcmp s{{[0-9]+}}, #0.0
+// CHECK-ASM-CONSTRAINED: fcmpe s{{[0-9]+}}, #0.0
 // CHECK-ASM-NEXT:cset {{w[0-9]+}}, mi
 // COMMONIR:      [[VCLTZ_I:%.*]] = sext i1 [[TMP0]] to i32
 // COMMONIR:      ret i32 [[VCLTZ_I]]
 uint32_t test_vcltzs_f32(float32_t a) {
   return (uint32_t)vcltzs_f32(a);
 }
 
 // COMMON-LABEL: test_vcltzd_f64
 // UNCONSTRAINED: [[TMP0:%.*]] = fcmp olt double %a, 0.000000e+00
 // CONSTRAINED:   [[TMP0:%.*]] = call i1 @llvm.experimental.constrained.fcmps.f64(double %a, double 0.000000e+00, metadata !"olt", metadata !"fpexcept.strict")
-// CHECK-ASM:     fcmp d{{[0-9]+}}, #0.0
+// CHECK-ASM-UNCONSTRAINED: fcmp d{{[0-9]+}}, #0.0
+// CHECK-ASM-CONSTRAINED: fcmpe d{{[0-9]+}}, #0.0
 // CHECK-ASM-NEXT:cset {{w[0-9]+}}, mi
 // COMMONIR:      [[VCLTZ_I:%.*]] = sext i1 [[TMP0]] to i64
 // COMMONIR:      ret i64 [[VCLTZ_I]]
 uint64_t test_vcltzd_f64(float64_t a) {
   return (uint64_t)vcltzd_f64(a);
 }
 
 // COMMON-LABEL: test_vadd_f64

 // CHECK-ASM:     fsub d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}
 // COMMONIR:      ret <1 x double> [[SUB_I]]
 float64x1_t test_vsub_f64(float64x1_t a, float64x1_t b) {
   return vsub_f64(a, b);
 }
 
 // COMMON-LABEL: test_vcvt_s64_f64
 // COMMONIR:      [[TMP0:%.*]] = bitcast <1 x double> %a to <8 x i8>
-// UNCONSTRAINED: [[TMP1:%.*]] = fptosi <1 x double> %a to <1 x i64>
-// CONSTRAINED:   [[TMP1:%.*]] = call <1 x i64> @llvm.experimental.constrained.fptosi.v1i64.v1f64(<1 x double> %a, metadata !"fpexcept.strict")
-// CHECK-ASM:     fcvtzs x{{[0-9]+}}, d{{[0-9]+}}
+// COMMONIR:      [[TMP1:%.*]] = call <1 x i64> @llvm.aarch64.neon.fcvtzs.v1i64.v1f64(<1 x double> %a)
+// CHECK-ASM:     fcvtzs d{{[0-9]+}}, d{{[0-9]+}}
 // COMMONIR:      ret <1 x i64> [[TMP1]]
 int64x1_t test_vcvt_s64_f64(float64x1_t a) {
   return vcvt_s64_f64(a);
 }
 
 // COMMON-LABEL: test_vcvt_u64_f64
 // COMMONIR:      [[TMP0:%.*]] = bitcast <1 x double> %a to <8 x i8>
-// UNCONSTRAINED: [[TMP1:%.*]] = fptoui <1 x double> %a to <1 x i64>
-// CONSTRAINED:   [[TMP1:%.*]] = call <1 x i64> @llvm.experimental.constrained.fptoui.v1i64.v1f64(<1 x double> %a, metadata !"fpexcept.strict")
-// CHECK-ASM:     fcvtzu x{{[0-9]+}}, d{{[0-9]+}}
+// COMMONIR:      [[TMP1:%.*]] = call <1 x i64> @llvm.aarch64.neon.fcvtzu.v1i64.v1f64(<1 x double> %a)
+// CHECK-ASM:     fcvtzu d{{[0-9]+}}, d{{[0-9]+}}
 // COMMONIR:      ret <1 x i64> [[TMP1]]
 uint64x1_t test_vcvt_u64_f64(float64x1_t a) {
   return vcvt_u64_f64(a);
 }
 
 // COMMON-LABEL: test_vcvt_f64_s64
 // COMMONIR:      [[TMP0:%.*]] = bitcast <1 x i64> %a to <8 x i8>
 // UNCONSTRAINED: [[VCVT_I:%.*]] = sitofp <1 x i64> %a to <1 x double>
 // CONSTRAINED:   [[VCVT_I:%.*]] = call <1 x double> @llvm.experimental.constrained.sitofp.v1f64.v1i64(<1 x i64> %a, metadata !"round.tonearest", metadata !"fpexcept.strict")
-// CHECK-ASM:     scvtf d{{[0-9]+}}, x{{[0-9]+}}
+// CHECK-ASM:     scvtf d{{[0-9]+}}, {{d|x}}{{[0-9]+}}
 // COMMONIR:      ret <1 x double> [[VCVT_I]]
 float64x1_t test_vcvt_f64_s64(int64x1_t a) {
   return vcvt_f64_s64(a);
 }
 
 // COMMON-LABEL: test_vcvt_f64_u64
 // COMMONIR:      [[TMP0:%.*]] = bitcast <1 x i64> %a to <8 x i8>
 // UNCONSTRAINED: [[VCVT_I:%.*]] = uitofp <1 x i64> %a to <1 x double>
 // CONSTRAINED:   [[VCVT_I:%.*]] = call <1 x double> @llvm.experimental.constrained.uitofp.v1f64.v1i64(<1 x i64> %a, metadata !"round.tonearest", metadata !"fpexcept.strict")
-// CHECK-ASM:     ucvtf d{{[0-9]+}}, x{{[0-9]+}}
+// CHECK-ASM:     ucvtf d{{[0-9]+}}, {{d|x}}{{[0-9]+}}
 // COMMONIR:      ret <1 x double> [[VCVT_I]]
 float64x1_t test_vcvt_f64_u64(uint64x1_t a) {
   return vcvt_f64_u64(a);
 }
 
 // COMMON-LABEL: test_vrnda_f64
 // COMMONIR:      [[TMP0:%.*]] = bitcast <1 x double> %a to <8 x i8>
 // UNCONSTRAINED: [[VRNDA1_I:%.*]] = call <1 x double> @llvm.round.v1f64(<1 x double> %a)