[PowerPC] Add the Power10 XS[MAX|MIN]CQP instruction.

[tingwang]

Summary

Add the Power 10 instruction XS[MAX|MIN]CQP.

This will enable the base instructions required by https://reviews.llvm.org/D117006.

[shchenz]

llvm/lib/Target/PowerPC/PPCInstrPrefix.td

2397

Should be put in the below block with Predicates = [IsISA3_1, HasVSX].

We also need one patch to move the above 4 VSX instructions to the same place.

[tingwang]

llvm/lib/Target/PowerPC/PPCInstrPrefix.td

2397

Sure. I will move the two XS[MAX|MIN]CQP under predicate [IsISA3_1, HasVSX]. Thanks!

Given what it was mentioned in D117006's code review that these Power10 instructions are put here temporarily, they probably will be relocated somewhere else in TD files once their locations are finally decided. Shall we leave them here for the moment?

[tingwang]

llvm/lib/Target/PowerPC/PPCInstrPrefix.td

2397

Sorry, it was ambiguous. I mean shall we leave the other 4 here for the moment?

[shchenz]

llvm/lib/Target/PowerPC/PPCInstrPrefix.td

2397

Yeah, leaving them for now sounds good to me.

[tingwang]

Move the two instructions XS[MAX|MIN]CQP under predicate [IsISA3_1, HasVSX]

[shchenz]

LGTM. Thanks for adding the instructions.

[amyk]

LGTM, too.

llvm/lib/Target/PowerPC/P10InstrResources.td

def : InstRW<[P10W_DX_5C, P10W_DISP_ANY, P10DX_Read, P10DX_Read],
     VADDUQM,
     VMUL10ECUQ,
     VMUL10EUQ,
     VSUBCUQ,
     VSUBUQM,
     XSCMPEXPQP,
     XSCMPOQP,
     XSCMPUQP,
+    XSMAXCQP,
+    XSMINCQP,
     XSTSTDCQP,
     XXGENPCVBM
 )>;
 
 // 5 Cycles Fixed-Point and BCD operations, 3 input operands
 def : InstRW<[P10W_DX_5C, P10W_DISP_ANY, P10DX_Read, P10DX_Read, P10DX_Read],
       (instrs
     BCDADD_rec,

llvm/lib/Target/PowerPC/PPCInstrPrefix.td

let Predicates = [IsISA3_1] in {
   def VSLQ : VX1_VT5_VA5_VB5<261, "vslq", []>;
   def VSRAQ : VX1_VT5_VA5_VB5<773, "vsraq", []>;
   def VSRQ : VX1_VT5_VA5_VB5<517, "vsrq", []>;
   def VRLQ : VX1_VT5_VA5_VB5<5, "vrlq", []>;
   def XSCVQPUQZ : X_VT5_XO5_VB5<63, 0, 836, "xscvqpuqz", []>;
   def XSCVQPSQZ : X_VT5_XO5_VB5<63, 8, 836, "xscvqpsqz", []>;
   def XSCVUQQP : X_VT5_XO5_VB5<63, 3, 836, "xscvuqqp", []>;
   def XSCVSQQP : X_VT5_XO5_VB5<63, 11, 836, "xscvsqqp", []>;
+  def XSMAXCQP : X_VT5_VA5_VB5<63, 676, "xsmaxcqp", []>;
+  def XSMINCQP : X_VT5_VA5_VB5<63, 740, "xsmincqp", []>;
 }
 
 let Predicates = [IsISA3_1, HasVSX] in {
   def XVCVSPBF16 : XX2_XT6_XO5_XB6<60, 17, 475, "xvcvspbf16", vsrc, []>;
   def XVCVBF16SPN : XX2_XT6_XO5_XB6<60, 16, 475, "xvcvbf16spn", vsrc, []>;
 }
 
 // Multiclass defining patterns for Set Boolean Extension Reverse Instructions.

llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-ISA31.txt

 0xfd 0x08 0xe6 0x88
 
 # CHECK: xscvuqqp 8, 28
 0xfd 0x03 0xe6 0x88
 
 # CHECK: xscvsqqp 8, 28
 0xfd 0xb 0xe6 0x88
 
+# CHECK: xsmaxcqp 2, 2, 3
+0xfc 0x42 0x1d 0x48
+
+# CHECK: xsmincqp 2, 2, 3
+0xfc 0x42 0x1d 0xc8
+
 # CHECK: vstribr 2, 2
 0x10 0x41 0x10 0x0d
 
 # CHECK: vstribl 2, 2
 0x10 0x40 0x10 0x0d
 
 # CHECK: vstrihr 2, 2
 0x10 0x43 0x10 0x0d

llvm/test/MC/PowerPC/ppc64-encoding-ISA31.s

 # CHECK-LE: xscvqpsqz 8, 28                       # encoding: [0x88,0xe6,0x08,0xfd]
             xscvqpsqz 8, 28
 # CHECK-BE: xscvuqqp 8, 28                        # encoding: [0xfd,0x03,0xe6,0x88]
 # CHECK-LE: xscvuqqp 8, 28                        # encoding: [0x88,0xe6,0x03,0xfd]
             xscvuqqp 8, 28
 # CHECK-BE: xscvsqqp 8, 28                        # encoding: [0xfd,0x0b,0xe6,0x88]
 # CHECK-LE: xscvsqqp 8, 28                        # encoding: [0x88,0xe6,0x0b,0xfd]
             xscvsqqp 8, 28
+# CHECK-BE: xsmaxcqp 2, 2, 3                      # encoding: [0xfc,0x42,0x1d,0x48]
+# CHECK-LE: xsmaxcqp 2, 2, 3                      # encoding: [0x48,0x1d,0x42,0xfc]
+            xsmaxcqp 2, 2, 3
+# CHECK-BE: xsmincqp 2, 2, 3                      # encoding: [0xfc,0x42,0x1d,0xc8]
+# CHECK-LE: xsmincqp 2, 2, 3                      # encoding: [0xc8,0x1d,0x42,0xfc]
+            xsmincqp 2, 2, 3
 # CHECK-BE: vstribr 2, 2                          # encoding: [0x10,0x41,0x10,0x0d]
 # CHECK-LE: vstribr 2, 2                          # encoding: [0x0d,0x10,0x41,0x10]
             vstribr 2, 2
 # CHECK-BE: vstribl 2, 2                          # encoding: [0x10,0x40,0x10,0x0d]
 # CHECK-LE: vstribl 2, 2                          # encoding: [0x0d,0x10,0x40,0x10]
             vstribl 2, 2
 # CHECK-BE: vstrihr 2, 2                          # encoding: [0x10,0x43,0x10,0x0d]
 # CHECK-LE: vstrihr 2, 2                          # encoding: [0x0d,0x10,0x43,0x10]