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Differential D117968

[RISCV] Merge some rvv intrinsic test cases that only differ by XLen type.
ClosedPublic

Authored by craig.topper on Jan 22 2022, 1:06 PM.

Details

Reviewers
frasercrmck
khchen
eopXD
arcbbb
kito-cheng
Commits
rG85e42db1b6db: [RISCV] Merge some rvv intrinsic test cases that only differ by XLen type.
Summary

Instead of having a test for i32 XLen and i64 XLen, use sed to
replace iXLen with i32/i64 before running llc.

This change updates tests for intrinsics that operate exclusively
on mask values. It removes over 4000 lines worth of test content.
More merging will come in future changes.

I would have just committed this, but I didn't want to block the patch to "experimental" from the command lines. I'll rebase after that.

Diff Detail

Event Timeline

craig.topper created this revision.Jan 22 2022, 1:06 PM
Herald added subscribers: VincentWu, luke957, achieveartificialintelligence and 24 others. · View Herald TranscriptJan 22 2022, 1:06 PM
craig.topper requested review of this revision.Jan 22 2022, 1:06 PM
Herald added a project: Restricted Project. · View Herald TranscriptJan 22 2022, 1:06 PM
Herald added a subscriber: MaskRay. · View Herald Transcript
craig.topper edited the summary of this revision. (Show Details)Jan 22 2022, 1:07 PM
Harbormaster completed remote builds in B145045: Diff 402257.Jan 22 2022, 2:03 PM
eopXD accepted this revision.Jan 22 2022, 8:36 PM

LGTM. Maybe I can also help on reducing test cases for other test cases since it might be pretty tedious.

This revision is now accepted and ready to land.Jan 22 2022, 8:36 PM
Closed by commit rG85e42db1b6db: [RISCV] Merge some rvv intrinsic test cases that only differ by XLen type. (authored by craig.topper). · Explain WhyJan 22 2022, 10:17 PM
This revision was automatically updated to reflect the committed changes.
craig.topper added a commit: rG85e42db1b6db: [RISCV] Merge some rvv intrinsic test cases that only differ by XLen type..

Revision Contents

Diff 402291

llvm/test/CodeGen/RISCV/rvv/vcpop-rv32.ll

  • This file was deleted.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+v,+f -verify-machineinstrs \
; RUN: < %s | FileCheck %s
declare i32 @llvm.riscv.vcpop.i32.nxv1i1(
<vscale x 1 x i1>,
i32);
define i32 @intrinsic_vcpop_m_i32_nxv1i1(<vscale x 1 x i1> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vcpop_m_i32_nxv1i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
; CHECK-NEXT: vcpop.m a0, v0
; CHECK-NEXT: ret
entry:
%a = call i32 @llvm.riscv.vcpop.i32.nxv1i1(
<vscale x 1 x i1> %0,
i32 %1)
ret i32 %a
}
declare i32 @llvm.riscv.vcpop.mask.i32.nxv1i1(
<vscale x 1 x i1>,
<vscale x 1 x i1>,
i32);
define i32 @intrinsic_vcpop_mask_m_i32_nxv1i1(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vcpop_mask_m_i32_nxv1i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v9, v0
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vcpop.m a0, v9, v0.t
; CHECK-NEXT: ret
entry:
%a = call i32 @llvm.riscv.vcpop.mask.i32.nxv1i1(
<vscale x 1 x i1> %0,
<vscale x 1 x i1> %1,
i32 %2)
ret i32 %a
}
declare i32 @llvm.riscv.vcpop.i32.nxv2i1(
<vscale x 2 x i1>,
i32);
define i32 @intrinsic_vcpop_m_i32_nxv2i1(<vscale x 2 x i1> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vcpop_m_i32_nxv2i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
; CHECK-NEXT: vcpop.m a0, v0
; CHECK-NEXT: ret
entry:
%a = call i32 @llvm.riscv.vcpop.i32.nxv2i1(
<vscale x 2 x i1> %0,
i32 %1)
ret i32 %a
}
declare i32 @llvm.riscv.vcpop.mask.i32.nxv2i1(
<vscale x 2 x i1>,
<vscale x 2 x i1>,
i32);
define i32 @intrinsic_vcpop_mask_m_i32_nxv2i1(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vcpop_mask_m_i32_nxv2i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v9, v0
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vcpop.m a0, v9, v0.t
; CHECK-NEXT: ret
entry:
%a = call i32 @llvm.riscv.vcpop.mask.i32.nxv2i1(
<vscale x 2 x i1> %0,
<vscale x 2 x i1> %1,
i32 %2)
ret i32 %a
}
declare i32 @llvm.riscv.vcpop.i32.nxv4i1(
<vscale x 4 x i1>,
i32);
define i32 @intrinsic_vcpop_m_i32_nxv4i1(<vscale x 4 x i1> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vcpop_m_i32_nxv4i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
; CHECK-NEXT: vcpop.m a0, v0
; CHECK-NEXT: ret
entry:
%a = call i32 @llvm.riscv.vcpop.i32.nxv4i1(
<vscale x 4 x i1> %0,
i32 %1)
ret i32 %a
}
declare i32 @llvm.riscv.vcpop.mask.i32.nxv4i1(
<vscale x 4 x i1>,
<vscale x 4 x i1>,
i32);
define i32 @intrinsic_vcpop_mask_m_i32_nxv4i1(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vcpop_mask_m_i32_nxv4i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v9, v0
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vcpop.m a0, v9, v0.t
; CHECK-NEXT: ret
entry:
%a = call i32 @llvm.riscv.vcpop.mask.i32.nxv4i1(
<vscale x 4 x i1> %0,
<vscale x 4 x i1> %1,
i32 %2)
ret i32 %a
}
declare i32 @llvm.riscv.vcpop.i32.nxv8i1(
<vscale x 8 x i1>,
i32);
define i32 @intrinsic_vcpop_m_i32_nxv8i1(<vscale x 8 x i1> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vcpop_m_i32_nxv8i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
; CHECK-NEXT: vcpop.m a0, v0
; CHECK-NEXT: ret
entry:
%a = call i32 @llvm.riscv.vcpop.i32.nxv8i1(
<vscale x 8 x i1> %0,
i32 %1)
ret i32 %a
}
declare i32 @llvm.riscv.vcpop.mask.i32.nxv8i1(
<vscale x 8 x i1>,
<vscale x 8 x i1>,
i32);
define i32 @intrinsic_vcpop_mask_m_i32_nxv8i1(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vcpop_mask_m_i32_nxv8i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v9, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vcpop.m a0, v9, v0.t
; CHECK-NEXT: ret
entry:
%a = call i32 @llvm.riscv.vcpop.mask.i32.nxv8i1(
<vscale x 8 x i1> %0,
<vscale x 8 x i1> %1,
i32 %2)
ret i32 %a
}
declare i32 @llvm.riscv.vcpop.i32.nxv16i1(
<vscale x 16 x i1>,
i32);
define i32 @intrinsic_vcpop_m_i32_nxv16i1(<vscale x 16 x i1> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vcpop_m_i32_nxv16i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
; CHECK-NEXT: vcpop.m a0, v0
; CHECK-NEXT: ret
entry:
%a = call i32 @llvm.riscv.vcpop.i32.nxv16i1(
<vscale x 16 x i1> %0,
i32 %1)
ret i32 %a
}
declare i32 @llvm.riscv.vcpop.mask.i32.nxv16i1(
<vscale x 16 x i1>,
<vscale x 16 x i1>,
i32);
define i32 @intrinsic_vcpop_mask_m_i32_nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vcpop_mask_m_i32_nxv16i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v9, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vcpop.m a0, v9, v0.t
; CHECK-NEXT: ret
entry:
%a = call i32 @llvm.riscv.vcpop.mask.i32.nxv16i1(
<vscale x 16 x i1> %0,
<vscale x 16 x i1> %1,
i32 %2)
ret i32 %a
}
declare i32 @llvm.riscv.vcpop.i32.nxv32i1(
<vscale x 32 x i1>,
i32);
define i32 @intrinsic_vcpop_m_i32_nxv32i1(<vscale x 32 x i1> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vcpop_m_i32_nxv32i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
; CHECK-NEXT: vcpop.m a0, v0
; CHECK-NEXT: ret
entry:
%a = call i32 @llvm.riscv.vcpop.i32.nxv32i1(
<vscale x 32 x i1> %0,
i32 %1)
ret i32 %a
}
declare i32 @llvm.riscv.vcpop.mask.i32.nxv32i1(
<vscale x 32 x i1>,
<vscale x 32 x i1>,
i32);
define i32 @intrinsic_vcpop_mask_m_i32_nxv32i1(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vcpop_mask_m_i32_nxv32i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v9, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vcpop.m a0, v9, v0.t
; CHECK-NEXT: ret
entry:
%a = call i32 @llvm.riscv.vcpop.mask.i32.nxv32i1(
<vscale x 32 x i1> %0,
<vscale x 32 x i1> %1,
i32 %2)
ret i32 %a
}
declare i32 @llvm.riscv.vcpop.i32.nxv64i1(
<vscale x 64 x i1>,
i32);
define i32 @intrinsic_vcpop_m_i32_nxv64i1(<vscale x 64 x i1> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vcpop_m_i32_nxv64i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu
; CHECK-NEXT: vcpop.m a0, v0
; CHECK-NEXT: ret
entry:
%a = call i32 @llvm.riscv.vcpop.i32.nxv64i1(
<vscale x 64 x i1> %0,
i32 %1)
ret i32 %a
}
declare i32 @llvm.riscv.vcpop.mask.i32.nxv64i1(
<vscale x 64 x i1>,
<vscale x 64 x i1>,
i32);
define i32 @intrinsic_vcpop_mask_m_i32_nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vcpop_mask_m_i32_nxv64i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v9, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu
; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vcpop.m a0, v9, v0.t
; CHECK-NEXT: ret
entry:
%a = call i32 @llvm.riscv.vcpop.mask.i32.nxv64i1(
<vscale x 64 x i1> %0,
<vscale x 64 x i1> %1,
i32 %2)
ret i32 %a
}

llvm/test/CodeGen/RISCV/rvv/vcpop-rv64.ll

  • This file was deleted.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+v,+d -verify-machineinstrs \
; RUN: < %s | FileCheck %s
declare i64 @llvm.riscv.vcpop.i64.nxv1i1(
<vscale x 1 x i1>,
i64);
define i64 @intrinsic_vcpop_m_i64_nxv1i1(<vscale x 1 x i1> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vcpop_m_i64_nxv1i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
; CHECK-NEXT: vcpop.m a0, v0
; CHECK-NEXT: ret
entry:
%a = call i64 @llvm.riscv.vcpop.i64.nxv1i1(
<vscale x 1 x i1> %0,
i64 %1)
ret i64 %a
}
declare i64 @llvm.riscv.vcpop.mask.i64.nxv1i1(
<vscale x 1 x i1>,
<vscale x 1 x i1>,
i64);
define i64 @intrinsic_vcpop_mask_m_i64_nxv1i1(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vcpop_mask_m_i64_nxv1i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v9, v0
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vcpop.m a0, v9, v0.t
; CHECK-NEXT: ret
entry:
%a = call i64 @llvm.riscv.vcpop.mask.i64.nxv1i1(
<vscale x 1 x i1> %0,
<vscale x 1 x i1> %1,
i64 %2)
ret i64 %a
}
declare i64 @llvm.riscv.vcpop.i64.nxv2i1(
<vscale x 2 x i1>,
i64);
define i64 @intrinsic_vcpop_m_i64_nxv2i1(<vscale x 2 x i1> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vcpop_m_i64_nxv2i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
; CHECK-NEXT: vcpop.m a0, v0
; CHECK-NEXT: ret
entry:
%a = call i64 @llvm.riscv.vcpop.i64.nxv2i1(
<vscale x 2 x i1> %0,
i64 %1)
ret i64 %a
}
declare i64 @llvm.riscv.vcpop.mask.i64.nxv2i1(
<vscale x 2 x i1>,
<vscale x 2 x i1>,
i64);
define i64 @intrinsic_vcpop_mask_m_i64_nxv2i1(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vcpop_mask_m_i64_nxv2i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v9, v0
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vcpop.m a0, v9, v0.t
; CHECK-NEXT: ret
entry:
%a = call i64 @llvm.riscv.vcpop.mask.i64.nxv2i1(
<vscale x 2 x i1> %0,
<vscale x 2 x i1> %1,
i64 %2)
ret i64 %a
}
declare i64 @llvm.riscv.vcpop.i64.nxv4i1(
<vscale x 4 x i1>,
i64);
define i64 @intrinsic_vcpop_m_i64_nxv4i1(<vscale x 4 x i1> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vcpop_m_i64_nxv4i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
; CHECK-NEXT: vcpop.m a0, v0
; CHECK-NEXT: ret
entry:
%a = call i64 @llvm.riscv.vcpop.i64.nxv4i1(
<vscale x 4 x i1> %0,
i64 %1)
ret i64 %a
}
declare i64 @llvm.riscv.vcpop.mask.i64.nxv4i1(
<vscale x 4 x i1>,
<vscale x 4 x i1>,
i64);
define i64 @intrinsic_vcpop_mask_m_i64_nxv4i1(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vcpop_mask_m_i64_nxv4i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v9, v0
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vcpop.m a0, v9, v0.t
; CHECK-NEXT: ret
entry:
%a = call i64 @llvm.riscv.vcpop.mask.i64.nxv4i1(
<vscale x 4 x i1> %0,
<vscale x 4 x i1> %1,
i64 %2)
ret i64 %a
}
declare i64 @llvm.riscv.vcpop.i64.nxv8i1(
<vscale x 8 x i1>,
i64);
define i64 @intrinsic_vcpop_m_i64_nxv8i1(<vscale x 8 x i1> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vcpop_m_i64_nxv8i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
; CHECK-NEXT: vcpop.m a0, v0
; CHECK-NEXT: ret
entry:
%a = call i64 @llvm.riscv.vcpop.i64.nxv8i1(
<vscale x 8 x i1> %0,
i64 %1)
ret i64 %a
}
declare i64 @llvm.riscv.vcpop.mask.i64.nxv8i1(
<vscale x 8 x i1>,
<vscale x 8 x i1>,
i64);
define i64 @intrinsic_vcpop_mask_m_i64_nxv8i1(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vcpop_mask_m_i64_nxv8i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v9, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vcpop.m a0, v9, v0.t
; CHECK-NEXT: ret
entry:
%a = call i64 @llvm.riscv.vcpop.mask.i64.nxv8i1(
<vscale x 8 x i1> %0,
<vscale x 8 x i1> %1,
i64 %2)
ret i64 %a
}
declare i64 @llvm.riscv.vcpop.i64.nxv16i1(
<vscale x 16 x i1>,
i64);
define i64 @intrinsic_vcpop_m_i64_nxv16i1(<vscale x 16 x i1> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vcpop_m_i64_nxv16i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
; CHECK-NEXT: vcpop.m a0, v0
; CHECK-NEXT: ret
entry:
%a = call i64 @llvm.riscv.vcpop.i64.nxv16i1(
<vscale x 16 x i1> %0,
i64 %1)
ret i64 %a
}
declare i64 @llvm.riscv.vcpop.mask.i64.nxv16i1(
<vscale x 16 x i1>,
<vscale x 16 x i1>,
i64);
define i64 @intrinsic_vcpop_mask_m_i64_nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vcpop_mask_m_i64_nxv16i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v9, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vcpop.m a0, v9, v0.t
; CHECK-NEXT: ret
entry:
%a = call i64 @llvm.riscv.vcpop.mask.i64.nxv16i1(
<vscale x 16 x i1> %0,
<vscale x 16 x i1> %1,
i64 %2)
ret i64 %a
}
declare i64 @llvm.riscv.vcpop.i64.nxv32i1(
<vscale x 32 x i1>,
i64);
define i64 @intrinsic_vcpop_m_i64_nxv32i1(<vscale x 32 x i1> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vcpop_m_i64_nxv32i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
; CHECK-NEXT: vcpop.m a0, v0
; CHECK-NEXT: ret
entry:
%a = call i64 @llvm.riscv.vcpop.i64.nxv32i1(
<vscale x 32 x i1> %0,
i64 %1)
ret i64 %a
}
declare i64 @llvm.riscv.vcpop.mask.i64.nxv32i1(
<vscale x 32 x i1>,
<vscale x 32 x i1>,
i64);
define i64 @intrinsic_vcpop_mask_m_i64_nxv32i1(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vcpop_mask_m_i64_nxv32i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v9, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vcpop.m a0, v9, v0.t
; CHECK-NEXT: ret
entry:
%a = call i64 @llvm.riscv.vcpop.mask.i64.nxv32i1(
<vscale x 32 x i1> %0,
<vscale x 32 x i1> %1,
i64 %2)
ret i64 %a
}
declare i64 @llvm.riscv.vcpop.i64.nxv64i1(
<vscale x 64 x i1>,
i64);
define i64 @intrinsic_vcpop_m_i64_nxv64i1(<vscale x 64 x i1> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vcpop_m_i64_nxv64i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu
; CHECK-NEXT: vcpop.m a0, v0
; CHECK-NEXT: ret
entry:
%a = call i64 @llvm.riscv.vcpop.i64.nxv64i1(
<vscale x 64 x i1> %0,
i64 %1)
ret i64 %a
}
declare i64 @llvm.riscv.vcpop.mask.i64.nxv64i1(
<vscale x 64 x i1>,
<vscale x 64 x i1>,
i64);
define i64 @intrinsic_vcpop_mask_m_i64_nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vcpop_mask_m_i64_nxv64i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v9, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu
; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vcpop.m a0, v9, v0.t
; CHECK-NEXT: ret
entry:
%a = call i64 @llvm.riscv.vcpop.mask.i64.nxv64i1(
<vscale x 64 x i1> %0,
<vscale x 64 x i1> %1,
i64 %2)
ret i64 %a
}

llvm/test/CodeGen/RISCV/rvv/vcpop.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v \
; RUN: -verify-machineinstrs | FileCheck %s
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v \
; RUN: -verify-machineinstrs | FileCheck %s
declare iXLen @llvm.riscv.vcpop.iXLen.nxv1i1(
<vscale x 1 x i1>,
iXLen);
define iXLen @intrinsic_vcpop_m_nxv1i1(<vscale x 1 x i1> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vcpop_m_nxv1i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
; CHECK-NEXT: vcpop.m a0, v0
; CHECK-NEXT: ret
entry:
%a = call iXLen @llvm.riscv.vcpop.iXLen.nxv1i1(
<vscale x 1 x i1> %0,
iXLen %1)
ret iXLen %a
}
declare iXLen @llvm.riscv.vcpop.mask.iXLen.nxv1i1(
<vscale x 1 x i1>,
<vscale x 1 x i1>,
iXLen);
define iXLen @intrinsic_vcpop_mask_m_nxv1i1(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vcpop_mask_m_nxv1i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v9, v0
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vcpop.m a0, v9, v0.t
; CHECK-NEXT: ret
entry:
%a = call iXLen @llvm.riscv.vcpop.mask.iXLen.nxv1i1(
<vscale x 1 x i1> %0,
<vscale x 1 x i1> %1,
iXLen %2)
ret iXLen %a
}
declare iXLen @llvm.riscv.vcpop.iXLen.nxv2i1(
<vscale x 2 x i1>,
iXLen);
define iXLen @intrinsic_vcpop_m_nxv2i1(<vscale x 2 x i1> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vcpop_m_nxv2i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
; CHECK-NEXT: vcpop.m a0, v0
; CHECK-NEXT: ret
entry:
%a = call iXLen @llvm.riscv.vcpop.iXLen.nxv2i1(
<vscale x 2 x i1> %0,
iXLen %1)
ret iXLen %a
}
declare iXLen @llvm.riscv.vcpop.mask.iXLen.nxv2i1(
<vscale x 2 x i1>,
<vscale x 2 x i1>,
iXLen);
define iXLen @intrinsic_vcpop_mask_m_nxv2i1(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vcpop_mask_m_nxv2i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v9, v0
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vcpop.m a0, v9, v0.t
; CHECK-NEXT: ret
entry:
%a = call iXLen @llvm.riscv.vcpop.mask.iXLen.nxv2i1(
<vscale x 2 x i1> %0,
<vscale x 2 x i1> %1,
iXLen %2)
ret iXLen %a
}
declare iXLen @llvm.riscv.vcpop.iXLen.nxv4i1(
<vscale x 4 x i1>,
iXLen);
define iXLen @intrinsic_vcpop_m_nxv4i1(<vscale x 4 x i1> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vcpop_m_nxv4i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
; CHECK-NEXT: vcpop.m a0, v0
; CHECK-NEXT: ret
entry:
%a = call iXLen @llvm.riscv.vcpop.iXLen.nxv4i1(
<vscale x 4 x i1> %0,
iXLen %1)
ret iXLen %a
}
declare iXLen @llvm.riscv.vcpop.mask.iXLen.nxv4i1(
<vscale x 4 x i1>,
<vscale x 4 x i1>,
iXLen);
define iXLen @intrinsic_vcpop_mask_m_nxv4i1(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vcpop_mask_m_nxv4i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v9, v0
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vcpop.m a0, v9, v0.t
; CHECK-NEXT: ret
entry:
%a = call iXLen @llvm.riscv.vcpop.mask.iXLen.nxv4i1(
<vscale x 4 x i1> %0,
<vscale x 4 x i1> %1,
iXLen %2)
ret iXLen %a
}
declare iXLen @llvm.riscv.vcpop.iXLen.nxv8i1(
<vscale x 8 x i1>,
iXLen);
define iXLen @intrinsic_vcpop_m_nxv8i1(<vscale x 8 x i1> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vcpop_m_nxv8i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
; CHECK-NEXT: vcpop.m a0, v0
; CHECK-NEXT: ret
entry:
%a = call iXLen @llvm.riscv.vcpop.iXLen.nxv8i1(
<vscale x 8 x i1> %0,
iXLen %1)
ret iXLen %a
}
declare iXLen @llvm.riscv.vcpop.mask.iXLen.nxv8i1(
<vscale x 8 x i1>,
<vscale x 8 x i1>,
iXLen);
define iXLen @intrinsic_vcpop_mask_m_nxv8i1(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vcpop_mask_m_nxv8i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v9, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vcpop.m a0, v9, v0.t
; CHECK-NEXT: ret
entry:
%a = call iXLen @llvm.riscv.vcpop.mask.iXLen.nxv8i1(
<vscale x 8 x i1> %0,
<vscale x 8 x i1> %1,
iXLen %2)
ret iXLen %a
}
declare iXLen @llvm.riscv.vcpop.iXLen.nxv16i1(
<vscale x 16 x i1>,
iXLen);
define iXLen @intrinsic_vcpop_m_nxv16i1(<vscale x 16 x i1> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vcpop_m_nxv16i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
; CHECK-NEXT: vcpop.m a0, v0
; CHECK-NEXT: ret
entry:
%a = call iXLen @llvm.riscv.vcpop.iXLen.nxv16i1(
<vscale x 16 x i1> %0,
iXLen %1)
ret iXLen %a
}
declare iXLen @llvm.riscv.vcpop.mask.iXLen.nxv16i1(
<vscale x 16 x i1>,
<vscale x 16 x i1>,
iXLen);
define iXLen @intrinsic_vcpop_mask_m_nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vcpop_mask_m_nxv16i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v9, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vcpop.m a0, v9, v0.t
; CHECK-NEXT: ret
entry:
%a = call iXLen @llvm.riscv.vcpop.mask.iXLen.nxv16i1(
<vscale x 16 x i1> %0,
<vscale x 16 x i1> %1,
iXLen %2)
ret iXLen %a
}
declare iXLen @llvm.riscv.vcpop.iXLen.nxv32i1(
<vscale x 32 x i1>,
iXLen);
define iXLen @intrinsic_vcpop_m_nxv32i1(<vscale x 32 x i1> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vcpop_m_nxv32i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
; CHECK-NEXT: vcpop.m a0, v0
; CHECK-NEXT: ret
entry:
%a = call iXLen @llvm.riscv.vcpop.iXLen.nxv32i1(
<vscale x 32 x i1> %0,
iXLen %1)
ret iXLen %a
}
declare iXLen @llvm.riscv.vcpop.mask.iXLen.nxv32i1(
<vscale x 32 x i1>,
<vscale x 32 x i1>,
iXLen);
define iXLen @intrinsic_vcpop_mask_m_nxv32i1(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vcpop_mask_m_nxv32i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v9, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vcpop.m a0, v9, v0.t
; CHECK-NEXT: ret
entry:
%a = call iXLen @llvm.riscv.vcpop.mask.iXLen.nxv32i1(
<vscale x 32 x i1> %0,
<vscale x 32 x i1> %1,
iXLen %2)
ret iXLen %a
}
declare iXLen @llvm.riscv.vcpop.iXLen.nxv64i1(
<vscale x 64 x i1>,
iXLen);
define iXLen @intrinsic_vcpop_m_nxv64i1(<vscale x 64 x i1> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vcpop_m_nxv64i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu
; CHECK-NEXT: vcpop.m a0, v0
; CHECK-NEXT: ret
entry:
%a = call iXLen @llvm.riscv.vcpop.iXLen.nxv64i1(
<vscale x 64 x i1> %0,
iXLen %1)
ret iXLen %a
}
declare iXLen @llvm.riscv.vcpop.mask.iXLen.nxv64i1(
<vscale x 64 x i1>,
<vscale x 64 x i1>,
iXLen);
define iXLen @intrinsic_vcpop_mask_m_nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vcpop_mask_m_nxv64i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v9, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu
; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vcpop.m a0, v9, v0.t
; CHECK-NEXT: ret
entry:
%a = call iXLen @llvm.riscv.vcpop.mask.iXLen.nxv64i1(
<vscale x 64 x i1> %0,
<vscale x 64 x i1> %1,
iXLen %2)
ret iXLen %a
}

llvm/test/CodeGen/RISCV/rvv/vfirst-rv32.ll

  • This file was deleted.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+v,+f -verify-machineinstrs \
; RUN: < %s | FileCheck %s
declare i32 @llvm.riscv.vfirst.i32.nxv1i1(
<vscale x 1 x i1>,
i32);
define i32 @intrinsic_vfirst_m_i32_nxv1i1(<vscale x 1 x i1> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vfirst_m_i32_nxv1i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
; CHECK-NEXT: vfirst.m a0, v0
; CHECK-NEXT: ret
entry:
%a = call i32 @llvm.riscv.vfirst.i32.nxv1i1(
<vscale x 1 x i1> %0,
i32 %1)
ret i32 %a
}
declare i32 @llvm.riscv.vfirst.mask.i32.nxv1i1(
<vscale x 1 x i1>,
<vscale x 1 x i1>,
i32);
define i32 @intrinsic_vfirst_mask_m_i32_nxv1i1(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vfirst_mask_m_i32_nxv1i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v9, v0
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vfirst.m a0, v9, v0.t
; CHECK-NEXT: ret
entry:
%a = call i32 @llvm.riscv.vfirst.mask.i32.nxv1i1(
<vscale x 1 x i1> %0,
<vscale x 1 x i1> %1,
i32 %2)
ret i32 %a
}
declare i32 @llvm.riscv.vfirst.i32.nxv2i1(
<vscale x 2 x i1>,
i32);
define i32 @intrinsic_vfirst_m_i32_nxv2i1(<vscale x 2 x i1> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vfirst_m_i32_nxv2i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
; CHECK-NEXT: vfirst.m a0, v0
; CHECK-NEXT: ret
entry:
%a = call i32 @llvm.riscv.vfirst.i32.nxv2i1(
<vscale x 2 x i1> %0,
i32 %1)
ret i32 %a
}
declare i32 @llvm.riscv.vfirst.mask.i32.nxv2i1(
<vscale x 2 x i1>,
<vscale x 2 x i1>,
i32);
define i32 @intrinsic_vfirst_mask_m_i32_nxv2i1(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vfirst_mask_m_i32_nxv2i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v9, v0
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vfirst.m a0, v9, v0.t
; CHECK-NEXT: ret
entry:
%a = call i32 @llvm.riscv.vfirst.mask.i32.nxv2i1(
<vscale x 2 x i1> %0,
<vscale x 2 x i1> %1,
i32 %2)
ret i32 %a
}
declare i32 @llvm.riscv.vfirst.i32.nxv4i1(
<vscale x 4 x i1>,
i32);
define i32 @intrinsic_vfirst_m_i32_nxv4i1(<vscale x 4 x i1> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vfirst_m_i32_nxv4i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
; CHECK-NEXT: vfirst.m a0, v0
; CHECK-NEXT: ret
entry:
%a = call i32 @llvm.riscv.vfirst.i32.nxv4i1(
<vscale x 4 x i1> %0,
i32 %1)
ret i32 %a
}
declare i32 @llvm.riscv.vfirst.mask.i32.nxv4i1(
<vscale x 4 x i1>,
<vscale x 4 x i1>,
i32);
define i32 @intrinsic_vfirst_mask_m_i32_nxv4i1(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vfirst_mask_m_i32_nxv4i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v9, v0
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vfirst.m a0, v9, v0.t
; CHECK-NEXT: ret
entry:
%a = call i32 @llvm.riscv.vfirst.mask.i32.nxv4i1(
<vscale x 4 x i1> %0,
<vscale x 4 x i1> %1,
i32 %2)
ret i32 %a
}
declare i32 @llvm.riscv.vfirst.i32.nxv8i1(
<vscale x 8 x i1>,
i32);
define i32 @intrinsic_vfirst_m_i32_nxv8i1(<vscale x 8 x i1> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vfirst_m_i32_nxv8i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
; CHECK-NEXT: vfirst.m a0, v0
; CHECK-NEXT: ret
entry:
%a = call i32 @llvm.riscv.vfirst.i32.nxv8i1(
<vscale x 8 x i1> %0,
i32 %1)
ret i32 %a
}
declare i32 @llvm.riscv.vfirst.mask.i32.nxv8i1(
<vscale x 8 x i1>,
<vscale x 8 x i1>,
i32);
define i32 @intrinsic_vfirst_mask_m_i32_nxv8i1(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vfirst_mask_m_i32_nxv8i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v9, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vfirst.m a0, v9, v0.t
; CHECK-NEXT: ret
entry:
%a = call i32 @llvm.riscv.vfirst.mask.i32.nxv8i1(
<vscale x 8 x i1> %0,
<vscale x 8 x i1> %1,
i32 %2)
ret i32 %a
}
declare i32 @llvm.riscv.vfirst.i32.nxv16i1(
<vscale x 16 x i1>,
i32);
define i32 @intrinsic_vfirst_m_i32_nxv16i1(<vscale x 16 x i1> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vfirst_m_i32_nxv16i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
; CHECK-NEXT: vfirst.m a0, v0
; CHECK-NEXT: ret
entry:
%a = call i32 @llvm.riscv.vfirst.i32.nxv16i1(
<vscale x 16 x i1> %0,
i32 %1)
ret i32 %a
}
declare i32 @llvm.riscv.vfirst.mask.i32.nxv16i1(
<vscale x 16 x i1>,
<vscale x 16 x i1>,
i32);
define i32 @intrinsic_vfirst_mask_m_i32_nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vfirst_mask_m_i32_nxv16i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v9, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vfirst.m a0, v9, v0.t
; CHECK-NEXT: ret
entry:
%a = call i32 @llvm.riscv.vfirst.mask.i32.nxv16i1(
<vscale x 16 x i1> %0,
<vscale x 16 x i1> %1,
i32 %2)
ret i32 %a
}
declare i32 @llvm.riscv.vfirst.i32.nxv32i1(
<vscale x 32 x i1>,
i32);
define i32 @intrinsic_vfirst_m_i32_nxv32i1(<vscale x 32 x i1> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vfirst_m_i32_nxv32i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
; CHECK-NEXT: vfirst.m a0, v0
; CHECK-NEXT: ret
entry:
%a = call i32 @llvm.riscv.vfirst.i32.nxv32i1(
<vscale x 32 x i1> %0,
i32 %1)
ret i32 %a
}
declare i32 @llvm.riscv.vfirst.mask.i32.nxv32i1(
<vscale x 32 x i1>,
<vscale x 32 x i1>,
i32);
define i32 @intrinsic_vfirst_mask_m_i32_nxv32i1(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vfirst_mask_m_i32_nxv32i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v9, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vfirst.m a0, v9, v0.t
; CHECK-NEXT: ret
entry:
%a = call i32 @llvm.riscv.vfirst.mask.i32.nxv32i1(
<vscale x 32 x i1> %0,
<vscale x 32 x i1> %1,
i32 %2)
ret i32 %a
}
declare i32 @llvm.riscv.vfirst.i32.nxv64i1(
<vscale x 64 x i1>,
i32);
define i32 @intrinsic_vfirst_m_i32_nxv64i1(<vscale x 64 x i1> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vfirst_m_i32_nxv64i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu
; CHECK-NEXT: vfirst.m a0, v0
; CHECK-NEXT: ret
entry:
%a = call i32 @llvm.riscv.vfirst.i32.nxv64i1(
<vscale x 64 x i1> %0,
i32 %1)
ret i32 %a
}
declare i32 @llvm.riscv.vfirst.mask.i32.nxv64i1(
<vscale x 64 x i1>,
<vscale x 64 x i1>,
i32);
define i32 @intrinsic_vfirst_mask_m_i32_nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vfirst_mask_m_i32_nxv64i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v9, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu
; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vfirst.m a0, v9, v0.t
; CHECK-NEXT: ret
entry:
%a = call i32 @llvm.riscv.vfirst.mask.i32.nxv64i1(
<vscale x 64 x i1> %0,
<vscale x 64 x i1> %1,
i32 %2)
ret i32 %a
}

llvm/test/CodeGen/RISCV/rvv/vfirst-rv64.ll

  • This file was deleted.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+v,+d -verify-machineinstrs \
; RUN: < %s | FileCheck %s
declare i64 @llvm.riscv.vfirst.i64.nxv1i1(
<vscale x 1 x i1>,
i64);
define i64 @intrinsic_vfirst_m_i64_nxv1i1(<vscale x 1 x i1> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vfirst_m_i64_nxv1i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
; CHECK-NEXT: vfirst.m a0, v0
; CHECK-NEXT: ret
entry:
%a = call i64 @llvm.riscv.vfirst.i64.nxv1i1(
<vscale x 1 x i1> %0,
i64 %1)
ret i64 %a
}
declare i64 @llvm.riscv.vfirst.mask.i64.nxv1i1(
<vscale x 1 x i1>,
<vscale x 1 x i1>,
i64);
define i64 @intrinsic_vfirst_mask_m_i64_nxv1i1(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vfirst_mask_m_i64_nxv1i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v9, v0
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vfirst.m a0, v9, v0.t
; CHECK-NEXT: ret
entry:
%a = call i64 @llvm.riscv.vfirst.mask.i64.nxv1i1(
<vscale x 1 x i1> %0,
<vscale x 1 x i1> %1,
i64 %2)
ret i64 %a
}
declare i64 @llvm.riscv.vfirst.i64.nxv2i1(
<vscale x 2 x i1>,
i64);
define i64 @intrinsic_vfirst_m_i64_nxv2i1(<vscale x 2 x i1> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vfirst_m_i64_nxv2i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
; CHECK-NEXT: vfirst.m a0, v0
; CHECK-NEXT: ret
entry:
%a = call i64 @llvm.riscv.vfirst.i64.nxv2i1(
<vscale x 2 x i1> %0,
i64 %1)
ret i64 %a
}
declare i64 @llvm.riscv.vfirst.mask.i64.nxv2i1(
<vscale x 2 x i1>,
<vscale x 2 x i1>,
i64);
define i64 @intrinsic_vfirst_mask_m_i64_nxv2i1(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vfirst_mask_m_i64_nxv2i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v9, v0
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vfirst.m a0, v9, v0.t
; CHECK-NEXT: ret
entry:
%a = call i64 @llvm.riscv.vfirst.mask.i64.nxv2i1(
<vscale x 2 x i1> %0,
<vscale x 2 x i1> %1,
i64 %2)
ret i64 %a
}
declare i64 @llvm.riscv.vfirst.i64.nxv4i1(
<vscale x 4 x i1>,
i64);
define i64 @intrinsic_vfirst_m_i64_nxv4i1(<vscale x 4 x i1> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vfirst_m_i64_nxv4i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
; CHECK-NEXT: vfirst.m a0, v0
; CHECK-NEXT: ret
entry:
%a = call i64 @llvm.riscv.vfirst.i64.nxv4i1(
<vscale x 4 x i1> %0,
i64 %1)
ret i64 %a
}
declare i64 @llvm.riscv.vfirst.mask.i64.nxv4i1(
<vscale x 4 x i1>,
<vscale x 4 x i1>,
i64);
define i64 @intrinsic_vfirst_mask_m_i64_nxv4i1(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vfirst_mask_m_i64_nxv4i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v9, v0
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vfirst.m a0, v9, v0.t
; CHECK-NEXT: ret
entry:
%a = call i64 @llvm.riscv.vfirst.mask.i64.nxv4i1(
<vscale x 4 x i1> %0,
<vscale x 4 x i1> %1,
i64 %2)
ret i64 %a
}
declare i64 @llvm.riscv.vfirst.i64.nxv8i1(
<vscale x 8 x i1>,
i64);
define i64 @intrinsic_vfirst_m_i64_nxv8i1(<vscale x 8 x i1> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vfirst_m_i64_nxv8i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
; CHECK-NEXT: vfirst.m a0, v0
; CHECK-NEXT: ret
entry:
%a = call i64 @llvm.riscv.vfirst.i64.nxv8i1(
<vscale x 8 x i1> %0,
i64 %1)
ret i64 %a
}
declare i64 @llvm.riscv.vfirst.mask.i64.nxv8i1(
<vscale x 8 x i1>,
<vscale x 8 x i1>,
i64);
define i64 @intrinsic_vfirst_mask_m_i64_nxv8i1(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vfirst_mask_m_i64_nxv8i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v9, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vfirst.m a0, v9, v0.t
; CHECK-NEXT: ret
entry:
%a = call i64 @llvm.riscv.vfirst.mask.i64.nxv8i1(
<vscale x 8 x i1> %0,
<vscale x 8 x i1> %1,
i64 %2)
ret i64 %a
}
declare i64 @llvm.riscv.vfirst.i64.nxv16i1(
<vscale x 16 x i1>,
i64);
define i64 @intrinsic_vfirst_m_i64_nxv16i1(<vscale x 16 x i1> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vfirst_m_i64_nxv16i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
; CHECK-NEXT: vfirst.m a0, v0
; CHECK-NEXT: ret
entry:
%a = call i64 @llvm.riscv.vfirst.i64.nxv16i1(
<vscale x 16 x i1> %0,
i64 %1)
ret i64 %a
}
declare i64 @llvm.riscv.vfirst.mask.i64.nxv16i1(
<vscale x 16 x i1>,
<vscale x 16 x i1>,
i64);
define i64 @intrinsic_vfirst_mask_m_i64_nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vfirst_mask_m_i64_nxv16i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v9, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vfirst.m a0, v9, v0.t
; CHECK-NEXT: ret
entry:
%a = call i64 @llvm.riscv.vfirst.mask.i64.nxv16i1(
<vscale x 16 x i1> %0,
<vscale x 16 x i1> %1,
i64 %2)
ret i64 %a
}
declare i64 @llvm.riscv.vfirst.i64.nxv32i1(
<vscale x 32 x i1>,
i64);
define i64 @intrinsic_vfirst_m_i64_nxv32i1(<vscale x 32 x i1> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vfirst_m_i64_nxv32i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
; CHECK-NEXT: vfirst.m a0, v0
; CHECK-NEXT: ret
entry:
%a = call i64 @llvm.riscv.vfirst.i64.nxv32i1(
<vscale x 32 x i1> %0,
i64 %1)
ret i64 %a
}
declare i64 @llvm.riscv.vfirst.mask.i64.nxv32i1(
<vscale x 32 x i1>,
<vscale x 32 x i1>,
i64);
define i64 @intrinsic_vfirst_mask_m_i64_nxv32i1(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vfirst_mask_m_i64_nxv32i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v9, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vfirst.m a0, v9, v0.t
; CHECK-NEXT: ret
entry:
%a = call i64 @llvm.riscv.vfirst.mask.i64.nxv32i1(
<vscale x 32 x i1> %0,
<vscale x 32 x i1> %1,
i64 %2)
ret i64 %a
}
declare i64 @llvm.riscv.vfirst.i64.nxv64i1(
<vscale x 64 x i1>,
i64);
define i64 @intrinsic_vfirst_m_i64_nxv64i1(<vscale x 64 x i1> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vfirst_m_i64_nxv64i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu
; CHECK-NEXT: vfirst.m a0, v0
; CHECK-NEXT: ret
entry:
%a = call i64 @llvm.riscv.vfirst.i64.nxv64i1(
<vscale x 64 x i1> %0,
i64 %1)
ret i64 %a
}
declare i64 @llvm.riscv.vfirst.mask.i64.nxv64i1(
<vscale x 64 x i1>,
<vscale x 64 x i1>,
i64);
define i64 @intrinsic_vfirst_mask_m_i64_nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vfirst_mask_m_i64_nxv64i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v9, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu
; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vfirst.m a0, v9, v0.t
; CHECK-NEXT: ret
entry:
%a = call i64 @llvm.riscv.vfirst.mask.i64.nxv64i1(
<vscale x 64 x i1> %0,
<vscale x 64 x i1> %1,
i64 %2)
ret i64 %a
}

llvm/test/CodeGen/RISCV/rvv/vfirst.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v \
; RUN: -verify-machineinstrs | FileCheck %s
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v \
; RUN: -verify-machineinstrs | FileCheck %s
declare iXLen @llvm.riscv.vfirst.iXLen.nxv1i1(
<vscale x 1 x i1>,
iXLen);
define iXLen @intrinsic_vfirst_m_nxv1i1(<vscale x 1 x i1> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfirst_m_nxv1i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
; CHECK-NEXT: vfirst.m a0, v0
; CHECK-NEXT: ret
entry:
%a = call iXLen @llvm.riscv.vfirst.iXLen.nxv1i1(
<vscale x 1 x i1> %0,
iXLen %1)
ret iXLen %a
}
declare iXLen @llvm.riscv.vfirst.mask.iXLen.nxv1i1(
<vscale x 1 x i1>,
<vscale x 1 x i1>,
iXLen);
define iXLen @intrinsic_vfirst_mask_m_nxv1i1(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vfirst_mask_m_nxv1i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v9, v0
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vfirst.m a0, v9, v0.t
; CHECK-NEXT: ret
entry:
%a = call iXLen @llvm.riscv.vfirst.mask.iXLen.nxv1i1(
<vscale x 1 x i1> %0,
<vscale x 1 x i1> %1,
iXLen %2)
ret iXLen %a
}
declare iXLen @llvm.riscv.vfirst.iXLen.nxv2i1(
<vscale x 2 x i1>,
iXLen);
define iXLen @intrinsic_vfirst_m_nxv2i1(<vscale x 2 x i1> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfirst_m_nxv2i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
; CHECK-NEXT: vfirst.m a0, v0
; CHECK-NEXT: ret
entry:
%a = call iXLen @llvm.riscv.vfirst.iXLen.nxv2i1(
<vscale x 2 x i1> %0,
iXLen %1)
ret iXLen %a
}
declare iXLen @llvm.riscv.vfirst.mask.iXLen.nxv2i1(
<vscale x 2 x i1>,
<vscale x 2 x i1>,
iXLen);
define iXLen @intrinsic_vfirst_mask_m_nxv2i1(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vfirst_mask_m_nxv2i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v9, v0
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vfirst.m a0, v9, v0.t
; CHECK-NEXT: ret
entry:
%a = call iXLen @llvm.riscv.vfirst.mask.iXLen.nxv2i1(
<vscale x 2 x i1> %0,
<vscale x 2 x i1> %1,
iXLen %2)
ret iXLen %a
}
declare iXLen @llvm.riscv.vfirst.iXLen.nxv4i1(
<vscale x 4 x i1>,
iXLen);
define iXLen @intrinsic_vfirst_m_nxv4i1(<vscale x 4 x i1> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfirst_m_nxv4i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
; CHECK-NEXT: vfirst.m a0, v0
; CHECK-NEXT: ret
entry:
%a = call iXLen @llvm.riscv.vfirst.iXLen.nxv4i1(
<vscale x 4 x i1> %0,
iXLen %1)
ret iXLen %a
}
declare iXLen @llvm.riscv.vfirst.mask.iXLen.nxv4i1(
<vscale x 4 x i1>,
<vscale x 4 x i1>,
iXLen);
define iXLen @intrinsic_vfirst_mask_m_nxv4i1(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vfirst_mask_m_nxv4i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v9, v0
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vfirst.m a0, v9, v0.t
; CHECK-NEXT: ret
entry:
%a = call iXLen @llvm.riscv.vfirst.mask.iXLen.nxv4i1(
<vscale x 4 x i1> %0,
<vscale x 4 x i1> %1,
iXLen %2)
ret iXLen %a
}
declare iXLen @llvm.riscv.vfirst.iXLen.nxv8i1(
<vscale x 8 x i1>,
iXLen);
define iXLen @intrinsic_vfirst_m_nxv8i1(<vscale x 8 x i1> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfirst_m_nxv8i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
; CHECK-NEXT: vfirst.m a0, v0
; CHECK-NEXT: ret
entry:
%a = call iXLen @llvm.riscv.vfirst.iXLen.nxv8i1(
<vscale x 8 x i1> %0,
iXLen %1)
ret iXLen %a
}
declare iXLen @llvm.riscv.vfirst.mask.iXLen.nxv8i1(
<vscale x 8 x i1>,
<vscale x 8 x i1>,
iXLen);
define iXLen @intrinsic_vfirst_mask_m_nxv8i1(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vfirst_mask_m_nxv8i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v9, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vfirst.m a0, v9, v0.t
; CHECK-NEXT: ret
entry:
%a = call iXLen @llvm.riscv.vfirst.mask.iXLen.nxv8i1(
<vscale x 8 x i1> %0,
<vscale x 8 x i1> %1,
iXLen %2)
ret iXLen %a
}
declare iXLen @llvm.riscv.vfirst.iXLen.nxv16i1(
<vscale x 16 x i1>,
iXLen);
define iXLen @intrinsic_vfirst_m_nxv16i1(<vscale x 16 x i1> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfirst_m_nxv16i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
; CHECK-NEXT: vfirst.m a0, v0
; CHECK-NEXT: ret
entry:
%a = call iXLen @llvm.riscv.vfirst.iXLen.nxv16i1(
<vscale x 16 x i1> %0,
iXLen %1)
ret iXLen %a
}
declare iXLen @llvm.riscv.vfirst.mask.iXLen.nxv16i1(
<vscale x 16 x i1>,
<vscale x 16 x i1>,
iXLen);
define iXLen @intrinsic_vfirst_mask_m_nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vfirst_mask_m_nxv16i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v9, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vfirst.m a0, v9, v0.t
; CHECK-NEXT: ret
entry:
%a = call iXLen @llvm.riscv.vfirst.mask.iXLen.nxv16i1(
<vscale x 16 x i1> %0,
<vscale x 16 x i1> %1,
iXLen %2)
ret iXLen %a
}
declare iXLen @llvm.riscv.vfirst.iXLen.nxv32i1(
<vscale x 32 x i1>,
iXLen);
define iXLen @intrinsic_vfirst_m_nxv32i1(<vscale x 32 x i1> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfirst_m_nxv32i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
; CHECK-NEXT: vfirst.m a0, v0
; CHECK-NEXT: ret
entry:
%a = call iXLen @llvm.riscv.vfirst.iXLen.nxv32i1(
<vscale x 32 x i1> %0,
iXLen %1)
ret iXLen %a
}
declare iXLen @llvm.riscv.vfirst.mask.iXLen.nxv32i1(
<vscale x 32 x i1>,
<vscale x 32 x i1>,
iXLen);
define iXLen @intrinsic_vfirst_mask_m_nxv32i1(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vfirst_mask_m_nxv32i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v9, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vfirst.m a0, v9, v0.t
; CHECK-NEXT: ret
entry:
%a = call iXLen @llvm.riscv.vfirst.mask.iXLen.nxv32i1(
<vscale x 32 x i1> %0,
<vscale x 32 x i1> %1,
iXLen %2)
ret iXLen %a
}
declare iXLen @llvm.riscv.vfirst.iXLen.nxv64i1(
<vscale x 64 x i1>,
iXLen);
define iXLen @intrinsic_vfirst_m_nxv64i1(<vscale x 64 x i1> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfirst_m_nxv64i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu
; CHECK-NEXT: vfirst.m a0, v0
; CHECK-NEXT: ret
entry:
%a = call iXLen @llvm.riscv.vfirst.iXLen.nxv64i1(
<vscale x 64 x i1> %0,
iXLen %1)
ret iXLen %a
}
declare iXLen @llvm.riscv.vfirst.mask.iXLen.nxv64i1(
<vscale x 64 x i1>,
<vscale x 64 x i1>,
iXLen);
define iXLen @intrinsic_vfirst_mask_m_nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vfirst_mask_m_nxv64i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v9, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu
; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vfirst.m a0, v9, v0.t
; CHECK-NEXT: ret
entry:
%a = call iXLen @llvm.riscv.vfirst.mask.iXLen.nxv64i1(
<vscale x 64 x i1> %0,
<vscale x 64 x i1> %1,
iXLen %2)
ret iXLen %a
}

llvm/test/CodeGen/RISCV/rvv/vid-rv32.ll

  • This file was moved to llvm/test/CodeGen/RISCV/rvv/vid.ll.

llvm/test/CodeGen/RISCV/rvv/vid-rv64.ll

  • This file was deleted.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs \
; RUN: < %s | FileCheck %s
declare <vscale x 1 x i8> @llvm.riscv.vid.nxv1i8(
i64);
define <vscale x 1 x i8> @intrinsic_vid_v_nxv1i8(i64 %0) nounwind {
; CHECK-LABEL: intrinsic_vid_v_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
; CHECK-NEXT: vid.v v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vid.nxv1i8(
i64 %0)
ret <vscale x 1 x i8> %a
}
declare <vscale x 1 x i8> @llvm.riscv.vid.mask.nxv1i8(
<vscale x 1 x i8>,
<vscale x 1 x i1>,
i64);
define <vscale x 1 x i8> @intrinsic_vid_mask_v_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i1> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vid_mask_v_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, mu
; CHECK-NEXT: vid.v v8, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vid.mask.nxv1i8(
<vscale x 1 x i8> %0,
<vscale x 1 x i1> %1,
i64 %2)
ret <vscale x 1 x i8> %a
}
declare <vscale x 2 x i8> @llvm.riscv.vid.nxv2i8(
i64);
define <vscale x 2 x i8> @intrinsic_vid_v_nxv2i8(i64 %0) nounwind {
; CHECK-LABEL: intrinsic_vid_v_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
; CHECK-NEXT: vid.v v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vid.nxv2i8(
i64 %0)
ret <vscale x 2 x i8> %a
}
declare <vscale x 2 x i8> @llvm.riscv.vid.mask.nxv2i8(
<vscale x 2 x i8>,
<vscale x 2 x i1>,
i64);
define <vscale x 2 x i8> @intrinsic_vid_mask_v_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i1> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vid_mask_v_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, tu, mu
; CHECK-NEXT: vid.v v8, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vid.mask.nxv2i8(
<vscale x 2 x i8> %0,
<vscale x 2 x i1> %1,
i64 %2)
ret <vscale x 2 x i8> %a
}
declare <vscale x 4 x i8> @llvm.riscv.vid.nxv4i8(
i64);
define <vscale x 4 x i8> @intrinsic_vid_v_nxv4i8(i64 %0) nounwind {
; CHECK-LABEL: intrinsic_vid_v_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
; CHECK-NEXT: vid.v v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vid.nxv4i8(
i64 %0)
ret <vscale x 4 x i8> %a
}
declare <vscale x 4 x i8> @llvm.riscv.vid.mask.nxv4i8(
<vscale x 4 x i8>,
<vscale x 4 x i1>,
i64);
define <vscale x 4 x i8> @intrinsic_vid_mask_v_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i1> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vid_mask_v_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, mu
; CHECK-NEXT: vid.v v8, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vid.mask.nxv4i8(
<vscale x 4 x i8> %0,
<vscale x 4 x i1> %1,
i64 %2)
ret <vscale x 4 x i8> %a
}
declare <vscale x 8 x i8> @llvm.riscv.vid.nxv8i8(
i64);
define <vscale x 8 x i8> @intrinsic_vid_v_nxv8i8(i64 %0) nounwind {
; CHECK-LABEL: intrinsic_vid_v_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
; CHECK-NEXT: vid.v v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vid.nxv8i8(
i64 %0)
ret <vscale x 8 x i8> %a
}
declare <vscale x 8 x i8> @llvm.riscv.vid.mask.nxv8i8(
<vscale x 8 x i8>,
<vscale x 8 x i1>,
i64);
define <vscale x 8 x i8> @intrinsic_vid_mask_v_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i1> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vid_mask_v_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, mu
; CHECK-NEXT: vid.v v8, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vid.mask.nxv8i8(
<vscale x 8 x i8> %0,
<vscale x 8 x i1> %1,
i64 %2)
ret <vscale x 8 x i8> %a
}
declare <vscale x 16 x i8> @llvm.riscv.vid.nxv16i8(
i64);
define <vscale x 16 x i8> @intrinsic_vid_v_nxv16i8(i64 %0) nounwind {
; CHECK-LABEL: intrinsic_vid_v_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
; CHECK-NEXT: vid.v v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vid.nxv16i8(
i64 %0)
ret <vscale x 16 x i8> %a
}
declare <vscale x 16 x i8> @llvm.riscv.vid.mask.nxv16i8(
<vscale x 16 x i8>,
<vscale x 16 x i1>,
i64);
define <vscale x 16 x i8> @intrinsic_vid_mask_v_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i1> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vid_mask_v_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, tu, mu
; CHECK-NEXT: vid.v v8, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vid.mask.nxv16i8(
<vscale x 16 x i8> %0,
<vscale x 16 x i1> %1,
i64 %2)
ret <vscale x 16 x i8> %a
}
declare <vscale x 32 x i8> @llvm.riscv.vid.nxv32i8(
i64);
define <vscale x 32 x i8> @intrinsic_vid_v_nxv32i8(i64 %0) nounwind {
; CHECK-LABEL: intrinsic_vid_v_nxv32i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
; CHECK-NEXT: vid.v v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vid.nxv32i8(
i64 %0)
ret <vscale x 32 x i8> %a
}
declare <vscale x 32 x i8> @llvm.riscv.vid.mask.nxv32i8(
<vscale x 32 x i8>,
<vscale x 32 x i1>,
i64);
define <vscale x 32 x i8> @intrinsic_vid_mask_v_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i1> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vid_mask_v_nxv32i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, tu, mu
; CHECK-NEXT: vid.v v8, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vid.mask.nxv32i8(
<vscale x 32 x i8> %0,
<vscale x 32 x i1> %1,
i64 %2)
ret <vscale x 32 x i8> %a
}
declare <vscale x 1 x i16> @llvm.riscv.vid.nxv1i16(
i64);
define <vscale x 1 x i16> @intrinsic_vid_v_nxv1i16(i64 %0) nounwind {
; CHECK-LABEL: intrinsic_vid_v_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
; CHECK-NEXT: vid.v v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vid.nxv1i16(
i64 %0)
ret <vscale x 1 x i16> %a
}
declare <vscale x 1 x i16> @llvm.riscv.vid.mask.nxv1i16(
<vscale x 1 x i16>,
<vscale x 1 x i1>,
i64);
define <vscale x 1 x i16> @intrinsic_vid_mask_v_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i1> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vid_mask_v_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu
; CHECK-NEXT: vid.v v8, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vid.mask.nxv1i16(
<vscale x 1 x i16> %0,
<vscale x 1 x i1> %1,
i64 %2)
ret <vscale x 1 x i16> %a
}
declare <vscale x 2 x i16> @llvm.riscv.vid.nxv2i16(
i64);
define <vscale x 2 x i16> @intrinsic_vid_v_nxv2i16(i64 %0) nounwind {
; CHECK-LABEL: intrinsic_vid_v_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
; CHECK-NEXT: vid.v v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vid.nxv2i16(
i64 %0)
ret <vscale x 2 x i16> %a
}
declare <vscale x 2 x i16> @llvm.riscv.vid.mask.nxv2i16(
<vscale x 2 x i16>,
<vscale x 2 x i1>,
i64);
define <vscale x 2 x i16> @intrinsic_vid_mask_v_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i1> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vid_mask_v_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu
; CHECK-NEXT: vid.v v8, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vid.mask.nxv2i16(
<vscale x 2 x i16> %0,
<vscale x 2 x i1> %1,
i64 %2)
ret <vscale x 2 x i16> %a
}
declare <vscale x 4 x i16> @llvm.riscv.vid.nxv4i16(
i64);
define <vscale x 4 x i16> @intrinsic_vid_v_nxv4i16(i64 %0) nounwind {
; CHECK-LABEL: intrinsic_vid_v_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
; CHECK-NEXT: vid.v v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vid.nxv4i16(
i64 %0)
ret <vscale x 4 x i16> %a
}
declare <vscale x 4 x i16> @llvm.riscv.vid.mask.nxv4i16(
<vscale x 4 x i16>,
<vscale x 4 x i1>,
i64);
define <vscale x 4 x i16> @intrinsic_vid_mask_v_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i1> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vid_mask_v_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu
; CHECK-NEXT: vid.v v8, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vid.mask.nxv4i16(
<vscale x 4 x i16> %0,
<vscale x 4 x i1> %1,
i64 %2)
ret <vscale x 4 x i16> %a
}
declare <vscale x 8 x i16> @llvm.riscv.vid.nxv8i16(
i64);
define <vscale x 8 x i16> @intrinsic_vid_v_nxv8i16(i64 %0) nounwind {
; CHECK-LABEL: intrinsic_vid_v_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
; CHECK-NEXT: vid.v v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vid.nxv8i16(
i64 %0)
ret <vscale x 8 x i16> %a
}
declare <vscale x 8 x i16> @llvm.riscv.vid.mask.nxv8i16(
<vscale x 8 x i16>,
<vscale x 8 x i1>,
i64);
define <vscale x 8 x i16> @intrinsic_vid_mask_v_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i1> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vid_mask_v_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu
; CHECK-NEXT: vid.v v8, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vid.mask.nxv8i16(
<vscale x 8 x i16> %0,
<vscale x 8 x i1> %1,
i64 %2)
ret <vscale x 8 x i16> %a
}
declare <vscale x 16 x i16> @llvm.riscv.vid.nxv16i16(
i64);
define <vscale x 16 x i16> @intrinsic_vid_v_nxv16i16(i64 %0) nounwind {
; CHECK-LABEL: intrinsic_vid_v_nxv16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
; CHECK-NEXT: vid.v v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vid.nxv16i16(
i64 %0)
ret <vscale x 16 x i16> %a
}
declare <vscale x 16 x i16> @llvm.riscv.vid.mask.nxv16i16(
<vscale x 16 x i16>,
<vscale x 16 x i1>,
i64);
define <vscale x 16 x i16> @intrinsic_vid_mask_v_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i1> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vid_mask_v_nxv16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu
; CHECK-NEXT: vid.v v8, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vid.mask.nxv16i16(
<vscale x 16 x i16> %0,
<vscale x 16 x i1> %1,
i64 %2)
ret <vscale x 16 x i16> %a
}
declare <vscale x 32 x i16> @llvm.riscv.vid.nxv32i16(
i64);
define <vscale x 32 x i16> @intrinsic_vid_v_nxv32i16(i64 %0) nounwind {
; CHECK-LABEL: intrinsic_vid_v_nxv32i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu
; CHECK-NEXT: vid.v v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vid.nxv32i16(
i64 %0)
ret <vscale x 32 x i16> %a
}
declare <vscale x 32 x i16> @llvm.riscv.vid.mask.nxv32i16(
<vscale x 32 x i16>,
<vscale x 32 x i1>,
i64);
define <vscale x 32 x i16> @intrinsic_vid_mask_v_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i1> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vid_mask_v_nxv32i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m8, tu, mu
; CHECK-NEXT: vid.v v8, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vid.mask.nxv32i16(
<vscale x 32 x i16> %0,
<vscale x 32 x i1> %1,
i64 %2)
ret <vscale x 32 x i16> %a
}
declare <vscale x 1 x i32> @llvm.riscv.vid.nxv1i32(
i64);
define <vscale x 1 x i32> @intrinsic_vid_v_nxv1i32(i64 %0) nounwind {
; CHECK-LABEL: intrinsic_vid_v_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
; CHECK-NEXT: vid.v v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vid.nxv1i32(
i64 %0)
ret <vscale x 1 x i32> %a
}
declare <vscale x 1 x i32> @llvm.riscv.vid.mask.nxv1i32(
<vscale x 1 x i32>,
<vscale x 1 x i1>,
i64);
define <vscale x 1 x i32> @intrinsic_vid_mask_v_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i1> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vid_mask_v_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu
; CHECK-NEXT: vid.v v8, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vid.mask.nxv1i32(
<vscale x 1 x i32> %0,
<vscale x 1 x i1> %1,
i64 %2)
ret <vscale x 1 x i32> %a
}
declare <vscale x 2 x i32> @llvm.riscv.vid.nxv2i32(
i64);
define <vscale x 2 x i32> @intrinsic_vid_v_nxv2i32(i64 %0) nounwind {
; CHECK-LABEL: intrinsic_vid_v_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
; CHECK-NEXT: vid.v v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vid.nxv2i32(
i64 %0)
ret <vscale x 2 x i32> %a
}
declare <vscale x 2 x i32> @llvm.riscv.vid.mask.nxv2i32(
<vscale x 2 x i32>,
<vscale x 2 x i1>,
i64);
define <vscale x 2 x i32> @intrinsic_vid_mask_v_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i1> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vid_mask_v_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu
; CHECK-NEXT: vid.v v8, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vid.mask.nxv2i32(
<vscale x 2 x i32> %0,
<vscale x 2 x i1> %1,
i64 %2)
ret <vscale x 2 x i32> %a
}
declare <vscale x 4 x i32> @llvm.riscv.vid.nxv4i32(
i64);
define <vscale x 4 x i32> @intrinsic_vid_v_nxv4i32(i64 %0) nounwind {
; CHECK-LABEL: intrinsic_vid_v_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
; CHECK-NEXT: vid.v v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vid.nxv4i32(
i64 %0)
ret <vscale x 4 x i32> %a
}
declare <vscale x 4 x i32> @llvm.riscv.vid.mask.nxv4i32(
<vscale x 4 x i32>,
<vscale x 4 x i1>,
i64);
define <vscale x 4 x i32> @intrinsic_vid_mask_v_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i1> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vid_mask_v_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu
; CHECK-NEXT: vid.v v8, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vid.mask.nxv4i32(
<vscale x 4 x i32> %0,
<vscale x 4 x i1> %1,
i64 %2)
ret <vscale x 4 x i32> %a
}
declare <vscale x 8 x i32> @llvm.riscv.vid.nxv8i32(
i64);
define <vscale x 8 x i32> @intrinsic_vid_v_nxv8i32(i64 %0) nounwind {
; CHECK-LABEL: intrinsic_vid_v_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
; CHECK-NEXT: vid.v v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vid.nxv8i32(
i64 %0)
ret <vscale x 8 x i32> %a
}
declare <vscale x 8 x i32> @llvm.riscv.vid.mask.nxv8i32(
<vscale x 8 x i32>,
<vscale x 8 x i1>,
i64);
define <vscale x 8 x i32> @intrinsic_vid_mask_v_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i1> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vid_mask_v_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu
; CHECK-NEXT: vid.v v8, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vid.mask.nxv8i32(
<vscale x 8 x i32> %0,
<vscale x 8 x i1> %1,
i64 %2)
ret <vscale x 8 x i32> %a
}
declare <vscale x 16 x i32> @llvm.riscv.vid.nxv16i32(
i64);
define <vscale x 16 x i32> @intrinsic_vid_v_nxv16i32(i64 %0) nounwind {
; CHECK-LABEL: intrinsic_vid_v_nxv16i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu
; CHECK-NEXT: vid.v v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vid.nxv16i32(
i64 %0)
ret <vscale x 16 x i32> %a
}
declare <vscale x 16 x i32> @llvm.riscv.vid.mask.nxv16i32(
<vscale x 16 x i32>,
<vscale x 16 x i1>,
i64);
define <vscale x 16 x i32> @intrinsic_vid_mask_v_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i1> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vid_mask_v_nxv16i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m8, tu, mu
; CHECK-NEXT: vid.v v8, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vid.mask.nxv16i32(
<vscale x 16 x i32> %0,
<vscale x 16 x i1> %1,
i64 %2)
ret <vscale x 16 x i32> %a
}
declare <vscale x 1 x i64> @llvm.riscv.vid.nxv1i64(
i64);
define <vscale x 1 x i64> @intrinsic_vid_v_nxv1i64(i64 %0) nounwind {
; CHECK-LABEL: intrinsic_vid_v_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
; CHECK-NEXT: vid.v v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vid.nxv1i64(
i64 %0)
ret <vscale x 1 x i64> %a
}
declare <vscale x 1 x i64> @llvm.riscv.vid.mask.nxv1i64(
<vscale x 1 x i64>,
<vscale x 1 x i1>,
i64);
define <vscale x 1 x i64> @intrinsic_vid_mask_v_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i1> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vid_mask_v_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu
; CHECK-NEXT: vid.v v8, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vid.mask.nxv1i64(
<vscale x 1 x i64> %0,
<vscale x 1 x i1> %1,
i64 %2)
ret <vscale x 1 x i64> %a
}
declare <vscale x 2 x i64> @llvm.riscv.vid.nxv2i64(
i64);
define <vscale x 2 x i64> @intrinsic_vid_v_nxv2i64(i64 %0) nounwind {
; CHECK-LABEL: intrinsic_vid_v_nxv2i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
; CHECK-NEXT: vid.v v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vid.nxv2i64(
i64 %0)
ret <vscale x 2 x i64> %a
}
declare <vscale x 2 x i64> @llvm.riscv.vid.mask.nxv2i64(
<vscale x 2 x i64>,
<vscale x 2 x i1>,
i64);
define <vscale x 2 x i64> @intrinsic_vid_mask_v_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i1> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vid_mask_v_nxv2i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu
; CHECK-NEXT: vid.v v8, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vid.mask.nxv2i64(
<vscale x 2 x i64> %0,
<vscale x 2 x i1> %1,
i64 %2)
ret <vscale x 2 x i64> %a
}
declare <vscale x 4 x i64> @llvm.riscv.vid.nxv4i64(
i64);
define <vscale x 4 x i64> @intrinsic_vid_v_nxv4i64(i64 %0) nounwind {
; CHECK-LABEL: intrinsic_vid_v_nxv4i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
; CHECK-NEXT: vid.v v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vid.nxv4i64(
i64 %0)
ret <vscale x 4 x i64> %a
}
declare <vscale x 4 x i64> @llvm.riscv.vid.mask.nxv4i64(
<vscale x 4 x i64>,
<vscale x 4 x i1>,
i64);
define <vscale x 4 x i64> @intrinsic_vid_mask_v_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i1> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vid_mask_v_nxv4i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu
; CHECK-NEXT: vid.v v8, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vid.mask.nxv4i64(
<vscale x 4 x i64> %0,
<vscale x 4 x i1> %1,
i64 %2)
ret <vscale x 4 x i64> %a
}
declare <vscale x 8 x i64> @llvm.riscv.vid.nxv8i64(
i64);
define <vscale x 8 x i64> @intrinsic_vid_v_nxv8i64(i64 %0) nounwind {
; CHECK-LABEL: intrinsic_vid_v_nxv8i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu
; CHECK-NEXT: vid.v v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vid.nxv8i64(
i64 %0)
ret <vscale x 8 x i64> %a
}
declare <vscale x 8 x i64> @llvm.riscv.vid.mask.nxv8i64(
<vscale x 8 x i64>,
<vscale x 8 x i1>,
i64);
define <vscale x 8 x i64> @intrinsic_vid_mask_v_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i1> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vid_mask_v_nxv8i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m8, tu, mu
; CHECK-NEXT: vid.v v8, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vid.mask.nxv8i64(
<vscale x 8 x i64> %0,
<vscale x 8 x i1> %1,
i64 %2)
ret <vscale x 8 x i64> %a
}

llvm/test/CodeGen/RISCV/rvv/vid.ll

  • This file was moved from llvm/test/CodeGen/RISCV/rvv/vid-rv32.ll.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs \ ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v \
; RUN: < %s | FileCheck %s ; RUN: -verify-machineinstrs | FileCheck %s
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v \
; RUN: -verify-machineinstrs | FileCheck %s
declare <vscale x 1 x i8> @llvm.riscv.vid.nxv1i8( declare <vscale x 1 x i8> @llvm.riscv.vid.nxv1i8(
i32); iXLen);
define <vscale x 1 x i8> @intrinsic_vid_v_nxv1i8(i32 %0) nounwind { define <vscale x 1 x i8> @intrinsic_vid_v_nxv1i8(iXLen %0) nounwind {
; CHECK-LABEL: intrinsic_vid_v_nxv1i8: ; CHECK-LABEL: intrinsic_vid_v_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
; CHECK-NEXT: vid.v v8 ; CHECK-NEXT: vid.v v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vid.nxv1i8( %a = call <vscale x 1 x i8> @llvm.riscv.vid.nxv1i8(
i32 %0) iXLen %0)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 1 x i8> @llvm.riscv.vid.mask.nxv1i8( declare <vscale x 1 x i8> @llvm.riscv.vid.mask.nxv1i8(
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); iXLen);
define <vscale x 1 x i8> @intrinsic_vid_mask_v_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i1> %1, i32 %2) nounwind { define <vscale x 1 x i8> @intrinsic_vid_mask_v_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vid_mask_v_nxv1i8: ; CHECK-LABEL: intrinsic_vid_mask_v_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, mu
; CHECK-NEXT: vid.v v8, v0.t ; CHECK-NEXT: vid.v v8, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vid.mask.nxv1i8( %a = call <vscale x 1 x i8> @llvm.riscv.vid.mask.nxv1i8(
<vscale x 1 x i8> %0, <vscale x 1 x i8> %0,
<vscale x 1 x i1> %1, <vscale x 1 x i1> %1,
i32 %2) iXLen %2)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 2 x i8> @llvm.riscv.vid.nxv2i8( declare <vscale x 2 x i8> @llvm.riscv.vid.nxv2i8(
i32); iXLen);
define <vscale x 2 x i8> @intrinsic_vid_v_nxv2i8(i32 %0) nounwind { define <vscale x 2 x i8> @intrinsic_vid_v_nxv2i8(iXLen %0) nounwind {
; CHECK-LABEL: intrinsic_vid_v_nxv2i8: ; CHECK-LABEL: intrinsic_vid_v_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
; CHECK-NEXT: vid.v v8 ; CHECK-NEXT: vid.v v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vid.nxv2i8( %a = call <vscale x 2 x i8> @llvm.riscv.vid.nxv2i8(
i32 %0) iXLen %0)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
declare <vscale x 2 x i8> @llvm.riscv.vid.mask.nxv2i8( declare <vscale x 2 x i8> @llvm.riscv.vid.mask.nxv2i8(
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); iXLen);
define <vscale x 2 x i8> @intrinsic_vid_mask_v_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i1> %1, i32 %2) nounwind { define <vscale x 2 x i8> @intrinsic_vid_mask_v_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vid_mask_v_nxv2i8: ; CHECK-LABEL: intrinsic_vid_mask_v_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, tu, mu
; CHECK-NEXT: vid.v v8, v0.t ; CHECK-NEXT: vid.v v8, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vid.mask.nxv2i8( %a = call <vscale x 2 x i8> @llvm.riscv.vid.mask.nxv2i8(
<vscale x 2 x i8> %0, <vscale x 2 x i8> %0,
<vscale x 2 x i1> %1, <vscale x 2 x i1> %1,
i32 %2) iXLen %2)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
declare <vscale x 4 x i8> @llvm.riscv.vid.nxv4i8( declare <vscale x 4 x i8> @llvm.riscv.vid.nxv4i8(
i32); iXLen);
define <vscale x 4 x i8> @intrinsic_vid_v_nxv4i8(i32 %0) nounwind { define <vscale x 4 x i8> @intrinsic_vid_v_nxv4i8(iXLen %0) nounwind {
; CHECK-LABEL: intrinsic_vid_v_nxv4i8: ; CHECK-LABEL: intrinsic_vid_v_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
; CHECK-NEXT: vid.v v8 ; CHECK-NEXT: vid.v v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vid.nxv4i8( %a = call <vscale x 4 x i8> @llvm.riscv.vid.nxv4i8(
i32 %0) iXLen %0)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
declare <vscale x 4 x i8> @llvm.riscv.vid.mask.nxv4i8( declare <vscale x 4 x i8> @llvm.riscv.vid.mask.nxv4i8(
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); iXLen);
define <vscale x 4 x i8> @intrinsic_vid_mask_v_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i1> %1, i32 %2) nounwind { define <vscale x 4 x i8> @intrinsic_vid_mask_v_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vid_mask_v_nxv4i8: ; CHECK-LABEL: intrinsic_vid_mask_v_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, mu
; CHECK-NEXT: vid.v v8, v0.t ; CHECK-NEXT: vid.v v8, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vid.mask.nxv4i8( %a = call <vscale x 4 x i8> @llvm.riscv.vid.mask.nxv4i8(
<vscale x 4 x i8> %0, <vscale x 4 x i8> %0,
<vscale x 4 x i1> %1, <vscale x 4 x i1> %1,
i32 %2) iXLen %2)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vid.nxv8i8( declare <vscale x 8 x i8> @llvm.riscv.vid.nxv8i8(
i32); iXLen);
define <vscale x 8 x i8> @intrinsic_vid_v_nxv8i8(i32 %0) nounwind { define <vscale x 8 x i8> @intrinsic_vid_v_nxv8i8(iXLen %0) nounwind {
; CHECK-LABEL: intrinsic_vid_v_nxv8i8: ; CHECK-LABEL: intrinsic_vid_v_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
; CHECK-NEXT: vid.v v8 ; CHECK-NEXT: vid.v v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vid.nxv8i8( %a = call <vscale x 8 x i8> @llvm.riscv.vid.nxv8i8(
i32 %0) iXLen %0)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vid.mask.nxv8i8( declare <vscale x 8 x i8> @llvm.riscv.vid.mask.nxv8i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); iXLen);
define <vscale x 8 x i8> @intrinsic_vid_mask_v_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i1> %1, i32 %2) nounwind { define <vscale x 8 x i8> @intrinsic_vid_mask_v_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vid_mask_v_nxv8i8: ; CHECK-LABEL: intrinsic_vid_mask_v_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, mu
; CHECK-NEXT: vid.v v8, v0.t ; CHECK-NEXT: vid.v v8, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vid.mask.nxv8i8( %a = call <vscale x 8 x i8> @llvm.riscv.vid.mask.nxv8i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 8 x i1> %1, <vscale x 8 x i1> %1,
i32 %2) iXLen %2)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 16 x i8> @llvm.riscv.vid.nxv16i8( declare <vscale x 16 x i8> @llvm.riscv.vid.nxv16i8(
i32); iXLen);
define <vscale x 16 x i8> @intrinsic_vid_v_nxv16i8(i32 %0) nounwind { define <vscale x 16 x i8> @intrinsic_vid_v_nxv16i8(iXLen %0) nounwind {
; CHECK-LABEL: intrinsic_vid_v_nxv16i8: ; CHECK-LABEL: intrinsic_vid_v_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
; CHECK-NEXT: vid.v v8 ; CHECK-NEXT: vid.v v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vid.nxv16i8( %a = call <vscale x 16 x i8> @llvm.riscv.vid.nxv16i8(
i32 %0) iXLen %0)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
declare <vscale x 16 x i8> @llvm.riscv.vid.mask.nxv16i8( declare <vscale x 16 x i8> @llvm.riscv.vid.mask.nxv16i8(
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); iXLen);
define <vscale x 16 x i8> @intrinsic_vid_mask_v_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i1> %1, i32 %2) nounwind { define <vscale x 16 x i8> @intrinsic_vid_mask_v_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vid_mask_v_nxv16i8: ; CHECK-LABEL: intrinsic_vid_mask_v_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m2, tu, mu
; CHECK-NEXT: vid.v v8, v0.t ; CHECK-NEXT: vid.v v8, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vid.mask.nxv16i8( %a = call <vscale x 16 x i8> @llvm.riscv.vid.mask.nxv16i8(
<vscale x 16 x i8> %0, <vscale x 16 x i8> %0,
<vscale x 16 x i1> %1, <vscale x 16 x i1> %1,
i32 %2) iXLen %2)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
declare <vscale x 32 x i8> @llvm.riscv.vid.nxv32i8( declare <vscale x 32 x i8> @llvm.riscv.vid.nxv32i8(
i32); iXLen);
define <vscale x 32 x i8> @intrinsic_vid_v_nxv32i8(i32 %0) nounwind { define <vscale x 32 x i8> @intrinsic_vid_v_nxv32i8(iXLen %0) nounwind {
; CHECK-LABEL: intrinsic_vid_v_nxv32i8: ; CHECK-LABEL: intrinsic_vid_v_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
; CHECK-NEXT: vid.v v8 ; CHECK-NEXT: vid.v v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vid.nxv32i8( %a = call <vscale x 32 x i8> @llvm.riscv.vid.nxv32i8(
i32 %0) iXLen %0)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
declare <vscale x 32 x i8> @llvm.riscv.vid.mask.nxv32i8( declare <vscale x 32 x i8> @llvm.riscv.vid.mask.nxv32i8(
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); iXLen);
define <vscale x 32 x i8> @intrinsic_vid_mask_v_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i1> %1, i32 %2) nounwind { define <vscale x 32 x i8> @intrinsic_vid_mask_v_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vid_mask_v_nxv32i8: ; CHECK-LABEL: intrinsic_vid_mask_v_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m4, tu, mu
; CHECK-NEXT: vid.v v8, v0.t ; CHECK-NEXT: vid.v v8, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vid.mask.nxv32i8( %a = call <vscale x 32 x i8> @llvm.riscv.vid.mask.nxv32i8(
<vscale x 32 x i8> %0, <vscale x 32 x i8> %0,
<vscale x 32 x i1> %1, <vscale x 32 x i1> %1,
i32 %2) iXLen %2)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vid.nxv1i16( declare <vscale x 1 x i16> @llvm.riscv.vid.nxv1i16(
i32); iXLen);
define <vscale x 1 x i16> @intrinsic_vid_v_nxv1i16(i32 %0) nounwind { define <vscale x 1 x i16> @intrinsic_vid_v_nxv1i16(iXLen %0) nounwind {
; CHECK-LABEL: intrinsic_vid_v_nxv1i16: ; CHECK-LABEL: intrinsic_vid_v_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
; CHECK-NEXT: vid.v v8 ; CHECK-NEXT: vid.v v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vid.nxv1i16( %a = call <vscale x 1 x i16> @llvm.riscv.vid.nxv1i16(
i32 %0) iXLen %0)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vid.mask.nxv1i16( declare <vscale x 1 x i16> @llvm.riscv.vid.mask.nxv1i16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); iXLen);
define <vscale x 1 x i16> @intrinsic_vid_mask_v_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i1> %1, i32 %2) nounwind { define <vscale x 1 x i16> @intrinsic_vid_mask_v_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vid_mask_v_nxv1i16: ; CHECK-LABEL: intrinsic_vid_mask_v_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu
; CHECK-NEXT: vid.v v8, v0.t ; CHECK-NEXT: vid.v v8, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vid.mask.nxv1i16( %a = call <vscale x 1 x i16> @llvm.riscv.vid.mask.nxv1i16(
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
<vscale x 1 x i1> %1, <vscale x 1 x i1> %1,
i32 %2) iXLen %2)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vid.nxv2i16( declare <vscale x 2 x i16> @llvm.riscv.vid.nxv2i16(
i32); iXLen);
define <vscale x 2 x i16> @intrinsic_vid_v_nxv2i16(i32 %0) nounwind { define <vscale x 2 x i16> @intrinsic_vid_v_nxv2i16(iXLen %0) nounwind {
; CHECK-LABEL: intrinsic_vid_v_nxv2i16: ; CHECK-LABEL: intrinsic_vid_v_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
; CHECK-NEXT: vid.v v8 ; CHECK-NEXT: vid.v v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vid.nxv2i16( %a = call <vscale x 2 x i16> @llvm.riscv.vid.nxv2i16(
i32 %0) iXLen %0)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vid.mask.nxv2i16( declare <vscale x 2 x i16> @llvm.riscv.vid.mask.nxv2i16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); iXLen);
define <vscale x 2 x i16> @intrinsic_vid_mask_v_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i1> %1, i32 %2) nounwind { define <vscale x 2 x i16> @intrinsic_vid_mask_v_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vid_mask_v_nxv2i16: ; CHECK-LABEL: intrinsic_vid_mask_v_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu
; CHECK-NEXT: vid.v v8, v0.t ; CHECK-NEXT: vid.v v8, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vid.mask.nxv2i16( %a = call <vscale x 2 x i16> @llvm.riscv.vid.mask.nxv2i16(
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
<vscale x 2 x i1> %1, <vscale x 2 x i1> %1,
i32 %2) iXLen %2)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vid.nxv4i16( declare <vscale x 4 x i16> @llvm.riscv.vid.nxv4i16(
i32); iXLen);
define <vscale x 4 x i16> @intrinsic_vid_v_nxv4i16(i32 %0) nounwind { define <vscale x 4 x i16> @intrinsic_vid_v_nxv4i16(iXLen %0) nounwind {
; CHECK-LABEL: intrinsic_vid_v_nxv4i16: ; CHECK-LABEL: intrinsic_vid_v_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
; CHECK-NEXT: vid.v v8 ; CHECK-NEXT: vid.v v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vid.nxv4i16( %a = call <vscale x 4 x i16> @llvm.riscv.vid.nxv4i16(
i32 %0) iXLen %0)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vid.mask.nxv4i16( declare <vscale x 4 x i16> @llvm.riscv.vid.mask.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); iXLen);
define <vscale x 4 x i16> @intrinsic_vid_mask_v_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i1> %1, i32 %2) nounwind { define <vscale x 4 x i16> @intrinsic_vid_mask_v_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vid_mask_v_nxv4i16: ; CHECK-LABEL: intrinsic_vid_mask_v_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu
; CHECK-NEXT: vid.v v8, v0.t ; CHECK-NEXT: vid.v v8, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vid.mask.nxv4i16( %a = call <vscale x 4 x i16> @llvm.riscv.vid.mask.nxv4i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 4 x i1> %1, <vscale x 4 x i1> %1,
i32 %2) iXLen %2)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vid.nxv8i16( declare <vscale x 8 x i16> @llvm.riscv.vid.nxv8i16(
i32); iXLen);
define <vscale x 8 x i16> @intrinsic_vid_v_nxv8i16(i32 %0) nounwind { define <vscale x 8 x i16> @intrinsic_vid_v_nxv8i16(iXLen %0) nounwind {
; CHECK-LABEL: intrinsic_vid_v_nxv8i16: ; CHECK-LABEL: intrinsic_vid_v_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
; CHECK-NEXT: vid.v v8 ; CHECK-NEXT: vid.v v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vid.nxv8i16( %a = call <vscale x 8 x i16> @llvm.riscv.vid.nxv8i16(
i32 %0) iXLen %0)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vid.mask.nxv8i16( declare <vscale x 8 x i16> @llvm.riscv.vid.mask.nxv8i16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); iXLen);
define <vscale x 8 x i16> @intrinsic_vid_mask_v_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i1> %1, i32 %2) nounwind { define <vscale x 8 x i16> @intrinsic_vid_mask_v_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vid_mask_v_nxv8i16: ; CHECK-LABEL: intrinsic_vid_mask_v_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu
; CHECK-NEXT: vid.v v8, v0.t ; CHECK-NEXT: vid.v v8, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vid.mask.nxv8i16( %a = call <vscale x 8 x i16> @llvm.riscv.vid.mask.nxv8i16(
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
<vscale x 8 x i1> %1, <vscale x 8 x i1> %1,
i32 %2) iXLen %2)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vid.nxv16i16( declare <vscale x 16 x i16> @llvm.riscv.vid.nxv16i16(
i32); iXLen);
define <vscale x 16 x i16> @intrinsic_vid_v_nxv16i16(i32 %0) nounwind { define <vscale x 16 x i16> @intrinsic_vid_v_nxv16i16(iXLen %0) nounwind {
; CHECK-LABEL: intrinsic_vid_v_nxv16i16: ; CHECK-LABEL: intrinsic_vid_v_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
; CHECK-NEXT: vid.v v8 ; CHECK-NEXT: vid.v v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vid.nxv16i16( %a = call <vscale x 16 x i16> @llvm.riscv.vid.nxv16i16(
i32 %0) iXLen %0)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vid.mask.nxv16i16( declare <vscale x 16 x i16> @llvm.riscv.vid.mask.nxv16i16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); iXLen);
define <vscale x 16 x i16> @intrinsic_vid_mask_v_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i1> %1, i32 %2) nounwind { define <vscale x 16 x i16> @intrinsic_vid_mask_v_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vid_mask_v_nxv16i16: ; CHECK-LABEL: intrinsic_vid_mask_v_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu
; CHECK-NEXT: vid.v v8, v0.t ; CHECK-NEXT: vid.v v8, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vid.mask.nxv16i16( %a = call <vscale x 16 x i16> @llvm.riscv.vid.mask.nxv16i16(
<vscale x 16 x i16> %0, <vscale x 16 x i16> %0,
<vscale x 16 x i1> %1, <vscale x 16 x i1> %1,
i32 %2) iXLen %2)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 32 x i16> @llvm.riscv.vid.nxv32i16( declare <vscale x 32 x i16> @llvm.riscv.vid.nxv32i16(
i32); iXLen);
define <vscale x 32 x i16> @intrinsic_vid_v_nxv32i16(i32 %0) nounwind { define <vscale x 32 x i16> @intrinsic_vid_v_nxv32i16(iXLen %0) nounwind {
; CHECK-LABEL: intrinsic_vid_v_nxv32i16: ; CHECK-LABEL: intrinsic_vid_v_nxv32i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu
; CHECK-NEXT: vid.v v8 ; CHECK-NEXT: vid.v v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vid.nxv32i16( %a = call <vscale x 32 x i16> @llvm.riscv.vid.nxv32i16(
i32 %0) iXLen %0)
ret <vscale x 32 x i16> %a ret <vscale x 32 x i16> %a
} }
declare <vscale x 32 x i16> @llvm.riscv.vid.mask.nxv32i16( declare <vscale x 32 x i16> @llvm.riscv.vid.mask.nxv32i16(
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); iXLen);
define <vscale x 32 x i16> @intrinsic_vid_mask_v_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i1> %1, i32 %2) nounwind { define <vscale x 32 x i16> @intrinsic_vid_mask_v_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vid_mask_v_nxv32i16: ; CHECK-LABEL: intrinsic_vid_mask_v_nxv32i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m8, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m8, tu, mu
; CHECK-NEXT: vid.v v8, v0.t ; CHECK-NEXT: vid.v v8, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vid.mask.nxv32i16( %a = call <vscale x 32 x i16> @llvm.riscv.vid.mask.nxv32i16(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
<vscale x 32 x i1> %1, <vscale x 32 x i1> %1,
i32 %2) iXLen %2)
ret <vscale x 32 x i16> %a ret <vscale x 32 x i16> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vid.nxv1i32( declare <vscale x 1 x i32> @llvm.riscv.vid.nxv1i32(
i32); iXLen);
define <vscale x 1 x i32> @intrinsic_vid_v_nxv1i32(i32 %0) nounwind { define <vscale x 1 x i32> @intrinsic_vid_v_nxv1i32(iXLen %0) nounwind {
; CHECK-LABEL: intrinsic_vid_v_nxv1i32: ; CHECK-LABEL: intrinsic_vid_v_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
; CHECK-NEXT: vid.v v8 ; CHECK-NEXT: vid.v v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vid.nxv1i32( %a = call <vscale x 1 x i32> @llvm.riscv.vid.nxv1i32(
i32 %0) iXLen %0)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vid.mask.nxv1i32( declare <vscale x 1 x i32> @llvm.riscv.vid.mask.nxv1i32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); iXLen);
define <vscale x 1 x i32> @intrinsic_vid_mask_v_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i1> %1, i32 %2) nounwind { define <vscale x 1 x i32> @intrinsic_vid_mask_v_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vid_mask_v_nxv1i32: ; CHECK-LABEL: intrinsic_vid_mask_v_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu
; CHECK-NEXT: vid.v v8, v0.t ; CHECK-NEXT: vid.v v8, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vid.mask.nxv1i32( %a = call <vscale x 1 x i32> @llvm.riscv.vid.mask.nxv1i32(
<vscale x 1 x i32> %0, <vscale x 1 x i32> %0,
<vscale x 1 x i1> %1, <vscale x 1 x i1> %1,
i32 %2) iXLen %2)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vid.nxv2i32( declare <vscale x 2 x i32> @llvm.riscv.vid.nxv2i32(
i32); iXLen);
define <vscale x 2 x i32> @intrinsic_vid_v_nxv2i32(i32 %0) nounwind { define <vscale x 2 x i32> @intrinsic_vid_v_nxv2i32(iXLen %0) nounwind {
; CHECK-LABEL: intrinsic_vid_v_nxv2i32: ; CHECK-LABEL: intrinsic_vid_v_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
; CHECK-NEXT: vid.v v8 ; CHECK-NEXT: vid.v v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vid.nxv2i32( %a = call <vscale x 2 x i32> @llvm.riscv.vid.nxv2i32(
i32 %0) iXLen %0)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vid.mask.nxv2i32( declare <vscale x 2 x i32> @llvm.riscv.vid.mask.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); iXLen);
define <vscale x 2 x i32> @intrinsic_vid_mask_v_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i1> %1, i32 %2) nounwind { define <vscale x 2 x i32> @intrinsic_vid_mask_v_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vid_mask_v_nxv2i32: ; CHECK-LABEL: intrinsic_vid_mask_v_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu
; CHECK-NEXT: vid.v v8, v0.t ; CHECK-NEXT: vid.v v8, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vid.mask.nxv2i32( %a = call <vscale x 2 x i32> @llvm.riscv.vid.mask.nxv2i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 2 x i1> %1, <vscale x 2 x i1> %1,
i32 %2) iXLen %2)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vid.nxv4i32( declare <vscale x 4 x i32> @llvm.riscv.vid.nxv4i32(
i32); iXLen);
define <vscale x 4 x i32> @intrinsic_vid_v_nxv4i32(i32 %0) nounwind { define <vscale x 4 x i32> @intrinsic_vid_v_nxv4i32(iXLen %0) nounwind {
; CHECK-LABEL: intrinsic_vid_v_nxv4i32: ; CHECK-LABEL: intrinsic_vid_v_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
; CHECK-NEXT: vid.v v8 ; CHECK-NEXT: vid.v v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vid.nxv4i32( %a = call <vscale x 4 x i32> @llvm.riscv.vid.nxv4i32(
i32 %0) iXLen %0)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vid.mask.nxv4i32( declare <vscale x 4 x i32> @llvm.riscv.vid.mask.nxv4i32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); iXLen);
define <vscale x 4 x i32> @intrinsic_vid_mask_v_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i1> %1, i32 %2) nounwind { define <vscale x 4 x i32> @intrinsic_vid_mask_v_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vid_mask_v_nxv4i32: ; CHECK-LABEL: intrinsic_vid_mask_v_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu
; CHECK-NEXT: vid.v v8, v0.t ; CHECK-NEXT: vid.v v8, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vid.mask.nxv4i32( %a = call <vscale x 4 x i32> @llvm.riscv.vid.mask.nxv4i32(
<vscale x 4 x i32> %0, <vscale x 4 x i32> %0,
<vscale x 4 x i1> %1, <vscale x 4 x i1> %1,
i32 %2) iXLen %2)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vid.nxv8i32( declare <vscale x 8 x i32> @llvm.riscv.vid.nxv8i32(
i32); iXLen);
define <vscale x 8 x i32> @intrinsic_vid_v_nxv8i32(i32 %0) nounwind { define <vscale x 8 x i32> @intrinsic_vid_v_nxv8i32(iXLen %0) nounwind {
; CHECK-LABEL: intrinsic_vid_v_nxv8i32: ; CHECK-LABEL: intrinsic_vid_v_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
; CHECK-NEXT: vid.v v8 ; CHECK-NEXT: vid.v v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vid.nxv8i32( %a = call <vscale x 8 x i32> @llvm.riscv.vid.nxv8i32(
i32 %0) iXLen %0)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vid.mask.nxv8i32( declare <vscale x 8 x i32> @llvm.riscv.vid.mask.nxv8i32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); iXLen);
define <vscale x 8 x i32> @intrinsic_vid_mask_v_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i1> %1, i32 %2) nounwind { define <vscale x 8 x i32> @intrinsic_vid_mask_v_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vid_mask_v_nxv8i32: ; CHECK-LABEL: intrinsic_vid_mask_v_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu
; CHECK-NEXT: vid.v v8, v0.t ; CHECK-NEXT: vid.v v8, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vid.mask.nxv8i32( %a = call <vscale x 8 x i32> @llvm.riscv.vid.mask.nxv8i32(
<vscale x 8 x i32> %0, <vscale x 8 x i32> %0,
<vscale x 8 x i1> %1, <vscale x 8 x i1> %1,
i32 %2) iXLen %2)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 16 x i32> @llvm.riscv.vid.nxv16i32( declare <vscale x 16 x i32> @llvm.riscv.vid.nxv16i32(
i32); iXLen);
define <vscale x 16 x i32> @intrinsic_vid_v_nxv16i32(i32 %0) nounwind { define <vscale x 16 x i32> @intrinsic_vid_v_nxv16i32(iXLen %0) nounwind {
; CHECK-LABEL: intrinsic_vid_v_nxv16i32: ; CHECK-LABEL: intrinsic_vid_v_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu
; CHECK-NEXT: vid.v v8 ; CHECK-NEXT: vid.v v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vid.nxv16i32( %a = call <vscale x 16 x i32> @llvm.riscv.vid.nxv16i32(
i32 %0) iXLen %0)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
declare <vscale x 16 x i32> @llvm.riscv.vid.mask.nxv16i32( declare <vscale x 16 x i32> @llvm.riscv.vid.mask.nxv16i32(
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); iXLen);
define <vscale x 16 x i32> @intrinsic_vid_mask_v_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i1> %1, i32 %2) nounwind { define <vscale x 16 x i32> @intrinsic_vid_mask_v_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vid_mask_v_nxv16i32: ; CHECK-LABEL: intrinsic_vid_mask_v_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m8, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m8, tu, mu
; CHECK-NEXT: vid.v v8, v0.t ; CHECK-NEXT: vid.v v8, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vid.mask.nxv16i32( %a = call <vscale x 16 x i32> @llvm.riscv.vid.mask.nxv16i32(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
<vscale x 16 x i1> %1, <vscale x 16 x i1> %1,
i32 %2) iXLen %2)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vid.nxv1i64( declare <vscale x 1 x i64> @llvm.riscv.vid.nxv1i64(
i32); iXLen);
define <vscale x 1 x i64> @intrinsic_vid_v_nxv1i64(i32 %0) nounwind { define <vscale x 1 x i64> @intrinsic_vid_v_nxv1i64(iXLen %0) nounwind {
; CHECK-LABEL: intrinsic_vid_v_nxv1i64: ; CHECK-LABEL: intrinsic_vid_v_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
; CHECK-NEXT: vid.v v8 ; CHECK-NEXT: vid.v v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vid.nxv1i64( %a = call <vscale x 1 x i64> @llvm.riscv.vid.nxv1i64(
i32 %0) iXLen %0)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vid.mask.nxv1i64( declare <vscale x 1 x i64> @llvm.riscv.vid.mask.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); iXLen);
define <vscale x 1 x i64> @intrinsic_vid_mask_v_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i1> %1, i32 %2) nounwind { define <vscale x 1 x i64> @intrinsic_vid_mask_v_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vid_mask_v_nxv1i64: ; CHECK-LABEL: intrinsic_vid_mask_v_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu
; CHECK-NEXT: vid.v v8, v0.t ; CHECK-NEXT: vid.v v8, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vid.mask.nxv1i64( %a = call <vscale x 1 x i64> @llvm.riscv.vid.mask.nxv1i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 1 x i1> %1, <vscale x 1 x i1> %1,
i32 %2) iXLen %2)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vid.nxv2i64( declare <vscale x 2 x i64> @llvm.riscv.vid.nxv2i64(
i32); iXLen);
define <vscale x 2 x i64> @intrinsic_vid_v_nxv2i64(i32 %0) nounwind { define <vscale x 2 x i64> @intrinsic_vid_v_nxv2i64(iXLen %0) nounwind {
; CHECK-LABEL: intrinsic_vid_v_nxv2i64: ; CHECK-LABEL: intrinsic_vid_v_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
; CHECK-NEXT: vid.v v8 ; CHECK-NEXT: vid.v v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vid.nxv2i64( %a = call <vscale x 2 x i64> @llvm.riscv.vid.nxv2i64(
i32 %0) iXLen %0)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vid.mask.nxv2i64( declare <vscale x 2 x i64> @llvm.riscv.vid.mask.nxv2i64(
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); iXLen);
define <vscale x 2 x i64> @intrinsic_vid_mask_v_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i1> %1, i32 %2) nounwind { define <vscale x 2 x i64> @intrinsic_vid_mask_v_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vid_mask_v_nxv2i64: ; CHECK-LABEL: intrinsic_vid_mask_v_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu
; CHECK-NEXT: vid.v v8, v0.t ; CHECK-NEXT: vid.v v8, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vid.mask.nxv2i64( %a = call <vscale x 2 x i64> @llvm.riscv.vid.mask.nxv2i64(
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
<vscale x 2 x i1> %1, <vscale x 2 x i1> %1,
i32 %2) iXLen %2)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vid.nxv4i64( declare <vscale x 4 x i64> @llvm.riscv.vid.nxv4i64(
i32); iXLen);
define <vscale x 4 x i64> @intrinsic_vid_v_nxv4i64(i32 %0) nounwind { define <vscale x 4 x i64> @intrinsic_vid_v_nxv4i64(iXLen %0) nounwind {
; CHECK-LABEL: intrinsic_vid_v_nxv4i64: ; CHECK-LABEL: intrinsic_vid_v_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
; CHECK-NEXT: vid.v v8 ; CHECK-NEXT: vid.v v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vid.nxv4i64( %a = call <vscale x 4 x i64> @llvm.riscv.vid.nxv4i64(
i32 %0) iXLen %0)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vid.mask.nxv4i64( declare <vscale x 4 x i64> @llvm.riscv.vid.mask.nxv4i64(
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); iXLen);
define <vscale x 4 x i64> @intrinsic_vid_mask_v_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i1> %1, i32 %2) nounwind { define <vscale x 4 x i64> @intrinsic_vid_mask_v_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vid_mask_v_nxv4i64: ; CHECK-LABEL: intrinsic_vid_mask_v_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu
; CHECK-NEXT: vid.v v8, v0.t ; CHECK-NEXT: vid.v v8, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vid.mask.nxv4i64( %a = call <vscale x 4 x i64> @llvm.riscv.vid.mask.nxv4i64(
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
<vscale x 4 x i1> %1, <vscale x 4 x i1> %1,
i32 %2) iXLen %2)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 8 x i64> @llvm.riscv.vid.nxv8i64( declare <vscale x 8 x i64> @llvm.riscv.vid.nxv8i64(
i32); iXLen);
define <vscale x 8 x i64> @intrinsic_vid_v_nxv8i64(i32 %0) nounwind { define <vscale x 8 x i64> @intrinsic_vid_v_nxv8i64(iXLen %0) nounwind {
; CHECK-LABEL: intrinsic_vid_v_nxv8i64: ; CHECK-LABEL: intrinsic_vid_v_nxv8i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu
; CHECK-NEXT: vid.v v8 ; CHECK-NEXT: vid.v v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vid.nxv8i64( %a = call <vscale x 8 x i64> @llvm.riscv.vid.nxv8i64(
i32 %0) iXLen %0)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }
declare <vscale x 8 x i64> @llvm.riscv.vid.mask.nxv8i64( declare <vscale x 8 x i64> @llvm.riscv.vid.mask.nxv8i64(
<vscale x 8 x i64>, <vscale x 8 x i64>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); iXLen);
define <vscale x 8 x i64> @intrinsic_vid_mask_v_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i1> %1, i32 %2) nounwind { define <vscale x 8 x i64> @intrinsic_vid_mask_v_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vid_mask_v_nxv8i64: ; CHECK-LABEL: intrinsic_vid_mask_v_nxv8i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m8, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m8, tu, mu
; CHECK-NEXT: vid.v v8, v0.t ; CHECK-NEXT: vid.v v8, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vid.mask.nxv8i64( %a = call <vscale x 8 x i64> @llvm.riscv.vid.mask.nxv8i64(
<vscale x 8 x i64> %0, <vscale x 8 x i64> %0,
<vscale x 8 x i1> %1, <vscale x 8 x i1> %1,
i32 %2) iXLen %2)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }

llvm/test/CodeGen/RISCV/rvv/viota-rv32.ll

  • This file was moved to llvm/test/CodeGen/RISCV/rvv/viota.ll.

llvm/test/CodeGen/RISCV/rvv/viota-rv64.ll

  • This file was deleted.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs \
; RUN: < %s | FileCheck %s
declare <vscale x 1 x i8> @llvm.riscv.viota.nxv1i8(
<vscale x 1 x i1>,
i64);
define <vscale x 1 x i8> @intrinsic_viota_m_nxv1i8_nxv1i1(<vscale x 1 x i1> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_viota_m_nxv1i8_nxv1i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
; CHECK-NEXT: viota.m v8, v0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i8> @llvm.riscv.viota.nxv1i8(
<vscale x 1 x i1> %0,
i64 %1)
ret <vscale x 1 x i8> %a
}
declare <vscale x 1 x i8> @llvm.riscv.viota.mask.nxv1i8(
<vscale x 1 x i8>,
<vscale x 1 x i1>,
<vscale x 1 x i1>,
i64);
define <vscale x 1 x i8> @intrinsic_viota_mask_m_nxv1i8_nxv1i1(<vscale x 1 x i8> %0, <vscale x 1 x i1> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_viota_mask_m_nxv1i8_nxv1i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, mu
; CHECK-NEXT: viota.m v8, v0, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i8> @llvm.riscv.viota.mask.nxv1i8(
<vscale x 1 x i8> %0,
<vscale x 1 x i1> %1,
<vscale x 1 x i1> %1,
i64 %2)
ret <vscale x 1 x i8> %a
}
declare <vscale x 2 x i8> @llvm.riscv.viota.nxv2i8(
<vscale x 2 x i1>,
i64);
define <vscale x 2 x i8> @intrinsic_viota_m_nxv2i8_nxv2i1(<vscale x 2 x i1> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_viota_m_nxv2i8_nxv2i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
; CHECK-NEXT: viota.m v8, v0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i8> @llvm.riscv.viota.nxv2i8(
<vscale x 2 x i1> %0,
i64 %1)
ret <vscale x 2 x i8> %a
}
declare <vscale x 2 x i8> @llvm.riscv.viota.mask.nxv2i8(
<vscale x 2 x i8>,
<vscale x 2 x i1>,
<vscale x 2 x i1>,
i64);
define <vscale x 2 x i8> @intrinsic_viota_mask_m_nxv2i8_nxv2i1(<vscale x 2 x i8> %0, <vscale x 2 x i1> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_viota_mask_m_nxv2i8_nxv2i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, tu, mu
; CHECK-NEXT: viota.m v8, v0, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i8> @llvm.riscv.viota.mask.nxv2i8(
<vscale x 2 x i8> %0,
<vscale x 2 x i1> %1,
<vscale x 2 x i1> %1,
i64 %2)
ret <vscale x 2 x i8> %a
}
declare <vscale x 4 x i8> @llvm.riscv.viota.nxv4i8(
<vscale x 4 x i1>,
i64);
define <vscale x 4 x i8> @intrinsic_viota_m_nxv4i8_nxv4i1(<vscale x 4 x i1> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_viota_m_nxv4i8_nxv4i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
; CHECK-NEXT: viota.m v8, v0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i8> @llvm.riscv.viota.nxv4i8(
<vscale x 4 x i1> %0,
i64 %1)
ret <vscale x 4 x i8> %a
}
declare <vscale x 4 x i8> @llvm.riscv.viota.mask.nxv4i8(
<vscale x 4 x i8>,
<vscale x 4 x i1>,
<vscale x 4 x i1>,
i64);
define <vscale x 4 x i8> @intrinsic_viota_mask_m_nxv4i8_nxv4i1(<vscale x 4 x i8> %0, <vscale x 4 x i1> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_viota_mask_m_nxv4i8_nxv4i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, mu
; CHECK-NEXT: viota.m v8, v0, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i8> @llvm.riscv.viota.mask.nxv4i8(
<vscale x 4 x i8> %0,
<vscale x 4 x i1> %1,
<vscale x 4 x i1> %1,
i64 %2)
ret <vscale x 4 x i8> %a
}
declare <vscale x 8 x i8> @llvm.riscv.viota.nxv8i8(
<vscale x 8 x i1>,
i64);
define <vscale x 8 x i8> @intrinsic_viota_m_nxv8i8_nxv8i1(<vscale x 8 x i1> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_viota_m_nxv8i8_nxv8i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
; CHECK-NEXT: viota.m v8, v0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i8> @llvm.riscv.viota.nxv8i8(
<vscale x 8 x i1> %0,
i64 %1)
ret <vscale x 8 x i8> %a
}
declare <vscale x 8 x i8> @llvm.riscv.viota.mask.nxv8i8(
<vscale x 8 x i8>,
<vscale x 8 x i1>,
<vscale x 8 x i1>,
i64);
define <vscale x 8 x i8> @intrinsic_viota_mask_m_nxv8i8_nxv8i1(<vscale x 8 x i8> %0, <vscale x 8 x i1> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_viota_mask_m_nxv8i8_nxv8i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, mu
; CHECK-NEXT: viota.m v8, v0, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i8> @llvm.riscv.viota.mask.nxv8i8(
<vscale x 8 x i8> %0,
<vscale x 8 x i1> %1,
<vscale x 8 x i1> %1,
i64 %2)
ret <vscale x 8 x i8> %a
}
declare <vscale x 16 x i8> @llvm.riscv.viota.nxv16i8(
<vscale x 16 x i1>,
i64);
define <vscale x 16 x i8> @intrinsic_viota_m_nxv16i8_nxv16i1(<vscale x 16 x i1> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_viota_m_nxv16i8_nxv16i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
; CHECK-NEXT: viota.m v8, v0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i8> @llvm.riscv.viota.nxv16i8(
<vscale x 16 x i1> %0,
i64 %1)
ret <vscale x 16 x i8> %a
}
declare <vscale x 16 x i8> @llvm.riscv.viota.mask.nxv16i8(
<vscale x 16 x i8>,
<vscale x 16 x i1>,
<vscale x 16 x i1>,
i64);
define <vscale x 16 x i8> @intrinsic_viota_mask_m_nxv16i8_nxv16i1(<vscale x 16 x i8> %0, <vscale x 16 x i1> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_viota_mask_m_nxv16i8_nxv16i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, tu, mu
; CHECK-NEXT: viota.m v8, v0, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i8> @llvm.riscv.viota.mask.nxv16i8(
<vscale x 16 x i8> %0,
<vscale x 16 x i1> %1,
<vscale x 16 x i1> %1,
i64 %2)
ret <vscale x 16 x i8> %a
}
declare <vscale x 32 x i8> @llvm.riscv.viota.nxv32i8(
<vscale x 32 x i1>,
i64);
define <vscale x 32 x i8> @intrinsic_viota_m_nxv32i8_nxv32i1(<vscale x 32 x i1> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_viota_m_nxv32i8_nxv32i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
; CHECK-NEXT: viota.m v8, v0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i8> @llvm.riscv.viota.nxv32i8(
<vscale x 32 x i1> %0,
i64 %1)
ret <vscale x 32 x i8> %a
}
declare <vscale x 32 x i8> @llvm.riscv.viota.mask.nxv32i8(
<vscale x 32 x i8>,
<vscale x 32 x i1>,
<vscale x 32 x i1>,
i64);
define <vscale x 32 x i8> @intrinsic_viota_mask_m_nxv32i8_nxv32i1(<vscale x 32 x i8> %0, <vscale x 32 x i1> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_viota_mask_m_nxv32i8_nxv32i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, tu, mu
; CHECK-NEXT: viota.m v8, v0, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i8> @llvm.riscv.viota.mask.nxv32i8(
<vscale x 32 x i8> %0,
<vscale x 32 x i1> %1,
<vscale x 32 x i1> %1,
i64 %2)
ret <vscale x 32 x i8> %a
}
declare <vscale x 64 x i8> @llvm.riscv.viota.nxv64i8(
<vscale x 64 x i1>,
i64);
define <vscale x 64 x i8> @intrinsic_viota_m_nxv64i8_nxv64i1(<vscale x 64 x i1> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_viota_m_nxv64i8_nxv64i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu
; CHECK-NEXT: viota.m v8, v0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 64 x i8> @llvm.riscv.viota.nxv64i8(
<vscale x 64 x i1> %0,
i64 %1)
ret <vscale x 64 x i8> %a
}
declare <vscale x 64 x i8> @llvm.riscv.viota.mask.nxv64i8(
<vscale x 64 x i8>,
<vscale x 64 x i1>,
<vscale x 64 x i1>,
i64);
define <vscale x 64 x i8> @intrinsic_viota_mask_m_nxv64i8_nxv64i1(<vscale x 64 x i8> %0, <vscale x 64 x i1> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_viota_mask_m_nxv64i8_nxv64i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m8, tu, mu
; CHECK-NEXT: viota.m v8, v0, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 64 x i8> @llvm.riscv.viota.mask.nxv64i8(
<vscale x 64 x i8> %0,
<vscale x 64 x i1> %1,
<vscale x 64 x i1> %1,
i64 %2)
ret <vscale x 64 x i8> %a
}
declare <vscale x 1 x i16> @llvm.riscv.viota.nxv1i16(
<vscale x 1 x i1>,
i64);
define <vscale x 1 x i16> @intrinsic_viota_m_nxv1i16_nxv1i1(<vscale x 1 x i1> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_viota_m_nxv1i16_nxv1i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
; CHECK-NEXT: viota.m v8, v0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.viota.nxv1i16(
<vscale x 1 x i1> %0,
i64 %1)
ret <vscale x 1 x i16> %a
}
declare <vscale x 1 x i16> @llvm.riscv.viota.mask.nxv1i16(
<vscale x 1 x i16>,
<vscale x 1 x i1>,
<vscale x 1 x i1>,
i64);
define <vscale x 1 x i16> @intrinsic_viota_mask_m_nxv1i16_nxv1i1(<vscale x 1 x i16> %0, <vscale x 1 x i1> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_viota_mask_m_nxv1i16_nxv1i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu
; CHECK-NEXT: viota.m v8, v0, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.viota.mask.nxv1i16(
<vscale x 1 x i16> %0,
<vscale x 1 x i1> %1,
<vscale x 1 x i1> %1,
i64 %2)
ret <vscale x 1 x i16> %a
}
declare <vscale x 2 x i16> @llvm.riscv.viota.nxv2i16(
<vscale x 2 x i1>,
i64);
define <vscale x 2 x i16> @intrinsic_viota_m_nxv2i16_nxv2i1(<vscale x 2 x i1> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_viota_m_nxv2i16_nxv2i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
; CHECK-NEXT: viota.m v8, v0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.viota.nxv2i16(
<vscale x 2 x i1> %0,
i64 %1)
ret <vscale x 2 x i16> %a
}
declare <vscale x 2 x i16> @llvm.riscv.viota.mask.nxv2i16(
<vscale x 2 x i16>,
<vscale x 2 x i1>,
<vscale x 2 x i1>,
i64);
define <vscale x 2 x i16> @intrinsic_viota_mask_m_nxv2i16_nxv2i1(<vscale x 2 x i16> %0, <vscale x 2 x i1> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_viota_mask_m_nxv2i16_nxv2i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu
; CHECK-NEXT: viota.m v8, v0, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.viota.mask.nxv2i16(
<vscale x 2 x i16> %0,
<vscale x 2 x i1> %1,
<vscale x 2 x i1> %1,
i64 %2)
ret <vscale x 2 x i16> %a
}
declare <vscale x 4 x i16> @llvm.riscv.viota.nxv4i16(
<vscale x 4 x i1>,
i64);
define <vscale x 4 x i16> @intrinsic_viota_m_nxv4i16_nxv4i1(<vscale x 4 x i1> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_viota_m_nxv4i16_nxv4i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
; CHECK-NEXT: viota.m v8, v0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.viota.nxv4i16(
<vscale x 4 x i1> %0,
i64 %1)
ret <vscale x 4 x i16> %a
}
declare <vscale x 4 x i16> @llvm.riscv.viota.mask.nxv4i16(
<vscale x 4 x i16>,
<vscale x 4 x i1>,
<vscale x 4 x i1>,
i64);
define <vscale x 4 x i16> @intrinsic_viota_mask_m_nxv4i16_nxv4i1(<vscale x 4 x i16> %0, <vscale x 4 x i1> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_viota_mask_m_nxv4i16_nxv4i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu
; CHECK-NEXT: viota.m v8, v0, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.viota.mask.nxv4i16(
<vscale x 4 x i16> %0,
<vscale x 4 x i1> %1,
<vscale x 4 x i1> %1,
i64 %2)
ret <vscale x 4 x i16> %a
}
declare <vscale x 8 x i16> @llvm.riscv.viota.nxv8i16(
<vscale x 8 x i1>,
i64);
define <vscale x 8 x i16> @intrinsic_viota_m_nxv8i16_nxv8i1(<vscale x 8 x i1> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_viota_m_nxv8i16_nxv8i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
; CHECK-NEXT: viota.m v8, v0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.viota.nxv8i16(
<vscale x 8 x i1> %0,
i64 %1)
ret <vscale x 8 x i16> %a
}
declare <vscale x 8 x i16> @llvm.riscv.viota.mask.nxv8i16(
<vscale x 8 x i16>,
<vscale x 8 x i1>,
<vscale x 8 x i1>,
i64);
define <vscale x 8 x i16> @intrinsic_viota_mask_m_nxv8i16_nxv8i1(<vscale x 8 x i16> %0, <vscale x 8 x i1> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_viota_mask_m_nxv8i16_nxv8i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu
; CHECK-NEXT: viota.m v8, v0, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.viota.mask.nxv8i16(
<vscale x 8 x i16> %0,
<vscale x 8 x i1> %1,
<vscale x 8 x i1> %1,
i64 %2)
ret <vscale x 8 x i16> %a
}
declare <vscale x 16 x i16> @llvm.riscv.viota.nxv16i16(
<vscale x 16 x i1>,
i64);
define <vscale x 16 x i16> @intrinsic_viota_m_nxv16i16_nxv16i1(<vscale x 16 x i1> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_viota_m_nxv16i16_nxv16i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
; CHECK-NEXT: viota.m v8, v0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.viota.nxv16i16(
<vscale x 16 x i1> %0,
i64 %1)
ret <vscale x 16 x i16> %a
}
declare <vscale x 16 x i16> @llvm.riscv.viota.mask.nxv16i16(
<vscale x 16 x i16>,
<vscale x 16 x i1>,
<vscale x 16 x i1>,
i64);
define <vscale x 16 x i16> @intrinsic_viota_mask_m_nxv16i16_nxv16i1(<vscale x 16 x i16> %0, <vscale x 16 x i1> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_viota_mask_m_nxv16i16_nxv16i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu
; CHECK-NEXT: viota.m v8, v0, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.viota.mask.nxv16i16(
<vscale x 16 x i16> %0,
<vscale x 16 x i1> %1,
<vscale x 16 x i1> %1,
i64 %2)
ret <vscale x 16 x i16> %a
}
declare <vscale x 32 x i16> @llvm.riscv.viota.nxv32i16(
<vscale x 32 x i1>,
i64);
define <vscale x 32 x i16> @intrinsic_viota_m_nxv32i16_nxv32i1(<vscale x 32 x i1> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_viota_m_nxv32i16_nxv32i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu
; CHECK-NEXT: viota.m v8, v0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i16> @llvm.riscv.viota.nxv32i16(
<vscale x 32 x i1> %0,
i64 %1)
ret <vscale x 32 x i16> %a
}
declare <vscale x 32 x i16> @llvm.riscv.viota.mask.nxv32i16(
<vscale x 32 x i16>,
<vscale x 32 x i1>,
<vscale x 32 x i1>,
i64);
define <vscale x 32 x i16> @intrinsic_viota_mask_m_nxv32i16_nxv32i1(<vscale x 32 x i16> %0, <vscale x 32 x i1> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_viota_mask_m_nxv32i16_nxv32i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m8, tu, mu
; CHECK-NEXT: viota.m v8, v0, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i16> @llvm.riscv.viota.mask.nxv32i16(
<vscale x 32 x i16> %0,
<vscale x 32 x i1> %1,
<vscale x 32 x i1> %1,
i64 %2)
ret <vscale x 32 x i16> %a
}
declare <vscale x 1 x i32> @llvm.riscv.viota.nxv1i32(
<vscale x 1 x i1>,
i64);
define <vscale x 1 x i32> @intrinsic_viota_m_nxv1i32_nxv1i1(<vscale x 1 x i1> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_viota_m_nxv1i32_nxv1i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
; CHECK-NEXT: viota.m v8, v0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.viota.nxv1i32(
<vscale x 1 x i1> %0,
i64 %1)
ret <vscale x 1 x i32> %a
}
declare <vscale x 1 x i32> @llvm.riscv.viota.mask.nxv1i32(
<vscale x 1 x i32>,
<vscale x 1 x i1>,
<vscale x 1 x i1>,
i64);
define <vscale x 1 x i32> @intrinsic_viota_mask_m_nxv1i32_nxv1i1(<vscale x 1 x i32> %0, <vscale x 1 x i1> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_viota_mask_m_nxv1i32_nxv1i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu
; CHECK-NEXT: viota.m v8, v0, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.viota.mask.nxv1i32(
<vscale x 1 x i32> %0,
<vscale x 1 x i1> %1,
<vscale x 1 x i1> %1,
i64 %2)
ret <vscale x 1 x i32> %a
}
declare <vscale x 2 x i32> @llvm.riscv.viota.nxv2i32(
<vscale x 2 x i1>,
i64);
define <vscale x 2 x i32> @intrinsic_viota_m_nxv2i32_nxv2i1(<vscale x 2 x i1> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_viota_m_nxv2i32_nxv2i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
; CHECK-NEXT: viota.m v8, v0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.viota.nxv2i32(
<vscale x 2 x i1> %0,
i64 %1)
ret <vscale x 2 x i32> %a
}
declare <vscale x 2 x i32> @llvm.riscv.viota.mask.nxv2i32(
<vscale x 2 x i32>,
<vscale x 2 x i1>,
<vscale x 2 x i1>,
i64);
define <vscale x 2 x i32> @intrinsic_viota_mask_m_nxv2i32_nxv2i1(<vscale x 2 x i32> %0, <vscale x 2 x i1> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_viota_mask_m_nxv2i32_nxv2i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu
; CHECK-NEXT: viota.m v8, v0, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.viota.mask.nxv2i32(
<vscale x 2 x i32> %0,
<vscale x 2 x i1> %1,
<vscale x 2 x i1> %1,
i64 %2)
ret <vscale x 2 x i32> %a
}
declare <vscale x 4 x i32> @llvm.riscv.viota.nxv4i32(
<vscale x 4 x i1>,
i64);
define <vscale x 4 x i32> @intrinsic_viota_m_nxv4i32_nxv4i1(<vscale x 4 x i1> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_viota_m_nxv4i32_nxv4i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
; CHECK-NEXT: viota.m v8, v0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.viota.nxv4i32(
<vscale x 4 x i1> %0,
i64 %1)
ret <vscale x 4 x i32> %a
}
declare <vscale x 4 x i32> @llvm.riscv.viota.mask.nxv4i32(
<vscale x 4 x i32>,
<vscale x 4 x i1>,
<vscale x 4 x i1>,
i64);
define <vscale x 4 x i32> @intrinsic_viota_mask_m_nxv4i32_nxv4i1(<vscale x 4 x i32> %0, <vscale x 4 x i1> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_viota_mask_m_nxv4i32_nxv4i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu
; CHECK-NEXT: viota.m v8, v0, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.viota.mask.nxv4i32(
<vscale x 4 x i32> %0,
<vscale x 4 x i1> %1,
<vscale x 4 x i1> %1,
i64 %2)
ret <vscale x 4 x i32> %a
}
declare <vscale x 8 x i32> @llvm.riscv.viota.nxv8i32(
<vscale x 8 x i1>,
i64);
define <vscale x 8 x i32> @intrinsic_viota_m_nxv8i32_nxv8i1(<vscale x 8 x i1> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_viota_m_nxv8i32_nxv8i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
; CHECK-NEXT: viota.m v8, v0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.viota.nxv8i32(
<vscale x 8 x i1> %0,
i64 %1)
ret <vscale x 8 x i32> %a
}
declare <vscale x 8 x i32> @llvm.riscv.viota.mask.nxv8i32(
<vscale x 8 x i32>,
<vscale x 8 x i1>,
<vscale x 8 x i1>,
i64);
define <vscale x 8 x i32> @intrinsic_viota_mask_m_nxv8i32_nxv8i1(<vscale x 8 x i32> %0, <vscale x 8 x i1> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_viota_mask_m_nxv8i32_nxv8i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu
; CHECK-NEXT: viota.m v8, v0, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.viota.mask.nxv8i32(
<vscale x 8 x i32> %0,
<vscale x 8 x i1> %1,
<vscale x 8 x i1> %1,
i64 %2)
ret <vscale x 8 x i32> %a
}
declare <vscale x 16 x i32> @llvm.riscv.viota.nxv16i32(
<vscale x 16 x i1>,
i64);
define <vscale x 16 x i32> @intrinsic_viota_m_nxv16i32_nxv16i1(<vscale x 16 x i1> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_viota_m_nxv16i32_nxv16i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu
; CHECK-NEXT: viota.m v8, v0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i32> @llvm.riscv.viota.nxv16i32(
<vscale x 16 x i1> %0,
i64 %1)
ret <vscale x 16 x i32> %a
}
declare <vscale x 16 x i32> @llvm.riscv.viota.mask.nxv16i32(
<vscale x 16 x i32>,
<vscale x 16 x i1>,
<vscale x 16 x i1>,
i64);
define <vscale x 16 x i32> @intrinsic_viota_mask_m_nxv16i32_nxv16i1(<vscale x 16 x i32> %0, <vscale x 16 x i1> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_viota_mask_m_nxv16i32_nxv16i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m8, tu, mu
; CHECK-NEXT: viota.m v8, v0, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i32> @llvm.riscv.viota.mask.nxv16i32(
<vscale x 16 x i32> %0,
<vscale x 16 x i1> %1,
<vscale x 16 x i1> %1,
i64 %2)
ret <vscale x 16 x i32> %a
}
declare <vscale x 1 x i64> @llvm.riscv.viota.nxv1i64(
<vscale x 1 x i1>,
i64);
define <vscale x 1 x i64> @intrinsic_viota_m_nxv1i64_nxv1i1(<vscale x 1 x i1> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_viota_m_nxv1i64_nxv1i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
; CHECK-NEXT: viota.m v8, v0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.viota.nxv1i64(
<vscale x 1 x i1> %0,
i64 %1)
ret <vscale x 1 x i64> %a
}
declare <vscale x 1 x i64> @llvm.riscv.viota.mask.nxv1i64(
<vscale x 1 x i64>,
<vscale x 1 x i1>,
<vscale x 1 x i1>,
i64);
define <vscale x 1 x i64> @intrinsic_viota_mask_m_nxv1i64_nxv1i1(<vscale x 1 x i64> %0, <vscale x 1 x i1> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_viota_mask_m_nxv1i64_nxv1i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu
; CHECK-NEXT: viota.m v8, v0, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.viota.mask.nxv1i64(
<vscale x 1 x i64> %0,
<vscale x 1 x i1> %1,
<vscale x 1 x i1> %1,
i64 %2)
ret <vscale x 1 x i64> %a
}
declare <vscale x 2 x i64> @llvm.riscv.viota.nxv2i64(
<vscale x 2 x i1>,
i64);
define <vscale x 2 x i64> @intrinsic_viota_m_nxv2i64_nxv2i1(<vscale x 2 x i1> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_viota_m_nxv2i64_nxv2i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
; CHECK-NEXT: viota.m v8, v0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.viota.nxv2i64(
<vscale x 2 x i1> %0,
i64 %1)
ret <vscale x 2 x i64> %a
}
declare <vscale x 2 x i64> @llvm.riscv.viota.mask.nxv2i64(
<vscale x 2 x i64>,
<vscale x 2 x i1>,
<vscale x 2 x i1>,
i64);
define <vscale x 2 x i64> @intrinsic_viota_mask_m_nxv2i64_nxv2i1(<vscale x 2 x i64> %0, <vscale x 2 x i1> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_viota_mask_m_nxv2i64_nxv2i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu
; CHECK-NEXT: viota.m v8, v0, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.viota.mask.nxv2i64(
<vscale x 2 x i64> %0,
<vscale x 2 x i1> %1,
<vscale x 2 x i1> %1,
i64 %2)
ret <vscale x 2 x i64> %a
}
declare <vscale x 4 x i64> @llvm.riscv.viota.nxv4i64(
<vscale x 4 x i1>,
i64);
define <vscale x 4 x i64> @intrinsic_viota_m_nxv4i64_nxv4i1(<vscale x 4 x i1> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_viota_m_nxv4i64_nxv4i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
; CHECK-NEXT: viota.m v8, v0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.viota.nxv4i64(
<vscale x 4 x i1> %0,
i64 %1)
ret <vscale x 4 x i64> %a
}
declare <vscale x 4 x i64> @llvm.riscv.viota.mask.nxv4i64(
<vscale x 4 x i64>,
<vscale x 4 x i1>,
<vscale x 4 x i1>,
i64);
define <vscale x 4 x i64> @intrinsic_viota_mask_m_nxv4i64_nxv4i1(<vscale x 4 x i64> %0, <vscale x 4 x i1> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_viota_mask_m_nxv4i64_nxv4i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu
; CHECK-NEXT: viota.m v8, v0, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.viota.mask.nxv4i64(
<vscale x 4 x i64> %0,
<vscale x 4 x i1> %1,
<vscale x 4 x i1> %1,
i64 %2)
ret <vscale x 4 x i64> %a
}
declare <vscale x 8 x i64> @llvm.riscv.viota.nxv8i64(
<vscale x 8 x i1>,
i64);
define <vscale x 8 x i64> @intrinsic_viota_m_nxv8i64_nxv8i1(<vscale x 8 x i1> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_viota_m_nxv8i64_nxv8i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu
; CHECK-NEXT: viota.m v8, v0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i64> @llvm.riscv.viota.nxv8i64(
<vscale x 8 x i1> %0,
i64 %1)
ret <vscale x 8 x i64> %a
}
declare <vscale x 8 x i64> @llvm.riscv.viota.mask.nxv8i64(
<vscale x 8 x i64>,
<vscale x 8 x i1>,
<vscale x 8 x i1>,
i64);
define <vscale x 8 x i64> @intrinsic_viota_mask_m_nxv8i64_nxv8i1(<vscale x 8 x i64> %0, <vscale x 8 x i1> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_viota_mask_m_nxv8i64_nxv8i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m8, tu, mu
; CHECK-NEXT: viota.m v8, v0, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i64> @llvm.riscv.viota.mask.nxv8i64(
<vscale x 8 x i64> %0,
<vscale x 8 x i1> %1,
<vscale x 8 x i1> %1,
i64 %2)
ret <vscale x 8 x i64> %a
}

llvm/test/CodeGen/RISCV/rvv/viota.ll

  • This file was moved from llvm/test/CodeGen/RISCV/rvv/viota-rv32.ll.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs \ ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v \
; RUN: < %s | FileCheck %s ; RUN: -verify-machineinstrs | FileCheck %s
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v \
; RUN: -verify-machineinstrs | FileCheck %s
declare <vscale x 1 x i8> @llvm.riscv.viota.nxv1i8( declare <vscale x 1 x i8> @llvm.riscv.viota.nxv1i8(
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); iXLen);
define <vscale x 1 x i8> @intrinsic_viota_m_nxv1i8_nxv1i1(<vscale x 1 x i1> %0, i32 %1) nounwind { define <vscale x 1 x i8> @intrinsic_viota_m_nxv1i8_nxv1i1(<vscale x 1 x i1> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_viota_m_nxv1i8_nxv1i1: ; CHECK-LABEL: intrinsic_viota_m_nxv1i8_nxv1i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
; CHECK-NEXT: viota.m v8, v0 ; CHECK-NEXT: viota.m v8, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i8> @llvm.riscv.viota.nxv1i8( %a = call <vscale x 1 x i8> @llvm.riscv.viota.nxv1i8(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
i32 %1) iXLen %1)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 1 x i8> @llvm.riscv.viota.mask.nxv1i8( declare <vscale x 1 x i8> @llvm.riscv.viota.mask.nxv1i8(
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); iXLen);
define <vscale x 1 x i8> @intrinsic_viota_mask_m_nxv1i8_nxv1i1(<vscale x 1 x i8> %0, <vscale x 1 x i1> %1, i32 %2) nounwind { define <vscale x 1 x i8> @intrinsic_viota_mask_m_nxv1i8_nxv1i1(<vscale x 1 x i8> %0, <vscale x 1 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_viota_mask_m_nxv1i8_nxv1i1: ; CHECK-LABEL: intrinsic_viota_mask_m_nxv1i8_nxv1i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, mu
; CHECK-NEXT: viota.m v8, v0, v0.t ; CHECK-NEXT: viota.m v8, v0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i8> @llvm.riscv.viota.mask.nxv1i8( %a = call <vscale x 1 x i8> @llvm.riscv.viota.mask.nxv1i8(
<vscale x 1 x i8> %0, <vscale x 1 x i8> %0,
<vscale x 1 x i1> %1, <vscale x 1 x i1> %1,
<vscale x 1 x i1> %1, <vscale x 1 x i1> %1,
i32 %2) iXLen %2)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 2 x i8> @llvm.riscv.viota.nxv2i8( declare <vscale x 2 x i8> @llvm.riscv.viota.nxv2i8(
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); iXLen);
define <vscale x 2 x i8> @intrinsic_viota_m_nxv2i8_nxv2i1(<vscale x 2 x i1> %0, i32 %1) nounwind { define <vscale x 2 x i8> @intrinsic_viota_m_nxv2i8_nxv2i1(<vscale x 2 x i1> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_viota_m_nxv2i8_nxv2i1: ; CHECK-LABEL: intrinsic_viota_m_nxv2i8_nxv2i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
; CHECK-NEXT: viota.m v8, v0 ; CHECK-NEXT: viota.m v8, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i8> @llvm.riscv.viota.nxv2i8( %a = call <vscale x 2 x i8> @llvm.riscv.viota.nxv2i8(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
i32 %1) iXLen %1)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
declare <vscale x 2 x i8> @llvm.riscv.viota.mask.nxv2i8( declare <vscale x 2 x i8> @llvm.riscv.viota.mask.nxv2i8(
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); iXLen);
define <vscale x 2 x i8> @intrinsic_viota_mask_m_nxv2i8_nxv2i1(<vscale x 2 x i8> %0, <vscale x 2 x i1> %1, i32 %2) nounwind { define <vscale x 2 x i8> @intrinsic_viota_mask_m_nxv2i8_nxv2i1(<vscale x 2 x i8> %0, <vscale x 2 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_viota_mask_m_nxv2i8_nxv2i1: ; CHECK-LABEL: intrinsic_viota_mask_m_nxv2i8_nxv2i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, tu, mu
; CHECK-NEXT: viota.m v8, v0, v0.t ; CHECK-NEXT: viota.m v8, v0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i8> @llvm.riscv.viota.mask.nxv2i8( %a = call <vscale x 2 x i8> @llvm.riscv.viota.mask.nxv2i8(
<vscale x 2 x i8> %0, <vscale x 2 x i8> %0,
<vscale x 2 x i1> %1, <vscale x 2 x i1> %1,
<vscale x 2 x i1> %1, <vscale x 2 x i1> %1,
i32 %2) iXLen %2)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
declare <vscale x 4 x i8> @llvm.riscv.viota.nxv4i8( declare <vscale x 4 x i8> @llvm.riscv.viota.nxv4i8(
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); iXLen);
define <vscale x 4 x i8> @intrinsic_viota_m_nxv4i8_nxv4i1(<vscale x 4 x i1> %0, i32 %1) nounwind { define <vscale x 4 x i8> @intrinsic_viota_m_nxv4i8_nxv4i1(<vscale x 4 x i1> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_viota_m_nxv4i8_nxv4i1: ; CHECK-LABEL: intrinsic_viota_m_nxv4i8_nxv4i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
; CHECK-NEXT: viota.m v8, v0 ; CHECK-NEXT: viota.m v8, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i8> @llvm.riscv.viota.nxv4i8( %a = call <vscale x 4 x i8> @llvm.riscv.viota.nxv4i8(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
i32 %1) iXLen %1)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
declare <vscale x 4 x i8> @llvm.riscv.viota.mask.nxv4i8( declare <vscale x 4 x i8> @llvm.riscv.viota.mask.nxv4i8(
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); iXLen);
define <vscale x 4 x i8> @intrinsic_viota_mask_m_nxv4i8_nxv4i1(<vscale x 4 x i8> %0, <vscale x 4 x i1> %1, i32 %2) nounwind { define <vscale x 4 x i8> @intrinsic_viota_mask_m_nxv4i8_nxv4i1(<vscale x 4 x i8> %0, <vscale x 4 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_viota_mask_m_nxv4i8_nxv4i1: ; CHECK-LABEL: intrinsic_viota_mask_m_nxv4i8_nxv4i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, mu
; CHECK-NEXT: viota.m v8, v0, v0.t ; CHECK-NEXT: viota.m v8, v0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i8> @llvm.riscv.viota.mask.nxv4i8( %a = call <vscale x 4 x i8> @llvm.riscv.viota.mask.nxv4i8(
<vscale x 4 x i8> %0, <vscale x 4 x i8> %0,
<vscale x 4 x i1> %1, <vscale x 4 x i1> %1,
<vscale x 4 x i1> %1, <vscale x 4 x i1> %1,
i32 %2) iXLen %2)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.viota.nxv8i8( declare <vscale x 8 x i8> @llvm.riscv.viota.nxv8i8(
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); iXLen);
define <vscale x 8 x i8> @intrinsic_viota_m_nxv8i8_nxv8i1(<vscale x 8 x i1> %0, i32 %1) nounwind { define <vscale x 8 x i8> @intrinsic_viota_m_nxv8i8_nxv8i1(<vscale x 8 x i1> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_viota_m_nxv8i8_nxv8i1: ; CHECK-LABEL: intrinsic_viota_m_nxv8i8_nxv8i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
; CHECK-NEXT: viota.m v8, v0 ; CHECK-NEXT: viota.m v8, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.viota.nxv8i8( %a = call <vscale x 8 x i8> @llvm.riscv.viota.nxv8i8(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
i32 %1) iXLen %1)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.viota.mask.nxv8i8( declare <vscale x 8 x i8> @llvm.riscv.viota.mask.nxv8i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); iXLen);
define <vscale x 8 x i8> @intrinsic_viota_mask_m_nxv8i8_nxv8i1(<vscale x 8 x i8> %0, <vscale x 8 x i1> %1, i32 %2) nounwind { define <vscale x 8 x i8> @intrinsic_viota_mask_m_nxv8i8_nxv8i1(<vscale x 8 x i8> %0, <vscale x 8 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_viota_mask_m_nxv8i8_nxv8i1: ; CHECK-LABEL: intrinsic_viota_mask_m_nxv8i8_nxv8i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, mu
; CHECK-NEXT: viota.m v8, v0, v0.t ; CHECK-NEXT: viota.m v8, v0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.viota.mask.nxv8i8( %a = call <vscale x 8 x i8> @llvm.riscv.viota.mask.nxv8i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 8 x i1> %1, <vscale x 8 x i1> %1,
<vscale x 8 x i1> %1, <vscale x 8 x i1> %1,
i32 %2) iXLen %2)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 16 x i8> @llvm.riscv.viota.nxv16i8( declare <vscale x 16 x i8> @llvm.riscv.viota.nxv16i8(
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); iXLen);
define <vscale x 16 x i8> @intrinsic_viota_m_nxv16i8_nxv16i1(<vscale x 16 x i1> %0, i32 %1) nounwind { define <vscale x 16 x i8> @intrinsic_viota_m_nxv16i8_nxv16i1(<vscale x 16 x i1> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_viota_m_nxv16i8_nxv16i1: ; CHECK-LABEL: intrinsic_viota_m_nxv16i8_nxv16i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
; CHECK-NEXT: viota.m v8, v0 ; CHECK-NEXT: viota.m v8, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i8> @llvm.riscv.viota.nxv16i8( %a = call <vscale x 16 x i8> @llvm.riscv.viota.nxv16i8(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
i32 %1) iXLen %1)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
declare <vscale x 16 x i8> @llvm.riscv.viota.mask.nxv16i8( declare <vscale x 16 x i8> @llvm.riscv.viota.mask.nxv16i8(
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); iXLen);
define <vscale x 16 x i8> @intrinsic_viota_mask_m_nxv16i8_nxv16i1(<vscale x 16 x i8> %0, <vscale x 16 x i1> %1, i32 %2) nounwind { define <vscale x 16 x i8> @intrinsic_viota_mask_m_nxv16i8_nxv16i1(<vscale x 16 x i8> %0, <vscale x 16 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_viota_mask_m_nxv16i8_nxv16i1: ; CHECK-LABEL: intrinsic_viota_mask_m_nxv16i8_nxv16i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m2, tu, mu
; CHECK-NEXT: viota.m v8, v0, v0.t ; CHECK-NEXT: viota.m v8, v0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i8> @llvm.riscv.viota.mask.nxv16i8( %a = call <vscale x 16 x i8> @llvm.riscv.viota.mask.nxv16i8(
<vscale x 16 x i8> %0, <vscale x 16 x i8> %0,
<vscale x 16 x i1> %1, <vscale x 16 x i1> %1,
<vscale x 16 x i1> %1, <vscale x 16 x i1> %1,
i32 %2) iXLen %2)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
declare <vscale x 32 x i8> @llvm.riscv.viota.nxv32i8( declare <vscale x 32 x i8> @llvm.riscv.viota.nxv32i8(
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); iXLen);
define <vscale x 32 x i8> @intrinsic_viota_m_nxv32i8_nxv32i1(<vscale x 32 x i1> %0, i32 %1) nounwind { define <vscale x 32 x i8> @intrinsic_viota_m_nxv32i8_nxv32i1(<vscale x 32 x i1> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_viota_m_nxv32i8_nxv32i1: ; CHECK-LABEL: intrinsic_viota_m_nxv32i8_nxv32i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
; CHECK-NEXT: viota.m v8, v0 ; CHECK-NEXT: viota.m v8, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i8> @llvm.riscv.viota.nxv32i8( %a = call <vscale x 32 x i8> @llvm.riscv.viota.nxv32i8(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
i32 %1) iXLen %1)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
declare <vscale x 32 x i8> @llvm.riscv.viota.mask.nxv32i8( declare <vscale x 32 x i8> @llvm.riscv.viota.mask.nxv32i8(
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); iXLen);
define <vscale x 32 x i8> @intrinsic_viota_mask_m_nxv32i8_nxv32i1(<vscale x 32 x i8> %0, <vscale x 32 x i1> %1, i32 %2) nounwind { define <vscale x 32 x i8> @intrinsic_viota_mask_m_nxv32i8_nxv32i1(<vscale x 32 x i8> %0, <vscale x 32 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_viota_mask_m_nxv32i8_nxv32i1: ; CHECK-LABEL: intrinsic_viota_mask_m_nxv32i8_nxv32i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m4, tu, mu
; CHECK-NEXT: viota.m v8, v0, v0.t ; CHECK-NEXT: viota.m v8, v0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i8> @llvm.riscv.viota.mask.nxv32i8( %a = call <vscale x 32 x i8> @llvm.riscv.viota.mask.nxv32i8(
<vscale x 32 x i8> %0, <vscale x 32 x i8> %0,
<vscale x 32 x i1> %1, <vscale x 32 x i1> %1,
<vscale x 32 x i1> %1, <vscale x 32 x i1> %1,
i32 %2) iXLen %2)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
declare <vscale x 64 x i8> @llvm.riscv.viota.nxv64i8( declare <vscale x 64 x i8> @llvm.riscv.viota.nxv64i8(
<vscale x 64 x i1>, <vscale x 64 x i1>,
i32); iXLen);
define <vscale x 64 x i8> @intrinsic_viota_m_nxv64i8_nxv64i1(<vscale x 64 x i1> %0, i32 %1) nounwind { define <vscale x 64 x i8> @intrinsic_viota_m_nxv64i8_nxv64i1(<vscale x 64 x i1> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_viota_m_nxv64i8_nxv64i1: ; CHECK-LABEL: intrinsic_viota_m_nxv64i8_nxv64i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu
; CHECK-NEXT: viota.m v8, v0 ; CHECK-NEXT: viota.m v8, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 64 x i8> @llvm.riscv.viota.nxv64i8( %a = call <vscale x 64 x i8> @llvm.riscv.viota.nxv64i8(
<vscale x 64 x i1> %0, <vscale x 64 x i1> %0,
i32 %1) iXLen %1)
ret <vscale x 64 x i8> %a ret <vscale x 64 x i8> %a
} }
declare <vscale x 64 x i8> @llvm.riscv.viota.mask.nxv64i8( declare <vscale x 64 x i8> @llvm.riscv.viota.mask.nxv64i8(
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 64 x i1>, <vscale x 64 x i1>,
<vscale x 64 x i1>, <vscale x 64 x i1>,
i32); iXLen);
define <vscale x 64 x i8> @intrinsic_viota_mask_m_nxv64i8_nxv64i1(<vscale x 64 x i8> %0, <vscale x 64 x i1> %1, i32 %2) nounwind { define <vscale x 64 x i8> @intrinsic_viota_mask_m_nxv64i8_nxv64i1(<vscale x 64 x i8> %0, <vscale x 64 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_viota_mask_m_nxv64i8_nxv64i1: ; CHECK-LABEL: intrinsic_viota_mask_m_nxv64i8_nxv64i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m8, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m8, tu, mu
; CHECK-NEXT: viota.m v8, v0, v0.t ; CHECK-NEXT: viota.m v8, v0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 64 x i8> @llvm.riscv.viota.mask.nxv64i8( %a = call <vscale x 64 x i8> @llvm.riscv.viota.mask.nxv64i8(
<vscale x 64 x i8> %0, <vscale x 64 x i8> %0,
<vscale x 64 x i1> %1, <vscale x 64 x i1> %1,
<vscale x 64 x i1> %1, <vscale x 64 x i1> %1,
i32 %2) iXLen %2)
ret <vscale x 64 x i8> %a ret <vscale x 64 x i8> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.viota.nxv1i16( declare <vscale x 1 x i16> @llvm.riscv.viota.nxv1i16(
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); iXLen);
define <vscale x 1 x i16> @intrinsic_viota_m_nxv1i16_nxv1i1(<vscale x 1 x i1> %0, i32 %1) nounwind { define <vscale x 1 x i16> @intrinsic_viota_m_nxv1i16_nxv1i1(<vscale x 1 x i1> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_viota_m_nxv1i16_nxv1i1: ; CHECK-LABEL: intrinsic_viota_m_nxv1i16_nxv1i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
; CHECK-NEXT: viota.m v8, v0 ; CHECK-NEXT: viota.m v8, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.viota.nxv1i16( %a = call <vscale x 1 x i16> @llvm.riscv.viota.nxv1i16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
i32 %1) iXLen %1)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.viota.mask.nxv1i16( declare <vscale x 1 x i16> @llvm.riscv.viota.mask.nxv1i16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); iXLen);
define <vscale x 1 x i16> @intrinsic_viota_mask_m_nxv1i16_nxv1i1(<vscale x 1 x i16> %0, <vscale x 1 x i1> %1, i32 %2) nounwind { define <vscale x 1 x i16> @intrinsic_viota_mask_m_nxv1i16_nxv1i1(<vscale x 1 x i16> %0, <vscale x 1 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_viota_mask_m_nxv1i16_nxv1i1: ; CHECK-LABEL: intrinsic_viota_mask_m_nxv1i16_nxv1i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu
; CHECK-NEXT: viota.m v8, v0, v0.t ; CHECK-NEXT: viota.m v8, v0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.viota.mask.nxv1i16( %a = call <vscale x 1 x i16> @llvm.riscv.viota.mask.nxv1i16(
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
<vscale x 1 x i1> %1, <vscale x 1 x i1> %1,
<vscale x 1 x i1> %1, <vscale x 1 x i1> %1,
i32 %2) iXLen %2)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.viota.nxv2i16( declare <vscale x 2 x i16> @llvm.riscv.viota.nxv2i16(
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); iXLen);
define <vscale x 2 x i16> @intrinsic_viota_m_nxv2i16_nxv2i1(<vscale x 2 x i1> %0, i32 %1) nounwind { define <vscale x 2 x i16> @intrinsic_viota_m_nxv2i16_nxv2i1(<vscale x 2 x i1> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_viota_m_nxv2i16_nxv2i1: ; CHECK-LABEL: intrinsic_viota_m_nxv2i16_nxv2i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
; CHECK-NEXT: viota.m v8, v0 ; CHECK-NEXT: viota.m v8, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.viota.nxv2i16( %a = call <vscale x 2 x i16> @llvm.riscv.viota.nxv2i16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
i32 %1) iXLen %1)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.viota.mask.nxv2i16( declare <vscale x 2 x i16> @llvm.riscv.viota.mask.nxv2i16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); iXLen);
define <vscale x 2 x i16> @intrinsic_viota_mask_m_nxv2i16_nxv2i1(<vscale x 2 x i16> %0, <vscale x 2 x i1> %1, i32 %2) nounwind { define <vscale x 2 x i16> @intrinsic_viota_mask_m_nxv2i16_nxv2i1(<vscale x 2 x i16> %0, <vscale x 2 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_viota_mask_m_nxv2i16_nxv2i1: ; CHECK-LABEL: intrinsic_viota_mask_m_nxv2i16_nxv2i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu
; CHECK-NEXT: viota.m v8, v0, v0.t ; CHECK-NEXT: viota.m v8, v0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.viota.mask.nxv2i16( %a = call <vscale x 2 x i16> @llvm.riscv.viota.mask.nxv2i16(
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
<vscale x 2 x i1> %1, <vscale x 2 x i1> %1,
<vscale x 2 x i1> %1, <vscale x 2 x i1> %1,
i32 %2) iXLen %2)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.viota.nxv4i16( declare <vscale x 4 x i16> @llvm.riscv.viota.nxv4i16(
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); iXLen);
define <vscale x 4 x i16> @intrinsic_viota_m_nxv4i16_nxv4i1(<vscale x 4 x i1> %0, i32 %1) nounwind { define <vscale x 4 x i16> @intrinsic_viota_m_nxv4i16_nxv4i1(<vscale x 4 x i1> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_viota_m_nxv4i16_nxv4i1: ; CHECK-LABEL: intrinsic_viota_m_nxv4i16_nxv4i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
; CHECK-NEXT: viota.m v8, v0 ; CHECK-NEXT: viota.m v8, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.viota.nxv4i16( %a = call <vscale x 4 x i16> @llvm.riscv.viota.nxv4i16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
i32 %1) iXLen %1)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.viota.mask.nxv4i16( declare <vscale x 4 x i16> @llvm.riscv.viota.mask.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); iXLen);
define <vscale x 4 x i16> @intrinsic_viota_mask_m_nxv4i16_nxv4i1(<vscale x 4 x i16> %0, <vscale x 4 x i1> %1, i32 %2) nounwind { define <vscale x 4 x i16> @intrinsic_viota_mask_m_nxv4i16_nxv4i1(<vscale x 4 x i16> %0, <vscale x 4 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_viota_mask_m_nxv4i16_nxv4i1: ; CHECK-LABEL: intrinsic_viota_mask_m_nxv4i16_nxv4i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu
; CHECK-NEXT: viota.m v8, v0, v0.t ; CHECK-NEXT: viota.m v8, v0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.viota.mask.nxv4i16( %a = call <vscale x 4 x i16> @llvm.riscv.viota.mask.nxv4i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 4 x i1> %1, <vscale x 4 x i1> %1,
<vscale x 4 x i1> %1, <vscale x 4 x i1> %1,
i32 %2) iXLen %2)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.viota.nxv8i16( declare <vscale x 8 x i16> @llvm.riscv.viota.nxv8i16(
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); iXLen);
define <vscale x 8 x i16> @intrinsic_viota_m_nxv8i16_nxv8i1(<vscale x 8 x i1> %0, i32 %1) nounwind { define <vscale x 8 x i16> @intrinsic_viota_m_nxv8i16_nxv8i1(<vscale x 8 x i1> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_viota_m_nxv8i16_nxv8i1: ; CHECK-LABEL: intrinsic_viota_m_nxv8i16_nxv8i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
; CHECK-NEXT: viota.m v8, v0 ; CHECK-NEXT: viota.m v8, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.viota.nxv8i16( %a = call <vscale x 8 x i16> @llvm.riscv.viota.nxv8i16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
i32 %1) iXLen %1)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.viota.mask.nxv8i16( declare <vscale x 8 x i16> @llvm.riscv.viota.mask.nxv8i16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); iXLen);
define <vscale x 8 x i16> @intrinsic_viota_mask_m_nxv8i16_nxv8i1(<vscale x 8 x i16> %0, <vscale x 8 x i1> %1, i32 %2) nounwind { define <vscale x 8 x i16> @intrinsic_viota_mask_m_nxv8i16_nxv8i1(<vscale x 8 x i16> %0, <vscale x 8 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_viota_mask_m_nxv8i16_nxv8i1: ; CHECK-LABEL: intrinsic_viota_mask_m_nxv8i16_nxv8i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu
; CHECK-NEXT: viota.m v8, v0, v0.t ; CHECK-NEXT: viota.m v8, v0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.viota.mask.nxv8i16( %a = call <vscale x 8 x i16> @llvm.riscv.viota.mask.nxv8i16(
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
<vscale x 8 x i1> %1, <vscale x 8 x i1> %1,
<vscale x 8 x i1> %1, <vscale x 8 x i1> %1,
i32 %2) iXLen %2)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.viota.nxv16i16( declare <vscale x 16 x i16> @llvm.riscv.viota.nxv16i16(
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); iXLen);
define <vscale x 16 x i16> @intrinsic_viota_m_nxv16i16_nxv16i1(<vscale x 16 x i1> %0, i32 %1) nounwind { define <vscale x 16 x i16> @intrinsic_viota_m_nxv16i16_nxv16i1(<vscale x 16 x i1> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_viota_m_nxv16i16_nxv16i1: ; CHECK-LABEL: intrinsic_viota_m_nxv16i16_nxv16i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
; CHECK-NEXT: viota.m v8, v0 ; CHECK-NEXT: viota.m v8, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.viota.nxv16i16( %a = call <vscale x 16 x i16> @llvm.riscv.viota.nxv16i16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
i32 %1) iXLen %1)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.viota.mask.nxv16i16( declare <vscale x 16 x i16> @llvm.riscv.viota.mask.nxv16i16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); iXLen);
define <vscale x 16 x i16> @intrinsic_viota_mask_m_nxv16i16_nxv16i1(<vscale x 16 x i16> %0, <vscale x 16 x i1> %1, i32 %2) nounwind { define <vscale x 16 x i16> @intrinsic_viota_mask_m_nxv16i16_nxv16i1(<vscale x 16 x i16> %0, <vscale x 16 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_viota_mask_m_nxv16i16_nxv16i1: ; CHECK-LABEL: intrinsic_viota_mask_m_nxv16i16_nxv16i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu
; CHECK-NEXT: viota.m v8, v0, v0.t ; CHECK-NEXT: viota.m v8, v0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.viota.mask.nxv16i16( %a = call <vscale x 16 x i16> @llvm.riscv.viota.mask.nxv16i16(
<vscale x 16 x i16> %0, <vscale x 16 x i16> %0,
<vscale x 16 x i1> %1, <vscale x 16 x i1> %1,
<vscale x 16 x i1> %1, <vscale x 16 x i1> %1,
i32 %2) iXLen %2)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 32 x i16> @llvm.riscv.viota.nxv32i16( declare <vscale x 32 x i16> @llvm.riscv.viota.nxv32i16(
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); iXLen);
define <vscale x 32 x i16> @intrinsic_viota_m_nxv32i16_nxv32i1(<vscale x 32 x i1> %0, i32 %1) nounwind { define <vscale x 32 x i16> @intrinsic_viota_m_nxv32i16_nxv32i1(<vscale x 32 x i1> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_viota_m_nxv32i16_nxv32i1: ; CHECK-LABEL: intrinsic_viota_m_nxv32i16_nxv32i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu
; CHECK-NEXT: viota.m v8, v0 ; CHECK-NEXT: viota.m v8, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.viota.nxv32i16( %a = call <vscale x 32 x i16> @llvm.riscv.viota.nxv32i16(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
i32 %1) iXLen %1)
ret <vscale x 32 x i16> %a ret <vscale x 32 x i16> %a
} }
declare <vscale x 32 x i16> @llvm.riscv.viota.mask.nxv32i16( declare <vscale x 32 x i16> @llvm.riscv.viota.mask.nxv32i16(
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); iXLen);
define <vscale x 32 x i16> @intrinsic_viota_mask_m_nxv32i16_nxv32i1(<vscale x 32 x i16> %0, <vscale x 32 x i1> %1, i32 %2) nounwind { define <vscale x 32 x i16> @intrinsic_viota_mask_m_nxv32i16_nxv32i1(<vscale x 32 x i16> %0, <vscale x 32 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_viota_mask_m_nxv32i16_nxv32i1: ; CHECK-LABEL: intrinsic_viota_mask_m_nxv32i16_nxv32i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m8, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m8, tu, mu
; CHECK-NEXT: viota.m v8, v0, v0.t ; CHECK-NEXT: viota.m v8, v0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.viota.mask.nxv32i16( %a = call <vscale x 32 x i16> @llvm.riscv.viota.mask.nxv32i16(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
<vscale x 32 x i1> %1, <vscale x 32 x i1> %1,
<vscale x 32 x i1> %1, <vscale x 32 x i1> %1,
i32 %2) iXLen %2)
ret <vscale x 32 x i16> %a ret <vscale x 32 x i16> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.viota.nxv1i32( declare <vscale x 1 x i32> @llvm.riscv.viota.nxv1i32(
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); iXLen);
define <vscale x 1 x i32> @intrinsic_viota_m_nxv1i32_nxv1i1(<vscale x 1 x i1> %0, i32 %1) nounwind { define <vscale x 1 x i32> @intrinsic_viota_m_nxv1i32_nxv1i1(<vscale x 1 x i1> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_viota_m_nxv1i32_nxv1i1: ; CHECK-LABEL: intrinsic_viota_m_nxv1i32_nxv1i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
; CHECK-NEXT: viota.m v8, v0 ; CHECK-NEXT: viota.m v8, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.viota.nxv1i32( %a = call <vscale x 1 x i32> @llvm.riscv.viota.nxv1i32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
i32 %1) iXLen %1)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.viota.mask.nxv1i32( declare <vscale x 1 x i32> @llvm.riscv.viota.mask.nxv1i32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); iXLen);
define <vscale x 1 x i32> @intrinsic_viota_mask_m_nxv1i32_nxv1i1(<vscale x 1 x i32> %0, <vscale x 1 x i1> %1, i32 %2) nounwind { define <vscale x 1 x i32> @intrinsic_viota_mask_m_nxv1i32_nxv1i1(<vscale x 1 x i32> %0, <vscale x 1 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_viota_mask_m_nxv1i32_nxv1i1: ; CHECK-LABEL: intrinsic_viota_mask_m_nxv1i32_nxv1i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu
; CHECK-NEXT: viota.m v8, v0, v0.t ; CHECK-NEXT: viota.m v8, v0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.viota.mask.nxv1i32( %a = call <vscale x 1 x i32> @llvm.riscv.viota.mask.nxv1i32(
<vscale x 1 x i32> %0, <vscale x 1 x i32> %0,
<vscale x 1 x i1> %1, <vscale x 1 x i1> %1,
<vscale x 1 x i1> %1, <vscale x 1 x i1> %1,
i32 %2) iXLen %2)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.viota.nxv2i32( declare <vscale x 2 x i32> @llvm.riscv.viota.nxv2i32(
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); iXLen);
define <vscale x 2 x i32> @intrinsic_viota_m_nxv2i32_nxv2i1(<vscale x 2 x i1> %0, i32 %1) nounwind { define <vscale x 2 x i32> @intrinsic_viota_m_nxv2i32_nxv2i1(<vscale x 2 x i1> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_viota_m_nxv2i32_nxv2i1: ; CHECK-LABEL: intrinsic_viota_m_nxv2i32_nxv2i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
; CHECK-NEXT: viota.m v8, v0 ; CHECK-NEXT: viota.m v8, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.viota.nxv2i32( %a = call <vscale x 2 x i32> @llvm.riscv.viota.nxv2i32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
i32 %1) iXLen %1)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.viota.mask.nxv2i32( declare <vscale x 2 x i32> @llvm.riscv.viota.mask.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); iXLen);
define <vscale x 2 x i32> @intrinsic_viota_mask_m_nxv2i32_nxv2i1(<vscale x 2 x i32> %0, <vscale x 2 x i1> %1, i32 %2) nounwind { define <vscale x 2 x i32> @intrinsic_viota_mask_m_nxv2i32_nxv2i1(<vscale x 2 x i32> %0, <vscale x 2 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_viota_mask_m_nxv2i32_nxv2i1: ; CHECK-LABEL: intrinsic_viota_mask_m_nxv2i32_nxv2i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu
; CHECK-NEXT: viota.m v8, v0, v0.t ; CHECK-NEXT: viota.m v8, v0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.viota.mask.nxv2i32( %a = call <vscale x 2 x i32> @llvm.riscv.viota.mask.nxv2i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 2 x i1> %1, <vscale x 2 x i1> %1,
<vscale x 2 x i1> %1, <vscale x 2 x i1> %1,
i32 %2) iXLen %2)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.viota.nxv4i32( declare <vscale x 4 x i32> @llvm.riscv.viota.nxv4i32(
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); iXLen);
define <vscale x 4 x i32> @intrinsic_viota_m_nxv4i32_nxv4i1(<vscale x 4 x i1> %0, i32 %1) nounwind { define <vscale x 4 x i32> @intrinsic_viota_m_nxv4i32_nxv4i1(<vscale x 4 x i1> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_viota_m_nxv4i32_nxv4i1: ; CHECK-LABEL: intrinsic_viota_m_nxv4i32_nxv4i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
; CHECK-NEXT: viota.m v8, v0 ; CHECK-NEXT: viota.m v8, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.viota.nxv4i32( %a = call <vscale x 4 x i32> @llvm.riscv.viota.nxv4i32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
i32 %1) iXLen %1)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.viota.mask.nxv4i32( declare <vscale x 4 x i32> @llvm.riscv.viota.mask.nxv4i32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); iXLen);
define <vscale x 4 x i32> @intrinsic_viota_mask_m_nxv4i32_nxv4i1(<vscale x 4 x i32> %0, <vscale x 4 x i1> %1, i32 %2) nounwind { define <vscale x 4 x i32> @intrinsic_viota_mask_m_nxv4i32_nxv4i1(<vscale x 4 x i32> %0, <vscale x 4 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_viota_mask_m_nxv4i32_nxv4i1: ; CHECK-LABEL: intrinsic_viota_mask_m_nxv4i32_nxv4i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu
; CHECK-NEXT: viota.m v8, v0, v0.t ; CHECK-NEXT: viota.m v8, v0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.viota.mask.nxv4i32( %a = call <vscale x 4 x i32> @llvm.riscv.viota.mask.nxv4i32(
<vscale x 4 x i32> %0, <vscale x 4 x i32> %0,
<vscale x 4 x i1> %1, <vscale x 4 x i1> %1,
<vscale x 4 x i1> %1, <vscale x 4 x i1> %1,
i32 %2) iXLen %2)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.viota.nxv8i32( declare <vscale x 8 x i32> @llvm.riscv.viota.nxv8i32(
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); iXLen);
define <vscale x 8 x i32> @intrinsic_viota_m_nxv8i32_nxv8i1(<vscale x 8 x i1> %0, i32 %1) nounwind { define <vscale x 8 x i32> @intrinsic_viota_m_nxv8i32_nxv8i1(<vscale x 8 x i1> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_viota_m_nxv8i32_nxv8i1: ; CHECK-LABEL: intrinsic_viota_m_nxv8i32_nxv8i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
; CHECK-NEXT: viota.m v8, v0 ; CHECK-NEXT: viota.m v8, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.viota.nxv8i32( %a = call <vscale x 8 x i32> @llvm.riscv.viota.nxv8i32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
i32 %1) iXLen %1)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.viota.mask.nxv8i32( declare <vscale x 8 x i32> @llvm.riscv.viota.mask.nxv8i32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); iXLen);
define <vscale x 8 x i32> @intrinsic_viota_mask_m_nxv8i32_nxv8i1(<vscale x 8 x i32> %0, <vscale x 8 x i1> %1, i32 %2) nounwind { define <vscale x 8 x i32> @intrinsic_viota_mask_m_nxv8i32_nxv8i1(<vscale x 8 x i32> %0, <vscale x 8 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_viota_mask_m_nxv8i32_nxv8i1: ; CHECK-LABEL: intrinsic_viota_mask_m_nxv8i32_nxv8i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu
; CHECK-NEXT: viota.m v8, v0, v0.t ; CHECK-NEXT: viota.m v8, v0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.viota.mask.nxv8i32( %a = call <vscale x 8 x i32> @llvm.riscv.viota.mask.nxv8i32(
<vscale x 8 x i32> %0, <vscale x 8 x i32> %0,
<vscale x 8 x i1> %1, <vscale x 8 x i1> %1,
<vscale x 8 x i1> %1, <vscale x 8 x i1> %1,
i32 %2) iXLen %2)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 16 x i32> @llvm.riscv.viota.nxv16i32( declare <vscale x 16 x i32> @llvm.riscv.viota.nxv16i32(
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); iXLen);
define <vscale x 16 x i32> @intrinsic_viota_m_nxv16i32_nxv16i1(<vscale x 16 x i1> %0, i32 %1) nounwind { define <vscale x 16 x i32> @intrinsic_viota_m_nxv16i32_nxv16i1(<vscale x 16 x i1> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_viota_m_nxv16i32_nxv16i1: ; CHECK-LABEL: intrinsic_viota_m_nxv16i32_nxv16i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu
; CHECK-NEXT: viota.m v8, v0 ; CHECK-NEXT: viota.m v8, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.viota.nxv16i32( %a = call <vscale x 16 x i32> @llvm.riscv.viota.nxv16i32(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
i32 %1) iXLen %1)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
declare <vscale x 16 x i32> @llvm.riscv.viota.mask.nxv16i32( declare <vscale x 16 x i32> @llvm.riscv.viota.mask.nxv16i32(
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); iXLen);
define <vscale x 16 x i32> @intrinsic_viota_mask_m_nxv16i32_nxv16i1(<vscale x 16 x i32> %0, <vscale x 16 x i1> %1, i32 %2) nounwind { define <vscale x 16 x i32> @intrinsic_viota_mask_m_nxv16i32_nxv16i1(<vscale x 16 x i32> %0, <vscale x 16 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_viota_mask_m_nxv16i32_nxv16i1: ; CHECK-LABEL: intrinsic_viota_mask_m_nxv16i32_nxv16i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m8, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m8, tu, mu
; CHECK-NEXT: viota.m v8, v0, v0.t ; CHECK-NEXT: viota.m v8, v0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.viota.mask.nxv16i32( %a = call <vscale x 16 x i32> @llvm.riscv.viota.mask.nxv16i32(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
<vscale x 16 x i1> %1, <vscale x 16 x i1> %1,
<vscale x 16 x i1> %1, <vscale x 16 x i1> %1,
i32 %2) iXLen %2)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.viota.nxv1i64( declare <vscale x 1 x i64> @llvm.riscv.viota.nxv1i64(
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); iXLen);
define <vscale x 1 x i64> @intrinsic_viota_m_nxv1i64_nxv1i1(<vscale x 1 x i1> %0, i32 %1) nounwind { define <vscale x 1 x i64> @intrinsic_viota_m_nxv1i64_nxv1i1(<vscale x 1 x i1> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_viota_m_nxv1i64_nxv1i1: ; CHECK-LABEL: intrinsic_viota_m_nxv1i64_nxv1i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
; CHECK-NEXT: viota.m v8, v0 ; CHECK-NEXT: viota.m v8, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.viota.nxv1i64( %a = call <vscale x 1 x i64> @llvm.riscv.viota.nxv1i64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
i32 %1) iXLen %1)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.viota.mask.nxv1i64( declare <vscale x 1 x i64> @llvm.riscv.viota.mask.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); iXLen);
define <vscale x 1 x i64> @intrinsic_viota_mask_m_nxv1i64_nxv1i1(<vscale x 1 x i64> %0, <vscale x 1 x i1> %1, i32 %2) nounwind { define <vscale x 1 x i64> @intrinsic_viota_mask_m_nxv1i64_nxv1i1(<vscale x 1 x i64> %0, <vscale x 1 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_viota_mask_m_nxv1i64_nxv1i1: ; CHECK-LABEL: intrinsic_viota_mask_m_nxv1i64_nxv1i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu
; CHECK-NEXT: viota.m v8, v0, v0.t ; CHECK-NEXT: viota.m v8, v0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.viota.mask.nxv1i64( %a = call <vscale x 1 x i64> @llvm.riscv.viota.mask.nxv1i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 1 x i1> %1, <vscale x 1 x i1> %1,
<vscale x 1 x i1> %1, <vscale x 1 x i1> %1,
i32 %2) iXLen %2)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.viota.nxv2i64( declare <vscale x 2 x i64> @llvm.riscv.viota.nxv2i64(
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); iXLen);
define <vscale x 2 x i64> @intrinsic_viota_m_nxv2i64_nxv2i1(<vscale x 2 x i1> %0, i32 %1) nounwind { define <vscale x 2 x i64> @intrinsic_viota_m_nxv2i64_nxv2i1(<vscale x 2 x i1> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_viota_m_nxv2i64_nxv2i1: ; CHECK-LABEL: intrinsic_viota_m_nxv2i64_nxv2i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
; CHECK-NEXT: viota.m v8, v0 ; CHECK-NEXT: viota.m v8, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.viota.nxv2i64( %a = call <vscale x 2 x i64> @llvm.riscv.viota.nxv2i64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
i32 %1) iXLen %1)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.viota.mask.nxv2i64( declare <vscale x 2 x i64> @llvm.riscv.viota.mask.nxv2i64(
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); iXLen);
define <vscale x 2 x i64> @intrinsic_viota_mask_m_nxv2i64_nxv2i1(<vscale x 2 x i64> %0, <vscale x 2 x i1> %1, i32 %2) nounwind { define <vscale x 2 x i64> @intrinsic_viota_mask_m_nxv2i64_nxv2i1(<vscale x 2 x i64> %0, <vscale x 2 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_viota_mask_m_nxv2i64_nxv2i1: ; CHECK-LABEL: intrinsic_viota_mask_m_nxv2i64_nxv2i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu
; CHECK-NEXT: viota.m v8, v0, v0.t ; CHECK-NEXT: viota.m v8, v0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.viota.mask.nxv2i64( %a = call <vscale x 2 x i64> @llvm.riscv.viota.mask.nxv2i64(
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
<vscale x 2 x i1> %1, <vscale x 2 x i1> %1,
<vscale x 2 x i1> %1, <vscale x 2 x i1> %1,
i32 %2) iXLen %2)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.viota.nxv4i64( declare <vscale x 4 x i64> @llvm.riscv.viota.nxv4i64(
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); iXLen);
define <vscale x 4 x i64> @intrinsic_viota_m_nxv4i64_nxv4i1(<vscale x 4 x i1> %0, i32 %1) nounwind { define <vscale x 4 x i64> @intrinsic_viota_m_nxv4i64_nxv4i1(<vscale x 4 x i1> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_viota_m_nxv4i64_nxv4i1: ; CHECK-LABEL: intrinsic_viota_m_nxv4i64_nxv4i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
; CHECK-NEXT: viota.m v8, v0 ; CHECK-NEXT: viota.m v8, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.viota.nxv4i64( %a = call <vscale x 4 x i64> @llvm.riscv.viota.nxv4i64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
i32 %1) iXLen %1)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.viota.mask.nxv4i64( declare <vscale x 4 x i64> @llvm.riscv.viota.mask.nxv4i64(
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); iXLen);
define <vscale x 4 x i64> @intrinsic_viota_mask_m_nxv4i64_nxv4i1(<vscale x 4 x i64> %0, <vscale x 4 x i1> %1, i32 %2) nounwind { define <vscale x 4 x i64> @intrinsic_viota_mask_m_nxv4i64_nxv4i1(<vscale x 4 x i64> %0, <vscale x 4 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_viota_mask_m_nxv4i64_nxv4i1: ; CHECK-LABEL: intrinsic_viota_mask_m_nxv4i64_nxv4i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu
; CHECK-NEXT: viota.m v8, v0, v0.t ; CHECK-NEXT: viota.m v8, v0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.viota.mask.nxv4i64( %a = call <vscale x 4 x i64> @llvm.riscv.viota.mask.nxv4i64(
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
<vscale x 4 x i1> %1, <vscale x 4 x i1> %1,
<vscale x 4 x i1> %1, <vscale x 4 x i1> %1,
i32 %2) iXLen %2)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 8 x i64> @llvm.riscv.viota.nxv8i64( declare <vscale x 8 x i64> @llvm.riscv.viota.nxv8i64(
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); iXLen);
define <vscale x 8 x i64> @intrinsic_viota_m_nxv8i64_nxv8i1(<vscale x 8 x i1> %0, i32 %1) nounwind { define <vscale x 8 x i64> @intrinsic_viota_m_nxv8i64_nxv8i1(<vscale x 8 x i1> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_viota_m_nxv8i64_nxv8i1: ; CHECK-LABEL: intrinsic_viota_m_nxv8i64_nxv8i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu
; CHECK-NEXT: viota.m v8, v0 ; CHECK-NEXT: viota.m v8, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.viota.nxv8i64( %a = call <vscale x 8 x i64> @llvm.riscv.viota.nxv8i64(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
i32 %1) iXLen %1)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }
declare <vscale x 8 x i64> @llvm.riscv.viota.mask.nxv8i64( declare <vscale x 8 x i64> @llvm.riscv.viota.mask.nxv8i64(
<vscale x 8 x i64>, <vscale x 8 x i64>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); iXLen);
define <vscale x 8 x i64> @intrinsic_viota_mask_m_nxv8i64_nxv8i1(<vscale x 8 x i64> %0, <vscale x 8 x i1> %1, i32 %2) nounwind { define <vscale x 8 x i64> @intrinsic_viota_mask_m_nxv8i64_nxv8i1(<vscale x 8 x i64> %0, <vscale x 8 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_viota_mask_m_nxv8i64_nxv8i1: ; CHECK-LABEL: intrinsic_viota_mask_m_nxv8i64_nxv8i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m8, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m8, tu, mu
; CHECK-NEXT: viota.m v8, v0, v0.t ; CHECK-NEXT: viota.m v8, v0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.viota.mask.nxv8i64( %a = call <vscale x 8 x i64> @llvm.riscv.viota.mask.nxv8i64(
<vscale x 8 x i64> %0, <vscale x 8 x i64> %0,
<vscale x 8 x i1> %1, <vscale x 8 x i1> %1,
<vscale x 8 x i1> %1, <vscale x 8 x i1> %1,
i32 %2) iXLen %2)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }

llvm/test/CodeGen/RISCV/rvv/vlm-rv32.ll

  • This file was moved to llvm/test/CodeGen/RISCV/rvv/vlm.ll.

llvm/test/CodeGen/RISCV/rvv/vlm-rv64.ll

  • This file was deleted.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs \
; RUN: < %s | FileCheck %s
declare <vscale x 1 x i1> @llvm.riscv.vlm.nxv1i1(<vscale x 1 x i1>*, i64);
define <vscale x 1 x i1> @intrinsic_vlm_v_nxv1i1(<vscale x 1 x i1>* %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vlm_v_nxv1i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
; CHECK-NEXT: vlm.v v0, (a0)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vlm.nxv1i1(<vscale x 1 x i1>* %0, i64 %1)
ret <vscale x 1 x i1> %a
}
declare <vscale x 2 x i1> @llvm.riscv.vlm.nxv2i1(<vscale x 2 x i1>*, i64);
define <vscale x 2 x i1> @intrinsic_vlm_v_nxv2i1(<vscale x 2 x i1>* %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vlm_v_nxv2i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
; CHECK-NEXT: vlm.v v0, (a0)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vlm.nxv2i1(<vscale x 2 x i1>* %0, i64 %1)
ret <vscale x 2 x i1> %a
}
declare <vscale x 4 x i1> @llvm.riscv.vlm.nxv4i1(<vscale x 4 x i1>*, i64);
define <vscale x 4 x i1> @intrinsic_vlm_v_nxv4i1(<vscale x 4 x i1>* %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vlm_v_nxv4i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
; CHECK-NEXT: vlm.v v0, (a0)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vlm.nxv4i1(<vscale x 4 x i1>* %0, i64 %1)
ret <vscale x 4 x i1> %a
}
declare <vscale x 8 x i1> @llvm.riscv.vlm.nxv8i1(<vscale x 8 x i1>*, i64);
define <vscale x 8 x i1> @intrinsic_vlm_v_nxv8i1(<vscale x 8 x i1>* %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vlm_v_nxv8i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
; CHECK-NEXT: vlm.v v0, (a0)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vlm.nxv8i1(<vscale x 8 x i1>* %0, i64 %1)
ret <vscale x 8 x i1> %a
}
declare <vscale x 16 x i1> @llvm.riscv.vlm.nxv16i1(<vscale x 16 x i1>*, i64);
define <vscale x 16 x i1> @intrinsic_vlm_v_nxv16i1(<vscale x 16 x i1>* %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vlm_v_nxv16i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
; CHECK-NEXT: vlm.v v0, (a0)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vlm.nxv16i1(<vscale x 16 x i1>* %0, i64 %1)
ret <vscale x 16 x i1> %a
}
declare <vscale x 32 x i1> @llvm.riscv.vlm.nxv32i1(<vscale x 32 x i1>*, i64);
define <vscale x 32 x i1> @intrinsic_vlm_v_nxv32i1(<vscale x 32 x i1>* %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vlm_v_nxv32i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
; CHECK-NEXT: vlm.v v0, (a0)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vlm.nxv32i1(<vscale x 32 x i1>* %0, i64 %1)
ret <vscale x 32 x i1> %a
}
declare <vscale x 64 x i1> @llvm.riscv.vlm.nxv64i1(<vscale x 64 x i1>*, i64);
define <vscale x 64 x i1> @intrinsic_vlm_v_nxv64i1(<vscale x 64 x i1>* %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vlm_v_nxv64i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu
; CHECK-NEXT: vlm.v v0, (a0)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 64 x i1> @llvm.riscv.vlm.nxv64i1(<vscale x 64 x i1>* %0, i64 %1)
ret <vscale x 64 x i1> %a
}

llvm/test/CodeGen/RISCV/rvv/vlm.ll

  • This file was moved from llvm/test/CodeGen/RISCV/rvv/vlm-rv32.ll.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs \ ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v \
; RUN: < %s | FileCheck %s ; RUN: -verify-machineinstrs | FileCheck %s
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v \
; RUN: -verify-machineinstrs | FileCheck %s
declare <vscale x 1 x i1> @llvm.riscv.vlm.nxv1i1(<vscale x 1 x i1>*, i32); declare <vscale x 1 x i1> @llvm.riscv.vlm.nxv1i1(<vscale x 1 x i1>*, iXLen);
define <vscale x 1 x i1> @intrinsic_vlm_v_nxv1i1(<vscale x 1 x i1>* %0, i32 %1) nounwind { define <vscale x 1 x i1> @intrinsic_vlm_v_nxv1i1(<vscale x 1 x i1>* %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vlm_v_nxv1i1: ; CHECK-LABEL: intrinsic_vlm_v_nxv1i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
; CHECK-NEXT: vlm.v v0, (a0) ; CHECK-NEXT: vlm.v v0, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vlm.nxv1i1(<vscale x 1 x i1>* %0, i32 %1) %a = call <vscale x 1 x i1> @llvm.riscv.vlm.nxv1i1(<vscale x 1 x i1>* %0, iXLen %1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vlm.nxv2i1(<vscale x 2 x i1>*, i32); declare <vscale x 2 x i1> @llvm.riscv.vlm.nxv2i1(<vscale x 2 x i1>*, iXLen);
define <vscale x 2 x i1> @intrinsic_vlm_v_nxv2i1(<vscale x 2 x i1>* %0, i32 %1) nounwind { define <vscale x 2 x i1> @intrinsic_vlm_v_nxv2i1(<vscale x 2 x i1>* %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vlm_v_nxv2i1: ; CHECK-LABEL: intrinsic_vlm_v_nxv2i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
; CHECK-NEXT: vlm.v v0, (a0) ; CHECK-NEXT: vlm.v v0, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vlm.nxv2i1(<vscale x 2 x i1>* %0, i32 %1) %a = call <vscale x 2 x i1> @llvm.riscv.vlm.nxv2i1(<vscale x 2 x i1>* %0, iXLen %1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vlm.nxv4i1(<vscale x 4 x i1>*, i32); declare <vscale x 4 x i1> @llvm.riscv.vlm.nxv4i1(<vscale x 4 x i1>*, iXLen);
define <vscale x 4 x i1> @intrinsic_vlm_v_nxv4i1(<vscale x 4 x i1>* %0, i32 %1) nounwind { define <vscale x 4 x i1> @intrinsic_vlm_v_nxv4i1(<vscale x 4 x i1>* %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vlm_v_nxv4i1: ; CHECK-LABEL: intrinsic_vlm_v_nxv4i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
; CHECK-NEXT: vlm.v v0, (a0) ; CHECK-NEXT: vlm.v v0, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vlm.nxv4i1(<vscale x 4 x i1>* %0, i32 %1) %a = call <vscale x 4 x i1> @llvm.riscv.vlm.nxv4i1(<vscale x 4 x i1>* %0, iXLen %1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vlm.nxv8i1(<vscale x 8 x i1>*, i32); declare <vscale x 8 x i1> @llvm.riscv.vlm.nxv8i1(<vscale x 8 x i1>*, iXLen);
define <vscale x 8 x i1> @intrinsic_vlm_v_nxv8i1(<vscale x 8 x i1>* %0, i32 %1) nounwind { define <vscale x 8 x i1> @intrinsic_vlm_v_nxv8i1(<vscale x 8 x i1>* %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vlm_v_nxv8i1: ; CHECK-LABEL: intrinsic_vlm_v_nxv8i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
; CHECK-NEXT: vlm.v v0, (a0) ; CHECK-NEXT: vlm.v v0, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vlm.nxv8i1(<vscale x 8 x i1>* %0, i32 %1) %a = call <vscale x 8 x i1> @llvm.riscv.vlm.nxv8i1(<vscale x 8 x i1>* %0, iXLen %1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vlm.nxv16i1(<vscale x 16 x i1>*, i32); declare <vscale x 16 x i1> @llvm.riscv.vlm.nxv16i1(<vscale x 16 x i1>*, iXLen);
define <vscale x 16 x i1> @intrinsic_vlm_v_nxv16i1(<vscale x 16 x i1>* %0, i32 %1) nounwind { define <vscale x 16 x i1> @intrinsic_vlm_v_nxv16i1(<vscale x 16 x i1>* %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vlm_v_nxv16i1: ; CHECK-LABEL: intrinsic_vlm_v_nxv16i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
; CHECK-NEXT: vlm.v v0, (a0) ; CHECK-NEXT: vlm.v v0, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vlm.nxv16i1(<vscale x 16 x i1>* %0, i32 %1) %a = call <vscale x 16 x i1> @llvm.riscv.vlm.nxv16i1(<vscale x 16 x i1>* %0, iXLen %1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 32 x i1> @llvm.riscv.vlm.nxv32i1(<vscale x 32 x i1>*, i32); declare <vscale x 32 x i1> @llvm.riscv.vlm.nxv32i1(<vscale x 32 x i1>*, iXLen);
define <vscale x 32 x i1> @intrinsic_vlm_v_nxv32i1(<vscale x 32 x i1>* %0, i32 %1) nounwind { define <vscale x 32 x i1> @intrinsic_vlm_v_nxv32i1(<vscale x 32 x i1>* %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vlm_v_nxv32i1: ; CHECK-LABEL: intrinsic_vlm_v_nxv32i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
; CHECK-NEXT: vlm.v v0, (a0) ; CHECK-NEXT: vlm.v v0, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vlm.nxv32i1(<vscale x 32 x i1>* %0, i32 %1) %a = call <vscale x 32 x i1> @llvm.riscv.vlm.nxv32i1(<vscale x 32 x i1>* %0, iXLen %1)
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
declare <vscale x 64 x i1> @llvm.riscv.vlm.nxv64i1(<vscale x 64 x i1>*, i32); declare <vscale x 64 x i1> @llvm.riscv.vlm.nxv64i1(<vscale x 64 x i1>*, iXLen);
define <vscale x 64 x i1> @intrinsic_vlm_v_nxv64i1(<vscale x 64 x i1>* %0, i32 %1) nounwind { define <vscale x 64 x i1> @intrinsic_vlm_v_nxv64i1(<vscale x 64 x i1>* %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vlm_v_nxv64i1: ; CHECK-LABEL: intrinsic_vlm_v_nxv64i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu
; CHECK-NEXT: vlm.v v0, (a0) ; CHECK-NEXT: vlm.v v0, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 64 x i1> @llvm.riscv.vlm.nxv64i1(<vscale x 64 x i1>* %0, i32 %1) %a = call <vscale x 64 x i1> @llvm.riscv.vlm.nxv64i1(<vscale x 64 x i1>* %0, iXLen %1)
ret <vscale x 64 x i1> %a ret <vscale x 64 x i1> %a
} }

llvm/test/CodeGen/RISCV/rvv/vmand-rv32.ll

  • This file was moved to llvm/test/CodeGen/RISCV/rvv/vmand.ll.

llvm/test/CodeGen/RISCV/rvv/vmand-rv64.ll

  • This file was deleted.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+v,+d -verify-machineinstrs \
; RUN: < %s | FileCheck %s
declare <vscale x 1 x i1> @llvm.riscv.vmand.nxv1i1(
<vscale x 1 x i1>,
<vscale x 1 x i1>,
i64);
define <vscale x 1 x i1> @intrinsic_vmand_mm_nxv1i1(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmand_mm_nxv1i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
; CHECK-NEXT: vmand.mm v0, v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmand.nxv1i1(
<vscale x 1 x i1> %0,
<vscale x 1 x i1> %1,
i64 %2)
ret <vscale x 1 x i1> %a
}
declare <vscale x 2 x i1> @llvm.riscv.vmand.nxv2i1(
<vscale x 2 x i1>,
<vscale x 2 x i1>,
i64);
define <vscale x 2 x i1> @intrinsic_vmand_mm_nxv2i1(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmand_mm_nxv2i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
; CHECK-NEXT: vmand.mm v0, v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmand.nxv2i1(
<vscale x 2 x i1> %0,
<vscale x 2 x i1> %1,
i64 %2)
ret <vscale x 2 x i1> %a
}
declare <vscale x 4 x i1> @llvm.riscv.vmand.nxv4i1(
<vscale x 4 x i1>,
<vscale x 4 x i1>,
i64);
define <vscale x 4 x i1> @intrinsic_vmand_mm_nxv4i1(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmand_mm_nxv4i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
; CHECK-NEXT: vmand.mm v0, v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmand.nxv4i1(
<vscale x 4 x i1> %0,
<vscale x 4 x i1> %1,
i64 %2)
ret <vscale x 4 x i1> %a
}
declare <vscale x 8 x i1> @llvm.riscv.vmand.nxv8i1(
<vscale x 8 x i1>,
<vscale x 8 x i1>,
i64);
define <vscale x 8 x i1> @intrinsic_vmand_mm_nxv8i1(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmand_mm_nxv8i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
; CHECK-NEXT: vmand.mm v0, v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmand.nxv8i1(
<vscale x 8 x i1> %0,
<vscale x 8 x i1> %1,
i64 %2)
ret <vscale x 8 x i1> %a
}
declare <vscale x 16 x i1> @llvm.riscv.vmand.nxv16i1(
<vscale x 16 x i1>,
<vscale x 16 x i1>,
i64);
define <vscale x 16 x i1> @intrinsic_vmand_mm_nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmand_mm_nxv16i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
; CHECK-NEXT: vmand.mm v0, v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmand.nxv16i1(
<vscale x 16 x i1> %0,
<vscale x 16 x i1> %1,
i64 %2)
ret <vscale x 16 x i1> %a
}
declare <vscale x 32 x i1> @llvm.riscv.vmand.nxv32i1(
<vscale x 32 x i1>,
<vscale x 32 x i1>,
i64);
define <vscale x 32 x i1> @intrinsic_vmand_mm_nxv32i1(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmand_mm_nxv32i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
; CHECK-NEXT: vmand.mm v0, v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmand.nxv32i1(
<vscale x 32 x i1> %0,
<vscale x 32 x i1> %1,
i64 %2)
ret <vscale x 32 x i1> %a
}
declare <vscale x 64 x i1> @llvm.riscv.vmand.nxv64i1(
<vscale x 64 x i1>,
<vscale x 64 x i1>,
i64);
define <vscale x 64 x i1> @intrinsic_vmand_mm_nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmand_mm_nxv64i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu
; CHECK-NEXT: vmand.mm v0, v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 64 x i1> @llvm.riscv.vmand.nxv64i1(
<vscale x 64 x i1> %0,
<vscale x 64 x i1> %1,
i64 %2)
ret <vscale x 64 x i1> %a
}

llvm/test/CodeGen/RISCV/rvv/vmand.ll

  • This file was moved from llvm/test/CodeGen/RISCV/rvv/vmand-rv32.ll.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+v,+f -verify-machineinstrs \ ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v \
; RUN: < %s | FileCheck %s ; RUN: -verify-machineinstrs | FileCheck %s
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v \
; RUN: -verify-machineinstrs | FileCheck %s
declare <vscale x 1 x i1> @llvm.riscv.vmand.nxv1i1( declare <vscale x 1 x i1> @llvm.riscv.vmand.nxv1i1(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); iXLen);
define <vscale x 1 x i1> @intrinsic_vmand_mm_nxv1i1(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, i32 %2) nounwind { define <vscale x 1 x i1> @intrinsic_vmand_mm_nxv1i1(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmand_mm_nxv1i1: ; CHECK-LABEL: intrinsic_vmand_mm_nxv1i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
; CHECK-NEXT: vmand.mm v0, v0, v8 ; CHECK-NEXT: vmand.mm v0, v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmand.nxv1i1( %a = call <vscale x 1 x i1> @llvm.riscv.vmand.nxv1i1(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i1> %1, <vscale x 1 x i1> %1,
i32 %2) iXLen %2)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmand.nxv2i1( declare <vscale x 2 x i1> @llvm.riscv.vmand.nxv2i1(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); iXLen);
define <vscale x 2 x i1> @intrinsic_vmand_mm_nxv2i1(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, i32 %2) nounwind { define <vscale x 2 x i1> @intrinsic_vmand_mm_nxv2i1(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmand_mm_nxv2i1: ; CHECK-LABEL: intrinsic_vmand_mm_nxv2i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
; CHECK-NEXT: vmand.mm v0, v0, v8 ; CHECK-NEXT: vmand.mm v0, v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmand.nxv2i1( %a = call <vscale x 2 x i1> @llvm.riscv.vmand.nxv2i1(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i1> %1, <vscale x 2 x i1> %1,
i32 %2) iXLen %2)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmand.nxv4i1( declare <vscale x 4 x i1> @llvm.riscv.vmand.nxv4i1(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); iXLen);
define <vscale x 4 x i1> @intrinsic_vmand_mm_nxv4i1(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, i32 %2) nounwind { define <vscale x 4 x i1> @intrinsic_vmand_mm_nxv4i1(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmand_mm_nxv4i1: ; CHECK-LABEL: intrinsic_vmand_mm_nxv4i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
; CHECK-NEXT: vmand.mm v0, v0, v8 ; CHECK-NEXT: vmand.mm v0, v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmand.nxv4i1( %a = call <vscale x 4 x i1> @llvm.riscv.vmand.nxv4i1(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i1> %1, <vscale x 4 x i1> %1,
i32 %2) iXLen %2)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmand.nxv8i1( declare <vscale x 8 x i1> @llvm.riscv.vmand.nxv8i1(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); iXLen);
define <vscale x 8 x i1> @intrinsic_vmand_mm_nxv8i1(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, i32 %2) nounwind { define <vscale x 8 x i1> @intrinsic_vmand_mm_nxv8i1(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmand_mm_nxv8i1: ; CHECK-LABEL: intrinsic_vmand_mm_nxv8i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
; CHECK-NEXT: vmand.mm v0, v0, v8 ; CHECK-NEXT: vmand.mm v0, v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmand.nxv8i1( %a = call <vscale x 8 x i1> @llvm.riscv.vmand.nxv8i1(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i1> %1, <vscale x 8 x i1> %1,
i32 %2) iXLen %2)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmand.nxv16i1( declare <vscale x 16 x i1> @llvm.riscv.vmand.nxv16i1(
<vscale x 16 x i1>, <vscale x 16 x i1>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); iXLen);
define <vscale x 16 x i1> @intrinsic_vmand_mm_nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, i32 %2) nounwind { define <vscale x 16 x i1> @intrinsic_vmand_mm_nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmand_mm_nxv16i1: ; CHECK-LABEL: intrinsic_vmand_mm_nxv16i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
; CHECK-NEXT: vmand.mm v0, v0, v8 ; CHECK-NEXT: vmand.mm v0, v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmand.nxv16i1( %a = call <vscale x 16 x i1> @llvm.riscv.vmand.nxv16i1(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i1> %1, <vscale x 16 x i1> %1,
i32 %2) iXLen %2)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 32 x i1> @llvm.riscv.vmand.nxv32i1( declare <vscale x 32 x i1> @llvm.riscv.vmand.nxv32i1(
<vscale x 32 x i1>, <vscale x 32 x i1>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); iXLen);
define <vscale x 32 x i1> @intrinsic_vmand_mm_nxv32i1(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, i32 %2) nounwind { define <vscale x 32 x i1> @intrinsic_vmand_mm_nxv32i1(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmand_mm_nxv32i1: ; CHECK-LABEL: intrinsic_vmand_mm_nxv32i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
; CHECK-NEXT: vmand.mm v0, v0, v8 ; CHECK-NEXT: vmand.mm v0, v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmand.nxv32i1( %a = call <vscale x 32 x i1> @llvm.riscv.vmand.nxv32i1(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
<vscale x 32 x i1> %1, <vscale x 32 x i1> %1,
i32 %2) iXLen %2)
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
declare <vscale x 64 x i1> @llvm.riscv.vmand.nxv64i1( declare <vscale x 64 x i1> @llvm.riscv.vmand.nxv64i1(
<vscale x 64 x i1>, <vscale x 64 x i1>,
<vscale x 64 x i1>, <vscale x 64 x i1>,
i32); iXLen);
define <vscale x 64 x i1> @intrinsic_vmand_mm_nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, i32 %2) nounwind { define <vscale x 64 x i1> @intrinsic_vmand_mm_nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmand_mm_nxv64i1: ; CHECK-LABEL: intrinsic_vmand_mm_nxv64i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu
; CHECK-NEXT: vmand.mm v0, v0, v8 ; CHECK-NEXT: vmand.mm v0, v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 64 x i1> @llvm.riscv.vmand.nxv64i1( %a = call <vscale x 64 x i1> @llvm.riscv.vmand.nxv64i1(
<vscale x 64 x i1> %0, <vscale x 64 x i1> %0,
<vscale x 64 x i1> %1, <vscale x 64 x i1> %1,
i32 %2) iXLen %2)
ret <vscale x 64 x i1> %a ret <vscale x 64 x i1> %a
} }

llvm/test/CodeGen/RISCV/rvv/vmandn-rv32.ll

  • This file was moved to llvm/test/CodeGen/RISCV/rvv/vmandn.ll.

llvm/test/CodeGen/RISCV/rvv/vmandn-rv64.ll

  • This file was deleted.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+v,+d -verify-machineinstrs \
; RUN: < %s | FileCheck %s
declare <vscale x 1 x i1> @llvm.riscv.vmandn.nxv1i1(
<vscale x 1 x i1>,
<vscale x 1 x i1>,
i64);
define <vscale x 1 x i1> @intrinsic_vmandn_mm_nxv1i1(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmandn_mm_nxv1i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
; CHECK-NEXT: vmandn.mm v0, v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmandn.nxv1i1(
<vscale x 1 x i1> %0,
<vscale x 1 x i1> %1,
i64 %2)
ret <vscale x 1 x i1> %a
}
declare <vscale x 2 x i1> @llvm.riscv.vmandn.nxv2i1(
<vscale x 2 x i1>,
<vscale x 2 x i1>,
i64);
define <vscale x 2 x i1> @intrinsic_vmandn_mm_nxv2i1(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmandn_mm_nxv2i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
; CHECK-NEXT: vmandn.mm v0, v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmandn.nxv2i1(
<vscale x 2 x i1> %0,
<vscale x 2 x i1> %1,
i64 %2)
ret <vscale x 2 x i1> %a
}
declare <vscale x 4 x i1> @llvm.riscv.vmandn.nxv4i1(
<vscale x 4 x i1>,
<vscale x 4 x i1>,
i64);
define <vscale x 4 x i1> @intrinsic_vmandn_mm_nxv4i1(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmandn_mm_nxv4i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
; CHECK-NEXT: vmandn.mm v0, v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmandn.nxv4i1(
<vscale x 4 x i1> %0,
<vscale x 4 x i1> %1,
i64 %2)
ret <vscale x 4 x i1> %a
}
declare <vscale x 8 x i1> @llvm.riscv.vmandn.nxv8i1(
<vscale x 8 x i1>,
<vscale x 8 x i1>,
i64);
define <vscale x 8 x i1> @intrinsic_vmandn_mm_nxv8i1(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmandn_mm_nxv8i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
; CHECK-NEXT: vmandn.mm v0, v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmandn.nxv8i1(
<vscale x 8 x i1> %0,
<vscale x 8 x i1> %1,
i64 %2)
ret <vscale x 8 x i1> %a
}
declare <vscale x 16 x i1> @llvm.riscv.vmandn.nxv16i1(
<vscale x 16 x i1>,
<vscale x 16 x i1>,
i64);
define <vscale x 16 x i1> @intrinsic_vmandn_mm_nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmandn_mm_nxv16i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
; CHECK-NEXT: vmandn.mm v0, v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmandn.nxv16i1(
<vscale x 16 x i1> %0,
<vscale x 16 x i1> %1,
i64 %2)
ret <vscale x 16 x i1> %a
}
declare <vscale x 32 x i1> @llvm.riscv.vmandn.nxv32i1(
<vscale x 32 x i1>,
<vscale x 32 x i1>,
i64);
define <vscale x 32 x i1> @intrinsic_vmandn_mm_nxv32i1(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmandn_mm_nxv32i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
; CHECK-NEXT: vmandn.mm v0, v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmandn.nxv32i1(
<vscale x 32 x i1> %0,
<vscale x 32 x i1> %1,
i64 %2)
ret <vscale x 32 x i1> %a
}
declare <vscale x 64 x i1> @llvm.riscv.vmandn.nxv64i1(
<vscale x 64 x i1>,
<vscale x 64 x i1>,
i64);
define <vscale x 64 x i1> @intrinsic_vmandn_mm_nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmandn_mm_nxv64i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu
; CHECK-NEXT: vmandn.mm v0, v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 64 x i1> @llvm.riscv.vmandn.nxv64i1(
<vscale x 64 x i1> %0,
<vscale x 64 x i1> %1,
i64 %2)
ret <vscale x 64 x i1> %a
}

llvm/test/CodeGen/RISCV/rvv/vmandn.ll

  • This file was moved from llvm/test/CodeGen/RISCV/rvv/vmandn-rv32.ll.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+v,+f -verify-machineinstrs \ ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v \
; RUN: < %s | FileCheck %s ; RUN: -verify-machineinstrs | FileCheck %s
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v \
; RUN: -verify-machineinstrs | FileCheck %s
declare <vscale x 1 x i1> @llvm.riscv.vmandn.nxv1i1( declare <vscale x 1 x i1> @llvm.riscv.vmandn.nxv1i1(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); iXLen);
define <vscale x 1 x i1> @intrinsic_vmandn_mm_nxv1i1(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, i32 %2) nounwind { define <vscale x 1 x i1> @intrinsic_vmandn_mm_nxv1i1(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmandn_mm_nxv1i1: ; CHECK-LABEL: intrinsic_vmandn_mm_nxv1i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
; CHECK-NEXT: vmandn.mm v0, v0, v8 ; CHECK-NEXT: vmandn.mm v0, v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmandn.nxv1i1( %a = call <vscale x 1 x i1> @llvm.riscv.vmandn.nxv1i1(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i1> %1, <vscale x 1 x i1> %1,
i32 %2) iXLen %2)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmandn.nxv2i1( declare <vscale x 2 x i1> @llvm.riscv.vmandn.nxv2i1(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); iXLen);
define <vscale x 2 x i1> @intrinsic_vmandn_mm_nxv2i1(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, i32 %2) nounwind { define <vscale x 2 x i1> @intrinsic_vmandn_mm_nxv2i1(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmandn_mm_nxv2i1: ; CHECK-LABEL: intrinsic_vmandn_mm_nxv2i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
; CHECK-NEXT: vmandn.mm v0, v0, v8 ; CHECK-NEXT: vmandn.mm v0, v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmandn.nxv2i1( %a = call <vscale x 2 x i1> @llvm.riscv.vmandn.nxv2i1(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i1> %1, <vscale x 2 x i1> %1,
i32 %2) iXLen %2)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmandn.nxv4i1( declare <vscale x 4 x i1> @llvm.riscv.vmandn.nxv4i1(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); iXLen);
define <vscale x 4 x i1> @intrinsic_vmandn_mm_nxv4i1(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, i32 %2) nounwind { define <vscale x 4 x i1> @intrinsic_vmandn_mm_nxv4i1(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmandn_mm_nxv4i1: ; CHECK-LABEL: intrinsic_vmandn_mm_nxv4i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
; CHECK-NEXT: vmandn.mm v0, v0, v8 ; CHECK-NEXT: vmandn.mm v0, v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmandn.nxv4i1( %a = call <vscale x 4 x i1> @llvm.riscv.vmandn.nxv4i1(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i1> %1, <vscale x 4 x i1> %1,
i32 %2) iXLen %2)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmandn.nxv8i1( declare <vscale x 8 x i1> @llvm.riscv.vmandn.nxv8i1(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); iXLen);
define <vscale x 8 x i1> @intrinsic_vmandn_mm_nxv8i1(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, i32 %2) nounwind { define <vscale x 8 x i1> @intrinsic_vmandn_mm_nxv8i1(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmandn_mm_nxv8i1: ; CHECK-LABEL: intrinsic_vmandn_mm_nxv8i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
; CHECK-NEXT: vmandn.mm v0, v0, v8 ; CHECK-NEXT: vmandn.mm v0, v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmandn.nxv8i1( %a = call <vscale x 8 x i1> @llvm.riscv.vmandn.nxv8i1(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i1> %1, <vscale x 8 x i1> %1,
i32 %2) iXLen %2)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmandn.nxv16i1( declare <vscale x 16 x i1> @llvm.riscv.vmandn.nxv16i1(
<vscale x 16 x i1>, <vscale x 16 x i1>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); iXLen);
define <vscale x 16 x i1> @intrinsic_vmandn_mm_nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, i32 %2) nounwind { define <vscale x 16 x i1> @intrinsic_vmandn_mm_nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmandn_mm_nxv16i1: ; CHECK-LABEL: intrinsic_vmandn_mm_nxv16i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
; CHECK-NEXT: vmandn.mm v0, v0, v8 ; CHECK-NEXT: vmandn.mm v0, v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmandn.nxv16i1( %a = call <vscale x 16 x i1> @llvm.riscv.vmandn.nxv16i1(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i1> %1, <vscale x 16 x i1> %1,
i32 %2) iXLen %2)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 32 x i1> @llvm.riscv.vmandn.nxv32i1( declare <vscale x 32 x i1> @llvm.riscv.vmandn.nxv32i1(
<vscale x 32 x i1>, <vscale x 32 x i1>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); iXLen);
define <vscale x 32 x i1> @intrinsic_vmandn_mm_nxv32i1(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, i32 %2) nounwind { define <vscale x 32 x i1> @intrinsic_vmandn_mm_nxv32i1(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmandn_mm_nxv32i1: ; CHECK-LABEL: intrinsic_vmandn_mm_nxv32i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
; CHECK-NEXT: vmandn.mm v0, v0, v8 ; CHECK-NEXT: vmandn.mm v0, v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmandn.nxv32i1( %a = call <vscale x 32 x i1> @llvm.riscv.vmandn.nxv32i1(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
<vscale x 32 x i1> %1, <vscale x 32 x i1> %1,
i32 %2) iXLen %2)
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
declare <vscale x 64 x i1> @llvm.riscv.vmandn.nxv64i1( declare <vscale x 64 x i1> @llvm.riscv.vmandn.nxv64i1(
<vscale x 64 x i1>, <vscale x 64 x i1>,
<vscale x 64 x i1>, <vscale x 64 x i1>,
i32); iXLen);
define <vscale x 64 x i1> @intrinsic_vmandn_mm_nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, i32 %2) nounwind { define <vscale x 64 x i1> @intrinsic_vmandn_mm_nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmandn_mm_nxv64i1: ; CHECK-LABEL: intrinsic_vmandn_mm_nxv64i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu
; CHECK-NEXT: vmandn.mm v0, v0, v8 ; CHECK-NEXT: vmandn.mm v0, v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 64 x i1> @llvm.riscv.vmandn.nxv64i1( %a = call <vscale x 64 x i1> @llvm.riscv.vmandn.nxv64i1(
<vscale x 64 x i1> %0, <vscale x 64 x i1> %0,
<vscale x 64 x i1> %1, <vscale x 64 x i1> %1,
i32 %2) iXLen %2)
ret <vscale x 64 x i1> %a ret <vscale x 64 x i1> %a
} }

llvm/test/CodeGen/RISCV/rvv/vmclr-rv32.ll

  • This file was moved to llvm/test/CodeGen/RISCV/rvv/vmclr.ll.

llvm/test/CodeGen/RISCV/rvv/vmclr-rv64.ll

  • This file was deleted.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+v,+zfh -verify-machineinstrs \
; RUN: < %s | FileCheck %s
declare <vscale x 1 x i1> @llvm.riscv.vmclr.nxv1i1(
i64);
define <vscale x 1 x i1> @intrinsic_vmclr_m_pseudo_nxv1i1(i64 %0) nounwind {
; CHECK-LABEL: intrinsic_vmclr_m_pseudo_nxv1i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
; CHECK-NEXT: vmclr.m v0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmclr.nxv1i1(
i64 %0)
ret <vscale x 1 x i1> %a
}
declare <vscale x 2 x i1> @llvm.riscv.vmclr.nxv2i1(
i64);
define <vscale x 2 x i1> @intrinsic_vmclr_m_pseudo_nxv2i1(i64 %0) nounwind {
; CHECK-LABEL: intrinsic_vmclr_m_pseudo_nxv2i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
; CHECK-NEXT: vmclr.m v0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmclr.nxv2i1(
i64 %0)
ret <vscale x 2 x i1> %a
}
declare <vscale x 4 x i1> @llvm.riscv.vmclr.nxv4i1(
i64);
define <vscale x 4 x i1> @intrinsic_vmclr_m_pseudo_nxv4i1(i64 %0) nounwind {
; CHECK-LABEL: intrinsic_vmclr_m_pseudo_nxv4i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
; CHECK-NEXT: vmclr.m v0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmclr.nxv4i1(
i64 %0)
ret <vscale x 4 x i1> %a
}
declare <vscale x 8 x i1> @llvm.riscv.vmclr.nxv8i1(
i64);
define <vscale x 8 x i1> @intrinsic_vmclr_m_pseudo_nxv8i1(i64 %0) nounwind {
; CHECK-LABEL: intrinsic_vmclr_m_pseudo_nxv8i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
; CHECK-NEXT: vmclr.m v0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmclr.nxv8i1(
i64 %0)
ret <vscale x 8 x i1> %a
}
declare <vscale x 16 x i1> @llvm.riscv.vmclr.nxv16i1(
i64);
define <vscale x 16 x i1> @intrinsic_vmclr_m_pseudo_nxv16i1(i64 %0) nounwind {
; CHECK-LABEL: intrinsic_vmclr_m_pseudo_nxv16i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
; CHECK-NEXT: vmclr.m v0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmclr.nxv16i1(
i64 %0)
ret <vscale x 16 x i1> %a
}
declare <vscale x 32 x i1> @llvm.riscv.vmclr.nxv32i1(
i64);
define <vscale x 32 x i1> @intrinsic_vmclr_m_pseudo_nxv32i1(i64 %0) nounwind {
; CHECK-LABEL: intrinsic_vmclr_m_pseudo_nxv32i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
; CHECK-NEXT: vmclr.m v0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmclr.nxv32i1(
i64 %0)
ret <vscale x 32 x i1> %a
}
declare <vscale x 64 x i1> @llvm.riscv.vmclr.nxv64i1(
i64);
define <vscale x 64 x i1> @intrinsic_vmclr_m_pseudo_nxv64i1(i64 %0) nounwind {
; CHECK-LABEL: intrinsic_vmclr_m_pseudo_nxv64i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu
; CHECK-NEXT: vmclr.m v0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 64 x i1> @llvm.riscv.vmclr.nxv64i1(
i64 %0)
ret <vscale x 64 x i1> %a
}

llvm/test/CodeGen/RISCV/rvv/vmclr.ll

  • This file was moved from llvm/test/CodeGen/RISCV/rvv/vmclr-rv32.ll.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+v,+zfh -verify-machineinstrs \ ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v \
; RUN: < %s | FileCheck %s ; RUN: -verify-machineinstrs | FileCheck %s
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v \
; RUN: -verify-machineinstrs | FileCheck %s
declare <vscale x 1 x i1> @llvm.riscv.vmclr.nxv1i1( declare <vscale x 1 x i1> @llvm.riscv.vmclr.nxv1i1(
i32); iXLen);
define <vscale x 1 x i1> @intrinsic_vmclr_m_pseudo_nxv1i1(i32 %0) nounwind { define <vscale x 1 x i1> @intrinsic_vmclr_m_pseudo_nxv1i1(iXLen %0) nounwind {
; CHECK-LABEL: intrinsic_vmclr_m_pseudo_nxv1i1: ; CHECK-LABEL: intrinsic_vmclr_m_pseudo_nxv1i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
; CHECK-NEXT: vmclr.m v0 ; CHECK-NEXT: vmclr.m v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmclr.nxv1i1( %a = call <vscale x 1 x i1> @llvm.riscv.vmclr.nxv1i1(
i32 %0) iXLen %0)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmclr.nxv2i1( declare <vscale x 2 x i1> @llvm.riscv.vmclr.nxv2i1(
i32); iXLen);
define <vscale x 2 x i1> @intrinsic_vmclr_m_pseudo_nxv2i1(i32 %0) nounwind { define <vscale x 2 x i1> @intrinsic_vmclr_m_pseudo_nxv2i1(iXLen %0) nounwind {
; CHECK-LABEL: intrinsic_vmclr_m_pseudo_nxv2i1: ; CHECK-LABEL: intrinsic_vmclr_m_pseudo_nxv2i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
; CHECK-NEXT: vmclr.m v0 ; CHECK-NEXT: vmclr.m v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmclr.nxv2i1( %a = call <vscale x 2 x i1> @llvm.riscv.vmclr.nxv2i1(
i32 %0) iXLen %0)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmclr.nxv4i1( declare <vscale x 4 x i1> @llvm.riscv.vmclr.nxv4i1(
i32); iXLen);
define <vscale x 4 x i1> @intrinsic_vmclr_m_pseudo_nxv4i1(i32 %0) nounwind { define <vscale x 4 x i1> @intrinsic_vmclr_m_pseudo_nxv4i1(iXLen %0) nounwind {
; CHECK-LABEL: intrinsic_vmclr_m_pseudo_nxv4i1: ; CHECK-LABEL: intrinsic_vmclr_m_pseudo_nxv4i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
; CHECK-NEXT: vmclr.m v0 ; CHECK-NEXT: vmclr.m v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmclr.nxv4i1( %a = call <vscale x 4 x i1> @llvm.riscv.vmclr.nxv4i1(
i32 %0) iXLen %0)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmclr.nxv8i1( declare <vscale x 8 x i1> @llvm.riscv.vmclr.nxv8i1(
i32); iXLen);
define <vscale x 8 x i1> @intrinsic_vmclr_m_pseudo_nxv8i1(i32 %0) nounwind { define <vscale x 8 x i1> @intrinsic_vmclr_m_pseudo_nxv8i1(iXLen %0) nounwind {
; CHECK-LABEL: intrinsic_vmclr_m_pseudo_nxv8i1: ; CHECK-LABEL: intrinsic_vmclr_m_pseudo_nxv8i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
; CHECK-NEXT: vmclr.m v0 ; CHECK-NEXT: vmclr.m v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmclr.nxv8i1( %a = call <vscale x 8 x i1> @llvm.riscv.vmclr.nxv8i1(
i32 %0) iXLen %0)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmclr.nxv16i1( declare <vscale x 16 x i1> @llvm.riscv.vmclr.nxv16i1(
i32); iXLen);
define <vscale x 16 x i1> @intrinsic_vmclr_m_pseudo_nxv16i1(i32 %0) nounwind { define <vscale x 16 x i1> @intrinsic_vmclr_m_pseudo_nxv16i1(iXLen %0) nounwind {
; CHECK-LABEL: intrinsic_vmclr_m_pseudo_nxv16i1: ; CHECK-LABEL: intrinsic_vmclr_m_pseudo_nxv16i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
; CHECK-NEXT: vmclr.m v0 ; CHECK-NEXT: vmclr.m v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmclr.nxv16i1( %a = call <vscale x 16 x i1> @llvm.riscv.vmclr.nxv16i1(
i32 %0) iXLen %0)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 32 x i1> @llvm.riscv.vmclr.nxv32i1( declare <vscale x 32 x i1> @llvm.riscv.vmclr.nxv32i1(
i32); iXLen);
define <vscale x 32 x i1> @intrinsic_vmclr_m_pseudo_nxv32i1(i32 %0) nounwind { define <vscale x 32 x i1> @intrinsic_vmclr_m_pseudo_nxv32i1(iXLen %0) nounwind {
; CHECK-LABEL: intrinsic_vmclr_m_pseudo_nxv32i1: ; CHECK-LABEL: intrinsic_vmclr_m_pseudo_nxv32i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
; CHECK-NEXT: vmclr.m v0 ; CHECK-NEXT: vmclr.m v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmclr.nxv32i1( %a = call <vscale x 32 x i1> @llvm.riscv.vmclr.nxv32i1(
i32 %0) iXLen %0)
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
declare <vscale x 64 x i1> @llvm.riscv.vmclr.nxv64i1( declare <vscale x 64 x i1> @llvm.riscv.vmclr.nxv64i1(
i32); iXLen);
define <vscale x 64 x i1> @intrinsic_vmclr_m_pseudo_nxv64i1(i32 %0) nounwind { define <vscale x 64 x i1> @intrinsic_vmclr_m_pseudo_nxv64i1(iXLen %0) nounwind {
; CHECK-LABEL: intrinsic_vmclr_m_pseudo_nxv64i1: ; CHECK-LABEL: intrinsic_vmclr_m_pseudo_nxv64i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu
; CHECK-NEXT: vmclr.m v0 ; CHECK-NEXT: vmclr.m v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 64 x i1> @llvm.riscv.vmclr.nxv64i1( %a = call <vscale x 64 x i1> @llvm.riscv.vmclr.nxv64i1(
i32 %0) iXLen %0)
ret <vscale x 64 x i1> %a ret <vscale x 64 x i1> %a
} }

llvm/test/CodeGen/RISCV/rvv/vmnand-rv32.ll

  • This file was moved to llvm/test/CodeGen/RISCV/rvv/vmnand.ll.

llvm/test/CodeGen/RISCV/rvv/vmnand-rv64.ll

  • This file was deleted.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+v,+d -verify-machineinstrs \
; RUN: < %s | FileCheck %s
declare <vscale x 1 x i1> @llvm.riscv.vmnand.nxv1i1(
<vscale x 1 x i1>,
<vscale x 1 x i1>,
i64);
define <vscale x 1 x i1> @intrinsic_vmnand_mm_nxv1i1(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmnand_mm_nxv1i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
; CHECK-NEXT: vmnand.mm v0, v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmnand.nxv1i1(
<vscale x 1 x i1> %0,
<vscale x 1 x i1> %1,
i64 %2)
ret <vscale x 1 x i1> %a
}
declare <vscale x 2 x i1> @llvm.riscv.vmnand.nxv2i1(
<vscale x 2 x i1>,
<vscale x 2 x i1>,
i64);
define <vscale x 2 x i1> @intrinsic_vmnand_mm_nxv2i1(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmnand_mm_nxv2i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
; CHECK-NEXT: vmnand.mm v0, v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmnand.nxv2i1(
<vscale x 2 x i1> %0,
<vscale x 2 x i1> %1,
i64 %2)
ret <vscale x 2 x i1> %a
}
declare <vscale x 4 x i1> @llvm.riscv.vmnand.nxv4i1(
<vscale x 4 x i1>,
<vscale x 4 x i1>,
i64);
define <vscale x 4 x i1> @intrinsic_vmnand_mm_nxv4i1(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmnand_mm_nxv4i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
; CHECK-NEXT: vmnand.mm v0, v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmnand.nxv4i1(
<vscale x 4 x i1> %0,
<vscale x 4 x i1> %1,
i64 %2)
ret <vscale x 4 x i1> %a
}
declare <vscale x 8 x i1> @llvm.riscv.vmnand.nxv8i1(
<vscale x 8 x i1>,
<vscale x 8 x i1>,
i64);
define <vscale x 8 x i1> @intrinsic_vmnand_mm_nxv8i1(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmnand_mm_nxv8i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
; CHECK-NEXT: vmnand.mm v0, v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmnand.nxv8i1(
<vscale x 8 x i1> %0,
<vscale x 8 x i1> %1,
i64 %2)
ret <vscale x 8 x i1> %a
}
declare <vscale x 16 x i1> @llvm.riscv.vmnand.nxv16i1(
<vscale x 16 x i1>,
<vscale x 16 x i1>,
i64);
define <vscale x 16 x i1> @intrinsic_vmnand_mm_nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmnand_mm_nxv16i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
; CHECK-NEXT: vmnand.mm v0, v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmnand.nxv16i1(
<vscale x 16 x i1> %0,
<vscale x 16 x i1> %1,
i64 %2)
ret <vscale x 16 x i1> %a
}
declare <vscale x 32 x i1> @llvm.riscv.vmnand.nxv32i1(
<vscale x 32 x i1>,
<vscale x 32 x i1>,
i64);
define <vscale x 32 x i1> @intrinsic_vmnand_mm_nxv32i1(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmnand_mm_nxv32i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
; CHECK-NEXT: vmnand.mm v0, v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmnand.nxv32i1(
<vscale x 32 x i1> %0,
<vscale x 32 x i1> %1,
i64 %2)
ret <vscale x 32 x i1> %a
}
declare <vscale x 64 x i1> @llvm.riscv.vmnand.nxv64i1(
<vscale x 64 x i1>,
<vscale x 64 x i1>,
i64);
define <vscale x 64 x i1> @intrinsic_vmnand_mm_nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmnand_mm_nxv64i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu
; CHECK-NEXT: vmnand.mm v0, v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 64 x i1> @llvm.riscv.vmnand.nxv64i1(
<vscale x 64 x i1> %0,
<vscale x 64 x i1> %1,
i64 %2)
ret <vscale x 64 x i1> %a
}

llvm/test/CodeGen/RISCV/rvv/vmnand.ll

  • This file was moved from llvm/test/CodeGen/RISCV/rvv/vmnand-rv32.ll.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+v,+f -verify-machineinstrs \ ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v \
; RUN: < %s | FileCheck %s ; RUN: -verify-machineinstrs | FileCheck %s
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v \
; RUN: -verify-machineinstrs | FileCheck %s
declare <vscale x 1 x i1> @llvm.riscv.vmnand.nxv1i1( declare <vscale x 1 x i1> @llvm.riscv.vmnand.nxv1i1(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); iXLen);
define <vscale x 1 x i1> @intrinsic_vmnand_mm_nxv1i1(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, i32 %2) nounwind { define <vscale x 1 x i1> @intrinsic_vmnand_mm_nxv1i1(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmnand_mm_nxv1i1: ; CHECK-LABEL: intrinsic_vmnand_mm_nxv1i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
; CHECK-NEXT: vmnand.mm v0, v0, v8 ; CHECK-NEXT: vmnand.mm v0, v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmnand.nxv1i1( %a = call <vscale x 1 x i1> @llvm.riscv.vmnand.nxv1i1(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i1> %1, <vscale x 1 x i1> %1,
i32 %2) iXLen %2)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmnand.nxv2i1( declare <vscale x 2 x i1> @llvm.riscv.vmnand.nxv2i1(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); iXLen);
define <vscale x 2 x i1> @intrinsic_vmnand_mm_nxv2i1(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, i32 %2) nounwind { define <vscale x 2 x i1> @intrinsic_vmnand_mm_nxv2i1(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmnand_mm_nxv2i1: ; CHECK-LABEL: intrinsic_vmnand_mm_nxv2i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
; CHECK-NEXT: vmnand.mm v0, v0, v8 ; CHECK-NEXT: vmnand.mm v0, v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmnand.nxv2i1( %a = call <vscale x 2 x i1> @llvm.riscv.vmnand.nxv2i1(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i1> %1, <vscale x 2 x i1> %1,
i32 %2) iXLen %2)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmnand.nxv4i1( declare <vscale x 4 x i1> @llvm.riscv.vmnand.nxv4i1(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); iXLen);
define <vscale x 4 x i1> @intrinsic_vmnand_mm_nxv4i1(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, i32 %2) nounwind { define <vscale x 4 x i1> @intrinsic_vmnand_mm_nxv4i1(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmnand_mm_nxv4i1: ; CHECK-LABEL: intrinsic_vmnand_mm_nxv4i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
; CHECK-NEXT: vmnand.mm v0, v0, v8 ; CHECK-NEXT: vmnand.mm v0, v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmnand.nxv4i1( %a = call <vscale x 4 x i1> @llvm.riscv.vmnand.nxv4i1(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i1> %1, <vscale x 4 x i1> %1,
i32 %2) iXLen %2)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmnand.nxv8i1( declare <vscale x 8 x i1> @llvm.riscv.vmnand.nxv8i1(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); iXLen);
define <vscale x 8 x i1> @intrinsic_vmnand_mm_nxv8i1(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, i32 %2) nounwind { define <vscale x 8 x i1> @intrinsic_vmnand_mm_nxv8i1(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmnand_mm_nxv8i1: ; CHECK-LABEL: intrinsic_vmnand_mm_nxv8i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
; CHECK-NEXT: vmnand.mm v0, v0, v8 ; CHECK-NEXT: vmnand.mm v0, v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmnand.nxv8i1( %a = call <vscale x 8 x i1> @llvm.riscv.vmnand.nxv8i1(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i1> %1, <vscale x 8 x i1> %1,
i32 %2) iXLen %2)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmnand.nxv16i1( declare <vscale x 16 x i1> @llvm.riscv.vmnand.nxv16i1(
<vscale x 16 x i1>, <vscale x 16 x i1>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); iXLen);
define <vscale x 16 x i1> @intrinsic_vmnand_mm_nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, i32 %2) nounwind { define <vscale x 16 x i1> @intrinsic_vmnand_mm_nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmnand_mm_nxv16i1: ; CHECK-LABEL: intrinsic_vmnand_mm_nxv16i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
; CHECK-NEXT: vmnand.mm v0, v0, v8 ; CHECK-NEXT: vmnand.mm v0, v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmnand.nxv16i1( %a = call <vscale x 16 x i1> @llvm.riscv.vmnand.nxv16i1(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i1> %1, <vscale x 16 x i1> %1,
i32 %2) iXLen %2)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 32 x i1> @llvm.riscv.vmnand.nxv32i1( declare <vscale x 32 x i1> @llvm.riscv.vmnand.nxv32i1(
<vscale x 32 x i1>, <vscale x 32 x i1>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); iXLen);
define <vscale x 32 x i1> @intrinsic_vmnand_mm_nxv32i1(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, i32 %2) nounwind { define <vscale x 32 x i1> @intrinsic_vmnand_mm_nxv32i1(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmnand_mm_nxv32i1: ; CHECK-LABEL: intrinsic_vmnand_mm_nxv32i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
; CHECK-NEXT: vmnand.mm v0, v0, v8 ; CHECK-NEXT: vmnand.mm v0, v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmnand.nxv32i1( %a = call <vscale x 32 x i1> @llvm.riscv.vmnand.nxv32i1(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
<vscale x 32 x i1> %1, <vscale x 32 x i1> %1,
i32 %2) iXLen %2)
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
declare <vscale x 64 x i1> @llvm.riscv.vmnand.nxv64i1( declare <vscale x 64 x i1> @llvm.riscv.vmnand.nxv64i1(
<vscale x 64 x i1>, <vscale x 64 x i1>,
<vscale x 64 x i1>, <vscale x 64 x i1>,
i32); iXLen);
define <vscale x 64 x i1> @intrinsic_vmnand_mm_nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, i32 %2) nounwind { define <vscale x 64 x i1> @intrinsic_vmnand_mm_nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmnand_mm_nxv64i1: ; CHECK-LABEL: intrinsic_vmnand_mm_nxv64i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu
; CHECK-NEXT: vmnand.mm v0, v0, v8 ; CHECK-NEXT: vmnand.mm v0, v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 64 x i1> @llvm.riscv.vmnand.nxv64i1( %a = call <vscale x 64 x i1> @llvm.riscv.vmnand.nxv64i1(
<vscale x 64 x i1> %0, <vscale x 64 x i1> %0,
<vscale x 64 x i1> %1, <vscale x 64 x i1> %1,
i32 %2) iXLen %2)
ret <vscale x 64 x i1> %a ret <vscale x 64 x i1> %a
} }

llvm/test/CodeGen/RISCV/rvv/vmnor-rv32.ll

  • This file was moved to llvm/test/CodeGen/RISCV/rvv/vmnor.ll.

llvm/test/CodeGen/RISCV/rvv/vmnor-rv64.ll

  • This file was deleted.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+v,+d -verify-machineinstrs \
; RUN: < %s | FileCheck %s
declare <vscale x 1 x i1> @llvm.riscv.vmnor.nxv1i1(
<vscale x 1 x i1>,
<vscale x 1 x i1>,
i64);
define <vscale x 1 x i1> @intrinsic_vmnor_mm_nxv1i1(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmnor_mm_nxv1i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
; CHECK-NEXT: vmnor.mm v0, v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmnor.nxv1i1(
<vscale x 1 x i1> %0,
<vscale x 1 x i1> %1,
i64 %2)
ret <vscale x 1 x i1> %a
}
declare <vscale x 2 x i1> @llvm.riscv.vmnor.nxv2i1(
<vscale x 2 x i1>,
<vscale x 2 x i1>,
i64);
define <vscale x 2 x i1> @intrinsic_vmnor_mm_nxv2i1(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmnor_mm_nxv2i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
; CHECK-NEXT: vmnor.mm v0, v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmnor.nxv2i1(
<vscale x 2 x i1> %0,
<vscale x 2 x i1> %1,
i64 %2)
ret <vscale x 2 x i1> %a
}
declare <vscale x 4 x i1> @llvm.riscv.vmnor.nxv4i1(
<vscale x 4 x i1>,
<vscale x 4 x i1>,
i64);
define <vscale x 4 x i1> @intrinsic_vmnor_mm_nxv4i1(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmnor_mm_nxv4i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
; CHECK-NEXT: vmnor.mm v0, v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmnor.nxv4i1(
<vscale x 4 x i1> %0,
<vscale x 4 x i1> %1,
i64 %2)
ret <vscale x 4 x i1> %a
}
declare <vscale x 8 x i1> @llvm.riscv.vmnor.nxv8i1(
<vscale x 8 x i1>,
<vscale x 8 x i1>,
i64);
define <vscale x 8 x i1> @intrinsic_vmnor_mm_nxv8i1(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmnor_mm_nxv8i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
; CHECK-NEXT: vmnor.mm v0, v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmnor.nxv8i1(
<vscale x 8 x i1> %0,
<vscale x 8 x i1> %1,
i64 %2)
ret <vscale x 8 x i1> %a
}
declare <vscale x 16 x i1> @llvm.riscv.vmnor.nxv16i1(
<vscale x 16 x i1>,
<vscale x 16 x i1>,
i64);
define <vscale x 16 x i1> @intrinsic_vmnor_mm_nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmnor_mm_nxv16i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
; CHECK-NEXT: vmnor.mm v0, v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmnor.nxv16i1(
<vscale x 16 x i1> %0,
<vscale x 16 x i1> %1,
i64 %2)
ret <vscale x 16 x i1> %a
}
declare <vscale x 32 x i1> @llvm.riscv.vmnor.nxv32i1(
<vscale x 32 x i1>,
<vscale x 32 x i1>,
i64);
define <vscale x 32 x i1> @intrinsic_vmnor_mm_nxv32i1(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmnor_mm_nxv32i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
; CHECK-NEXT: vmnor.mm v0, v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmnor.nxv32i1(
<vscale x 32 x i1> %0,
<vscale x 32 x i1> %1,
i64 %2)
ret <vscale x 32 x i1> %a
}
declare <vscale x 64 x i1> @llvm.riscv.vmnor.nxv64i1(
<vscale x 64 x i1>,
<vscale x 64 x i1>,
i64);
define <vscale x 64 x i1> @intrinsic_vmnor_mm_nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmnor_mm_nxv64i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu
; CHECK-NEXT: vmnor.mm v0, v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 64 x i1> @llvm.riscv.vmnor.nxv64i1(
<vscale x 64 x i1> %0,
<vscale x 64 x i1> %1,
i64 %2)
ret <vscale x 64 x i1> %a
}

llvm/test/CodeGen/RISCV/rvv/vmnor.ll

  • This file was moved from llvm/test/CodeGen/RISCV/rvv/vmnor-rv32.ll.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+v,+f -verify-machineinstrs \ ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v \
; RUN: < %s | FileCheck %s ; RUN: -verify-machineinstrs | FileCheck %s
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v \
; RUN: -verify-machineinstrs | FileCheck %s
declare <vscale x 1 x i1> @llvm.riscv.vmnor.nxv1i1( declare <vscale x 1 x i1> @llvm.riscv.vmnor.nxv1i1(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); iXLen);
define <vscale x 1 x i1> @intrinsic_vmnor_mm_nxv1i1(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, i32 %2) nounwind { define <vscale x 1 x i1> @intrinsic_vmnor_mm_nxv1i1(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmnor_mm_nxv1i1: ; CHECK-LABEL: intrinsic_vmnor_mm_nxv1i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
; CHECK-NEXT: vmnor.mm v0, v0, v8 ; CHECK-NEXT: vmnor.mm v0, v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmnor.nxv1i1( %a = call <vscale x 1 x i1> @llvm.riscv.vmnor.nxv1i1(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i1> %1, <vscale x 1 x i1> %1,
i32 %2) iXLen %2)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmnor.nxv2i1( declare <vscale x 2 x i1> @llvm.riscv.vmnor.nxv2i1(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); iXLen);
define <vscale x 2 x i1> @intrinsic_vmnor_mm_nxv2i1(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, i32 %2) nounwind { define <vscale x 2 x i1> @intrinsic_vmnor_mm_nxv2i1(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmnor_mm_nxv2i1: ; CHECK-LABEL: intrinsic_vmnor_mm_nxv2i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
; CHECK-NEXT: vmnor.mm v0, v0, v8 ; CHECK-NEXT: vmnor.mm v0, v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmnor.nxv2i1( %a = call <vscale x 2 x i1> @llvm.riscv.vmnor.nxv2i1(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i1> %1, <vscale x 2 x i1> %1,
i32 %2) iXLen %2)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmnor.nxv4i1( declare <vscale x 4 x i1> @llvm.riscv.vmnor.nxv4i1(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); iXLen);
define <vscale x 4 x i1> @intrinsic_vmnor_mm_nxv4i1(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, i32 %2) nounwind { define <vscale x 4 x i1> @intrinsic_vmnor_mm_nxv4i1(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmnor_mm_nxv4i1: ; CHECK-LABEL: intrinsic_vmnor_mm_nxv4i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
; CHECK-NEXT: vmnor.mm v0, v0, v8 ; CHECK-NEXT: vmnor.mm v0, v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmnor.nxv4i1( %a = call <vscale x 4 x i1> @llvm.riscv.vmnor.nxv4i1(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i1> %1, <vscale x 4 x i1> %1,
i32 %2) iXLen %2)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmnor.nxv8i1( declare <vscale x 8 x i1> @llvm.riscv.vmnor.nxv8i1(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); iXLen);
define <vscale x 8 x i1> @intrinsic_vmnor_mm_nxv8i1(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, i32 %2) nounwind { define <vscale x 8 x i1> @intrinsic_vmnor_mm_nxv8i1(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmnor_mm_nxv8i1: ; CHECK-LABEL: intrinsic_vmnor_mm_nxv8i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
; CHECK-NEXT: vmnor.mm v0, v0, v8 ; CHECK-NEXT: vmnor.mm v0, v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmnor.nxv8i1( %a = call <vscale x 8 x i1> @llvm.riscv.vmnor.nxv8i1(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i1> %1, <vscale x 8 x i1> %1,
i32 %2) iXLen %2)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmnor.nxv16i1( declare <vscale x 16 x i1> @llvm.riscv.vmnor.nxv16i1(
<vscale x 16 x i1>, <vscale x 16 x i1>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); iXLen);
define <vscale x 16 x i1> @intrinsic_vmnor_mm_nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, i32 %2) nounwind { define <vscale x 16 x i1> @intrinsic_vmnor_mm_nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmnor_mm_nxv16i1: ; CHECK-LABEL: intrinsic_vmnor_mm_nxv16i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
; CHECK-NEXT: vmnor.mm v0, v0, v8 ; CHECK-NEXT: vmnor.mm v0, v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmnor.nxv16i1( %a = call <vscale x 16 x i1> @llvm.riscv.vmnor.nxv16i1(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i1> %1, <vscale x 16 x i1> %1,
i32 %2) iXLen %2)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 32 x i1> @llvm.riscv.vmnor.nxv32i1( declare <vscale x 32 x i1> @llvm.riscv.vmnor.nxv32i1(
<vscale x 32 x i1>, <vscale x 32 x i1>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); iXLen);
define <vscale x 32 x i1> @intrinsic_vmnor_mm_nxv32i1(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, i32 %2) nounwind { define <vscale x 32 x i1> @intrinsic_vmnor_mm_nxv32i1(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmnor_mm_nxv32i1: ; CHECK-LABEL: intrinsic_vmnor_mm_nxv32i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
; CHECK-NEXT: vmnor.mm v0, v0, v8 ; CHECK-NEXT: vmnor.mm v0, v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmnor.nxv32i1( %a = call <vscale x 32 x i1> @llvm.riscv.vmnor.nxv32i1(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
<vscale x 32 x i1> %1, <vscale x 32 x i1> %1,
i32 %2) iXLen %2)
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
declare <vscale x 64 x i1> @llvm.riscv.vmnor.nxv64i1( declare <vscale x 64 x i1> @llvm.riscv.vmnor.nxv64i1(
<vscale x 64 x i1>, <vscale x 64 x i1>,
<vscale x 64 x i1>, <vscale x 64 x i1>,
i32); iXLen);
define <vscale x 64 x i1> @intrinsic_vmnor_mm_nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, i32 %2) nounwind { define <vscale x 64 x i1> @intrinsic_vmnor_mm_nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmnor_mm_nxv64i1: ; CHECK-LABEL: intrinsic_vmnor_mm_nxv64i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu
; CHECK-NEXT: vmnor.mm v0, v0, v8 ; CHECK-NEXT: vmnor.mm v0, v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 64 x i1> @llvm.riscv.vmnor.nxv64i1( %a = call <vscale x 64 x i1> @llvm.riscv.vmnor.nxv64i1(
<vscale x 64 x i1> %0, <vscale x 64 x i1> %0,
<vscale x 64 x i1> %1, <vscale x 64 x i1> %1,
i32 %2) iXLen %2)
ret <vscale x 64 x i1> %a ret <vscale x 64 x i1> %a
} }

llvm/test/CodeGen/RISCV/rvv/vmor-rv32.ll

  • This file was moved to llvm/test/CodeGen/RISCV/rvv/vmor.ll.

llvm/test/CodeGen/RISCV/rvv/vmor-rv64.ll

  • This file was deleted.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+v,+d -verify-machineinstrs \
; RUN: < %s | FileCheck %s
declare <vscale x 1 x i1> @llvm.riscv.vmor.nxv1i1(
<vscale x 1 x i1>,
<vscale x 1 x i1>,
i64);
define <vscale x 1 x i1> @intrinsic_vmor_mm_nxv1i1(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmor_mm_nxv1i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
; CHECK-NEXT: vmor.mm v0, v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmor.nxv1i1(
<vscale x 1 x i1> %0,
<vscale x 1 x i1> %1,
i64 %2)
ret <vscale x 1 x i1> %a
}
declare <vscale x 2 x i1> @llvm.riscv.vmor.nxv2i1(
<vscale x 2 x i1>,
<vscale x 2 x i1>,
i64);
define <vscale x 2 x i1> @intrinsic_vmor_mm_nxv2i1(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmor_mm_nxv2i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
; CHECK-NEXT: vmor.mm v0, v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmor.nxv2i1(
<vscale x 2 x i1> %0,
<vscale x 2 x i1> %1,
i64 %2)
ret <vscale x 2 x i1> %a
}
declare <vscale x 4 x i1> @llvm.riscv.vmor.nxv4i1(
<vscale x 4 x i1>,
<vscale x 4 x i1>,
i64);
define <vscale x 4 x i1> @intrinsic_vmor_mm_nxv4i1(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmor_mm_nxv4i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
; CHECK-NEXT: vmor.mm v0, v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmor.nxv4i1(
<vscale x 4 x i1> %0,
<vscale x 4 x i1> %1,
i64 %2)
ret <vscale x 4 x i1> %a
}
declare <vscale x 8 x i1> @llvm.riscv.vmor.nxv8i1(
<vscale x 8 x i1>,
<vscale x 8 x i1>,
i64);
define <vscale x 8 x i1> @intrinsic_vmor_mm_nxv8i1(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmor_mm_nxv8i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
; CHECK-NEXT: vmor.mm v0, v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmor.nxv8i1(
<vscale x 8 x i1> %0,
<vscale x 8 x i1> %1,
i64 %2)
ret <vscale x 8 x i1> %a
}
declare <vscale x 16 x i1> @llvm.riscv.vmor.nxv16i1(
<vscale x 16 x i1>,
<vscale x 16 x i1>,
i64);
define <vscale x 16 x i1> @intrinsic_vmor_mm_nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmor_mm_nxv16i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
; CHECK-NEXT: vmor.mm v0, v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmor.nxv16i1(
<vscale x 16 x i1> %0,
<vscale x 16 x i1> %1,
i64 %2)
ret <vscale x 16 x i1> %a
}
declare <vscale x 32 x i1> @llvm.riscv.vmor.nxv32i1(
<vscale x 32 x i1>,
<vscale x 32 x i1>,
i64);
define <vscale x 32 x i1> @intrinsic_vmor_mm_nxv32i1(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmor_mm_nxv32i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
; CHECK-NEXT: vmor.mm v0, v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmor.nxv32i1(
<vscale x 32 x i1> %0,
<vscale x 32 x i1> %1,
i64 %2)
ret <vscale x 32 x i1> %a
}
declare <vscale x 64 x i1> @llvm.riscv.vmor.nxv64i1(
<vscale x 64 x i1>,
<vscale x 64 x i1>,
i64);
define <vscale x 64 x i1> @intrinsic_vmor_mm_nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmor_mm_nxv64i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu
; CHECK-NEXT: vmor.mm v0, v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 64 x i1> @llvm.riscv.vmor.nxv64i1(
<vscale x 64 x i1> %0,
<vscale x 64 x i1> %1,
i64 %2)
ret <vscale x 64 x i1> %a
}

llvm/test/CodeGen/RISCV/rvv/vmor.ll

  • This file was moved from llvm/test/CodeGen/RISCV/rvv/vmor-rv32.ll.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+v,+f -verify-machineinstrs \ ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v \
; RUN: < %s | FileCheck %s ; RUN: -verify-machineinstrs | FileCheck %s
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v \
; RUN: -verify-machineinstrs | FileCheck %s
declare <vscale x 1 x i1> @llvm.riscv.vmor.nxv1i1( declare <vscale x 1 x i1> @llvm.riscv.vmor.nxv1i1(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); iXLen);
define <vscale x 1 x i1> @intrinsic_vmor_mm_nxv1i1(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, i32 %2) nounwind { define <vscale x 1 x i1> @intrinsic_vmor_mm_nxv1i1(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmor_mm_nxv1i1: ; CHECK-LABEL: intrinsic_vmor_mm_nxv1i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
; CHECK-NEXT: vmor.mm v0, v0, v8 ; CHECK-NEXT: vmor.mm v0, v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmor.nxv1i1( %a = call <vscale x 1 x i1> @llvm.riscv.vmor.nxv1i1(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i1> %1, <vscale x 1 x i1> %1,
i32 %2) iXLen %2)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmor.nxv2i1( declare <vscale x 2 x i1> @llvm.riscv.vmor.nxv2i1(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); iXLen);
define <vscale x 2 x i1> @intrinsic_vmor_mm_nxv2i1(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, i32 %2) nounwind { define <vscale x 2 x i1> @intrinsic_vmor_mm_nxv2i1(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmor_mm_nxv2i1: ; CHECK-LABEL: intrinsic_vmor_mm_nxv2i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
; CHECK-NEXT: vmor.mm v0, v0, v8 ; CHECK-NEXT: vmor.mm v0, v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmor.nxv2i1( %a = call <vscale x 2 x i1> @llvm.riscv.vmor.nxv2i1(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i1> %1, <vscale x 2 x i1> %1,
i32 %2) iXLen %2)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmor.nxv4i1( declare <vscale x 4 x i1> @llvm.riscv.vmor.nxv4i1(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); iXLen);
define <vscale x 4 x i1> @intrinsic_vmor_mm_nxv4i1(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, i32 %2) nounwind { define <vscale x 4 x i1> @intrinsic_vmor_mm_nxv4i1(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmor_mm_nxv4i1: ; CHECK-LABEL: intrinsic_vmor_mm_nxv4i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
; CHECK-NEXT: vmor.mm v0, v0, v8 ; CHECK-NEXT: vmor.mm v0, v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmor.nxv4i1( %a = call <vscale x 4 x i1> @llvm.riscv.vmor.nxv4i1(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i1> %1, <vscale x 4 x i1> %1,
i32 %2) iXLen %2)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmor.nxv8i1( declare <vscale x 8 x i1> @llvm.riscv.vmor.nxv8i1(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); iXLen);
define <vscale x 8 x i1> @intrinsic_vmor_mm_nxv8i1(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, i32 %2) nounwind { define <vscale x 8 x i1> @intrinsic_vmor_mm_nxv8i1(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmor_mm_nxv8i1: ; CHECK-LABEL: intrinsic_vmor_mm_nxv8i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
; CHECK-NEXT: vmor.mm v0, v0, v8 ; CHECK-NEXT: vmor.mm v0, v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmor.nxv8i1( %a = call <vscale x 8 x i1> @llvm.riscv.vmor.nxv8i1(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i1> %1, <vscale x 8 x i1> %1,
i32 %2) iXLen %2)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmor.nxv16i1( declare <vscale x 16 x i1> @llvm.riscv.vmor.nxv16i1(
<vscale x 16 x i1>, <vscale x 16 x i1>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); iXLen);
define <vscale x 16 x i1> @intrinsic_vmor_mm_nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, i32 %2) nounwind { define <vscale x 16 x i1> @intrinsic_vmor_mm_nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmor_mm_nxv16i1: ; CHECK-LABEL: intrinsic_vmor_mm_nxv16i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
; CHECK-NEXT: vmor.mm v0, v0, v8 ; CHECK-NEXT: vmor.mm v0, v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmor.nxv16i1( %a = call <vscale x 16 x i1> @llvm.riscv.vmor.nxv16i1(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i1> %1, <vscale x 16 x i1> %1,
i32 %2) iXLen %2)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 32 x i1> @llvm.riscv.vmor.nxv32i1( declare <vscale x 32 x i1> @llvm.riscv.vmor.nxv32i1(
<vscale x 32 x i1>, <vscale x 32 x i1>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); iXLen);
define <vscale x 32 x i1> @intrinsic_vmor_mm_nxv32i1(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, i32 %2) nounwind { define <vscale x 32 x i1> @intrinsic_vmor_mm_nxv32i1(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmor_mm_nxv32i1: ; CHECK-LABEL: intrinsic_vmor_mm_nxv32i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
; CHECK-NEXT: vmor.mm v0, v0, v8 ; CHECK-NEXT: vmor.mm v0, v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmor.nxv32i1( %a = call <vscale x 32 x i1> @llvm.riscv.vmor.nxv32i1(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
<vscale x 32 x i1> %1, <vscale x 32 x i1> %1,
i32 %2) iXLen %2)
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
declare <vscale x 64 x i1> @llvm.riscv.vmor.nxv64i1( declare <vscale x 64 x i1> @llvm.riscv.vmor.nxv64i1(
<vscale x 64 x i1>, <vscale x 64 x i1>,
<vscale x 64 x i1>, <vscale x 64 x i1>,
i32); iXLen);
define <vscale x 64 x i1> @intrinsic_vmor_mm_nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, i32 %2) nounwind { define <vscale x 64 x i1> @intrinsic_vmor_mm_nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmor_mm_nxv64i1: ; CHECK-LABEL: intrinsic_vmor_mm_nxv64i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu
; CHECK-NEXT: vmor.mm v0, v0, v8 ; CHECK-NEXT: vmor.mm v0, v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 64 x i1> @llvm.riscv.vmor.nxv64i1( %a = call <vscale x 64 x i1> @llvm.riscv.vmor.nxv64i1(
<vscale x 64 x i1> %0, <vscale x 64 x i1> %0,
<vscale x 64 x i1> %1, <vscale x 64 x i1> %1,
i32 %2) iXLen %2)
ret <vscale x 64 x i1> %a ret <vscale x 64 x i1> %a
} }

llvm/test/CodeGen/RISCV/rvv/vmorn-rv32.ll

  • This file was moved to llvm/test/CodeGen/RISCV/rvv/vmorn.ll.

llvm/test/CodeGen/RISCV/rvv/vmorn-rv64.ll

  • This file was deleted.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+v,+d -verify-machineinstrs \
; RUN: < %s | FileCheck %s
declare <vscale x 1 x i1> @llvm.riscv.vmorn.nxv1i1(
<vscale x 1 x i1>,
<vscale x 1 x i1>,
i64);
define <vscale x 1 x i1> @intrinsic_vmorn_mm_nxv1i1(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmorn_mm_nxv1i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
; CHECK-NEXT: vmorn.mm v0, v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmorn.nxv1i1(
<vscale x 1 x i1> %0,
<vscale x 1 x i1> %1,
i64 %2)
ret <vscale x 1 x i1> %a
}
declare <vscale x 2 x i1> @llvm.riscv.vmorn.nxv2i1(
<vscale x 2 x i1>,
<vscale x 2 x i1>,
i64);
define <vscale x 2 x i1> @intrinsic_vmorn_mm_nxv2i1(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmorn_mm_nxv2i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
; CHECK-NEXT: vmorn.mm v0, v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmorn.nxv2i1(
<vscale x 2 x i1> %0,
<vscale x 2 x i1> %1,
i64 %2)
ret <vscale x 2 x i1> %a
}
declare <vscale x 4 x i1> @llvm.riscv.vmorn.nxv4i1(
<vscale x 4 x i1>,
<vscale x 4 x i1>,
i64);
define <vscale x 4 x i1> @intrinsic_vmorn_mm_nxv4i1(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmorn_mm_nxv4i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
; CHECK-NEXT: vmorn.mm v0, v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmorn.nxv4i1(
<vscale x 4 x i1> %0,
<vscale x 4 x i1> %1,
i64 %2)
ret <vscale x 4 x i1> %a
}
declare <vscale x 8 x i1> @llvm.riscv.vmorn.nxv8i1(
<vscale x 8 x i1>,
<vscale x 8 x i1>,
i64);
define <vscale x 8 x i1> @intrinsic_vmorn_mm_nxv8i1(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmorn_mm_nxv8i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
; CHECK-NEXT: vmorn.mm v0, v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmorn.nxv8i1(
<vscale x 8 x i1> %0,
<vscale x 8 x i1> %1,
i64 %2)
ret <vscale x 8 x i1> %a
}
declare <vscale x 16 x i1> @llvm.riscv.vmorn.nxv16i1(
<vscale x 16 x i1>,
<vscale x 16 x i1>,
i64);
define <vscale x 16 x i1> @intrinsic_vmorn_mm_nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmorn_mm_nxv16i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
; CHECK-NEXT: vmorn.mm v0, v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmorn.nxv16i1(
<vscale x 16 x i1> %0,
<vscale x 16 x i1> %1,
i64 %2)
ret <vscale x 16 x i1> %a
}
declare <vscale x 32 x i1> @llvm.riscv.vmorn.nxv32i1(
<vscale x 32 x i1>,
<vscale x 32 x i1>,
i64);
define <vscale x 32 x i1> @intrinsic_vmorn_mm_nxv32i1(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmorn_mm_nxv32i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
; CHECK-NEXT: vmorn.mm v0, v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmorn.nxv32i1(
<vscale x 32 x i1> %0,
<vscale x 32 x i1> %1,
i64 %2)
ret <vscale x 32 x i1> %a
}
declare <vscale x 64 x i1> @llvm.riscv.vmorn.nxv64i1(
<vscale x 64 x i1>,
<vscale x 64 x i1>,
i64);
define <vscale x 64 x i1> @intrinsic_vmorn_mm_nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmorn_mm_nxv64i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu
; CHECK-NEXT: vmorn.mm v0, v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 64 x i1> @llvm.riscv.vmorn.nxv64i1(
<vscale x 64 x i1> %0,
<vscale x 64 x i1> %1,
i64 %2)
ret <vscale x 64 x i1> %a
}

llvm/test/CodeGen/RISCV/rvv/vmorn.ll

  • This file was moved from llvm/test/CodeGen/RISCV/rvv/vmorn-rv32.ll.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+v,+f -verify-machineinstrs \ ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v \
; RUN: < %s | FileCheck %s ; RUN: -verify-machineinstrs | FileCheck %s
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v \
; RUN: -verify-machineinstrs | FileCheck %s
declare <vscale x 1 x i1> @llvm.riscv.vmorn.nxv1i1( declare <vscale x 1 x i1> @llvm.riscv.vmorn.nxv1i1(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); iXLen);
define <vscale x 1 x i1> @intrinsic_vmorn_mm_nxv1i1(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, i32 %2) nounwind { define <vscale x 1 x i1> @intrinsic_vmorn_mm_nxv1i1(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmorn_mm_nxv1i1: ; CHECK-LABEL: intrinsic_vmorn_mm_nxv1i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
; CHECK-NEXT: vmorn.mm v0, v0, v8 ; CHECK-NEXT: vmorn.mm v0, v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmorn.nxv1i1( %a = call <vscale x 1 x i1> @llvm.riscv.vmorn.nxv1i1(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i1> %1, <vscale x 1 x i1> %1,
i32 %2) iXLen %2)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmorn.nxv2i1( declare <vscale x 2 x i1> @llvm.riscv.vmorn.nxv2i1(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); iXLen);
define <vscale x 2 x i1> @intrinsic_vmorn_mm_nxv2i1(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, i32 %2) nounwind { define <vscale x 2 x i1> @intrinsic_vmorn_mm_nxv2i1(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmorn_mm_nxv2i1: ; CHECK-LABEL: intrinsic_vmorn_mm_nxv2i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
; CHECK-NEXT: vmorn.mm v0, v0, v8 ; CHECK-NEXT: vmorn.mm v0, v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmorn.nxv2i1( %a = call <vscale x 2 x i1> @llvm.riscv.vmorn.nxv2i1(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i1> %1, <vscale x 2 x i1> %1,
i32 %2) iXLen %2)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmorn.nxv4i1( declare <vscale x 4 x i1> @llvm.riscv.vmorn.nxv4i1(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); iXLen);
define <vscale x 4 x i1> @intrinsic_vmorn_mm_nxv4i1(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, i32 %2) nounwind { define <vscale x 4 x i1> @intrinsic_vmorn_mm_nxv4i1(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmorn_mm_nxv4i1: ; CHECK-LABEL: intrinsic_vmorn_mm_nxv4i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
; CHECK-NEXT: vmorn.mm v0, v0, v8 ; CHECK-NEXT: vmorn.mm v0, v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmorn.nxv4i1( %a = call <vscale x 4 x i1> @llvm.riscv.vmorn.nxv4i1(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i1> %1, <vscale x 4 x i1> %1,
i32 %2) iXLen %2)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmorn.nxv8i1( declare <vscale x 8 x i1> @llvm.riscv.vmorn.nxv8i1(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); iXLen);
define <vscale x 8 x i1> @intrinsic_vmorn_mm_nxv8i1(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, i32 %2) nounwind { define <vscale x 8 x i1> @intrinsic_vmorn_mm_nxv8i1(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmorn_mm_nxv8i1: ; CHECK-LABEL: intrinsic_vmorn_mm_nxv8i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
; CHECK-NEXT: vmorn.mm v0, v0, v8 ; CHECK-NEXT: vmorn.mm v0, v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmorn.nxv8i1( %a = call <vscale x 8 x i1> @llvm.riscv.vmorn.nxv8i1(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i1> %1, <vscale x 8 x i1> %1,
i32 %2) iXLen %2)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmorn.nxv16i1( declare <vscale x 16 x i1> @llvm.riscv.vmorn.nxv16i1(
<vscale x 16 x i1>, <vscale x 16 x i1>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); iXLen);
define <vscale x 16 x i1> @intrinsic_vmorn_mm_nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, i32 %2) nounwind { define <vscale x 16 x i1> @intrinsic_vmorn_mm_nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmorn_mm_nxv16i1: ; CHECK-LABEL: intrinsic_vmorn_mm_nxv16i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
; CHECK-NEXT: vmorn.mm v0, v0, v8 ; CHECK-NEXT: vmorn.mm v0, v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmorn.nxv16i1( %a = call <vscale x 16 x i1> @llvm.riscv.vmorn.nxv16i1(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i1> %1, <vscale x 16 x i1> %1,
i32 %2) iXLen %2)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 32 x i1> @llvm.riscv.vmorn.nxv32i1( declare <vscale x 32 x i1> @llvm.riscv.vmorn.nxv32i1(
<vscale x 32 x i1>, <vscale x 32 x i1>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); iXLen);
define <vscale x 32 x i1> @intrinsic_vmorn_mm_nxv32i1(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, i32 %2) nounwind { define <vscale x 32 x i1> @intrinsic_vmorn_mm_nxv32i1(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmorn_mm_nxv32i1: ; CHECK-LABEL: intrinsic_vmorn_mm_nxv32i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
; CHECK-NEXT: vmorn.mm v0, v0, v8 ; CHECK-NEXT: vmorn.mm v0, v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmorn.nxv32i1( %a = call <vscale x 32 x i1> @llvm.riscv.vmorn.nxv32i1(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
<vscale x 32 x i1> %1, <vscale x 32 x i1> %1,
i32 %2) iXLen %2)
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
declare <vscale x 64 x i1> @llvm.riscv.vmorn.nxv64i1( declare <vscale x 64 x i1> @llvm.riscv.vmorn.nxv64i1(
<vscale x 64 x i1>, <vscale x 64 x i1>,
<vscale x 64 x i1>, <vscale x 64 x i1>,
i32); iXLen);
define <vscale x 64 x i1> @intrinsic_vmorn_mm_nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, i32 %2) nounwind { define <vscale x 64 x i1> @intrinsic_vmorn_mm_nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmorn_mm_nxv64i1: ; CHECK-LABEL: intrinsic_vmorn_mm_nxv64i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu
; CHECK-NEXT: vmorn.mm v0, v0, v8 ; CHECK-NEXT: vmorn.mm v0, v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 64 x i1> @llvm.riscv.vmorn.nxv64i1( %a = call <vscale x 64 x i1> @llvm.riscv.vmorn.nxv64i1(
<vscale x 64 x i1> %0, <vscale x 64 x i1> %0,
<vscale x 64 x i1> %1, <vscale x 64 x i1> %1,
i32 %2) iXLen %2)
ret <vscale x 64 x i1> %a ret <vscale x 64 x i1> %a
} }

llvm/test/CodeGen/RISCV/rvv/vmset-rv32.ll

  • This file was moved to llvm/test/CodeGen/RISCV/rvv/vmset.ll.

llvm/test/CodeGen/RISCV/rvv/vmset-rv64.ll

  • This file was deleted.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+v,+zfh -verify-machineinstrs \
; RUN: < %s | FileCheck %s
declare <vscale x 1 x i1> @llvm.riscv.vmset.nxv1i1(
i64);
define <vscale x 1 x i1> @intrinsic_vmset_m_pseudo_nxv1i1(i64 %0) nounwind {
; CHECK-LABEL: intrinsic_vmset_m_pseudo_nxv1i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
; CHECK-NEXT: vmset.m v0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmset.nxv1i1(
i64 %0)
ret <vscale x 1 x i1> %a
}
declare <vscale x 2 x i1> @llvm.riscv.vmset.nxv2i1(
i64);
define <vscale x 2 x i1> @intrinsic_vmset_m_pseudo_nxv2i1(i64 %0) nounwind {
; CHECK-LABEL: intrinsic_vmset_m_pseudo_nxv2i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
; CHECK-NEXT: vmset.m v0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmset.nxv2i1(
i64 %0)
ret <vscale x 2 x i1> %a
}
declare <vscale x 4 x i1> @llvm.riscv.vmset.nxv4i1(
i64);
define <vscale x 4 x i1> @intrinsic_vmset_m_pseudo_nxv4i1(i64 %0) nounwind {
; CHECK-LABEL: intrinsic_vmset_m_pseudo_nxv4i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
; CHECK-NEXT: vmset.m v0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmset.nxv4i1(
i64 %0)
ret <vscale x 4 x i1> %a
}
declare <vscale x 8 x i1> @llvm.riscv.vmset.nxv8i1(
i64);
define <vscale x 8 x i1> @intrinsic_vmset_m_pseudo_nxv8i1(i64 %0) nounwind {
; CHECK-LABEL: intrinsic_vmset_m_pseudo_nxv8i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
; CHECK-NEXT: vmset.m v0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmset.nxv8i1(
i64 %0)
ret <vscale x 8 x i1> %a
}
declare <vscale x 16 x i1> @llvm.riscv.vmset.nxv16i1(
i64);
define <vscale x 16 x i1> @intrinsic_vmset_m_pseudo_nxv16i1(i64 %0) nounwind {
; CHECK-LABEL: intrinsic_vmset_m_pseudo_nxv16i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
; CHECK-NEXT: vmset.m v0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmset.nxv16i1(
i64 %0)
ret <vscale x 16 x i1> %a
}
declare <vscale x 32 x i1> @llvm.riscv.vmset.nxv32i1(
i64);
define <vscale x 32 x i1> @intrinsic_vmset_m_pseudo_nxv32i1(i64 %0) nounwind {
; CHECK-LABEL: intrinsic_vmset_m_pseudo_nxv32i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
; CHECK-NEXT: vmset.m v0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmset.nxv32i1(
i64 %0)
ret <vscale x 32 x i1> %a
}
declare <vscale x 64 x i1> @llvm.riscv.vmset.nxv64i1(
i64);
define <vscale x 64 x i1> @intrinsic_vmset_m_pseudo_nxv64i1(i64 %0) nounwind {
; CHECK-LABEL: intrinsic_vmset_m_pseudo_nxv64i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu
; CHECK-NEXT: vmset.m v0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 64 x i1> @llvm.riscv.vmset.nxv64i1(
i64 %0)
ret <vscale x 64 x i1> %a
}

llvm/test/CodeGen/RISCV/rvv/vmset.ll

  • This file was moved from llvm/test/CodeGen/RISCV/rvv/vmset-rv32.ll.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+v,+zfh -verify-machineinstrs \ ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v \
; RUN: < %s | FileCheck %s ; RUN: -verify-machineinstrs | FileCheck %s
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v \
; RUN: -verify-machineinstrs | FileCheck %s
declare <vscale x 1 x i1> @llvm.riscv.vmset.nxv1i1( declare <vscale x 1 x i1> @llvm.riscv.vmset.nxv1i1(
i32); iXLen);
define <vscale x 1 x i1> @intrinsic_vmset_m_pseudo_nxv1i1(i32 %0) nounwind { define <vscale x 1 x i1> @intrinsic_vmset_m_pseudo_nxv1i1(iXLen %0) nounwind {
; CHECK-LABEL: intrinsic_vmset_m_pseudo_nxv1i1: ; CHECK-LABEL: intrinsic_vmset_m_pseudo_nxv1i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
; CHECK-NEXT: vmset.m v0 ; CHECK-NEXT: vmset.m v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmset.nxv1i1( %a = call <vscale x 1 x i1> @llvm.riscv.vmset.nxv1i1(
i32 %0) iXLen %0)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmset.nxv2i1( declare <vscale x 2 x i1> @llvm.riscv.vmset.nxv2i1(
i32); iXLen);
define <vscale x 2 x i1> @intrinsic_vmset_m_pseudo_nxv2i1(i32 %0) nounwind { define <vscale x 2 x i1> @intrinsic_vmset_m_pseudo_nxv2i1(iXLen %0) nounwind {
; CHECK-LABEL: intrinsic_vmset_m_pseudo_nxv2i1: ; CHECK-LABEL: intrinsic_vmset_m_pseudo_nxv2i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
; CHECK-NEXT: vmset.m v0 ; CHECK-NEXT: vmset.m v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmset.nxv2i1( %a = call <vscale x 2 x i1> @llvm.riscv.vmset.nxv2i1(
i32 %0) iXLen %0)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmset.nxv4i1( declare <vscale x 4 x i1> @llvm.riscv.vmset.nxv4i1(
i32); iXLen);
define <vscale x 4 x i1> @intrinsic_vmset_m_pseudo_nxv4i1(i32 %0) nounwind { define <vscale x 4 x i1> @intrinsic_vmset_m_pseudo_nxv4i1(iXLen %0) nounwind {
; CHECK-LABEL: intrinsic_vmset_m_pseudo_nxv4i1: ; CHECK-LABEL: intrinsic_vmset_m_pseudo_nxv4i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
; CHECK-NEXT: vmset.m v0 ; CHECK-NEXT: vmset.m v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmset.nxv4i1( %a = call <vscale x 4 x i1> @llvm.riscv.vmset.nxv4i1(
i32 %0) iXLen %0)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmset.nxv8i1( declare <vscale x 8 x i1> @llvm.riscv.vmset.nxv8i1(
i32); iXLen);
define <vscale x 8 x i1> @intrinsic_vmset_m_pseudo_nxv8i1(i32 %0) nounwind { define <vscale x 8 x i1> @intrinsic_vmset_m_pseudo_nxv8i1(iXLen %0) nounwind {
; CHECK-LABEL: intrinsic_vmset_m_pseudo_nxv8i1: ; CHECK-LABEL: intrinsic_vmset_m_pseudo_nxv8i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
; CHECK-NEXT: vmset.m v0 ; CHECK-NEXT: vmset.m v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmset.nxv8i1( %a = call <vscale x 8 x i1> @llvm.riscv.vmset.nxv8i1(
i32 %0) iXLen %0)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmset.nxv16i1( declare <vscale x 16 x i1> @llvm.riscv.vmset.nxv16i1(
i32); iXLen);
define <vscale x 16 x i1> @intrinsic_vmset_m_pseudo_nxv16i1(i32 %0) nounwind { define <vscale x 16 x i1> @intrinsic_vmset_m_pseudo_nxv16i1(iXLen %0) nounwind {
; CHECK-LABEL: intrinsic_vmset_m_pseudo_nxv16i1: ; CHECK-LABEL: intrinsic_vmset_m_pseudo_nxv16i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
; CHECK-NEXT: vmset.m v0 ; CHECK-NEXT: vmset.m v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmset.nxv16i1( %a = call <vscale x 16 x i1> @llvm.riscv.vmset.nxv16i1(
i32 %0) iXLen %0)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 32 x i1> @llvm.riscv.vmset.nxv32i1( declare <vscale x 32 x i1> @llvm.riscv.vmset.nxv32i1(
i32); iXLen);
define <vscale x 32 x i1> @intrinsic_vmset_m_pseudo_nxv32i1(i32 %0) nounwind { define <vscale x 32 x i1> @intrinsic_vmset_m_pseudo_nxv32i1(iXLen %0) nounwind {
; CHECK-LABEL: intrinsic_vmset_m_pseudo_nxv32i1: ; CHECK-LABEL: intrinsic_vmset_m_pseudo_nxv32i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
; CHECK-NEXT: vmset.m v0 ; CHECK-NEXT: vmset.m v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmset.nxv32i1( %a = call <vscale x 32 x i1> @llvm.riscv.vmset.nxv32i1(
i32 %0) iXLen %0)
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
declare <vscale x 64 x i1> @llvm.riscv.vmset.nxv64i1( declare <vscale x 64 x i1> @llvm.riscv.vmset.nxv64i1(
i32); iXLen);
define <vscale x 64 x i1> @intrinsic_vmset_m_pseudo_nxv64i1(i32 %0) nounwind { define <vscale x 64 x i1> @intrinsic_vmset_m_pseudo_nxv64i1(iXLen %0) nounwind {
; CHECK-LABEL: intrinsic_vmset_m_pseudo_nxv64i1: ; CHECK-LABEL: intrinsic_vmset_m_pseudo_nxv64i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu
; CHECK-NEXT: vmset.m v0 ; CHECK-NEXT: vmset.m v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 64 x i1> @llvm.riscv.vmset.nxv64i1( %a = call <vscale x 64 x i1> @llvm.riscv.vmset.nxv64i1(
i32 %0) iXLen %0)
ret <vscale x 64 x i1> %a ret <vscale x 64 x i1> %a
} }

llvm/test/CodeGen/RISCV/rvv/vmsif-rv32.ll

  • This file was moved to llvm/test/CodeGen/RISCV/rvv/vmsif.ll.

llvm/test/CodeGen/RISCV/rvv/vmsif-rv64.ll

  • This file was deleted.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs \
; RUN: < %s | FileCheck %s
declare <vscale x 1 x i1> @llvm.riscv.vmsif.nxv1i1(
<vscale x 1 x i1>,
i64);
define <vscale x 1 x i1> @intrinsic_vmsif_m_nxv1i1(<vscale x 1 x i1> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsif_m_nxv1i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
; CHECK-NEXT: vmsif.m v8, v0
; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsif.nxv1i1(
<vscale x 1 x i1> %0,
i64 %1)
ret <vscale x 1 x i1> %a
}
declare <vscale x 1 x i1> @llvm.riscv.vmsif.mask.nxv1i1(
<vscale x 1 x i1>,
<vscale x 1 x i1>,
<vscale x 1 x i1>,
i64);
define <vscale x 1 x i1> @intrinsic_vmsif_mask_m_nxv1i1_nxv1i1(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsif_mask_m_nxv1i1_nxv1i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, mu
; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsif.m v10, v8, v0.t
; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsif.mask.nxv1i1(
<vscale x 1 x i1> %0,
<vscale x 1 x i1> %1,
<vscale x 1 x i1> %2,
i64 %3)
ret <vscale x 1 x i1> %a
}
declare <vscale x 2 x i1> @llvm.riscv.vmsif.nxv2i1(
<vscale x 2 x i1>,
i64);
define <vscale x 2 x i1> @intrinsic_vmsif_m_nxv2i1(<vscale x 2 x i1> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsif_m_nxv2i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
; CHECK-NEXT: vmsif.m v8, v0
; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsif.nxv2i1(
<vscale x 2 x i1> %0,
i64 %1)
ret <vscale x 2 x i1> %a
}
declare <vscale x 2 x i1> @llvm.riscv.vmsif.mask.nxv2i1(
<vscale x 2 x i1>,
<vscale x 2 x i1>,
<vscale x 2 x i1>,
i64);
define <vscale x 2 x i1> @intrinsic_vmsif_mask_m_nxv2i1_nxv2i1(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsif_mask_m_nxv2i1_nxv2i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, tu, mu
; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsif.m v10, v8, v0.t
; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsif.mask.nxv2i1(
<vscale x 2 x i1> %0,
<vscale x 2 x i1> %1,
<vscale x 2 x i1> %2,
i64 %3)
ret <vscale x 2 x i1> %a
}
declare <vscale x 4 x i1> @llvm.riscv.vmsif.nxv4i1(
<vscale x 4 x i1>,
i64);
define <vscale x 4 x i1> @intrinsic_vmsif_m_nxv4i1(<vscale x 4 x i1> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsif_m_nxv4i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
; CHECK-NEXT: vmsif.m v8, v0
; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsif.nxv4i1(
<vscale x 4 x i1> %0,
i64 %1)
ret <vscale x 4 x i1> %a
}
declare <vscale x 4 x i1> @llvm.riscv.vmsif.mask.nxv4i1(
<vscale x 4 x i1>,
<vscale x 4 x i1>,
<vscale x 4 x i1>,
i64);
define <vscale x 4 x i1> @intrinsic_vmsif_mask_m_nxv4i1_nxv4i1(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsif_mask_m_nxv4i1_nxv4i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, mu
; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsif.m v10, v8, v0.t
; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsif.mask.nxv4i1(
<vscale x 4 x i1> %0,
<vscale x 4 x i1> %1,
<vscale x 4 x i1> %2,
i64 %3)
ret <vscale x 4 x i1> %a
}
declare <vscale x 8 x i1> @llvm.riscv.vmsif.nxv8i1(
<vscale x 8 x i1>,
i64);
define <vscale x 8 x i1> @intrinsic_vmsif_m_nxv8i1(<vscale x 8 x i1> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsif_m_nxv8i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
; CHECK-NEXT: vmsif.m v8, v0
; CHECK-NEXT: vmv.v.v v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsif.nxv8i1(
<vscale x 8 x i1> %0,
i64 %1)
ret <vscale x 8 x i1> %a
}
declare <vscale x 8 x i1> @llvm.riscv.vmsif.mask.nxv8i1(
<vscale x 8 x i1>,
<vscale x 8 x i1>,
<vscale x 8 x i1>,
i64);
define <vscale x 8 x i1> @intrinsic_vmsif_mask_m_nxv8i1_nxv8i1(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsif_mask_m_nxv8i1_nxv8i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, mu
; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsif.m v10, v8, v0.t
; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsif.mask.nxv8i1(
<vscale x 8 x i1> %0,
<vscale x 8 x i1> %1,
<vscale x 8 x i1> %2,
i64 %3)
ret <vscale x 8 x i1> %a
}
declare <vscale x 16 x i1> @llvm.riscv.vmsif.nxv16i1(
<vscale x 16 x i1>,
i64);
define <vscale x 16 x i1> @intrinsic_vmsif_m_nxv16i1(<vscale x 16 x i1> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsif_m_nxv16i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
; CHECK-NEXT: vmsif.m v8, v0
; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsif.nxv16i1(
<vscale x 16 x i1> %0,
i64 %1)
ret <vscale x 16 x i1> %a
}
declare <vscale x 16 x i1> @llvm.riscv.vmsif.mask.nxv16i1(
<vscale x 16 x i1>,
<vscale x 16 x i1>,
<vscale x 16 x i1>,
i64);
define <vscale x 16 x i1> @intrinsic_vmsif_mask_m_nxv16i1_nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsif_mask_m_nxv16i1_nxv16i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m2, tu, mu
; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsif.m v10, v8, v0.t
; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsif.mask.nxv16i1(
<vscale x 16 x i1> %0,
<vscale x 16 x i1> %1,
<vscale x 16 x i1> %2,
i64 %3)
ret <vscale x 16 x i1> %a
}
declare <vscale x 32 x i1> @llvm.riscv.vmsif.nxv32i1(
<vscale x 32 x i1>,
i64);
define <vscale x 32 x i1> @intrinsic_vmsif_m_nxv32i1(<vscale x 32 x i1> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsif_m_nxv32i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
; CHECK-NEXT: vmsif.m v8, v0
; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsif.nxv32i1(
<vscale x 32 x i1> %0,
i64 %1)
ret <vscale x 32 x i1> %a
}
declare <vscale x 32 x i1> @llvm.riscv.vmsif.mask.nxv32i1(
<vscale x 32 x i1>,
<vscale x 32 x i1>,
<vscale x 32 x i1>,
i64);
define <vscale x 32 x i1> @intrinsic_vmsif_mask_m_nxv32i1_nxv32i1(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, <vscale x 32 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsif_mask_m_nxv32i1_nxv32i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m4, tu, mu
; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsif.m v10, v8, v0.t
; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsif.mask.nxv32i1(
<vscale x 32 x i1> %0,
<vscale x 32 x i1> %1,
<vscale x 32 x i1> %2,
i64 %3)
ret <vscale x 32 x i1> %a
}
declare <vscale x 64 x i1> @llvm.riscv.vmsif.nxv64i1(
<vscale x 64 x i1>,
i64);
define <vscale x 64 x i1> @intrinsic_vmsif_m_nxv64i1(<vscale x 64 x i1> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsif_m_nxv64i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu
; CHECK-NEXT: vmsif.m v8, v0
; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 64 x i1> @llvm.riscv.vmsif.nxv64i1(
<vscale x 64 x i1> %0,
i64 %1)
ret <vscale x 64 x i1> %a
}
declare <vscale x 64 x i1> @llvm.riscv.vmsif.mask.nxv64i1(
<vscale x 64 x i1>,
<vscale x 64 x i1>,
<vscale x 64 x i1>,
i64);
define <vscale x 64 x i1> @intrinsic_vmsif_mask_m_nxv64i1_nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, <vscale x 64 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsif_mask_m_nxv64i1_nxv64i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m8, tu, mu
; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsif.m v10, v8, v0.t
; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 64 x i1> @llvm.riscv.vmsif.mask.nxv64i1(
<vscale x 64 x i1> %0,
<vscale x 64 x i1> %1,
<vscale x 64 x i1> %2,
i64 %3)
ret <vscale x 64 x i1> %a
}

llvm/test/CodeGen/RISCV/rvv/vmsif.ll

  • This file was moved from llvm/test/CodeGen/RISCV/rvv/vmsif-rv32.ll.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs \ ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v \
; RUN: < %s | FileCheck %s ; RUN: -verify-machineinstrs | FileCheck %s
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v \
; RUN: -verify-machineinstrs | FileCheck %s
declare <vscale x 1 x i1> @llvm.riscv.vmsif.nxv1i1( declare <vscale x 1 x i1> @llvm.riscv.vmsif.nxv1i1(
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); iXLen);
define <vscale x 1 x i1> @intrinsic_vmsif_m_nxv1i1(<vscale x 1 x i1> %0, i32 %1) nounwind { define <vscale x 1 x i1> @intrinsic_vmsif_m_nxv1i1(<vscale x 1 x i1> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vmsif_m_nxv1i1: ; CHECK-LABEL: intrinsic_vmsif_m_nxv1i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
; CHECK-NEXT: vmsif.m v8, v0 ; CHECK-NEXT: vmsif.m v8, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsif.nxv1i1( %a = call <vscale x 1 x i1> @llvm.riscv.vmsif.nxv1i1(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
i32 %1) iXLen %1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsif.mask.nxv1i1( declare <vscale x 1 x i1> @llvm.riscv.vmsif.mask.nxv1i1(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); iXLen);
define <vscale x 1 x i1> @intrinsic_vmsif_mask_m_nxv1i1_nxv1i1(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, <vscale x 1 x i1> %2, i32 %3) nounwind { define <vscale x 1 x i1> @intrinsic_vmsif_mask_m_nxv1i1_nxv1i1(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vmsif_mask_m_nxv1i1_nxv1i1: ; CHECK-LABEL: intrinsic_vmsif_mask_m_nxv1i1_nxv1i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsif.m v10, v8, v0.t ; CHECK-NEXT: vmsif.m v10, v8, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsif.mask.nxv1i1( %a = call <vscale x 1 x i1> @llvm.riscv.vmsif.mask.nxv1i1(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i1> %1, <vscale x 1 x i1> %1,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i32 %3) iXLen %3)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsif.nxv2i1( declare <vscale x 2 x i1> @llvm.riscv.vmsif.nxv2i1(
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); iXLen);
define <vscale x 2 x i1> @intrinsic_vmsif_m_nxv2i1(<vscale x 2 x i1> %0, i32 %1) nounwind { define <vscale x 2 x i1> @intrinsic_vmsif_m_nxv2i1(<vscale x 2 x i1> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vmsif_m_nxv2i1: ; CHECK-LABEL: intrinsic_vmsif_m_nxv2i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
; CHECK-NEXT: vmsif.m v8, v0 ; CHECK-NEXT: vmsif.m v8, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsif.nxv2i1( %a = call <vscale x 2 x i1> @llvm.riscv.vmsif.nxv2i1(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
i32 %1) iXLen %1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsif.mask.nxv2i1( declare <vscale x 2 x i1> @llvm.riscv.vmsif.mask.nxv2i1(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); iXLen);
define <vscale x 2 x i1> @intrinsic_vmsif_mask_m_nxv2i1_nxv2i1(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, <vscale x 2 x i1> %2, i32 %3) nounwind { define <vscale x 2 x i1> @intrinsic_vmsif_mask_m_nxv2i1_nxv2i1(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vmsif_mask_m_nxv2i1_nxv2i1: ; CHECK-LABEL: intrinsic_vmsif_mask_m_nxv2i1_nxv2i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, tu, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsif.m v10, v8, v0.t ; CHECK-NEXT: vmsif.m v10, v8, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsif.mask.nxv2i1( %a = call <vscale x 2 x i1> @llvm.riscv.vmsif.mask.nxv2i1(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i1> %1, <vscale x 2 x i1> %1,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i32 %3) iXLen %3)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsif.nxv4i1( declare <vscale x 4 x i1> @llvm.riscv.vmsif.nxv4i1(
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); iXLen);
define <vscale x 4 x i1> @intrinsic_vmsif_m_nxv4i1(<vscale x 4 x i1> %0, i32 %1) nounwind { define <vscale x 4 x i1> @intrinsic_vmsif_m_nxv4i1(<vscale x 4 x i1> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vmsif_m_nxv4i1: ; CHECK-LABEL: intrinsic_vmsif_m_nxv4i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
; CHECK-NEXT: vmsif.m v8, v0 ; CHECK-NEXT: vmsif.m v8, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsif.nxv4i1( %a = call <vscale x 4 x i1> @llvm.riscv.vmsif.nxv4i1(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
i32 %1) iXLen %1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsif.mask.nxv4i1( declare <vscale x 4 x i1> @llvm.riscv.vmsif.mask.nxv4i1(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); iXLen);
define <vscale x 4 x i1> @intrinsic_vmsif_mask_m_nxv4i1_nxv4i1(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, <vscale x 4 x i1> %2, i32 %3) nounwind { define <vscale x 4 x i1> @intrinsic_vmsif_mask_m_nxv4i1_nxv4i1(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vmsif_mask_m_nxv4i1_nxv4i1: ; CHECK-LABEL: intrinsic_vmsif_mask_m_nxv4i1_nxv4i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsif.m v10, v8, v0.t ; CHECK-NEXT: vmsif.m v10, v8, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsif.mask.nxv4i1( %a = call <vscale x 4 x i1> @llvm.riscv.vmsif.mask.nxv4i1(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i1> %1, <vscale x 4 x i1> %1,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i32 %3) iXLen %3)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsif.nxv8i1( declare <vscale x 8 x i1> @llvm.riscv.vmsif.nxv8i1(
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); iXLen);
define <vscale x 8 x i1> @intrinsic_vmsif_m_nxv8i1(<vscale x 8 x i1> %0, i32 %1) nounwind { define <vscale x 8 x i1> @intrinsic_vmsif_m_nxv8i1(<vscale x 8 x i1> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vmsif_m_nxv8i1: ; CHECK-LABEL: intrinsic_vmsif_m_nxv8i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
; CHECK-NEXT: vmsif.m v8, v0 ; CHECK-NEXT: vmsif.m v8, v0
; CHECK-NEXT: vmv.v.v v0, v8 ; CHECK-NEXT: vmv.v.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsif.nxv8i1( %a = call <vscale x 8 x i1> @llvm.riscv.vmsif.nxv8i1(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
i32 %1) iXLen %1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsif.mask.nxv8i1( declare <vscale x 8 x i1> @llvm.riscv.vmsif.mask.nxv8i1(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); iXLen);
define <vscale x 8 x i1> @intrinsic_vmsif_mask_m_nxv8i1_nxv8i1(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, <vscale x 8 x i1> %2, i32 %3) nounwind { define <vscale x 8 x i1> @intrinsic_vmsif_mask_m_nxv8i1_nxv8i1(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vmsif_mask_m_nxv8i1_nxv8i1: ; CHECK-LABEL: intrinsic_vmsif_mask_m_nxv8i1_nxv8i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsif.m v10, v8, v0.t ; CHECK-NEXT: vmsif.m v10, v8, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsif.mask.nxv8i1( %a = call <vscale x 8 x i1> @llvm.riscv.vmsif.mask.nxv8i1(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i1> %1, <vscale x 8 x i1> %1,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i32 %3) iXLen %3)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsif.nxv16i1( declare <vscale x 16 x i1> @llvm.riscv.vmsif.nxv16i1(
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); iXLen);
define <vscale x 16 x i1> @intrinsic_vmsif_m_nxv16i1(<vscale x 16 x i1> %0, i32 %1) nounwind { define <vscale x 16 x i1> @intrinsic_vmsif_m_nxv16i1(<vscale x 16 x i1> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vmsif_m_nxv16i1: ; CHECK-LABEL: intrinsic_vmsif_m_nxv16i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
; CHECK-NEXT: vmsif.m v8, v0 ; CHECK-NEXT: vmsif.m v8, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsif.nxv16i1( %a = call <vscale x 16 x i1> @llvm.riscv.vmsif.nxv16i1(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
i32 %1) iXLen %1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsif.mask.nxv16i1( declare <vscale x 16 x i1> @llvm.riscv.vmsif.mask.nxv16i1(
<vscale x 16 x i1>, <vscale x 16 x i1>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); iXLen);
define <vscale x 16 x i1> @intrinsic_vmsif_mask_m_nxv16i1_nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, <vscale x 16 x i1> %2, i32 %3) nounwind { define <vscale x 16 x i1> @intrinsic_vmsif_mask_m_nxv16i1_nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, <vscale x 16 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vmsif_mask_m_nxv16i1_nxv16i1: ; CHECK-LABEL: intrinsic_vmsif_mask_m_nxv16i1_nxv16i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m2, tu, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsif.m v10, v8, v0.t ; CHECK-NEXT: vmsif.m v10, v8, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsif.mask.nxv16i1( %a = call <vscale x 16 x i1> @llvm.riscv.vmsif.mask.nxv16i1(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i1> %1, <vscale x 16 x i1> %1,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
i32 %3) iXLen %3)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 32 x i1> @llvm.riscv.vmsif.nxv32i1( declare <vscale x 32 x i1> @llvm.riscv.vmsif.nxv32i1(
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); iXLen);
define <vscale x 32 x i1> @intrinsic_vmsif_m_nxv32i1(<vscale x 32 x i1> %0, i32 %1) nounwind { define <vscale x 32 x i1> @intrinsic_vmsif_m_nxv32i1(<vscale x 32 x i1> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vmsif_m_nxv32i1: ; CHECK-LABEL: intrinsic_vmsif_m_nxv32i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
; CHECK-NEXT: vmsif.m v8, v0 ; CHECK-NEXT: vmsif.m v8, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsif.nxv32i1( %a = call <vscale x 32 x i1> @llvm.riscv.vmsif.nxv32i1(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
i32 %1) iXLen %1)
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
declare <vscale x 32 x i1> @llvm.riscv.vmsif.mask.nxv32i1( declare <vscale x 32 x i1> @llvm.riscv.vmsif.mask.nxv32i1(
<vscale x 32 x i1>, <vscale x 32 x i1>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); iXLen);
define <vscale x 32 x i1> @intrinsic_vmsif_mask_m_nxv32i1_nxv32i1(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, <vscale x 32 x i1> %2, i32 %3) nounwind { define <vscale x 32 x i1> @intrinsic_vmsif_mask_m_nxv32i1_nxv32i1(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, <vscale x 32 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vmsif_mask_m_nxv32i1_nxv32i1: ; CHECK-LABEL: intrinsic_vmsif_mask_m_nxv32i1_nxv32i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m4, tu, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsif.m v10, v8, v0.t ; CHECK-NEXT: vmsif.m v10, v8, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsif.mask.nxv32i1( %a = call <vscale x 32 x i1> @llvm.riscv.vmsif.mask.nxv32i1(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
<vscale x 32 x i1> %1, <vscale x 32 x i1> %1,
<vscale x 32 x i1> %2, <vscale x 32 x i1> %2,
i32 %3) iXLen %3)
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
declare <vscale x 64 x i1> @llvm.riscv.vmsif.nxv64i1( declare <vscale x 64 x i1> @llvm.riscv.vmsif.nxv64i1(
<vscale x 64 x i1>, <vscale x 64 x i1>,
i32); iXLen);
define <vscale x 64 x i1> @intrinsic_vmsif_m_nxv64i1(<vscale x 64 x i1> %0, i32 %1) nounwind { define <vscale x 64 x i1> @intrinsic_vmsif_m_nxv64i1(<vscale x 64 x i1> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vmsif_m_nxv64i1: ; CHECK-LABEL: intrinsic_vmsif_m_nxv64i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu
; CHECK-NEXT: vmsif.m v8, v0 ; CHECK-NEXT: vmsif.m v8, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 64 x i1> @llvm.riscv.vmsif.nxv64i1( %a = call <vscale x 64 x i1> @llvm.riscv.vmsif.nxv64i1(
<vscale x 64 x i1> %0, <vscale x 64 x i1> %0,
i32 %1) iXLen %1)
ret <vscale x 64 x i1> %a ret <vscale x 64 x i1> %a
} }
declare <vscale x 64 x i1> @llvm.riscv.vmsif.mask.nxv64i1( declare <vscale x 64 x i1> @llvm.riscv.vmsif.mask.nxv64i1(
<vscale x 64 x i1>, <vscale x 64 x i1>,
<vscale x 64 x i1>, <vscale x 64 x i1>,
<vscale x 64 x i1>, <vscale x 64 x i1>,
i32); iXLen);
define <vscale x 64 x i1> @intrinsic_vmsif_mask_m_nxv64i1_nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, <vscale x 64 x i1> %2, i32 %3) nounwind { define <vscale x 64 x i1> @intrinsic_vmsif_mask_m_nxv64i1_nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, <vscale x 64 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vmsif_mask_m_nxv64i1_nxv64i1: ; CHECK-LABEL: intrinsic_vmsif_mask_m_nxv64i1_nxv64i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m8, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m8, tu, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsif.m v10, v8, v0.t ; CHECK-NEXT: vmsif.m v10, v8, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 64 x i1> @llvm.riscv.vmsif.mask.nxv64i1( %a = call <vscale x 64 x i1> @llvm.riscv.vmsif.mask.nxv64i1(
<vscale x 64 x i1> %0, <vscale x 64 x i1> %0,
<vscale x 64 x i1> %1, <vscale x 64 x i1> %1,
<vscale x 64 x i1> %2, <vscale x 64 x i1> %2,
i32 %3) iXLen %3)
ret <vscale x 64 x i1> %a ret <vscale x 64 x i1> %a
} }

llvm/test/CodeGen/RISCV/rvv/vmsof-rv32.ll

  • This file was moved to llvm/test/CodeGen/RISCV/rvv/vmsof.ll.

llvm/test/CodeGen/RISCV/rvv/vmsof-rv64.ll

  • This file was deleted.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs \
; RUN: < %s | FileCheck %s
declare <vscale x 1 x i1> @llvm.riscv.vmsof.nxv1i1(
<vscale x 1 x i1>,
i64);
define <vscale x 1 x i1> @intrinsic_vmsof_m_nxv1i1(<vscale x 1 x i1> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsof_m_nxv1i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
; CHECK-NEXT: vmsof.m v8, v0
; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsof.nxv1i1(
<vscale x 1 x i1> %0,
i64 %1)
ret <vscale x 1 x i1> %a
}
declare <vscale x 1 x i1> @llvm.riscv.vmsof.mask.nxv1i1(
<vscale x 1 x i1>,
<vscale x 1 x i1>,
<vscale x 1 x i1>,
i64);
define <vscale x 1 x i1> @intrinsic_vmsof_mask_m_nxv1i1_nxv1i1(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsof_mask_m_nxv1i1_nxv1i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, mu
; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsof.m v10, v8, v0.t
; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsof.mask.nxv1i1(
<vscale x 1 x i1> %0,
<vscale x 1 x i1> %1,
<vscale x 1 x i1> %2,
i64 %3)
ret <vscale x 1 x i1> %a
}
declare <vscale x 2 x i1> @llvm.riscv.vmsof.nxv2i1(
<vscale x 2 x i1>,
i64);
define <vscale x 2 x i1> @intrinsic_vmsof_m_nxv2i1(<vscale x 2 x i1> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsof_m_nxv2i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
; CHECK-NEXT: vmsof.m v8, v0
; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsof.nxv2i1(
<vscale x 2 x i1> %0,
i64 %1)
ret <vscale x 2 x i1> %a
}
declare <vscale x 2 x i1> @llvm.riscv.vmsof.mask.nxv2i1(
<vscale x 2 x i1>,
<vscale x 2 x i1>,
<vscale x 2 x i1>,
i64);
define <vscale x 2 x i1> @intrinsic_vmsof_mask_m_nxv2i1_nxv2i1(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsof_mask_m_nxv2i1_nxv2i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, tu, mu
; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsof.m v10, v8, v0.t
; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsof.mask.nxv2i1(
<vscale x 2 x i1> %0,
<vscale x 2 x i1> %1,
<vscale x 2 x i1> %2,
i64 %3)
ret <vscale x 2 x i1> %a
}
declare <vscale x 4 x i1> @llvm.riscv.vmsof.nxv4i1(
<vscale x 4 x i1>,
i64);
define <vscale x 4 x i1> @intrinsic_vmsof_m_nxv4i1(<vscale x 4 x i1> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsof_m_nxv4i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
; CHECK-NEXT: vmsof.m v8, v0
; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsof.nxv4i1(
<vscale x 4 x i1> %0,
i64 %1)
ret <vscale x 4 x i1> %a
}
declare <vscale x 4 x i1> @llvm.riscv.vmsof.mask.nxv4i1(
<vscale x 4 x i1>,
<vscale x 4 x i1>,
<vscale x 4 x i1>,
i64);
define <vscale x 4 x i1> @intrinsic_vmsof_mask_m_nxv4i1_nxv4i1(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsof_mask_m_nxv4i1_nxv4i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, mu
; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsof.m v10, v8, v0.t
; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsof.mask.nxv4i1(
<vscale x 4 x i1> %0,
<vscale x 4 x i1> %1,
<vscale x 4 x i1> %2,
i64 %3)
ret <vscale x 4 x i1> %a
}
declare <vscale x 8 x i1> @llvm.riscv.vmsof.nxv8i1(
<vscale x 8 x i1>,
i64);
define <vscale x 8 x i1> @intrinsic_vmsof_m_nxv8i1(<vscale x 8 x i1> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsof_m_nxv8i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
; CHECK-NEXT: vmsof.m v8, v0
; CHECK-NEXT: vmv.v.v v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsof.nxv8i1(
<vscale x 8 x i1> %0,
i64 %1)
ret <vscale x 8 x i1> %a
}
declare <vscale x 8 x i1> @llvm.riscv.vmsof.mask.nxv8i1(
<vscale x 8 x i1>,
<vscale x 8 x i1>,
<vscale x 8 x i1>,
i64);
define <vscale x 8 x i1> @intrinsic_vmsof_mask_m_nxv8i1_nxv8i1(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsof_mask_m_nxv8i1_nxv8i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, mu
; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsof.m v10, v8, v0.t
; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsof.mask.nxv8i1(
<vscale x 8 x i1> %0,
<vscale x 8 x i1> %1,
<vscale x 8 x i1> %2,
i64 %3)
ret <vscale x 8 x i1> %a
}
declare <vscale x 16 x i1> @llvm.riscv.vmsof.nxv16i1(
<vscale x 16 x i1>,
i64);
define <vscale x 16 x i1> @intrinsic_vmsof_m_nxv16i1(<vscale x 16 x i1> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsof_m_nxv16i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
; CHECK-NEXT: vmsof.m v8, v0
; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsof.nxv16i1(
<vscale x 16 x i1> %0,
i64 %1)
ret <vscale x 16 x i1> %a
}
declare <vscale x 16 x i1> @llvm.riscv.vmsof.mask.nxv16i1(
<vscale x 16 x i1>,
<vscale x 16 x i1>,
<vscale x 16 x i1>,
i64);
define <vscale x 16 x i1> @intrinsic_vmsof_mask_m_nxv16i1_nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsof_mask_m_nxv16i1_nxv16i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m2, tu, mu
; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsof.m v10, v8, v0.t
; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsof.mask.nxv16i1(
<vscale x 16 x i1> %0,
<vscale x 16 x i1> %1,
<vscale x 16 x i1> %2,
i64 %3)
ret <vscale x 16 x i1> %a
}
declare <vscale x 32 x i1> @llvm.riscv.vmsof.nxv32i1(
<vscale x 32 x i1>,
i64);
define <vscale x 32 x i1> @intrinsic_vmsof_m_nxv32i1(<vscale x 32 x i1> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsof_m_nxv32i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
; CHECK-NEXT: vmsof.m v8, v0
; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsof.nxv32i1(
<vscale x 32 x i1> %0,
i64 %1)
ret <vscale x 32 x i1> %a
}
declare <vscale x 32 x i1> @llvm.riscv.vmsof.mask.nxv32i1(
<vscale x 32 x i1>,
<vscale x 32 x i1>,
<vscale x 32 x i1>,
i64);
define <vscale x 32 x i1> @intrinsic_vmsof_mask_m_nxv32i1_nxv32i1(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, <vscale x 32 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsof_mask_m_nxv32i1_nxv32i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m4, tu, mu
; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsof.m v10, v8, v0.t
; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsof.mask.nxv32i1(
<vscale x 32 x i1> %0,
<vscale x 32 x i1> %1,
<vscale x 32 x i1> %2,
i64 %3)
ret <vscale x 32 x i1> %a
}
declare <vscale x 64 x i1> @llvm.riscv.vmsof.nxv64i1(
<vscale x 64 x i1>,
i64);
define <vscale x 64 x i1> @intrinsic_vmsof_m_nxv64i1(<vscale x 64 x i1> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsof_m_nxv64i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu
; CHECK-NEXT: vmsof.m v8, v0
; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 64 x i1> @llvm.riscv.vmsof.nxv64i1(
<vscale x 64 x i1> %0,
i64 %1)
ret <vscale x 64 x i1> %a
}
declare <vscale x 64 x i1> @llvm.riscv.vmsof.mask.nxv64i1(
<vscale x 64 x i1>,
<vscale x 64 x i1>,
<vscale x 64 x i1>,
i64);
define <vscale x 64 x i1> @intrinsic_vmsof_mask_m_nxv64i1_nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, <vscale x 64 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsof_mask_m_nxv64i1_nxv64i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m8, tu, mu
; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsof.m v10, v8, v0.t
; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 64 x i1> @llvm.riscv.vmsof.mask.nxv64i1(
<vscale x 64 x i1> %0,
<vscale x 64 x i1> %1,
<vscale x 64 x i1> %2,
i64 %3)
ret <vscale x 64 x i1> %a
}

llvm/test/CodeGen/RISCV/rvv/vmsof.ll

  • This file was moved from llvm/test/CodeGen/RISCV/rvv/vmsof-rv32.ll.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs \ ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v \
; RUN: < %s | FileCheck %s ; RUN: -verify-machineinstrs | FileCheck %s
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v \
; RUN: -verify-machineinstrs | FileCheck %s
declare <vscale x 1 x i1> @llvm.riscv.vmsof.nxv1i1( declare <vscale x 1 x i1> @llvm.riscv.vmsof.nxv1i1(
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); iXLen);
define <vscale x 1 x i1> @intrinsic_vmsof_m_nxv1i1(<vscale x 1 x i1> %0, i32 %1) nounwind { define <vscale x 1 x i1> @intrinsic_vmsof_m_nxv1i1(<vscale x 1 x i1> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vmsof_m_nxv1i1: ; CHECK-LABEL: intrinsic_vmsof_m_nxv1i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
; CHECK-NEXT: vmsof.m v8, v0 ; CHECK-NEXT: vmsof.m v8, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsof.nxv1i1( %a = call <vscale x 1 x i1> @llvm.riscv.vmsof.nxv1i1(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
i32 %1) iXLen %1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsof.mask.nxv1i1( declare <vscale x 1 x i1> @llvm.riscv.vmsof.mask.nxv1i1(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); iXLen);
define <vscale x 1 x i1> @intrinsic_vmsof_mask_m_nxv1i1_nxv1i1(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, <vscale x 1 x i1> %2, i32 %3) nounwind { define <vscale x 1 x i1> @intrinsic_vmsof_mask_m_nxv1i1_nxv1i1(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vmsof_mask_m_nxv1i1_nxv1i1: ; CHECK-LABEL: intrinsic_vmsof_mask_m_nxv1i1_nxv1i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsof.m v10, v8, v0.t ; CHECK-NEXT: vmsof.m v10, v8, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsof.mask.nxv1i1( %a = call <vscale x 1 x i1> @llvm.riscv.vmsof.mask.nxv1i1(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i1> %1, <vscale x 1 x i1> %1,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i32 %3) iXLen %3)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsof.nxv2i1( declare <vscale x 2 x i1> @llvm.riscv.vmsof.nxv2i1(
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); iXLen);
define <vscale x 2 x i1> @intrinsic_vmsof_m_nxv2i1(<vscale x 2 x i1> %0, i32 %1) nounwind { define <vscale x 2 x i1> @intrinsic_vmsof_m_nxv2i1(<vscale x 2 x i1> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vmsof_m_nxv2i1: ; CHECK-LABEL: intrinsic_vmsof_m_nxv2i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
; CHECK-NEXT: vmsof.m v8, v0 ; CHECK-NEXT: vmsof.m v8, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsof.nxv2i1( %a = call <vscale x 2 x i1> @llvm.riscv.vmsof.nxv2i1(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
i32 %1) iXLen %1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsof.mask.nxv2i1( declare <vscale x 2 x i1> @llvm.riscv.vmsof.mask.nxv2i1(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); iXLen);
define <vscale x 2 x i1> @intrinsic_vmsof_mask_m_nxv2i1_nxv2i1(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, <vscale x 2 x i1> %2, i32 %3) nounwind { define <vscale x 2 x i1> @intrinsic_vmsof_mask_m_nxv2i1_nxv2i1(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vmsof_mask_m_nxv2i1_nxv2i1: ; CHECK-LABEL: intrinsic_vmsof_mask_m_nxv2i1_nxv2i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, tu, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsof.m v10, v8, v0.t ; CHECK-NEXT: vmsof.m v10, v8, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsof.mask.nxv2i1( %a = call <vscale x 2 x i1> @llvm.riscv.vmsof.mask.nxv2i1(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i1> %1, <vscale x 2 x i1> %1,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i32 %3) iXLen %3)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsof.nxv4i1( declare <vscale x 4 x i1> @llvm.riscv.vmsof.nxv4i1(
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); iXLen);
define <vscale x 4 x i1> @intrinsic_vmsof_m_nxv4i1(<vscale x 4 x i1> %0, i32 %1) nounwind { define <vscale x 4 x i1> @intrinsic_vmsof_m_nxv4i1(<vscale x 4 x i1> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vmsof_m_nxv4i1: ; CHECK-LABEL: intrinsic_vmsof_m_nxv4i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
; CHECK-NEXT: vmsof.m v8, v0 ; CHECK-NEXT: vmsof.m v8, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsof.nxv4i1( %a = call <vscale x 4 x i1> @llvm.riscv.vmsof.nxv4i1(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
i32 %1) iXLen %1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsof.mask.nxv4i1( declare <vscale x 4 x i1> @llvm.riscv.vmsof.mask.nxv4i1(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); iXLen);
define <vscale x 4 x i1> @intrinsic_vmsof_mask_m_nxv4i1_nxv4i1(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, <vscale x 4 x i1> %2, i32 %3) nounwind { define <vscale x 4 x i1> @intrinsic_vmsof_mask_m_nxv4i1_nxv4i1(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vmsof_mask_m_nxv4i1_nxv4i1: ; CHECK-LABEL: intrinsic_vmsof_mask_m_nxv4i1_nxv4i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsof.m v10, v8, v0.t ; CHECK-NEXT: vmsof.m v10, v8, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsof.mask.nxv4i1( %a = call <vscale x 4 x i1> @llvm.riscv.vmsof.mask.nxv4i1(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i1> %1, <vscale x 4 x i1> %1,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i32 %3) iXLen %3)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsof.nxv8i1( declare <vscale x 8 x i1> @llvm.riscv.vmsof.nxv8i1(
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); iXLen);
define <vscale x 8 x i1> @intrinsic_vmsof_m_nxv8i1(<vscale x 8 x i1> %0, i32 %1) nounwind { define <vscale x 8 x i1> @intrinsic_vmsof_m_nxv8i1(<vscale x 8 x i1> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vmsof_m_nxv8i1: ; CHECK-LABEL: intrinsic_vmsof_m_nxv8i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
; CHECK-NEXT: vmsof.m v8, v0 ; CHECK-NEXT: vmsof.m v8, v0
; CHECK-NEXT: vmv.v.v v0, v8 ; CHECK-NEXT: vmv.v.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsof.nxv8i1( %a = call <vscale x 8 x i1> @llvm.riscv.vmsof.nxv8i1(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
i32 %1) iXLen %1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsof.mask.nxv8i1( declare <vscale x 8 x i1> @llvm.riscv.vmsof.mask.nxv8i1(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); iXLen);
define <vscale x 8 x i1> @intrinsic_vmsof_mask_m_nxv8i1_nxv8i1(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, <vscale x 8 x i1> %2, i32 %3) nounwind { define <vscale x 8 x i1> @intrinsic_vmsof_mask_m_nxv8i1_nxv8i1(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vmsof_mask_m_nxv8i1_nxv8i1: ; CHECK-LABEL: intrinsic_vmsof_mask_m_nxv8i1_nxv8i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsof.m v10, v8, v0.t ; CHECK-NEXT: vmsof.m v10, v8, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsof.mask.nxv8i1( %a = call <vscale x 8 x i1> @llvm.riscv.vmsof.mask.nxv8i1(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i1> %1, <vscale x 8 x i1> %1,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i32 %3) iXLen %3)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsof.nxv16i1( declare <vscale x 16 x i1> @llvm.riscv.vmsof.nxv16i1(
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); iXLen);
define <vscale x 16 x i1> @intrinsic_vmsof_m_nxv16i1(<vscale x 16 x i1> %0, i32 %1) nounwind { define <vscale x 16 x i1> @intrinsic_vmsof_m_nxv16i1(<vscale x 16 x i1> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vmsof_m_nxv16i1: ; CHECK-LABEL: intrinsic_vmsof_m_nxv16i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
; CHECK-NEXT: vmsof.m v8, v0 ; CHECK-NEXT: vmsof.m v8, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsof.nxv16i1( %a = call <vscale x 16 x i1> @llvm.riscv.vmsof.nxv16i1(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
i32 %1) iXLen %1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsof.mask.nxv16i1( declare <vscale x 16 x i1> @llvm.riscv.vmsof.mask.nxv16i1(
<vscale x 16 x i1>, <vscale x 16 x i1>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); iXLen);
define <vscale x 16 x i1> @intrinsic_vmsof_mask_m_nxv16i1_nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, <vscale x 16 x i1> %2, i32 %3) nounwind { define <vscale x 16 x i1> @intrinsic_vmsof_mask_m_nxv16i1_nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, <vscale x 16 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vmsof_mask_m_nxv16i1_nxv16i1: ; CHECK-LABEL: intrinsic_vmsof_mask_m_nxv16i1_nxv16i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m2, tu, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsof.m v10, v8, v0.t ; CHECK-NEXT: vmsof.m v10, v8, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsof.mask.nxv16i1( %a = call <vscale x 16 x i1> @llvm.riscv.vmsof.mask.nxv16i1(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i1> %1, <vscale x 16 x i1> %1,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
i32 %3) iXLen %3)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 32 x i1> @llvm.riscv.vmsof.nxv32i1( declare <vscale x 32 x i1> @llvm.riscv.vmsof.nxv32i1(
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); iXLen);
define <vscale x 32 x i1> @intrinsic_vmsof_m_nxv32i1(<vscale x 32 x i1> %0, i32 %1) nounwind { define <vscale x 32 x i1> @intrinsic_vmsof_m_nxv32i1(<vscale x 32 x i1> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vmsof_m_nxv32i1: ; CHECK-LABEL: intrinsic_vmsof_m_nxv32i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
; CHECK-NEXT: vmsof.m v8, v0 ; CHECK-NEXT: vmsof.m v8, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsof.nxv32i1( %a = call <vscale x 32 x i1> @llvm.riscv.vmsof.nxv32i1(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
i32 %1) iXLen %1)
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
declare <vscale x 32 x i1> @llvm.riscv.vmsof.mask.nxv32i1( declare <vscale x 32 x i1> @llvm.riscv.vmsof.mask.nxv32i1(
<vscale x 32 x i1>, <vscale x 32 x i1>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); iXLen);
define <vscale x 32 x i1> @intrinsic_vmsof_mask_m_nxv32i1_nxv32i1(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, <vscale x 32 x i1> %2, i32 %3) nounwind { define <vscale x 32 x i1> @intrinsic_vmsof_mask_m_nxv32i1_nxv32i1(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, <vscale x 32 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vmsof_mask_m_nxv32i1_nxv32i1: ; CHECK-LABEL: intrinsic_vmsof_mask_m_nxv32i1_nxv32i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m4, tu, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsof.m v10, v8, v0.t ; CHECK-NEXT: vmsof.m v10, v8, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsof.mask.nxv32i1( %a = call <vscale x 32 x i1> @llvm.riscv.vmsof.mask.nxv32i1(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
<vscale x 32 x i1> %1, <vscale x 32 x i1> %1,
<vscale x 32 x i1> %2, <vscale x 32 x i1> %2,
i32 %3) iXLen %3)
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
declare <vscale x 64 x i1> @llvm.riscv.vmsof.nxv64i1( declare <vscale x 64 x i1> @llvm.riscv.vmsof.nxv64i1(
<vscale x 64 x i1>, <vscale x 64 x i1>,
i32); iXLen);
define <vscale x 64 x i1> @intrinsic_vmsof_m_nxv64i1(<vscale x 64 x i1> %0, i32 %1) nounwind { define <vscale x 64 x i1> @intrinsic_vmsof_m_nxv64i1(<vscale x 64 x i1> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vmsof_m_nxv64i1: ; CHECK-LABEL: intrinsic_vmsof_m_nxv64i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu
; CHECK-NEXT: vmsof.m v8, v0 ; CHECK-NEXT: vmsof.m v8, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 64 x i1> @llvm.riscv.vmsof.nxv64i1( %a = call <vscale x 64 x i1> @llvm.riscv.vmsof.nxv64i1(
<vscale x 64 x i1> %0, <vscale x 64 x i1> %0,
i32 %1) iXLen %1)
ret <vscale x 64 x i1> %a ret <vscale x 64 x i1> %a
} }
declare <vscale x 64 x i1> @llvm.riscv.vmsof.mask.nxv64i1( declare <vscale x 64 x i1> @llvm.riscv.vmsof.mask.nxv64i1(
<vscale x 64 x i1>, <vscale x 64 x i1>,
<vscale x 64 x i1>, <vscale x 64 x i1>,
<vscale x 64 x i1>, <vscale x 64 x i1>,
i32); iXLen);
define <vscale x 64 x i1> @intrinsic_vmsof_mask_m_nxv64i1_nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, <vscale x 64 x i1> %2, i32 %3) nounwind { define <vscale x 64 x i1> @intrinsic_vmsof_mask_m_nxv64i1_nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, <vscale x 64 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vmsof_mask_m_nxv64i1_nxv64i1: ; CHECK-LABEL: intrinsic_vmsof_mask_m_nxv64i1_nxv64i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m8, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m8, tu, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsof.m v10, v8, v0.t ; CHECK-NEXT: vmsof.m v10, v8, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 64 x i1> @llvm.riscv.vmsof.mask.nxv64i1( %a = call <vscale x 64 x i1> @llvm.riscv.vmsof.mask.nxv64i1(
<vscale x 64 x i1> %0, <vscale x 64 x i1> %0,
<vscale x 64 x i1> %1, <vscale x 64 x i1> %1,
<vscale x 64 x i1> %2, <vscale x 64 x i1> %2,
i32 %3) iXLen %3)
ret <vscale x 64 x i1> %a ret <vscale x 64 x i1> %a
} }

llvm/test/CodeGen/RISCV/rvv/vmxnor-rv32.ll

  • This file was moved to llvm/test/CodeGen/RISCV/rvv/vmxnor.ll.

llvm/test/CodeGen/RISCV/rvv/vmxnor-rv64.ll

  • This file was deleted.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+v,+d -verify-machineinstrs \
; RUN: < %s | FileCheck %s
declare <vscale x 1 x i1> @llvm.riscv.vmxnor.nxv1i1(
<vscale x 1 x i1>,
<vscale x 1 x i1>,
i64);
define <vscale x 1 x i1> @intrinsic_vmxnor_mm_nxv1i1(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmxnor_mm_nxv1i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
; CHECK-NEXT: vmxnor.mm v0, v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmxnor.nxv1i1(
<vscale x 1 x i1> %0,
<vscale x 1 x i1> %1,
i64 %2)
ret <vscale x 1 x i1> %a
}
declare <vscale x 2 x i1> @llvm.riscv.vmxnor.nxv2i1(
<vscale x 2 x i1>,
<vscale x 2 x i1>,
i64);
define <vscale x 2 x i1> @intrinsic_vmxnor_mm_nxv2i1(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmxnor_mm_nxv2i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
; CHECK-NEXT: vmxnor.mm v0, v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmxnor.nxv2i1(
<vscale x 2 x i1> %0,
<vscale x 2 x i1> %1,
i64 %2)
ret <vscale x 2 x i1> %a
}
declare <vscale x 4 x i1> @llvm.riscv.vmxnor.nxv4i1(
<vscale x 4 x i1>,
<vscale x 4 x i1>,
i64);
define <vscale x 4 x i1> @intrinsic_vmxnor_mm_nxv4i1(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmxnor_mm_nxv4i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
; CHECK-NEXT: vmxnor.mm v0, v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmxnor.nxv4i1(
<vscale x 4 x i1> %0,
<vscale x 4 x i1> %1,
i64 %2)
ret <vscale x 4 x i1> %a
}
declare <vscale x 8 x i1> @llvm.riscv.vmxnor.nxv8i1(
<vscale x 8 x i1>,
<vscale x 8 x i1>,
i64);
define <vscale x 8 x i1> @intrinsic_vmxnor_mm_nxv8i1(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmxnor_mm_nxv8i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
; CHECK-NEXT: vmxnor.mm v0, v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmxnor.nxv8i1(
<vscale x 8 x i1> %0,
<vscale x 8 x i1> %1,
i64 %2)
ret <vscale x 8 x i1> %a
}
declare <vscale x 16 x i1> @llvm.riscv.vmxnor.nxv16i1(
<vscale x 16 x i1>,
<vscale x 16 x i1>,
i64);
define <vscale x 16 x i1> @intrinsic_vmxnor_mm_nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmxnor_mm_nxv16i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
; CHECK-NEXT: vmxnor.mm v0, v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmxnor.nxv16i1(
<vscale x 16 x i1> %0,
<vscale x 16 x i1> %1,
i64 %2)
ret <vscale x 16 x i1> %a
}
declare <vscale x 32 x i1> @llvm.riscv.vmxnor.nxv32i1(
<vscale x 32 x i1>,
<vscale x 32 x i1>,
i64);
define <vscale x 32 x i1> @intrinsic_vmxnor_mm_nxv32i1(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmxnor_mm_nxv32i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
; CHECK-NEXT: vmxnor.mm v0, v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmxnor.nxv32i1(
<vscale x 32 x i1> %0,
<vscale x 32 x i1> %1,
i64 %2)
ret <vscale x 32 x i1> %a
}
declare <vscale x 64 x i1> @llvm.riscv.vmxnor.nxv64i1(
<vscale x 64 x i1>,
<vscale x 64 x i1>,
i64);
define <vscale x 64 x i1> @intrinsic_vmxnor_mm_nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmxnor_mm_nxv64i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu
; CHECK-NEXT: vmxnor.mm v0, v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 64 x i1> @llvm.riscv.vmxnor.nxv64i1(
<vscale x 64 x i1> %0,
<vscale x 64 x i1> %1,
i64 %2)
ret <vscale x 64 x i1> %a
}

llvm/test/CodeGen/RISCV/rvv/vmxnor.ll

  • This file was moved from llvm/test/CodeGen/RISCV/rvv/vmxnor-rv32.ll.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+v,+f -verify-machineinstrs \ ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v \
; RUN: < %s | FileCheck %s ; RUN: -verify-machineinstrs | FileCheck %s
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v \
; RUN: -verify-machineinstrs | FileCheck %s
declare <vscale x 1 x i1> @llvm.riscv.vmxnor.nxv1i1( declare <vscale x 1 x i1> @llvm.riscv.vmxnor.nxv1i1(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); iXLen);
define <vscale x 1 x i1> @intrinsic_vmxnor_mm_nxv1i1(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, i32 %2) nounwind { define <vscale x 1 x i1> @intrinsic_vmxnor_mm_nxv1i1(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmxnor_mm_nxv1i1: ; CHECK-LABEL: intrinsic_vmxnor_mm_nxv1i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
; CHECK-NEXT: vmxnor.mm v0, v0, v8 ; CHECK-NEXT: vmxnor.mm v0, v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmxnor.nxv1i1( %a = call <vscale x 1 x i1> @llvm.riscv.vmxnor.nxv1i1(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i1> %1, <vscale x 1 x i1> %1,
i32 %2) iXLen %2)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmxnor.nxv2i1( declare <vscale x 2 x i1> @llvm.riscv.vmxnor.nxv2i1(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); iXLen);
define <vscale x 2 x i1> @intrinsic_vmxnor_mm_nxv2i1(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, i32 %2) nounwind { define <vscale x 2 x i1> @intrinsic_vmxnor_mm_nxv2i1(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmxnor_mm_nxv2i1: ; CHECK-LABEL: intrinsic_vmxnor_mm_nxv2i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
; CHECK-NEXT: vmxnor.mm v0, v0, v8 ; CHECK-NEXT: vmxnor.mm v0, v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmxnor.nxv2i1( %a = call <vscale x 2 x i1> @llvm.riscv.vmxnor.nxv2i1(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i1> %1, <vscale x 2 x i1> %1,
i32 %2) iXLen %2)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmxnor.nxv4i1( declare <vscale x 4 x i1> @llvm.riscv.vmxnor.nxv4i1(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); iXLen);
define <vscale x 4 x i1> @intrinsic_vmxnor_mm_nxv4i1(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, i32 %2) nounwind { define <vscale x 4 x i1> @intrinsic_vmxnor_mm_nxv4i1(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmxnor_mm_nxv4i1: ; CHECK-LABEL: intrinsic_vmxnor_mm_nxv4i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
; CHECK-NEXT: vmxnor.mm v0, v0, v8 ; CHECK-NEXT: vmxnor.mm v0, v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmxnor.nxv4i1( %a = call <vscale x 4 x i1> @llvm.riscv.vmxnor.nxv4i1(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i1> %1, <vscale x 4 x i1> %1,
i32 %2) iXLen %2)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmxnor.nxv8i1( declare <vscale x 8 x i1> @llvm.riscv.vmxnor.nxv8i1(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); iXLen);
define <vscale x 8 x i1> @intrinsic_vmxnor_mm_nxv8i1(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, i32 %2) nounwind { define <vscale x 8 x i1> @intrinsic_vmxnor_mm_nxv8i1(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmxnor_mm_nxv8i1: ; CHECK-LABEL: intrinsic_vmxnor_mm_nxv8i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
; CHECK-NEXT: vmxnor.mm v0, v0, v8 ; CHECK-NEXT: vmxnor.mm v0, v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmxnor.nxv8i1( %a = call <vscale x 8 x i1> @llvm.riscv.vmxnor.nxv8i1(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i1> %1, <vscale x 8 x i1> %1,
i32 %2) iXLen %2)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmxnor.nxv16i1( declare <vscale x 16 x i1> @llvm.riscv.vmxnor.nxv16i1(
<vscale x 16 x i1>, <vscale x 16 x i1>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); iXLen);
define <vscale x 16 x i1> @intrinsic_vmxnor_mm_nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, i32 %2) nounwind { define <vscale x 16 x i1> @intrinsic_vmxnor_mm_nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmxnor_mm_nxv16i1: ; CHECK-LABEL: intrinsic_vmxnor_mm_nxv16i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
; CHECK-NEXT: vmxnor.mm v0, v0, v8 ; CHECK-NEXT: vmxnor.mm v0, v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmxnor.nxv16i1( %a = call <vscale x 16 x i1> @llvm.riscv.vmxnor.nxv16i1(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i1> %1, <vscale x 16 x i1> %1,
i32 %2) iXLen %2)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 32 x i1> @llvm.riscv.vmxnor.nxv32i1( declare <vscale x 32 x i1> @llvm.riscv.vmxnor.nxv32i1(
<vscale x 32 x i1>, <vscale x 32 x i1>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); iXLen);
define <vscale x 32 x i1> @intrinsic_vmxnor_mm_nxv32i1(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, i32 %2) nounwind { define <vscale x 32 x i1> @intrinsic_vmxnor_mm_nxv32i1(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmxnor_mm_nxv32i1: ; CHECK-LABEL: intrinsic_vmxnor_mm_nxv32i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
; CHECK-NEXT: vmxnor.mm v0, v0, v8 ; CHECK-NEXT: vmxnor.mm v0, v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmxnor.nxv32i1( %a = call <vscale x 32 x i1> @llvm.riscv.vmxnor.nxv32i1(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
<vscale x 32 x i1> %1, <vscale x 32 x i1> %1,
i32 %2) iXLen %2)
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
declare <vscale x 64 x i1> @llvm.riscv.vmxnor.nxv64i1( declare <vscale x 64 x i1> @llvm.riscv.vmxnor.nxv64i1(
<vscale x 64 x i1>, <vscale x 64 x i1>,
<vscale x 64 x i1>, <vscale x 64 x i1>,
i32); iXLen);
define <vscale x 64 x i1> @intrinsic_vmxnor_mm_nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, i32 %2) nounwind { define <vscale x 64 x i1> @intrinsic_vmxnor_mm_nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmxnor_mm_nxv64i1: ; CHECK-LABEL: intrinsic_vmxnor_mm_nxv64i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu
; CHECK-NEXT: vmxnor.mm v0, v0, v8 ; CHECK-NEXT: vmxnor.mm v0, v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 64 x i1> @llvm.riscv.vmxnor.nxv64i1( %a = call <vscale x 64 x i1> @llvm.riscv.vmxnor.nxv64i1(
<vscale x 64 x i1> %0, <vscale x 64 x i1> %0,
<vscale x 64 x i1> %1, <vscale x 64 x i1> %1,
i32 %2) iXLen %2)
ret <vscale x 64 x i1> %a ret <vscale x 64 x i1> %a
} }

llvm/test/CodeGen/RISCV/rvv/vmxor-rv32.ll

  • This file was moved to llvm/test/CodeGen/RISCV/rvv/vmxor.ll.

llvm/test/CodeGen/RISCV/rvv/vmxor-rv64.ll

  • This file was deleted.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+v,+d -verify-machineinstrs \
; RUN: < %s | FileCheck %s
declare <vscale x 1 x i1> @llvm.riscv.vmxor.nxv1i1(
<vscale x 1 x i1>,
<vscale x 1 x i1>,
i64);
define <vscale x 1 x i1> @intrinsic_vmxor_mm_nxv1i1(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmxor_mm_nxv1i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
; CHECK-NEXT: vmxor.mm v0, v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmxor.nxv1i1(
<vscale x 1 x i1> %0,
<vscale x 1 x i1> %1,
i64 %2)
ret <vscale x 1 x i1> %a
}
declare <vscale x 2 x i1> @llvm.riscv.vmxor.nxv2i1(
<vscale x 2 x i1>,
<vscale x 2 x i1>,
i64);
define <vscale x 2 x i1> @intrinsic_vmxor_mm_nxv2i1(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmxor_mm_nxv2i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
; CHECK-NEXT: vmxor.mm v0, v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmxor.nxv2i1(
<vscale x 2 x i1> %0,
<vscale x 2 x i1> %1,
i64 %2)
ret <vscale x 2 x i1> %a
}
declare <vscale x 4 x i1> @llvm.riscv.vmxor.nxv4i1(
<vscale x 4 x i1>,
<vscale x 4 x i1>,
i64);
define <vscale x 4 x i1> @intrinsic_vmxor_mm_nxv4i1(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmxor_mm_nxv4i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
; CHECK-NEXT: vmxor.mm v0, v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmxor.nxv4i1(
<vscale x 4 x i1> %0,
<vscale x 4 x i1> %1,
i64 %2)
ret <vscale x 4 x i1> %a
}
declare <vscale x 8 x i1> @llvm.riscv.vmxor.nxv8i1(
<vscale x 8 x i1>,
<vscale x 8 x i1>,
i64);
define <vscale x 8 x i1> @intrinsic_vmxor_mm_nxv8i1(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmxor_mm_nxv8i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
; CHECK-NEXT: vmxor.mm v0, v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmxor.nxv8i1(
<vscale x 8 x i1> %0,
<vscale x 8 x i1> %1,
i64 %2)
ret <vscale x 8 x i1> %a
}
declare <vscale x 16 x i1> @llvm.riscv.vmxor.nxv16i1(
<vscale x 16 x i1>,
<vscale x 16 x i1>,
i64);
define <vscale x 16 x i1> @intrinsic_vmxor_mm_nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmxor_mm_nxv16i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
; CHECK-NEXT: vmxor.mm v0, v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmxor.nxv16i1(
<vscale x 16 x i1> %0,
<vscale x 16 x i1> %1,
i64 %2)
ret <vscale x 16 x i1> %a
}
declare <vscale x 32 x i1> @llvm.riscv.vmxor.nxv32i1(
<vscale x 32 x i1>,
<vscale x 32 x i1>,
i64);
define <vscale x 32 x i1> @intrinsic_vmxor_mm_nxv32i1(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmxor_mm_nxv32i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
; CHECK-NEXT: vmxor.mm v0, v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmxor.nxv32i1(
<vscale x 32 x i1> %0,
<vscale x 32 x i1> %1,
i64 %2)
ret <vscale x 32 x i1> %a
}
declare <vscale x 64 x i1> @llvm.riscv.vmxor.nxv64i1(
<vscale x 64 x i1>,
<vscale x 64 x i1>,
i64);
define <vscale x 64 x i1> @intrinsic_vmxor_mm_nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmxor_mm_nxv64i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu
; CHECK-NEXT: vmxor.mm v0, v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 64 x i1> @llvm.riscv.vmxor.nxv64i1(
<vscale x 64 x i1> %0,
<vscale x 64 x i1> %1,
i64 %2)
ret <vscale x 64 x i1> %a
}

llvm/test/CodeGen/RISCV/rvv/vmxor.ll

  • This file was moved from llvm/test/CodeGen/RISCV/rvv/vmxor-rv32.ll.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+v,+f -verify-machineinstrs \ ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v \
; RUN: < %s | FileCheck %s ; RUN: -verify-machineinstrs | FileCheck %s
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v \
; RUN: -verify-machineinstrs | FileCheck %s
declare <vscale x 1 x i1> @llvm.riscv.vmxor.nxv1i1( declare <vscale x 1 x i1> @llvm.riscv.vmxor.nxv1i1(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); iXLen);
define <vscale x 1 x i1> @intrinsic_vmxor_mm_nxv1i1(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, i32 %2) nounwind { define <vscale x 1 x i1> @intrinsic_vmxor_mm_nxv1i1(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmxor_mm_nxv1i1: ; CHECK-LABEL: intrinsic_vmxor_mm_nxv1i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
; CHECK-NEXT: vmxor.mm v0, v0, v8 ; CHECK-NEXT: vmxor.mm v0, v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmxor.nxv1i1( %a = call <vscale x 1 x i1> @llvm.riscv.vmxor.nxv1i1(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i1> %1, <vscale x 1 x i1> %1,
i32 %2) iXLen %2)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmxor.nxv2i1( declare <vscale x 2 x i1> @llvm.riscv.vmxor.nxv2i1(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); iXLen);
define <vscale x 2 x i1> @intrinsic_vmxor_mm_nxv2i1(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, i32 %2) nounwind { define <vscale x 2 x i1> @intrinsic_vmxor_mm_nxv2i1(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmxor_mm_nxv2i1: ; CHECK-LABEL: intrinsic_vmxor_mm_nxv2i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
; CHECK-NEXT: vmxor.mm v0, v0, v8 ; CHECK-NEXT: vmxor.mm v0, v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmxor.nxv2i1( %a = call <vscale x 2 x i1> @llvm.riscv.vmxor.nxv2i1(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i1> %1, <vscale x 2 x i1> %1,
i32 %2) iXLen %2)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmxor.nxv4i1( declare <vscale x 4 x i1> @llvm.riscv.vmxor.nxv4i1(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); iXLen);
define <vscale x 4 x i1> @intrinsic_vmxor_mm_nxv4i1(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, i32 %2) nounwind { define <vscale x 4 x i1> @intrinsic_vmxor_mm_nxv4i1(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmxor_mm_nxv4i1: ; CHECK-LABEL: intrinsic_vmxor_mm_nxv4i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
; CHECK-NEXT: vmxor.mm v0, v0, v8 ; CHECK-NEXT: vmxor.mm v0, v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmxor.nxv4i1( %a = call <vscale x 4 x i1> @llvm.riscv.vmxor.nxv4i1(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i1> %1, <vscale x 4 x i1> %1,
i32 %2) iXLen %2)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmxor.nxv8i1( declare <vscale x 8 x i1> @llvm.riscv.vmxor.nxv8i1(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); iXLen);
define <vscale x 8 x i1> @intrinsic_vmxor_mm_nxv8i1(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, i32 %2) nounwind { define <vscale x 8 x i1> @intrinsic_vmxor_mm_nxv8i1(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmxor_mm_nxv8i1: ; CHECK-LABEL: intrinsic_vmxor_mm_nxv8i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
; CHECK-NEXT: vmxor.mm v0, v0, v8 ; CHECK-NEXT: vmxor.mm v0, v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmxor.nxv8i1( %a = call <vscale x 8 x i1> @llvm.riscv.vmxor.nxv8i1(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i1> %1, <vscale x 8 x i1> %1,
i32 %2) iXLen %2)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmxor.nxv16i1( declare <vscale x 16 x i1> @llvm.riscv.vmxor.nxv16i1(
<vscale x 16 x i1>, <vscale x 16 x i1>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); iXLen);
define <vscale x 16 x i1> @intrinsic_vmxor_mm_nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, i32 %2) nounwind { define <vscale x 16 x i1> @intrinsic_vmxor_mm_nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmxor_mm_nxv16i1: ; CHECK-LABEL: intrinsic_vmxor_mm_nxv16i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
; CHECK-NEXT: vmxor.mm v0, v0, v8 ; CHECK-NEXT: vmxor.mm v0, v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmxor.nxv16i1( %a = call <vscale x 16 x i1> @llvm.riscv.vmxor.nxv16i1(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i1> %1, <vscale x 16 x i1> %1,
i32 %2) iXLen %2)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 32 x i1> @llvm.riscv.vmxor.nxv32i1( declare <vscale x 32 x i1> @llvm.riscv.vmxor.nxv32i1(
<vscale x 32 x i1>, <vscale x 32 x i1>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); iXLen);
define <vscale x 32 x i1> @intrinsic_vmxor_mm_nxv32i1(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, i32 %2) nounwind { define <vscale x 32 x i1> @intrinsic_vmxor_mm_nxv32i1(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmxor_mm_nxv32i1: ; CHECK-LABEL: intrinsic_vmxor_mm_nxv32i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
; CHECK-NEXT: vmxor.mm v0, v0, v8 ; CHECK-NEXT: vmxor.mm v0, v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmxor.nxv32i1( %a = call <vscale x 32 x i1> @llvm.riscv.vmxor.nxv32i1(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
<vscale x 32 x i1> %1, <vscale x 32 x i1> %1,
i32 %2) iXLen %2)
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
declare <vscale x 64 x i1> @llvm.riscv.vmxor.nxv64i1( declare <vscale x 64 x i1> @llvm.riscv.vmxor.nxv64i1(
<vscale x 64 x i1>, <vscale x 64 x i1>,
<vscale x 64 x i1>, <vscale x 64 x i1>,
i32); iXLen);
define <vscale x 64 x i1> @intrinsic_vmxor_mm_nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, i32 %2) nounwind { define <vscale x 64 x i1> @intrinsic_vmxor_mm_nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmxor_mm_nxv64i1: ; CHECK-LABEL: intrinsic_vmxor_mm_nxv64i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu
; CHECK-NEXT: vmxor.mm v0, v0, v8 ; CHECK-NEXT: vmxor.mm v0, v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 64 x i1> @llvm.riscv.vmxor.nxv64i1( %a = call <vscale x 64 x i1> @llvm.riscv.vmxor.nxv64i1(
<vscale x 64 x i1> %0, <vscale x 64 x i1> %0,
<vscale x 64 x i1> %1, <vscale x 64 x i1> %1,
i32 %2) iXLen %2)
ret <vscale x 64 x i1> %a ret <vscale x 64 x i1> %a
} }

llvm/test/CodeGen/RISCV/rvv/vsm-rv32.ll

  • This file was moved to llvm/test/CodeGen/RISCV/rvv/vsm.ll.

llvm/test/CodeGen/RISCV/rvv/vsm-rv64.ll

  • This file was deleted.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs \
; RUN: < %s | FileCheck %s
declare void @llvm.riscv.vsm.nxv1i1(<vscale x 1 x i1>, <vscale x 1 x i1>*, i64);
define void @intrinsic_vsm_v_nxv1i1(<vscale x 1 x i1> %0, <vscale x 1 x i1>* %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vsm_v_nxv1i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
; CHECK-NEXT: vsm.v v0, (a0)
; CHECK-NEXT: ret
entry:
call void @llvm.riscv.vsm.nxv1i1(<vscale x 1 x i1> %0, <vscale x 1 x i1>* %1, i64 %2)
ret void
}
declare void @llvm.riscv.vsm.nxv2i1(<vscale x 2 x i1>, <vscale x 2 x i1>*, i64);
define void @intrinsic_vsm_v_nxv2i1(<vscale x 2 x i1> %0, <vscale x 2 x i1>* %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vsm_v_nxv2i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
; CHECK-NEXT: vsm.v v0, (a0)
; CHECK-NEXT: ret
entry:
call void @llvm.riscv.vsm.nxv2i1(<vscale x 2 x i1> %0, <vscale x 2 x i1>* %1, i64 %2)
ret void
}
declare void @llvm.riscv.vsm.nxv4i1(<vscale x 4 x i1>, <vscale x 4 x i1>*, i64);
define void @intrinsic_vsm_v_nxv4i1(<vscale x 4 x i1> %0, <vscale x 4 x i1>* %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vsm_v_nxv4i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
; CHECK-NEXT: vsm.v v0, (a0)
; CHECK-NEXT: ret
entry:
call void @llvm.riscv.vsm.nxv4i1(<vscale x 4 x i1> %0, <vscale x 4 x i1>* %1, i64 %2)
ret void
}
declare void @llvm.riscv.vsm.nxv8i1(<vscale x 8 x i1>, <vscale x 8 x i1>*, i64);
define void @intrinsic_vsm_v_nxv8i1(<vscale x 8 x i1> %0, <vscale x 8 x i1>* %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vsm_v_nxv8i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
; CHECK-NEXT: vsm.v v0, (a0)
; CHECK-NEXT: ret
entry:
call void @llvm.riscv.vsm.nxv8i1(<vscale x 8 x i1> %0, <vscale x 8 x i1>* %1, i64 %2)
ret void
}
declare void @llvm.riscv.vsm.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>*, i64);
define void @intrinsic_vsm_v_nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1>* %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vsm_v_nxv16i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
; CHECK-NEXT: vsm.v v0, (a0)
; CHECK-NEXT: ret
entry:
call void @llvm.riscv.vsm.nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1>* %1, i64 %2)
ret void
}
declare void @llvm.riscv.vsm.nxv32i1(<vscale x 32 x i1>, <vscale x 32 x i1>*, i64);
define void @intrinsic_vsm_v_nxv32i1(<vscale x 32 x i1> %0, <vscale x 32 x i1>* %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vsm_v_nxv32i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
; CHECK-NEXT: vsm.v v0, (a0)
; CHECK-NEXT: ret
entry:
call void @llvm.riscv.vsm.nxv32i1(<vscale x 32 x i1> %0, <vscale x 32 x i1>* %1, i64 %2)
ret void
}
declare void @llvm.riscv.vsm.nxv64i1(<vscale x 64 x i1>, <vscale x 64 x i1>*, i64);
define void @intrinsic_vsm_v_nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1>* %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vsm_v_nxv64i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu
; CHECK-NEXT: vsm.v v0, (a0)
; CHECK-NEXT: ret
entry:
call void @llvm.riscv.vsm.nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1>* %1, i64 %2)
ret void
}
declare <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i16(
<vscale x 1 x i16>,
<vscale x 1 x i16>,
i64);
; Make sure we can use the vsetvli from the producing instruction.
define void @test_vsetvli_i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1>* %2, i64 %3) nounwind {
; CHECK-LABEL: test_vsetvli_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
; CHECK-NEXT: vmseq.vv v8, v8, v9
; CHECK-NEXT: vsm.v v8, (a0)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i16(
<vscale x 1 x i16> %0,
<vscale x 1 x i16> %1,
i64 %3)
call void @llvm.riscv.vsm.nxv1i1(<vscale x 1 x i1> %a, <vscale x 1 x i1>* %2, i64 %3)
ret void
}
declare <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i32(
<vscale x 1 x i32>,
<vscale x 1 x i32>,
i64);
define void @test_vsetvli_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1>* %2, i64 %3) nounwind {
; CHECK-LABEL: test_vsetvli_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
; CHECK-NEXT: vmseq.vv v8, v8, v9
; CHECK-NEXT: vsm.v v8, (a0)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i32(
<vscale x 1 x i32> %0,
<vscale x 1 x i32> %1,
i64 %3)
call void @llvm.riscv.vsm.nxv1i1(<vscale x 1 x i1> %a, <vscale x 1 x i1>* %2, i64 %3)
ret void
}

llvm/test/CodeGen/RISCV/rvv/vsm.ll

  • This file was moved from llvm/test/CodeGen/RISCV/rvv/vsm-rv32.ll.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs \ ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v \
; RUN: < %s | FileCheck %s ; RUN: -verify-machineinstrs | FileCheck %s
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v \
; RUN: -verify-machineinstrs | FileCheck %s
declare void @llvm.riscv.vsm.nxv1i1(<vscale x 1 x i1>, <vscale x 1 x i1>*, i32); declare void @llvm.riscv.vsm.nxv1i1(<vscale x 1 x i1>, <vscale x 1 x i1>*, iXLen);
define void @intrinsic_vsm_v_nxv1i1(<vscale x 1 x i1> %0, <vscale x 1 x i1>* %1, i32 %2) nounwind { define void @intrinsic_vsm_v_nxv1i1(<vscale x 1 x i1> %0, <vscale x 1 x i1>* %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vsm_v_nxv1i1: ; CHECK-LABEL: intrinsic_vsm_v_nxv1i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
; CHECK-NEXT: vsm.v v0, (a0) ; CHECK-NEXT: vsm.v v0, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
call void @llvm.riscv.vsm.nxv1i1(<vscale x 1 x i1> %0, <vscale x 1 x i1>* %1, i32 %2) call void @llvm.riscv.vsm.nxv1i1(<vscale x 1 x i1> %0, <vscale x 1 x i1>* %1, iXLen %2)
ret void ret void
} }
declare void @llvm.riscv.vsm.nxv2i1(<vscale x 2 x i1>, <vscale x 2 x i1>*, i32); declare void @llvm.riscv.vsm.nxv2i1(<vscale x 2 x i1>, <vscale x 2 x i1>*, iXLen);
define void @intrinsic_vsm_v_nxv2i1(<vscale x 2 x i1> %0, <vscale x 2 x i1>* %1, i32 %2) nounwind { define void @intrinsic_vsm_v_nxv2i1(<vscale x 2 x i1> %0, <vscale x 2 x i1>* %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vsm_v_nxv2i1: ; CHECK-LABEL: intrinsic_vsm_v_nxv2i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
; CHECK-NEXT: vsm.v v0, (a0) ; CHECK-NEXT: vsm.v v0, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
call void @llvm.riscv.vsm.nxv2i1(<vscale x 2 x i1> %0, <vscale x 2 x i1>* %1, i32 %2) call void @llvm.riscv.vsm.nxv2i1(<vscale x 2 x i1> %0, <vscale x 2 x i1>* %1, iXLen %2)
ret void ret void
} }
declare void @llvm.riscv.vsm.nxv4i1(<vscale x 4 x i1>, <vscale x 4 x i1>*, i32); declare void @llvm.riscv.vsm.nxv4i1(<vscale x 4 x i1>, <vscale x 4 x i1>*, iXLen);
define void @intrinsic_vsm_v_nxv4i1(<vscale x 4 x i1> %0, <vscale x 4 x i1>* %1, i32 %2) nounwind { define void @intrinsic_vsm_v_nxv4i1(<vscale x 4 x i1> %0, <vscale x 4 x i1>* %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vsm_v_nxv4i1: ; CHECK-LABEL: intrinsic_vsm_v_nxv4i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
; CHECK-NEXT: vsm.v v0, (a0) ; CHECK-NEXT: vsm.v v0, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
call void @llvm.riscv.vsm.nxv4i1(<vscale x 4 x i1> %0, <vscale x 4 x i1>* %1, i32 %2) call void @llvm.riscv.vsm.nxv4i1(<vscale x 4 x i1> %0, <vscale x 4 x i1>* %1, iXLen %2)
ret void ret void
} }
declare void @llvm.riscv.vsm.nxv8i1(<vscale x 8 x i1>, <vscale x 8 x i1>*, i32); declare void @llvm.riscv.vsm.nxv8i1(<vscale x 8 x i1>, <vscale x 8 x i1>*, iXLen);
define void @intrinsic_vsm_v_nxv8i1(<vscale x 8 x i1> %0, <vscale x 8 x i1>* %1, i32 %2) nounwind { define void @intrinsic_vsm_v_nxv8i1(<vscale x 8 x i1> %0, <vscale x 8 x i1>* %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vsm_v_nxv8i1: ; CHECK-LABEL: intrinsic_vsm_v_nxv8i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
; CHECK-NEXT: vsm.v v0, (a0) ; CHECK-NEXT: vsm.v v0, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
call void @llvm.riscv.vsm.nxv8i1(<vscale x 8 x i1> %0, <vscale x 8 x i1>* %1, i32 %2) call void @llvm.riscv.vsm.nxv8i1(<vscale x 8 x i1> %0, <vscale x 8 x i1>* %1, iXLen %2)
ret void ret void
} }
declare void @llvm.riscv.vsm.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>*, i32); declare void @llvm.riscv.vsm.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>*, iXLen);
define void @intrinsic_vsm_v_nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1>* %1, i32 %2) nounwind { define void @intrinsic_vsm_v_nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1>* %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vsm_v_nxv16i1: ; CHECK-LABEL: intrinsic_vsm_v_nxv16i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
; CHECK-NEXT: vsm.v v0, (a0) ; CHECK-NEXT: vsm.v v0, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
call void @llvm.riscv.vsm.nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1>* %1, i32 %2) call void @llvm.riscv.vsm.nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1>* %1, iXLen %2)
ret void ret void
} }
declare void @llvm.riscv.vsm.nxv32i1(<vscale x 32 x i1>, <vscale x 32 x i1>*, i32); declare void @llvm.riscv.vsm.nxv32i1(<vscale x 32 x i1>, <vscale x 32 x i1>*, iXLen);
define void @intrinsic_vsm_v_nxv32i1(<vscale x 32 x i1> %0, <vscale x 32 x i1>* %1, i32 %2) nounwind { define void @intrinsic_vsm_v_nxv32i1(<vscale x 32 x i1> %0, <vscale x 32 x i1>* %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vsm_v_nxv32i1: ; CHECK-LABEL: intrinsic_vsm_v_nxv32i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
; CHECK-NEXT: vsm.v v0, (a0) ; CHECK-NEXT: vsm.v v0, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
call void @llvm.riscv.vsm.nxv32i1(<vscale x 32 x i1> %0, <vscale x 32 x i1>* %1, i32 %2) call void @llvm.riscv.vsm.nxv32i1(<vscale x 32 x i1> %0, <vscale x 32 x i1>* %1, iXLen %2)
ret void ret void
} }
declare void @llvm.riscv.vsm.nxv64i1(<vscale x 64 x i1>, <vscale x 64 x i1>*, i32); declare void @llvm.riscv.vsm.nxv64i1(<vscale x 64 x i1>, <vscale x 64 x i1>*, iXLen);
define void @intrinsic_vsm_v_nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1>* %1, i32 %2) nounwind { define void @intrinsic_vsm_v_nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1>* %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vsm_v_nxv64i1: ; CHECK-LABEL: intrinsic_vsm_v_nxv64i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu
; CHECK-NEXT: vsm.v v0, (a0) ; CHECK-NEXT: vsm.v v0, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
call void @llvm.riscv.vsm.nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1>* %1, i32 %2) call void @llvm.riscv.vsm.nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1>* %1, iXLen %2)
ret void ret void
} }
declare <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i16( declare <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
i32); iXLen);
; Make sure we can use the vsetvli from the producing instruction. ; Make sure we can use the vsetvli from the producing instruction.
define void @test_vsetvli_i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1>* %2, i32 %3) nounwind { define void @test_vsetvli_i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1>* %2, iXLen %3) nounwind {
; CHECK-LABEL: test_vsetvli_i16: ; CHECK-LABEL: test_vsetvli_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
; CHECK-NEXT: vmseq.vv v8, v8, v9 ; CHECK-NEXT: vmseq.vv v8, v8, v9
; CHECK-NEXT: vsm.v v8, (a0) ; CHECK-NEXT: vsm.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i16( %a = call <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i16(
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
i32 %3) iXLen %3)
call void @llvm.riscv.vsm.nxv1i1(<vscale x 1 x i1> %a, <vscale x 1 x i1>* %2, i32 %3) call void @llvm.riscv.vsm.nxv1i1(<vscale x 1 x i1> %a, <vscale x 1 x i1>* %2, iXLen %3)
ret void ret void
} }
declare <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i32( declare <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
i32); iXLen);
define void @test_vsetvli_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1>* %2, i32 %3) nounwind { define void @test_vsetvli_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1>* %2, iXLen %3) nounwind {
; CHECK-LABEL: test_vsetvli_i32: ; CHECK-LABEL: test_vsetvli_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
; CHECK-NEXT: vmseq.vv v8, v8, v9 ; CHECK-NEXT: vmseq.vv v8, v8, v9
; CHECK-NEXT: vsm.v v8, (a0) ; CHECK-NEXT: vsm.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i32( %a = call <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i32(
<vscale x 1 x i32> %0, <vscale x 1 x i32> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
i32 %3) iXLen %3)
call void @llvm.riscv.vsm.nxv1i1(<vscale x 1 x i1> %a, <vscale x 1 x i1>* %2, i32 %3) call void @llvm.riscv.vsm.nxv1i1(<vscale x 1 x i1> %a, <vscale x 1 x i1>* %2, iXLen %3)
ret void ret void
} }
llvm/test/CodeGen/RISCV/rvv/vmxor.ll