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Differential D117404

[RISCV] Add patterns for vector widening integer multiply-add instructions
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Authored by eopXD on Jan 15 2022, 12:12 PM.

Details

Reviewers
craig.topper
jacquesguan
arcbbb
HanKuanChen
khchen
Commits
rG5a457782a26e: [RISCV] Add patterns for vector widening integer multiply-add instructions

Diff Detail

Unit TestsFailed

TimeTest
690 msx64 debian > SanitizerCommon-asan-x86_64-Linux.Linux::decorate_proc_maps.cpp
900 msx64 debian > SanitizerCommon-tsan-x86_64-Linux.Linux::decorate_proc_maps.cpp

Event Timeline

eopXD created this revision.Jan 15 2022, 12:12 PM
Herald added subscribers: VincentWu, luke957, achieveartificialintelligence and 27 others. · View Herald TranscriptJan 15 2022, 12:12 PM
eopXD requested review of this revision.Jan 15 2022, 12:12 PM
Herald added a project: Restricted Project. · View Herald TranscriptJan 15 2022, 12:12 PM
Herald added subscribers: llvm-commits, MaskRay. · View Herald Transcript
Harbormaster completed remote builds in B143615: Diff 400314.Jan 15 2022, 1:05 PM
eopXD added reviewers: arcbbb, HanKuanChen, khchen.Jan 15 2022, 9:24 PM
craig.topper added inline comments.Jan 16 2022, 12:54 AM
llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
555

Indent this at least one more space so that its more clear that its nested under the add.

558

Indent this one more space.

Herald added a subscriber: alextsao1999. · View Herald TranscriptJan 16 2022, 12:54 AM
eopXD updated this revision to Diff 400355.Jan 16 2022, 12:59 AM
eopXD marked 2 inline comments as done.

Address comments: update indention.

Harbormaster completed remote builds in B143653: Diff 400355.Jan 16 2022, 1:54 AM
craig.topper accepted this revision.Jan 16 2022, 11:45 AM

LGTM

This revision is now accepted and ready to land.Jan 16 2022, 11:45 AM
jacquesguan added inline comments.Jan 16 2022, 6:32 PM
llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
551

I think if move these class definations to upper section near to other class definations and leave pattern def here, maybe more clear.

eopXD updated this revision to Diff 400415.Jan 16 2022, 6:36 PM

Address comment: Move class definitions to upper section.

eopXD marked an inline comment as done.Jan 16 2022, 6:36 PM
This revision was landed with ongoing or failed builds.Jan 16 2022, 6:37 PM
Closed by commit rG5a457782a26e: [RISCV] Add patterns for vector widening integer multiply-add instructions (authored by eopXD). · Explain Why
This revision was automatically updated to reflect the committed changes.
eopXD added a commit: rG5a457782a26e: [RISCV] Add patterns for vector widening integer multiply-add instructions.
Harbormaster completed remote builds in B143706: Diff 400415.Jan 16 2022, 7:16 PM

Revision Contents

PathSize
llvm/
lib/
Target/
RISCV/
34 lines
test/
CodeGen/
RISCV/
rvv/
457 lines

Diff 400314

llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td

Show First 20 Lines • Show All 541 Lines • ▼ Show 20 Linesforeach vti = AllIntegerVectors in {
def : Pat<(vti.Vector (sub vti.RegClass:$rs2, def : Pat<(vti.Vector (sub vti.RegClass:$rs2,
(mul_oneuse (SplatPat XLenVT:$rs1), (mul_oneuse (SplatPat XLenVT:$rs1),
vti.RegClass:$rd))), vti.RegClass:$rd))),
(!cast<Instruction>("PseudoVNMSUB_VX_" # suffix) (!cast<Instruction>("PseudoVNMSUB_VX_" # suffix)
vti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, vti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2,
vti.AVL, vti.Log2SEW, TAIL_AGNOSTIC)>; vti.AVL, vti.Log2SEW, TAIL_AGNOSTIC)>;
} }
// 12.14 Vector Widening Integer Multiply-Add Instructions
multiclass VPatWidenMulAddSDNode_VV<PatFrags extop1, PatFrags extop2, string instruction_name> {
jacquesguanUnsubmitted
Done
ReplyInline Actions

I think if move these class definations to upper section near to other class definations and leave pattern def here, maybe more clear.

jacquesguan: I think if move these class definations to upper section near to other class definations and…
foreach vti = AllWidenableIntVectors in {
def : Pat<
(add (vti.Wti.Vector vti.Wti.RegClass:$rd),
(mul_oneuse (vti.Wti.Vector (extop1 (vti.Vti.Vector vti.Vti.RegClass:$rs1))),
craig.topperUnsubmitted
Done
ReplyInline Actions

Indent this at least one more space so that its more clear that its nested under the add.

craig.topper: Indent this at least one more space so that its more clear that its nested under the `add`.
(vti.Wti.Vector (extop2 (vti.Vti.Vector vti.Vti.RegClass:$rs2))))),
(!cast<Instruction>(instruction_name#"_VV_"#vti.Vti.LMul.MX)
vti.Wti.RegClass:$rd, vti.Vti.RegClass:$rs1, vti.Vti.RegClass:$rs2,
craig.topperUnsubmitted
Done
ReplyInline Actions

Indent this one more space.

craig.topper: Indent this one more space.
vti.Vti.AVL, vti.Vti.Log2SEW, TAIL_AGNOSTIC
)>;
}
}
multiclass VPatWidenMulAddSDNode_VX<PatFrags extop1, PatFrags extop2, string instruction_name> {
foreach vti = AllWidenableIntVectors in {
def : Pat<
(add (vti.Wti.Vector vti.Wti.RegClass:$rd),
(mul_oneuse (vti.Wti.Vector (extop1 (vti.Vti.Vector (SplatPat GPR:$rs1)))),
(vti.Wti.Vector (extop2 (vti.Vti.Vector vti.Vti.RegClass:$rs2))))),
(!cast<Instruction>(instruction_name#"_VX_"#vti.Vti.LMul.MX)
vti.Wti.RegClass:$rd, GPR:$rs1, vti.Vti.RegClass:$rs2,
vti.Vti.AVL, vti.Vti.Log2SEW, TAIL_AGNOSTIC
)>;
}
}
defm : VPatWidenMulAddSDNode_VV<sext_oneuse, sext_oneuse, "PseudoVWMACC">;
defm : VPatWidenMulAddSDNode_VX<sext_oneuse, sext_oneuse, "PseudoVWMACC">;
defm : VPatWidenMulAddSDNode_VV<zext_oneuse, zext_oneuse, "PseudoVWMACCU">;
defm : VPatWidenMulAddSDNode_VX<zext_oneuse, zext_oneuse, "PseudoVWMACCU">;
defm : VPatWidenMulAddSDNode_VV<sext_oneuse, zext_oneuse, "PseudoVWMACCSU">;
defm : VPatWidenMulAddSDNode_VX<sext_oneuse, zext_oneuse, "PseudoVWMACCSU">;
defm : VPatWidenMulAddSDNode_VX<zext_oneuse, sext_oneuse, "PseudoVWMACCUS">;
// 12.15. Vector Integer Merge Instructions // 12.15. Vector Integer Merge Instructions
foreach vti = AllIntegerVectors in { foreach vti = AllIntegerVectors in {
def : Pat<(vti.Vector (vselect (vti.Mask V0), vti.RegClass:$rs1, def : Pat<(vti.Vector (vselect (vti.Mask V0), vti.RegClass:$rs1,
vti.RegClass:$rs2)), vti.RegClass:$rs2)),
(!cast<Instruction>("PseudoVMERGE_VVM_"#vti.LMul.MX) (!cast<Instruction>("PseudoVMERGE_VVM_"#vti.LMul.MX)
vti.RegClass:$rs2, vti.RegClass:$rs1, (vti.Mask V0), vti.RegClass:$rs2, vti.RegClass:$rs1, (vti.Mask V0),
vti.AVL, vti.Log2SEW)>; vti.AVL, vti.Log2SEW)>;
▲ Show 20 Lines • Show All 280 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vwmacc-sdnode.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -target-abi=ilp32 \
; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK
; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -target-abi=lp64 \
; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK
define <vscale x 1 x i64> @vwmacc_vv_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb, <vscale x 1 x i64> %vc) {
; CHECK-LABEL: vwmacc_vv_nxv1i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
; CHECK-NEXT: vwmacc.vv v10, v8, v9
; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
%vd = sext <vscale x 1 x i32> %va to <vscale x 1 x i64>
%ve = sext <vscale x 1 x i32> %vb to <vscale x 1 x i64>
%x = mul <vscale x 1 x i64> %vd, %ve
%y = add <vscale x 1 x i64> %x, %vc
ret <vscale x 1 x i64> %y
}
define <vscale x 1 x i64> @vwmacc_vx_nxv1i32(<vscale x 1 x i32> %va, i32 %b, <vscale x 1 x i64> %vc) {
; CHECK-LABEL: vwmacc_vx_nxv1i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, mu
; CHECK-NEXT: vwmacc.vx v9, a0, v8
; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i32> undef, i32 %b, i32 0
%splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
%vd = sext <vscale x 1 x i32> %va to <vscale x 1 x i64>
%ve = sext <vscale x 1 x i32> %splat to <vscale x 1 x i64>
%x = mul <vscale x 1 x i64> %vd, %ve
%y = add <vscale x 1 x i64> %x, %vc
ret <vscale x 1 x i64> %y
}
define <vscale x 1 x i64> @vwmaccu_vv_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb, <vscale x 1 x i64> %vc) {
; CHECK-LABEL: vwmaccu_vv_nxv1i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
; CHECK-NEXT: vwmaccu.vv v10, v8, v9
; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
%vd = zext <vscale x 1 x i32> %va to <vscale x 1 x i64>
%ve = zext <vscale x 1 x i32> %vb to <vscale x 1 x i64>
%x = mul <vscale x 1 x i64> %vd, %ve
%y = add <vscale x 1 x i64> %x, %vc
ret <vscale x 1 x i64> %y
}
define <vscale x 1 x i64> @vwmaccu_vx_nxv1i32(<vscale x 1 x i32> %va, i32 %b, <vscale x 1 x i64> %vc) {
; CHECK-LABEL: vwmaccu_vx_nxv1i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, mu
; CHECK-NEXT: vwmaccu.vx v9, a0, v8
; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i32> undef, i32 %b, i32 0
%splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
%vd = zext <vscale x 1 x i32> %va to <vscale x 1 x i64>
%ve = zext <vscale x 1 x i32> %splat to <vscale x 1 x i64>
%x = mul <vscale x 1 x i64> %vd, %ve
%y = add <vscale x 1 x i64> %x, %vc
ret <vscale x 1 x i64> %y
}
define <vscale x 1 x i64> @vwmaccsu_vv_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb, <vscale x 1 x i64> %vc) {
; CHECK-LABEL: vwmaccsu_vv_nxv1i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
; CHECK-NEXT: vwmaccsu.vv v10, v9, v8
; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
%vd = zext <vscale x 1 x i32> %va to <vscale x 1 x i64>
%ve = sext <vscale x 1 x i32> %vb to <vscale x 1 x i64>
%x = mul <vscale x 1 x i64> %vd, %ve
%y = add <vscale x 1 x i64> %x, %vc
ret <vscale x 1 x i64> %y
}
define <vscale x 1 x i64> @vwmaccsu_vx_nxv1i32(<vscale x 1 x i32> %va, i32 %b, <vscale x 1 x i64> %vc) {
; CHECK-LABEL: vwmaccsu_vx_nxv1i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, mu
; CHECK-NEXT: vwmaccsu.vx v9, a0, v8
; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i32> undef, i32 %b, i32 0
%splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
%vd = zext <vscale x 1 x i32> %va to <vscale x 1 x i64>
%ve = sext <vscale x 1 x i32> %splat to <vscale x 1 x i64>
%x = mul <vscale x 1 x i64> %vd, %ve
%y = add <vscale x 1 x i64> %x, %vc
ret <vscale x 1 x i64> %y
}
define <vscale x 1 x i64> @vwmaccus_vx_nxv1i32(<vscale x 1 x i32> %va, i32 %b, <vscale x 1 x i64> %vc) {
; CHECK-LABEL: vwmaccus_vx_nxv1i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, mu
; CHECK-NEXT: vwmaccus.vx v9, a0, v8
; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i32> undef, i32 %b, i32 0
%splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
%vd = sext <vscale x 1 x i32> %va to <vscale x 1 x i64>
%ve = zext <vscale x 1 x i32> %splat to <vscale x 1 x i64>
%x = mul <vscale x 1 x i64> %vd, %ve
%y = add <vscale x 1 x i64> %x, %vc
ret <vscale x 1 x i64> %y
}
define <vscale x 2 x i64> @vwmacc_vv_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb, <vscale x 2 x i64> %vc) {
; CHECK-LABEL: vwmacc_vv_nxv2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
; CHECK-NEXT: vwmacc.vv v10, v8, v9
; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
%vd = sext <vscale x 2 x i32> %va to <vscale x 2 x i64>
%ve = sext <vscale x 2 x i32> %vb to <vscale x 2 x i64>
%x = mul <vscale x 2 x i64> %vd, %ve
%y = add <vscale x 2 x i64> %x, %vc
ret <vscale x 2 x i64> %y
}
define <vscale x 2 x i64> @vwmacc_vx_nxv2i32(<vscale x 2 x i32> %va, i32 %b, <vscale x 2 x i64> %vc) {
; CHECK-LABEL: vwmacc_vx_nxv2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu
; CHECK-NEXT: vwmacc.vx v10, a0, v8
; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i32> undef, i32 %b, i32 0
%splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
%vd = sext <vscale x 2 x i32> %va to <vscale x 2 x i64>
%ve = sext <vscale x 2 x i32> %splat to <vscale x 2 x i64>
%x = mul <vscale x 2 x i64> %vd, %ve
%y = add <vscale x 2 x i64> %x, %vc
ret <vscale x 2 x i64> %y
}
define <vscale x 2 x i64> @vwmaccu_vv_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb, <vscale x 2 x i64> %vc) {
; CHECK-LABEL: vwmaccu_vv_nxv2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
; CHECK-NEXT: vwmaccu.vv v10, v8, v9
; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
%vd = zext <vscale x 2 x i32> %va to <vscale x 2 x i64>
%ve = zext <vscale x 2 x i32> %vb to <vscale x 2 x i64>
%x = mul <vscale x 2 x i64> %vd, %ve
%y = add <vscale x 2 x i64> %x, %vc
ret <vscale x 2 x i64> %y
}
define <vscale x 2 x i64> @vwmaccu_vx_nxv2i32(<vscale x 2 x i32> %va, i32 %b, <vscale x 2 x i64> %vc) {
; CHECK-LABEL: vwmaccu_vx_nxv2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu
; CHECK-NEXT: vwmaccu.vx v10, a0, v8
; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i32> undef, i32 %b, i32 0
%splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
%vd = zext <vscale x 2 x i32> %va to <vscale x 2 x i64>
%ve = zext <vscale x 2 x i32> %splat to <vscale x 2 x i64>
%x = mul <vscale x 2 x i64> %vd, %ve
%y = add <vscale x 2 x i64> %x, %vc
ret <vscale x 2 x i64> %y
}
define <vscale x 2 x i64> @vwmaccsu_vv_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb, <vscale x 2 x i64> %vc) {
; CHECK-LABEL: vwmaccsu_vv_nxv2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
; CHECK-NEXT: vwmaccsu.vv v10, v9, v8
; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
%vd = zext <vscale x 2 x i32> %va to <vscale x 2 x i64>
%ve = sext <vscale x 2 x i32> %vb to <vscale x 2 x i64>
%x = mul <vscale x 2 x i64> %vd, %ve
%y = add <vscale x 2 x i64> %x, %vc
ret <vscale x 2 x i64> %y
}
define <vscale x 2 x i64> @vwmaccsu_vx_nxv2i32(<vscale x 2 x i32> %va, i32 %b, <vscale x 2 x i64> %vc) {
; CHECK-LABEL: vwmaccsu_vx_nxv2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu
; CHECK-NEXT: vwmaccsu.vx v10, a0, v8
; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i32> undef, i32 %b, i32 0
%splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
%vd = zext <vscale x 2 x i32> %va to <vscale x 2 x i64>
%ve = sext <vscale x 2 x i32> %splat to <vscale x 2 x i64>
%x = mul <vscale x 2 x i64> %vd, %ve
%y = add <vscale x 2 x i64> %x, %vc
ret <vscale x 2 x i64> %y
}
define <vscale x 2 x i64> @vwmaccus_vx_nxv2i32(<vscale x 2 x i32> %va, i32 %b, <vscale x 2 x i64> %vc) {
; CHECK-LABEL: vwmaccus_vx_nxv2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu
; CHECK-NEXT: vwmaccus.vx v10, a0, v8
; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i32> undef, i32 %b, i32 0
%splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
%vd = sext <vscale x 2 x i32> %va to <vscale x 2 x i64>
%ve = zext <vscale x 2 x i32> %splat to <vscale x 2 x i64>
%x = mul <vscale x 2 x i64> %vd, %ve
%y = add <vscale x 2 x i64> %x, %vc
ret <vscale x 2 x i64> %y
}
define <vscale x 4 x i64> @vwmacc_vv_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %vb, <vscale x 4 x i64> %vc) {
; CHECK-LABEL: vwmacc_vv_nxv4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
; CHECK-NEXT: vwmacc.vv v12, v8, v10
; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
%vd = sext <vscale x 4 x i32> %va to <vscale x 4 x i64>
%ve = sext <vscale x 4 x i32> %vb to <vscale x 4 x i64>
%x = mul <vscale x 4 x i64> %vd, %ve
%y = add <vscale x 4 x i64> %x, %vc
ret <vscale x 4 x i64> %y
}
define <vscale x 4 x i64> @vwmacc_vx_nxv4i32(<vscale x 4 x i32> %va, i32 %b, <vscale x 4 x i64> %vc) {
; CHECK-LABEL: vwmacc_vx_nxv4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu
; CHECK-NEXT: vwmacc.vx v12, a0, v8
; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i32> undef, i32 %b, i32 0
%splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
%vd = sext <vscale x 4 x i32> %va to <vscale x 4 x i64>
%ve = sext <vscale x 4 x i32> %splat to <vscale x 4 x i64>
%x = mul <vscale x 4 x i64> %vd, %ve
%y = add <vscale x 4 x i64> %x, %vc
ret <vscale x 4 x i64> %y
}
define <vscale x 4 x i64> @vwmaccu_vv_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %vb, <vscale x 4 x i64> %vc) {
; CHECK-LABEL: vwmaccu_vv_nxv4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
; CHECK-NEXT: vwmaccu.vv v12, v8, v10
; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
%vd = zext <vscale x 4 x i32> %va to <vscale x 4 x i64>
%ve = zext <vscale x 4 x i32> %vb to <vscale x 4 x i64>
%x = mul <vscale x 4 x i64> %vd, %ve
%y = add <vscale x 4 x i64> %x, %vc
ret <vscale x 4 x i64> %y
}
define <vscale x 4 x i64> @vwmaccu_vx_nxv4i32(<vscale x 4 x i32> %va, i32 %b, <vscale x 4 x i64> %vc) {
; CHECK-LABEL: vwmaccu_vx_nxv4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu
; CHECK-NEXT: vwmaccu.vx v12, a0, v8
; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i32> undef, i32 %b, i32 0
%splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
%vd = zext <vscale x 4 x i32> %va to <vscale x 4 x i64>
%ve = zext <vscale x 4 x i32> %splat to <vscale x 4 x i64>
%x = mul <vscale x 4 x i64> %vd, %ve
%y = add <vscale x 4 x i64> %x, %vc
ret <vscale x 4 x i64> %y
}
define <vscale x 4 x i64> @vwmaccsu_vv_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %vb, <vscale x 4 x i64> %vc) {
; CHECK-LABEL: vwmaccsu_vv_nxv4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
; CHECK-NEXT: vwmaccsu.vv v12, v10, v8
; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
%vd = zext <vscale x 4 x i32> %va to <vscale x 4 x i64>
%ve = sext <vscale x 4 x i32> %vb to <vscale x 4 x i64>
%x = mul <vscale x 4 x i64> %vd, %ve
%y = add <vscale x 4 x i64> %x, %vc
ret <vscale x 4 x i64> %y
}
define <vscale x 4 x i64> @vwmaccsu_vx_nxv4i32(<vscale x 4 x i32> %va, i32 %b, <vscale x 4 x i64> %vc) {
; CHECK-LABEL: vwmaccsu_vx_nxv4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu
; CHECK-NEXT: vwmaccsu.vx v12, a0, v8
; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i32> undef, i32 %b, i32 0
%splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
%vd = zext <vscale x 4 x i32> %va to <vscale x 4 x i64>
%ve = sext <vscale x 4 x i32> %splat to <vscale x 4 x i64>
%x = mul <vscale x 4 x i64> %vd, %ve
%y = add <vscale x 4 x i64> %x, %vc
ret <vscale x 4 x i64> %y
}
define <vscale x 4 x i64> @vwmaccus_vx_nxv4i32(<vscale x 4 x i32> %va, i32 %b, <vscale x 4 x i64> %vc) {
; CHECK-LABEL: vwmaccus_vx_nxv4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu
; CHECK-NEXT: vwmaccus.vx v12, a0, v8
; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i32> undef, i32 %b, i32 0
%splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
%vd = sext <vscale x 4 x i32> %va to <vscale x 4 x i64>
%ve = zext <vscale x 4 x i32> %splat to <vscale x 4 x i64>
%x = mul <vscale x 4 x i64> %vd, %ve
%y = add <vscale x 4 x i64> %x, %vc
ret <vscale x 4 x i64> %y
}
define <vscale x 8 x i64> @vwmacc_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb, <vscale x 8 x i64> %vc) {
; CHECK-LABEL: vwmacc_vv_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
; CHECK-NEXT: vwmacc.vv v16, v8, v12
; CHECK-NEXT: vmv8r.v v8, v16
; CHECK-NEXT: ret
%vd = sext <vscale x 8 x i32> %va to <vscale x 8 x i64>
%ve = sext <vscale x 8 x i32> %vb to <vscale x 8 x i64>
%x = mul <vscale x 8 x i64> %vd, %ve
%y = add <vscale x 8 x i64> %x, %vc
ret <vscale x 8 x i64> %y
}
define <vscale x 8 x i64> @vwmacc_vx_nxv8i32(<vscale x 8 x i32> %va, i32 %b, <vscale x 8 x i64> %vc) {
; CHECK-LABEL: vwmacc_vx_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
; CHECK-NEXT: vwmacc.vx v16, a0, v8
; CHECK-NEXT: vmv8r.v v8, v16
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> undef, i32 %b, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
%vd = sext <vscale x 8 x i32> %va to <vscale x 8 x i64>
%ve = sext <vscale x 8 x i32> %splat to <vscale x 8 x i64>
%x = mul <vscale x 8 x i64> %vd, %ve
%y = add <vscale x 8 x i64> %x, %vc
ret <vscale x 8 x i64> %y
}
define <vscale x 8 x i64> @vwmaccu_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb, <vscale x 8 x i64> %vc) {
; CHECK-LABEL: vwmaccu_vv_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
; CHECK-NEXT: vwmaccu.vv v16, v8, v12
; CHECK-NEXT: vmv8r.v v8, v16
; CHECK-NEXT: ret
%vd = zext <vscale x 8 x i32> %va to <vscale x 8 x i64>
%ve = zext <vscale x 8 x i32> %vb to <vscale x 8 x i64>
%x = mul <vscale x 8 x i64> %vd, %ve
%y = add <vscale x 8 x i64> %x, %vc
ret <vscale x 8 x i64> %y
}
define <vscale x 8 x i64> @vwmaccu_vx_nxv8i32(<vscale x 8 x i32> %va, i32 %b, <vscale x 8 x i64> %vc) {
; CHECK-LABEL: vwmaccu_vx_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
; CHECK-NEXT: vwmaccu.vx v16, a0, v8
; CHECK-NEXT: vmv8r.v v8, v16
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> undef, i32 %b, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
%vd = zext <vscale x 8 x i32> %va to <vscale x 8 x i64>
%ve = zext <vscale x 8 x i32> %splat to <vscale x 8 x i64>
%x = mul <vscale x 8 x i64> %vd, %ve
%y = add <vscale x 8 x i64> %x, %vc
ret <vscale x 8 x i64> %y
}
define <vscale x 8 x i64> @vwmaccsu_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb, <vscale x 8 x i64> %vc) {
; CHECK-LABEL: vwmaccsu_vv_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
; CHECK-NEXT: vwmaccsu.vv v16, v12, v8
; CHECK-NEXT: vmv8r.v v8, v16
; CHECK-NEXT: ret
%vd = zext <vscale x 8 x i32> %va to <vscale x 8 x i64>
%ve = sext <vscale x 8 x i32> %vb to <vscale x 8 x i64>
%x = mul <vscale x 8 x i64> %vd, %ve
%y = add <vscale x 8 x i64> %x, %vc
ret <vscale x 8 x i64> %y
}
define <vscale x 8 x i64> @vwmaccsu_vx_nxv8i32(<vscale x 8 x i32> %va, i32 %b, <vscale x 8 x i64> %vc) {
; CHECK-LABEL: vwmaccsu_vx_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
; CHECK-NEXT: vwmaccsu.vx v16, a0, v8
; CHECK-NEXT: vmv8r.v v8, v16
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> undef, i32 %b, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
%vd = zext <vscale x 8 x i32> %va to <vscale x 8 x i64>
%ve = sext <vscale x 8 x i32> %splat to <vscale x 8 x i64>
%x = mul <vscale x 8 x i64> %vd, %ve
%y = add <vscale x 8 x i64> %x, %vc
ret <vscale x 8 x i64> %y
}
define <vscale x 8 x i64> @vwmaccus_vx_nxv8i32(<vscale x 8 x i32> %va, i32 %b, <vscale x 8 x i64> %vc) {
; CHECK-LABEL: vwmaccus_vx_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
; CHECK-NEXT: vwmaccus.vx v16, a0, v8
; CHECK-NEXT: vmv8r.v v8, v16
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> undef, i32 %b, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
%vd = sext <vscale x 8 x i32> %va to <vscale x 8 x i64>
%ve = zext <vscale x 8 x i32> %splat to <vscale x 8 x i64>
%x = mul <vscale x 8 x i64> %vd, %ve
%y = add <vscale x 8 x i64> %x, %vc
ret <vscale x 8 x i64> %y
}