This is an archive of the discontinued LLVM Phabricator instance.

Paths

Table of Contentst

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clang/test/OpenMP/
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test/
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OpenMP/
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amdgcn_target_codegen.cpp
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declare_target_codegen_globalization.cpp
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distribute_firstprivate_codegen.cpp
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distribute_lastprivate_codegen.cpp
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distribute_parallel_for_lastprivate_codegen.cpp
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distribute_parallel_for_num_threads_codegen.cpp
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distribute_parallel_for_private_codegen.cpp
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distribute_parallel_for_proc_bind_codegen.cpp
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distribute_parallel_for_simd_firstprivate_codegen.cpp
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distribute_parallel_for_simd_lastprivate_codegen.cpp
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distribute_parallel_for_simd_num_threads_codegen.cpp
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distribute_parallel_for_simd_private_codegen.cpp
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distribute_parallel_for_simd_proc_bind_codegen.cpp
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distribute_private_codegen.cpp
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distribute_simd_firstprivate_codegen.cpp
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distribute_simd_lastprivate_codegen.cpp
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distribute_simd_private_codegen.cpp
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distribute_simd_reduction_codegen.cpp
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for_lastprivate_codegen.cpp
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for_private_codegen.cpp
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nvptx_SPMD_codegen.cpp
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nvptx_data_sharing.cpp
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nvptx_distribute_parallel_generic_mode_codegen.cpp
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nvptx_force_full_runtime_SPMD_codegen.cpp
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nvptx_lambda_capturing.cpp
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nvptx_multi_target_parallel_codegen.cpp
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nvptx_nested_parallel_codegen.cpp
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nvptx_parallel_codegen.cpp
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nvptx_parallel_for_codegen.cpp
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nvptx_target_codegen.cpp
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nvptx_target_parallel_codegen.cpp
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nvptx_target_parallel_num_threads_codegen.cpp
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nvptx_target_parallel_reduction_codegen.cpp
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nvptx_target_parallel_reduction_codegen_tbaa_PR46146.cpp
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nvptx_target_printf_codegen.c
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nvptx_target_simd_codegen.cpp
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nvptx_target_teams_codegen.cpp
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nvptx_target_teams_distribute_codegen.cpp
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nvptx_target_teams_distribute_parallel_for_codegen.cpp
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nvptx_target_teams_distribute_parallel_for_generic_mode_codegen.cpp
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nvptx_target_teams_distribute_parallel_for_simd_codegen.cpp
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nvptx_target_teams_distribute_simd_codegen.cpp
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nvptx_teams_codegen.cpp
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openmp_win_codegen.cpp
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parallel_codegen.cpp
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parallel_for_simd_aligned_codegen.cpp
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parallel_private_codegen.cpp
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parallel_reduction_codegen.cpp
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parallel_sections_codegen.cpp
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sections_lastprivate_codegen.cpp
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sections_private_codegen.cpp
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sections_reduction_codegen.cpp
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single_private_codegen.cpp
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target_data_map_codegen_hold.cpp
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target_globals_codegen.cpp
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target_map_codegen_hold.cpp
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target_parallel_debug_codegen.cpp
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target_parallel_for_debug_codegen.cpp
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target_teams_distribute_parallel_for_proc_bind_codegen.cpp
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target_teams_distribute_parallel_for_reduction_codegen.cpp
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target_teams_distribute_parallel_for_simd_codegen.cpp
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target_teams_distribute_parallel_for_simd_collapse_codegen.cpp
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target_teams_distribute_parallel_for_simd_dist_schedule_codegen.cpp
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target_teams_distribute_parallel_for_simd_firstprivate_codegen.cpp
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target_teams_distribute_parallel_for_simd_if_codegen.cpp
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target_teams_distribute_parallel_for_simd_proc_bind_codegen.cpp
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target_teams_distribute_parallel_for_simd_reduction_codegen.cpp
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target_teams_distribute_reduction_codegen.cpp
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taskgroup_codegen.cpp
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teams_distribute_collapse_codegen.cpp
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teams_distribute_lastprivate_codegen.cpp
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teams_distribute_parallel_for_collapse_codegen.cpp
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teams_distribute_parallel_for_copyin_codegen.cpp
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teams_distribute_parallel_for_lastprivate_codegen.cpp
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teams_distribute_parallel_for_proc_bind_codegen.cpp
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teams_distribute_parallel_for_reduction_codegen.cpp
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teams_distribute_parallel_for_simd_collapse_codegen.cpp
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teams_distribute_parallel_for_simd_dist_schedule_codegen.cpp
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teams_distribute_parallel_for_simd_firstprivate_codegen.cpp
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teams_distribute_parallel_for_simd_if_codegen.cpp
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teams_distribute_parallel_for_simd_lastprivate_codegen.cpp
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teams_distribute_parallel_for_simd_num_threads_codegen.cpp
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teams_distribute_parallel_for_simd_proc_bind_codegen.cpp
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teams_distribute_parallel_for_simd_reduction_codegen.cpp
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teams_distribute_reduction_codegen.cpp
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teams_distribute_simd_collapse_codegen.cpp
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teams_distribute_simd_firstprivate_codegen.cpp
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teams_distribute_simd_lastprivate_codegen.cpp
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teams_distribute_simd_reduction_codegen.cpp
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teams_private_codegen.cpp
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threadprivate_codegen.cpp
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tile_codegen.cpp

Differential D116910

[OpenMP][3/3] Introduce the KernelEnvironment into Clang tests
ClosedPublic

Authored by jdoerfert on Jan 9 2022, 7:16 PM.

Download Raw Diff

Details

Reviewers

jhuber6
tianshilei1992
JonChesterfield

Summary

Since Clang uses the OpenMP-IR-Builder to create kernels, the
introduction of the KernelEnvironment in the middle-end will require all
GPU tests to be updated. This was done mostly via the script.
Only test changes are include and no other Clang changes are expected.

Diff Detail

Repository: rG LLVM Github Monorepo

Unit TestsFailed

	Time	Test
	130 ms	x64 debian > Clang.OpenMP::declare_target_codegen_globalization.cpp
	230 ms	x64 debian > Clang.OpenMP::distribute_parallel_for_simd_firstprivate_codegen.cpp
	190 ms	x64 debian > Clang.OpenMP::nvptx_data_sharing.cpp
	410 ms	x64 debian > Clang.OpenMP::nvptx_distribute_parallel_generic_mode_codegen.cpp
	980 ms	x64 debian > Clang.OpenMP::nvptx_lambda_capturing.cpp
		View Full Test Results (38 Failed)

Event Timeline

jdoerfert created this revision.Jan 9 2022, 7:16 PM

Herald added subscribers: asavonic, guansong, bollu and 2 others. · View Herald TranscriptJan 9 2022, 7:16 PM

jdoerfert requested review of this revision.Jan 9 2022, 7:16 PM

Herald added a project: Restricted Project. · View Herald TranscriptJan 9 2022, 7:16 PM

Herald added subscribers: cfe-commits, sstefan1. · View Herald Transcript

jdoerfert added a parent revision: D116909: [OpenMP][2/3] Introduce the KernelEnvironment into the middle-end.Jan 9 2022, 7:16 PM

Harbormaster completed remote builds in B142345: Diff 398489.Jan 9 2022, 7:58 PM

LGTM if it passes all the tests.

This revision is now accepted and ready to land.Jan 21 2022, 3:52 PM

tianshilei1992 mentioned this in D142569: [OpenMP] Introduce kernel environment.Jan 25 2023, 3:54 PM

tianshilei1992 mentioned this in rG35cfadfbe2de: [OpenMP] Introduce kernel environment.Apr 22 2023, 5:47 PM

tianshilei1992 mentioned this in rGc5c8040390e7: [OpenMP] Introduce kernel environment.Jul 23 2023, 3:36 PM

tianshilei1992 mentioned this in rG10068cd65440: [OpenMP] Introduce kernel environment.Jul 26 2023, 10:35 AM

Subsumed by D142569

Herald added a project: Restricted Project. · View Herald TranscriptJul 26 2023, 1:41 PM

Herald added subscribers: jplehr, sunshaoce, mattd. · View Herald Transcript

Revision Contents

Path

Size

clang/

test/

OpenMP/

amdgcn_target_codegen.cpp

4 lines

declare_target_codegen_globalization.cpp

4 lines

distribute_firstprivate_codegen.cpp

1 line

distribute_lastprivate_codegen.cpp

1 line

distribute_parallel_for_lastprivate_codegen.cpp

1 line

distribute_parallel_for_num_threads_codegen.cpp

1 line

distribute_parallel_for_private_codegen.cpp

1 line

distribute_parallel_for_proc_bind_codegen.cpp

1 line

distribute_parallel_for_simd_firstprivate_codegen.cpp

16 lines

distribute_parallel_for_simd_lastprivate_codegen.cpp

592 lines

distribute_parallel_for_simd_num_threads_codegen.cpp

1984 lines

distribute_parallel_for_simd_private_codegen.cpp

568 lines

distribute_parallel_for_simd_proc_bind_codegen.cpp

204 lines

distribute_private_codegen.cpp

1 line

distribute_simd_firstprivate_codegen.cpp

384 lines

distribute_simd_lastprivate_codegen.cpp

352 lines

distribute_simd_private_codegen.cpp

408 lines

distribute_simd_reduction_codegen.cpp

208 lines

for_lastprivate_codegen.cpp

1 line

for_private_codegen.cpp

1 line

nvptx_SPMD_codegen.cpp

124 lines

nvptx_data_sharing.cpp

6 lines

nvptx_distribute_parallel_generic_mode_codegen.cpp

12 lines

nvptx_force_full_runtime_SPMD_codegen.cpp

126 lines

nvptx_lambda_capturing.cpp

96 lines

nvptx_multi_target_parallel_codegen.cpp

24 lines

nvptx_nested_parallel_codegen.cpp

18 lines

nvptx_parallel_codegen.cpp

48 lines

nvptx_parallel_for_codegen.cpp

8 lines

nvptx_target_codegen.cpp

170 lines

nvptx_target_parallel_codegen.cpp

48 lines

nvptx_target_parallel_num_threads_codegen.cpp

48 lines

nvptx_target_parallel_reduction_codegen.cpp

12 lines

nvptx_target_parallel_reduction_codegen_tbaa_PR46146.cpp

990 lines

nvptx_target_printf_codegen.c

24 lines

nvptx_target_simd_codegen.cpp

16 lines

nvptx_target_teams_codegen.cpp

72 lines

nvptx_target_teams_distribute_codegen.cpp

18 lines

nvptx_target_teams_distribute_parallel_for_codegen.cpp

96 lines

nvptx_target_teams_distribute_parallel_for_generic_mode_codegen.cpp

24 lines

nvptx_target_teams_distribute_parallel_for_simd_codegen.cpp

48 lines

nvptx_target_teams_distribute_simd_codegen.cpp

16 lines

nvptx_teams_codegen.cpp

40 lines

openmp_win_codegen.cpp

1 line

parallel_codegen.cpp

527 lines

parallel_for_simd_aligned_codegen.cpp

56 lines

parallel_private_codegen.cpp

1 line

parallel_reduction_codegen.cpp

5 lines

parallel_sections_codegen.cpp

1 line

sections_lastprivate_codegen.cpp

1 line

sections_private_codegen.cpp

1 line

sections_reduction_codegen.cpp

1 line

single_private_codegen.cpp

1 line

target_data_map_codegen_hold.cpp

36 lines

target_globals_codegen.cpp

71 lines

target_map_codegen_hold.cpp

171 lines

target_parallel_debug_codegen.cpp

20 lines

target_parallel_for_debug_codegen.cpp

28 lines

target_teams_distribute_parallel_for_proc_bind_codegen.cpp

1 line

target_teams_distribute_parallel_for_reduction_codegen.cpp

1 line

target_teams_distribute_parallel_for_simd_codegen.cpp

120 lines

target_teams_distribute_parallel_for_simd_collapse_codegen.cpp

32 lines

target_teams_distribute_parallel_for_simd_dist_schedule_codegen.cpp

72 lines

target_teams_distribute_parallel_for_simd_firstprivate_codegen.cpp

116 lines

target_teams_distribute_parallel_for_simd_if_codegen.cpp

160 lines

target_teams_distribute_parallel_for_simd_proc_bind_codegen.cpp

204 lines

target_teams_distribute_parallel_for_simd_reduction_codegen.cpp

388 lines

target_teams_distribute_reduction_codegen.cpp

1 line

taskgroup_codegen.cpp

84 lines

teams_distribute_collapse_codegen.cpp

1 line

teams_distribute_lastprivate_codegen.cpp

1 line

teams_distribute_parallel_for_collapse_codegen.cpp

1 line

teams_distribute_parallel_for_copyin_codegen.cpp

1 line

teams_distribute_parallel_for_lastprivate_codegen.cpp

1 line

teams_distribute_parallel_for_proc_bind_codegen.cpp

1 line

teams_distribute_parallel_for_reduction_codegen.cpp

1 line

teams_distribute_parallel_for_simd_collapse_codegen.cpp

552 lines

teams_distribute_parallel_for_simd_dist_schedule_codegen.cpp

24 lines

teams_distribute_parallel_for_simd_firstprivate_codegen.cpp

64 lines

teams_distribute_parallel_for_simd_if_codegen.cpp

112 lines

teams_distribute_parallel_for_simd_lastprivate_codegen.cpp

592 lines

teams_distribute_parallel_for_simd_num_threads_codegen.cpp

24 lines

teams_distribute_parallel_for_simd_proc_bind_codegen.cpp

204 lines

teams_distribute_parallel_for_simd_reduction_codegen.cpp

388 lines

teams_distribute_reduction_codegen.cpp

1 line

teams_distribute_simd_collapse_codegen.cpp

336 lines

teams_distribute_simd_firstprivate_codegen.cpp

44 lines

teams_distribute_simd_lastprivate_codegen.cpp

352 lines

teams_distribute_simd_reduction_codegen.cpp

208 lines

teams_private_codegen.cpp

1 line

threadprivate_codegen.cpp

10 lines

tile_codegen.cpp

68 lines

Diff 398489

clang/test/OpenMP/amdgcn_target_codegen.cpp

	// REQUIRES: amdgpu-registered-target			// REQUIRES: amdgpu-registered-target

	// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple x86_64-unknown-unknown -fopenmp-targets=amdgcn-amd-amdhsa -emit-llvm-bc %s -o %t-ppc-host.bc			// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple x86_64-unknown-unknown -fopenmp-targets=amdgcn-amd-amdhsa -emit-llvm-bc %s -o %t-ppc-host.bc
	// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple amdgcn-amd-amdhsa -fopenmp-targets=amdgcn-amd-amdhsa -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - \| FileCheck %s			// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple amdgcn-amd-amdhsa -fopenmp-targets=amdgcn-amd-amdhsa -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - \| FileCheck %s
	// expected-no-diagnostics			// expected-no-diagnostics
	#ifndef HEADER			#ifndef HEADER
	#define HEADER			#define HEADER

	#define N 1000			#define N 1000

	int test_amdgcn_target_tid_threads() {			int test_amdgcn_target_tid_threads() {
	// CHECK-LABEL: define weak amdgpu_kernel void @{{.*}}test_amdgcn_target_tid_threads			// CHECK-LABEL: define weak amdgpu_kernel void @{{.*}}test_amdgcn_target_tid_threads

	int arr[N];			int arr[N];

	// CHECK: call i32 @__kmpc_target_init(%struct.ident_t* addrspacecast (%struct.ident_t addrspace(1)* @1 to %struct.ident_t*), i8 1, i1 true, i1 true)			// CHECK: call i32 @__kmpc_target_init(
	#pragma omp target			#pragma omp target
	for (int i = 0; i < N; i++) {			for (int i = 0; i < N; i++) {
	arr[i] = 1;			arr[i] = 1;
	}			}

	return arr[0];			return arr[0];
	}			}

	int test_amdgcn_target_tid_threads_simd() {			int test_amdgcn_target_tid_threads_simd() {
	// CHECK-LABEL: define weak amdgpu_kernel void @{{.*}}test_amdgcn_target_tid_threads_simd			// CHECK-LABEL: define weak amdgpu_kernel void @{{.*}}test_amdgcn_target_tid_threads_simd

	int arr[N];			int arr[N];

	// CHECK: call i32 @__kmpc_target_init(%struct.ident_t* addrspacecast (%struct.ident_t addrspace(1)* @1 to %struct.ident_t*), i8 2, i1 false, i1 false)			// CHECK: call i32 @__kmpc_target_init(
	#pragma omp target simd			#pragma omp target simd
	for (int i = 0; i < N; i++) {			for (int i = 0; i < N; i++) {
	arr[i] = 1;			arr[i] = 1;
	}			}
	return arr[0];			return arr[0];
	}			}

	#endif			#endif

clang/test/OpenMP/declare_target_codegen_globalization.cpp

	Show All 25 Lines

	// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6maini1v_l16			// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6maini1v_l16
	// CHECK1-SAME: (i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR0:[0-9]+]] {			// CHECK1-SAME: (i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR0:[0-9]+]] {
	// CHECK1-NEXT: entry:			// CHECK1-NEXT: entry:
	// CHECK1-NEXT: [[A_ADDR:%.]] = alloca i32, align 8			// CHECK1-NEXT: [[A_ADDR:%.]] = alloca i32, align 8
	// CHECK1-NEXT: [[CAPTURED_VARS_ADDRS:%.]] = alloca [1 x i8], align 8			// CHECK1-NEXT: [[CAPTURED_VARS_ADDRS:%.]] = alloca [1 x i8], align 8
	// CHECK1-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8			// CHECK1-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
	// CHECK1-NEXT: [[TMP0:%.]] = load i32, i32** [[A_ADDR]], align 8			// CHECK1-NEXT: [[TMP0:%.]] = load i32, i32** [[A_ADDR]], align 8
	// CHECK1-NEXT: [[TMP1:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1:[0-9]+]], i8 2, i1 false, i1 true)			// CHECK1-NEXT: [[TMP1:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6maini1v_l16_kernel_info, i1 true)
	// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1			// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
	// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]			// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
	// CHECK1: user_code.entry:			// CHECK1: user_code.entry:
	// CHECK1-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB2:[0-9]+]])			// CHECK1-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB2:[0-9]+]])
	// CHECK1-NEXT: [[TMP3:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 0			// CHECK1-NEXT: [[TMP3:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
	// CHECK1-NEXT: [[TMP4:%.]] = bitcast i32 [[TMP0]] to i8*			// CHECK1-NEXT: [[TMP4:%.]] = bitcast i32 [[TMP0]] to i8*
	// CHECK1-NEXT: store i8* [[TMP4]], i8** [[TMP3]], align 8			// CHECK1-NEXT: store i8* [[TMP4]], i8** [[TMP3]], align 8
	// CHECK1-NEXT: [[TMP5:%.]] = bitcast [1 x i8]* [[CAPTURED_VARS_ADDRS]] to i8**			// CHECK1-NEXT: [[TMP5:%.]] = bitcast [1 x i8]* [[CAPTURED_VARS_ADDRS]] to i8**
	// CHECK1-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32, i32, i32) @__omp_outlined__ to i8), i8 null, i8** [[TMP5]], i64 1)			// CHECK1-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32, i32, i32) @__omp_outlined__ to i8), i8 null, i8** [[TMP5]], i64 1)
	// CHECK1-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 true)			// CHECK1-NEXT: call void @__kmpc_target_deinit(i1 true)
	// CHECK1-NEXT: ret void			// CHECK1-NEXT: ret void
	// CHECK1: worker.exit:			// CHECK1: worker.exit:
	// CHECK1-NEXT: ret void			// CHECK1-NEXT: ret void
	//			//
	//			//
	// CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__			// CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__
	// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i32 nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR1:[0-9]+]] {			// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i32 nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR1:[0-9]+]] {
	// CHECK1-NEXT: entry:			// CHECK1-NEXT: entry:
	Show All 34 Lines

clang/test/OpenMP/distribute_firstprivate_codegen.cpp

	Show First 20 Lines • Show All 3,455 Lines • ▼ Show 20 Lines
	//			//
	//			//
	// CHECK12-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg			// CHECK12-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
	// CHECK12-SAME: () #[[ATTR6:[0-9]+]] {			// CHECK12-SAME: () #[[ATTR6:[0-9]+]] {
	// CHECK12-NEXT: entry:			// CHECK12-NEXT: entry:
	// CHECK12-NEXT: call void @__tgt_register_requires(i64 1)			// CHECK12-NEXT: call void @__tgt_register_requires(i64 1)
	// CHECK12-NEXT: ret void			// CHECK12-NEXT: ret void
	//			//
	//
	No newline at end of file

clang/test/OpenMP/distribute_lastprivate_codegen.cpp

This file is larger than 256 KB, so syntax highlighting is disabled by default.

	Show First 20 Lines • Show All 3,581 Lines • ▼ Show 20 Lines
	//			//
	//			//
	// CHECK12-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg			// CHECK12-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
	// CHECK12-SAME: () #[[ATTR6:[0-9]+]] {			// CHECK12-SAME: () #[[ATTR6:[0-9]+]] {
	// CHECK12-NEXT: entry:			// CHECK12-NEXT: entry:
	// CHECK12-NEXT: call void @__tgt_register_requires(i64 1)			// CHECK12-NEXT: call void @__tgt_register_requires(i64 1)
	// CHECK12-NEXT: ret void			// CHECK12-NEXT: ret void
	//			//
	//
	No newline at end of file

clang/test/OpenMP/distribute_parallel_for_lastprivate_codegen.cpp

This file is larger than 256 KB, so syntax highlighting is disabled by default.

	Show First 20 Lines • Show All 5,265 Lines • ▼ Show 20 Lines
	//			//
	//			//
	// CHECK12-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg			// CHECK12-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
	// CHECK12-SAME: () #[[ATTR6:[0-9]+]] {			// CHECK12-SAME: () #[[ATTR6:[0-9]+]] {
	// CHECK12-NEXT: entry:			// CHECK12-NEXT: entry:
	// CHECK12-NEXT: call void @__tgt_register_requires(i64 1)			// CHECK12-NEXT: call void @__tgt_register_requires(i64 1)
	// CHECK12-NEXT: ret void			// CHECK12-NEXT: ret void
	//			//
	//
	No newline at end of file

clang/test/OpenMP/distribute_parallel_for_num_threads_codegen.cpp

This file is larger than 256 KB, so syntax highlighting is disabled by default.

	Show First 20 Lines • Show All 9,062 Lines • ▼ Show 20 Lines
	//			//
	//			//
	// CHECK14-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg			// CHECK14-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
	// CHECK14-SAME: () #[[ATTR9:[0-9]+]] {			// CHECK14-SAME: () #[[ATTR9:[0-9]+]] {
	// CHECK14-NEXT: entry:			// CHECK14-NEXT: entry:
	// CHECK14-NEXT: call void @__tgt_register_requires(i64 1)			// CHECK14-NEXT: call void @__tgt_register_requires(i64 1)
	// CHECK14-NEXT: ret void			// CHECK14-NEXT: ret void
	//			//
	//
	No newline at end of file

clang/test/OpenMP/distribute_parallel_for_private_codegen.cpp

	Show First 20 Lines • Show All 3,540 Lines • ▼ Show 20 Lines
	//			//
	//			//
	// CHECK12-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg			// CHECK12-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
	// CHECK12-SAME: () #[[ATTR6:[0-9]+]] {			// CHECK12-SAME: () #[[ATTR6:[0-9]+]] {
	// CHECK12-NEXT: entry:			// CHECK12-NEXT: entry:
	// CHECK12-NEXT: call void @__tgt_register_requires(i64 1)			// CHECK12-NEXT: call void @__tgt_register_requires(i64 1)
	// CHECK12-NEXT: ret void			// CHECK12-NEXT: ret void
	//			//
	//
	No newline at end of file

clang/test/OpenMP/distribute_parallel_for_proc_bind_codegen.cpp

	Show First 20 Lines • Show All 972 Lines • ▼ Show 20 Lines
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg			// CHECK2-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
	// CHECK2-SAME: () #[[ATTR4:[0-9]+]] {			// CHECK2-SAME: () #[[ATTR4:[0-9]+]] {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	// CHECK2-NEXT: call void @__tgt_register_requires(i64 1)			// CHECK2-NEXT: call void @__tgt_register_requires(i64 1)
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	//			//
	//
	No newline at end of file

clang/test/OpenMP/distribute_parallel_for_simd_firstprivate_codegen.cpp

This file is larger than 256 KB, so syntax highlighting is disabled by default.

	Show First 20 Lines • Show All 489 Lines • ▼ Show 20 Lines
	// CHECK1: omp.inner.for.body:			// CHECK1: omp.inner.for.body:
	// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !8			// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !8
	// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !8			// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !8
	// CHECK1-NEXT: store double 1.000000e+00, double* [[CONV]], align 8, !llvm.access.group !8			// CHECK1-NEXT: store double 1.000000e+00, double* [[CONV]], align 8, !llvm.access.group !8
	// CHECK1-NEXT: [[TMP10:%.]] = load double, double** [[TMP]], align 8, !llvm.access.group !8			// CHECK1-NEXT: [[TMP10:%.]] = load double, double** [[TMP]], align 8, !llvm.access.group !8
	// CHECK1-NEXT: store volatile double 1.000000e+00, double* [[TMP10]], align 8, !llvm.access.group !8			// CHECK1-NEXT: store volatile double 1.000000e+00, double* [[TMP10]], align 8, !llvm.access.group !8
	// CHECK1-NEXT: store i32 3, i32* [[CONV2]], align 4, !llvm.access.group !8			// CHECK1-NEXT: store i32 3, i32* [[CONV2]], align 8, !llvm.access.group !8
	// CHECK1-NEXT: store float 4.000000e+00, float* [[CONV3]], align 4, !llvm.access.group !8			// CHECK1-NEXT: store float 4.000000e+00, float* [[CONV3]], align 8, !llvm.access.group !8
	// CHECK1-NEXT: [[TMP11:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 0			// CHECK1-NEXT: [[TMP11:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 0
	// CHECK1-NEXT: store double* [[CONV]], double** [[TMP11]], align 8, !llvm.access.group !8			// CHECK1-NEXT: store double* [[CONV]], double** [[TMP11]], align 8, !llvm.access.group !8
	// CHECK1-NEXT: [[TMP12:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 1			// CHECK1-NEXT: [[TMP12:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 1
	// CHECK1-NEXT: [[TMP13:%.]] = load double, double** [[TMP]], align 8, !llvm.access.group !8			// CHECK1-NEXT: [[TMP13:%.]] = load double, double** [[TMP]], align 8, !llvm.access.group !8
	// CHECK1-NEXT: store double* [[TMP13]], double** [[TMP12]], align 8, !llvm.access.group !8			// CHECK1-NEXT: store double* [[TMP13]], double** [[TMP12]], align 8, !llvm.access.group !8
	// CHECK1-NEXT: [[TMP14:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 2			// CHECK1-NEXT: [[TMP14:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 2
	// CHECK1-NEXT: store i32* [[CONV2]], i32** [[TMP14]], align 8, !llvm.access.group !8			// CHECK1-NEXT: store i32* [[CONV2]], i32** [[TMP14]], align 8, !llvm.access.group !8
	// CHECK1-NEXT: [[TMP15:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 3			// CHECK1-NEXT: [[TMP15:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 3
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	// CHECK2: omp.inner.for.body:			// CHECK2: omp.inner.for.body:
	// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !8			// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !8
	// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !8			// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !8
	// CHECK2-NEXT: store double 1.000000e+00, double* [[CONV]], align 8, !llvm.access.group !8			// CHECK2-NEXT: store double 1.000000e+00, double* [[CONV]], align 8, !llvm.access.group !8
	// CHECK2-NEXT: [[TMP10:%.]] = load double, double** [[TMP]], align 8, !llvm.access.group !8			// CHECK2-NEXT: [[TMP10:%.]] = load double, double** [[TMP]], align 8, !llvm.access.group !8
	// CHECK2-NEXT: store volatile double 1.000000e+00, double* [[TMP10]], align 8, !llvm.access.group !8			// CHECK2-NEXT: store volatile double 1.000000e+00, double* [[TMP10]], align 8, !llvm.access.group !8
	// CHECK2-NEXT: store i32 3, i32* [[CONV2]], align 4, !llvm.access.group !8			// CHECK2-NEXT: store i32 3, i32* [[CONV2]], align 8, !llvm.access.group !8
	// CHECK2-NEXT: store float 4.000000e+00, float* [[CONV3]], align 4, !llvm.access.group !8			// CHECK2-NEXT: store float 4.000000e+00, float* [[CONV3]], align 8, !llvm.access.group !8
	// CHECK2-NEXT: [[TMP11:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 0			// CHECK2-NEXT: [[TMP11:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 0
	// CHECK2-NEXT: store double* [[CONV]], double** [[TMP11]], align 8, !llvm.access.group !8			// CHECK2-NEXT: store double* [[CONV]], double** [[TMP11]], align 8, !llvm.access.group !8
	// CHECK2-NEXT: [[TMP12:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 1			// CHECK2-NEXT: [[TMP12:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 1
	// CHECK2-NEXT: [[TMP13:%.]] = load double, double** [[TMP]], align 8, !llvm.access.group !8			// CHECK2-NEXT: [[TMP13:%.]] = load double, double** [[TMP]], align 8, !llvm.access.group !8
	// CHECK2-NEXT: store double* [[TMP13]], double** [[TMP12]], align 8, !llvm.access.group !8			// CHECK2-NEXT: store double* [[TMP13]], double** [[TMP12]], align 8, !llvm.access.group !8
	// CHECK2-NEXT: [[TMP14:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 2			// CHECK2-NEXT: [[TMP14:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 2
	// CHECK2-NEXT: store i32* [[CONV2]], i32** [[TMP14]], align 8, !llvm.access.group !8			// CHECK2-NEXT: store i32* [[CONV2]], i32** [[TMP14]], align 8, !llvm.access.group !8
	// CHECK2-NEXT: [[TMP15:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 3			// CHECK2-NEXT: [[TMP15:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 3
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	// CHECK8-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]			// CHECK8-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]
	// CHECK8: omp.inner.for.cond.cleanup:			// CHECK8: omp.inner.for.cond.cleanup:
	// CHECK8-NEXT: br label [[OMP_INNER_FOR_END:%.*]]			// CHECK8-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
	// CHECK8: omp.inner.for.body:			// CHECK8: omp.inner.for.body:
	// CHECK8-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9			// CHECK8-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP21]], 1			// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP21]], 1
	// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9			// CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9
	// CHECK8-NEXT: [[TMP22:%.]] = load i32, i32 [[CONV]], align 4, !llvm.access.group !9			// CHECK8-NEXT: [[TMP22:%.]] = load i32, i32 [[CONV]], align 8, !llvm.access.group !9
	// CHECK8-NEXT: [[TMP23:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !9			// CHECK8-NEXT: [[TMP23:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !9
	// CHECK8-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP23]] to i64			// CHECK8-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP23]] to i64
	// CHECK8-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC5]], i64 0, i64 [[IDXPROM]]			// CHECK8-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC5]], i64 0, i64 [[IDXPROM]]
	// CHECK8-NEXT: store i32 [[TMP22]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !9			// CHECK8-NEXT: store i32 [[TMP22]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !9
	// CHECK8-NEXT: [[TMP24:%.]] = load %struct.S, %struct.S** [[_TMP9]], align 8, !llvm.access.group !9			// CHECK8-NEXT: [[TMP24:%.]] = load %struct.S, %struct.S** [[_TMP9]], align 8, !llvm.access.group !9
	// CHECK8-NEXT: [[TMP25:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !9			// CHECK8-NEXT: [[TMP25:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !9
	// CHECK8-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP25]] to i64			// CHECK8-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP25]] to i64
	// CHECK8-NEXT: [[ARRAYIDX12:%.]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S] [[S_ARR6]], i64 0, i64 [[IDXPROM11]]			// CHECK8-NEXT: [[ARRAYIDX12:%.]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S] [[S_ARR6]], i64 0, i64 [[IDXPROM11]]
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	// CHECK8-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]			// CHECK8-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]
	// CHECK8: omp.inner.for.cond.cleanup:			// CHECK8: omp.inner.for.cond.cleanup:
	// CHECK8-NEXT: br label [[OMP_INNER_FOR_END:%.*]]			// CHECK8-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
	// CHECK8: omp.inner.for.body:			// CHECK8: omp.inner.for.body:
	// CHECK8-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !17			// CHECK8-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !17
	// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP21]], 1			// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP21]], 1
	// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !17			// CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !17
	// CHECK8-NEXT: [[TMP22:%.]] = load i32, i32 [[CONV]], align 4, !llvm.access.group !17			// CHECK8-NEXT: [[TMP22:%.]] = load i32, i32 [[CONV]], align 8, !llvm.access.group !17
	// CHECK8-NEXT: [[TMP23:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !17			// CHECK8-NEXT: [[TMP23:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !17
	// CHECK8-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP23]] to i64			// CHECK8-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP23]] to i64
	// CHECK8-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC4]], i64 0, i64 [[IDXPROM]]			// CHECK8-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC4]], i64 0, i64 [[IDXPROM]]
	// CHECK8-NEXT: store i32 [[TMP22]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !17			// CHECK8-NEXT: store i32 [[TMP22]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !17
	// CHECK8-NEXT: [[TMP24:%.]] = load %struct.S.0, %struct.S.0** [[_TMP8]], align 8, !llvm.access.group !17			// CHECK8-NEXT: [[TMP24:%.]] = load %struct.S.0, %struct.S.0** [[_TMP8]], align 8, !llvm.access.group !17
	// CHECK8-NEXT: [[TMP25:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !17			// CHECK8-NEXT: [[TMP25:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !17
	// CHECK8-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP25]] to i64			// CHECK8-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP25]] to i64
	// CHECK8-NEXT: [[ARRAYIDX11:%.]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0] [[S_ARR5]], i64 0, i64 [[IDXPROM10]]			// CHECK8-NEXT: [[ARRAYIDX11:%.]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0] [[S_ARR5]], i64 0, i64 [[IDXPROM10]]
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	// CHECK9-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]			// CHECK9-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]
	// CHECK9: omp.inner.for.cond.cleanup:			// CHECK9: omp.inner.for.cond.cleanup:
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_END:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
	// CHECK9: omp.inner.for.body:			// CHECK9: omp.inner.for.body:
	// CHECK9-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9			// CHECK9-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP21]], 1			// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP21]], 1
	// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9			// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9
	// CHECK9-NEXT: [[TMP22:%.]] = load i32, i32 [[CONV]], align 4, !llvm.access.group !9			// CHECK9-NEXT: [[TMP22:%.]] = load i32, i32 [[CONV]], align 8, !llvm.access.group !9
	// CHECK9-NEXT: [[TMP23:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !9			// CHECK9-NEXT: [[TMP23:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !9
	// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP23]] to i64			// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP23]] to i64
	// CHECK9-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC5]], i64 0, i64 [[IDXPROM]]			// CHECK9-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC5]], i64 0, i64 [[IDXPROM]]
	// CHECK9-NEXT: store i32 [[TMP22]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !9			// CHECK9-NEXT: store i32 [[TMP22]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !9
	// CHECK9-NEXT: [[TMP24:%.]] = load %struct.S, %struct.S** [[_TMP9]], align 8, !llvm.access.group !9			// CHECK9-NEXT: [[TMP24:%.]] = load %struct.S, %struct.S** [[_TMP9]], align 8, !llvm.access.group !9
	// CHECK9-NEXT: [[TMP25:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !9			// CHECK9-NEXT: [[TMP25:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !9
	// CHECK9-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP25]] to i64			// CHECK9-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP25]] to i64
	// CHECK9-NEXT: [[ARRAYIDX12:%.]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S] [[S_ARR6]], i64 0, i64 [[IDXPROM11]]			// CHECK9-NEXT: [[ARRAYIDX12:%.]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S] [[S_ARR6]], i64 0, i64 [[IDXPROM11]]
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	// CHECK9-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]			// CHECK9-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]
	// CHECK9: omp.inner.for.cond.cleanup:			// CHECK9: omp.inner.for.cond.cleanup:
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_END:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
	// CHECK9: omp.inner.for.body:			// CHECK9: omp.inner.for.body:
	// CHECK9-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !17			// CHECK9-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !17
	// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP21]], 1			// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP21]], 1
	// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !17			// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !17
	// CHECK9-NEXT: [[TMP22:%.]] = load i32, i32 [[CONV]], align 4, !llvm.access.group !17			// CHECK9-NEXT: [[TMP22:%.]] = load i32, i32 [[CONV]], align 8, !llvm.access.group !17
	// CHECK9-NEXT: [[TMP23:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !17			// CHECK9-NEXT: [[TMP23:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !17
	// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP23]] to i64			// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP23]] to i64
	// CHECK9-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC4]], i64 0, i64 [[IDXPROM]]			// CHECK9-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC4]], i64 0, i64 [[IDXPROM]]
	// CHECK9-NEXT: store i32 [[TMP22]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !17			// CHECK9-NEXT: store i32 [[TMP22]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !17
	// CHECK9-NEXT: [[TMP24:%.]] = load %struct.S.0, %struct.S.0** [[_TMP8]], align 8, !llvm.access.group !17			// CHECK9-NEXT: [[TMP24:%.]] = load %struct.S.0, %struct.S.0** [[_TMP8]], align 8, !llvm.access.group !17
	// CHECK9-NEXT: [[TMP25:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !17			// CHECK9-NEXT: [[TMP25:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !17
	// CHECK9-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP25]] to i64			// CHECK9-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP25]] to i64
	// CHECK9-NEXT: [[ARRAYIDX11:%.]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0] [[S_ARR5]], i64 0, i64 [[IDXPROM10]]			// CHECK9-NEXT: [[ARRAYIDX11:%.]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0] [[S_ARR5]], i64 0, i64 [[IDXPROM10]]
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clang/test/OpenMP/distribute_parallel_for_simd_lastprivate_codegen.cpp

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	// CHECK1-NEXT: br label [[COND_END]]			// CHECK1-NEXT: br label [[COND_END]]
	// CHECK1: cond.end:			// CHECK1: cond.end:
	// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ]			// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ]
	// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK1-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK1: omp.inner.for.cond:			// CHECK1: omp.inner.for.cond:
	// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !4
	// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !4
	// CHECK1-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]]			// CHECK1-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]]
	// CHECK1-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK1-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK1: omp.inner.for.body:			// CHECK1: omp.inner.for.body:
	// CHECK1-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK1-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !4
	// CHECK1-NEXT: [[TMP14:%.*]] = zext i32 [[TMP13]] to i64			// CHECK1-NEXT: [[TMP14:%.*]] = zext i32 [[TMP13]] to i64
	// CHECK1-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK1-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !4
	// CHECK1-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64			// CHECK1-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64
	// CHECK1-NEXT: [[TMP17:%.]] = load double, double** [[_TMP5]], align 8			// CHECK1-NEXT: [[TMP17:%.]] = load double, double** [[_TMP5]], align 8, !llvm.access.group !4
	// CHECK1-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, double, double, i32, float)* @.omp_outlined..1 to void (i32, i32, ...)), i64 [[TMP14]], i64 [[TMP16]], double [[G3]], double* [[TMP17]], i32* [[SVAR6]], float* [[SFVAR7]])			// CHECK1-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, double, double, i32, float)* @.omp_outlined..1 to void (i32, i32, ...)), i64 [[TMP14]], i64 [[TMP16]], double [[G3]], double* [[TMP17]], i32* [[SVAR6]], float* [[SFVAR7]]), !llvm.access.group !4
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK1: omp.inner.for.inc:			// CHECK1: omp.inner.for.inc:
	// CHECK1-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !4
	// CHECK1-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK1-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !4
	// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], [[TMP19]]			// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], [[TMP19]]
	// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]
	// CHECK1: omp.inner.for.end:			// CHECK1: omp.inner.for.end:
	// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK1: omp.loop.exit:			// CHECK1: omp.loop.exit:
	// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP7]])			// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP7]])
	// CHECK1-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK1-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK1-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0			// CHECK1-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0
	// CHECK1-NEXT: br i1 [[TMP21]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK1-NEXT: br i1 [[TMP21]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK1: .omp.final.then:			// CHECK1: .omp.final.then:
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	// CHECK1-NEXT: br label [[COND_END]]			// CHECK1-NEXT: br label [[COND_END]]
	// CHECK1: cond.end:			// CHECK1: cond.end:
	// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ]			// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ]
	// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK1-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK1: omp.inner.for.cond:			// CHECK1: omp.inner.for.cond:
	// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !8
	// CHECK1-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK1-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !8
	// CHECK1-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]]			// CHECK1-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]]
	// CHECK1-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK1-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK1: omp.inner.for.body:			// CHECK1: omp.inner.for.body:
	// CHECK1-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !8
	// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1			// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1
	// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !8
	// CHECK1-NEXT: store double 1.000000e+00, double* [[G3]], align 8			// CHECK1-NEXT: store double 1.000000e+00, double* [[G3]], align 8, !llvm.access.group !8
	// CHECK1-NEXT: [[TMP15:%.]] = load double, double** [[_TMP5]], align 8			// CHECK1-NEXT: [[TMP15:%.]] = load double, double** [[_TMP5]], align 8, !llvm.access.group !8
	// CHECK1-NEXT: store volatile double 1.000000e+00, double* [[TMP15]], align 8			// CHECK1-NEXT: store volatile double 1.000000e+00, double* [[TMP15]], align 8, !llvm.access.group !8
	// CHECK1-NEXT: store i32 3, i32* [[SVAR6]], align 4			// CHECK1-NEXT: store i32 3, i32* [[SVAR6]], align 4, !llvm.access.group !8
	// CHECK1-NEXT: store float 4.000000e+00, float* [[SFVAR7]], align 4			// CHECK1-NEXT: store float 4.000000e+00, float* [[SFVAR7]], align 4, !llvm.access.group !8
	// CHECK1-NEXT: [[TMP16:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 0			// CHECK1-NEXT: [[TMP16:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 0
	// CHECK1-NEXT: store double* [[G3]], double** [[TMP16]], align 8			// CHECK1-NEXT: store double* [[G3]], double** [[TMP16]], align 8, !llvm.access.group !8
	// CHECK1-NEXT: [[TMP17:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 1			// CHECK1-NEXT: [[TMP17:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 1
	// CHECK1-NEXT: [[TMP18:%.]] = load double, double** [[_TMP5]], align 8			// CHECK1-NEXT: [[TMP18:%.]] = load double, double** [[_TMP5]], align 8, !llvm.access.group !8
	// CHECK1-NEXT: store double* [[TMP18]], double** [[TMP17]], align 8			// CHECK1-NEXT: store double* [[TMP18]], double** [[TMP17]], align 8, !llvm.access.group !8
	// CHECK1-NEXT: [[TMP19:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 2			// CHECK1-NEXT: [[TMP19:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 2
	// CHECK1-NEXT: store i32* [[SVAR6]], i32** [[TMP19]], align 8			// CHECK1-NEXT: store i32* [[SVAR6]], i32** [[TMP19]], align 8, !llvm.access.group !8
	// CHECK1-NEXT: [[TMP20:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 3			// CHECK1-NEXT: [[TMP20:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 3
	// CHECK1-NEXT: store float* [[SFVAR7]], float** [[TMP20]], align 8			// CHECK1-NEXT: store float* [[SFVAR7]], float** [[TMP20]], align 8, !llvm.access.group !8
	// CHECK1-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(32) [[REF_TMP]])			// CHECK1-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(32) [[REF_TMP]]), !llvm.access.group !8
	// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK1: omp.body.continue:			// CHECK1: omp.body.continue:
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK1: omp.inner.for.inc:			// CHECK1: omp.inner.for.inc:
	// CHECK1-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !8
	// CHECK1-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP21]], 1			// CHECK1-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP21]], 1
	// CHECK1-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]
	// CHECK1: omp.inner.for.end:			// CHECK1: omp.inner.for.end:
	// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK1: omp.loop.exit:			// CHECK1: omp.loop.exit:
	// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]])			// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]])
	// CHECK1-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK1-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK1-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0			// CHECK1-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0
	// CHECK1-NEXT: br i1 [[TMP23]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK1-NEXT: br i1 [[TMP23]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK1: .omp.final.then:			// CHECK1: .omp.final.then:
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	// CHECK2-NEXT: br label [[COND_END]]			// CHECK2-NEXT: br label [[COND_END]]
	// CHECK2: cond.end:			// CHECK2: cond.end:
	// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ]			// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ]
	// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK2-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK2-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK2-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK2: omp.inner.for.cond:			// CHECK2: omp.inner.for.cond:
	// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !4
	// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !4
	// CHECK2-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]]			// CHECK2-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]]
	// CHECK2-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK2-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK2: omp.inner.for.body:			// CHECK2: omp.inner.for.body:
	// CHECK2-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK2-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !4
	// CHECK2-NEXT: [[TMP14:%.*]] = zext i32 [[TMP13]] to i64			// CHECK2-NEXT: [[TMP14:%.*]] = zext i32 [[TMP13]] to i64
	// CHECK2-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK2-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !4
	// CHECK2-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64			// CHECK2-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64
	// CHECK2-NEXT: [[TMP17:%.]] = load double, double** [[_TMP5]], align 8			// CHECK2-NEXT: [[TMP17:%.]] = load double, double** [[_TMP5]], align 8, !llvm.access.group !4
	// CHECK2-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, double, double, i32, float)* @.omp_outlined..1 to void (i32, i32, ...)), i64 [[TMP14]], i64 [[TMP16]], double [[G3]], double* [[TMP17]], i32* [[SVAR6]], float* [[SFVAR7]])			// CHECK2-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, double, double, i32, float)* @.omp_outlined..1 to void (i32, i32, ...)), i64 [[TMP14]], i64 [[TMP16]], double [[G3]], double* [[TMP17]], i32* [[SVAR6]], float* [[SFVAR7]]), !llvm.access.group !4
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK2: omp.inner.for.inc:			// CHECK2: omp.inner.for.inc:
	// CHECK2-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !4
	// CHECK2-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK2-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !4
	// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], [[TMP19]]			// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], [[TMP19]]
	// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]
	// CHECK2: omp.inner.for.end:			// CHECK2: omp.inner.for.end:
	// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK2: omp.loop.exit:			// CHECK2: omp.loop.exit:
	// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP7]])			// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP7]])
	// CHECK2-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK2-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK2-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0			// CHECK2-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0
	// CHECK2-NEXT: br i1 [[TMP21]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK2-NEXT: br i1 [[TMP21]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK2: .omp.final.then:			// CHECK2: .omp.final.then:
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	// CHECK2-NEXT: br label [[COND_END]]			// CHECK2-NEXT: br label [[COND_END]]
	// CHECK2: cond.end:			// CHECK2: cond.end:
	// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ]			// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ]
	// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK2-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK2: omp.inner.for.cond:			// CHECK2: omp.inner.for.cond:
	// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !8
	// CHECK2-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK2-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !8
	// CHECK2-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]]			// CHECK2-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]]
	// CHECK2-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK2-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK2: omp.inner.for.body:			// CHECK2: omp.inner.for.body:
	// CHECK2-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !8
	// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1			// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1
	// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !8
	// CHECK2-NEXT: store double 1.000000e+00, double* [[G3]], align 8			// CHECK2-NEXT: store double 1.000000e+00, double* [[G3]], align 8, !llvm.access.group !8
	// CHECK2-NEXT: [[TMP15:%.]] = load double, double** [[_TMP5]], align 8			// CHECK2-NEXT: [[TMP15:%.]] = load double, double** [[_TMP5]], align 8, !llvm.access.group !8
	// CHECK2-NEXT: store volatile double 1.000000e+00, double* [[TMP15]], align 8			// CHECK2-NEXT: store volatile double 1.000000e+00, double* [[TMP15]], align 8, !llvm.access.group !8
	// CHECK2-NEXT: store i32 3, i32* [[SVAR6]], align 4			// CHECK2-NEXT: store i32 3, i32* [[SVAR6]], align 4, !llvm.access.group !8
	// CHECK2-NEXT: store float 4.000000e+00, float* [[SFVAR7]], align 4			// CHECK2-NEXT: store float 4.000000e+00, float* [[SFVAR7]], align 4, !llvm.access.group !8
	// CHECK2-NEXT: [[TMP16:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 0			// CHECK2-NEXT: [[TMP16:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 0
	// CHECK2-NEXT: store double* [[G3]], double** [[TMP16]], align 8			// CHECK2-NEXT: store double* [[G3]], double** [[TMP16]], align 8, !llvm.access.group !8
	// CHECK2-NEXT: [[TMP17:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 1			// CHECK2-NEXT: [[TMP17:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 1
	// CHECK2-NEXT: [[TMP18:%.]] = load double, double** [[_TMP5]], align 8			// CHECK2-NEXT: [[TMP18:%.]] = load double, double** [[_TMP5]], align 8, !llvm.access.group !8
	// CHECK2-NEXT: store double* [[TMP18]], double** [[TMP17]], align 8			// CHECK2-NEXT: store double* [[TMP18]], double** [[TMP17]], align 8, !llvm.access.group !8
	// CHECK2-NEXT: [[TMP19:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 2			// CHECK2-NEXT: [[TMP19:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 2
	// CHECK2-NEXT: store i32* [[SVAR6]], i32** [[TMP19]], align 8			// CHECK2-NEXT: store i32* [[SVAR6]], i32** [[TMP19]], align 8, !llvm.access.group !8
	// CHECK2-NEXT: [[TMP20:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 3			// CHECK2-NEXT: [[TMP20:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 3
	// CHECK2-NEXT: store float* [[SFVAR7]], float** [[TMP20]], align 8			// CHECK2-NEXT: store float* [[SFVAR7]], float** [[TMP20]], align 8, !llvm.access.group !8
	// CHECK2-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(32) [[REF_TMP]])			// CHECK2-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(32) [[REF_TMP]]), !llvm.access.group !8
	// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK2: omp.body.continue:			// CHECK2: omp.body.continue:
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK2: omp.inner.for.inc:			// CHECK2: omp.inner.for.inc:
	// CHECK2-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !8
	// CHECK2-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP21]], 1			// CHECK2-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP21]], 1
	// CHECK2-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]
	// CHECK2: omp.inner.for.end:			// CHECK2: omp.inner.for.end:
	// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK2: omp.loop.exit:			// CHECK2: omp.loop.exit:
	// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]])			// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]])
	// CHECK2-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK2-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK2-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0			// CHECK2-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0
	// CHECK2-NEXT: br i1 [[TMP23]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK2-NEXT: br i1 [[TMP23]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK2: .omp.final.then:			// CHECK2: .omp.final.then:
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	// CHECK3-NEXT: br label [[COND_END]]			// CHECK3-NEXT: br label [[COND_END]]
	// CHECK3: cond.end:			// CHECK3: cond.end:
	// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ]			// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ]
	// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK3-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK3-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK3-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4			// CHECK3-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK3: omp.inner.for.cond:			// CHECK3: omp.inner.for.cond:
	// CHECK3-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK3-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK3-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK3-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5
	// CHECK3-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]]			// CHECK3-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]]
	// CHECK3-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK3-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK3: omp.inner.for.body:			// CHECK3: omp.inner.for.body:
	// CHECK3-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK3-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !5
	// CHECK3-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK3-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5
	// CHECK3-NEXT: [[TMP15:%.]] = load double, double** [[_TMP5]], align 4			// CHECK3-NEXT: [[TMP15:%.]] = load double, double** [[_TMP5]], align 4, !llvm.access.group !5
	// CHECK3-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32, i32, ...)* bitcast (void (i32, i32, i32, i32, double, double, i32, float)* @.omp_outlined..1 to void (i32, i32, ...)), i32 [[TMP13]], i32 [[TMP14]], double [[G3]], double* [[TMP15]], i32* [[SVAR6]], float* [[SFVAR7]])			// CHECK3-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32, i32, ...)* bitcast (void (i32, i32, i32, i32, double, double, i32, float)* @.omp_outlined..1 to void (i32, i32, ...)), i32 [[TMP13]], i32 [[TMP14]], double [[G3]], double* [[TMP15]], i32* [[SVAR6]], float* [[SFVAR7]]), !llvm.access.group !5
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK3: omp.inner.for.inc:			// CHECK3: omp.inner.for.inc:
	// CHECK3-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK3-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK3-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK3-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !5
	// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP16]], [[TMP17]]			// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP16]], [[TMP17]]
	// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]
	// CHECK3: omp.inner.for.end:			// CHECK3: omp.inner.for.end:
	// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK3: omp.loop.exit:			// CHECK3: omp.loop.exit:
	// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP7]])			// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP7]])
	// CHECK3-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK3-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK3-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0			// CHECK3-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
	// CHECK3-NEXT: br i1 [[TMP19]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK3-NEXT: br i1 [[TMP19]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK3: .omp.final.then:			// CHECK3: .omp.final.then:
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	// CHECK3-NEXT: br label [[COND_END]]			// CHECK3-NEXT: br label [[COND_END]]
	// CHECK3: cond.end:			// CHECK3: cond.end:
	// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ]			// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ]
	// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK3-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK3-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK3-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4			// CHECK3-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK3: omp.inner.for.cond:			// CHECK3: omp.inner.for.cond:
	// CHECK3-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK3-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK3-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK3-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !9
	// CHECK3-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]]			// CHECK3-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]]
	// CHECK3-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK3-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK3: omp.inner.for.body:			// CHECK3: omp.inner.for.body:
	// CHECK3-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK3-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1			// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1
	// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9
	// CHECK3-NEXT: store double 1.000000e+00, double* [[G2]], align 8			// CHECK3-NEXT: store double 1.000000e+00, double* [[G2]], align 8, !llvm.access.group !9
	// CHECK3-NEXT: [[TMP15:%.]] = load double, double** [[_TMP4]], align 4			// CHECK3-NEXT: [[TMP15:%.]] = load double, double** [[_TMP4]], align 4, !llvm.access.group !9
	// CHECK3-NEXT: store volatile double 1.000000e+00, double* [[TMP15]], align 4			// CHECK3-NEXT: store volatile double 1.000000e+00, double* [[TMP15]], align 4, !llvm.access.group !9
	// CHECK3-NEXT: store i32 3, i32* [[SVAR5]], align 4			// CHECK3-NEXT: store i32 3, i32* [[SVAR5]], align 4, !llvm.access.group !9
	// CHECK3-NEXT: store float 4.000000e+00, float* [[SFVAR6]], align 4			// CHECK3-NEXT: store float 4.000000e+00, float* [[SFVAR6]], align 4, !llvm.access.group !9
	// CHECK3-NEXT: [[TMP16:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 0			// CHECK3-NEXT: [[TMP16:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 0
	// CHECK3-NEXT: store double* [[G2]], double** [[TMP16]], align 4			// CHECK3-NEXT: store double* [[G2]], double** [[TMP16]], align 4, !llvm.access.group !9
	// CHECK3-NEXT: [[TMP17:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 1			// CHECK3-NEXT: [[TMP17:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 1
	// CHECK3-NEXT: [[TMP18:%.]] = load double, double** [[_TMP4]], align 4			// CHECK3-NEXT: [[TMP18:%.]] = load double, double** [[_TMP4]], align 4, !llvm.access.group !9
	// CHECK3-NEXT: store double* [[TMP18]], double** [[TMP17]], align 4			// CHECK3-NEXT: store double* [[TMP18]], double** [[TMP17]], align 4, !llvm.access.group !9
	// CHECK3-NEXT: [[TMP19:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 2			// CHECK3-NEXT: [[TMP19:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 2
	// CHECK3-NEXT: store i32* [[SVAR5]], i32** [[TMP19]], align 4			// CHECK3-NEXT: store i32* [[SVAR5]], i32** [[TMP19]], align 4, !llvm.access.group !9
	// CHECK3-NEXT: [[TMP20:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 3			// CHECK3-NEXT: [[TMP20:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 3
	// CHECK3-NEXT: store float* [[SFVAR6]], float** [[TMP20]], align 4			// CHECK3-NEXT: store float* [[SFVAR6]], float** [[TMP20]], align 4, !llvm.access.group !9
	// CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 4 dereferenceable(16) [[REF_TMP]])			// CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 4 dereferenceable(16) [[REF_TMP]]), !llvm.access.group !9
	// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK3: omp.body.continue:			// CHECK3: omp.body.continue:
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK3: omp.inner.for.inc:			// CHECK3: omp.inner.for.inc:
	// CHECK3-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK3-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK3-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP21]], 1			// CHECK3-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP21]], 1
	// CHECK3-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4			// CHECK3-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]
	// CHECK3: omp.inner.for.end:			// CHECK3: omp.inner.for.end:
	// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK3: omp.loop.exit:			// CHECK3: omp.loop.exit:
	// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]])			// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]])
	// CHECK3-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK3-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK3-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0			// CHECK3-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0
	// CHECK3-NEXT: br i1 [[TMP23]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK3-NEXT: br i1 [[TMP23]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK3: .omp.final.then:			// CHECK3: .omp.final.then:
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	// CHECK4-NEXT: br label [[COND_END]]			// CHECK4-NEXT: br label [[COND_END]]
	// CHECK4: cond.end:			// CHECK4: cond.end:
	// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ]			// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ]
	// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK4-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK4-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK4-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4			// CHECK4-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK4: omp.inner.for.cond:			// CHECK4: omp.inner.for.cond:
	// CHECK4-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK4-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK4-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK4-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5
	// CHECK4-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]]			// CHECK4-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]]
	// CHECK4-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK4-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK4: omp.inner.for.body:			// CHECK4: omp.inner.for.body:
	// CHECK4-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK4-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !5
	// CHECK4-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK4-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5
	// CHECK4-NEXT: [[TMP15:%.]] = load double, double** [[_TMP5]], align 4			// CHECK4-NEXT: [[TMP15:%.]] = load double, double** [[_TMP5]], align 4, !llvm.access.group !5
	// CHECK4-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32, i32, ...)* bitcast (void (i32, i32, i32, i32, double, double, i32, float)* @.omp_outlined..1 to void (i32, i32, ...)), i32 [[TMP13]], i32 [[TMP14]], double [[G3]], double* [[TMP15]], i32* [[SVAR6]], float* [[SFVAR7]])			// CHECK4-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32, i32, ...)* bitcast (void (i32, i32, i32, i32, double, double, i32, float)* @.omp_outlined..1 to void (i32, i32, ...)), i32 [[TMP13]], i32 [[TMP14]], double [[G3]], double* [[TMP15]], i32* [[SVAR6]], float* [[SFVAR7]]), !llvm.access.group !5
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK4: omp.inner.for.inc:			// CHECK4: omp.inner.for.inc:
	// CHECK4-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK4-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK4-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK4-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !5
	// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP16]], [[TMP17]]			// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP16]], [[TMP17]]
	// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]
	// CHECK4: omp.inner.for.end:			// CHECK4: omp.inner.for.end:
	// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK4: omp.loop.exit:			// CHECK4: omp.loop.exit:
	// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP7]])			// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP7]])
	// CHECK4-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK4-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK4-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0			// CHECK4-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
	// CHECK4-NEXT: br i1 [[TMP19]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK4-NEXT: br i1 [[TMP19]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK4: .omp.final.then:			// CHECK4: .omp.final.then:
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	// CHECK4-NEXT: br label [[COND_END]]			// CHECK4-NEXT: br label [[COND_END]]
	// CHECK4: cond.end:			// CHECK4: cond.end:
	// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ]			// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ]
	// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK4-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK4-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK4-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4			// CHECK4-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK4: omp.inner.for.cond:			// CHECK4: omp.inner.for.cond:
	// CHECK4-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK4-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK4-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK4-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !9
	// CHECK4-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]]			// CHECK4-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]]
	// CHECK4-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK4-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK4: omp.inner.for.body:			// CHECK4: omp.inner.for.body:
	// CHECK4-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK4-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1			// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1
	// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9
	// CHECK4-NEXT: store double 1.000000e+00, double* [[G2]], align 8			// CHECK4-NEXT: store double 1.000000e+00, double* [[G2]], align 8, !llvm.access.group !9
	// CHECK4-NEXT: [[TMP15:%.]] = load double, double** [[_TMP4]], align 4			// CHECK4-NEXT: [[TMP15:%.]] = load double, double** [[_TMP4]], align 4, !llvm.access.group !9
	// CHECK4-NEXT: store volatile double 1.000000e+00, double* [[TMP15]], align 4			// CHECK4-NEXT: store volatile double 1.000000e+00, double* [[TMP15]], align 4, !llvm.access.group !9
	// CHECK4-NEXT: store i32 3, i32* [[SVAR5]], align 4			// CHECK4-NEXT: store i32 3, i32* [[SVAR5]], align 4, !llvm.access.group !9
	// CHECK4-NEXT: store float 4.000000e+00, float* [[SFVAR6]], align 4			// CHECK4-NEXT: store float 4.000000e+00, float* [[SFVAR6]], align 4, !llvm.access.group !9
	// CHECK4-NEXT: [[TMP16:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 0			// CHECK4-NEXT: [[TMP16:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 0
	// CHECK4-NEXT: store double* [[G2]], double** [[TMP16]], align 4			// CHECK4-NEXT: store double* [[G2]], double** [[TMP16]], align 4, !llvm.access.group !9
	// CHECK4-NEXT: [[TMP17:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 1			// CHECK4-NEXT: [[TMP17:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 1
	// CHECK4-NEXT: [[TMP18:%.]] = load double, double** [[_TMP4]], align 4			// CHECK4-NEXT: [[TMP18:%.]] = load double, double** [[_TMP4]], align 4, !llvm.access.group !9
	// CHECK4-NEXT: store double* [[TMP18]], double** [[TMP17]], align 4			// CHECK4-NEXT: store double* [[TMP18]], double** [[TMP17]], align 4, !llvm.access.group !9
	// CHECK4-NEXT: [[TMP19:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 2			// CHECK4-NEXT: [[TMP19:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 2
	// CHECK4-NEXT: store i32* [[SVAR5]], i32** [[TMP19]], align 4			// CHECK4-NEXT: store i32* [[SVAR5]], i32** [[TMP19]], align 4, !llvm.access.group !9
	// CHECK4-NEXT: [[TMP20:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 3			// CHECK4-NEXT: [[TMP20:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 3
	// CHECK4-NEXT: store float* [[SFVAR6]], float** [[TMP20]], align 4			// CHECK4-NEXT: store float* [[SFVAR6]], float** [[TMP20]], align 4, !llvm.access.group !9
	// CHECK4-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 4 dereferenceable(16) [[REF_TMP]])			// CHECK4-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 4 dereferenceable(16) [[REF_TMP]]), !llvm.access.group !9
	// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK4: omp.body.continue:			// CHECK4: omp.body.continue:
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK4: omp.inner.for.inc:			// CHECK4: omp.inner.for.inc:
	// CHECK4-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK4-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK4-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP21]], 1			// CHECK4-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP21]], 1
	// CHECK4-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4			// CHECK4-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]
	// CHECK4: omp.inner.for.end:			// CHECK4: omp.inner.for.end:
	// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK4: omp.loop.exit:			// CHECK4: omp.loop.exit:
	// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]])			// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]])
	// CHECK4-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK4-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK4-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0			// CHECK4-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0
	// CHECK4-NEXT: br i1 [[TMP23]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK4-NEXT: br i1 [[TMP23]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK4: .omp.final.then:			// CHECK4: .omp.final.then:
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	// CHECK9-NEXT: br label [[COND_END]]			// CHECK9-NEXT: br label [[COND_END]]
	// CHECK9: cond.end:			// CHECK9: cond.end:
	// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ]			// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ]
	// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK9-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK9-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK9-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4			// CHECK9-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK9: omp.inner.for.cond:			// CHECK9: omp.inner.for.cond:
	// CHECK9-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK9-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK9-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5
	// CHECK9-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]]			// CHECK9-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]]
	// CHECK9-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]			// CHECK9-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]
	// CHECK9: omp.inner.for.cond.cleanup:			// CHECK9: omp.inner.for.cond.cleanup:
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_END:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
	// CHECK9: omp.inner.for.body:			// CHECK9: omp.inner.for.body:
	// CHECK9-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK9-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !5
	// CHECK9-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64			// CHECK9-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64
	// CHECK9-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK9-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5
	// CHECK9-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64			// CHECK9-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
	// CHECK9-NEXT: [[TMP18:%.]] = load %struct.S, %struct.S** [[_TMP7]], align 8			// CHECK9-NEXT: [[TMP18:%.]] = load %struct.S, %struct.S** [[_TMP7]], align 8, !llvm.access.group !5
	// CHECK9-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, [2 x i32], i32, [2 x %struct.S], %struct.S, i32) @.omp_outlined..1 to void (i32, i32, ...)), i64 [[TMP15]], i64 [[TMP17]], [2 x i32] [[VEC4]], i32* [[T_VAR3]], [2 x %struct.S]* [[S_ARR5]], %struct.S* [[TMP18]], i32* [[SVAR8]])			// CHECK9-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, [2 x i32], i32, [2 x %struct.S], %struct.S, i32) @.omp_outlined..1 to void (i32, i32, ...)), i64 [[TMP15]], i64 [[TMP17]], [2 x i32] [[VEC4]], i32* [[T_VAR3]], [2 x %struct.S]* [[S_ARR5]], %struct.S* [[TMP18]], i32* [[SVAR8]]), !llvm.access.group !5
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK9: omp.inner.for.inc:			// CHECK9: omp.inner.for.inc:
	// CHECK9-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK9-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK9-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !5
	// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], [[TMP20]]			// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], [[TMP20]]
	// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]
	// CHECK9: omp.inner.for.end:			// CHECK9: omp.inner.for.end:
	// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK9: omp.loop.exit:			// CHECK9: omp.loop.exit:
	// CHECK9-NEXT: [[TMP21:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK9-NEXT: [[TMP21:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK9-NEXT: [[TMP22:%.]] = load i32, i32 [[TMP21]], align 4			// CHECK9-NEXT: [[TMP22:%.]] = load i32, i32 [[TMP21]], align 4
	// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]])			// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]])
	// CHECK9-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK9-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK9-NEXT: [[TMP24:%.*]] = icmp ne i32 [[TMP23]], 0			// CHECK9-NEXT: [[TMP24:%.*]] = icmp ne i32 [[TMP23]], 0
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	// CHECK9-NEXT: br label [[COND_END]]			// CHECK9-NEXT: br label [[COND_END]]
	// CHECK9: cond.end:			// CHECK9: cond.end:
	// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ]			// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ]
	// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK9-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK9-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK9-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4			// CHECK9-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK9: omp.inner.for.cond:			// CHECK9: omp.inner.for.cond:
	// CHECK9-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK9-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK9-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !9
	// CHECK9-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]			// CHECK9-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
	// CHECK9-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]			// CHECK9-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]
	// CHECK9: omp.inner.for.cond.cleanup:			// CHECK9: omp.inner.for.cond.cleanup:
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_END:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
	// CHECK9: omp.inner.for.body:			// CHECK9: omp.inner.for.body:
	// CHECK9-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1			// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1
	// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9
	// CHECK9-NEXT: [[TMP16:%.]] = load i32, i32 [[T_VAR3]], align 4			// CHECK9-NEXT: [[TMP16:%.]] = load i32, i32 [[T_VAR3]], align 4, !llvm.access.group !9
	// CHECK9-NEXT: [[TMP17:%.]] = load i32, i32 [[I]], align 4			// CHECK9-NEXT: [[TMP17:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !9
	// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64			// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64
	// CHECK9-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC4]], i64 0, i64 [[IDXPROM]]			// CHECK9-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC4]], i64 0, i64 [[IDXPROM]]
	// CHECK9-NEXT: store i32 [[TMP16]], i32* [[ARRAYIDX]], align 4			// CHECK9-NEXT: store i32 [[TMP16]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !9
	// CHECK9-NEXT: [[TMP18:%.]] = load %struct.S, %struct.S** [[_TMP7]], align 8			// CHECK9-NEXT: [[TMP18:%.]] = load %struct.S, %struct.S** [[_TMP7]], align 8, !llvm.access.group !9
	// CHECK9-NEXT: [[TMP19:%.]] = load i32, i32 [[I]], align 4			// CHECK9-NEXT: [[TMP19:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !9
	// CHECK9-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP19]] to i64			// CHECK9-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP19]] to i64
	// CHECK9-NEXT: [[ARRAYIDX11:%.]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S] [[S_ARR5]], i64 0, i64 [[IDXPROM10]]			// CHECK9-NEXT: [[ARRAYIDX11:%.]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S] [[S_ARR5]], i64 0, i64 [[IDXPROM10]]
	// CHECK9-NEXT: [[TMP20:%.]] = bitcast %struct.S [[ARRAYIDX11]] to i8*			// CHECK9-NEXT: [[TMP20:%.]] = bitcast %struct.S [[ARRAYIDX11]] to i8*
	// CHECK9-NEXT: [[TMP21:%.]] = bitcast %struct.S [[TMP18]] to i8*			// CHECK9-NEXT: [[TMP21:%.]] = bitcast %struct.S [[TMP18]] to i8*
	// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i64 4, i1 false)			// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i64 4, i1 false), !llvm.access.group !9
	// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK9: omp.body.continue:			// CHECK9: omp.body.continue:
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK9: omp.inner.for.inc:			// CHECK9: omp.inner.for.inc:
	// CHECK9-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK9-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP22]], 1			// CHECK9-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP22]], 1
	// CHECK9-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4			// CHECK9-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]
	// CHECK9: omp.inner.for.end:			// CHECK9: omp.inner.for.end:
	// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK9: omp.loop.exit:			// CHECK9: omp.loop.exit:
	// CHECK9-NEXT: [[TMP23:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK9-NEXT: [[TMP23:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK9-NEXT: [[TMP24:%.]] = load i32, i32 [[TMP23]], align 4			// CHECK9-NEXT: [[TMP24:%.]] = load i32, i32 [[TMP23]], align 4
	// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]])			// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]])
	// CHECK9-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK9-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK9-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0			// CHECK9-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0
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	// CHECK9-NEXT: br label [[COND_END]]			// CHECK9-NEXT: br label [[COND_END]]
	// CHECK9: cond.end:			// CHECK9: cond.end:
	// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ]			// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ]
	// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK9-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK9-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK9-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4			// CHECK9-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK9: omp.inner.for.cond:			// CHECK9: omp.inner.for.cond:
	// CHECK9-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK9-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK9-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !14
	// CHECK9-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]]			// CHECK9-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]]
	// CHECK9-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]			// CHECK9-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]
	// CHECK9: omp.inner.for.cond.cleanup:			// CHECK9: omp.inner.for.cond.cleanup:
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_END:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
	// CHECK9: omp.inner.for.body:			// CHECK9: omp.inner.for.body:
	// CHECK9-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK9-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !14
	// CHECK9-NEXT: [[TMP14:%.*]] = zext i32 [[TMP13]] to i64			// CHECK9-NEXT: [[TMP14:%.*]] = zext i32 [[TMP13]] to i64
	// CHECK9-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK9-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !14
	// CHECK9-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64			// CHECK9-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64
	// CHECK9-NEXT: [[TMP17:%.]] = load %struct.S.0, %struct.S.0** [[_TMP7]], align 8			// CHECK9-NEXT: [[TMP17:%.]] = load %struct.S.0, %struct.S.0** [[_TMP7]], align 8, !llvm.access.group !14
	// CHECK9-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, [2 x i32], i32, [2 x %struct.S.0], %struct.S.0)* @.omp_outlined..3 to void (i32, i32, ...)), i64 [[TMP14]], i64 [[TMP16]], [2 x i32] [[VEC4]], i32* [[T_VAR3]], [2 x %struct.S.0]* [[S_ARR5]], %struct.S.0* [[TMP17]])			// CHECK9-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, [2 x i32], i32, [2 x %struct.S.0], %struct.S.0)* @.omp_outlined..3 to void (i32, i32, ...)), i64 [[TMP14]], i64 [[TMP16]], [2 x i32] [[VEC4]], i32* [[T_VAR3]], [2 x %struct.S.0]* [[S_ARR5]], %struct.S.0* [[TMP17]]), !llvm.access.group !14
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK9: omp.inner.for.inc:			// CHECK9: omp.inner.for.inc:
	// CHECK9-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK9-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK9-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !14
	// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], [[TMP19]]			// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], [[TMP19]]
	// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]]
	// CHECK9: omp.inner.for.end:			// CHECK9: omp.inner.for.end:
	// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK9: omp.loop.exit:			// CHECK9: omp.loop.exit:
	// CHECK9-NEXT: [[TMP20:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK9-NEXT: [[TMP20:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK9-NEXT: [[TMP21:%.]] = load i32, i32 [[TMP20]], align 4			// CHECK9-NEXT: [[TMP21:%.]] = load i32, i32 [[TMP20]], align 4
	// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP21]])			// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP21]])
	// CHECK9-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK9-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK9-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0			// CHECK9-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0
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	// CHECK9-NEXT: br label [[COND_END]]			// CHECK9-NEXT: br label [[COND_END]]
	// CHECK9: cond.end:			// CHECK9: cond.end:
	// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ]			// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ]
	// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK9-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK9-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK9-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4			// CHECK9-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK9: omp.inner.for.cond:			// CHECK9: omp.inner.for.cond:
	// CHECK9-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !17
	// CHECK9-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK9-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !17
	// CHECK9-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]]			// CHECK9-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]]
	// CHECK9-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]			// CHECK9-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]
	// CHECK9: omp.inner.for.cond.cleanup:			// CHECK9: omp.inner.for.cond.cleanup:
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_END:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
	// CHECK9: omp.inner.for.body:			// CHECK9: omp.inner.for.body:
	// CHECK9-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !17
	// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1			// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1
	// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !17
	// CHECK9-NEXT: [[TMP15:%.]] = load i32, i32 [[T_VAR3]], align 4			// CHECK9-NEXT: [[TMP15:%.]] = load i32, i32 [[T_VAR3]], align 4, !llvm.access.group !17
	// CHECK9-NEXT: [[TMP16:%.]] = load i32, i32 [[I]], align 4			// CHECK9-NEXT: [[TMP16:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !17
	// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64			// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64
	// CHECK9-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC4]], i64 0, i64 [[IDXPROM]]			// CHECK9-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC4]], i64 0, i64 [[IDXPROM]]
	// CHECK9-NEXT: store i32 [[TMP15]], i32* [[ARRAYIDX]], align 4			// CHECK9-NEXT: store i32 [[TMP15]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !17
	// CHECK9-NEXT: [[TMP17:%.]] = load %struct.S.0, %struct.S.0** [[_TMP7]], align 8			// CHECK9-NEXT: [[TMP17:%.]] = load %struct.S.0, %struct.S.0** [[_TMP7]], align 8, !llvm.access.group !17
	// CHECK9-NEXT: [[TMP18:%.]] = load i32, i32 [[I]], align 4			// CHECK9-NEXT: [[TMP18:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !17
	// CHECK9-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP18]] to i64			// CHECK9-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP18]] to i64
	// CHECK9-NEXT: [[ARRAYIDX10:%.]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0] [[S_ARR5]], i64 0, i64 [[IDXPROM9]]			// CHECK9-NEXT: [[ARRAYIDX10:%.]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0] [[S_ARR5]], i64 0, i64 [[IDXPROM9]]
	// CHECK9-NEXT: [[TMP19:%.]] = bitcast %struct.S.0 [[ARRAYIDX10]] to i8*			// CHECK9-NEXT: [[TMP19:%.]] = bitcast %struct.S.0 [[ARRAYIDX10]] to i8*
	// CHECK9-NEXT: [[TMP20:%.]] = bitcast %struct.S.0 [[TMP17]] to i8*			// CHECK9-NEXT: [[TMP20:%.]] = bitcast %struct.S.0 [[TMP17]] to i8*
	// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP19]], i8* align 4 [[TMP20]], i64 4, i1 false)			// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP19]], i8* align 4 [[TMP20]], i64 4, i1 false), !llvm.access.group !17
	// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK9: omp.body.continue:			// CHECK9: omp.body.continue:
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK9: omp.inner.for.inc:			// CHECK9: omp.inner.for.inc:
	// CHECK9-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !17
	// CHECK9-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP21]], 1			// CHECK9-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP21]], 1
	// CHECK9-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4			// CHECK9-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]]
	// CHECK9: omp.inner.for.end:			// CHECK9: omp.inner.for.end:
	// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK9: omp.loop.exit:			// CHECK9: omp.loop.exit:
	// CHECK9-NEXT: [[TMP22:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK9-NEXT: [[TMP22:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK9-NEXT: [[TMP23:%.]] = load i32, i32 [[TMP22]], align 4			// CHECK9-NEXT: [[TMP23:%.]] = load i32, i32 [[TMP22]], align 4
	// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]])			// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]])
	// CHECK9-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK9-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK9-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0			// CHECK9-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0
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	// CHECK10-NEXT: br label [[COND_END]]			// CHECK10-NEXT: br label [[COND_END]]
	// CHECK10: cond.end:			// CHECK10: cond.end:
	// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ]			// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ]
	// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK10-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK10-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK10-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4			// CHECK10-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK10: omp.inner.for.cond:			// CHECK10: omp.inner.for.cond:
	// CHECK10-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK10-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK10-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5
	// CHECK10-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]]			// CHECK10-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]]
	// CHECK10-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]			// CHECK10-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]
	// CHECK10: omp.inner.for.cond.cleanup:			// CHECK10: omp.inner.for.cond.cleanup:
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_END:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
	// CHECK10: omp.inner.for.body:			// CHECK10: omp.inner.for.body:
	// CHECK10-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK10-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !5
	// CHECK10-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64			// CHECK10-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64
	// CHECK10-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK10-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5
	// CHECK10-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64			// CHECK10-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
	// CHECK10-NEXT: [[TMP18:%.]] = load %struct.S, %struct.S** [[_TMP7]], align 8			// CHECK10-NEXT: [[TMP18:%.]] = load %struct.S, %struct.S** [[_TMP7]], align 8, !llvm.access.group !5
	// CHECK10-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, [2 x i32], i32, [2 x %struct.S], %struct.S, i32) @.omp_outlined..1 to void (i32, i32, ...)), i64 [[TMP15]], i64 [[TMP17]], [2 x i32] [[VEC4]], i32* [[T_VAR3]], [2 x %struct.S]* [[S_ARR5]], %struct.S* [[TMP18]], i32* [[SVAR8]])			// CHECK10-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, [2 x i32], i32, [2 x %struct.S], %struct.S, i32) @.omp_outlined..1 to void (i32, i32, ...)), i64 [[TMP15]], i64 [[TMP17]], [2 x i32] [[VEC4]], i32* [[T_VAR3]], [2 x %struct.S]* [[S_ARR5]], %struct.S* [[TMP18]], i32* [[SVAR8]]), !llvm.access.group !5
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK10: omp.inner.for.inc:			// CHECK10: omp.inner.for.inc:
	// CHECK10-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK10-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK10-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !5
	// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], [[TMP20]]			// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], [[TMP20]]
	// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]
	// CHECK10: omp.inner.for.end:			// CHECK10: omp.inner.for.end:
	// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK10: omp.loop.exit:			// CHECK10: omp.loop.exit:
	// CHECK10-NEXT: [[TMP21:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK10-NEXT: [[TMP21:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK10-NEXT: [[TMP22:%.]] = load i32, i32 [[TMP21]], align 4			// CHECK10-NEXT: [[TMP22:%.]] = load i32, i32 [[TMP21]], align 4
	// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]])			// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]])
	// CHECK10-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK10-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK10-NEXT: [[TMP24:%.*]] = icmp ne i32 [[TMP23]], 0			// CHECK10-NEXT: [[TMP24:%.*]] = icmp ne i32 [[TMP23]], 0
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	// CHECK10-NEXT: br label [[COND_END]]			// CHECK10-NEXT: br label [[COND_END]]
	// CHECK10: cond.end:			// CHECK10: cond.end:
	// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ]			// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ]
	// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK10-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK10-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK10-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4			// CHECK10-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK10: omp.inner.for.cond:			// CHECK10: omp.inner.for.cond:
	// CHECK10-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK10-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK10-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !9
	// CHECK10-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]			// CHECK10-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
	// CHECK10-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]			// CHECK10-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]
	// CHECK10: omp.inner.for.cond.cleanup:			// CHECK10: omp.inner.for.cond.cleanup:
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_END:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
	// CHECK10: omp.inner.for.body:			// CHECK10: omp.inner.for.body:
	// CHECK10-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1			// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1
	// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9
	// CHECK10-NEXT: [[TMP16:%.]] = load i32, i32 [[T_VAR3]], align 4			// CHECK10-NEXT: [[TMP16:%.]] = load i32, i32 [[T_VAR3]], align 4, !llvm.access.group !9
	// CHECK10-NEXT: [[TMP17:%.]] = load i32, i32 [[I]], align 4			// CHECK10-NEXT: [[TMP17:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !9
	// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64			// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64
	// CHECK10-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC4]], i64 0, i64 [[IDXPROM]]			// CHECK10-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC4]], i64 0, i64 [[IDXPROM]]
	// CHECK10-NEXT: store i32 [[TMP16]], i32* [[ARRAYIDX]], align 4			// CHECK10-NEXT: store i32 [[TMP16]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !9
	// CHECK10-NEXT: [[TMP18:%.]] = load %struct.S, %struct.S** [[_TMP7]], align 8			// CHECK10-NEXT: [[TMP18:%.]] = load %struct.S, %struct.S** [[_TMP7]], align 8, !llvm.access.group !9
	// CHECK10-NEXT: [[TMP19:%.]] = load i32, i32 [[I]], align 4			// CHECK10-NEXT: [[TMP19:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !9
	// CHECK10-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP19]] to i64			// CHECK10-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP19]] to i64
	// CHECK10-NEXT: [[ARRAYIDX11:%.]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S] [[S_ARR5]], i64 0, i64 [[IDXPROM10]]			// CHECK10-NEXT: [[ARRAYIDX11:%.]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S] [[S_ARR5]], i64 0, i64 [[IDXPROM10]]
	// CHECK10-NEXT: [[TMP20:%.]] = bitcast %struct.S [[ARRAYIDX11]] to i8*			// CHECK10-NEXT: [[TMP20:%.]] = bitcast %struct.S [[ARRAYIDX11]] to i8*
	// CHECK10-NEXT: [[TMP21:%.]] = bitcast %struct.S [[TMP18]] to i8*			// CHECK10-NEXT: [[TMP21:%.]] = bitcast %struct.S [[TMP18]] to i8*
	// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i64 4, i1 false)			// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i64 4, i1 false), !llvm.access.group !9
	// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK10: omp.body.continue:			// CHECK10: omp.body.continue:
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK10: omp.inner.for.inc:			// CHECK10: omp.inner.for.inc:
	// CHECK10-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK10-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP22]], 1			// CHECK10-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP22]], 1
	// CHECK10-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4			// CHECK10-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]
	// CHECK10: omp.inner.for.end:			// CHECK10: omp.inner.for.end:
	// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK10: omp.loop.exit:			// CHECK10: omp.loop.exit:
	// CHECK10-NEXT: [[TMP23:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK10-NEXT: [[TMP23:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK10-NEXT: [[TMP24:%.]] = load i32, i32 [[TMP23]], align 4			// CHECK10-NEXT: [[TMP24:%.]] = load i32, i32 [[TMP23]], align 4
	// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]])			// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]])
	// CHECK10-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK10-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK10-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0			// CHECK10-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0
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	// CHECK10-NEXT: br label [[COND_END]]			// CHECK10-NEXT: br label [[COND_END]]
	// CHECK10: cond.end:			// CHECK10: cond.end:
	// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ]			// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ]
	// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK10-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK10-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK10-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4			// CHECK10-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK10: omp.inner.for.cond:			// CHECK10: omp.inner.for.cond:
	// CHECK10-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK10-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK10-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !14
	// CHECK10-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]]			// CHECK10-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]]
	// CHECK10-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]			// CHECK10-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]
	// CHECK10: omp.inner.for.cond.cleanup:			// CHECK10: omp.inner.for.cond.cleanup:
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_END:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
	// CHECK10: omp.inner.for.body:			// CHECK10: omp.inner.for.body:
	// CHECK10-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK10-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !14
	// CHECK10-NEXT: [[TMP14:%.*]] = zext i32 [[TMP13]] to i64			// CHECK10-NEXT: [[TMP14:%.*]] = zext i32 [[TMP13]] to i64
	// CHECK10-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK10-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !14
	// CHECK10-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64			// CHECK10-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64
	// CHECK10-NEXT: [[TMP17:%.]] = load %struct.S.0, %struct.S.0** [[_TMP7]], align 8			// CHECK10-NEXT: [[TMP17:%.]] = load %struct.S.0, %struct.S.0** [[_TMP7]], align 8, !llvm.access.group !14
	// CHECK10-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, [2 x i32], i32, [2 x %struct.S.0], %struct.S.0)* @.omp_outlined..3 to void (i32, i32, ...)), i64 [[TMP14]], i64 [[TMP16]], [2 x i32] [[VEC4]], i32* [[T_VAR3]], [2 x %struct.S.0]* [[S_ARR5]], %struct.S.0* [[TMP17]])			// CHECK10-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, [2 x i32], i32, [2 x %struct.S.0], %struct.S.0)* @.omp_outlined..3 to void (i32, i32, ...)), i64 [[TMP14]], i64 [[TMP16]], [2 x i32] [[VEC4]], i32* [[T_VAR3]], [2 x %struct.S.0]* [[S_ARR5]], %struct.S.0* [[TMP17]]), !llvm.access.group !14
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK10: omp.inner.for.inc:			// CHECK10: omp.inner.for.inc:
	// CHECK10-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK10-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK10-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !14
	// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], [[TMP19]]			// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], [[TMP19]]
	// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]]
	// CHECK10: omp.inner.for.end:			// CHECK10: omp.inner.for.end:
	// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK10: omp.loop.exit:			// CHECK10: omp.loop.exit:
	// CHECK10-NEXT: [[TMP20:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK10-NEXT: [[TMP20:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK10-NEXT: [[TMP21:%.]] = load i32, i32 [[TMP20]], align 4			// CHECK10-NEXT: [[TMP21:%.]] = load i32, i32 [[TMP20]], align 4
	// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP21]])			// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP21]])
	// CHECK10-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK10-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK10-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0			// CHECK10-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0
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	// CHECK10-NEXT: br label [[COND_END]]			// CHECK10-NEXT: br label [[COND_END]]
	// CHECK10: cond.end:			// CHECK10: cond.end:
	// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ]			// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ]
	// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK10-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK10-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK10-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4			// CHECK10-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK10: omp.inner.for.cond:			// CHECK10: omp.inner.for.cond:
	// CHECK10-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !17
	// CHECK10-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK10-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !17
	// CHECK10-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]]			// CHECK10-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]]
	// CHECK10-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]			// CHECK10-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]
	// CHECK10: omp.inner.for.cond.cleanup:			// CHECK10: omp.inner.for.cond.cleanup:
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_END:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
	// CHECK10: omp.inner.for.body:			// CHECK10: omp.inner.for.body:
	// CHECK10-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !17
	// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1			// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1
	// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !17
	// CHECK10-NEXT: [[TMP15:%.]] = load i32, i32 [[T_VAR3]], align 4			// CHECK10-NEXT: [[TMP15:%.]] = load i32, i32 [[T_VAR3]], align 4, !llvm.access.group !17
	// CHECK10-NEXT: [[TMP16:%.]] = load i32, i32 [[I]], align 4			// CHECK10-NEXT: [[TMP16:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !17
	// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64			// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64
	// CHECK10-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC4]], i64 0, i64 [[IDXPROM]]			// CHECK10-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC4]], i64 0, i64 [[IDXPROM]]
	// CHECK10-NEXT: store i32 [[TMP15]], i32* [[ARRAYIDX]], align 4			// CHECK10-NEXT: store i32 [[TMP15]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !17
	// CHECK10-NEXT: [[TMP17:%.]] = load %struct.S.0, %struct.S.0** [[_TMP7]], align 8			// CHECK10-NEXT: [[TMP17:%.]] = load %struct.S.0, %struct.S.0** [[_TMP7]], align 8, !llvm.access.group !17
	// CHECK10-NEXT: [[TMP18:%.]] = load i32, i32 [[I]], align 4			// CHECK10-NEXT: [[TMP18:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !17
	// CHECK10-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP18]] to i64			// CHECK10-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP18]] to i64
	// CHECK10-NEXT: [[ARRAYIDX10:%.]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0] [[S_ARR5]], i64 0, i64 [[IDXPROM9]]			// CHECK10-NEXT: [[ARRAYIDX10:%.]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0] [[S_ARR5]], i64 0, i64 [[IDXPROM9]]
	// CHECK10-NEXT: [[TMP19:%.]] = bitcast %struct.S.0 [[ARRAYIDX10]] to i8*			// CHECK10-NEXT: [[TMP19:%.]] = bitcast %struct.S.0 [[ARRAYIDX10]] to i8*
	// CHECK10-NEXT: [[TMP20:%.]] = bitcast %struct.S.0 [[TMP17]] to i8*			// CHECK10-NEXT: [[TMP20:%.]] = bitcast %struct.S.0 [[TMP17]] to i8*
	// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP19]], i8* align 4 [[TMP20]], i64 4, i1 false)			// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP19]], i8* align 4 [[TMP20]], i64 4, i1 false), !llvm.access.group !17
	// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK10: omp.body.continue:			// CHECK10: omp.body.continue:
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK10: omp.inner.for.inc:			// CHECK10: omp.inner.for.inc:
	// CHECK10-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !17
	// CHECK10-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP21]], 1			// CHECK10-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP21]], 1
	// CHECK10-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4			// CHECK10-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]]
	// CHECK10: omp.inner.for.end:			// CHECK10: omp.inner.for.end:
	// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK10: omp.loop.exit:			// CHECK10: omp.loop.exit:
	// CHECK10-NEXT: [[TMP22:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK10-NEXT: [[TMP22:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK10-NEXT: [[TMP23:%.]] = load i32, i32 [[TMP22]], align 4			// CHECK10-NEXT: [[TMP23:%.]] = load i32, i32 [[TMP22]], align 4
	// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]])			// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]])
	// CHECK10-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK10-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK10-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0			// CHECK10-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0
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	// CHECK11-NEXT: br label [[COND_END]]			// CHECK11-NEXT: br label [[COND_END]]
	// CHECK11: cond.end:			// CHECK11: cond.end:
	// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ]			// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ]
	// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK11-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK11-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK11-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4			// CHECK11-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK11: omp.inner.for.cond:			// CHECK11: omp.inner.for.cond:
	// CHECK11-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK11-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !6
	// CHECK11-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK11-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !6
	// CHECK11-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]]			// CHECK11-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]]
	// CHECK11-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]			// CHECK11-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]
	// CHECK11: omp.inner.for.cond.cleanup:			// CHECK11: omp.inner.for.cond.cleanup:
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_END:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
	// CHECK11: omp.inner.for.body:			// CHECK11: omp.inner.for.body:
	// CHECK11-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK11-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !6
	// CHECK11-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK11-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !6
	// CHECK11-NEXT: [[TMP16:%.]] = load %struct.S, %struct.S** [[_TMP7]], align 4			// CHECK11-NEXT: [[TMP16:%.]] = load %struct.S, %struct.S** [[_TMP7]], align 4, !llvm.access.group !6
	// CHECK11-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32, i32, ...)* bitcast (void (i32, i32, i32, i32, [2 x i32], i32, [2 x %struct.S], %struct.S, i32) @.omp_outlined..1 to void (i32, i32, ...)), i32 [[TMP14]], i32 [[TMP15]], [2 x i32] [[VEC4]], i32* [[T_VAR3]], [2 x %struct.S]* [[S_ARR5]], %struct.S* [[TMP16]], i32* [[SVAR8]])			// CHECK11-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32, i32, ...)* bitcast (void (i32, i32, i32, i32, [2 x i32], i32, [2 x %struct.S], %struct.S, i32) @.omp_outlined..1 to void (i32, i32, ...)), i32 [[TMP14]], i32 [[TMP15]], [2 x i32] [[VEC4]], i32* [[T_VAR3]], [2 x %struct.S]* [[S_ARR5]], %struct.S* [[TMP16]], i32* [[SVAR8]]), !llvm.access.group !6
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK11: omp.inner.for.inc:			// CHECK11: omp.inner.for.inc:
	// CHECK11-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK11-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !6
	// CHECK11-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK11-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !6
	// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP17]], [[TMP18]]			// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP17]], [[TMP18]]
	// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]
	// CHECK11: omp.inner.for.end:			// CHECK11: omp.inner.for.end:
	// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK11: omp.loop.exit:			// CHECK11: omp.loop.exit:
	// CHECK11-NEXT: [[TMP19:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4			// CHECK11-NEXT: [[TMP19:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4
	// CHECK11-NEXT: [[TMP20:%.]] = load i32, i32 [[TMP19]], align 4			// CHECK11-NEXT: [[TMP20:%.]] = load i32, i32 [[TMP19]], align 4
	// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]])			// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]])
	// CHECK11-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK11-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK11-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0			// CHECK11-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0
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	// CHECK11-NEXT: br label [[COND_END]]			// CHECK11-NEXT: br label [[COND_END]]
	// CHECK11: cond.end:			// CHECK11: cond.end:
	// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ]			// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ]
	// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK11-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK11-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK11-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4			// CHECK11-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK11: omp.inner.for.cond:			// CHECK11: omp.inner.for.cond:
	// CHECK11-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK11-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK11-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK11-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !10
	// CHECK11-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]			// CHECK11-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
	// CHECK11-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]			// CHECK11-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]
	// CHECK11: omp.inner.for.cond.cleanup:			// CHECK11: omp.inner.for.cond.cleanup:
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_END:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
	// CHECK11: omp.inner.for.body:			// CHECK11: omp.inner.for.body:
	// CHECK11-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK11-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1			// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1
	// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10
	// CHECK11-NEXT: [[TMP16:%.]] = load i32, i32 [[T_VAR2]], align 4			// CHECK11-NEXT: [[TMP16:%.]] = load i32, i32 [[T_VAR2]], align 4, !llvm.access.group !10
	// CHECK11-NEXT: [[TMP17:%.]] = load i32, i32 [[I]], align 4			// CHECK11-NEXT: [[TMP17:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !10
	// CHECK11-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC3]], i32 0, i32 [[TMP17]]			// CHECK11-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC3]], i32 0, i32 [[TMP17]]
	// CHECK11-NEXT: store i32 [[TMP16]], i32* [[ARRAYIDX]], align 4			// CHECK11-NEXT: store i32 [[TMP16]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !10
	// CHECK11-NEXT: [[TMP18:%.]] = load %struct.S, %struct.S** [[_TMP6]], align 4			// CHECK11-NEXT: [[TMP18:%.]] = load %struct.S, %struct.S** [[_TMP6]], align 4, !llvm.access.group !10
	// CHECK11-NEXT: [[TMP19:%.]] = load i32, i32 [[I]], align 4			// CHECK11-NEXT: [[TMP19:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !10
	// CHECK11-NEXT: [[ARRAYIDX9:%.]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S] [[S_ARR4]], i32 0, i32 [[TMP19]]			// CHECK11-NEXT: [[ARRAYIDX9:%.]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S] [[S_ARR4]], i32 0, i32 [[TMP19]]
	// CHECK11-NEXT: [[TMP20:%.]] = bitcast %struct.S [[ARRAYIDX9]] to i8*			// CHECK11-NEXT: [[TMP20:%.]] = bitcast %struct.S [[ARRAYIDX9]] to i8*
	// CHECK11-NEXT: [[TMP21:%.]] = bitcast %struct.S [[TMP18]] to i8*			// CHECK11-NEXT: [[TMP21:%.]] = bitcast %struct.S [[TMP18]] to i8*
	// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i32 4, i1 false)			// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i32 4, i1 false), !llvm.access.group !10
	// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK11: omp.body.continue:			// CHECK11: omp.body.continue:
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK11: omp.inner.for.inc:			// CHECK11: omp.inner.for.inc:
	// CHECK11-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK11-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK11-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP22]], 1			// CHECK11-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP22]], 1
	// CHECK11-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4			// CHECK11-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]
	// CHECK11: omp.inner.for.end:			// CHECK11: omp.inner.for.end:
	// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK11: omp.loop.exit:			// CHECK11: omp.loop.exit:
	// CHECK11-NEXT: [[TMP23:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4			// CHECK11-NEXT: [[TMP23:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4
	// CHECK11-NEXT: [[TMP24:%.]] = load i32, i32 [[TMP23]], align 4			// CHECK11-NEXT: [[TMP24:%.]] = load i32, i32 [[TMP23]], align 4
	// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]])			// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]])
	// CHECK11-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK11-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK11-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0			// CHECK11-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0
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	// CHECK11-NEXT: br label [[COND_END]]			// CHECK11-NEXT: br label [[COND_END]]
	// CHECK11: cond.end:			// CHECK11: cond.end:
	// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ]			// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ]
	// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK11-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK11-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK11-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4			// CHECK11-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK11: omp.inner.for.cond:			// CHECK11: omp.inner.for.cond:
	// CHECK11-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK11-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK11-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK11-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15
	// CHECK11-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]]			// CHECK11-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]]
	// CHECK11-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]			// CHECK11-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]
	// CHECK11: omp.inner.for.cond.cleanup:			// CHECK11: omp.inner.for.cond.cleanup:
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_END:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
	// CHECK11: omp.inner.for.body:			// CHECK11: omp.inner.for.body:
	// CHECK11-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK11-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !15
	// CHECK11-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK11-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15
	// CHECK11-NEXT: [[TMP15:%.]] = load %struct.S.0, %struct.S.0** [[_TMP7]], align 4			// CHECK11-NEXT: [[TMP15:%.]] = load %struct.S.0, %struct.S.0** [[_TMP7]], align 4, !llvm.access.group !15
	// CHECK11-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32, i32, ...)* bitcast (void (i32, i32, i32, i32, [2 x i32], i32, [2 x %struct.S.0], %struct.S.0)* @.omp_outlined..3 to void (i32, i32, ...)), i32 [[TMP13]], i32 [[TMP14]], [2 x i32] [[VEC4]], i32* [[T_VAR3]], [2 x %struct.S.0]* [[S_ARR5]], %struct.S.0* [[TMP15]])			// CHECK11-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32, i32, ...)* bitcast (void (i32, i32, i32, i32, [2 x i32], i32, [2 x %struct.S.0], %struct.S.0)* @.omp_outlined..3 to void (i32, i32, ...)), i32 [[TMP13]], i32 [[TMP14]], [2 x i32] [[VEC4]], i32* [[T_VAR3]], [2 x %struct.S.0]* [[S_ARR5]], %struct.S.0* [[TMP15]]), !llvm.access.group !15
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK11: omp.inner.for.inc:			// CHECK11: omp.inner.for.inc:
	// CHECK11-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK11-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK11-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK11-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !15
	// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP16]], [[TMP17]]			// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP16]], [[TMP17]]
	// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]]
	// CHECK11: omp.inner.for.end:			// CHECK11: omp.inner.for.end:
	// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK11: omp.loop.exit:			// CHECK11: omp.loop.exit:
	// CHECK11-NEXT: [[TMP18:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4			// CHECK11-NEXT: [[TMP18:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4
	// CHECK11-NEXT: [[TMP19:%.]] = load i32, i32 [[TMP18]], align 4			// CHECK11-NEXT: [[TMP19:%.]] = load i32, i32 [[TMP18]], align 4
	// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP19]])			// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP19]])
	// CHECK11-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK11-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK11-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0			// CHECK11-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0
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	// CHECK11-NEXT: br label [[COND_END]]			// CHECK11-NEXT: br label [[COND_END]]
	// CHECK11: cond.end:			// CHECK11: cond.end:
	// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ]			// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ]
	// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK11-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK11-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK11-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4			// CHECK11-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK11: omp.inner.for.cond:			// CHECK11: omp.inner.for.cond:
	// CHECK11-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK11-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK11-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK11-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !18
	// CHECK11-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]]			// CHECK11-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]]
	// CHECK11-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]			// CHECK11-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]
	// CHECK11: omp.inner.for.cond.cleanup:			// CHECK11: omp.inner.for.cond.cleanup:
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_END:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
	// CHECK11: omp.inner.for.body:			// CHECK11: omp.inner.for.body:
	// CHECK11-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK11-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1			// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1
	// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !18
	// CHECK11-NEXT: [[TMP15:%.]] = load i32, i32 [[T_VAR2]], align 4			// CHECK11-NEXT: [[TMP15:%.]] = load i32, i32 [[T_VAR2]], align 4, !llvm.access.group !18
	// CHECK11-NEXT: [[TMP16:%.]] = load i32, i32 [[I]], align 4			// CHECK11-NEXT: [[TMP16:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !18
	// CHECK11-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC3]], i32 0, i32 [[TMP16]]			// CHECK11-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC3]], i32 0, i32 [[TMP16]]
	// CHECK11-NEXT: store i32 [[TMP15]], i32* [[ARRAYIDX]], align 4			// CHECK11-NEXT: store i32 [[TMP15]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !18
	// CHECK11-NEXT: [[TMP17:%.]] = load %struct.S.0, %struct.S.0** [[_TMP6]], align 4			// CHECK11-NEXT: [[TMP17:%.]] = load %struct.S.0, %struct.S.0** [[_TMP6]], align 4, !llvm.access.group !18
	// CHECK11-NEXT: [[TMP18:%.]] = load i32, i32 [[I]], align 4			// CHECK11-NEXT: [[TMP18:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !18
	// CHECK11-NEXT: [[ARRAYIDX8:%.]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0] [[S_ARR4]], i32 0, i32 [[TMP18]]			// CHECK11-NEXT: [[ARRAYIDX8:%.]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0] [[S_ARR4]], i32 0, i32 [[TMP18]]
	// CHECK11-NEXT: [[TMP19:%.]] = bitcast %struct.S.0 [[ARRAYIDX8]] to i8*			// CHECK11-NEXT: [[TMP19:%.]] = bitcast %struct.S.0 [[ARRAYIDX8]] to i8*
	// CHECK11-NEXT: [[TMP20:%.]] = bitcast %struct.S.0 [[TMP17]] to i8*			// CHECK11-NEXT: [[TMP20:%.]] = bitcast %struct.S.0 [[TMP17]] to i8*
	// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP19]], i8* align 4 [[TMP20]], i32 4, i1 false)			// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP19]], i8* align 4 [[TMP20]], i32 4, i1 false), !llvm.access.group !18
	// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK11: omp.body.continue:			// CHECK11: omp.body.continue:
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK11: omp.inner.for.inc:			// CHECK11: omp.inner.for.inc:
	// CHECK11-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK11-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK11-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP21]], 1			// CHECK11-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP21]], 1
	// CHECK11-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4			// CHECK11-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]
	// CHECK11: omp.inner.for.end:			// CHECK11: omp.inner.for.end:
	// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK11: omp.loop.exit:			// CHECK11: omp.loop.exit:
	// CHECK11-NEXT: [[TMP22:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4			// CHECK11-NEXT: [[TMP22:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4
	// CHECK11-NEXT: [[TMP23:%.]] = load i32, i32 [[TMP22]], align 4			// CHECK11-NEXT: [[TMP23:%.]] = load i32, i32 [[TMP22]], align 4
	// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]])			// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]])
	// CHECK11-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK11-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK11-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0			// CHECK11-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0
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	// CHECK12-NEXT: br label [[COND_END]]			// CHECK12-NEXT: br label [[COND_END]]
	// CHECK12: cond.end:			// CHECK12: cond.end:
	// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ]			// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ]
	// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK12-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK12-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK12-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4			// CHECK12-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK12: omp.inner.for.cond:			// CHECK12: omp.inner.for.cond:
	// CHECK12-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK12-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !6
	// CHECK12-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK12-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !6
	// CHECK12-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]]			// CHECK12-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]]
	// CHECK12-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]			// CHECK12-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]
	// CHECK12: omp.inner.for.cond.cleanup:			// CHECK12: omp.inner.for.cond.cleanup:
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_END:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
	// CHECK12: omp.inner.for.body:			// CHECK12: omp.inner.for.body:
	// CHECK12-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK12-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !6
	// CHECK12-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK12-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !6
	// CHECK12-NEXT: [[TMP16:%.]] = load %struct.S, %struct.S** [[_TMP7]], align 4			// CHECK12-NEXT: [[TMP16:%.]] = load %struct.S, %struct.S** [[_TMP7]], align 4, !llvm.access.group !6
	// CHECK12-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32, i32, ...)* bitcast (void (i32, i32, i32, i32, [2 x i32], i32, [2 x %struct.S], %struct.S, i32) @.omp_outlined..1 to void (i32, i32, ...)), i32 [[TMP14]], i32 [[TMP15]], [2 x i32] [[VEC4]], i32* [[T_VAR3]], [2 x %struct.S]* [[S_ARR5]], %struct.S* [[TMP16]], i32* [[SVAR8]])			// CHECK12-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32, i32, ...)* bitcast (void (i32, i32, i32, i32, [2 x i32], i32, [2 x %struct.S], %struct.S, i32) @.omp_outlined..1 to void (i32, i32, ...)), i32 [[TMP14]], i32 [[TMP15]], [2 x i32] [[VEC4]], i32* [[T_VAR3]], [2 x %struct.S]* [[S_ARR5]], %struct.S* [[TMP16]], i32* [[SVAR8]]), !llvm.access.group !6
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK12: omp.inner.for.inc:			// CHECK12: omp.inner.for.inc:
	// CHECK12-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK12-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !6
	// CHECK12-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK12-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !6
	// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP17]], [[TMP18]]			// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP17]], [[TMP18]]
	// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]
	// CHECK12: omp.inner.for.end:			// CHECK12: omp.inner.for.end:
	// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK12: omp.loop.exit:			// CHECK12: omp.loop.exit:
	// CHECK12-NEXT: [[TMP19:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4			// CHECK12-NEXT: [[TMP19:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4
	// CHECK12-NEXT: [[TMP20:%.]] = load i32, i32 [[TMP19]], align 4			// CHECK12-NEXT: [[TMP20:%.]] = load i32, i32 [[TMP19]], align 4
	// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]])			// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]])
	// CHECK12-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK12-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK12-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0			// CHECK12-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0
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	// CHECK12-NEXT: br label [[COND_END]]			// CHECK12-NEXT: br label [[COND_END]]
	// CHECK12: cond.end:			// CHECK12: cond.end:
	// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ]			// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ]
	// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK12-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK12-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK12-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4			// CHECK12-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK12: omp.inner.for.cond:			// CHECK12: omp.inner.for.cond:
	// CHECK12-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK12-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK12-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK12-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !10
	// CHECK12-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]			// CHECK12-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
	// CHECK12-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]			// CHECK12-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]
	// CHECK12: omp.inner.for.cond.cleanup:			// CHECK12: omp.inner.for.cond.cleanup:
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_END:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
	// CHECK12: omp.inner.for.body:			// CHECK12: omp.inner.for.body:
	// CHECK12-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK12-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1			// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1
	// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10
	// CHECK12-NEXT: [[TMP16:%.]] = load i32, i32 [[T_VAR2]], align 4			// CHECK12-NEXT: [[TMP16:%.]] = load i32, i32 [[T_VAR2]], align 4, !llvm.access.group !10
	// CHECK12-NEXT: [[TMP17:%.]] = load i32, i32 [[I]], align 4			// CHECK12-NEXT: [[TMP17:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !10
	// CHECK12-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC3]], i32 0, i32 [[TMP17]]			// CHECK12-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC3]], i32 0, i32 [[TMP17]]
	// CHECK12-NEXT: store i32 [[TMP16]], i32* [[ARRAYIDX]], align 4			// CHECK12-NEXT: store i32 [[TMP16]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !10
	// CHECK12-NEXT: [[TMP18:%.]] = load %struct.S, %struct.S** [[_TMP6]], align 4			// CHECK12-NEXT: [[TMP18:%.]] = load %struct.S, %struct.S** [[_TMP6]], align 4, !llvm.access.group !10
	// CHECK12-NEXT: [[TMP19:%.]] = load i32, i32 [[I]], align 4			// CHECK12-NEXT: [[TMP19:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !10
	// CHECK12-NEXT: [[ARRAYIDX9:%.]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S] [[S_ARR4]], i32 0, i32 [[TMP19]]			// CHECK12-NEXT: [[ARRAYIDX9:%.]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S] [[S_ARR4]], i32 0, i32 [[TMP19]]
	// CHECK12-NEXT: [[TMP20:%.]] = bitcast %struct.S [[ARRAYIDX9]] to i8*			// CHECK12-NEXT: [[TMP20:%.]] = bitcast %struct.S [[ARRAYIDX9]] to i8*
	// CHECK12-NEXT: [[TMP21:%.]] = bitcast %struct.S [[TMP18]] to i8*			// CHECK12-NEXT: [[TMP21:%.]] = bitcast %struct.S [[TMP18]] to i8*
	// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i32 4, i1 false)			// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i32 4, i1 false), !llvm.access.group !10
	// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK12: omp.body.continue:			// CHECK12: omp.body.continue:
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK12: omp.inner.for.inc:			// CHECK12: omp.inner.for.inc:
	// CHECK12-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK12-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK12-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP22]], 1			// CHECK12-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP22]], 1
	// CHECK12-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4			// CHECK12-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]
	// CHECK12: omp.inner.for.end:			// CHECK12: omp.inner.for.end:
	// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK12: omp.loop.exit:			// CHECK12: omp.loop.exit:
	// CHECK12-NEXT: [[TMP23:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4			// CHECK12-NEXT: [[TMP23:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4
	// CHECK12-NEXT: [[TMP24:%.]] = load i32, i32 [[TMP23]], align 4			// CHECK12-NEXT: [[TMP24:%.]] = load i32, i32 [[TMP23]], align 4
	// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]])			// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]])
	// CHECK12-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK12-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK12-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0			// CHECK12-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0
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	// CHECK12-NEXT: br label [[COND_END]]			// CHECK12-NEXT: br label [[COND_END]]
	// CHECK12: cond.end:			// CHECK12: cond.end:
	// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ]			// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ]
	// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK12-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK12-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK12-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4			// CHECK12-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK12: omp.inner.for.cond:			// CHECK12: omp.inner.for.cond:
	// CHECK12-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK12-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK12-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK12-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15
	// CHECK12-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]]			// CHECK12-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]]
	// CHECK12-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]			// CHECK12-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]
	// CHECK12: omp.inner.for.cond.cleanup:			// CHECK12: omp.inner.for.cond.cleanup:
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_END:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
	// CHECK12: omp.inner.for.body:			// CHECK12: omp.inner.for.body:
	// CHECK12-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK12-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !15
	// CHECK12-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK12-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15
	// CHECK12-NEXT: [[TMP15:%.]] = load %struct.S.0, %struct.S.0** [[_TMP7]], align 4			// CHECK12-NEXT: [[TMP15:%.]] = load %struct.S.0, %struct.S.0** [[_TMP7]], align 4, !llvm.access.group !15
	// CHECK12-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32, i32, ...)* bitcast (void (i32, i32, i32, i32, [2 x i32], i32, [2 x %struct.S.0], %struct.S.0)* @.omp_outlined..3 to void (i32, i32, ...)), i32 [[TMP13]], i32 [[TMP14]], [2 x i32] [[VEC4]], i32* [[T_VAR3]], [2 x %struct.S.0]* [[S_ARR5]], %struct.S.0* [[TMP15]])			// CHECK12-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32, i32, ...)* bitcast (void (i32, i32, i32, i32, [2 x i32], i32, [2 x %struct.S.0], %struct.S.0)* @.omp_outlined..3 to void (i32, i32, ...)), i32 [[TMP13]], i32 [[TMP14]], [2 x i32] [[VEC4]], i32* [[T_VAR3]], [2 x %struct.S.0]* [[S_ARR5]], %struct.S.0* [[TMP15]]), !llvm.access.group !15
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK12: omp.inner.for.inc:			// CHECK12: omp.inner.for.inc:
	// CHECK12-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK12-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK12-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK12-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !15
	// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP16]], [[TMP17]]			// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP16]], [[TMP17]]
	// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]]
	// CHECK12: omp.inner.for.end:			// CHECK12: omp.inner.for.end:
	// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK12: omp.loop.exit:			// CHECK12: omp.loop.exit:
	// CHECK12-NEXT: [[TMP18:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4			// CHECK12-NEXT: [[TMP18:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4
	// CHECK12-NEXT: [[TMP19:%.]] = load i32, i32 [[TMP18]], align 4			// CHECK12-NEXT: [[TMP19:%.]] = load i32, i32 [[TMP18]], align 4
	// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP19]])			// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP19]])
	// CHECK12-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK12-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK12-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0			// CHECK12-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0
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	// CHECK12-NEXT: br label [[COND_END]]			// CHECK12-NEXT: br label [[COND_END]]
	// CHECK12: cond.end:			// CHECK12: cond.end:
	// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ]			// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ]
	// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK12-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK12-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK12-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4			// CHECK12-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK12: omp.inner.for.cond:			// CHECK12: omp.inner.for.cond:
	// CHECK12-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK12-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK12-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK12-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !18
	// CHECK12-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]]			// CHECK12-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]]
	// CHECK12-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]			// CHECK12-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]
	// CHECK12: omp.inner.for.cond.cleanup:			// CHECK12: omp.inner.for.cond.cleanup:
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_END:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
	// CHECK12: omp.inner.for.body:			// CHECK12: omp.inner.for.body:
	// CHECK12-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK12-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1			// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1
	// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !18
	// CHECK12-NEXT: [[TMP15:%.]] = load i32, i32 [[T_VAR2]], align 4			// CHECK12-NEXT: [[TMP15:%.]] = load i32, i32 [[T_VAR2]], align 4, !llvm.access.group !18
	// CHECK12-NEXT: [[TMP16:%.]] = load i32, i32 [[I]], align 4			// CHECK12-NEXT: [[TMP16:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !18
	// CHECK12-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC3]], i32 0, i32 [[TMP16]]			// CHECK12-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC3]], i32 0, i32 [[TMP16]]
	// CHECK12-NEXT: store i32 [[TMP15]], i32* [[ARRAYIDX]], align 4			// CHECK12-NEXT: store i32 [[TMP15]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !18
	// CHECK12-NEXT: [[TMP17:%.]] = load %struct.S.0, %struct.S.0** [[_TMP6]], align 4			// CHECK12-NEXT: [[TMP17:%.]] = load %struct.S.0, %struct.S.0** [[_TMP6]], align 4, !llvm.access.group !18
	// CHECK12-NEXT: [[TMP18:%.]] = load i32, i32 [[I]], align 4			// CHECK12-NEXT: [[TMP18:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !18
	// CHECK12-NEXT: [[ARRAYIDX8:%.]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0] [[S_ARR4]], i32 0, i32 [[TMP18]]			// CHECK12-NEXT: [[ARRAYIDX8:%.]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0] [[S_ARR4]], i32 0, i32 [[TMP18]]
	// CHECK12-NEXT: [[TMP19:%.]] = bitcast %struct.S.0 [[ARRAYIDX8]] to i8*			// CHECK12-NEXT: [[TMP19:%.]] = bitcast %struct.S.0 [[ARRAYIDX8]] to i8*
	// CHECK12-NEXT: [[TMP20:%.]] = bitcast %struct.S.0 [[TMP17]] to i8*			// CHECK12-NEXT: [[TMP20:%.]] = bitcast %struct.S.0 [[TMP17]] to i8*
	// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP19]], i8* align 4 [[TMP20]], i32 4, i1 false)			// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP19]], i8* align 4 [[TMP20]], i32 4, i1 false), !llvm.access.group !18
	// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK12: omp.body.continue:			// CHECK12: omp.body.continue:
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK12: omp.inner.for.inc:			// CHECK12: omp.inner.for.inc:
	// CHECK12-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK12-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK12-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP21]], 1			// CHECK12-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP21]], 1
	// CHECK12-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4			// CHECK12-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]
	// CHECK12: omp.inner.for.end:			// CHECK12: omp.inner.for.end:
	// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK12: omp.loop.exit:			// CHECK12: omp.loop.exit:
	// CHECK12-NEXT: [[TMP22:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4			// CHECK12-NEXT: [[TMP22:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4
	// CHECK12-NEXT: [[TMP23:%.]] = load i32, i32 [[TMP22]], align 4			// CHECK12-NEXT: [[TMP23:%.]] = load i32, i32 [[TMP22]], align 4
	// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]])			// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]])
	// CHECK12-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK12-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK12-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0			// CHECK12-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0
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clang/test/OpenMP/distribute_parallel_for_simd_num_threads_codegen.cpp

This file is larger than 256 KB, so syntax highlighting is disabled by default.

	Show First 20 Lines • Show All 237 Lines • ▼ Show 20 Lines
	// CHECK1-NEXT: br label [[COND_END]]			// CHECK1-NEXT: br label [[COND_END]]
	// CHECK1: cond.end:			// CHECK1: cond.end:
	// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]			// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
	// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK1-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK1-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK1: omp.inner.for.cond:			// CHECK1: omp.inner.for.cond:
	// CHECK1-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !9
	// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK1: omp.inner.for.body:			// CHECK1: omp.inner.for.body:
	// CHECK1-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 2)			// CHECK1-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 2), !llvm.access.group !9
	// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !9
	// CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64			// CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
	// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !9
	// CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK1-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..1 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]])			// CHECK1-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..1 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !9
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK1: omp.inner.for.inc:			// CHECK1: omp.inner.for.inc:
	// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !9
	// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]			// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
	// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]
	// CHECK1: omp.inner.for.end:			// CHECK1: omp.inner.for.end:
	// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK1: omp.loop.exit:			// CHECK1: omp.loop.exit:
	// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])			// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
	// CHECK1-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK1-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK1-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0			// CHECK1-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
	// CHECK1-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK1-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK1: .omp.final.then:			// CHECK1: .omp.final.then:
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	// CHECK1-NEXT: br label [[COND_END]]			// CHECK1-NEXT: br label [[COND_END]]
	// CHECK1: cond.end:			// CHECK1: cond.end:
	// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]			// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
	// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK1-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK1: omp.inner.for.cond:			// CHECK1: omp.inner.for.cond:
	// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK1-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK1-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !13
	// CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK1: omp.inner.for.body:			// CHECK1: omp.inner.for.body:
	// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !13
	// CHECK1-NEXT: invoke void @_Z3foov()			// CHECK1-NEXT: invoke void @_Z3foov()
	// CHECK1-NEXT: to label [[INVOKE_CONT:%.]] unwind label [[TERMINATE_LPAD:%.]]			// CHECK1-NEXT: to label [[INVOKE_CONT:%.]] unwind label [[TERMINATE_LPAD:%.]], !llvm.access.group !13
	// CHECK1: invoke.cont:			// CHECK1: invoke.cont:
	// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK1: omp.body.continue:			// CHECK1: omp.body.continue:
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK1: omp.inner.for.inc:			// CHECK1: omp.inner.for.inc:
	// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]]
	// CHECK1: omp.inner.for.end:			// CHECK1: omp.inner.for.end:
	// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK1: omp.loop.exit:			// CHECK1: omp.loop.exit:
	// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])			// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
	// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK1-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK1-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK1-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK1-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK1: .omp.final.then:			// CHECK1: .omp.final.then:
	// CHECK1-NEXT: store i32 100, i32* [[I]], align 4			// CHECK1-NEXT: store i32 100, i32* [[I]], align 4
	// CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]]			// CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]]
	// CHECK1: .omp.final.done:			// CHECK1: .omp.final.done:
	// CHECK1-NEXT: ret void			// CHECK1-NEXT: ret void
	// CHECK1: terminate.lpad:			// CHECK1: terminate.lpad:
	// CHECK1-NEXT: [[TMP13:%.]] = landingpad { i8, i32 }			// CHECK1-NEXT: [[TMP13:%.]] = landingpad { i8, i32 }
	// CHECK1-NEXT: catch i8* null			// CHECK1-NEXT: catch i8* null
	// CHECK1-NEXT: [[TMP14:%.]] = extractvalue { i8, i32 } [[TMP13]], 0			// CHECK1-NEXT: [[TMP14:%.]] = extractvalue { i8, i32 } [[TMP13]], 0
	// CHECK1-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10:[0-9]+]]			// CHECK1-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10:[0-9]+]], !llvm.access.group !13
	// CHECK1-NEXT: unreachable			// CHECK1-NEXT: unreachable
	//			//
	//			//
	// CHECK1-LABEL: define {{[^@]+}}@__clang_call_terminate			// CHECK1-LABEL: define {{[^@]+}}@__clang_call_terminate
	// CHECK1-SAME: (i8* [[TMP0:%.*]]) #[[ATTR5:[0-9]+]] comdat {			// CHECK1-SAME: (i8* [[TMP0:%.*]]) #[[ATTR5:[0-9]+]] comdat {
	// CHECK1-NEXT: [[TMP2:%.]] = call i8 @__cxa_begin_catch(i8* [[TMP0]]) #[[ATTR6]]			// CHECK1-NEXT: [[TMP2:%.]] = call i8 @__cxa_begin_catch(i8* [[TMP0]]) #[[ATTR6]]
	// CHECK1-NEXT: call void @_ZSt9terminatev() #[[ATTR10]]			// CHECK1-NEXT: call void @_ZSt9terminatev() #[[ATTR10]]
	// CHECK1-NEXT: unreachable			// CHECK1-NEXT: unreachable
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	// CHECK1-NEXT: br label [[COND_END]]			// CHECK1-NEXT: br label [[COND_END]]
	// CHECK1: cond.end:			// CHECK1: cond.end:
	// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]			// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
	// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK1-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK1-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK1-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK1: omp.inner.for.cond:			// CHECK1: omp.inner.for.cond:
	// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !18
	// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK1: omp.inner.for.body:			// CHECK1: omp.inner.for.body:
	// CHECK1-NEXT: [[TMP8:%.]] = load i8, i8 [[TMP0]], align 1			// CHECK1-NEXT: [[TMP8:%.]] = load i8, i8 [[TMP0]], align 1, !llvm.access.group !18
	// CHECK1-NEXT: [[TMP9:%.*]] = sext i8 [[TMP8]] to i32			// CHECK1-NEXT: [[TMP9:%.*]] = sext i8 [[TMP8]] to i32
	// CHECK1-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP2]], i32 [[TMP9]])			// CHECK1-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP2]], i32 [[TMP9]]), !llvm.access.group !18
	// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !18
	// CHECK1-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64			// CHECK1-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
	// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !18
	// CHECK1-NEXT: [[TMP13:%.*]] = zext i32 [[TMP12]] to i64			// CHECK1-NEXT: [[TMP13:%.*]] = zext i32 [[TMP12]] to i64
	// CHECK1-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..3 to void (i32, i32, ...)*), i64 [[TMP11]], i64 [[TMP13]])			// CHECK1-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..3 to void (i32, i32, ...)*), i64 [[TMP11]], i64 [[TMP13]]), !llvm.access.group !18
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK1: omp.inner.for.inc:			// CHECK1: omp.inner.for.inc:
	// CHECK1-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK1-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK1-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !18
	// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP14]], [[TMP15]]			// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP14]], [[TMP15]]
	// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]
	// CHECK1: omp.inner.for.end:			// CHECK1: omp.inner.for.end:
	// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK1: omp.loop.exit:			// CHECK1: omp.loop.exit:
	// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])			// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
	// CHECK1-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK1-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK1-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0			// CHECK1-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0
	// CHECK1-NEXT: br i1 [[TMP17]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK1-NEXT: br i1 [[TMP17]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK1: .omp.final.then:			// CHECK1: .omp.final.then:
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	// CHECK1-NEXT: br label [[COND_END]]			// CHECK1-NEXT: br label [[COND_END]]
	// CHECK1: cond.end:			// CHECK1: cond.end:
	// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]			// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
	// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK1-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK1: omp.inner.for.cond:			// CHECK1: omp.inner.for.cond:
	// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !21
	// CHECK1-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK1-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !21
	// CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK1: omp.inner.for.body:			// CHECK1: omp.inner.for.body:
	// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !21
	// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !21
	// CHECK1-NEXT: invoke void @_Z3foov()			// CHECK1-NEXT: invoke void @_Z3foov()
	// CHECK1-NEXT: to label [[INVOKE_CONT:%.]] unwind label [[TERMINATE_LPAD:%.]]			// CHECK1-NEXT: to label [[INVOKE_CONT:%.]] unwind label [[TERMINATE_LPAD:%.]], !llvm.access.group !21
	// CHECK1: invoke.cont:			// CHECK1: invoke.cont:
	// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK1: omp.body.continue:			// CHECK1: omp.body.continue:
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK1: omp.inner.for.inc:			// CHECK1: omp.inner.for.inc:
	// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !21
	// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]]
	// CHECK1: omp.inner.for.end:			// CHECK1: omp.inner.for.end:
	// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK1: omp.loop.exit:			// CHECK1: omp.loop.exit:
	// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])			// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
	// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK1-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK1-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK1-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK1-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK1: .omp.final.then:			// CHECK1: .omp.final.then:
	// CHECK1-NEXT: store i32 100, i32* [[I]], align 4			// CHECK1-NEXT: store i32 100, i32* [[I]], align 4
	// CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]]			// CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]]
	// CHECK1: .omp.final.done:			// CHECK1: .omp.final.done:
	// CHECK1-NEXT: ret void			// CHECK1-NEXT: ret void
	// CHECK1: terminate.lpad:			// CHECK1: terminate.lpad:
	// CHECK1-NEXT: [[TMP13:%.]] = landingpad { i8, i32 }			// CHECK1-NEXT: [[TMP13:%.]] = landingpad { i8, i32 }
	// CHECK1-NEXT: catch i8* null			// CHECK1-NEXT: catch i8* null
	// CHECK1-NEXT: [[TMP14:%.]] = extractvalue { i8, i32 } [[TMP13]], 0			// CHECK1-NEXT: [[TMP14:%.]] = extractvalue { i8, i32 } [[TMP13]], 0
	// CHECK1-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]]			// CHECK1-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]], !llvm.access.group !21
	// CHECK1-NEXT: unreachable			// CHECK1-NEXT: unreachable
	//			//
	//			//
	// CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIcLi5EEiv			// CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIcLi5EEiv
	// CHECK1-SAME: () #[[ATTR7:[0-9]+]] comdat {			// CHECK1-SAME: () #[[ATTR7:[0-9]+]] comdat {
	// CHECK1-NEXT: entry:			// CHECK1-NEXT: entry:
	// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4			// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
	// CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32, align 4			// CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
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	// CHECK1-NEXT: br label [[COND_END]]			// CHECK1-NEXT: br label [[COND_END]]
	// CHECK1: cond.end:			// CHECK1: cond.end:
	// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]			// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
	// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK1-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK1-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK1: omp.inner.for.cond:			// CHECK1: omp.inner.for.cond:
	// CHECK1-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !24
	// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !24
	// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK1: omp.inner.for.body:			// CHECK1: omp.inner.for.body:
	// CHECK1-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 5)			// CHECK1-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 5), !llvm.access.group !24
	// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !24
	// CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64			// CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
	// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !24
	// CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK1-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..5 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]])			// CHECK1-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..5 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !24
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK1: omp.inner.for.inc:			// CHECK1: omp.inner.for.inc:
	// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !24
	// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !24
	// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]			// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
	// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]]
	// CHECK1: omp.inner.for.end:			// CHECK1: omp.inner.for.end:
	// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK1: omp.loop.exit:			// CHECK1: omp.loop.exit:
	// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])			// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
	// CHECK1-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK1-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK1-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0			// CHECK1-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
	// CHECK1-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK1-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK1: .omp.final.then:			// CHECK1: .omp.final.then:
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	// CHECK1-NEXT: br label [[COND_END]]			// CHECK1-NEXT: br label [[COND_END]]
	// CHECK1: cond.end:			// CHECK1: cond.end:
	// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]			// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
	// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK1-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK1: omp.inner.for.cond:			// CHECK1: omp.inner.for.cond:
	// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !27
	// CHECK1-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK1-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !27
	// CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK1: omp.inner.for.body:			// CHECK1: omp.inner.for.body:
	// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !27
	// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !27
	// CHECK1-NEXT: invoke void @_Z3foov()			// CHECK1-NEXT: invoke void @_Z3foov()
	// CHECK1-NEXT: to label [[INVOKE_CONT:%.]] unwind label [[TERMINATE_LPAD:%.]]			// CHECK1-NEXT: to label [[INVOKE_CONT:%.]] unwind label [[TERMINATE_LPAD:%.]], !llvm.access.group !27
	// CHECK1: invoke.cont:			// CHECK1: invoke.cont:
	// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK1: omp.body.continue:			// CHECK1: omp.body.continue:
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK1: omp.inner.for.inc:			// CHECK1: omp.inner.for.inc:
	// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !27
	// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]]
	// CHECK1: omp.inner.for.end:			// CHECK1: omp.inner.for.end:
	// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK1: omp.loop.exit:			// CHECK1: omp.loop.exit:
	// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])			// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
	// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK1-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK1-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK1-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK1-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK1: .omp.final.then:			// CHECK1: .omp.final.then:
	// CHECK1-NEXT: store i32 100, i32* [[I]], align 4			// CHECK1-NEXT: store i32 100, i32* [[I]], align 4
	// CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]]			// CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]]
	// CHECK1: .omp.final.done:			// CHECK1: .omp.final.done:
	// CHECK1-NEXT: ret void			// CHECK1-NEXT: ret void
	// CHECK1: terminate.lpad:			// CHECK1: terminate.lpad:
	// CHECK1-NEXT: [[TMP13:%.]] = landingpad { i8, i32 }			// CHECK1-NEXT: [[TMP13:%.]] = landingpad { i8, i32 }
	// CHECK1-NEXT: catch i8* null			// CHECK1-NEXT: catch i8* null
	// CHECK1-NEXT: [[TMP14:%.]] = extractvalue { i8, i32 } [[TMP13]], 0			// CHECK1-NEXT: [[TMP14:%.]] = extractvalue { i8, i32 } [[TMP13]], 0
	// CHECK1-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]]			// CHECK1-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]], !llvm.access.group !27
	// CHECK1-NEXT: unreachable			// CHECK1-NEXT: unreachable
	//			//
	//			//
	// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l57			// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l57
	// CHECK1-SAME: () #[[ATTR3]] {			// CHECK1-SAME: () #[[ATTR3]] {
	// CHECK1-NEXT: entry:			// CHECK1-NEXT: entry:
	// CHECK1-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32, i32, ...)* bitcast (void (i32, i32)* @.omp_outlined..6 to void (i32, i32, ...)*))			// CHECK1-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32, i32, ...)* bitcast (void (i32, i32)* @.omp_outlined..6 to void (i32, i32, ...)*))
	// CHECK1-NEXT: ret void			// CHECK1-NEXT: ret void
	Show All 30 Lines
	// CHECK1-NEXT: br label [[COND_END]]			// CHECK1-NEXT: br label [[COND_END]]
	// CHECK1: cond.end:			// CHECK1: cond.end:
	// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]			// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
	// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK1-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK1-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK1: omp.inner.for.cond:			// CHECK1: omp.inner.for.cond:
	// CHECK1-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !30
	// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !30
	// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK1: omp.inner.for.body:			// CHECK1: omp.inner.for.body:
	// CHECK1-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 23)			// CHECK1-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 23), !llvm.access.group !30
	// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !30
	// CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64			// CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
	// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !30
	// CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK1-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..7 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]])			// CHECK1-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..7 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !30
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK1: omp.inner.for.inc:			// CHECK1: omp.inner.for.inc:
	// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !30
	// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !30
	// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]			// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
	// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP31:![0-9]+]]
	// CHECK1: omp.inner.for.end:			// CHECK1: omp.inner.for.end:
	// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK1: omp.loop.exit:			// CHECK1: omp.loop.exit:
	// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])			// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
	// CHECK1-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK1-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK1-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0			// CHECK1-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
	// CHECK1-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK1-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK1: .omp.final.then:			// CHECK1: .omp.final.then:
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	// CHECK1-NEXT: br label [[COND_END]]			// CHECK1-NEXT: br label [[COND_END]]
	// CHECK1: cond.end:			// CHECK1: cond.end:
	// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]			// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
	// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK1-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK1: omp.inner.for.cond:			// CHECK1: omp.inner.for.cond:
	// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !33
	// CHECK1-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK1-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !33
	// CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK1: omp.inner.for.body:			// CHECK1: omp.inner.for.body:
	// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !33
	// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !33
	// CHECK1-NEXT: invoke void @_Z3foov()			// CHECK1-NEXT: invoke void @_Z3foov()
	// CHECK1-NEXT: to label [[INVOKE_CONT:%.]] unwind label [[TERMINATE_LPAD:%.]]			// CHECK1-NEXT: to label [[INVOKE_CONT:%.]] unwind label [[TERMINATE_LPAD:%.]], !llvm.access.group !33
	// CHECK1: invoke.cont:			// CHECK1: invoke.cont:
	// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK1: omp.body.continue:			// CHECK1: omp.body.continue:
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK1: omp.inner.for.inc:			// CHECK1: omp.inner.for.inc:
	// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !33
	// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP34:![0-9]+]]
	// CHECK1: omp.inner.for.end:			// CHECK1: omp.inner.for.end:
	// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK1: omp.loop.exit:			// CHECK1: omp.loop.exit:
	// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])			// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
	// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK1-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK1-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK1-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK1-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK1: .omp.final.then:			// CHECK1: .omp.final.then:
	// CHECK1-NEXT: store i32 100, i32* [[I]], align 4			// CHECK1-NEXT: store i32 100, i32* [[I]], align 4
	// CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]]			// CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]]
	// CHECK1: .omp.final.done:			// CHECK1: .omp.final.done:
	// CHECK1-NEXT: ret void			// CHECK1-NEXT: ret void
	// CHECK1: terminate.lpad:			// CHECK1: terminate.lpad:
	// CHECK1-NEXT: [[TMP13:%.]] = landingpad { i8, i32 }			// CHECK1-NEXT: [[TMP13:%.]] = landingpad { i8, i32 }
	// CHECK1-NEXT: catch i8* null			// CHECK1-NEXT: catch i8* null
	// CHECK1-NEXT: [[TMP14:%.]] = extractvalue { i8, i32 } [[TMP13]], 0			// CHECK1-NEXT: [[TMP14:%.]] = extractvalue { i8, i32 } [[TMP13]], 0
	// CHECK1-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]]			// CHECK1-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]], !llvm.access.group !33
	// CHECK1-NEXT: unreachable			// CHECK1-NEXT: unreachable
	//			//
	//			//
	// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l52			// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l52
	// CHECK1-SAME: () #[[ATTR3]] {			// CHECK1-SAME: () #[[ATTR3]] {
	// CHECK1-NEXT: entry:			// CHECK1-NEXT: entry:
	// CHECK1-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32, i32, ...)* bitcast (void (i32, i32)* @.omp_outlined..8 to void (i32, i32, ...)*))			// CHECK1-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32, i32, ...)* bitcast (void (i32, i32)* @.omp_outlined..8 to void (i32, i32, ...)*))
	// CHECK1-NEXT: ret void			// CHECK1-NEXT: ret void
	Show All 30 Lines
	// CHECK1-NEXT: br label [[COND_END]]			// CHECK1-NEXT: br label [[COND_END]]
	// CHECK1: cond.end:			// CHECK1: cond.end:
	// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]			// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
	// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK1-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK1-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK1: omp.inner.for.cond:			// CHECK1: omp.inner.for.cond:
	// CHECK1-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !36
	// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !36
	// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK1: omp.inner.for.body:			// CHECK1: omp.inner.for.body:
	// CHECK1-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 1)			// CHECK1-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 1), !llvm.access.group !36
	// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !36
	// CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64			// CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
	// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !36
	// CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK1-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..9 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]])			// CHECK1-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..9 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !36
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK1: omp.inner.for.inc:			// CHECK1: omp.inner.for.inc:
	// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !36
	// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !36
	// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]			// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
	// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP37:![0-9]+]]
	// CHECK1: omp.inner.for.end:			// CHECK1: omp.inner.for.end:
	// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK1: omp.loop.exit:			// CHECK1: omp.loop.exit:
	// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])			// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
	// CHECK1-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK1-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK1-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0			// CHECK1-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
	// CHECK1-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK1-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK1: .omp.final.then:			// CHECK1: .omp.final.then:
	▲ Show 20 Lines • Show All 44 Lines • ▼ Show 20 Lines
	// CHECK1-NEXT: br label [[COND_END]]			// CHECK1-NEXT: br label [[COND_END]]
	// CHECK1: cond.end:			// CHECK1: cond.end:
	// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]			// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
	// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK1-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK1: omp.inner.for.cond:			// CHECK1: omp.inner.for.cond:
	// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !39
	// CHECK1-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK1-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !39
	// CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK1: omp.inner.for.body:			// CHECK1: omp.inner.for.body:
	// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !39
	// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !39
	// CHECK1-NEXT: invoke void @_Z3foov()			// CHECK1-NEXT: invoke void @_Z3foov()
	// CHECK1-NEXT: to label [[INVOKE_CONT:%.]] unwind label [[TERMINATE_LPAD:%.]]			// CHECK1-NEXT: to label [[INVOKE_CONT:%.]] unwind label [[TERMINATE_LPAD:%.]], !llvm.access.group !39
	// CHECK1: invoke.cont:			// CHECK1: invoke.cont:
	// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK1: omp.body.continue:			// CHECK1: omp.body.continue:
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK1: omp.inner.for.inc:			// CHECK1: omp.inner.for.inc:
	// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !39
	// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP40:![0-9]+]]
	// CHECK1: omp.inner.for.end:			// CHECK1: omp.inner.for.end:
	// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK1: omp.loop.exit:			// CHECK1: omp.loop.exit:
	// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])			// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
	// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK1-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK1-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK1-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK1-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK1: .omp.final.then:			// CHECK1: .omp.final.then:
	// CHECK1-NEXT: store i32 100, i32* [[I]], align 4			// CHECK1-NEXT: store i32 100, i32* [[I]], align 4
	// CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]]			// CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]]
	// CHECK1: .omp.final.done:			// CHECK1: .omp.final.done:
	// CHECK1-NEXT: ret void			// CHECK1-NEXT: ret void
	// CHECK1: terminate.lpad:			// CHECK1: terminate.lpad:
	// CHECK1-NEXT: [[TMP13:%.]] = landingpad { i8, i32 }			// CHECK1-NEXT: [[TMP13:%.]] = landingpad { i8, i32 }
	// CHECK1-NEXT: catch i8* null			// CHECK1-NEXT: catch i8* null
	// CHECK1-NEXT: [[TMP14:%.]] = extractvalue { i8, i32 } [[TMP13]], 0			// CHECK1-NEXT: [[TMP14:%.]] = extractvalue { i8, i32 } [[TMP13]], 0
	// CHECK1-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]]			// CHECK1-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]], !llvm.access.group !39
	// CHECK1-NEXT: unreachable			// CHECK1-NEXT: unreachable
	//			//
	//			//
	// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l57			// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l57
	// CHECK1-SAME: () #[[ATTR3]] {			// CHECK1-SAME: () #[[ATTR3]] {
	// CHECK1-NEXT: entry:			// CHECK1-NEXT: entry:
	// CHECK1-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32, i32, ...)* bitcast (void (i32, i32)* @.omp_outlined..10 to void (i32, i32, ...)*))			// CHECK1-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32, i32, ...)* bitcast (void (i32, i32)* @.omp_outlined..10 to void (i32, i32, ...)*))
	// CHECK1-NEXT: ret void			// CHECK1-NEXT: ret void
	Show All 33 Lines
	// CHECK1-NEXT: br label [[COND_END]]			// CHECK1-NEXT: br label [[COND_END]]
	// CHECK1: cond.end:			// CHECK1: cond.end:
	// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]			// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
	// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK1-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK1-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK1: omp.inner.for.cond:			// CHECK1: omp.inner.for.cond:
	// CHECK1-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !42
	// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !42
	// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK1: omp.inner.for.body:			// CHECK1: omp.inner.for.body:
	// CHECK1-NEXT: invoke void @_ZN1SC1El(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]], i64 23)			// CHECK1-NEXT: invoke void @_ZN1SC1El(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]], i64 23)
	// CHECK1-NEXT: to label [[INVOKE_CONT:%.]] unwind label [[TERMINATE_LPAD:%.]]			// CHECK1-NEXT: to label [[INVOKE_CONT:%.]] unwind label [[TERMINATE_LPAD:%.]], !llvm.access.group !42
	// CHECK1: invoke.cont:			// CHECK1: invoke.cont:
	// CHECK1-NEXT: [[CALL:%.]] = invoke signext i8 @_ZN1ScvcEv(%struct.S nonnull align 8 dereferenceable(24) [[REF_TMP]])			// CHECK1-NEXT: [[CALL:%.]] = invoke signext i8 @_ZN1ScvcEv(%struct.S nonnull align 8 dereferenceable(24) [[REF_TMP]])
	// CHECK1-NEXT: to label [[INVOKE_CONT2:%.]] unwind label [[LPAD:%.]]			// CHECK1-NEXT: to label [[INVOKE_CONT2:%.]] unwind label [[LPAD:%.]], !llvm.access.group !42
	// CHECK1: invoke.cont2:			// CHECK1: invoke.cont2:
	// CHECK1-NEXT: [[TMP7:%.*]] = sext i8 [[CALL]] to i32			// CHECK1-NEXT: [[TMP7:%.*]] = sext i8 [[CALL]] to i32
	// CHECK1-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 [[TMP7]])			// CHECK1-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 [[TMP7]]), !llvm.access.group !42
	// CHECK1-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR6]]			// CHECK1-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR6]], !llvm.access.group !42
	// CHECK1-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK1-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !42
	// CHECK1-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64			// CHECK1-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
	// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !42
	// CHECK1-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64			// CHECK1-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
	// CHECK1-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..11 to void (i32, i32, ...)*), i64 [[TMP9]], i64 [[TMP11]])			// CHECK1-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..11 to void (i32, i32, ...)*), i64 [[TMP9]], i64 [[TMP11]]), !llvm.access.group !42
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK1: omp.inner.for.inc:			// CHECK1: omp.inner.for.inc:
	// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !42
	// CHECK1-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK1-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !42
	// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]			// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]
	// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !42
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP43:![0-9]+]]
	// CHECK1: lpad:			// CHECK1: lpad:
	// CHECK1-NEXT: [[TMP14:%.]] = landingpad { i8, i32 }			// CHECK1-NEXT: [[TMP14:%.]] = landingpad { i8, i32 }
	// CHECK1-NEXT: catch i8* null			// CHECK1-NEXT: catch i8* null
	// CHECK1-NEXT: [[TMP15:%.]] = extractvalue { i8, i32 } [[TMP14]], 0			// CHECK1-NEXT: [[TMP15:%.]] = extractvalue { i8, i32 } [[TMP14]], 0
	// CHECK1-NEXT: store i8* [[TMP15]], i8** [[EXN_SLOT]], align 8			// CHECK1-NEXT: store i8* [[TMP15]], i8** [[EXN_SLOT]], align 8, !llvm.access.group !42
	// CHECK1-NEXT: [[TMP16:%.]] = extractvalue { i8, i32 } [[TMP14]], 1			// CHECK1-NEXT: [[TMP16:%.]] = extractvalue { i8, i32 } [[TMP14]], 1
	// CHECK1-NEXT: store i32 [[TMP16]], i32* [[EHSELECTOR_SLOT]], align 4			// CHECK1-NEXT: store i32 [[TMP16]], i32* [[EHSELECTOR_SLOT]], align 4, !llvm.access.group !42
	// CHECK1-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR6]]			// CHECK1-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR6]], !llvm.access.group !42
	// CHECK1-NEXT: br label [[TERMINATE_HANDLER:%.*]]			// CHECK1-NEXT: br label [[TERMINATE_HANDLER:%.*]]
	// CHECK1: omp.inner.for.end:			// CHECK1: omp.inner.for.end:
	// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK1: omp.loop.exit:			// CHECK1: omp.loop.exit:
	// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])			// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
	// CHECK1-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK1-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK1-NEXT: [[TMP18:%.*]] = icmp ne i32 [[TMP17]], 0			// CHECK1-NEXT: [[TMP18:%.*]] = icmp ne i32 [[TMP17]], 0
	// CHECK1-NEXT: br i1 [[TMP18]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK1-NEXT: br i1 [[TMP18]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK1: .omp.final.then:			// CHECK1: .omp.final.then:
	// CHECK1-NEXT: store i32 100, i32* [[I]], align 4			// CHECK1-NEXT: store i32 100, i32* [[I]], align 4
	// CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]]			// CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]]
	// CHECK1: .omp.final.done:			// CHECK1: .omp.final.done:
	// CHECK1-NEXT: ret void			// CHECK1-NEXT: ret void
	// CHECK1: terminate.lpad:			// CHECK1: terminate.lpad:
	// CHECK1-NEXT: [[TMP19:%.]] = landingpad { i8, i32 }			// CHECK1-NEXT: [[TMP19:%.]] = landingpad { i8, i32 }
	// CHECK1-NEXT: catch i8* null			// CHECK1-NEXT: catch i8* null
	// CHECK1-NEXT: [[TMP20:%.]] = extractvalue { i8, i32 } [[TMP19]], 0			// CHECK1-NEXT: [[TMP20:%.]] = extractvalue { i8, i32 } [[TMP19]], 0
	// CHECK1-NEXT: call void @__clang_call_terminate(i8* [[TMP20]]) #[[ATTR10]]			// CHECK1-NEXT: call void @__clang_call_terminate(i8* [[TMP20]]) #[[ATTR10]], !llvm.access.group !42
	// CHECK1-NEXT: unreachable			// CHECK1-NEXT: unreachable
	// CHECK1: terminate.handler:			// CHECK1: terminate.handler:
	// CHECK1-NEXT: [[EXN:%.]] = load i8, i8** [[EXN_SLOT]], align 8			// CHECK1-NEXT: [[EXN:%.]] = load i8, i8** [[EXN_SLOT]], align 8, !llvm.access.group !42
	// CHECK1-NEXT: call void @__clang_call_terminate(i8* [[EXN]]) #[[ATTR10]]			// CHECK1-NEXT: call void @__clang_call_terminate(i8* [[EXN]]) #[[ATTR10]], !llvm.access.group !42
	// CHECK1-NEXT: unreachable			// CHECK1-NEXT: unreachable
	//			//
	//			//
	// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..11			// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..11
	// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i64 [[DOTPREVIOUS_LB_:%.]], i64 [[DOTPREVIOUS_UB_:%.]]) #[[ATTR3]] personality i8 bitcast (i32 (...)* @__gxx_personality_v0 to i8*) {			// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i64 [[DOTPREVIOUS_LB_:%.]], i64 [[DOTPREVIOUS_UB_:%.]]) #[[ATTR3]] personality i8 bitcast (i32 (...)* @__gxx_personality_v0 to i8*) {
	// CHECK1-NEXT: entry:			// CHECK1-NEXT: entry:
	// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8			// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8
	// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8			// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8
	Show All 33 Lines
	// CHECK1-NEXT: br label [[COND_END]]			// CHECK1-NEXT: br label [[COND_END]]
	// CHECK1: cond.end:			// CHECK1: cond.end:
	// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]			// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
	// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK1-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK1: omp.inner.for.cond:			// CHECK1: omp.inner.for.cond:
	// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !45
	// CHECK1-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK1-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !45
	// CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK1: omp.inner.for.body:			// CHECK1: omp.inner.for.body:
	// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !45
	// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !45
	// CHECK1-NEXT: invoke void @_Z3foov()			// CHECK1-NEXT: invoke void @_Z3foov()
	// CHECK1-NEXT: to label [[INVOKE_CONT:%.]] unwind label [[TERMINATE_LPAD:%.]]			// CHECK1-NEXT: to label [[INVOKE_CONT:%.]] unwind label [[TERMINATE_LPAD:%.]], !llvm.access.group !45
	// CHECK1: invoke.cont:			// CHECK1: invoke.cont:
	// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK1: omp.body.continue:			// CHECK1: omp.body.continue:
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK1: omp.inner.for.inc:			// CHECK1: omp.inner.for.inc:
	// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !45
	// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !45
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP46:![0-9]+]]
	// CHECK1: omp.inner.for.end:			// CHECK1: omp.inner.for.end:
	// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK1: omp.loop.exit:			// CHECK1: omp.loop.exit:
	// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])			// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
	// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK1-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK1-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK1-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK1-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK1: .omp.final.then:			// CHECK1: .omp.final.then:
	// CHECK1-NEXT: store i32 100, i32* [[I]], align 4			// CHECK1-NEXT: store i32 100, i32* [[I]], align 4
	// CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]]			// CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]]
	// CHECK1: .omp.final.done:			// CHECK1: .omp.final.done:
	// CHECK1-NEXT: ret void			// CHECK1-NEXT: ret void
	// CHECK1: terminate.lpad:			// CHECK1: terminate.lpad:
	// CHECK1-NEXT: [[TMP13:%.]] = landingpad { i8, i32 }			// CHECK1-NEXT: [[TMP13:%.]] = landingpad { i8, i32 }
	// CHECK1-NEXT: catch i8* null			// CHECK1-NEXT: catch i8* null
	// CHECK1-NEXT: [[TMP14:%.]] = extractvalue { i8, i32 } [[TMP13]], 0			// CHECK1-NEXT: [[TMP14:%.]] = extractvalue { i8, i32 } [[TMP13]], 0
	// CHECK1-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]]			// CHECK1-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]], !llvm.access.group !45
	// CHECK1-NEXT: unreachable			// CHECK1-NEXT: unreachable
	//			//
	//			//
	// CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg			// CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
	// CHECK1-SAME: () #[[ATTR9:[0-9]+]] {			// CHECK1-SAME: () #[[ATTR9:[0-9]+]] {
	// CHECK1-NEXT: entry:			// CHECK1-NEXT: entry:
	// CHECK1-NEXT: call void @__tgt_register_requires(i64 1)			// CHECK1-NEXT: call void @__tgt_register_requires(i64 1)
	// CHECK1-NEXT: ret void			// CHECK1-NEXT: ret void
	▲ Show 20 Lines • Show All 144 Lines • ▼ Show 20 Lines
	// CHECK2-NEXT: br label [[COND_END]]			// CHECK2-NEXT: br label [[COND_END]]
	// CHECK2: cond.end:			// CHECK2: cond.end:
	// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]			// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
	// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK2-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK2-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK2-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK2: omp.inner.for.cond:			// CHECK2: omp.inner.for.cond:
	// CHECK2-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !9
	// CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK2: omp.inner.for.body:			// CHECK2: omp.inner.for.body:
	// CHECK2-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 2)			// CHECK2-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 2), !llvm.access.group !9
	// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !9
	// CHECK2-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64			// CHECK2-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
	// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !9
	// CHECK2-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK2-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK2-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..1 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]])			// CHECK2-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..1 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !9
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK2: omp.inner.for.inc:			// CHECK2: omp.inner.for.inc:
	// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !9
	// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]			// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
	// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]
	// CHECK2: omp.inner.for.end:			// CHECK2: omp.inner.for.end:
	// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK2: omp.loop.exit:			// CHECK2: omp.loop.exit:
	// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])			// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
	// CHECK2-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK2-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK2-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0			// CHECK2-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
	// CHECK2-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK2-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK2: .omp.final.then:			// CHECK2: .omp.final.then:
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	// CHECK2-NEXT: br label [[COND_END]]			// CHECK2-NEXT: br label [[COND_END]]
	// CHECK2: cond.end:			// CHECK2: cond.end:
	// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]			// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
	// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK2-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK2: omp.inner.for.cond:			// CHECK2: omp.inner.for.cond:
	// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK2-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK2-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !13
	// CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK2: omp.inner.for.body:			// CHECK2: omp.inner.for.body:
	// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !13
	// CHECK2-NEXT: invoke void @_Z3foov()			// CHECK2-NEXT: invoke void @_Z3foov()
	// CHECK2-NEXT: to label [[INVOKE_CONT:%.]] unwind label [[TERMINATE_LPAD:%.]]			// CHECK2-NEXT: to label [[INVOKE_CONT:%.]] unwind label [[TERMINATE_LPAD:%.]], !llvm.access.group !13
	// CHECK2: invoke.cont:			// CHECK2: invoke.cont:
	// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK2: omp.body.continue:			// CHECK2: omp.body.continue:
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK2: omp.inner.for.inc:			// CHECK2: omp.inner.for.inc:
	// CHECK2-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]]
	// CHECK2: omp.inner.for.end:			// CHECK2: omp.inner.for.end:
	// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK2: omp.loop.exit:			// CHECK2: omp.loop.exit:
	// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])			// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
	// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK2-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK2-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK2-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK2-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK2: .omp.final.then:			// CHECK2: .omp.final.then:
	// CHECK2-NEXT: store i32 100, i32* [[I]], align 4			// CHECK2-NEXT: store i32 100, i32* [[I]], align 4
	// CHECK2-NEXT: br label [[DOTOMP_FINAL_DONE]]			// CHECK2-NEXT: br label [[DOTOMP_FINAL_DONE]]
	// CHECK2: .omp.final.done:			// CHECK2: .omp.final.done:
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	// CHECK2: terminate.lpad:			// CHECK2: terminate.lpad:
	// CHECK2-NEXT: [[TMP13:%.]] = landingpad { i8, i32 }			// CHECK2-NEXT: [[TMP13:%.]] = landingpad { i8, i32 }
	// CHECK2-NEXT: catch i8* null			// CHECK2-NEXT: catch i8* null
	// CHECK2-NEXT: [[TMP14:%.]] = extractvalue { i8, i32 } [[TMP13]], 0			// CHECK2-NEXT: [[TMP14:%.]] = extractvalue { i8, i32 } [[TMP13]], 0
	// CHECK2-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10:[0-9]+]]			// CHECK2-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10:[0-9]+]], !llvm.access.group !13
	// CHECK2-NEXT: unreachable			// CHECK2-NEXT: unreachable
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@__clang_call_terminate			// CHECK2-LABEL: define {{[^@]+}}@__clang_call_terminate
	// CHECK2-SAME: (i8* [[TMP0:%.*]]) #[[ATTR5:[0-9]+]] comdat {			// CHECK2-SAME: (i8* [[TMP0:%.*]]) #[[ATTR5:[0-9]+]] comdat {
	// CHECK2-NEXT: [[TMP2:%.]] = call i8 @__cxa_begin_catch(i8* [[TMP0]]) #[[ATTR6]]			// CHECK2-NEXT: [[TMP2:%.]] = call i8 @__cxa_begin_catch(i8* [[TMP0]]) #[[ATTR6]]
	// CHECK2-NEXT: call void @_ZSt9terminatev() #[[ATTR10]]			// CHECK2-NEXT: call void @_ZSt9terminatev() #[[ATTR10]]
	// CHECK2-NEXT: unreachable			// CHECK2-NEXT: unreachable
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	// CHECK2-NEXT: br label [[COND_END]]			// CHECK2-NEXT: br label [[COND_END]]
	// CHECK2: cond.end:			// CHECK2: cond.end:
	// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]			// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
	// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK2-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK2-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK2-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK2: omp.inner.for.cond:			// CHECK2: omp.inner.for.cond:
	// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !18
	// CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK2: omp.inner.for.body:			// CHECK2: omp.inner.for.body:
	// CHECK2-NEXT: [[TMP8:%.]] = load i8, i8 [[TMP0]], align 1			// CHECK2-NEXT: [[TMP8:%.]] = load i8, i8 [[TMP0]], align 1, !llvm.access.group !18
	// CHECK2-NEXT: [[TMP9:%.*]] = sext i8 [[TMP8]] to i32			// CHECK2-NEXT: [[TMP9:%.*]] = sext i8 [[TMP8]] to i32
	// CHECK2-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP2]], i32 [[TMP9]])			// CHECK2-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP2]], i32 [[TMP9]]), !llvm.access.group !18
	// CHECK2-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK2-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !18
	// CHECK2-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64			// CHECK2-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
	// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !18
	// CHECK2-NEXT: [[TMP13:%.*]] = zext i32 [[TMP12]] to i64			// CHECK2-NEXT: [[TMP13:%.*]] = zext i32 [[TMP12]] to i64
	// CHECK2-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..3 to void (i32, i32, ...)*), i64 [[TMP11]], i64 [[TMP13]])			// CHECK2-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..3 to void (i32, i32, ...)*), i64 [[TMP11]], i64 [[TMP13]]), !llvm.access.group !18
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK2: omp.inner.for.inc:			// CHECK2: omp.inner.for.inc:
	// CHECK2-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK2-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK2-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !18
	// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP14]], [[TMP15]]			// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP14]], [[TMP15]]
	// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]
	// CHECK2: omp.inner.for.end:			// CHECK2: omp.inner.for.end:
	// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK2: omp.loop.exit:			// CHECK2: omp.loop.exit:
	// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])			// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
	// CHECK2-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK2-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK2-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0			// CHECK2-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0
	// CHECK2-NEXT: br i1 [[TMP17]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK2-NEXT: br i1 [[TMP17]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK2: .omp.final.then:			// CHECK2: .omp.final.then:
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	// CHECK2-NEXT: br label [[COND_END]]			// CHECK2-NEXT: br label [[COND_END]]
	// CHECK2: cond.end:			// CHECK2: cond.end:
	// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]			// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
	// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK2-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK2: omp.inner.for.cond:			// CHECK2: omp.inner.for.cond:
	// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !21
	// CHECK2-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK2-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !21
	// CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK2: omp.inner.for.body:			// CHECK2: omp.inner.for.body:
	// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !21
	// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !21
	// CHECK2-NEXT: invoke void @_Z3foov()			// CHECK2-NEXT: invoke void @_Z3foov()
	// CHECK2-NEXT: to label [[INVOKE_CONT:%.]] unwind label [[TERMINATE_LPAD:%.]]			// CHECK2-NEXT: to label [[INVOKE_CONT:%.]] unwind label [[TERMINATE_LPAD:%.]], !llvm.access.group !21
	// CHECK2: invoke.cont:			// CHECK2: invoke.cont:
	// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK2: omp.body.continue:			// CHECK2: omp.body.continue:
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK2: omp.inner.for.inc:			// CHECK2: omp.inner.for.inc:
	// CHECK2-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !21
	// CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]]
	// CHECK2: omp.inner.for.end:			// CHECK2: omp.inner.for.end:
	// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK2: omp.loop.exit:			// CHECK2: omp.loop.exit:
	// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])			// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
	// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK2-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK2-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK2-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK2-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK2: .omp.final.then:			// CHECK2: .omp.final.then:
	// CHECK2-NEXT: store i32 100, i32* [[I]], align 4			// CHECK2-NEXT: store i32 100, i32* [[I]], align 4
	// CHECK2-NEXT: br label [[DOTOMP_FINAL_DONE]]			// CHECK2-NEXT: br label [[DOTOMP_FINAL_DONE]]
	// CHECK2: .omp.final.done:			// CHECK2: .omp.final.done:
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	// CHECK2: terminate.lpad:			// CHECK2: terminate.lpad:
	// CHECK2-NEXT: [[TMP13:%.]] = landingpad { i8, i32 }			// CHECK2-NEXT: [[TMP13:%.]] = landingpad { i8, i32 }
	// CHECK2-NEXT: catch i8* null			// CHECK2-NEXT: catch i8* null
	// CHECK2-NEXT: [[TMP14:%.]] = extractvalue { i8, i32 } [[TMP13]], 0			// CHECK2-NEXT: [[TMP14:%.]] = extractvalue { i8, i32 } [[TMP13]], 0
	// CHECK2-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]]			// CHECK2-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]], !llvm.access.group !21
	// CHECK2-NEXT: unreachable			// CHECK2-NEXT: unreachable
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@_Z5tmainIcLi5EEiv			// CHECK2-LABEL: define {{[^@]+}}@_Z5tmainIcLi5EEiv
	// CHECK2-SAME: () #[[ATTR7:[0-9]+]] comdat {			// CHECK2-SAME: () #[[ATTR7:[0-9]+]] comdat {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	// CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4			// CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4
	// CHECK2-NEXT: [[_TMP1:%.*]] = alloca i32, align 4			// CHECK2-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
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	// CHECK2-NEXT: br label [[COND_END]]			// CHECK2-NEXT: br label [[COND_END]]
	// CHECK2: cond.end:			// CHECK2: cond.end:
	// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]			// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
	// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK2-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK2-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK2-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK2: omp.inner.for.cond:			// CHECK2: omp.inner.for.cond:
	// CHECK2-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !24
	// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !24
	// CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK2: omp.inner.for.body:			// CHECK2: omp.inner.for.body:
	// CHECK2-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 5)			// CHECK2-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 5), !llvm.access.group !24
	// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !24
	// CHECK2-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64			// CHECK2-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
	// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !24
	// CHECK2-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK2-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK2-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..5 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]])			// CHECK2-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..5 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !24
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK2: omp.inner.for.inc:			// CHECK2: omp.inner.for.inc:
	// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !24
	// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !24
	// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]			// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
	// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]]
	// CHECK2: omp.inner.for.end:			// CHECK2: omp.inner.for.end:
	// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK2: omp.loop.exit:			// CHECK2: omp.loop.exit:
	// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])			// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
	// CHECK2-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK2-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK2-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0			// CHECK2-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
	// CHECK2-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK2-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK2: .omp.final.then:			// CHECK2: .omp.final.then:
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	// CHECK2-NEXT: br label [[COND_END]]			// CHECK2-NEXT: br label [[COND_END]]
	// CHECK2: cond.end:			// CHECK2: cond.end:
	// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]			// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
	// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK2-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK2: omp.inner.for.cond:			// CHECK2: omp.inner.for.cond:
	// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !27
	// CHECK2-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK2-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !27
	// CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK2: omp.inner.for.body:			// CHECK2: omp.inner.for.body:
	// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !27
	// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !27
	// CHECK2-NEXT: invoke void @_Z3foov()			// CHECK2-NEXT: invoke void @_Z3foov()
	// CHECK2-NEXT: to label [[INVOKE_CONT:%.]] unwind label [[TERMINATE_LPAD:%.]]			// CHECK2-NEXT: to label [[INVOKE_CONT:%.]] unwind label [[TERMINATE_LPAD:%.]], !llvm.access.group !27
	// CHECK2: invoke.cont:			// CHECK2: invoke.cont:
	// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK2: omp.body.continue:			// CHECK2: omp.body.continue:
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK2: omp.inner.for.inc:			// CHECK2: omp.inner.for.inc:
	// CHECK2-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !27
	// CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]]
	// CHECK2: omp.inner.for.end:			// CHECK2: omp.inner.for.end:
	// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK2: omp.loop.exit:			// CHECK2: omp.loop.exit:
	// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])			// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
	// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK2-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK2-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK2-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK2-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK2: .omp.final.then:			// CHECK2: .omp.final.then:
	// CHECK2-NEXT: store i32 100, i32* [[I]], align 4			// CHECK2-NEXT: store i32 100, i32* [[I]], align 4
	// CHECK2-NEXT: br label [[DOTOMP_FINAL_DONE]]			// CHECK2-NEXT: br label [[DOTOMP_FINAL_DONE]]
	// CHECK2: .omp.final.done:			// CHECK2: .omp.final.done:
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	// CHECK2: terminate.lpad:			// CHECK2: terminate.lpad:
	// CHECK2-NEXT: [[TMP13:%.]] = landingpad { i8, i32 }			// CHECK2-NEXT: [[TMP13:%.]] = landingpad { i8, i32 }
	// CHECK2-NEXT: catch i8* null			// CHECK2-NEXT: catch i8* null
	// CHECK2-NEXT: [[TMP14:%.]] = extractvalue { i8, i32 } [[TMP13]], 0			// CHECK2-NEXT: [[TMP14:%.]] = extractvalue { i8, i32 } [[TMP13]], 0
	// CHECK2-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]]			// CHECK2-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]], !llvm.access.group !27
	// CHECK2-NEXT: unreachable			// CHECK2-NEXT: unreachable
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l57			// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l57
	// CHECK2-SAME: () #[[ATTR3]] {			// CHECK2-SAME: () #[[ATTR3]] {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	// CHECK2-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32, i32, ...)* bitcast (void (i32, i32)* @.omp_outlined..6 to void (i32, i32, ...)*))			// CHECK2-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32, i32, ...)* bitcast (void (i32, i32)* @.omp_outlined..6 to void (i32, i32, ...)*))
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	Show All 30 Lines
	// CHECK2-NEXT: br label [[COND_END]]			// CHECK2-NEXT: br label [[COND_END]]
	// CHECK2: cond.end:			// CHECK2: cond.end:
	// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]			// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
	// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK2-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK2-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK2-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK2: omp.inner.for.cond:			// CHECK2: omp.inner.for.cond:
	// CHECK2-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !30
	// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !30
	// CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK2: omp.inner.for.body:			// CHECK2: omp.inner.for.body:
	// CHECK2-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 23)			// CHECK2-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 23), !llvm.access.group !30
	// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !30
	// CHECK2-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64			// CHECK2-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
	// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !30
	// CHECK2-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK2-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK2-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..7 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]])			// CHECK2-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..7 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !30
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK2: omp.inner.for.inc:			// CHECK2: omp.inner.for.inc:
	// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !30
	// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !30
	// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]			// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
	// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP31:![0-9]+]]
	// CHECK2: omp.inner.for.end:			// CHECK2: omp.inner.for.end:
	// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK2: omp.loop.exit:			// CHECK2: omp.loop.exit:
	// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])			// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
	// CHECK2-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK2-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK2-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0			// CHECK2-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
	// CHECK2-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK2-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK2: .omp.final.then:			// CHECK2: .omp.final.then:
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	// CHECK2-NEXT: br label [[COND_END]]			// CHECK2-NEXT: br label [[COND_END]]
	// CHECK2: cond.end:			// CHECK2: cond.end:
	// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]			// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
	// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK2-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK2: omp.inner.for.cond:			// CHECK2: omp.inner.for.cond:
	// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !33
	// CHECK2-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK2-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !33
	// CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK2: omp.inner.for.body:			// CHECK2: omp.inner.for.body:
	// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !33
	// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !33
	// CHECK2-NEXT: invoke void @_Z3foov()			// CHECK2-NEXT: invoke void @_Z3foov()
	// CHECK2-NEXT: to label [[INVOKE_CONT:%.]] unwind label [[TERMINATE_LPAD:%.]]			// CHECK2-NEXT: to label [[INVOKE_CONT:%.]] unwind label [[TERMINATE_LPAD:%.]], !llvm.access.group !33
	// CHECK2: invoke.cont:			// CHECK2: invoke.cont:
	// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK2: omp.body.continue:			// CHECK2: omp.body.continue:
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK2: omp.inner.for.inc:			// CHECK2: omp.inner.for.inc:
	// CHECK2-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !33
	// CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP34:![0-9]+]]
	// CHECK2: omp.inner.for.end:			// CHECK2: omp.inner.for.end:
	// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK2: omp.loop.exit:			// CHECK2: omp.loop.exit:
	// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])			// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
	// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK2-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK2-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK2-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK2-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK2: .omp.final.then:			// CHECK2: .omp.final.then:
	// CHECK2-NEXT: store i32 100, i32* [[I]], align 4			// CHECK2-NEXT: store i32 100, i32* [[I]], align 4
	// CHECK2-NEXT: br label [[DOTOMP_FINAL_DONE]]			// CHECK2-NEXT: br label [[DOTOMP_FINAL_DONE]]
	// CHECK2: .omp.final.done:			// CHECK2: .omp.final.done:
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	// CHECK2: terminate.lpad:			// CHECK2: terminate.lpad:
	// CHECK2-NEXT: [[TMP13:%.]] = landingpad { i8, i32 }			// CHECK2-NEXT: [[TMP13:%.]] = landingpad { i8, i32 }
	// CHECK2-NEXT: catch i8* null			// CHECK2-NEXT: catch i8* null
	// CHECK2-NEXT: [[TMP14:%.]] = extractvalue { i8, i32 } [[TMP13]], 0			// CHECK2-NEXT: [[TMP14:%.]] = extractvalue { i8, i32 } [[TMP13]], 0
	// CHECK2-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]]			// CHECK2-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]], !llvm.access.group !33
	// CHECK2-NEXT: unreachable			// CHECK2-NEXT: unreachable
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l52			// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l52
	// CHECK2-SAME: () #[[ATTR3]] {			// CHECK2-SAME: () #[[ATTR3]] {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	// CHECK2-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32, i32, ...)* bitcast (void (i32, i32)* @.omp_outlined..8 to void (i32, i32, ...)*))			// CHECK2-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32, i32, ...)* bitcast (void (i32, i32)* @.omp_outlined..8 to void (i32, i32, ...)*))
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	Show All 30 Lines
	// CHECK2-NEXT: br label [[COND_END]]			// CHECK2-NEXT: br label [[COND_END]]
	// CHECK2: cond.end:			// CHECK2: cond.end:
	// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]			// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
	// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK2-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK2-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK2-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK2: omp.inner.for.cond:			// CHECK2: omp.inner.for.cond:
	// CHECK2-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !36
	// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !36
	// CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK2: omp.inner.for.body:			// CHECK2: omp.inner.for.body:
	// CHECK2-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 1)			// CHECK2-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 1), !llvm.access.group !36
	// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !36
	// CHECK2-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64			// CHECK2-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
	// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !36
	// CHECK2-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK2-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK2-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..9 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]])			// CHECK2-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..9 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !36
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK2: omp.inner.for.inc:			// CHECK2: omp.inner.for.inc:
	// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !36
	// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !36
	// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]			// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
	// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP37:![0-9]+]]
	// CHECK2: omp.inner.for.end:			// CHECK2: omp.inner.for.end:
	// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK2: omp.loop.exit:			// CHECK2: omp.loop.exit:
	// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])			// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
	// CHECK2-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK2-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK2-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0			// CHECK2-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
	// CHECK2-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK2-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK2: .omp.final.then:			// CHECK2: .omp.final.then:
	▲ Show 20 Lines • Show All 44 Lines • ▼ Show 20 Lines
	// CHECK2-NEXT: br label [[COND_END]]			// CHECK2-NEXT: br label [[COND_END]]
	// CHECK2: cond.end:			// CHECK2: cond.end:
	// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]			// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
	// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK2-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK2: omp.inner.for.cond:			// CHECK2: omp.inner.for.cond:
	// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !39
	// CHECK2-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK2-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !39
	// CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK2: omp.inner.for.body:			// CHECK2: omp.inner.for.body:
	// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !39
	// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !39
	// CHECK2-NEXT: invoke void @_Z3foov()			// CHECK2-NEXT: invoke void @_Z3foov()
	// CHECK2-NEXT: to label [[INVOKE_CONT:%.]] unwind label [[TERMINATE_LPAD:%.]]			// CHECK2-NEXT: to label [[INVOKE_CONT:%.]] unwind label [[TERMINATE_LPAD:%.]], !llvm.access.group !39
	// CHECK2: invoke.cont:			// CHECK2: invoke.cont:
	// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK2: omp.body.continue:			// CHECK2: omp.body.continue:
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK2: omp.inner.for.inc:			// CHECK2: omp.inner.for.inc:
	// CHECK2-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !39
	// CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP40:![0-9]+]]
	// CHECK2: omp.inner.for.end:			// CHECK2: omp.inner.for.end:
	// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK2: omp.loop.exit:			// CHECK2: omp.loop.exit:
	// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])			// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
	// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK2-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK2-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK2-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK2-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK2: .omp.final.then:			// CHECK2: .omp.final.then:
	// CHECK2-NEXT: store i32 100, i32* [[I]], align 4			// CHECK2-NEXT: store i32 100, i32* [[I]], align 4
	// CHECK2-NEXT: br label [[DOTOMP_FINAL_DONE]]			// CHECK2-NEXT: br label [[DOTOMP_FINAL_DONE]]
	// CHECK2: .omp.final.done:			// CHECK2: .omp.final.done:
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	// CHECK2: terminate.lpad:			// CHECK2: terminate.lpad:
	// CHECK2-NEXT: [[TMP13:%.]] = landingpad { i8, i32 }			// CHECK2-NEXT: [[TMP13:%.]] = landingpad { i8, i32 }
	// CHECK2-NEXT: catch i8* null			// CHECK2-NEXT: catch i8* null
	// CHECK2-NEXT: [[TMP14:%.]] = extractvalue { i8, i32 } [[TMP13]], 0			// CHECK2-NEXT: [[TMP14:%.]] = extractvalue { i8, i32 } [[TMP13]], 0
	// CHECK2-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]]			// CHECK2-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]], !llvm.access.group !39
	// CHECK2-NEXT: unreachable			// CHECK2-NEXT: unreachable
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l57			// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l57
	// CHECK2-SAME: () #[[ATTR3]] {			// CHECK2-SAME: () #[[ATTR3]] {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	// CHECK2-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32, i32, ...)* bitcast (void (i32, i32)* @.omp_outlined..10 to void (i32, i32, ...)*))			// CHECK2-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32, i32, ...)* bitcast (void (i32, i32)* @.omp_outlined..10 to void (i32, i32, ...)*))
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	Show All 33 Lines
	// CHECK2-NEXT: br label [[COND_END]]			// CHECK2-NEXT: br label [[COND_END]]
	// CHECK2: cond.end:			// CHECK2: cond.end:
	// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]			// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
	// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK2-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK2-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK2-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK2: omp.inner.for.cond:			// CHECK2: omp.inner.for.cond:
	// CHECK2-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !42
	// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !42
	// CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK2: omp.inner.for.body:			// CHECK2: omp.inner.for.body:
	// CHECK2-NEXT: invoke void @_ZN1SC1El(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]], i64 23)			// CHECK2-NEXT: invoke void @_ZN1SC1El(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]], i64 23)
	// CHECK2-NEXT: to label [[INVOKE_CONT:%.]] unwind label [[TERMINATE_LPAD:%.]]			// CHECK2-NEXT: to label [[INVOKE_CONT:%.]] unwind label [[TERMINATE_LPAD:%.]], !llvm.access.group !42
	// CHECK2: invoke.cont:			// CHECK2: invoke.cont:
	// CHECK2-NEXT: [[CALL:%.]] = invoke signext i8 @_ZN1ScvcEv(%struct.S nonnull align 8 dereferenceable(24) [[REF_TMP]])			// CHECK2-NEXT: [[CALL:%.]] = invoke signext i8 @_ZN1ScvcEv(%struct.S nonnull align 8 dereferenceable(24) [[REF_TMP]])
	// CHECK2-NEXT: to label [[INVOKE_CONT2:%.]] unwind label [[LPAD:%.]]			// CHECK2-NEXT: to label [[INVOKE_CONT2:%.]] unwind label [[LPAD:%.]], !llvm.access.group !42
	// CHECK2: invoke.cont2:			// CHECK2: invoke.cont2:
	// CHECK2-NEXT: [[TMP7:%.*]] = sext i8 [[CALL]] to i32			// CHECK2-NEXT: [[TMP7:%.*]] = sext i8 [[CALL]] to i32
	// CHECK2-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 [[TMP7]])			// CHECK2-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 [[TMP7]]), !llvm.access.group !42
	// CHECK2-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR6]]			// CHECK2-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR6]], !llvm.access.group !42
	// CHECK2-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK2-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !42
	// CHECK2-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64			// CHECK2-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
	// CHECK2-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK2-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !42
	// CHECK2-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64			// CHECK2-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
	// CHECK2-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..11 to void (i32, i32, ...)*), i64 [[TMP9]], i64 [[TMP11]])			// CHECK2-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..11 to void (i32, i32, ...)*), i64 [[TMP9]], i64 [[TMP11]]), !llvm.access.group !42
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK2: omp.inner.for.inc:			// CHECK2: omp.inner.for.inc:
	// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !42
	// CHECK2-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK2-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !42
	// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]			// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]
	// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !42
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP43:![0-9]+]]
	// CHECK2: lpad:			// CHECK2: lpad:
	// CHECK2-NEXT: [[TMP14:%.]] = landingpad { i8, i32 }			// CHECK2-NEXT: [[TMP14:%.]] = landingpad { i8, i32 }
	// CHECK2-NEXT: catch i8* null			// CHECK2-NEXT: catch i8* null
	// CHECK2-NEXT: [[TMP15:%.]] = extractvalue { i8, i32 } [[TMP14]], 0			// CHECK2-NEXT: [[TMP15:%.]] = extractvalue { i8, i32 } [[TMP14]], 0
	// CHECK2-NEXT: store i8* [[TMP15]], i8** [[EXN_SLOT]], align 8			// CHECK2-NEXT: store i8* [[TMP15]], i8** [[EXN_SLOT]], align 8, !llvm.access.group !42
	// CHECK2-NEXT: [[TMP16:%.]] = extractvalue { i8, i32 } [[TMP14]], 1			// CHECK2-NEXT: [[TMP16:%.]] = extractvalue { i8, i32 } [[TMP14]], 1
	// CHECK2-NEXT: store i32 [[TMP16]], i32* [[EHSELECTOR_SLOT]], align 4			// CHECK2-NEXT: store i32 [[TMP16]], i32* [[EHSELECTOR_SLOT]], align 4, !llvm.access.group !42
	// CHECK2-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR6]]			// CHECK2-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR6]], !llvm.access.group !42
	// CHECK2-NEXT: br label [[TERMINATE_HANDLER:%.*]]			// CHECK2-NEXT: br label [[TERMINATE_HANDLER:%.*]]
	// CHECK2: omp.inner.for.end:			// CHECK2: omp.inner.for.end:
	// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK2: omp.loop.exit:			// CHECK2: omp.loop.exit:
	// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])			// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
	// CHECK2-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK2-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK2-NEXT: [[TMP18:%.*]] = icmp ne i32 [[TMP17]], 0			// CHECK2-NEXT: [[TMP18:%.*]] = icmp ne i32 [[TMP17]], 0
	// CHECK2-NEXT: br i1 [[TMP18]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK2-NEXT: br i1 [[TMP18]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK2: .omp.final.then:			// CHECK2: .omp.final.then:
	// CHECK2-NEXT: store i32 100, i32* [[I]], align 4			// CHECK2-NEXT: store i32 100, i32* [[I]], align 4
	// CHECK2-NEXT: br label [[DOTOMP_FINAL_DONE]]			// CHECK2-NEXT: br label [[DOTOMP_FINAL_DONE]]
	// CHECK2: .omp.final.done:			// CHECK2: .omp.final.done:
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	// CHECK2: terminate.lpad:			// CHECK2: terminate.lpad:
	// CHECK2-NEXT: [[TMP19:%.]] = landingpad { i8, i32 }			// CHECK2-NEXT: [[TMP19:%.]] = landingpad { i8, i32 }
	// CHECK2-NEXT: catch i8* null			// CHECK2-NEXT: catch i8* null
	// CHECK2-NEXT: [[TMP20:%.]] = extractvalue { i8, i32 } [[TMP19]], 0			// CHECK2-NEXT: [[TMP20:%.]] = extractvalue { i8, i32 } [[TMP19]], 0
	// CHECK2-NEXT: call void @__clang_call_terminate(i8* [[TMP20]]) #[[ATTR10]]			// CHECK2-NEXT: call void @__clang_call_terminate(i8* [[TMP20]]) #[[ATTR10]], !llvm.access.group !42
	// CHECK2-NEXT: unreachable			// CHECK2-NEXT: unreachable
	// CHECK2: terminate.handler:			// CHECK2: terminate.handler:
	// CHECK2-NEXT: [[EXN:%.]] = load i8, i8** [[EXN_SLOT]], align 8			// CHECK2-NEXT: [[EXN:%.]] = load i8, i8** [[EXN_SLOT]], align 8, !llvm.access.group !42
	// CHECK2-NEXT: call void @__clang_call_terminate(i8* [[EXN]]) #[[ATTR10]]			// CHECK2-NEXT: call void @__clang_call_terminate(i8* [[EXN]]) #[[ATTR10]], !llvm.access.group !42
	// CHECK2-NEXT: unreachable			// CHECK2-NEXT: unreachable
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..11			// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..11
	// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i64 [[DOTPREVIOUS_LB_:%.]], i64 [[DOTPREVIOUS_UB_:%.]]) #[[ATTR3]] personality i8 bitcast (i32 (...)* @__gxx_personality_v0 to i8*) {			// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i64 [[DOTPREVIOUS_LB_:%.]], i64 [[DOTPREVIOUS_UB_:%.]]) #[[ATTR3]] personality i8 bitcast (i32 (...)* @__gxx_personality_v0 to i8*) {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8			// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8
	// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8			// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8
	Show All 33 Lines
	// CHECK2-NEXT: br label [[COND_END]]			// CHECK2-NEXT: br label [[COND_END]]
	// CHECK2: cond.end:			// CHECK2: cond.end:
	// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]			// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
	// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK2-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK2: omp.inner.for.cond:			// CHECK2: omp.inner.for.cond:
	// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !45
	// CHECK2-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK2-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !45
	// CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK2: omp.inner.for.body:			// CHECK2: omp.inner.for.body:
	// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !45
	// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !45
	// CHECK2-NEXT: invoke void @_Z3foov()			// CHECK2-NEXT: invoke void @_Z3foov()
	// CHECK2-NEXT: to label [[INVOKE_CONT:%.]] unwind label [[TERMINATE_LPAD:%.]]			// CHECK2-NEXT: to label [[INVOKE_CONT:%.]] unwind label [[TERMINATE_LPAD:%.]], !llvm.access.group !45
	// CHECK2: invoke.cont:			// CHECK2: invoke.cont:
	// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK2: omp.body.continue:			// CHECK2: omp.body.continue:
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK2: omp.inner.for.inc:			// CHECK2: omp.inner.for.inc:
	// CHECK2-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !45
	// CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !45
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP46:![0-9]+]]
	// CHECK2: omp.inner.for.end:			// CHECK2: omp.inner.for.end:
	// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK2: omp.loop.exit:			// CHECK2: omp.loop.exit:
	// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])			// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
	// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK2-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK2-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK2-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK2-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK2: .omp.final.then:			// CHECK2: .omp.final.then:
	// CHECK2-NEXT: store i32 100, i32* [[I]], align 4			// CHECK2-NEXT: store i32 100, i32* [[I]], align 4
	// CHECK2-NEXT: br label [[DOTOMP_FINAL_DONE]]			// CHECK2-NEXT: br label [[DOTOMP_FINAL_DONE]]
	// CHECK2: .omp.final.done:			// CHECK2: .omp.final.done:
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	// CHECK2: terminate.lpad:			// CHECK2: terminate.lpad:
	// CHECK2-NEXT: [[TMP13:%.]] = landingpad { i8, i32 }			// CHECK2-NEXT: [[TMP13:%.]] = landingpad { i8, i32 }
	// CHECK2-NEXT: catch i8* null			// CHECK2-NEXT: catch i8* null
	// CHECK2-NEXT: [[TMP14:%.]] = extractvalue { i8, i32 } [[TMP13]], 0			// CHECK2-NEXT: [[TMP14:%.]] = extractvalue { i8, i32 } [[TMP13]], 0
	// CHECK2-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]]			// CHECK2-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]], !llvm.access.group !45
	// CHECK2-NEXT: unreachable			// CHECK2-NEXT: unreachable
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg			// CHECK2-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
	// CHECK2-SAME: () #[[ATTR9:[0-9]+]] {			// CHECK2-SAME: () #[[ATTR9:[0-9]+]] {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	// CHECK2-NEXT: call void @__tgt_register_requires(i64 1)			// CHECK2-NEXT: call void @__tgt_register_requires(i64 1)
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	▲ Show 20 Lines • Show All 822 Lines • ▼ Show 20 Lines
	// CHECK5-NEXT: br label [[COND_END]]			// CHECK5-NEXT: br label [[COND_END]]
	// CHECK5: cond.end:			// CHECK5: cond.end:
	// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]			// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
	// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK5-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK5-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK5-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK5-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK5: omp.inner.for.cond:			// CHECK5: omp.inner.for.cond:
	// CHECK5-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK5-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK5-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK5-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !9
	// CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK5: omp.inner.for.body:			// CHECK5: omp.inner.for.body:
	// CHECK5-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 2)			// CHECK5-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 2), !llvm.access.group !9
	// CHECK5-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK5-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !9
	// CHECK5-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64			// CHECK5-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
	// CHECK5-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK5-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !9
	// CHECK5-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK5-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK5-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..1 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]])			// CHECK5-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..1 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !9
	// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK5: omp.inner.for.inc:			// CHECK5: omp.inner.for.inc:
	// CHECK5-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK5-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK5-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK5-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !9
	// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]			// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
	// CHECK5-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK5-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]]			// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]
	// CHECK5: omp.inner.for.end:			// CHECK5: omp.inner.for.end:
	// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK5: omp.loop.exit:			// CHECK5: omp.loop.exit:
	// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])			// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
	// CHECK5-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK5-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK5-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0			// CHECK5-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
	// CHECK5-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK5-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK5: .omp.final.then:			// CHECK5: .omp.final.then:
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	// CHECK5-NEXT: br label [[COND_END]]			// CHECK5-NEXT: br label [[COND_END]]
	// CHECK5: cond.end:			// CHECK5: cond.end:
	// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]			// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
	// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK5-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK5-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK5-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK5-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK5: omp.inner.for.cond:			// CHECK5: omp.inner.for.cond:
	// CHECK5-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK5-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK5-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK5-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !13
	// CHECK5-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK5-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK5: omp.inner.for.body:			// CHECK5: omp.inner.for.body:
	// CHECK5-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK5-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !13
	// CHECK5-NEXT: invoke void @_Z3foov()			// CHECK5-NEXT: invoke void @_Z3foov()
	// CHECK5-NEXT: to label [[INVOKE_CONT:%.]] unwind label [[TERMINATE_LPAD:%.]]			// CHECK5-NEXT: to label [[INVOKE_CONT:%.]] unwind label [[TERMINATE_LPAD:%.]], !llvm.access.group !13
	// CHECK5: invoke.cont:			// CHECK5: invoke.cont:
	// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK5: omp.body.continue:			// CHECK5: omp.body.continue:
	// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK5: omp.inner.for.inc:			// CHECK5: omp.inner.for.inc:
	// CHECK5-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK5-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK5-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4			// CHECK5-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]			// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]]
	// CHECK5: omp.inner.for.end:			// CHECK5: omp.inner.for.end:
	// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK5: omp.loop.exit:			// CHECK5: omp.loop.exit:
	// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])			// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
	// CHECK5-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK5-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK5-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK5-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK5-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK5-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK5: .omp.final.then:			// CHECK5: .omp.final.then:
	// CHECK5-NEXT: store i32 100, i32* [[I]], align 4			// CHECK5-NEXT: store i32 100, i32* [[I]], align 4
	// CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]]			// CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]]
	// CHECK5: .omp.final.done:			// CHECK5: .omp.final.done:
	// CHECK5-NEXT: ret void			// CHECK5-NEXT: ret void
	// CHECK5: terminate.lpad:			// CHECK5: terminate.lpad:
	// CHECK5-NEXT: [[TMP13:%.]] = landingpad { i8, i32 }			// CHECK5-NEXT: [[TMP13:%.]] = landingpad { i8, i32 }
	// CHECK5-NEXT: catch i8* null			// CHECK5-NEXT: catch i8* null
	// CHECK5-NEXT: [[TMP14:%.]] = extractvalue { i8, i32 } [[TMP13]], 0			// CHECK5-NEXT: [[TMP14:%.]] = extractvalue { i8, i32 } [[TMP13]], 0
	// CHECK5-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10:[0-9]+]]			// CHECK5-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10:[0-9]+]], !llvm.access.group !13
	// CHECK5-NEXT: unreachable			// CHECK5-NEXT: unreachable
	//			//
	//			//
	// CHECK5-LABEL: define {{[^@]+}}@__clang_call_terminate			// CHECK5-LABEL: define {{[^@]+}}@__clang_call_terminate
	// CHECK5-SAME: (i8* [[TMP0:%.*]]) #[[ATTR5:[0-9]+]] comdat {			// CHECK5-SAME: (i8* [[TMP0:%.*]]) #[[ATTR5:[0-9]+]] comdat {
	// CHECK5-NEXT: [[TMP2:%.]] = call i8 @__cxa_begin_catch(i8* [[TMP0]]) #[[ATTR6]]			// CHECK5-NEXT: [[TMP2:%.]] = call i8 @__cxa_begin_catch(i8* [[TMP0]]) #[[ATTR6]]
	// CHECK5-NEXT: call void @_ZSt9terminatev() #[[ATTR10]]			// CHECK5-NEXT: call void @_ZSt9terminatev() #[[ATTR10]]
	// CHECK5-NEXT: unreachable			// CHECK5-NEXT: unreachable
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	// CHECK5-NEXT: br label [[COND_END]]			// CHECK5-NEXT: br label [[COND_END]]
	// CHECK5: cond.end:			// CHECK5: cond.end:
	// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]			// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
	// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK5-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK5-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK5-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK5-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK5: omp.inner.for.cond:			// CHECK5: omp.inner.for.cond:
	// CHECK5-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK5-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK5-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK5-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !18
	// CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK5: omp.inner.for.body:			// CHECK5: omp.inner.for.body:
	// CHECK5-NEXT: [[TMP8:%.]] = load i8, i8 [[TMP0]], align 1			// CHECK5-NEXT: [[TMP8:%.]] = load i8, i8 [[TMP0]], align 1, !llvm.access.group !18
	// CHECK5-NEXT: [[TMP9:%.*]] = sext i8 [[TMP8]] to i32			// CHECK5-NEXT: [[TMP9:%.*]] = sext i8 [[TMP8]] to i32
	// CHECK5-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP2]], i32 [[TMP9]])			// CHECK5-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP2]], i32 [[TMP9]]), !llvm.access.group !18
	// CHECK5-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK5-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !18
	// CHECK5-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64			// CHECK5-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
	// CHECK5-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK5-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !18
	// CHECK5-NEXT: [[TMP13:%.*]] = zext i32 [[TMP12]] to i64			// CHECK5-NEXT: [[TMP13:%.*]] = zext i32 [[TMP12]] to i64
	// CHECK5-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..3 to void (i32, i32, ...)*), i64 [[TMP11]], i64 [[TMP13]])			// CHECK5-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..3 to void (i32, i32, ...)*), i64 [[TMP11]], i64 [[TMP13]]), !llvm.access.group !18
	// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK5: omp.inner.for.inc:			// CHECK5: omp.inner.for.inc:
	// CHECK5-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK5-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK5-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK5-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !18
	// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP14]], [[TMP15]]			// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP14]], [[TMP15]]
	// CHECK5-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK5-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]			// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]
	// CHECK5: omp.inner.for.end:			// CHECK5: omp.inner.for.end:
	// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK5: omp.loop.exit:			// CHECK5: omp.loop.exit:
	// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])			// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
	// CHECK5-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK5-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK5-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0			// CHECK5-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0
	// CHECK5-NEXT: br i1 [[TMP17]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK5-NEXT: br i1 [[TMP17]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK5: .omp.final.then:			// CHECK5: .omp.final.then:
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	// CHECK5-NEXT: br label [[COND_END]]			// CHECK5-NEXT: br label [[COND_END]]
	// CHECK5: cond.end:			// CHECK5: cond.end:
	// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]			// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
	// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK5-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK5-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK5-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK5-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK5: omp.inner.for.cond:			// CHECK5: omp.inner.for.cond:
	// CHECK5-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK5-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !21
	// CHECK5-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK5-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !21
	// CHECK5-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK5-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK5: omp.inner.for.body:			// CHECK5: omp.inner.for.body:
	// CHECK5-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK5-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !21
	// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !21
	// CHECK5-NEXT: invoke void @_Z3foov()			// CHECK5-NEXT: invoke void @_Z3foov()
	// CHECK5-NEXT: to label [[INVOKE_CONT:%.]] unwind label [[TERMINATE_LPAD:%.]]			// CHECK5-NEXT: to label [[INVOKE_CONT:%.]] unwind label [[TERMINATE_LPAD:%.]], !llvm.access.group !21
	// CHECK5: invoke.cont:			// CHECK5: invoke.cont:
	// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK5: omp.body.continue:			// CHECK5: omp.body.continue:
	// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK5: omp.inner.for.inc:			// CHECK5: omp.inner.for.inc:
	// CHECK5-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK5-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !21
	// CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK5-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4			// CHECK5-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
	// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]]			// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]]
	// CHECK5: omp.inner.for.end:			// CHECK5: omp.inner.for.end:
	// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK5: omp.loop.exit:			// CHECK5: omp.loop.exit:
	// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])			// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
	// CHECK5-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK5-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK5-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK5-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK5-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK5-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK5: .omp.final.then:			// CHECK5: .omp.final.then:
	// CHECK5-NEXT: store i32 100, i32* [[I]], align 4			// CHECK5-NEXT: store i32 100, i32* [[I]], align 4
	// CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]]			// CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]]
	// CHECK5: .omp.final.done:			// CHECK5: .omp.final.done:
	// CHECK5-NEXT: ret void			// CHECK5-NEXT: ret void
	// CHECK5: terminate.lpad:			// CHECK5: terminate.lpad:
	// CHECK5-NEXT: [[TMP13:%.]] = landingpad { i8, i32 }			// CHECK5-NEXT: [[TMP13:%.]] = landingpad { i8, i32 }
	// CHECK5-NEXT: catch i8* null			// CHECK5-NEXT: catch i8* null
	// CHECK5-NEXT: [[TMP14:%.]] = extractvalue { i8, i32 } [[TMP13]], 0			// CHECK5-NEXT: [[TMP14:%.]] = extractvalue { i8, i32 } [[TMP13]], 0
	// CHECK5-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]]			// CHECK5-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]], !llvm.access.group !21
	// CHECK5-NEXT: unreachable			// CHECK5-NEXT: unreachable
	//			//
	//			//
	// CHECK5-LABEL: define {{[^@]+}}@_Z5tmainIcLi5EEiv			// CHECK5-LABEL: define {{[^@]+}}@_Z5tmainIcLi5EEiv
	// CHECK5-SAME: () #[[ATTR7:[0-9]+]] comdat {			// CHECK5-SAME: () #[[ATTR7:[0-9]+]] comdat {
	// CHECK5-NEXT: entry:			// CHECK5-NEXT: entry:
	// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4			// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4
	// CHECK5-NEXT: [[_TMP1:%.*]] = alloca i32, align 4			// CHECK5-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
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	// CHECK5-NEXT: br label [[COND_END]]			// CHECK5-NEXT: br label [[COND_END]]
	// CHECK5: cond.end:			// CHECK5: cond.end:
	// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]			// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
	// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK5-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK5-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK5-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK5-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK5: omp.inner.for.cond:			// CHECK5: omp.inner.for.cond:
	// CHECK5-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK5-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !24
	// CHECK5-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK5-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !24
	// CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK5: omp.inner.for.body:			// CHECK5: omp.inner.for.body:
	// CHECK5-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 5)			// CHECK5-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 5), !llvm.access.group !24
	// CHECK5-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK5-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !24
	// CHECK5-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64			// CHECK5-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
	// CHECK5-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK5-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !24
	// CHECK5-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK5-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK5-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..5 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]])			// CHECK5-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..5 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !24
	// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK5: omp.inner.for.inc:			// CHECK5: omp.inner.for.inc:
	// CHECK5-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK5-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !24
	// CHECK5-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK5-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !24
	// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]			// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
	// CHECK5-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK5-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
	// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]]			// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]]
	// CHECK5: omp.inner.for.end:			// CHECK5: omp.inner.for.end:
	// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK5: omp.loop.exit:			// CHECK5: omp.loop.exit:
	// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])			// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
	// CHECK5-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK5-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK5-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0			// CHECK5-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
	// CHECK5-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK5-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK5: .omp.final.then:			// CHECK5: .omp.final.then:
	▲ Show 20 Lines • Show All 44 Lines • ▼ Show 20 Lines
	// CHECK5-NEXT: br label [[COND_END]]			// CHECK5-NEXT: br label [[COND_END]]
	// CHECK5: cond.end:			// CHECK5: cond.end:
	// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]			// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
	// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK5-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK5-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK5-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK5-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK5: omp.inner.for.cond:			// CHECK5: omp.inner.for.cond:
	// CHECK5-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK5-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !27
	// CHECK5-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK5-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !27
	// CHECK5-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK5-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK5: omp.inner.for.body:			// CHECK5: omp.inner.for.body:
	// CHECK5-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK5-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !27
	// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !27
	// CHECK5-NEXT: invoke void @_Z3foov()			// CHECK5-NEXT: invoke void @_Z3foov()
	// CHECK5-NEXT: to label [[INVOKE_CONT:%.]] unwind label [[TERMINATE_LPAD:%.]]			// CHECK5-NEXT: to label [[INVOKE_CONT:%.]] unwind label [[TERMINATE_LPAD:%.]], !llvm.access.group !27
	// CHECK5: invoke.cont:			// CHECK5: invoke.cont:
	// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK5: omp.body.continue:			// CHECK5: omp.body.continue:
	// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK5: omp.inner.for.inc:			// CHECK5: omp.inner.for.inc:
	// CHECK5-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK5-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !27
	// CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK5-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4			// CHECK5-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27
	// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]]			// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]]
	// CHECK5: omp.inner.for.end:			// CHECK5: omp.inner.for.end:
	// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK5: omp.loop.exit:			// CHECK5: omp.loop.exit:
	// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])			// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
	// CHECK5-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK5-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK5-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK5-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK5-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK5-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK5: .omp.final.then:			// CHECK5: .omp.final.then:
	// CHECK5-NEXT: store i32 100, i32* [[I]], align 4			// CHECK5-NEXT: store i32 100, i32* [[I]], align 4
	// CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]]			// CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]]
	// CHECK5: .omp.final.done:			// CHECK5: .omp.final.done:
	// CHECK5-NEXT: ret void			// CHECK5-NEXT: ret void
	// CHECK5: terminate.lpad:			// CHECK5: terminate.lpad:
	// CHECK5-NEXT: [[TMP13:%.]] = landingpad { i8, i32 }			// CHECK5-NEXT: [[TMP13:%.]] = landingpad { i8, i32 }
	// CHECK5-NEXT: catch i8* null			// CHECK5-NEXT: catch i8* null
	// CHECK5-NEXT: [[TMP14:%.]] = extractvalue { i8, i32 } [[TMP13]], 0			// CHECK5-NEXT: [[TMP14:%.]] = extractvalue { i8, i32 } [[TMP13]], 0
	// CHECK5-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]]			// CHECK5-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]], !llvm.access.group !27
	// CHECK5-NEXT: unreachable			// CHECK5-NEXT: unreachable
	//			//
	//			//
	// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l57			// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l57
	// CHECK5-SAME: () #[[ATTR3]] {			// CHECK5-SAME: () #[[ATTR3]] {
	// CHECK5-NEXT: entry:			// CHECK5-NEXT: entry:
	// CHECK5-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32, i32, ...)* bitcast (void (i32, i32)* @.omp_outlined..6 to void (i32, i32, ...)*))			// CHECK5-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32, i32, ...)* bitcast (void (i32, i32)* @.omp_outlined..6 to void (i32, i32, ...)*))
	// CHECK5-NEXT: ret void			// CHECK5-NEXT: ret void
	Show All 30 Lines
	// CHECK5-NEXT: br label [[COND_END]]			// CHECK5-NEXT: br label [[COND_END]]
	// CHECK5: cond.end:			// CHECK5: cond.end:
	// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]			// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
	// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK5-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK5-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK5-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK5-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK5: omp.inner.for.cond:			// CHECK5: omp.inner.for.cond:
	// CHECK5-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK5-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !30
	// CHECK5-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK5-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !30
	// CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK5: omp.inner.for.body:			// CHECK5: omp.inner.for.body:
	// CHECK5-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 23)			// CHECK5-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 23), !llvm.access.group !30
	// CHECK5-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK5-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !30
	// CHECK5-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64			// CHECK5-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
	// CHECK5-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK5-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !30
	// CHECK5-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK5-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK5-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..7 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]])			// CHECK5-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..7 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !30
	// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK5: omp.inner.for.inc:			// CHECK5: omp.inner.for.inc:
	// CHECK5-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK5-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !30
	// CHECK5-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK5-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !30
	// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]			// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
	// CHECK5-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK5-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30
	// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]]			// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP31:![0-9]+]]
	// CHECK5: omp.inner.for.end:			// CHECK5: omp.inner.for.end:
	// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK5: omp.loop.exit:			// CHECK5: omp.loop.exit:
	// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])			// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
	// CHECK5-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK5-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK5-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0			// CHECK5-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
	// CHECK5-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK5-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK5: .omp.final.then:			// CHECK5: .omp.final.then:
	▲ Show 20 Lines • Show All 44 Lines • ▼ Show 20 Lines
	// CHECK5-NEXT: br label [[COND_END]]			// CHECK5-NEXT: br label [[COND_END]]
	// CHECK5: cond.end:			// CHECK5: cond.end:
	// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]			// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
	// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK5-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK5-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK5-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK5-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK5: omp.inner.for.cond:			// CHECK5: omp.inner.for.cond:
	// CHECK5-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK5-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !33
	// CHECK5-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK5-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !33
	// CHECK5-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK5-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK5: omp.inner.for.body:			// CHECK5: omp.inner.for.body:
	// CHECK5-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK5-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !33
	// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !33
	// CHECK5-NEXT: invoke void @_Z3foov()			// CHECK5-NEXT: invoke void @_Z3foov()
	// CHECK5-NEXT: to label [[INVOKE_CONT:%.]] unwind label [[TERMINATE_LPAD:%.]]			// CHECK5-NEXT: to label [[INVOKE_CONT:%.]] unwind label [[TERMINATE_LPAD:%.]], !llvm.access.group !33
	// CHECK5: invoke.cont:			// CHECK5: invoke.cont:
	// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK5: omp.body.continue:			// CHECK5: omp.body.continue:
	// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK5: omp.inner.for.inc:			// CHECK5: omp.inner.for.inc:
	// CHECK5-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK5-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !33
	// CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK5-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4			// CHECK5-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33
	// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]]			// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP34:![0-9]+]]
	// CHECK5: omp.inner.for.end:			// CHECK5: omp.inner.for.end:
	// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK5: omp.loop.exit:			// CHECK5: omp.loop.exit:
	// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])			// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
	// CHECK5-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK5-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK5-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK5-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK5-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK5-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK5: .omp.final.then:			// CHECK5: .omp.final.then:
	// CHECK5-NEXT: store i32 100, i32* [[I]], align 4			// CHECK5-NEXT: store i32 100, i32* [[I]], align 4
	// CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]]			// CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]]
	// CHECK5: .omp.final.done:			// CHECK5: .omp.final.done:
	// CHECK5-NEXT: ret void			// CHECK5-NEXT: ret void
	// CHECK5: terminate.lpad:			// CHECK5: terminate.lpad:
	// CHECK5-NEXT: [[TMP13:%.]] = landingpad { i8, i32 }			// CHECK5-NEXT: [[TMP13:%.]] = landingpad { i8, i32 }
	// CHECK5-NEXT: catch i8* null			// CHECK5-NEXT: catch i8* null
	// CHECK5-NEXT: [[TMP14:%.]] = extractvalue { i8, i32 } [[TMP13]], 0			// CHECK5-NEXT: [[TMP14:%.]] = extractvalue { i8, i32 } [[TMP13]], 0
	// CHECK5-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]]			// CHECK5-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]], !llvm.access.group !33
	// CHECK5-NEXT: unreachable			// CHECK5-NEXT: unreachable
	//			//
	//			//
	// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l52			// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l52
	// CHECK5-SAME: () #[[ATTR3]] {			// CHECK5-SAME: () #[[ATTR3]] {
	// CHECK5-NEXT: entry:			// CHECK5-NEXT: entry:
	// CHECK5-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32, i32, ...)* bitcast (void (i32, i32)* @.omp_outlined..8 to void (i32, i32, ...)*))			// CHECK5-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32, i32, ...)* bitcast (void (i32, i32)* @.omp_outlined..8 to void (i32, i32, ...)*))
	// CHECK5-NEXT: ret void			// CHECK5-NEXT: ret void
	Show All 30 Lines
	// CHECK5-NEXT: br label [[COND_END]]			// CHECK5-NEXT: br label [[COND_END]]
	// CHECK5: cond.end:			// CHECK5: cond.end:
	// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]			// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
	// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK5-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK5-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK5-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK5-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK5: omp.inner.for.cond:			// CHECK5: omp.inner.for.cond:
	// CHECK5-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK5-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !36
	// CHECK5-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK5-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !36
	// CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK5: omp.inner.for.body:			// CHECK5: omp.inner.for.body:
	// CHECK5-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 1)			// CHECK5-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 1), !llvm.access.group !36
	// CHECK5-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK5-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !36
	// CHECK5-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64			// CHECK5-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
	// CHECK5-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK5-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !36
	// CHECK5-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK5-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK5-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..9 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]])			// CHECK5-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..9 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !36
	// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK5: omp.inner.for.inc:			// CHECK5: omp.inner.for.inc:
	// CHECK5-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK5-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !36
	// CHECK5-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK5-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !36
	// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]			// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
	// CHECK5-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK5-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36
	// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]			// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP37:![0-9]+]]
	// CHECK5: omp.inner.for.end:			// CHECK5: omp.inner.for.end:
	// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK5: omp.loop.exit:			// CHECK5: omp.loop.exit:
	// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])			// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
	// CHECK5-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK5-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK5-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0			// CHECK5-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
	// CHECK5-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK5-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK5: .omp.final.then:			// CHECK5: .omp.final.then:
	▲ Show 20 Lines • Show All 44 Lines • ▼ Show 20 Lines
	// CHECK5-NEXT: br label [[COND_END]]			// CHECK5-NEXT: br label [[COND_END]]
	// CHECK5: cond.end:			// CHECK5: cond.end:
	// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]			// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
	// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK5-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK5-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK5-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK5-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK5: omp.inner.for.cond:			// CHECK5: omp.inner.for.cond:
	// CHECK5-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK5-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !39
	// CHECK5-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK5-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !39
	// CHECK5-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK5-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK5: omp.inner.for.body:			// CHECK5: omp.inner.for.body:
	// CHECK5-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK5-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !39
	// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !39
	// CHECK5-NEXT: invoke void @_Z3foov()			// CHECK5-NEXT: invoke void @_Z3foov()
	// CHECK5-NEXT: to label [[INVOKE_CONT:%.]] unwind label [[TERMINATE_LPAD:%.]]			// CHECK5-NEXT: to label [[INVOKE_CONT:%.]] unwind label [[TERMINATE_LPAD:%.]], !llvm.access.group !39
	// CHECK5: invoke.cont:			// CHECK5: invoke.cont:
	// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK5: omp.body.continue:			// CHECK5: omp.body.continue:
	// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK5: omp.inner.for.inc:			// CHECK5: omp.inner.for.inc:
	// CHECK5-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK5-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !39
	// CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK5-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4			// CHECK5-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39
	// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]]			// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP40:![0-9]+]]
	// CHECK5: omp.inner.for.end:			// CHECK5: omp.inner.for.end:
	// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK5: omp.loop.exit:			// CHECK5: omp.loop.exit:
	// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])			// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
	// CHECK5-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK5-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK5-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK5-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK5-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK5-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK5: .omp.final.then:			// CHECK5: .omp.final.then:
	// CHECK5-NEXT: store i32 100, i32* [[I]], align 4			// CHECK5-NEXT: store i32 100, i32* [[I]], align 4
	// CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]]			// CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]]
	// CHECK5: .omp.final.done:			// CHECK5: .omp.final.done:
	// CHECK5-NEXT: ret void			// CHECK5-NEXT: ret void
	// CHECK5: terminate.lpad:			// CHECK5: terminate.lpad:
	// CHECK5-NEXT: [[TMP13:%.]] = landingpad { i8, i32 }			// CHECK5-NEXT: [[TMP13:%.]] = landingpad { i8, i32 }
	// CHECK5-NEXT: catch i8* null			// CHECK5-NEXT: catch i8* null
	// CHECK5-NEXT: [[TMP14:%.]] = extractvalue { i8, i32 } [[TMP13]], 0			// CHECK5-NEXT: [[TMP14:%.]] = extractvalue { i8, i32 } [[TMP13]], 0
	// CHECK5-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]]			// CHECK5-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]], !llvm.access.group !39
	// CHECK5-NEXT: unreachable			// CHECK5-NEXT: unreachable
	//			//
	//			//
	// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l57			// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l57
	// CHECK5-SAME: () #[[ATTR3]] {			// CHECK5-SAME: () #[[ATTR3]] {
	// CHECK5-NEXT: entry:			// CHECK5-NEXT: entry:
	// CHECK5-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32, i32, ...)* bitcast (void (i32, i32)* @.omp_outlined..10 to void (i32, i32, ...)*))			// CHECK5-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32, i32, ...)* bitcast (void (i32, i32)* @.omp_outlined..10 to void (i32, i32, ...)*))
	// CHECK5-NEXT: ret void			// CHECK5-NEXT: ret void
	Show All 33 Lines
	// CHECK5-NEXT: br label [[COND_END]]			// CHECK5-NEXT: br label [[COND_END]]
	// CHECK5: cond.end:			// CHECK5: cond.end:
	// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]			// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
	// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK5-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK5-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK5-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK5-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK5: omp.inner.for.cond:			// CHECK5: omp.inner.for.cond:
	// CHECK5-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK5-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !42
	// CHECK5-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK5-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !42
	// CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK5: omp.inner.for.body:			// CHECK5: omp.inner.for.body:
	// CHECK5-NEXT: invoke void @_ZN1SC1El(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]], i64 23)			// CHECK5-NEXT: invoke void @_ZN1SC1El(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]], i64 23)
	// CHECK5-NEXT: to label [[INVOKE_CONT:%.]] unwind label [[TERMINATE_LPAD:%.]]			// CHECK5-NEXT: to label [[INVOKE_CONT:%.]] unwind label [[TERMINATE_LPAD:%.]], !llvm.access.group !42
	// CHECK5: invoke.cont:			// CHECK5: invoke.cont:
	// CHECK5-NEXT: [[CALL:%.]] = invoke signext i8 @_ZN1ScvcEv(%struct.S nonnull align 8 dereferenceable(24) [[REF_TMP]])			// CHECK5-NEXT: [[CALL:%.]] = invoke signext i8 @_ZN1ScvcEv(%struct.S nonnull align 8 dereferenceable(24) [[REF_TMP]])
	// CHECK5-NEXT: to label [[INVOKE_CONT2:%.]] unwind label [[LPAD:%.]]			// CHECK5-NEXT: to label [[INVOKE_CONT2:%.]] unwind label [[LPAD:%.]], !llvm.access.group !42
	// CHECK5: invoke.cont2:			// CHECK5: invoke.cont2:
	// CHECK5-NEXT: [[TMP7:%.*]] = sext i8 [[CALL]] to i32			// CHECK5-NEXT: [[TMP7:%.*]] = sext i8 [[CALL]] to i32
	// CHECK5-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 [[TMP7]])			// CHECK5-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 [[TMP7]]), !llvm.access.group !42
	// CHECK5-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR6]]			// CHECK5-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR6]], !llvm.access.group !42
	// CHECK5-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK5-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !42
	// CHECK5-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64			// CHECK5-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
	// CHECK5-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK5-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !42
	// CHECK5-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64			// CHECK5-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
	// CHECK5-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..11 to void (i32, i32, ...)*), i64 [[TMP9]], i64 [[TMP11]])			// CHECK5-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..11 to void (i32, i32, ...)*), i64 [[TMP9]], i64 [[TMP11]]), !llvm.access.group !42
	// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK5: omp.inner.for.inc:			// CHECK5: omp.inner.for.inc:
	// CHECK5-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK5-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !42
	// CHECK5-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK5-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !42
	// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]			// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]
	// CHECK5-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK5-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !42
	// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]]			// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP43:![0-9]+]]
	// CHECK5: lpad:			// CHECK5: lpad:
	// CHECK5-NEXT: [[TMP14:%.]] = landingpad { i8, i32 }			// CHECK5-NEXT: [[TMP14:%.]] = landingpad { i8, i32 }
	// CHECK5-NEXT: catch i8* null			// CHECK5-NEXT: catch i8* null
	// CHECK5-NEXT: [[TMP15:%.]] = extractvalue { i8, i32 } [[TMP14]], 0			// CHECK5-NEXT: [[TMP15:%.]] = extractvalue { i8, i32 } [[TMP14]], 0
	// CHECK5-NEXT: store i8* [[TMP15]], i8** [[EXN_SLOT]], align 8			// CHECK5-NEXT: store i8* [[TMP15]], i8** [[EXN_SLOT]], align 8, !llvm.access.group !42
	// CHECK5-NEXT: [[TMP16:%.]] = extractvalue { i8, i32 } [[TMP14]], 1			// CHECK5-NEXT: [[TMP16:%.]] = extractvalue { i8, i32 } [[TMP14]], 1
	// CHECK5-NEXT: store i32 [[TMP16]], i32* [[EHSELECTOR_SLOT]], align 4			// CHECK5-NEXT: store i32 [[TMP16]], i32* [[EHSELECTOR_SLOT]], align 4, !llvm.access.group !42
	// CHECK5-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR6]]			// CHECK5-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR6]], !llvm.access.group !42
	// CHECK5-NEXT: br label [[TERMINATE_HANDLER:%.*]]			// CHECK5-NEXT: br label [[TERMINATE_HANDLER:%.*]]
	// CHECK5: omp.inner.for.end:			// CHECK5: omp.inner.for.end:
	// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK5: omp.loop.exit:			// CHECK5: omp.loop.exit:
	// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])			// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
	// CHECK5-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK5-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK5-NEXT: [[TMP18:%.*]] = icmp ne i32 [[TMP17]], 0			// CHECK5-NEXT: [[TMP18:%.*]] = icmp ne i32 [[TMP17]], 0
	// CHECK5-NEXT: br i1 [[TMP18]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK5-NEXT: br i1 [[TMP18]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK5: .omp.final.then:			// CHECK5: .omp.final.then:
	// CHECK5-NEXT: store i32 100, i32* [[I]], align 4			// CHECK5-NEXT: store i32 100, i32* [[I]], align 4
	// CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]]			// CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]]
	// CHECK5: .omp.final.done:			// CHECK5: .omp.final.done:
	// CHECK5-NEXT: ret void			// CHECK5-NEXT: ret void
	// CHECK5: terminate.lpad:			// CHECK5: terminate.lpad:
	// CHECK5-NEXT: [[TMP19:%.]] = landingpad { i8, i32 }			// CHECK5-NEXT: [[TMP19:%.]] = landingpad { i8, i32 }
	// CHECK5-NEXT: catch i8* null			// CHECK5-NEXT: catch i8* null
	// CHECK5-NEXT: [[TMP20:%.]] = extractvalue { i8, i32 } [[TMP19]], 0			// CHECK5-NEXT: [[TMP20:%.]] = extractvalue { i8, i32 } [[TMP19]], 0
	// CHECK5-NEXT: call void @__clang_call_terminate(i8* [[TMP20]]) #[[ATTR10]]			// CHECK5-NEXT: call void @__clang_call_terminate(i8* [[TMP20]]) #[[ATTR10]], !llvm.access.group !42
	// CHECK5-NEXT: unreachable			// CHECK5-NEXT: unreachable
	// CHECK5: terminate.handler:			// CHECK5: terminate.handler:
	// CHECK5-NEXT: [[EXN:%.]] = load i8, i8** [[EXN_SLOT]], align 8			// CHECK5-NEXT: [[EXN:%.]] = load i8, i8** [[EXN_SLOT]], align 8, !llvm.access.group !42
	// CHECK5-NEXT: call void @__clang_call_terminate(i8* [[EXN]]) #[[ATTR10]]			// CHECK5-NEXT: call void @__clang_call_terminate(i8* [[EXN]]) #[[ATTR10]], !llvm.access.group !42
	// CHECK5-NEXT: unreachable			// CHECK5-NEXT: unreachable
	//			//
	//			//
	// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..11			// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..11
	// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i64 [[DOTPREVIOUS_LB_:%.]], i64 [[DOTPREVIOUS_UB_:%.]]) #[[ATTR3]] personality i8 bitcast (i32 (...)* @__gxx_personality_v0 to i8*) {			// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i64 [[DOTPREVIOUS_LB_:%.]], i64 [[DOTPREVIOUS_UB_:%.]]) #[[ATTR3]] personality i8 bitcast (i32 (...)* @__gxx_personality_v0 to i8*) {
	// CHECK5-NEXT: entry:			// CHECK5-NEXT: entry:
	// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8			// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8
	// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8			// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8
	Show All 33 Lines
	// CHECK5-NEXT: br label [[COND_END]]			// CHECK5-NEXT: br label [[COND_END]]
	// CHECK5: cond.end:			// CHECK5: cond.end:
	// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]			// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
	// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK5-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK5-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK5-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK5-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK5: omp.inner.for.cond:			// CHECK5: omp.inner.for.cond:
	// CHECK5-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK5-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !45
	// CHECK5-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK5-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !45
	// CHECK5-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK5-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK5: omp.inner.for.body:			// CHECK5: omp.inner.for.body:
	// CHECK5-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK5-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !45
	// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !45
	// CHECK5-NEXT: invoke void @_Z3foov()			// CHECK5-NEXT: invoke void @_Z3foov()
	// CHECK5-NEXT: to label [[INVOKE_CONT:%.]] unwind label [[TERMINATE_LPAD:%.]]			// CHECK5-NEXT: to label [[INVOKE_CONT:%.]] unwind label [[TERMINATE_LPAD:%.]], !llvm.access.group !45
	// CHECK5: invoke.cont:			// CHECK5: invoke.cont:
	// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK5: omp.body.continue:			// CHECK5: omp.body.continue:
	// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK5: omp.inner.for.inc:			// CHECK5: omp.inner.for.inc:
	// CHECK5-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK5-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !45
	// CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK5-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4			// CHECK5-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !45
	// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]]			// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP46:![0-9]+]]
	// CHECK5: omp.inner.for.end:			// CHECK5: omp.inner.for.end:
	// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK5: omp.loop.exit:			// CHECK5: omp.loop.exit:
	// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])			// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
	// CHECK5-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK5-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK5-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK5-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK5-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK5-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK5: .omp.final.then:			// CHECK5: .omp.final.then:
	// CHECK5-NEXT: store i32 100, i32* [[I]], align 4			// CHECK5-NEXT: store i32 100, i32* [[I]], align 4
	// CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]]			// CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]]
	// CHECK5: .omp.final.done:			// CHECK5: .omp.final.done:
	// CHECK5-NEXT: ret void			// CHECK5-NEXT: ret void
	// CHECK5: terminate.lpad:			// CHECK5: terminate.lpad:
	// CHECK5-NEXT: [[TMP13:%.]] = landingpad { i8, i32 }			// CHECK5-NEXT: [[TMP13:%.]] = landingpad { i8, i32 }
	// CHECK5-NEXT: catch i8* null			// CHECK5-NEXT: catch i8* null
	// CHECK5-NEXT: [[TMP14:%.]] = extractvalue { i8, i32 } [[TMP13]], 0			// CHECK5-NEXT: [[TMP14:%.]] = extractvalue { i8, i32 } [[TMP13]], 0
	// CHECK5-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]]			// CHECK5-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]], !llvm.access.group !45
	// CHECK5-NEXT: unreachable			// CHECK5-NEXT: unreachable
	//			//
	//			//
	// CHECK5-LABEL: define {{[^@]+}}@_ZN1SD2Ev			// CHECK5-LABEL: define {{[^@]+}}@_ZN1SD2Ev
	// CHECK5-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR8]] comdat align 2 {			// CHECK5-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR8]] comdat align 2 {
	// CHECK5-NEXT: entry:			// CHECK5-NEXT: entry:
	// CHECK5-NEXT: [[THIS_ADDR:%.]] = alloca %struct.S, align 8			// CHECK5-NEXT: [[THIS_ADDR:%.]] = alloca %struct.S, align 8
	// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8			// CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
	▲ Show 20 Lines • Show All 153 Lines • ▼ Show 20 Lines
	// CHECK6-NEXT: br label [[COND_END]]			// CHECK6-NEXT: br label [[COND_END]]
	// CHECK6: cond.end:			// CHECK6: cond.end:
	// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]			// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
	// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK6-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK6-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK6-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK6-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK6: omp.inner.for.cond:			// CHECK6: omp.inner.for.cond:
	// CHECK6-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK6-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK6-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK6-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !9
	// CHECK6-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK6-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK6-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK6-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK6: omp.inner.for.body:			// CHECK6: omp.inner.for.body:
	// CHECK6-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 2)			// CHECK6-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 2), !llvm.access.group !9
	// CHECK6-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK6-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !9
	// CHECK6-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64			// CHECK6-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
	// CHECK6-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK6-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !9
	// CHECK6-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK6-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK6-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..1 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]])			// CHECK6-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..1 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !9
	// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK6: omp.inner.for.inc:			// CHECK6: omp.inner.for.inc:
	// CHECK6-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK6-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK6-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK6-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !9
	// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]			// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
	// CHECK6-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK6-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]]			// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]
	// CHECK6: omp.inner.for.end:			// CHECK6: omp.inner.for.end:
	// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK6: omp.loop.exit:			// CHECK6: omp.loop.exit:
	// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])			// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
	// CHECK6-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK6-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK6-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0			// CHECK6-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
	// CHECK6-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK6-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK6: .omp.final.then:			// CHECK6: .omp.final.then:
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	// CHECK6-NEXT: br label [[COND_END]]			// CHECK6-NEXT: br label [[COND_END]]
	// CHECK6: cond.end:			// CHECK6: cond.end:
	// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]			// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
	// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK6-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK6-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK6-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK6-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK6: omp.inner.for.cond:			// CHECK6: omp.inner.for.cond:
	// CHECK6-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK6-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK6-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK6-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !13
	// CHECK6-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK6-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK6-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK6-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK6: omp.inner.for.body:			// CHECK6: omp.inner.for.body:
	// CHECK6-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK6-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !13
	// CHECK6-NEXT: invoke void @_Z3foov()			// CHECK6-NEXT: invoke void @_Z3foov()
	// CHECK6-NEXT: to label [[INVOKE_CONT:%.]] unwind label [[TERMINATE_LPAD:%.]]			// CHECK6-NEXT: to label [[INVOKE_CONT:%.]] unwind label [[TERMINATE_LPAD:%.]], !llvm.access.group !13
	// CHECK6: invoke.cont:			// CHECK6: invoke.cont:
	// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK6: omp.body.continue:			// CHECK6: omp.body.continue:
	// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK6: omp.inner.for.inc:			// CHECK6: omp.inner.for.inc:
	// CHECK6-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK6-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK6-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK6-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK6-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4			// CHECK6-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]			// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]]
	// CHECK6: omp.inner.for.end:			// CHECK6: omp.inner.for.end:
	// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK6: omp.loop.exit:			// CHECK6: omp.loop.exit:
	// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])			// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
	// CHECK6-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK6-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK6-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK6-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK6-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK6-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK6: .omp.final.then:			// CHECK6: .omp.final.then:
	// CHECK6-NEXT: store i32 100, i32* [[I]], align 4			// CHECK6-NEXT: store i32 100, i32* [[I]], align 4
	// CHECK6-NEXT: br label [[DOTOMP_FINAL_DONE]]			// CHECK6-NEXT: br label [[DOTOMP_FINAL_DONE]]
	// CHECK6: .omp.final.done:			// CHECK6: .omp.final.done:
	// CHECK6-NEXT: ret void			// CHECK6-NEXT: ret void
	// CHECK6: terminate.lpad:			// CHECK6: terminate.lpad:
	// CHECK6-NEXT: [[TMP13:%.]] = landingpad { i8, i32 }			// CHECK6-NEXT: [[TMP13:%.]] = landingpad { i8, i32 }
	// CHECK6-NEXT: catch i8* null			// CHECK6-NEXT: catch i8* null
	// CHECK6-NEXT: [[TMP14:%.]] = extractvalue { i8, i32 } [[TMP13]], 0			// CHECK6-NEXT: [[TMP14:%.]] = extractvalue { i8, i32 } [[TMP13]], 0
	// CHECK6-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10:[0-9]+]]			// CHECK6-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10:[0-9]+]], !llvm.access.group !13
	// CHECK6-NEXT: unreachable			// CHECK6-NEXT: unreachable
	//			//
	//			//
	// CHECK6-LABEL: define {{[^@]+}}@__clang_call_terminate			// CHECK6-LABEL: define {{[^@]+}}@__clang_call_terminate
	// CHECK6-SAME: (i8* [[TMP0:%.*]]) #[[ATTR5:[0-9]+]] comdat {			// CHECK6-SAME: (i8* [[TMP0:%.*]]) #[[ATTR5:[0-9]+]] comdat {
	// CHECK6-NEXT: [[TMP2:%.]] = call i8 @__cxa_begin_catch(i8* [[TMP0]]) #[[ATTR6]]			// CHECK6-NEXT: [[TMP2:%.]] = call i8 @__cxa_begin_catch(i8* [[TMP0]]) #[[ATTR6]]
	// CHECK6-NEXT: call void @_ZSt9terminatev() #[[ATTR10]]			// CHECK6-NEXT: call void @_ZSt9terminatev() #[[ATTR10]]
	// CHECK6-NEXT: unreachable			// CHECK6-NEXT: unreachable
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	// CHECK6-NEXT: br label [[COND_END]]			// CHECK6-NEXT: br label [[COND_END]]
	// CHECK6: cond.end:			// CHECK6: cond.end:
	// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]			// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
	// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK6-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK6-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK6-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK6-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK6: omp.inner.for.cond:			// CHECK6: omp.inner.for.cond:
	// CHECK6-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK6-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK6-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK6-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !18
	// CHECK6-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK6-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK6-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK6-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK6: omp.inner.for.body:			// CHECK6: omp.inner.for.body:
	// CHECK6-NEXT: [[TMP8:%.]] = load i8, i8 [[TMP0]], align 1			// CHECK6-NEXT: [[TMP8:%.]] = load i8, i8 [[TMP0]], align 1, !llvm.access.group !18
	// CHECK6-NEXT: [[TMP9:%.*]] = sext i8 [[TMP8]] to i32			// CHECK6-NEXT: [[TMP9:%.*]] = sext i8 [[TMP8]] to i32
	// CHECK6-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP2]], i32 [[TMP9]])			// CHECK6-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP2]], i32 [[TMP9]]), !llvm.access.group !18
	// CHECK6-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK6-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !18
	// CHECK6-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64			// CHECK6-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
	// CHECK6-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK6-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !18
	// CHECK6-NEXT: [[TMP13:%.*]] = zext i32 [[TMP12]] to i64			// CHECK6-NEXT: [[TMP13:%.*]] = zext i32 [[TMP12]] to i64
	// CHECK6-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..3 to void (i32, i32, ...)*), i64 [[TMP11]], i64 [[TMP13]])			// CHECK6-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..3 to void (i32, i32, ...)*), i64 [[TMP11]], i64 [[TMP13]]), !llvm.access.group !18
	// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK6: omp.inner.for.inc:			// CHECK6: omp.inner.for.inc:
	// CHECK6-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK6-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK6-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK6-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !18
	// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP14]], [[TMP15]]			// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP14]], [[TMP15]]
	// CHECK6-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK6-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]			// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]
	// CHECK6: omp.inner.for.end:			// CHECK6: omp.inner.for.end:
	// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK6: omp.loop.exit:			// CHECK6: omp.loop.exit:
	// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])			// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
	// CHECK6-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK6-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK6-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0			// CHECK6-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0
	// CHECK6-NEXT: br i1 [[TMP17]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK6-NEXT: br i1 [[TMP17]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK6: .omp.final.then:			// CHECK6: .omp.final.then:
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	// CHECK6-NEXT: br label [[COND_END]]			// CHECK6-NEXT: br label [[COND_END]]
	// CHECK6: cond.end:			// CHECK6: cond.end:
	// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]			// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
	// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK6-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK6-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK6-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK6-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK6: omp.inner.for.cond:			// CHECK6: omp.inner.for.cond:
	// CHECK6-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK6-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !21
	// CHECK6-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK6-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !21
	// CHECK6-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK6-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK6-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK6-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK6: omp.inner.for.body:			// CHECK6: omp.inner.for.body:
	// CHECK6-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK6-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !21
	// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !21
	// CHECK6-NEXT: invoke void @_Z3foov()			// CHECK6-NEXT: invoke void @_Z3foov()
	// CHECK6-NEXT: to label [[INVOKE_CONT:%.]] unwind label [[TERMINATE_LPAD:%.]]			// CHECK6-NEXT: to label [[INVOKE_CONT:%.]] unwind label [[TERMINATE_LPAD:%.]], !llvm.access.group !21
	// CHECK6: invoke.cont:			// CHECK6: invoke.cont:
	// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK6: omp.body.continue:			// CHECK6: omp.body.continue:
	// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK6: omp.inner.for.inc:			// CHECK6: omp.inner.for.inc:
	// CHECK6-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK6-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !21
	// CHECK6-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK6-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK6-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4			// CHECK6-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
	// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]]			// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]]
	// CHECK6: omp.inner.for.end:			// CHECK6: omp.inner.for.end:
	// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK6: omp.loop.exit:			// CHECK6: omp.loop.exit:
	// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])			// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
	// CHECK6-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK6-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK6-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK6-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK6-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK6-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK6: .omp.final.then:			// CHECK6: .omp.final.then:
	// CHECK6-NEXT: store i32 100, i32* [[I]], align 4			// CHECK6-NEXT: store i32 100, i32* [[I]], align 4
	// CHECK6-NEXT: br label [[DOTOMP_FINAL_DONE]]			// CHECK6-NEXT: br label [[DOTOMP_FINAL_DONE]]
	// CHECK6: .omp.final.done:			// CHECK6: .omp.final.done:
	// CHECK6-NEXT: ret void			// CHECK6-NEXT: ret void
	// CHECK6: terminate.lpad:			// CHECK6: terminate.lpad:
	// CHECK6-NEXT: [[TMP13:%.]] = landingpad { i8, i32 }			// CHECK6-NEXT: [[TMP13:%.]] = landingpad { i8, i32 }
	// CHECK6-NEXT: catch i8* null			// CHECK6-NEXT: catch i8* null
	// CHECK6-NEXT: [[TMP14:%.]] = extractvalue { i8, i32 } [[TMP13]], 0			// CHECK6-NEXT: [[TMP14:%.]] = extractvalue { i8, i32 } [[TMP13]], 0
	// CHECK6-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]]			// CHECK6-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]], !llvm.access.group !21
	// CHECK6-NEXT: unreachable			// CHECK6-NEXT: unreachable
	//			//
	//			//
	// CHECK6-LABEL: define {{[^@]+}}@_Z5tmainIcLi5EEiv			// CHECK6-LABEL: define {{[^@]+}}@_Z5tmainIcLi5EEiv
	// CHECK6-SAME: () #[[ATTR7:[0-9]+]] comdat {			// CHECK6-SAME: () #[[ATTR7:[0-9]+]] comdat {
	// CHECK6-NEXT: entry:			// CHECK6-NEXT: entry:
	// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4			// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4
	// CHECK6-NEXT: [[_TMP1:%.*]] = alloca i32, align 4			// CHECK6-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
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	// CHECK6-NEXT: br label [[COND_END]]			// CHECK6-NEXT: br label [[COND_END]]
	// CHECK6: cond.end:			// CHECK6: cond.end:
	// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]			// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
	// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK6-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK6-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK6-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK6-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK6: omp.inner.for.cond:			// CHECK6: omp.inner.for.cond:
	// CHECK6-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK6-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !24
	// CHECK6-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK6-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !24
	// CHECK6-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK6-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK6-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK6-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK6: omp.inner.for.body:			// CHECK6: omp.inner.for.body:
	// CHECK6-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 5)			// CHECK6-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 5), !llvm.access.group !24
	// CHECK6-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK6-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !24
	// CHECK6-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64			// CHECK6-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
	// CHECK6-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK6-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !24
	// CHECK6-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK6-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK6-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..5 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]])			// CHECK6-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..5 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !24
	// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK6: omp.inner.for.inc:			// CHECK6: omp.inner.for.inc:
	// CHECK6-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK6-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !24
	// CHECK6-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK6-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !24
	// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]			// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
	// CHECK6-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK6-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
	// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]]			// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]]
	// CHECK6: omp.inner.for.end:			// CHECK6: omp.inner.for.end:
	// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK6: omp.loop.exit:			// CHECK6: omp.loop.exit:
	// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])			// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
	// CHECK6-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK6-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK6-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0			// CHECK6-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
	// CHECK6-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK6-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK6: .omp.final.then:			// CHECK6: .omp.final.then:
	▲ Show 20 Lines • Show All 44 Lines • ▼ Show 20 Lines
	// CHECK6-NEXT: br label [[COND_END]]			// CHECK6-NEXT: br label [[COND_END]]
	// CHECK6: cond.end:			// CHECK6: cond.end:
	// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]			// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
	// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK6-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK6-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK6-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK6-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK6: omp.inner.for.cond:			// CHECK6: omp.inner.for.cond:
	// CHECK6-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK6-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !27
	// CHECK6-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK6-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !27
	// CHECK6-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK6-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK6-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK6-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK6: omp.inner.for.body:			// CHECK6: omp.inner.for.body:
	// CHECK6-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK6-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !27
	// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !27
	// CHECK6-NEXT: invoke void @_Z3foov()			// CHECK6-NEXT: invoke void @_Z3foov()
	// CHECK6-NEXT: to label [[INVOKE_CONT:%.]] unwind label [[TERMINATE_LPAD:%.]]			// CHECK6-NEXT: to label [[INVOKE_CONT:%.]] unwind label [[TERMINATE_LPAD:%.]], !llvm.access.group !27
	// CHECK6: invoke.cont:			// CHECK6: invoke.cont:
	// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK6: omp.body.continue:			// CHECK6: omp.body.continue:
	// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK6: omp.inner.for.inc:			// CHECK6: omp.inner.for.inc:
	// CHECK6-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK6-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !27
	// CHECK6-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK6-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK6-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4			// CHECK6-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27
	// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]]			// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]]
	// CHECK6: omp.inner.for.end:			// CHECK6: omp.inner.for.end:
	// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK6: omp.loop.exit:			// CHECK6: omp.loop.exit:
	// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])			// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
	// CHECK6-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK6-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK6-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK6-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK6-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK6-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK6: .omp.final.then:			// CHECK6: .omp.final.then:
	// CHECK6-NEXT: store i32 100, i32* [[I]], align 4			// CHECK6-NEXT: store i32 100, i32* [[I]], align 4
	// CHECK6-NEXT: br label [[DOTOMP_FINAL_DONE]]			// CHECK6-NEXT: br label [[DOTOMP_FINAL_DONE]]
	// CHECK6: .omp.final.done:			// CHECK6: .omp.final.done:
	// CHECK6-NEXT: ret void			// CHECK6-NEXT: ret void
	// CHECK6: terminate.lpad:			// CHECK6: terminate.lpad:
	// CHECK6-NEXT: [[TMP13:%.]] = landingpad { i8, i32 }			// CHECK6-NEXT: [[TMP13:%.]] = landingpad { i8, i32 }
	// CHECK6-NEXT: catch i8* null			// CHECK6-NEXT: catch i8* null
	// CHECK6-NEXT: [[TMP14:%.]] = extractvalue { i8, i32 } [[TMP13]], 0			// CHECK6-NEXT: [[TMP14:%.]] = extractvalue { i8, i32 } [[TMP13]], 0
	// CHECK6-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]]			// CHECK6-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]], !llvm.access.group !27
	// CHECK6-NEXT: unreachable			// CHECK6-NEXT: unreachable
	//			//
	//			//
	// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l57			// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l57
	// CHECK6-SAME: () #[[ATTR3]] {			// CHECK6-SAME: () #[[ATTR3]] {
	// CHECK6-NEXT: entry:			// CHECK6-NEXT: entry:
	// CHECK6-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32, i32, ...)* bitcast (void (i32, i32)* @.omp_outlined..6 to void (i32, i32, ...)*))			// CHECK6-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32, i32, ...)* bitcast (void (i32, i32)* @.omp_outlined..6 to void (i32, i32, ...)*))
	// CHECK6-NEXT: ret void			// CHECK6-NEXT: ret void
	Show All 30 Lines
	// CHECK6-NEXT: br label [[COND_END]]			// CHECK6-NEXT: br label [[COND_END]]
	// CHECK6: cond.end:			// CHECK6: cond.end:
	// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]			// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
	// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK6-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK6-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK6-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK6-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK6: omp.inner.for.cond:			// CHECK6: omp.inner.for.cond:
	// CHECK6-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK6-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !30
	// CHECK6-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK6-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !30
	// CHECK6-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK6-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK6-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK6-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK6: omp.inner.for.body:			// CHECK6: omp.inner.for.body:
	// CHECK6-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 23)			// CHECK6-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 23), !llvm.access.group !30
	// CHECK6-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK6-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !30
	// CHECK6-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64			// CHECK6-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
	// CHECK6-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK6-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !30
	// CHECK6-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK6-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK6-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..7 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]])			// CHECK6-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..7 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !30
	// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK6: omp.inner.for.inc:			// CHECK6: omp.inner.for.inc:
	// CHECK6-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK6-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !30
	// CHECK6-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK6-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !30
	// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]			// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
	// CHECK6-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK6-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30
	// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]]			// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP31:![0-9]+]]
	// CHECK6: omp.inner.for.end:			// CHECK6: omp.inner.for.end:
	// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK6: omp.loop.exit:			// CHECK6: omp.loop.exit:
	// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])			// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
	// CHECK6-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK6-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK6-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0			// CHECK6-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
	// CHECK6-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK6-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK6: .omp.final.then:			// CHECK6: .omp.final.then:
	▲ Show 20 Lines • Show All 44 Lines • ▼ Show 20 Lines
	// CHECK6-NEXT: br label [[COND_END]]			// CHECK6-NEXT: br label [[COND_END]]
	// CHECK6: cond.end:			// CHECK6: cond.end:
	// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]			// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
	// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK6-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK6-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK6-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK6-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK6: omp.inner.for.cond:			// CHECK6: omp.inner.for.cond:
	// CHECK6-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK6-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !33
	// CHECK6-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK6-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !33
	// CHECK6-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK6-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK6-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK6-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK6: omp.inner.for.body:			// CHECK6: omp.inner.for.body:
	// CHECK6-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK6-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !33
	// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !33
	// CHECK6-NEXT: invoke void @_Z3foov()			// CHECK6-NEXT: invoke void @_Z3foov()
	// CHECK6-NEXT: to label [[INVOKE_CONT:%.]] unwind label [[TERMINATE_LPAD:%.]]			// CHECK6-NEXT: to label [[INVOKE_CONT:%.]] unwind label [[TERMINATE_LPAD:%.]], !llvm.access.group !33
	// CHECK6: invoke.cont:			// CHECK6: invoke.cont:
	// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK6: omp.body.continue:			// CHECK6: omp.body.continue:
	// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK6: omp.inner.for.inc:			// CHECK6: omp.inner.for.inc:
	// CHECK6-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK6-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !33
	// CHECK6-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK6-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK6-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4			// CHECK6-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33
	// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]]			// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP34:![0-9]+]]
	// CHECK6: omp.inner.for.end:			// CHECK6: omp.inner.for.end:
	// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK6: omp.loop.exit:			// CHECK6: omp.loop.exit:
	// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])			// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
	// CHECK6-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK6-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK6-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK6-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK6-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK6-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK6: .omp.final.then:			// CHECK6: .omp.final.then:
	// CHECK6-NEXT: store i32 100, i32* [[I]], align 4			// CHECK6-NEXT: store i32 100, i32* [[I]], align 4
	// CHECK6-NEXT: br label [[DOTOMP_FINAL_DONE]]			// CHECK6-NEXT: br label [[DOTOMP_FINAL_DONE]]
	// CHECK6: .omp.final.done:			// CHECK6: .omp.final.done:
	// CHECK6-NEXT: ret void			// CHECK6-NEXT: ret void
	// CHECK6: terminate.lpad:			// CHECK6: terminate.lpad:
	// CHECK6-NEXT: [[TMP13:%.]] = landingpad { i8, i32 }			// CHECK6-NEXT: [[TMP13:%.]] = landingpad { i8, i32 }
	// CHECK6-NEXT: catch i8* null			// CHECK6-NEXT: catch i8* null
	// CHECK6-NEXT: [[TMP14:%.]] = extractvalue { i8, i32 } [[TMP13]], 0			// CHECK6-NEXT: [[TMP14:%.]] = extractvalue { i8, i32 } [[TMP13]], 0
	// CHECK6-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]]			// CHECK6-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]], !llvm.access.group !33
	// CHECK6-NEXT: unreachable			// CHECK6-NEXT: unreachable
	//			//
	//			//
	// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l52			// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l52
	// CHECK6-SAME: () #[[ATTR3]] {			// CHECK6-SAME: () #[[ATTR3]] {
	// CHECK6-NEXT: entry:			// CHECK6-NEXT: entry:
	// CHECK6-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32, i32, ...)* bitcast (void (i32, i32)* @.omp_outlined..8 to void (i32, i32, ...)*))			// CHECK6-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32, i32, ...)* bitcast (void (i32, i32)* @.omp_outlined..8 to void (i32, i32, ...)*))
	// CHECK6-NEXT: ret void			// CHECK6-NEXT: ret void
	Show All 30 Lines
	// CHECK6-NEXT: br label [[COND_END]]			// CHECK6-NEXT: br label [[COND_END]]
	// CHECK6: cond.end:			// CHECK6: cond.end:
	// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]			// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
	// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK6-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK6-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK6-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK6-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK6: omp.inner.for.cond:			// CHECK6: omp.inner.for.cond:
	// CHECK6-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK6-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !36
	// CHECK6-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK6-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !36
	// CHECK6-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK6-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK6-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK6-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK6: omp.inner.for.body:			// CHECK6: omp.inner.for.body:
	// CHECK6-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 1)			// CHECK6-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 1), !llvm.access.group !36
	// CHECK6-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK6-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !36
	// CHECK6-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64			// CHECK6-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
	// CHECK6-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK6-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !36
	// CHECK6-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK6-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK6-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..9 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]])			// CHECK6-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..9 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !36
	// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK6: omp.inner.for.inc:			// CHECK6: omp.inner.for.inc:
	// CHECK6-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK6-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !36
	// CHECK6-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK6-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !36
	// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]			// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
	// CHECK6-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK6-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36
	// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]			// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP37:![0-9]+]]
	// CHECK6: omp.inner.for.end:			// CHECK6: omp.inner.for.end:
	// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK6: omp.loop.exit:			// CHECK6: omp.loop.exit:
	// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])			// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
	// CHECK6-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK6-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK6-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0			// CHECK6-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
	// CHECK6-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK6-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK6: .omp.final.then:			// CHECK6: .omp.final.then:
	▲ Show 20 Lines • Show All 44 Lines • ▼ Show 20 Lines
	// CHECK6-NEXT: br label [[COND_END]]			// CHECK6-NEXT: br label [[COND_END]]
	// CHECK6: cond.end:			// CHECK6: cond.end:
	// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]			// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
	// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK6-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK6-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK6-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK6-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK6: omp.inner.for.cond:			// CHECK6: omp.inner.for.cond:
	// CHECK6-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK6-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !39
	// CHECK6-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK6-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !39
	// CHECK6-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK6-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK6-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK6-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK6: omp.inner.for.body:			// CHECK6: omp.inner.for.body:
	// CHECK6-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK6-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !39
	// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !39
	// CHECK6-NEXT: invoke void @_Z3foov()			// CHECK6-NEXT: invoke void @_Z3foov()
	// CHECK6-NEXT: to label [[INVOKE_CONT:%.]] unwind label [[TERMINATE_LPAD:%.]]			// CHECK6-NEXT: to label [[INVOKE_CONT:%.]] unwind label [[TERMINATE_LPAD:%.]], !llvm.access.group !39
	// CHECK6: invoke.cont:			// CHECK6: invoke.cont:
	// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK6: omp.body.continue:			// CHECK6: omp.body.continue:
	// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK6: omp.inner.for.inc:			// CHECK6: omp.inner.for.inc:
	// CHECK6-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK6-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !39
	// CHECK6-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK6-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK6-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4			// CHECK6-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39
	// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]]			// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP40:![0-9]+]]
	// CHECK6: omp.inner.for.end:			// CHECK6: omp.inner.for.end:
	// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK6: omp.loop.exit:			// CHECK6: omp.loop.exit:
	// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])			// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
	// CHECK6-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK6-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK6-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK6-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK6-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK6-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK6: .omp.final.then:			// CHECK6: .omp.final.then:
	// CHECK6-NEXT: store i32 100, i32* [[I]], align 4			// CHECK6-NEXT: store i32 100, i32* [[I]], align 4
	// CHECK6-NEXT: br label [[DOTOMP_FINAL_DONE]]			// CHECK6-NEXT: br label [[DOTOMP_FINAL_DONE]]
	// CHECK6: .omp.final.done:			// CHECK6: .omp.final.done:
	// CHECK6-NEXT: ret void			// CHECK6-NEXT: ret void
	// CHECK6: terminate.lpad:			// CHECK6: terminate.lpad:
	// CHECK6-NEXT: [[TMP13:%.]] = landingpad { i8, i32 }			// CHECK6-NEXT: [[TMP13:%.]] = landingpad { i8, i32 }
	// CHECK6-NEXT: catch i8* null			// CHECK6-NEXT: catch i8* null
	// CHECK6-NEXT: [[TMP14:%.]] = extractvalue { i8, i32 } [[TMP13]], 0			// CHECK6-NEXT: [[TMP14:%.]] = extractvalue { i8, i32 } [[TMP13]], 0
	// CHECK6-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]]			// CHECK6-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]], !llvm.access.group !39
	// CHECK6-NEXT: unreachable			// CHECK6-NEXT: unreachable
	//			//
	//			//
	// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l57			// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l57
	// CHECK6-SAME: () #[[ATTR3]] {			// CHECK6-SAME: () #[[ATTR3]] {
	// CHECK6-NEXT: entry:			// CHECK6-NEXT: entry:
	// CHECK6-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32, i32, ...)* bitcast (void (i32, i32)* @.omp_outlined..10 to void (i32, i32, ...)*))			// CHECK6-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32, i32, ...)* bitcast (void (i32, i32)* @.omp_outlined..10 to void (i32, i32, ...)*))
	// CHECK6-NEXT: ret void			// CHECK6-NEXT: ret void
	Show All 33 Lines
	// CHECK6-NEXT: br label [[COND_END]]			// CHECK6-NEXT: br label [[COND_END]]
	// CHECK6: cond.end:			// CHECK6: cond.end:
	// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]			// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
	// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK6-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK6-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK6-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK6-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK6: omp.inner.for.cond:			// CHECK6: omp.inner.for.cond:
	// CHECK6-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK6-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !42
	// CHECK6-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK6-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !42
	// CHECK6-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK6-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK6-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK6-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK6: omp.inner.for.body:			// CHECK6: omp.inner.for.body:
	// CHECK6-NEXT: invoke void @_ZN1SC1El(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]], i64 23)			// CHECK6-NEXT: invoke void @_ZN1SC1El(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]], i64 23)
	// CHECK6-NEXT: to label [[INVOKE_CONT:%.]] unwind label [[TERMINATE_LPAD:%.]]			// CHECK6-NEXT: to label [[INVOKE_CONT:%.]] unwind label [[TERMINATE_LPAD:%.]], !llvm.access.group !42
	// CHECK6: invoke.cont:			// CHECK6: invoke.cont:
	// CHECK6-NEXT: [[CALL:%.]] = invoke signext i8 @_ZN1ScvcEv(%struct.S nonnull align 8 dereferenceable(24) [[REF_TMP]])			// CHECK6-NEXT: [[CALL:%.]] = invoke signext i8 @_ZN1ScvcEv(%struct.S nonnull align 8 dereferenceable(24) [[REF_TMP]])
	// CHECK6-NEXT: to label [[INVOKE_CONT2:%.]] unwind label [[LPAD:%.]]			// CHECK6-NEXT: to label [[INVOKE_CONT2:%.]] unwind label [[LPAD:%.]], !llvm.access.group !42
	// CHECK6: invoke.cont2:			// CHECK6: invoke.cont2:
	// CHECK6-NEXT: [[TMP7:%.*]] = sext i8 [[CALL]] to i32			// CHECK6-NEXT: [[TMP7:%.*]] = sext i8 [[CALL]] to i32
	// CHECK6-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 [[TMP7]])			// CHECK6-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 [[TMP7]]), !llvm.access.group !42
	// CHECK6-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR6]]			// CHECK6-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR6]], !llvm.access.group !42
	// CHECK6-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK6-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !42
	// CHECK6-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64			// CHECK6-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
	// CHECK6-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK6-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !42
	// CHECK6-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64			// CHECK6-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
	// CHECK6-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..11 to void (i32, i32, ...)*), i64 [[TMP9]], i64 [[TMP11]])			// CHECK6-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..11 to void (i32, i32, ...)*), i64 [[TMP9]], i64 [[TMP11]]), !llvm.access.group !42
	// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK6: omp.inner.for.inc:			// CHECK6: omp.inner.for.inc:
	// CHECK6-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK6-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !42
	// CHECK6-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK6-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !42
	// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]			// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]
	// CHECK6-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK6-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !42
	// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]]			// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP43:![0-9]+]]
	// CHECK6: lpad:			// CHECK6: lpad:
	// CHECK6-NEXT: [[TMP14:%.]] = landingpad { i8, i32 }			// CHECK6-NEXT: [[TMP14:%.]] = landingpad { i8, i32 }
	// CHECK6-NEXT: catch i8* null			// CHECK6-NEXT: catch i8* null
	// CHECK6-NEXT: [[TMP15:%.]] = extractvalue { i8, i32 } [[TMP14]], 0			// CHECK6-NEXT: [[TMP15:%.]] = extractvalue { i8, i32 } [[TMP14]], 0
	// CHECK6-NEXT: store i8* [[TMP15]], i8** [[EXN_SLOT]], align 8			// CHECK6-NEXT: store i8* [[TMP15]], i8** [[EXN_SLOT]], align 8, !llvm.access.group !42
	// CHECK6-NEXT: [[TMP16:%.]] = extractvalue { i8, i32 } [[TMP14]], 1			// CHECK6-NEXT: [[TMP16:%.]] = extractvalue { i8, i32 } [[TMP14]], 1
	// CHECK6-NEXT: store i32 [[TMP16]], i32* [[EHSELECTOR_SLOT]], align 4			// CHECK6-NEXT: store i32 [[TMP16]], i32* [[EHSELECTOR_SLOT]], align 4, !llvm.access.group !42
	// CHECK6-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR6]]			// CHECK6-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR6]], !llvm.access.group !42
	// CHECK6-NEXT: br label [[TERMINATE_HANDLER:%.*]]			// CHECK6-NEXT: br label [[TERMINATE_HANDLER:%.*]]
	// CHECK6: omp.inner.for.end:			// CHECK6: omp.inner.for.end:
	// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK6: omp.loop.exit:			// CHECK6: omp.loop.exit:
	// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])			// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
	// CHECK6-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK6-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK6-NEXT: [[TMP18:%.*]] = icmp ne i32 [[TMP17]], 0			// CHECK6-NEXT: [[TMP18:%.*]] = icmp ne i32 [[TMP17]], 0
	// CHECK6-NEXT: br i1 [[TMP18]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK6-NEXT: br i1 [[TMP18]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK6: .omp.final.then:			// CHECK6: .omp.final.then:
	// CHECK6-NEXT: store i32 100, i32* [[I]], align 4			// CHECK6-NEXT: store i32 100, i32* [[I]], align 4
	// CHECK6-NEXT: br label [[DOTOMP_FINAL_DONE]]			// CHECK6-NEXT: br label [[DOTOMP_FINAL_DONE]]
	// CHECK6: .omp.final.done:			// CHECK6: .omp.final.done:
	// CHECK6-NEXT: ret void			// CHECK6-NEXT: ret void
	// CHECK6: terminate.lpad:			// CHECK6: terminate.lpad:
	// CHECK6-NEXT: [[TMP19:%.]] = landingpad { i8, i32 }			// CHECK6-NEXT: [[TMP19:%.]] = landingpad { i8, i32 }
	// CHECK6-NEXT: catch i8* null			// CHECK6-NEXT: catch i8* null
	// CHECK6-NEXT: [[TMP20:%.]] = extractvalue { i8, i32 } [[TMP19]], 0			// CHECK6-NEXT: [[TMP20:%.]] = extractvalue { i8, i32 } [[TMP19]], 0
	// CHECK6-NEXT: call void @__clang_call_terminate(i8* [[TMP20]]) #[[ATTR10]]			// CHECK6-NEXT: call void @__clang_call_terminate(i8* [[TMP20]]) #[[ATTR10]], !llvm.access.group !42
	// CHECK6-NEXT: unreachable			// CHECK6-NEXT: unreachable
	// CHECK6: terminate.handler:			// CHECK6: terminate.handler:
	// CHECK6-NEXT: [[EXN:%.]] = load i8, i8** [[EXN_SLOT]], align 8			// CHECK6-NEXT: [[EXN:%.]] = load i8, i8** [[EXN_SLOT]], align 8, !llvm.access.group !42
	// CHECK6-NEXT: call void @__clang_call_terminate(i8* [[EXN]]) #[[ATTR10]]			// CHECK6-NEXT: call void @__clang_call_terminate(i8* [[EXN]]) #[[ATTR10]], !llvm.access.group !42
	// CHECK6-NEXT: unreachable			// CHECK6-NEXT: unreachable
	//			//
	//			//
	// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..11			// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..11
	// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i64 [[DOTPREVIOUS_LB_:%.]], i64 [[DOTPREVIOUS_UB_:%.]]) #[[ATTR3]] personality i8 bitcast (i32 (...)* @__gxx_personality_v0 to i8*) {			// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i64 [[DOTPREVIOUS_LB_:%.]], i64 [[DOTPREVIOUS_UB_:%.]]) #[[ATTR3]] personality i8 bitcast (i32 (...)* @__gxx_personality_v0 to i8*) {
	// CHECK6-NEXT: entry:			// CHECK6-NEXT: entry:
	// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8			// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8
	// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8			// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8
	Show All 33 Lines
	// CHECK6-NEXT: br label [[COND_END]]			// CHECK6-NEXT: br label [[COND_END]]
	// CHECK6: cond.end:			// CHECK6: cond.end:
	// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]			// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
	// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK6-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK6-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK6-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK6-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK6: omp.inner.for.cond:			// CHECK6: omp.inner.for.cond:
	// CHECK6-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK6-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !45
	// CHECK6-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK6-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !45
	// CHECK6-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK6-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK6-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK6-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK6: omp.inner.for.body:			// CHECK6: omp.inner.for.body:
	// CHECK6-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK6-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !45
	// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !45
	// CHECK6-NEXT: invoke void @_Z3foov()			// CHECK6-NEXT: invoke void @_Z3foov()
	// CHECK6-NEXT: to label [[INVOKE_CONT:%.]] unwind label [[TERMINATE_LPAD:%.]]			// CHECK6-NEXT: to label [[INVOKE_CONT:%.]] unwind label [[TERMINATE_LPAD:%.]], !llvm.access.group !45
	// CHECK6: invoke.cont:			// CHECK6: invoke.cont:
	// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK6: omp.body.continue:			// CHECK6: omp.body.continue:
	// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK6: omp.inner.for.inc:			// CHECK6: omp.inner.for.inc:
	// CHECK6-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK6-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !45
	// CHECK6-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK6-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK6-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4			// CHECK6-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !45
	// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]]			// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP46:![0-9]+]]
	// CHECK6: omp.inner.for.end:			// CHECK6: omp.inner.for.end:
	// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK6: omp.loop.exit:			// CHECK6: omp.loop.exit:
	// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])			// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
	// CHECK6-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK6-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK6-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK6-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK6-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK6-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK6: .omp.final.then:			// CHECK6: .omp.final.then:
	// CHECK6-NEXT: store i32 100, i32* [[I]], align 4			// CHECK6-NEXT: store i32 100, i32* [[I]], align 4
	// CHECK6-NEXT: br label [[DOTOMP_FINAL_DONE]]			// CHECK6-NEXT: br label [[DOTOMP_FINAL_DONE]]
	// CHECK6: .omp.final.done:			// CHECK6: .omp.final.done:
	// CHECK6-NEXT: ret void			// CHECK6-NEXT: ret void
	// CHECK6: terminate.lpad:			// CHECK6: terminate.lpad:
	// CHECK6-NEXT: [[TMP13:%.]] = landingpad { i8, i32 }			// CHECK6-NEXT: [[TMP13:%.]] = landingpad { i8, i32 }
	// CHECK6-NEXT: catch i8* null			// CHECK6-NEXT: catch i8* null
	// CHECK6-NEXT: [[TMP14:%.]] = extractvalue { i8, i32 } [[TMP13]], 0			// CHECK6-NEXT: [[TMP14:%.]] = extractvalue { i8, i32 } [[TMP13]], 0
	// CHECK6-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]]			// CHECK6-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]], !llvm.access.group !45
	// CHECK6-NEXT: unreachable			// CHECK6-NEXT: unreachable
	//			//
	//			//
	// CHECK6-LABEL: define {{[^@]+}}@_ZN1SD2Ev			// CHECK6-LABEL: define {{[^@]+}}@_ZN1SD2Ev
	// CHECK6-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR8]] comdat align 2 {			// CHECK6-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR8]] comdat align 2 {
	// CHECK6-NEXT: entry:			// CHECK6-NEXT: entry:
	// CHECK6-NEXT: [[THIS_ADDR:%.]] = alloca %struct.S, align 8			// CHECK6-NEXT: [[THIS_ADDR:%.]] = alloca %struct.S, align 8
	// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8			// CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
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	// CHECK9-NEXT: br label [[COND_END]]			// CHECK9-NEXT: br label [[COND_END]]
	// CHECK9: cond.end:			// CHECK9: cond.end:
	// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]			// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
	// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK9-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK9-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK9: omp.inner.for.cond:			// CHECK9: omp.inner.for.cond:
	// CHECK9-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK9-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK9-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !13
	// CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK9: omp.inner.for.body:			// CHECK9: omp.inner.for.body:
	// CHECK9-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 2)			// CHECK9-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 2), !llvm.access.group !13
	// CHECK9-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK9-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !13
	// CHECK9-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64			// CHECK9-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
	// CHECK9-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK9-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !13
	// CHECK9-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK9-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK9-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..1 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]])			// CHECK9-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..1 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !13
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK9: omp.inner.for.inc:			// CHECK9: omp.inner.for.inc:
	// CHECK9-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK9-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK9-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !13
	// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]			// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
	// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]]
	// CHECK9: omp.inner.for.end:			// CHECK9: omp.inner.for.end:
	// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK9: omp.loop.exit:			// CHECK9: omp.loop.exit:
	// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])			// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
	// CHECK9-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK9-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK9-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0			// CHECK9-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
	// CHECK9-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK9-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK9: .omp.final.then:			// CHECK9: .omp.final.then:
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	// CHECK9-NEXT: br label [[COND_END]]			// CHECK9-NEXT: br label [[COND_END]]
	// CHECK9: cond.end:			// CHECK9: cond.end:
	// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]			// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
	// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK9-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK9-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK9: omp.inner.for.cond:			// CHECK9: omp.inner.for.cond:
	// CHECK9-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !17
	// CHECK9-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK9-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !17
	// CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK9: omp.inner.for.body:			// CHECK9: omp.inner.for.body:
	// CHECK9-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !17
	// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !17
	// CHECK9-NEXT: invoke void @_Z3foov()			// CHECK9-NEXT: invoke void @_Z3foov()
	// CHECK9-NEXT: to label [[INVOKE_CONT:%.]] unwind label [[TERMINATE_LPAD:%.]]			// CHECK9-NEXT: to label [[INVOKE_CONT:%.]] unwind label [[TERMINATE_LPAD:%.]], !llvm.access.group !17
	// CHECK9: invoke.cont:			// CHECK9: invoke.cont:
	// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK9: omp.body.continue:			// CHECK9: omp.body.continue:
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK9: omp.inner.for.inc:			// CHECK9: omp.inner.for.inc:
	// CHECK9-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !17
	// CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK9-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4			// CHECK9-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]]
	// CHECK9: omp.inner.for.end:			// CHECK9: omp.inner.for.end:
	// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK9: omp.loop.exit:			// CHECK9: omp.loop.exit:
	// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])			// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
	// CHECK9-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK9-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK9-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK9-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK9-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK9-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK9: .omp.final.then:			// CHECK9: .omp.final.then:
	// CHECK9-NEXT: store i32 100, i32* [[I]], align 4			// CHECK9-NEXT: store i32 100, i32* [[I]], align 4
	// CHECK9-NEXT: br label [[DOTOMP_FINAL_DONE]]			// CHECK9-NEXT: br label [[DOTOMP_FINAL_DONE]]
	// CHECK9: .omp.final.done:			// CHECK9: .omp.final.done:
	// CHECK9-NEXT: ret void			// CHECK9-NEXT: ret void
	// CHECK9: terminate.lpad:			// CHECK9: terminate.lpad:
	// CHECK9-NEXT: [[TMP13:%.]] = landingpad { i8, i32 }			// CHECK9-NEXT: [[TMP13:%.]] = landingpad { i8, i32 }
	// CHECK9-NEXT: catch i8* null			// CHECK9-NEXT: catch i8* null
	// CHECK9-NEXT: [[TMP14:%.]] = extractvalue { i8, i32 } [[TMP13]], 0			// CHECK9-NEXT: [[TMP14:%.]] = extractvalue { i8, i32 } [[TMP13]], 0
	// CHECK9-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10:[0-9]+]]			// CHECK9-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10:[0-9]+]], !llvm.access.group !17
	// CHECK9-NEXT: unreachable			// CHECK9-NEXT: unreachable
	//			//
	//			//
	// CHECK9-LABEL: define {{[^@]+}}@__clang_call_terminate			// CHECK9-LABEL: define {{[^@]+}}@__clang_call_terminate
	// CHECK9-SAME: (i8* [[TMP0:%.*]]) #[[ATTR5:[0-9]+]] comdat {			// CHECK9-SAME: (i8* [[TMP0:%.*]]) #[[ATTR5:[0-9]+]] comdat {
	// CHECK9-NEXT: [[TMP2:%.]] = call i8 @__cxa_begin_catch(i8* [[TMP0]]) #[[ATTR6]]			// CHECK9-NEXT: [[TMP2:%.]] = call i8 @__cxa_begin_catch(i8* [[TMP0]]) #[[ATTR6]]
	// CHECK9-NEXT: call void @_ZSt9terminatev() #[[ATTR10]]			// CHECK9-NEXT: call void @_ZSt9terminatev() #[[ATTR10]]
	// CHECK9-NEXT: unreachable			// CHECK9-NEXT: unreachable
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	// CHECK9-NEXT: br label [[COND_END]]			// CHECK9-NEXT: br label [[COND_END]]
	// CHECK9: cond.end:			// CHECK9: cond.end:
	// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]			// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
	// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK9-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK9-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK9: omp.inner.for.cond:			// CHECK9: omp.inner.for.cond:
	// CHECK9-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !22
	// CHECK9-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK9-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !22
	// CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK9: omp.inner.for.body:			// CHECK9: omp.inner.for.body:
	// CHECK9-NEXT: [[TMP8:%.]] = load i8, i8 [[TMP0]], align 1			// CHECK9-NEXT: [[TMP8:%.]] = load i8, i8 [[TMP0]], align 1, !llvm.access.group !22
	// CHECK9-NEXT: [[TMP9:%.*]] = sext i8 [[TMP8]] to i32			// CHECK9-NEXT: [[TMP9:%.*]] = sext i8 [[TMP8]] to i32
	// CHECK9-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP2]], i32 [[TMP9]])			// CHECK9-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP2]], i32 [[TMP9]]), !llvm.access.group !22
	// CHECK9-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK9-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !22
	// CHECK9-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64			// CHECK9-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
	// CHECK9-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK9-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !22
	// CHECK9-NEXT: [[TMP13:%.*]] = zext i32 [[TMP12]] to i64			// CHECK9-NEXT: [[TMP13:%.*]] = zext i32 [[TMP12]] to i64
	// CHECK9-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..3 to void (i32, i32, ...)*), i64 [[TMP11]], i64 [[TMP13]])			// CHECK9-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..3 to void (i32, i32, ...)*), i64 [[TMP11]], i64 [[TMP13]]), !llvm.access.group !22
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK9: omp.inner.for.inc:			// CHECK9: omp.inner.for.inc:
	// CHECK9-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !22
	// CHECK9-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK9-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !22
	// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP14]], [[TMP15]]			// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP14]], [[TMP15]]
	// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]]
	// CHECK9: omp.inner.for.end:			// CHECK9: omp.inner.for.end:
	// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK9: omp.loop.exit:			// CHECK9: omp.loop.exit:
	// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])			// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
	// CHECK9-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK9-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK9-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0			// CHECK9-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0
	// CHECK9-NEXT: br i1 [[TMP17]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK9-NEXT: br i1 [[TMP17]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK9: .omp.final.then:			// CHECK9: .omp.final.then:
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	// CHECK9-NEXT: br label [[COND_END]]			// CHECK9-NEXT: br label [[COND_END]]
	// CHECK9: cond.end:			// CHECK9: cond.end:
	// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]			// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
	// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK9-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK9-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK9: omp.inner.for.cond:			// CHECK9: omp.inner.for.cond:
	// CHECK9-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !25
	// CHECK9-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK9-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !25
	// CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK9: omp.inner.for.body:			// CHECK9: omp.inner.for.body:
	// CHECK9-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !25
	// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !25
	// CHECK9-NEXT: invoke void @_Z3foov()			// CHECK9-NEXT: invoke void @_Z3foov()
	// CHECK9-NEXT: to label [[INVOKE_CONT:%.]] unwind label [[TERMINATE_LPAD:%.]]			// CHECK9-NEXT: to label [[INVOKE_CONT:%.]] unwind label [[TERMINATE_LPAD:%.]], !llvm.access.group !25
	// CHECK9: invoke.cont:			// CHECK9: invoke.cont:
	// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK9: omp.body.continue:			// CHECK9: omp.body.continue:
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK9: omp.inner.for.inc:			// CHECK9: omp.inner.for.inc:
	// CHECK9-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !25
	// CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK9-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4			// CHECK9-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP26:![0-9]+]]
	// CHECK9: omp.inner.for.end:			// CHECK9: omp.inner.for.end:
	// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK9: omp.loop.exit:			// CHECK9: omp.loop.exit:
	// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])			// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
	// CHECK9-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK9-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK9-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK9-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK9-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK9-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK9: .omp.final.then:			// CHECK9: .omp.final.then:
	// CHECK9-NEXT: store i32 100, i32* [[I]], align 4			// CHECK9-NEXT: store i32 100, i32* [[I]], align 4
	// CHECK9-NEXT: br label [[DOTOMP_FINAL_DONE]]			// CHECK9-NEXT: br label [[DOTOMP_FINAL_DONE]]
	// CHECK9: .omp.final.done:			// CHECK9: .omp.final.done:
	// CHECK9-NEXT: ret void			// CHECK9-NEXT: ret void
	// CHECK9: terminate.lpad:			// CHECK9: terminate.lpad:
	// CHECK9-NEXT: [[TMP13:%.]] = landingpad { i8, i32 }			// CHECK9-NEXT: [[TMP13:%.]] = landingpad { i8, i32 }
	// CHECK9-NEXT: catch i8* null			// CHECK9-NEXT: catch i8* null
	// CHECK9-NEXT: [[TMP14:%.]] = extractvalue { i8, i32 } [[TMP13]], 0			// CHECK9-NEXT: [[TMP14:%.]] = extractvalue { i8, i32 } [[TMP13]], 0
	// CHECK9-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]]			// CHECK9-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]], !llvm.access.group !25
	// CHECK9-NEXT: unreachable			// CHECK9-NEXT: unreachable
	//			//
	//			//
	// CHECK9-LABEL: define {{[^@]+}}@_Z5tmainIcLi5EEiv			// CHECK9-LABEL: define {{[^@]+}}@_Z5tmainIcLi5EEiv
	// CHECK9-SAME: () #[[ATTR7:[0-9]+]] comdat {			// CHECK9-SAME: () #[[ATTR7:[0-9]+]] comdat {
	// CHECK9-NEXT: entry:			// CHECK9-NEXT: entry:
	// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4			// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4
	// CHECK9-NEXT: [[_TMP1:%.*]] = alloca i32, align 4			// CHECK9-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
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	// CHECK9-NEXT: br label [[COND_END]]			// CHECK9-NEXT: br label [[COND_END]]
	// CHECK9: cond.end:			// CHECK9: cond.end:
	// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]			// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
	// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK9-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK9-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK9: omp.inner.for.cond:			// CHECK9: omp.inner.for.cond:
	// CHECK9-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !28
	// CHECK9-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK9-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !28
	// CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK9: omp.inner.for.body:			// CHECK9: omp.inner.for.body:
	// CHECK9-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 5)			// CHECK9-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 5), !llvm.access.group !28
	// CHECK9-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK9-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !28
	// CHECK9-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64			// CHECK9-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
	// CHECK9-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK9-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !28
	// CHECK9-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK9-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK9-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..5 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]])			// CHECK9-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..5 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !28
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK9: omp.inner.for.inc:			// CHECK9: omp.inner.for.inc:
	// CHECK9-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !28
	// CHECK9-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK9-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !28
	// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]			// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
	// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP29:![0-9]+]]
	// CHECK9: omp.inner.for.end:			// CHECK9: omp.inner.for.end:
	// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK9: omp.loop.exit:			// CHECK9: omp.loop.exit:
	// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])			// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
	// CHECK9-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK9-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK9-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0			// CHECK9-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
	// CHECK9-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK9-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK9: .omp.final.then:			// CHECK9: .omp.final.then:
	▲ Show 20 Lines • Show All 44 Lines • ▼ Show 20 Lines
	// CHECK9-NEXT: br label [[COND_END]]			// CHECK9-NEXT: br label [[COND_END]]
	// CHECK9: cond.end:			// CHECK9: cond.end:
	// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]			// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
	// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK9-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK9-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK9: omp.inner.for.cond:			// CHECK9: omp.inner.for.cond:
	// CHECK9-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !31
	// CHECK9-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK9-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !31
	// CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK9: omp.inner.for.body:			// CHECK9: omp.inner.for.body:
	// CHECK9-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !31
	// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !31
	// CHECK9-NEXT: invoke void @_Z3foov()			// CHECK9-NEXT: invoke void @_Z3foov()
	// CHECK9-NEXT: to label [[INVOKE_CONT:%.]] unwind label [[TERMINATE_LPAD:%.]]			// CHECK9-NEXT: to label [[INVOKE_CONT:%.]] unwind label [[TERMINATE_LPAD:%.]], !llvm.access.group !31
	// CHECK9: invoke.cont:			// CHECK9: invoke.cont:
	// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK9: omp.body.continue:			// CHECK9: omp.body.continue:
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK9: omp.inner.for.inc:			// CHECK9: omp.inner.for.inc:
	// CHECK9-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !31
	// CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK9-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4			// CHECK9-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !31
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP32:![0-9]+]]
	// CHECK9: omp.inner.for.end:			// CHECK9: omp.inner.for.end:
	// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK9: omp.loop.exit:			// CHECK9: omp.loop.exit:
	// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])			// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
	// CHECK9-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK9-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK9-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK9-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK9-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK9-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK9: .omp.final.then:			// CHECK9: .omp.final.then:
	// CHECK9-NEXT: store i32 100, i32* [[I]], align 4			// CHECK9-NEXT: store i32 100, i32* [[I]], align 4
	// CHECK9-NEXT: br label [[DOTOMP_FINAL_DONE]]			// CHECK9-NEXT: br label [[DOTOMP_FINAL_DONE]]
	// CHECK9: .omp.final.done:			// CHECK9: .omp.final.done:
	// CHECK9-NEXT: ret void			// CHECK9-NEXT: ret void
	// CHECK9: terminate.lpad:			// CHECK9: terminate.lpad:
	// CHECK9-NEXT: [[TMP13:%.]] = landingpad { i8, i32 }			// CHECK9-NEXT: [[TMP13:%.]] = landingpad { i8, i32 }
	// CHECK9-NEXT: catch i8* null			// CHECK9-NEXT: catch i8* null
	// CHECK9-NEXT: [[TMP14:%.]] = extractvalue { i8, i32 } [[TMP13]], 0			// CHECK9-NEXT: [[TMP14:%.]] = extractvalue { i8, i32 } [[TMP13]], 0
	// CHECK9-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]]			// CHECK9-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]], !llvm.access.group !31
	// CHECK9-NEXT: unreachable			// CHECK9-NEXT: unreachable
	//			//
	//			//
	// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l57			// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l57
	// CHECK9-SAME: () #[[ATTR3]] {			// CHECK9-SAME: () #[[ATTR3]] {
	// CHECK9-NEXT: entry:			// CHECK9-NEXT: entry:
	// CHECK9-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32, i32, ...)* bitcast (void (i32, i32)* @.omp_outlined..6 to void (i32, i32, ...)*))			// CHECK9-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32, i32, ...)* bitcast (void (i32, i32)* @.omp_outlined..6 to void (i32, i32, ...)*))
	// CHECK9-NEXT: ret void			// CHECK9-NEXT: ret void
	Show All 30 Lines
	// CHECK9-NEXT: br label [[COND_END]]			// CHECK9-NEXT: br label [[COND_END]]
	// CHECK9: cond.end:			// CHECK9: cond.end:
	// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]			// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
	// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK9-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK9-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK9: omp.inner.for.cond:			// CHECK9: omp.inner.for.cond:
	// CHECK9-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !34
	// CHECK9-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK9-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !34
	// CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK9: omp.inner.for.body:			// CHECK9: omp.inner.for.body:
	// CHECK9-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 23)			// CHECK9-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 23), !llvm.access.group !34
	// CHECK9-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK9-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !34
	// CHECK9-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64			// CHECK9-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
	// CHECK9-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK9-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !34
	// CHECK9-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK9-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK9-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..7 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]])			// CHECK9-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..7 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !34
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK9: omp.inner.for.inc:			// CHECK9: omp.inner.for.inc:
	// CHECK9-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !34
	// CHECK9-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK9-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !34
	// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]			// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
	// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !34
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP35:![0-9]+]]
	// CHECK9: omp.inner.for.end:			// CHECK9: omp.inner.for.end:
	// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK9: omp.loop.exit:			// CHECK9: omp.loop.exit:
	// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])			// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
	// CHECK9-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK9-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK9-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0			// CHECK9-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
	// CHECK9-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK9-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK9: .omp.final.then:			// CHECK9: .omp.final.then:
	▲ Show 20 Lines • Show All 44 Lines • ▼ Show 20 Lines
	// CHECK9-NEXT: br label [[COND_END]]			// CHECK9-NEXT: br label [[COND_END]]
	// CHECK9: cond.end:			// CHECK9: cond.end:
	// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]			// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
	// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK9-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK9-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK9: omp.inner.for.cond:			// CHECK9: omp.inner.for.cond:
	// CHECK9-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !37
	// CHECK9-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK9-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !37
	// CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK9: omp.inner.for.body:			// CHECK9: omp.inner.for.body:
	// CHECK9-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !37
	// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !37
	// CHECK9-NEXT: invoke void @_Z3foov()			// CHECK9-NEXT: invoke void @_Z3foov()
	// CHECK9-NEXT: to label [[INVOKE_CONT:%.]] unwind label [[TERMINATE_LPAD:%.]]			// CHECK9-NEXT: to label [[INVOKE_CONT:%.]] unwind label [[TERMINATE_LPAD:%.]], !llvm.access.group !37
	// CHECK9: invoke.cont:			// CHECK9: invoke.cont:
	// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK9: omp.body.continue:			// CHECK9: omp.body.continue:
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK9: omp.inner.for.inc:			// CHECK9: omp.inner.for.inc:
	// CHECK9-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !37
	// CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK9-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4			// CHECK9-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !37
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP38:![0-9]+]]
	// CHECK9: omp.inner.for.end:			// CHECK9: omp.inner.for.end:
	// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK9: omp.loop.exit:			// CHECK9: omp.loop.exit:
	// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])			// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
	// CHECK9-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK9-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK9-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK9-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK9-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK9-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK9: .omp.final.then:			// CHECK9: .omp.final.then:
	// CHECK9-NEXT: store i32 100, i32* [[I]], align 4			// CHECK9-NEXT: store i32 100, i32* [[I]], align 4
	// CHECK9-NEXT: br label [[DOTOMP_FINAL_DONE]]			// CHECK9-NEXT: br label [[DOTOMP_FINAL_DONE]]
	// CHECK9: .omp.final.done:			// CHECK9: .omp.final.done:
	// CHECK9-NEXT: ret void			// CHECK9-NEXT: ret void
	// CHECK9: terminate.lpad:			// CHECK9: terminate.lpad:
	// CHECK9-NEXT: [[TMP13:%.]] = landingpad { i8, i32 }			// CHECK9-NEXT: [[TMP13:%.]] = landingpad { i8, i32 }
	// CHECK9-NEXT: catch i8* null			// CHECK9-NEXT: catch i8* null
	// CHECK9-NEXT: [[TMP14:%.]] = extractvalue { i8, i32 } [[TMP13]], 0			// CHECK9-NEXT: [[TMP14:%.]] = extractvalue { i8, i32 } [[TMP13]], 0
	// CHECK9-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]]			// CHECK9-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]], !llvm.access.group !37
	// CHECK9-NEXT: unreachable			// CHECK9-NEXT: unreachable
	//			//
	//			//
	// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l52			// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l52
	// CHECK9-SAME: () #[[ATTR3]] {			// CHECK9-SAME: () #[[ATTR3]] {
	// CHECK9-NEXT: entry:			// CHECK9-NEXT: entry:
	// CHECK9-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32, i32, ...)* bitcast (void (i32, i32)* @.omp_outlined..8 to void (i32, i32, ...)*))			// CHECK9-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32, i32, ...)* bitcast (void (i32, i32)* @.omp_outlined..8 to void (i32, i32, ...)*))
	// CHECK9-NEXT: ret void			// CHECK9-NEXT: ret void
	Show All 30 Lines
	// CHECK9-NEXT: br label [[COND_END]]			// CHECK9-NEXT: br label [[COND_END]]
	// CHECK9: cond.end:			// CHECK9: cond.end:
	// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]			// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
	// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK9-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK9-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK9: omp.inner.for.cond:			// CHECK9: omp.inner.for.cond:
	// CHECK9-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !40
	// CHECK9-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK9-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !40
	// CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK9: omp.inner.for.body:			// CHECK9: omp.inner.for.body:
	// CHECK9-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 1)			// CHECK9-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 1), !llvm.access.group !40
	// CHECK9-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK9-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !40
	// CHECK9-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64			// CHECK9-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
	// CHECK9-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK9-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !40
	// CHECK9-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK9-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK9-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..9 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]])			// CHECK9-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..9 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !40
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK9: omp.inner.for.inc:			// CHECK9: omp.inner.for.inc:
	// CHECK9-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !40
	// CHECK9-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK9-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !40
	// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]			// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
	// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !40
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP41:![0-9]+]]
	// CHECK9: omp.inner.for.end:			// CHECK9: omp.inner.for.end:
	// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK9: omp.loop.exit:			// CHECK9: omp.loop.exit:
	// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])			// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
	// CHECK9-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK9-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK9-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0			// CHECK9-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
	// CHECK9-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK9-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK9: .omp.final.then:			// CHECK9: .omp.final.then:
	▲ Show 20 Lines • Show All 44 Lines • ▼ Show 20 Lines
	// CHECK9-NEXT: br label [[COND_END]]			// CHECK9-NEXT: br label [[COND_END]]
	// CHECK9: cond.end:			// CHECK9: cond.end:
	// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]			// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
	// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK9-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK9-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK9: omp.inner.for.cond:			// CHECK9: omp.inner.for.cond:
	// CHECK9-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !43
	// CHECK9-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK9-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !43
	// CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK9: omp.inner.for.body:			// CHECK9: omp.inner.for.body:
	// CHECK9-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !43
	// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !43
	// CHECK9-NEXT: invoke void @_Z3foov()			// CHECK9-NEXT: invoke void @_Z3foov()
	// CHECK9-NEXT: to label [[INVOKE_CONT:%.]] unwind label [[TERMINATE_LPAD:%.]]			// CHECK9-NEXT: to label [[INVOKE_CONT:%.]] unwind label [[TERMINATE_LPAD:%.]], !llvm.access.group !43
	// CHECK9: invoke.cont:			// CHECK9: invoke.cont:
	// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK9: omp.body.continue:			// CHECK9: omp.body.continue:
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK9: omp.inner.for.inc:			// CHECK9: omp.inner.for.inc:
	// CHECK9-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !43
	// CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK9-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4			// CHECK9-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !43
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP24:![0-9]+]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP44:![0-9]+]]
	// CHECK9: omp.inner.for.end:			// CHECK9: omp.inner.for.end:
	// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK9: omp.loop.exit:			// CHECK9: omp.loop.exit:
	// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])			// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
	// CHECK9-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK9-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK9-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK9-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK9-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK9-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK9: .omp.final.then:			// CHECK9: .omp.final.then:
	// CHECK9-NEXT: store i32 100, i32* [[I]], align 4			// CHECK9-NEXT: store i32 100, i32* [[I]], align 4
	// CHECK9-NEXT: br label [[DOTOMP_FINAL_DONE]]			// CHECK9-NEXT: br label [[DOTOMP_FINAL_DONE]]
	// CHECK9: .omp.final.done:			// CHECK9: .omp.final.done:
	// CHECK9-NEXT: ret void			// CHECK9-NEXT: ret void
	// CHECK9: terminate.lpad:			// CHECK9: terminate.lpad:
	// CHECK9-NEXT: [[TMP13:%.]] = landingpad { i8, i32 }			// CHECK9-NEXT: [[TMP13:%.]] = landingpad { i8, i32 }
	// CHECK9-NEXT: catch i8* null			// CHECK9-NEXT: catch i8* null
	// CHECK9-NEXT: [[TMP14:%.]] = extractvalue { i8, i32 } [[TMP13]], 0			// CHECK9-NEXT: [[TMP14:%.]] = extractvalue { i8, i32 } [[TMP13]], 0
	// CHECK9-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]]			// CHECK9-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]], !llvm.access.group !43
	// CHECK9-NEXT: unreachable			// CHECK9-NEXT: unreachable
	//			//
	//			//
	// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l57			// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l57
	// CHECK9-SAME: () #[[ATTR3]] {			// CHECK9-SAME: () #[[ATTR3]] {
	// CHECK9-NEXT: entry:			// CHECK9-NEXT: entry:
	// CHECK9-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32, i32, ...)* bitcast (void (i32, i32)* @.omp_outlined..10 to void (i32, i32, ...)*))			// CHECK9-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32, i32, ...)* bitcast (void (i32, i32)* @.omp_outlined..10 to void (i32, i32, ...)*))
	// CHECK9-NEXT: ret void			// CHECK9-NEXT: ret void
	Show All 33 Lines
	// CHECK9-NEXT: br label [[COND_END]]			// CHECK9-NEXT: br label [[COND_END]]
	// CHECK9: cond.end:			// CHECK9: cond.end:
	// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]			// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
	// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK9-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK9-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK9: omp.inner.for.cond:			// CHECK9: omp.inner.for.cond:
	// CHECK9-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !46
	// CHECK9-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK9-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !46
	// CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK9: omp.inner.for.body:			// CHECK9: omp.inner.for.body:
	// CHECK9-NEXT: invoke void @_ZN1SC1El(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]], i64 23)			// CHECK9-NEXT: invoke void @_ZN1SC1El(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]], i64 23)
	// CHECK9-NEXT: to label [[INVOKE_CONT:%.]] unwind label [[TERMINATE_LPAD:%.]]			// CHECK9-NEXT: to label [[INVOKE_CONT:%.]] unwind label [[TERMINATE_LPAD:%.]], !llvm.access.group !46
	// CHECK9: invoke.cont:			// CHECK9: invoke.cont:
	// CHECK9-NEXT: [[CALL:%.]] = invoke i8 @_ZN1ScvcEv(%struct.S nonnull align 8 dereferenceable(24) [[REF_TMP]])			// CHECK9-NEXT: [[CALL:%.]] = invoke i8 @_ZN1ScvcEv(%struct.S nonnull align 8 dereferenceable(24) [[REF_TMP]])
	// CHECK9-NEXT: to label [[INVOKE_CONT2:%.]] unwind label [[LPAD:%.]]			// CHECK9-NEXT: to label [[INVOKE_CONT2:%.]] unwind label [[LPAD:%.]], !llvm.access.group !46
	// CHECK9: invoke.cont2:			// CHECK9: invoke.cont2:
	// CHECK9-NEXT: [[TMP7:%.*]] = sext i8 [[CALL]] to i32			// CHECK9-NEXT: [[TMP7:%.*]] = sext i8 [[CALL]] to i32
	// CHECK9-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 [[TMP7]])			// CHECK9-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 [[TMP7]]), !llvm.access.group !46
	// CHECK9-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR6]]			// CHECK9-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR6]], !llvm.access.group !46
	// CHECK9-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK9-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !46
	// CHECK9-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64			// CHECK9-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
	// CHECK9-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK9-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !46
	// CHECK9-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64			// CHECK9-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
	// CHECK9-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..11 to void (i32, i32, ...)*), i64 [[TMP9]], i64 [[TMP11]])			// CHECK9-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..11 to void (i32, i32, ...)*), i64 [[TMP9]], i64 [[TMP11]]), !llvm.access.group !46
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK9: omp.inner.for.inc:			// CHECK9: omp.inner.for.inc:
	// CHECK9-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !46
	// CHECK9-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK9-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !46
	// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]			// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]
	// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !46
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP47:![0-9]+]]
	// CHECK9: lpad:			// CHECK9: lpad:
	// CHECK9-NEXT: [[TMP14:%.]] = landingpad { i8, i32 }			// CHECK9-NEXT: [[TMP14:%.]] = landingpad { i8, i32 }
	// CHECK9-NEXT: catch i8* null			// CHECK9-NEXT: catch i8* null
	// CHECK9-NEXT: [[TMP15:%.]] = extractvalue { i8, i32 } [[TMP14]], 0			// CHECK9-NEXT: [[TMP15:%.]] = extractvalue { i8, i32 } [[TMP14]], 0
	// CHECK9-NEXT: store i8* [[TMP15]], i8** [[EXN_SLOT]], align 8			// CHECK9-NEXT: store i8* [[TMP15]], i8** [[EXN_SLOT]], align 8, !llvm.access.group !46
	// CHECK9-NEXT: [[TMP16:%.]] = extractvalue { i8, i32 } [[TMP14]], 1			// CHECK9-NEXT: [[TMP16:%.]] = extractvalue { i8, i32 } [[TMP14]], 1
	// CHECK9-NEXT: store i32 [[TMP16]], i32* [[EHSELECTOR_SLOT]], align 4			// CHECK9-NEXT: store i32 [[TMP16]], i32* [[EHSELECTOR_SLOT]], align 4, !llvm.access.group !46
	// CHECK9-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR6]]			// CHECK9-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR6]], !llvm.access.group !46
	// CHECK9-NEXT: br label [[TERMINATE_HANDLER:%.*]]			// CHECK9-NEXT: br label [[TERMINATE_HANDLER:%.*]]
	// CHECK9: omp.inner.for.end:			// CHECK9: omp.inner.for.end:
	// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK9: omp.loop.exit:			// CHECK9: omp.loop.exit:
	// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])			// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
	// CHECK9-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK9-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK9-NEXT: [[TMP18:%.*]] = icmp ne i32 [[TMP17]], 0			// CHECK9-NEXT: [[TMP18:%.*]] = icmp ne i32 [[TMP17]], 0
	// CHECK9-NEXT: br i1 [[TMP18]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK9-NEXT: br i1 [[TMP18]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK9: .omp.final.then:			// CHECK9: .omp.final.then:
	// CHECK9-NEXT: store i32 100, i32* [[I]], align 4			// CHECK9-NEXT: store i32 100, i32* [[I]], align 4
	// CHECK9-NEXT: br label [[DOTOMP_FINAL_DONE]]			// CHECK9-NEXT: br label [[DOTOMP_FINAL_DONE]]
	// CHECK9: .omp.final.done:			// CHECK9: .omp.final.done:
	// CHECK9-NEXT: ret void			// CHECK9-NEXT: ret void
	// CHECK9: terminate.lpad:			// CHECK9: terminate.lpad:
	// CHECK9-NEXT: [[TMP19:%.]] = landingpad { i8, i32 }			// CHECK9-NEXT: [[TMP19:%.]] = landingpad { i8, i32 }
	// CHECK9-NEXT: catch i8* null			// CHECK9-NEXT: catch i8* null
	// CHECK9-NEXT: [[TMP20:%.]] = extractvalue { i8, i32 } [[TMP19]], 0			// CHECK9-NEXT: [[TMP20:%.]] = extractvalue { i8, i32 } [[TMP19]], 0
	// CHECK9-NEXT: call void @__clang_call_terminate(i8* [[TMP20]]) #[[ATTR10]]			// CHECK9-NEXT: call void @__clang_call_terminate(i8* [[TMP20]]) #[[ATTR10]], !llvm.access.group !46
	// CHECK9-NEXT: unreachable			// CHECK9-NEXT: unreachable
	// CHECK9: terminate.handler:			// CHECK9: terminate.handler:
	// CHECK9-NEXT: [[EXN:%.]] = load i8, i8** [[EXN_SLOT]], align 8			// CHECK9-NEXT: [[EXN:%.]] = load i8, i8** [[EXN_SLOT]], align 8, !llvm.access.group !46
	// CHECK9-NEXT: call void @__clang_call_terminate(i8* [[EXN]]) #[[ATTR10]]			// CHECK9-NEXT: call void @__clang_call_terminate(i8* [[EXN]]) #[[ATTR10]], !llvm.access.group !46
	// CHECK9-NEXT: unreachable			// CHECK9-NEXT: unreachable
	//			//
	//			//
	// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..11			// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..11
	// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i64 [[DOTPREVIOUS_LB_:%.]], i64 [[DOTPREVIOUS_UB_:%.]]) #[[ATTR3]] personality i8 bitcast (i32 (...)* @__gxx_personality_v0 to i8*) {			// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i64 [[DOTPREVIOUS_LB_:%.]], i64 [[DOTPREVIOUS_UB_:%.]]) #[[ATTR3]] personality i8 bitcast (i32 (...)* @__gxx_personality_v0 to i8*) {
	// CHECK9-NEXT: entry:			// CHECK9-NEXT: entry:
	// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8			// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8
	// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8			// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8
	Show All 33 Lines
	// CHECK9-NEXT: br label [[COND_END]]			// CHECK9-NEXT: br label [[COND_END]]
	// CHECK9: cond.end:			// CHECK9: cond.end:
	// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]			// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
	// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK9-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK9-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK9: omp.inner.for.cond:			// CHECK9: omp.inner.for.cond:
	// CHECK9-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !49
	// CHECK9-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK9-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !49
	// CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK9: omp.inner.for.body:			// CHECK9: omp.inner.for.body:
	// CHECK9-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !49
	// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !49
	// CHECK9-NEXT: invoke void @_Z3foov()			// CHECK9-NEXT: invoke void @_Z3foov()
	// CHECK9-NEXT: to label [[INVOKE_CONT:%.]] unwind label [[TERMINATE_LPAD:%.]]			// CHECK9-NEXT: to label [[INVOKE_CONT:%.]] unwind label [[TERMINATE_LPAD:%.]], !llvm.access.group !49
	// CHECK9: invoke.cont:			// CHECK9: invoke.cont:
	// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK9: omp.body.continue:			// CHECK9: omp.body.continue:
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK9: omp.inner.for.inc:			// CHECK9: omp.inner.for.inc:
	// CHECK9-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !49
	// CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK9-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4			// CHECK9-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !49
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP26:![0-9]+]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP50:![0-9]+]]
	// CHECK9: omp.inner.for.end:			// CHECK9: omp.inner.for.end:
	// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK9: omp.loop.exit:			// CHECK9: omp.loop.exit:
	// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])			// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
	// CHECK9-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK9-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK9-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK9-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK9-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK9-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK9: .omp.final.then:			// CHECK9: .omp.final.then:
	// CHECK9-NEXT: store i32 100, i32* [[I]], align 4			// CHECK9-NEXT: store i32 100, i32* [[I]], align 4
	// CHECK9-NEXT: br label [[DOTOMP_FINAL_DONE]]			// CHECK9-NEXT: br label [[DOTOMP_FINAL_DONE]]
	// CHECK9: .omp.final.done:			// CHECK9: .omp.final.done:
	// CHECK9-NEXT: ret void			// CHECK9-NEXT: ret void
	// CHECK9: terminate.lpad:			// CHECK9: terminate.lpad:
	// CHECK9-NEXT: [[TMP13:%.]] = landingpad { i8, i32 }			// CHECK9-NEXT: [[TMP13:%.]] = landingpad { i8, i32 }
	// CHECK9-NEXT: catch i8* null			// CHECK9-NEXT: catch i8* null
	// CHECK9-NEXT: [[TMP14:%.]] = extractvalue { i8, i32 } [[TMP13]], 0			// CHECK9-NEXT: [[TMP14:%.]] = extractvalue { i8, i32 } [[TMP13]], 0
	// CHECK9-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]]			// CHECK9-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]], !llvm.access.group !49
	// CHECK9-NEXT: unreachable			// CHECK9-NEXT: unreachable
	//			//
	//			//
	// CHECK9-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg			// CHECK9-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
	// CHECK9-SAME: () #[[ATTR9:[0-9]+]] {			// CHECK9-SAME: () #[[ATTR9:[0-9]+]] {
	// CHECK9-NEXT: entry:			// CHECK9-NEXT: entry:
	// CHECK9-NEXT: call void @__tgt_register_requires(i64 1)			// CHECK9-NEXT: call void @__tgt_register_requires(i64 1)
	// CHECK9-NEXT: ret void			// CHECK9-NEXT: ret void
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	// CHECK10-NEXT: br label [[COND_END]]			// CHECK10-NEXT: br label [[COND_END]]
	// CHECK10: cond.end:			// CHECK10: cond.end:
	// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]			// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
	// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK10-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK10-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK10: omp.inner.for.cond:			// CHECK10: omp.inner.for.cond:
	// CHECK10-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK10-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK10-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !13
	// CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK10: omp.inner.for.body:			// CHECK10: omp.inner.for.body:
	// CHECK10-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 2)			// CHECK10-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 2), !llvm.access.group !13
	// CHECK10-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK10-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !13
	// CHECK10-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64			// CHECK10-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
	// CHECK10-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK10-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !13
	// CHECK10-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK10-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK10-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..1 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]])			// CHECK10-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..1 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !13
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK10: omp.inner.for.inc:			// CHECK10: omp.inner.for.inc:
	// CHECK10-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK10-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK10-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !13
	// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]			// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
	// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]]
	// CHECK10: omp.inner.for.end:			// CHECK10: omp.inner.for.end:
	// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK10: omp.loop.exit:			// CHECK10: omp.loop.exit:
	// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])			// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
	// CHECK10-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK10-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK10-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0			// CHECK10-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
	// CHECK10-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK10-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK10: .omp.final.then:			// CHECK10: .omp.final.then:
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	// CHECK10-NEXT: br label [[COND_END]]			// CHECK10-NEXT: br label [[COND_END]]
	// CHECK10: cond.end:			// CHECK10: cond.end:
	// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]			// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
	// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK10-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK10-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK10: omp.inner.for.cond:			// CHECK10: omp.inner.for.cond:
	// CHECK10-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !17
	// CHECK10-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK10-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !17
	// CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK10: omp.inner.for.body:			// CHECK10: omp.inner.for.body:
	// CHECK10-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !17
	// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !17
	// CHECK10-NEXT: invoke void @_Z3foov()			// CHECK10-NEXT: invoke void @_Z3foov()
	// CHECK10-NEXT: to label [[INVOKE_CONT:%.]] unwind label [[TERMINATE_LPAD:%.]]			// CHECK10-NEXT: to label [[INVOKE_CONT:%.]] unwind label [[TERMINATE_LPAD:%.]], !llvm.access.group !17
	// CHECK10: invoke.cont:			// CHECK10: invoke.cont:
	// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK10: omp.body.continue:			// CHECK10: omp.body.continue:
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK10: omp.inner.for.inc:			// CHECK10: omp.inner.for.inc:
	// CHECK10-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !17
	// CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK10-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4			// CHECK10-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]]
	// CHECK10: omp.inner.for.end:			// CHECK10: omp.inner.for.end:
	// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK10: omp.loop.exit:			// CHECK10: omp.loop.exit:
	// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])			// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
	// CHECK10-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK10-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK10-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK10-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK10-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK10-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK10: .omp.final.then:			// CHECK10: .omp.final.then:
	// CHECK10-NEXT: store i32 100, i32* [[I]], align 4			// CHECK10-NEXT: store i32 100, i32* [[I]], align 4
	// CHECK10-NEXT: br label [[DOTOMP_FINAL_DONE]]			// CHECK10-NEXT: br label [[DOTOMP_FINAL_DONE]]
	// CHECK10: .omp.final.done:			// CHECK10: .omp.final.done:
	// CHECK10-NEXT: ret void			// CHECK10-NEXT: ret void
	// CHECK10: terminate.lpad:			// CHECK10: terminate.lpad:
	// CHECK10-NEXT: [[TMP13:%.]] = landingpad { i8, i32 }			// CHECK10-NEXT: [[TMP13:%.]] = landingpad { i8, i32 }
	// CHECK10-NEXT: catch i8* null			// CHECK10-NEXT: catch i8* null
	// CHECK10-NEXT: [[TMP14:%.]] = extractvalue { i8, i32 } [[TMP13]], 0			// CHECK10-NEXT: [[TMP14:%.]] = extractvalue { i8, i32 } [[TMP13]], 0
	// CHECK10-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10:[0-9]+]]			// CHECK10-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10:[0-9]+]], !llvm.access.group !17
	// CHECK10-NEXT: unreachable			// CHECK10-NEXT: unreachable
	//			//
	//			//
	// CHECK10-LABEL: define {{[^@]+}}@__clang_call_terminate			// CHECK10-LABEL: define {{[^@]+}}@__clang_call_terminate
	// CHECK10-SAME: (i8* [[TMP0:%.*]]) #[[ATTR5:[0-9]+]] comdat {			// CHECK10-SAME: (i8* [[TMP0:%.*]]) #[[ATTR5:[0-9]+]] comdat {
	// CHECK10-NEXT: [[TMP2:%.]] = call i8 @__cxa_begin_catch(i8* [[TMP0]]) #[[ATTR6]]			// CHECK10-NEXT: [[TMP2:%.]] = call i8 @__cxa_begin_catch(i8* [[TMP0]]) #[[ATTR6]]
	// CHECK10-NEXT: call void @_ZSt9terminatev() #[[ATTR10]]			// CHECK10-NEXT: call void @_ZSt9terminatev() #[[ATTR10]]
	// CHECK10-NEXT: unreachable			// CHECK10-NEXT: unreachable
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	// CHECK10-NEXT: br label [[COND_END]]			// CHECK10-NEXT: br label [[COND_END]]
	// CHECK10: cond.end:			// CHECK10: cond.end:
	// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]			// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
	// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK10-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK10-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK10-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK10-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK10: omp.inner.for.cond:			// CHECK10: omp.inner.for.cond:
	// CHECK10-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !22
	// CHECK10-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK10-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !22
	// CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK10: omp.inner.for.body:			// CHECK10: omp.inner.for.body:
	// CHECK10-NEXT: [[TMP8:%.]] = load i8, i8 [[TMP0]], align 1			// CHECK10-NEXT: [[TMP8:%.]] = load i8, i8 [[TMP0]], align 1, !llvm.access.group !22
	// CHECK10-NEXT: [[TMP9:%.*]] = sext i8 [[TMP8]] to i32			// CHECK10-NEXT: [[TMP9:%.*]] = sext i8 [[TMP8]] to i32
	// CHECK10-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP2]], i32 [[TMP9]])			// CHECK10-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP2]], i32 [[TMP9]]), !llvm.access.group !22
	// CHECK10-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK10-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !22
	// CHECK10-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64			// CHECK10-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
	// CHECK10-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK10-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !22
	// CHECK10-NEXT: [[TMP13:%.*]] = zext i32 [[TMP12]] to i64			// CHECK10-NEXT: [[TMP13:%.*]] = zext i32 [[TMP12]] to i64
	// CHECK10-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..3 to void (i32, i32, ...)*), i64 [[TMP11]], i64 [[TMP13]])			// CHECK10-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..3 to void (i32, i32, ...)*), i64 [[TMP11]], i64 [[TMP13]]), !llvm.access.group !22
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK10: omp.inner.for.inc:			// CHECK10: omp.inner.for.inc:
	// CHECK10-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !22
	// CHECK10-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK10-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !22
	// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP14]], [[TMP15]]			// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP14]], [[TMP15]]
	// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]]
	// CHECK10: omp.inner.for.end:			// CHECK10: omp.inner.for.end:
	// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK10: omp.loop.exit:			// CHECK10: omp.loop.exit:
	// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])			// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
	// CHECK10-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK10-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK10-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0			// CHECK10-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0
	// CHECK10-NEXT: br i1 [[TMP17]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK10-NEXT: br i1 [[TMP17]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK10: .omp.final.then:			// CHECK10: .omp.final.then:
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	// CHECK10-NEXT: br label [[COND_END]]			// CHECK10-NEXT: br label [[COND_END]]
	// CHECK10: cond.end:			// CHECK10: cond.end:
	// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]			// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
	// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK10-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK10-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK10: omp.inner.for.cond:			// CHECK10: omp.inner.for.cond:
	// CHECK10-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !25
	// CHECK10-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK10-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !25
	// CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK10: omp.inner.for.body:			// CHECK10: omp.inner.for.body:
	// CHECK10-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !25
	// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !25
	// CHECK10-NEXT: invoke void @_Z3foov()			// CHECK10-NEXT: invoke void @_Z3foov()
	// CHECK10-NEXT: to label [[INVOKE_CONT:%.]] unwind label [[TERMINATE_LPAD:%.]]			// CHECK10-NEXT: to label [[INVOKE_CONT:%.]] unwind label [[TERMINATE_LPAD:%.]], !llvm.access.group !25
	// CHECK10: invoke.cont:			// CHECK10: invoke.cont:
	// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK10: omp.body.continue:			// CHECK10: omp.body.continue:
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK10: omp.inner.for.inc:			// CHECK10: omp.inner.for.inc:
	// CHECK10-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !25
	// CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK10-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4			// CHECK10-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP26:![0-9]+]]
	// CHECK10: omp.inner.for.end:			// CHECK10: omp.inner.for.end:
	// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK10: omp.loop.exit:			// CHECK10: omp.loop.exit:
	// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])			// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
	// CHECK10-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK10-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK10-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK10-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK10-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK10-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK10: .omp.final.then:			// CHECK10: .omp.final.then:
	// CHECK10-NEXT: store i32 100, i32* [[I]], align 4			// CHECK10-NEXT: store i32 100, i32* [[I]], align 4
	// CHECK10-NEXT: br label [[DOTOMP_FINAL_DONE]]			// CHECK10-NEXT: br label [[DOTOMP_FINAL_DONE]]
	// CHECK10: .omp.final.done:			// CHECK10: .omp.final.done:
	// CHECK10-NEXT: ret void			// CHECK10-NEXT: ret void
	// CHECK10: terminate.lpad:			// CHECK10: terminate.lpad:
	// CHECK10-NEXT: [[TMP13:%.]] = landingpad { i8, i32 }			// CHECK10-NEXT: [[TMP13:%.]] = landingpad { i8, i32 }
	// CHECK10-NEXT: catch i8* null			// CHECK10-NEXT: catch i8* null
	// CHECK10-NEXT: [[TMP14:%.]] = extractvalue { i8, i32 } [[TMP13]], 0			// CHECK10-NEXT: [[TMP14:%.]] = extractvalue { i8, i32 } [[TMP13]], 0
	// CHECK10-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]]			// CHECK10-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]], !llvm.access.group !25
	// CHECK10-NEXT: unreachable			// CHECK10-NEXT: unreachable
	//			//
	//			//
	// CHECK10-LABEL: define {{[^@]+}}@_Z5tmainIcLi5EEiv			// CHECK10-LABEL: define {{[^@]+}}@_Z5tmainIcLi5EEiv
	// CHECK10-SAME: () #[[ATTR7:[0-9]+]] comdat {			// CHECK10-SAME: () #[[ATTR7:[0-9]+]] comdat {
	// CHECK10-NEXT: entry:			// CHECK10-NEXT: entry:
	// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4			// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4
	// CHECK10-NEXT: [[_TMP1:%.*]] = alloca i32, align 4			// CHECK10-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
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	// CHECK10-NEXT: br label [[COND_END]]			// CHECK10-NEXT: br label [[COND_END]]
	// CHECK10: cond.end:			// CHECK10: cond.end:
	// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]			// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
	// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK10-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK10-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK10: omp.inner.for.cond:			// CHECK10: omp.inner.for.cond:
	// CHECK10-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !28
	// CHECK10-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK10-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !28
	// CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK10: omp.inner.for.body:			// CHECK10: omp.inner.for.body:
	// CHECK10-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 5)			// CHECK10-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 5), !llvm.access.group !28
	// CHECK10-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK10-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !28
	// CHECK10-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64			// CHECK10-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
	// CHECK10-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK10-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !28
	// CHECK10-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK10-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK10-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..5 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]])			// CHECK10-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..5 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !28
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK10: omp.inner.for.inc:			// CHECK10: omp.inner.for.inc:
	// CHECK10-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !28
	// CHECK10-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK10-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !28
	// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]			// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
	// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP29:![0-9]+]]
	// CHECK10: omp.inner.for.end:			// CHECK10: omp.inner.for.end:
	// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK10: omp.loop.exit:			// CHECK10: omp.loop.exit:
	// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])			// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
	// CHECK10-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK10-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK10-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0			// CHECK10-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
	// CHECK10-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK10-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK10: .omp.final.then:			// CHECK10: .omp.final.then:
	▲ Show 20 Lines • Show All 44 Lines • ▼ Show 20 Lines
	// CHECK10-NEXT: br label [[COND_END]]			// CHECK10-NEXT: br label [[COND_END]]
	// CHECK10: cond.end:			// CHECK10: cond.end:
	// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]			// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
	// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK10-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK10-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK10: omp.inner.for.cond:			// CHECK10: omp.inner.for.cond:
	// CHECK10-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !31
	// CHECK10-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK10-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !31
	// CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK10: omp.inner.for.body:			// CHECK10: omp.inner.for.body:
	// CHECK10-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !31
	// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !31
	// CHECK10-NEXT: invoke void @_Z3foov()			// CHECK10-NEXT: invoke void @_Z3foov()
	// CHECK10-NEXT: to label [[INVOKE_CONT:%.]] unwind label [[TERMINATE_LPAD:%.]]			// CHECK10-NEXT: to label [[INVOKE_CONT:%.]] unwind label [[TERMINATE_LPAD:%.]], !llvm.access.group !31
	// CHECK10: invoke.cont:			// CHECK10: invoke.cont:
	// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK10: omp.body.continue:			// CHECK10: omp.body.continue:
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK10: omp.inner.for.inc:			// CHECK10: omp.inner.for.inc:
	// CHECK10-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !31
	// CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK10-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4			// CHECK10-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !31
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP32:![0-9]+]]
	// CHECK10: omp.inner.for.end:			// CHECK10: omp.inner.for.end:
	// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK10: omp.loop.exit:			// CHECK10: omp.loop.exit:
	// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])			// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
	// CHECK10-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK10-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK10-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK10-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK10-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK10-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK10: .omp.final.then:			// CHECK10: .omp.final.then:
	// CHECK10-NEXT: store i32 100, i32* [[I]], align 4			// CHECK10-NEXT: store i32 100, i32* [[I]], align 4
	// CHECK10-NEXT: br label [[DOTOMP_FINAL_DONE]]			// CHECK10-NEXT: br label [[DOTOMP_FINAL_DONE]]
	// CHECK10: .omp.final.done:			// CHECK10: .omp.final.done:
	// CHECK10-NEXT: ret void			// CHECK10-NEXT: ret void
	// CHECK10: terminate.lpad:			// CHECK10: terminate.lpad:
	// CHECK10-NEXT: [[TMP13:%.]] = landingpad { i8, i32 }			// CHECK10-NEXT: [[TMP13:%.]] = landingpad { i8, i32 }
	// CHECK10-NEXT: catch i8* null			// CHECK10-NEXT: catch i8* null
	// CHECK10-NEXT: [[TMP14:%.]] = extractvalue { i8, i32 } [[TMP13]], 0			// CHECK10-NEXT: [[TMP14:%.]] = extractvalue { i8, i32 } [[TMP13]], 0
	// CHECK10-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]]			// CHECK10-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]], !llvm.access.group !31
	// CHECK10-NEXT: unreachable			// CHECK10-NEXT: unreachable
	//			//
	//			//
	// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l57			// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l57
	// CHECK10-SAME: () #[[ATTR3]] {			// CHECK10-SAME: () #[[ATTR3]] {
	// CHECK10-NEXT: entry:			// CHECK10-NEXT: entry:
	// CHECK10-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32, i32, ...)* bitcast (void (i32, i32)* @.omp_outlined..6 to void (i32, i32, ...)*))			// CHECK10-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32, i32, ...)* bitcast (void (i32, i32)* @.omp_outlined..6 to void (i32, i32, ...)*))
	// CHECK10-NEXT: ret void			// CHECK10-NEXT: ret void
	Show All 30 Lines
	// CHECK10-NEXT: br label [[COND_END]]			// CHECK10-NEXT: br label [[COND_END]]
	// CHECK10: cond.end:			// CHECK10: cond.end:
	// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]			// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
	// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK10-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK10-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK10: omp.inner.for.cond:			// CHECK10: omp.inner.for.cond:
	// CHECK10-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !34
	// CHECK10-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK10-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !34
	// CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK10: omp.inner.for.body:			// CHECK10: omp.inner.for.body:
	// CHECK10-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 23)			// CHECK10-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 23), !llvm.access.group !34
	// CHECK10-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK10-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !34
	// CHECK10-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64			// CHECK10-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
	// CHECK10-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK10-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !34
	// CHECK10-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK10-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK10-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..7 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]])			// CHECK10-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..7 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !34
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK10: omp.inner.for.inc:			// CHECK10: omp.inner.for.inc:
	// CHECK10-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !34
	// CHECK10-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK10-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !34
	// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]			// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
	// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !34
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP35:![0-9]+]]
	// CHECK10: omp.inner.for.end:			// CHECK10: omp.inner.for.end:
	// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK10: omp.loop.exit:			// CHECK10: omp.loop.exit:
	// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])			// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
	// CHECK10-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK10-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK10-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0			// CHECK10-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
	// CHECK10-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK10-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK10: .omp.final.then:			// CHECK10: .omp.final.then:
	▲ Show 20 Lines • Show All 44 Lines • ▼ Show 20 Lines
	// CHECK10-NEXT: br label [[COND_END]]			// CHECK10-NEXT: br label [[COND_END]]
	// CHECK10: cond.end:			// CHECK10: cond.end:
	// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]			// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
	// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK10-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK10-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK10: omp.inner.for.cond:			// CHECK10: omp.inner.for.cond:
	// CHECK10-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !37
	// CHECK10-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK10-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !37
	// CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK10: omp.inner.for.body:			// CHECK10: omp.inner.for.body:
	// CHECK10-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !37
	// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !37
	// CHECK10-NEXT: invoke void @_Z3foov()			// CHECK10-NEXT: invoke void @_Z3foov()
	// CHECK10-NEXT: to label [[INVOKE_CONT:%.]] unwind label [[TERMINATE_LPAD:%.]]			// CHECK10-NEXT: to label [[INVOKE_CONT:%.]] unwind label [[TERMINATE_LPAD:%.]], !llvm.access.group !37
	// CHECK10: invoke.cont:			// CHECK10: invoke.cont:
	// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK10: omp.body.continue:			// CHECK10: omp.body.continue:
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK10: omp.inner.for.inc:			// CHECK10: omp.inner.for.inc:
	// CHECK10-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !37
	// CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK10-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4			// CHECK10-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !37
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP38:![0-9]+]]
	// CHECK10: omp.inner.for.end:			// CHECK10: omp.inner.for.end:
	// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK10: omp.loop.exit:			// CHECK10: omp.loop.exit:
	// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])			// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
	// CHECK10-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK10-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK10-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK10-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK10-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK10-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK10: .omp.final.then:			// CHECK10: .omp.final.then:
	// CHECK10-NEXT: store i32 100, i32* [[I]], align 4			// CHECK10-NEXT: store i32 100, i32* [[I]], align 4
	// CHECK10-NEXT: br label [[DOTOMP_FINAL_DONE]]			// CHECK10-NEXT: br label [[DOTOMP_FINAL_DONE]]
	// CHECK10: .omp.final.done:			// CHECK10: .omp.final.done:
	// CHECK10-NEXT: ret void			// CHECK10-NEXT: ret void
	// CHECK10: terminate.lpad:			// CHECK10: terminate.lpad:
	// CHECK10-NEXT: [[TMP13:%.]] = landingpad { i8, i32 }			// CHECK10-NEXT: [[TMP13:%.]] = landingpad { i8, i32 }
	// CHECK10-NEXT: catch i8* null			// CHECK10-NEXT: catch i8* null
	// CHECK10-NEXT: [[TMP14:%.]] = extractvalue { i8, i32 } [[TMP13]], 0			// CHECK10-NEXT: [[TMP14:%.]] = extractvalue { i8, i32 } [[TMP13]], 0
	// CHECK10-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]]			// CHECK10-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]], !llvm.access.group !37
	// CHECK10-NEXT: unreachable			// CHECK10-NEXT: unreachable
	//			//
	//			//
	// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l52			// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l52
	// CHECK10-SAME: () #[[ATTR3]] {			// CHECK10-SAME: () #[[ATTR3]] {
	// CHECK10-NEXT: entry:			// CHECK10-NEXT: entry:
	// CHECK10-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32, i32, ...)* bitcast (void (i32, i32)* @.omp_outlined..8 to void (i32, i32, ...)*))			// CHECK10-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32, i32, ...)* bitcast (void (i32, i32)* @.omp_outlined..8 to void (i32, i32, ...)*))
	// CHECK10-NEXT: ret void			// CHECK10-NEXT: ret void
	Show All 30 Lines
	// CHECK10-NEXT: br label [[COND_END]]			// CHECK10-NEXT: br label [[COND_END]]
	// CHECK10: cond.end:			// CHECK10: cond.end:
	// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]			// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
	// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK10-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK10-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK10: omp.inner.for.cond:			// CHECK10: omp.inner.for.cond:
	// CHECK10-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !40
	// CHECK10-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK10-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !40
	// CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK10: omp.inner.for.body:			// CHECK10: omp.inner.for.body:
	// CHECK10-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 1)			// CHECK10-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 1), !llvm.access.group !40
	// CHECK10-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK10-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !40
	// CHECK10-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64			// CHECK10-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
	// CHECK10-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK10-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !40
	// CHECK10-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK10-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK10-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..9 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]])			// CHECK10-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..9 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !40
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK10: omp.inner.for.inc:			// CHECK10: omp.inner.for.inc:
	// CHECK10-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !40
	// CHECK10-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK10-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !40
	// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]			// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
	// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !40
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP41:![0-9]+]]
	// CHECK10: omp.inner.for.end:			// CHECK10: omp.inner.for.end:
	// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK10: omp.loop.exit:			// CHECK10: omp.loop.exit:
	// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])			// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
	// CHECK10-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK10-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK10-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0			// CHECK10-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
	// CHECK10-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK10-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK10: .omp.final.then:			// CHECK10: .omp.final.then:
	▲ Show 20 Lines • Show All 44 Lines • ▼ Show 20 Lines
	// CHECK10-NEXT: br label [[COND_END]]			// CHECK10-NEXT: br label [[COND_END]]
	// CHECK10: cond.end:			// CHECK10: cond.end:
	// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]			// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
	// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK10-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK10-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK10: omp.inner.for.cond:			// CHECK10: omp.inner.for.cond:
	// CHECK10-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !43
	// CHECK10-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK10-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !43
	// CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK10: omp.inner.for.body:			// CHECK10: omp.inner.for.body:
	// CHECK10-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !43
	// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !43
	// CHECK10-NEXT: invoke void @_Z3foov()			// CHECK10-NEXT: invoke void @_Z3foov()
	// CHECK10-NEXT: to label [[INVOKE_CONT:%.]] unwind label [[TERMINATE_LPAD:%.]]			// CHECK10-NEXT: to label [[INVOKE_CONT:%.]] unwind label [[TERMINATE_LPAD:%.]], !llvm.access.group !43
	// CHECK10: invoke.cont:			// CHECK10: invoke.cont:
	// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK10: omp.body.continue:			// CHECK10: omp.body.continue:
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK10: omp.inner.for.inc:			// CHECK10: omp.inner.for.inc:
	// CHECK10-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !43
	// CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK10-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4			// CHECK10-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !43
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP24:![0-9]+]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP44:![0-9]+]]
	// CHECK10: omp.inner.for.end:			// CHECK10: omp.inner.for.end:
	// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK10: omp.loop.exit:			// CHECK10: omp.loop.exit:
	// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])			// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
	// CHECK10-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK10-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK10-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK10-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK10-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK10-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK10: .omp.final.then:			// CHECK10: .omp.final.then:
	// CHECK10-NEXT: store i32 100, i32* [[I]], align 4			// CHECK10-NEXT: store i32 100, i32* [[I]], align 4
	// CHECK10-NEXT: br label [[DOTOMP_FINAL_DONE]]			// CHECK10-NEXT: br label [[DOTOMP_FINAL_DONE]]
	// CHECK10: .omp.final.done:			// CHECK10: .omp.final.done:
	// CHECK10-NEXT: ret void			// CHECK10-NEXT: ret void
	// CHECK10: terminate.lpad:			// CHECK10: terminate.lpad:
	// CHECK10-NEXT: [[TMP13:%.]] = landingpad { i8, i32 }			// CHECK10-NEXT: [[TMP13:%.]] = landingpad { i8, i32 }
	// CHECK10-NEXT: catch i8* null			// CHECK10-NEXT: catch i8* null
	// CHECK10-NEXT: [[TMP14:%.]] = extractvalue { i8, i32 } [[TMP13]], 0			// CHECK10-NEXT: [[TMP14:%.]] = extractvalue { i8, i32 } [[TMP13]], 0
	// CHECK10-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]]			// CHECK10-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]], !llvm.access.group !43
	// CHECK10-NEXT: unreachable			// CHECK10-NEXT: unreachable
	//			//
	//			//
	// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l57			// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l57
	// CHECK10-SAME: () #[[ATTR3]] {			// CHECK10-SAME: () #[[ATTR3]] {
	// CHECK10-NEXT: entry:			// CHECK10-NEXT: entry:
	// CHECK10-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32, i32, ...)* bitcast (void (i32, i32)* @.omp_outlined..10 to void (i32, i32, ...)*))			// CHECK10-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32, i32, ...)* bitcast (void (i32, i32)* @.omp_outlined..10 to void (i32, i32, ...)*))
	// CHECK10-NEXT: ret void			// CHECK10-NEXT: ret void
	Show All 33 Lines
	// CHECK10-NEXT: br label [[COND_END]]			// CHECK10-NEXT: br label [[COND_END]]
	// CHECK10: cond.end:			// CHECK10: cond.end:
	// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]			// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
	// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK10-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK10-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK10: omp.inner.for.cond:			// CHECK10: omp.inner.for.cond:
	// CHECK10-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !46
	// CHECK10-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK10-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !46
	// CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK10: omp.inner.for.body:			// CHECK10: omp.inner.for.body:
	// CHECK10-NEXT: invoke void @_ZN1SC1El(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]], i64 23)			// CHECK10-NEXT: invoke void @_ZN1SC1El(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]], i64 23)
	// CHECK10-NEXT: to label [[INVOKE_CONT:%.]] unwind label [[TERMINATE_LPAD:%.]]			// CHECK10-NEXT: to label [[INVOKE_CONT:%.]] unwind label [[TERMINATE_LPAD:%.]], !llvm.access.group !46
	// CHECK10: invoke.cont:			// CHECK10: invoke.cont:
	// CHECK10-NEXT: [[CALL:%.]] = invoke i8 @_ZN1ScvcEv(%struct.S nonnull align 8 dereferenceable(24) [[REF_TMP]])			// CHECK10-NEXT: [[CALL:%.]] = invoke i8 @_ZN1ScvcEv(%struct.S nonnull align 8 dereferenceable(24) [[REF_TMP]])
	// CHECK10-NEXT: to label [[INVOKE_CONT2:%.]] unwind label [[LPAD:%.]]			// CHECK10-NEXT: to label [[INVOKE_CONT2:%.]] unwind label [[LPAD:%.]], !llvm.access.group !46
	// CHECK10: invoke.cont2:			// CHECK10: invoke.cont2:
	// CHECK10-NEXT: [[TMP7:%.*]] = sext i8 [[CALL]] to i32			// CHECK10-NEXT: [[TMP7:%.*]] = sext i8 [[CALL]] to i32
	// CHECK10-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 [[TMP7]])			// CHECK10-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 [[TMP7]]), !llvm.access.group !46
	// CHECK10-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR6]]			// CHECK10-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR6]], !llvm.access.group !46
	// CHECK10-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK10-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !46
	// CHECK10-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64			// CHECK10-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
	// CHECK10-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK10-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !46
	// CHECK10-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64			// CHECK10-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
	// CHECK10-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..11 to void (i32, i32, ...)*), i64 [[TMP9]], i64 [[TMP11]])			// CHECK10-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..11 to void (i32, i32, ...)*), i64 [[TMP9]], i64 [[TMP11]]), !llvm.access.group !46
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK10: omp.inner.for.inc:			// CHECK10: omp.inner.for.inc:
	// CHECK10-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !46
	// CHECK10-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK10-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !46
	// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]			// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]
	// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !46
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP47:![0-9]+]]
	// CHECK10: lpad:			// CHECK10: lpad:
	// CHECK10-NEXT: [[TMP14:%.]] = landingpad { i8, i32 }			// CHECK10-NEXT: [[TMP14:%.]] = landingpad { i8, i32 }
	// CHECK10-NEXT: catch i8* null			// CHECK10-NEXT: catch i8* null
	// CHECK10-NEXT: [[TMP15:%.]] = extractvalue { i8, i32 } [[TMP14]], 0			// CHECK10-NEXT: [[TMP15:%.]] = extractvalue { i8, i32 } [[TMP14]], 0
	// CHECK10-NEXT: store i8* [[TMP15]], i8** [[EXN_SLOT]], align 8			// CHECK10-NEXT: store i8* [[TMP15]], i8** [[EXN_SLOT]], align 8, !llvm.access.group !46
	// CHECK10-NEXT: [[TMP16:%.]] = extractvalue { i8, i32 } [[TMP14]], 1			// CHECK10-NEXT: [[TMP16:%.]] = extractvalue { i8, i32 } [[TMP14]], 1
	// CHECK10-NEXT: store i32 [[TMP16]], i32* [[EHSELECTOR_SLOT]], align 4			// CHECK10-NEXT: store i32 [[TMP16]], i32* [[EHSELECTOR_SLOT]], align 4, !llvm.access.group !46
	// CHECK10-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR6]]			// CHECK10-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR6]], !llvm.access.group !46
	// CHECK10-NEXT: br label [[TERMINATE_HANDLER:%.*]]			// CHECK10-NEXT: br label [[TERMINATE_HANDLER:%.*]]
	// CHECK10: omp.inner.for.end:			// CHECK10: omp.inner.for.end:
	// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK10: omp.loop.exit:			// CHECK10: omp.loop.exit:
	// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])			// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
	// CHECK10-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK10-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK10-NEXT: [[TMP18:%.*]] = icmp ne i32 [[TMP17]], 0			// CHECK10-NEXT: [[TMP18:%.*]] = icmp ne i32 [[TMP17]], 0
	// CHECK10-NEXT: br i1 [[TMP18]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK10-NEXT: br i1 [[TMP18]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK10: .omp.final.then:			// CHECK10: .omp.final.then:
	// CHECK10-NEXT: store i32 100, i32* [[I]], align 4			// CHECK10-NEXT: store i32 100, i32* [[I]], align 4
	// CHECK10-NEXT: br label [[DOTOMP_FINAL_DONE]]			// CHECK10-NEXT: br label [[DOTOMP_FINAL_DONE]]
	// CHECK10: .omp.final.done:			// CHECK10: .omp.final.done:
	// CHECK10-NEXT: ret void			// CHECK10-NEXT: ret void
	// CHECK10: terminate.lpad:			// CHECK10: terminate.lpad:
	// CHECK10-NEXT: [[TMP19:%.]] = landingpad { i8, i32 }			// CHECK10-NEXT: [[TMP19:%.]] = landingpad { i8, i32 }
	// CHECK10-NEXT: catch i8* null			// CHECK10-NEXT: catch i8* null
	// CHECK10-NEXT: [[TMP20:%.]] = extractvalue { i8, i32 } [[TMP19]], 0			// CHECK10-NEXT: [[TMP20:%.]] = extractvalue { i8, i32 } [[TMP19]], 0
	// CHECK10-NEXT: call void @__clang_call_terminate(i8* [[TMP20]]) #[[ATTR10]]			// CHECK10-NEXT: call void @__clang_call_terminate(i8* [[TMP20]]) #[[ATTR10]], !llvm.access.group !46
	// CHECK10-NEXT: unreachable			// CHECK10-NEXT: unreachable
	// CHECK10: terminate.handler:			// CHECK10: terminate.handler:
	// CHECK10-NEXT: [[EXN:%.]] = load i8, i8** [[EXN_SLOT]], align 8			// CHECK10-NEXT: [[EXN:%.]] = load i8, i8** [[EXN_SLOT]], align 8, !llvm.access.group !46
	// CHECK10-NEXT: call void @__clang_call_terminate(i8* [[EXN]]) #[[ATTR10]]			// CHECK10-NEXT: call void @__clang_call_terminate(i8* [[EXN]]) #[[ATTR10]], !llvm.access.group !46
	// CHECK10-NEXT: unreachable			// CHECK10-NEXT: unreachable
	//			//
	//			//
	// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..11			// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..11
	// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i64 [[DOTPREVIOUS_LB_:%.]], i64 [[DOTPREVIOUS_UB_:%.]]) #[[ATTR3]] personality i8 bitcast (i32 (...)* @__gxx_personality_v0 to i8*) {			// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i64 [[DOTPREVIOUS_LB_:%.]], i64 [[DOTPREVIOUS_UB_:%.]]) #[[ATTR3]] personality i8 bitcast (i32 (...)* @__gxx_personality_v0 to i8*) {
	// CHECK10-NEXT: entry:			// CHECK10-NEXT: entry:
	// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8			// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8
	// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8			// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8
	Show All 33 Lines
	// CHECK10-NEXT: br label [[COND_END]]			// CHECK10-NEXT: br label [[COND_END]]
	// CHECK10: cond.end:			// CHECK10: cond.end:
	// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]			// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
	// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK10-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK10-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK10: omp.inner.for.cond:			// CHECK10: omp.inner.for.cond:
	// CHECK10-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !49
	// CHECK10-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK10-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !49
	// CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK10: omp.inner.for.body:			// CHECK10: omp.inner.for.body:
	// CHECK10-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !49
	// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !49
	// CHECK10-NEXT: invoke void @_Z3foov()			// CHECK10-NEXT: invoke void @_Z3foov()
	// CHECK10-NEXT: to label [[INVOKE_CONT:%.]] unwind label [[TERMINATE_LPAD:%.]]			// CHECK10-NEXT: to label [[INVOKE_CONT:%.]] unwind label [[TERMINATE_LPAD:%.]], !llvm.access.group !49
	// CHECK10: invoke.cont:			// CHECK10: invoke.cont:
	// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK10: omp.body.continue:			// CHECK10: omp.body.continue:
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK10: omp.inner.for.inc:			// CHECK10: omp.inner.for.inc:
	// CHECK10-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !49
	// CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK10-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4			// CHECK10-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !49
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP26:![0-9]+]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP50:![0-9]+]]
	// CHECK10: omp.inner.for.end:			// CHECK10: omp.inner.for.end:
	// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK10: omp.loop.exit:			// CHECK10: omp.loop.exit:
	// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])			// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
	// CHECK10-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK10-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK10-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK10-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK10-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK10-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK10: .omp.final.then:			// CHECK10: .omp.final.then:
	// CHECK10-NEXT: store i32 100, i32* [[I]], align 4			// CHECK10-NEXT: store i32 100, i32* [[I]], align 4
	// CHECK10-NEXT: br label [[DOTOMP_FINAL_DONE]]			// CHECK10-NEXT: br label [[DOTOMP_FINAL_DONE]]
	// CHECK10: .omp.final.done:			// CHECK10: .omp.final.done:
	// CHECK10-NEXT: ret void			// CHECK10-NEXT: ret void
	// CHECK10: terminate.lpad:			// CHECK10: terminate.lpad:
	// CHECK10-NEXT: [[TMP13:%.]] = landingpad { i8, i32 }			// CHECK10-NEXT: [[TMP13:%.]] = landingpad { i8, i32 }
	// CHECK10-NEXT: catch i8* null			// CHECK10-NEXT: catch i8* null
	// CHECK10-NEXT: [[TMP14:%.]] = extractvalue { i8, i32 } [[TMP13]], 0			// CHECK10-NEXT: [[TMP14:%.]] = extractvalue { i8, i32 } [[TMP13]], 0
	// CHECK10-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]]			// CHECK10-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]], !llvm.access.group !49
	// CHECK10-NEXT: unreachable			// CHECK10-NEXT: unreachable
	//			//
	//			//
	// CHECK10-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg			// CHECK10-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
	// CHECK10-SAME: () #[[ATTR9:[0-9]+]] {			// CHECK10-SAME: () #[[ATTR9:[0-9]+]] {
	// CHECK10-NEXT: entry:			// CHECK10-NEXT: entry:
	// CHECK10-NEXT: call void @__tgt_register_requires(i64 1)			// CHECK10-NEXT: call void @__tgt_register_requires(i64 1)
	// CHECK10-NEXT: ret void			// CHECK10-NEXT: ret void
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	// CHECK13-NEXT: br label [[COND_END]]			// CHECK13-NEXT: br label [[COND_END]]
	// CHECK13: cond.end:			// CHECK13: cond.end:
	// CHECK13-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]			// CHECK13-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
	// CHECK13-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK13-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK13-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK13-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK13-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK13-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK13: omp.inner.for.cond:			// CHECK13: omp.inner.for.cond:
	// CHECK13-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK13-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK13-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK13-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !13
	// CHECK13-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK13-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK13-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK13-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK13: omp.inner.for.body:			// CHECK13: omp.inner.for.body:
	// CHECK13-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 2)			// CHECK13-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 2), !llvm.access.group !13
	// CHECK13-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK13-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !13
	// CHECK13-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64			// CHECK13-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
	// CHECK13-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK13-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !13
	// CHECK13-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK13-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK13-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..1 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]])			// CHECK13-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..1 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !13
	// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK13: omp.inner.for.inc:			// CHECK13: omp.inner.for.inc:
	// CHECK13-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK13-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK13-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK13-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !13
	// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]			// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
	// CHECK13-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK13-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]			// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]]
	// CHECK13: omp.inner.for.end:			// CHECK13: omp.inner.for.end:
	// CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK13: omp.loop.exit:			// CHECK13: omp.loop.exit:
	// CHECK13-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])			// CHECK13-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
	// CHECK13-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK13-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK13-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0			// CHECK13-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
	// CHECK13-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK13-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK13: .omp.final.then:			// CHECK13: .omp.final.then:
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	// CHECK13-NEXT: br label [[COND_END]]			// CHECK13-NEXT: br label [[COND_END]]
	// CHECK13: cond.end:			// CHECK13: cond.end:
	// CHECK13-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]			// CHECK13-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
	// CHECK13-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK13-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK13-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK13-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK13-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK13-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK13: omp.inner.for.cond:			// CHECK13: omp.inner.for.cond:
	// CHECK13-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK13-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !17
	// CHECK13-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK13-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !17
	// CHECK13-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK13-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK13-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK13-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK13: omp.inner.for.body:			// CHECK13: omp.inner.for.body:
	// CHECK13-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK13-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !17
	// CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK13-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK13-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !17
	// CHECK13-NEXT: invoke void @_Z3foov()			// CHECK13-NEXT: invoke void @_Z3foov()
	// CHECK13-NEXT: to label [[INVOKE_CONT:%.]] unwind label [[TERMINATE_LPAD:%.]]			// CHECK13-NEXT: to label [[INVOKE_CONT:%.]] unwind label [[TERMINATE_LPAD:%.]], !llvm.access.group !17
	// CHECK13: invoke.cont:			// CHECK13: invoke.cont:
	// CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK13: omp.body.continue:			// CHECK13: omp.body.continue:
	// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK13: omp.inner.for.inc:			// CHECK13: omp.inner.for.inc:
	// CHECK13-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK13-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !17
	// CHECK13-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK13-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK13-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4			// CHECK13-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17
	// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]]			// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]]
	// CHECK13: omp.inner.for.end:			// CHECK13: omp.inner.for.end:
	// CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK13: omp.loop.exit:			// CHECK13: omp.loop.exit:
	// CHECK13-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])			// CHECK13-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
	// CHECK13-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK13-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK13-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK13-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK13-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK13-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK13: .omp.final.then:			// CHECK13: .omp.final.then:
	// CHECK13-NEXT: store i32 100, i32* [[I]], align 4			// CHECK13-NEXT: store i32 100, i32* [[I]], align 4
	// CHECK13-NEXT: br label [[DOTOMP_FINAL_DONE]]			// CHECK13-NEXT: br label [[DOTOMP_FINAL_DONE]]
	// CHECK13: .omp.final.done:			// CHECK13: .omp.final.done:
	// CHECK13-NEXT: ret void			// CHECK13-NEXT: ret void
	// CHECK13: terminate.lpad:			// CHECK13: terminate.lpad:
	// CHECK13-NEXT: [[TMP13:%.]] = landingpad { i8, i32 }			// CHECK13-NEXT: [[TMP13:%.]] = landingpad { i8, i32 }
	// CHECK13-NEXT: catch i8* null			// CHECK13-NEXT: catch i8* null
	// CHECK13-NEXT: [[TMP14:%.]] = extractvalue { i8, i32 } [[TMP13]], 0			// CHECK13-NEXT: [[TMP14:%.]] = extractvalue { i8, i32 } [[TMP13]], 0
	// CHECK13-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10:[0-9]+]]			// CHECK13-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10:[0-9]+]], !llvm.access.group !17
	// CHECK13-NEXT: unreachable			// CHECK13-NEXT: unreachable
	//			//
	//			//
	// CHECK13-LABEL: define {{[^@]+}}@__clang_call_terminate			// CHECK13-LABEL: define {{[^@]+}}@__clang_call_terminate
	// CHECK13-SAME: (i8* [[TMP0:%.*]]) #[[ATTR5:[0-9]+]] comdat {			// CHECK13-SAME: (i8* [[TMP0:%.*]]) #[[ATTR5:[0-9]+]] comdat {
	// CHECK13-NEXT: [[TMP2:%.]] = call i8 @__cxa_begin_catch(i8* [[TMP0]]) #[[ATTR6]]			// CHECK13-NEXT: [[TMP2:%.]] = call i8 @__cxa_begin_catch(i8* [[TMP0]]) #[[ATTR6]]
	// CHECK13-NEXT: call void @_ZSt9terminatev() #[[ATTR10]]			// CHECK13-NEXT: call void @_ZSt9terminatev() #[[ATTR10]]
	// CHECK13-NEXT: unreachable			// CHECK13-NEXT: unreachable
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	// CHECK13-NEXT: br label [[COND_END]]			// CHECK13-NEXT: br label [[COND_END]]
	// CHECK13: cond.end:			// CHECK13: cond.end:
	// CHECK13-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]			// CHECK13-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
	// CHECK13-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK13-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK13-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK13-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK13-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK13-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK13: omp.inner.for.cond:			// CHECK13: omp.inner.for.cond:
	// CHECK13-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK13-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !22
	// CHECK13-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK13-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !22
	// CHECK13-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK13-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK13-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK13-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK13: omp.inner.for.body:			// CHECK13: omp.inner.for.body:
	// CHECK13-NEXT: [[TMP8:%.]] = load i8, i8 [[TMP0]], align 1			// CHECK13-NEXT: [[TMP8:%.]] = load i8, i8 [[TMP0]], align 1, !llvm.access.group !22
	// CHECK13-NEXT: [[TMP9:%.*]] = sext i8 [[TMP8]] to i32			// CHECK13-NEXT: [[TMP9:%.*]] = sext i8 [[TMP8]] to i32
	// CHECK13-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP2]], i32 [[TMP9]])			// CHECK13-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP2]], i32 [[TMP9]]), !llvm.access.group !22
	// CHECK13-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK13-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !22
	// CHECK13-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64			// CHECK13-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
	// CHECK13-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK13-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !22
	// CHECK13-NEXT: [[TMP13:%.*]] = zext i32 [[TMP12]] to i64			// CHECK13-NEXT: [[TMP13:%.*]] = zext i32 [[TMP12]] to i64
	// CHECK13-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..3 to void (i32, i32, ...)*), i64 [[TMP11]], i64 [[TMP13]])			// CHECK13-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..3 to void (i32, i32, ...)*), i64 [[TMP11]], i64 [[TMP13]]), !llvm.access.group !22
	// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK13: omp.inner.for.inc:			// CHECK13: omp.inner.for.inc:
	// CHECK13-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK13-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !22
	// CHECK13-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK13-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !22
	// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP14]], [[TMP15]]			// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP14]], [[TMP15]]
	// CHECK13-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK13-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
	// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]]			// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]]
	// CHECK13: omp.inner.for.end:			// CHECK13: omp.inner.for.end:
	// CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK13: omp.loop.exit:			// CHECK13: omp.loop.exit:
	// CHECK13-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])			// CHECK13-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
	// CHECK13-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK13-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK13-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0			// CHECK13-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0
	// CHECK13-NEXT: br i1 [[TMP17]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK13-NEXT: br i1 [[TMP17]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK13: .omp.final.then:			// CHECK13: .omp.final.then:
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	// CHECK13-NEXT: br label [[COND_END]]			// CHECK13-NEXT: br label [[COND_END]]
	// CHECK13: cond.end:			// CHECK13: cond.end:
	// CHECK13-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]			// CHECK13-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
	// CHECK13-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK13-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK13-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK13-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK13-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK13-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK13: omp.inner.for.cond:			// CHECK13: omp.inner.for.cond:
	// CHECK13-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK13-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !25
	// CHECK13-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK13-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !25
	// CHECK13-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK13-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK13-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK13-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK13: omp.inner.for.body:			// CHECK13: omp.inner.for.body:
	// CHECK13-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK13-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !25
	// CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK13-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK13-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !25
	// CHECK13-NEXT: invoke void @_Z3foov()			// CHECK13-NEXT: invoke void @_Z3foov()
	// CHECK13-NEXT: to label [[INVOKE_CONT:%.]] unwind label [[TERMINATE_LPAD:%.]]			// CHECK13-NEXT: to label [[INVOKE_CONT:%.]] unwind label [[TERMINATE_LPAD:%.]], !llvm.access.group !25
	// CHECK13: invoke.cont:			// CHECK13: invoke.cont:
	// CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK13: omp.body.continue:			// CHECK13: omp.body.continue:
	// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK13: omp.inner.for.inc:			// CHECK13: omp.inner.for.inc:
	// CHECK13-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK13-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !25
	// CHECK13-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK13-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK13-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4			// CHECK13-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25
	// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]]			// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP26:![0-9]+]]
	// CHECK13: omp.inner.for.end:			// CHECK13: omp.inner.for.end:
	// CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK13: omp.loop.exit:			// CHECK13: omp.loop.exit:
	// CHECK13-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])			// CHECK13-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
	// CHECK13-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK13-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK13-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK13-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK13-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK13-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK13: .omp.final.then:			// CHECK13: .omp.final.then:
	// CHECK13-NEXT: store i32 100, i32* [[I]], align 4			// CHECK13-NEXT: store i32 100, i32* [[I]], align 4
	// CHECK13-NEXT: br label [[DOTOMP_FINAL_DONE]]			// CHECK13-NEXT: br label [[DOTOMP_FINAL_DONE]]
	// CHECK13: .omp.final.done:			// CHECK13: .omp.final.done:
	// CHECK13-NEXT: ret void			// CHECK13-NEXT: ret void
	// CHECK13: terminate.lpad:			// CHECK13: terminate.lpad:
	// CHECK13-NEXT: [[TMP13:%.]] = landingpad { i8, i32 }			// CHECK13-NEXT: [[TMP13:%.]] = landingpad { i8, i32 }
	// CHECK13-NEXT: catch i8* null			// CHECK13-NEXT: catch i8* null
	// CHECK13-NEXT: [[TMP14:%.]] = extractvalue { i8, i32 } [[TMP13]], 0			// CHECK13-NEXT: [[TMP14:%.]] = extractvalue { i8, i32 } [[TMP13]], 0
	// CHECK13-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]]			// CHECK13-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]], !llvm.access.group !25
	// CHECK13-NEXT: unreachable			// CHECK13-NEXT: unreachable
	//			//
	//			//
	// CHECK13-LABEL: define {{[^@]+}}@_Z5tmainIcLi5EEiv			// CHECK13-LABEL: define {{[^@]+}}@_Z5tmainIcLi5EEiv
	// CHECK13-SAME: () #[[ATTR7:[0-9]+]] comdat {			// CHECK13-SAME: () #[[ATTR7:[0-9]+]] comdat {
	// CHECK13-NEXT: entry:			// CHECK13-NEXT: entry:
	// CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4			// CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4
	// CHECK13-NEXT: [[_TMP1:%.*]] = alloca i32, align 4			// CHECK13-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
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	// CHECK13-NEXT: br label [[COND_END]]			// CHECK13-NEXT: br label [[COND_END]]
	// CHECK13: cond.end:			// CHECK13: cond.end:
	// CHECK13-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]			// CHECK13-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
	// CHECK13-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK13-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK13-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK13-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK13-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK13-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK13: omp.inner.for.cond:			// CHECK13: omp.inner.for.cond:
	// CHECK13-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK13-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !28
	// CHECK13-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK13-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !28
	// CHECK13-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK13-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK13-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK13-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK13: omp.inner.for.body:			// CHECK13: omp.inner.for.body:
	// CHECK13-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 5)			// CHECK13-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 5), !llvm.access.group !28
	// CHECK13-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK13-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !28
	// CHECK13-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64			// CHECK13-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
	// CHECK13-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK13-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !28
	// CHECK13-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK13-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK13-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..5 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]])			// CHECK13-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..5 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !28
	// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK13: omp.inner.for.inc:			// CHECK13: omp.inner.for.inc:
	// CHECK13-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK13-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !28
	// CHECK13-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK13-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !28
	// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]			// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
	// CHECK13-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK13-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28
	// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]			// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP29:![0-9]+]]
	// CHECK13: omp.inner.for.end:			// CHECK13: omp.inner.for.end:
	// CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK13: omp.loop.exit:			// CHECK13: omp.loop.exit:
	// CHECK13-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])			// CHECK13-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
	// CHECK13-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK13-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK13-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0			// CHECK13-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
	// CHECK13-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK13-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK13: .omp.final.then:			// CHECK13: .omp.final.then:
	▲ Show 20 Lines • Show All 44 Lines • ▼ Show 20 Lines
	// CHECK13-NEXT: br label [[COND_END]]			// CHECK13-NEXT: br label [[COND_END]]
	// CHECK13: cond.end:			// CHECK13: cond.end:
	// CHECK13-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]			// CHECK13-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
	// CHECK13-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK13-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK13-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK13-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK13-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK13-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK13: omp.inner.for.cond:			// CHECK13: omp.inner.for.cond:
	// CHECK13-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK13-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !31
	// CHECK13-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK13-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !31
	// CHECK13-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK13-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK13-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK13-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK13: omp.inner.for.body:			// CHECK13: omp.inner.for.body:
	// CHECK13-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK13-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !31
	// CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK13-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK13-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !31
	// CHECK13-NEXT: invoke void @_Z3foov()			// CHECK13-NEXT: invoke void @_Z3foov()
	// CHECK13-NEXT: to label [[INVOKE_CONT:%.]] unwind label [[TERMINATE_LPAD:%.]]			// CHECK13-NEXT: to label [[INVOKE_CONT:%.]] unwind label [[TERMINATE_LPAD:%.]], !llvm.access.group !31
	// CHECK13: invoke.cont:			// CHECK13: invoke.cont:
	// CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK13: omp.body.continue:			// CHECK13: omp.body.continue:
	// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK13: omp.inner.for.inc:			// CHECK13: omp.inner.for.inc:
	// CHECK13-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK13-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !31
	// CHECK13-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK13-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK13-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4			// CHECK13-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !31
	// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]]			// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP32:![0-9]+]]
	// CHECK13: omp.inner.for.end:			// CHECK13: omp.inner.for.end:
	// CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK13: omp.loop.exit:			// CHECK13: omp.loop.exit:
	// CHECK13-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])			// CHECK13-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
	// CHECK13-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK13-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK13-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK13-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK13-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK13-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK13: .omp.final.then:			// CHECK13: .omp.final.then:
	// CHECK13-NEXT: store i32 100, i32* [[I]], align 4			// CHECK13-NEXT: store i32 100, i32* [[I]], align 4
	// CHECK13-NEXT: br label [[DOTOMP_FINAL_DONE]]			// CHECK13-NEXT: br label [[DOTOMP_FINAL_DONE]]
	// CHECK13: .omp.final.done:			// CHECK13: .omp.final.done:
	// CHECK13-NEXT: ret void			// CHECK13-NEXT: ret void
	// CHECK13: terminate.lpad:			// CHECK13: terminate.lpad:
	// CHECK13-NEXT: [[TMP13:%.]] = landingpad { i8, i32 }			// CHECK13-NEXT: [[TMP13:%.]] = landingpad { i8, i32 }
	// CHECK13-NEXT: catch i8* null			// CHECK13-NEXT: catch i8* null
	// CHECK13-NEXT: [[TMP14:%.]] = extractvalue { i8, i32 } [[TMP13]], 0			// CHECK13-NEXT: [[TMP14:%.]] = extractvalue { i8, i32 } [[TMP13]], 0
	// CHECK13-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]]			// CHECK13-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]], !llvm.access.group !31
	// CHECK13-NEXT: unreachable			// CHECK13-NEXT: unreachable
	//			//
	//			//
	// CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l57			// CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l57
	// CHECK13-SAME: () #[[ATTR3]] {			// CHECK13-SAME: () #[[ATTR3]] {
	// CHECK13-NEXT: entry:			// CHECK13-NEXT: entry:
	// CHECK13-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32, i32, ...)* bitcast (void (i32, i32)* @.omp_outlined..6 to void (i32, i32, ...)*))			// CHECK13-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32, i32, ...)* bitcast (void (i32, i32)* @.omp_outlined..6 to void (i32, i32, ...)*))
	// CHECK13-NEXT: ret void			// CHECK13-NEXT: ret void
	Show All 30 Lines
	// CHECK13-NEXT: br label [[COND_END]]			// CHECK13-NEXT: br label [[COND_END]]
	// CHECK13: cond.end:			// CHECK13: cond.end:
	// CHECK13-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]			// CHECK13-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
	// CHECK13-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK13-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK13-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK13-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK13-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK13-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK13: omp.inner.for.cond:			// CHECK13: omp.inner.for.cond:
	// CHECK13-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK13-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !34
	// CHECK13-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK13-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !34
	// CHECK13-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK13-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK13-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK13-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK13: omp.inner.for.body:			// CHECK13: omp.inner.for.body:
	// CHECK13-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 23)			// CHECK13-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 23), !llvm.access.group !34
	// CHECK13-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK13-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !34
	// CHECK13-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64			// CHECK13-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
	// CHECK13-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK13-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !34
	// CHECK13-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK13-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK13-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..7 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]])			// CHECK13-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..7 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !34
	// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK13: omp.inner.for.inc:			// CHECK13: omp.inner.for.inc:
	// CHECK13-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK13-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !34
	// CHECK13-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK13-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !34
	// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]			// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
	// CHECK13-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK13-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !34
	// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]]			// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP35:![0-9]+]]
	// CHECK13: omp.inner.for.end:			// CHECK13: omp.inner.for.end:
	// CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK13: omp.loop.exit:			// CHECK13: omp.loop.exit:
	// CHECK13-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])			// CHECK13-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
	// CHECK13-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK13-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK13-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0			// CHECK13-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
	// CHECK13-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK13-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK13: .omp.final.then:			// CHECK13: .omp.final.then:
	▲ Show 20 Lines • Show All 44 Lines • ▼ Show 20 Lines
	// CHECK13-NEXT: br label [[COND_END]]			// CHECK13-NEXT: br label [[COND_END]]
	// CHECK13: cond.end:			// CHECK13: cond.end:
	// CHECK13-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]			// CHECK13-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
	// CHECK13-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK13-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK13-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK13-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK13-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK13-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK13: omp.inner.for.cond:			// CHECK13: omp.inner.for.cond:
	// CHECK13-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK13-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !37
	// CHECK13-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK13-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !37
	// CHECK13-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK13-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK13-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK13-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK13: omp.inner.for.body:			// CHECK13: omp.inner.for.body:
	// CHECK13-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK13-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !37
	// CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK13-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK13-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !37
	// CHECK13-NEXT: invoke void @_Z3foov()			// CHECK13-NEXT: invoke void @_Z3foov()
	// CHECK13-NEXT: to label [[INVOKE_CONT:%.]] unwind label [[TERMINATE_LPAD:%.]]			// CHECK13-NEXT: to label [[INVOKE_CONT:%.]] unwind label [[TERMINATE_LPAD:%.]], !llvm.access.group !37
	// CHECK13: invoke.cont:			// CHECK13: invoke.cont:
	// CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK13: omp.body.continue:			// CHECK13: omp.body.continue:
	// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK13: omp.inner.for.inc:			// CHECK13: omp.inner.for.inc:
	// CHECK13-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK13-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !37
	// CHECK13-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK13-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK13-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4			// CHECK13-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !37
	// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]]			// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP38:![0-9]+]]
	// CHECK13: omp.inner.for.end:			// CHECK13: omp.inner.for.end:
	// CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK13: omp.loop.exit:			// CHECK13: omp.loop.exit:
	// CHECK13-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])			// CHECK13-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
	// CHECK13-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK13-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK13-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK13-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK13-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK13-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK13: .omp.final.then:			// CHECK13: .omp.final.then:
	// CHECK13-NEXT: store i32 100, i32* [[I]], align 4			// CHECK13-NEXT: store i32 100, i32* [[I]], align 4
	// CHECK13-NEXT: br label [[DOTOMP_FINAL_DONE]]			// CHECK13-NEXT: br label [[DOTOMP_FINAL_DONE]]
	// CHECK13: .omp.final.done:			// CHECK13: .omp.final.done:
	// CHECK13-NEXT: ret void			// CHECK13-NEXT: ret void
	// CHECK13: terminate.lpad:			// CHECK13: terminate.lpad:
	// CHECK13-NEXT: [[TMP13:%.]] = landingpad { i8, i32 }			// CHECK13-NEXT: [[TMP13:%.]] = landingpad { i8, i32 }
	// CHECK13-NEXT: catch i8* null			// CHECK13-NEXT: catch i8* null
	// CHECK13-NEXT: [[TMP14:%.]] = extractvalue { i8, i32 } [[TMP13]], 0			// CHECK13-NEXT: [[TMP14:%.]] = extractvalue { i8, i32 } [[TMP13]], 0
	// CHECK13-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]]			// CHECK13-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]], !llvm.access.group !37
	// CHECK13-NEXT: unreachable			// CHECK13-NEXT: unreachable
	//			//
	//			//
	// CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l52			// CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l52
	// CHECK13-SAME: () #[[ATTR3]] {			// CHECK13-SAME: () #[[ATTR3]] {
	// CHECK13-NEXT: entry:			// CHECK13-NEXT: entry:
	// CHECK13-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32, i32, ...)* bitcast (void (i32, i32)* @.omp_outlined..8 to void (i32, i32, ...)*))			// CHECK13-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32, i32, ...)* bitcast (void (i32, i32)* @.omp_outlined..8 to void (i32, i32, ...)*))
	// CHECK13-NEXT: ret void			// CHECK13-NEXT: ret void
	Show All 30 Lines
	// CHECK13-NEXT: br label [[COND_END]]			// CHECK13-NEXT: br label [[COND_END]]
	// CHECK13: cond.end:			// CHECK13: cond.end:
	// CHECK13-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]			// CHECK13-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
	// CHECK13-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK13-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK13-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK13-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK13-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK13-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK13: omp.inner.for.cond:			// CHECK13: omp.inner.for.cond:
	// CHECK13-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK13-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !40
	// CHECK13-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK13-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !40
	// CHECK13-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK13-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK13-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK13-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK13: omp.inner.for.body:			// CHECK13: omp.inner.for.body:
	// CHECK13-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 1)			// CHECK13-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 1), !llvm.access.group !40
	// CHECK13-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK13-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !40
	// CHECK13-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64			// CHECK13-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
	// CHECK13-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK13-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !40
	// CHECK13-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK13-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK13-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..9 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]])			// CHECK13-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..9 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !40
	// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK13: omp.inner.for.inc:			// CHECK13: omp.inner.for.inc:
	// CHECK13-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK13-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !40
	// CHECK13-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK13-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !40
	// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]			// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
	// CHECK13-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK13-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !40
	// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]]			// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP41:![0-9]+]]
	// CHECK13: omp.inner.for.end:			// CHECK13: omp.inner.for.end:
	// CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK13: omp.loop.exit:			// CHECK13: omp.loop.exit:
	// CHECK13-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])			// CHECK13-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
	// CHECK13-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK13-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK13-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0			// CHECK13-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
	// CHECK13-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK13-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK13: .omp.final.then:			// CHECK13: .omp.final.then:
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	// CHECK13-NEXT: br label [[COND_END]]			// CHECK13-NEXT: br label [[COND_END]]
	// CHECK13: cond.end:			// CHECK13: cond.end:
	// CHECK13-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]			// CHECK13-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
	// CHECK13-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK13-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK13-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK13-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK13-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK13-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK13: omp.inner.for.cond:			// CHECK13: omp.inner.for.cond:
	// CHECK13-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK13-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !43
	// CHECK13-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK13-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !43
	// CHECK13-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK13-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK13-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK13-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK13: omp.inner.for.body:			// CHECK13: omp.inner.for.body:
	// CHECK13-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK13-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !43
	// CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK13-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK13-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !43
	// CHECK13-NEXT: invoke void @_Z3foov()			// CHECK13-NEXT: invoke void @_Z3foov()
	// CHECK13-NEXT: to label [[INVOKE_CONT:%.]] unwind label [[TERMINATE_LPAD:%.]]			// CHECK13-NEXT: to label [[INVOKE_CONT:%.]] unwind label [[TERMINATE_LPAD:%.]], !llvm.access.group !43
	// CHECK13: invoke.cont:			// CHECK13: invoke.cont:
	// CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK13: omp.body.continue:			// CHECK13: omp.body.continue:
	// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK13: omp.inner.for.inc:			// CHECK13: omp.inner.for.inc:
	// CHECK13-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK13-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !43
	// CHECK13-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK13-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK13-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4			// CHECK13-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !43
	// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP24:![0-9]+]]			// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP44:![0-9]+]]
	// CHECK13: omp.inner.for.end:			// CHECK13: omp.inner.for.end:
	// CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK13: omp.loop.exit:			// CHECK13: omp.loop.exit:
	// CHECK13-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])			// CHECK13-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
	// CHECK13-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK13-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK13-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK13-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK13-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK13-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK13: .omp.final.then:			// CHECK13: .omp.final.then:
	// CHECK13-NEXT: store i32 100, i32* [[I]], align 4			// CHECK13-NEXT: store i32 100, i32* [[I]], align 4
	// CHECK13-NEXT: br label [[DOTOMP_FINAL_DONE]]			// CHECK13-NEXT: br label [[DOTOMP_FINAL_DONE]]
	// CHECK13: .omp.final.done:			// CHECK13: .omp.final.done:
	// CHECK13-NEXT: ret void			// CHECK13-NEXT: ret void
	// CHECK13: terminate.lpad:			// CHECK13: terminate.lpad:
	// CHECK13-NEXT: [[TMP13:%.]] = landingpad { i8, i32 }			// CHECK13-NEXT: [[TMP13:%.]] = landingpad { i8, i32 }
	// CHECK13-NEXT: catch i8* null			// CHECK13-NEXT: catch i8* null
	// CHECK13-NEXT: [[TMP14:%.]] = extractvalue { i8, i32 } [[TMP13]], 0			// CHECK13-NEXT: [[TMP14:%.]] = extractvalue { i8, i32 } [[TMP13]], 0
	// CHECK13-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]]			// CHECK13-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]], !llvm.access.group !43
	// CHECK13-NEXT: unreachable			// CHECK13-NEXT: unreachable
	//			//
	//			//
	// CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l57			// CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l57
	// CHECK13-SAME: () #[[ATTR3]] {			// CHECK13-SAME: () #[[ATTR3]] {
	// CHECK13-NEXT: entry:			// CHECK13-NEXT: entry:
	// CHECK13-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32, i32, ...)* bitcast (void (i32, i32)* @.omp_outlined..10 to void (i32, i32, ...)*))			// CHECK13-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32, i32, ...)* bitcast (void (i32, i32)* @.omp_outlined..10 to void (i32, i32, ...)*))
	// CHECK13-NEXT: ret void			// CHECK13-NEXT: ret void
	Show All 33 Lines
	// CHECK13-NEXT: br label [[COND_END]]			// CHECK13-NEXT: br label [[COND_END]]
	// CHECK13: cond.end:			// CHECK13: cond.end:
	// CHECK13-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]			// CHECK13-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
	// CHECK13-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK13-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK13-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK13-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK13-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK13-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK13: omp.inner.for.cond:			// CHECK13: omp.inner.for.cond:
	// CHECK13-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK13-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !46
	// CHECK13-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK13-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !46
	// CHECK13-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK13-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK13-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK13-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK13: omp.inner.for.body:			// CHECK13: omp.inner.for.body:
	// CHECK13-NEXT: invoke void @_ZN1SC1El(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]], i64 23)			// CHECK13-NEXT: invoke void @_ZN1SC1El(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]], i64 23)
	// CHECK13-NEXT: to label [[INVOKE_CONT:%.]] unwind label [[TERMINATE_LPAD:%.]]			// CHECK13-NEXT: to label [[INVOKE_CONT:%.]] unwind label [[TERMINATE_LPAD:%.]], !llvm.access.group !46
	// CHECK13: invoke.cont:			// CHECK13: invoke.cont:
	// CHECK13-NEXT: [[CALL:%.]] = invoke i8 @_ZN1ScvcEv(%struct.S nonnull align 8 dereferenceable(24) [[REF_TMP]])			// CHECK13-NEXT: [[CALL:%.]] = invoke i8 @_ZN1ScvcEv(%struct.S nonnull align 8 dereferenceable(24) [[REF_TMP]])
	// CHECK13-NEXT: to label [[INVOKE_CONT2:%.]] unwind label [[LPAD:%.]]			// CHECK13-NEXT: to label [[INVOKE_CONT2:%.]] unwind label [[LPAD:%.]], !llvm.access.group !46
	// CHECK13: invoke.cont2:			// CHECK13: invoke.cont2:
	// CHECK13-NEXT: [[TMP7:%.*]] = sext i8 [[CALL]] to i32			// CHECK13-NEXT: [[TMP7:%.*]] = sext i8 [[CALL]] to i32
	// CHECK13-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 [[TMP7]])			// CHECK13-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 [[TMP7]]), !llvm.access.group !46
	// CHECK13-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR6]]			// CHECK13-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR6]], !llvm.access.group !46
	// CHECK13-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK13-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !46
	// CHECK13-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64			// CHECK13-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
	// CHECK13-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK13-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !46
	// CHECK13-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64			// CHECK13-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
	// CHECK13-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..11 to void (i32, i32, ...)*), i64 [[TMP9]], i64 [[TMP11]])			// CHECK13-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..11 to void (i32, i32, ...)*), i64 [[TMP9]], i64 [[TMP11]]), !llvm.access.group !46
	// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK13: omp.inner.for.inc:			// CHECK13: omp.inner.for.inc:
	// CHECK13-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK13-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !46
	// CHECK13-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK13-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !46
	// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]			// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]
	// CHECK13-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK13-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !46
	// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]]			// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP47:![0-9]+]]
	// CHECK13: lpad:			// CHECK13: lpad:
	// CHECK13-NEXT: [[TMP14:%.]] = landingpad { i8, i32 }			// CHECK13-NEXT: [[TMP14:%.]] = landingpad { i8, i32 }
	// CHECK13-NEXT: catch i8* null			// CHECK13-NEXT: catch i8* null
	// CHECK13-NEXT: [[TMP15:%.]] = extractvalue { i8, i32 } [[TMP14]], 0			// CHECK13-NEXT: [[TMP15:%.]] = extractvalue { i8, i32 } [[TMP14]], 0
	// CHECK13-NEXT: store i8* [[TMP15]], i8** [[EXN_SLOT]], align 8			// CHECK13-NEXT: store i8* [[TMP15]], i8** [[EXN_SLOT]], align 8, !llvm.access.group !46
	// CHECK13-NEXT: [[TMP16:%.]] = extractvalue { i8, i32 } [[TMP14]], 1			// CHECK13-NEXT: [[TMP16:%.]] = extractvalue { i8, i32 } [[TMP14]], 1
	// CHECK13-NEXT: store i32 [[TMP16]], i32* [[EHSELECTOR_SLOT]], align 4			// CHECK13-NEXT: store i32 [[TMP16]], i32* [[EHSELECTOR_SLOT]], align 4, !llvm.access.group !46
	// CHECK13-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR6]]			// CHECK13-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR6]], !llvm.access.group !46
	// CHECK13-NEXT: br label [[TERMINATE_HANDLER:%.*]]			// CHECK13-NEXT: br label [[TERMINATE_HANDLER:%.*]]
	// CHECK13: omp.inner.for.end:			// CHECK13: omp.inner.for.end:
	// CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK13: omp.loop.exit:			// CHECK13: omp.loop.exit:
	// CHECK13-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])			// CHECK13-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
	// CHECK13-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK13-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK13-NEXT: [[TMP18:%.*]] = icmp ne i32 [[TMP17]], 0			// CHECK13-NEXT: [[TMP18:%.*]] = icmp ne i32 [[TMP17]], 0
	// CHECK13-NEXT: br i1 [[TMP18]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK13-NEXT: br i1 [[TMP18]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK13: .omp.final.then:			// CHECK13: .omp.final.then:
	// CHECK13-NEXT: store i32 100, i32* [[I]], align 4			// CHECK13-NEXT: store i32 100, i32* [[I]], align 4
	// CHECK13-NEXT: br label [[DOTOMP_FINAL_DONE]]			// CHECK13-NEXT: br label [[DOTOMP_FINAL_DONE]]
	// CHECK13: .omp.final.done:			// CHECK13: .omp.final.done:
	// CHECK13-NEXT: ret void			// CHECK13-NEXT: ret void
	// CHECK13: terminate.lpad:			// CHECK13: terminate.lpad:
	// CHECK13-NEXT: [[TMP19:%.]] = landingpad { i8, i32 }			// CHECK13-NEXT: [[TMP19:%.]] = landingpad { i8, i32 }
	// CHECK13-NEXT: catch i8* null			// CHECK13-NEXT: catch i8* null
	// CHECK13-NEXT: [[TMP20:%.]] = extractvalue { i8, i32 } [[TMP19]], 0			// CHECK13-NEXT: [[TMP20:%.]] = extractvalue { i8, i32 } [[TMP19]], 0
	// CHECK13-NEXT: call void @__clang_call_terminate(i8* [[TMP20]]) #[[ATTR10]]			// CHECK13-NEXT: call void @__clang_call_terminate(i8* [[TMP20]]) #[[ATTR10]], !llvm.access.group !46
	// CHECK13-NEXT: unreachable			// CHECK13-NEXT: unreachable
	// CHECK13: terminate.handler:			// CHECK13: terminate.handler:
	// CHECK13-NEXT: [[EXN:%.]] = load i8, i8** [[EXN_SLOT]], align 8			// CHECK13-NEXT: [[EXN:%.]] = load i8, i8** [[EXN_SLOT]], align 8, !llvm.access.group !46
	// CHECK13-NEXT: call void @__clang_call_terminate(i8* [[EXN]]) #[[ATTR10]]			// CHECK13-NEXT: call void @__clang_call_terminate(i8* [[EXN]]) #[[ATTR10]], !llvm.access.group !46
	// CHECK13-NEXT: unreachable			// CHECK13-NEXT: unreachable
	//			//
	//			//
	// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..11			// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..11
	// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i64 [[DOTPREVIOUS_LB_:%.]], i64 [[DOTPREVIOUS_UB_:%.]]) #[[ATTR3]] personality i8 bitcast (i32 (...)* @__gxx_personality_v0 to i8*) {			// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i64 [[DOTPREVIOUS_LB_:%.]], i64 [[DOTPREVIOUS_UB_:%.]]) #[[ATTR3]] personality i8 bitcast (i32 (...)* @__gxx_personality_v0 to i8*) {
	// CHECK13-NEXT: entry:			// CHECK13-NEXT: entry:
	// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8			// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8
	// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8			// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8
	Show All 33 Lines
	// CHECK13-NEXT: br label [[COND_END]]			// CHECK13-NEXT: br label [[COND_END]]
	// CHECK13: cond.end:			// CHECK13: cond.end:
	// CHECK13-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]			// CHECK13-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
	// CHECK13-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK13-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK13-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK13-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK13-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK13-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK13: omp.inner.for.cond:			// CHECK13: omp.inner.for.cond:
	// CHECK13-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK13-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !49
	// CHECK13-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK13-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !49
	// CHECK13-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK13-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK13-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK13-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK13: omp.inner.for.body:			// CHECK13: omp.inner.for.body:
	// CHECK13-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK13-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !49
	// CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK13-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK13-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !49
	// CHECK13-NEXT: invoke void @_Z3foov()			// CHECK13-NEXT: invoke void @_Z3foov()
	// CHECK13-NEXT: to label [[INVOKE_CONT:%.]] unwind label [[TERMINATE_LPAD:%.]]			// CHECK13-NEXT: to label [[INVOKE_CONT:%.]] unwind label [[TERMINATE_LPAD:%.]], !llvm.access.group !49
	// CHECK13: invoke.cont:			// CHECK13: invoke.cont:
	// CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK13: omp.body.continue:			// CHECK13: omp.body.continue:
	// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK13: omp.inner.for.inc:			// CHECK13: omp.inner.for.inc:
	// CHECK13-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK13-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !49
	// CHECK13-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK13-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK13-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4			// CHECK13-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !49
	// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP26:![0-9]+]]			// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP50:![0-9]+]]
	// CHECK13: omp.inner.for.end:			// CHECK13: omp.inner.for.end:
	// CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK13: omp.loop.exit:			// CHECK13: omp.loop.exit:
	// CHECK13-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])			// CHECK13-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
	// CHECK13-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK13-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK13-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK13-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK13-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK13-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK13: .omp.final.then:			// CHECK13: .omp.final.then:
	// CHECK13-NEXT: store i32 100, i32* [[I]], align 4			// CHECK13-NEXT: store i32 100, i32* [[I]], align 4
	// CHECK13-NEXT: br label [[DOTOMP_FINAL_DONE]]			// CHECK13-NEXT: br label [[DOTOMP_FINAL_DONE]]
	// CHECK13: .omp.final.done:			// CHECK13: .omp.final.done:
	// CHECK13-NEXT: ret void			// CHECK13-NEXT: ret void
	// CHECK13: terminate.lpad:			// CHECK13: terminate.lpad:
	// CHECK13-NEXT: [[TMP13:%.]] = landingpad { i8, i32 }			// CHECK13-NEXT: [[TMP13:%.]] = landingpad { i8, i32 }
	// CHECK13-NEXT: catch i8* null			// CHECK13-NEXT: catch i8* null
	// CHECK13-NEXT: [[TMP14:%.]] = extractvalue { i8, i32 } [[TMP13]], 0			// CHECK13-NEXT: [[TMP14:%.]] = extractvalue { i8, i32 } [[TMP13]], 0
	// CHECK13-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]]			// CHECK13-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]], !llvm.access.group !49
	// CHECK13-NEXT: unreachable			// CHECK13-NEXT: unreachable
	//			//
	//			//
	// CHECK13-LABEL: define {{[^@]+}}@_ZN1SD2Ev			// CHECK13-LABEL: define {{[^@]+}}@_ZN1SD2Ev
	// CHECK13-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR8]] comdat align 2 {			// CHECK13-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR8]] comdat align 2 {
	// CHECK13-NEXT: entry:			// CHECK13-NEXT: entry:
	// CHECK13-NEXT: [[THIS_ADDR:%.]] = alloca %struct.S, align 8			// CHECK13-NEXT: [[THIS_ADDR:%.]] = alloca %struct.S, align 8
	// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8			// CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
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	// CHECK14-NEXT: br label [[COND_END]]			// CHECK14-NEXT: br label [[COND_END]]
	// CHECK14: cond.end:			// CHECK14: cond.end:
	// CHECK14-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]			// CHECK14-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
	// CHECK14-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK14-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK14-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK14-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK14-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK14-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK14: omp.inner.for.cond:			// CHECK14: omp.inner.for.cond:
	// CHECK14-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK14-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK14-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK14-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !13
	// CHECK14-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK14-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK14-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK14-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK14: omp.inner.for.body:			// CHECK14: omp.inner.for.body:
	// CHECK14-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 2)			// CHECK14-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 2), !llvm.access.group !13
	// CHECK14-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK14-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !13
	// CHECK14-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64			// CHECK14-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
	// CHECK14-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK14-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !13
	// CHECK14-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK14-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK14-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..1 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]])			// CHECK14-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..1 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !13
	// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK14: omp.inner.for.inc:			// CHECK14: omp.inner.for.inc:
	// CHECK14-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK14-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK14-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK14-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !13
	// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]			// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
	// CHECK14-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK14-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]			// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]]
	// CHECK14: omp.inner.for.end:			// CHECK14: omp.inner.for.end:
	// CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK14: omp.loop.exit:			// CHECK14: omp.loop.exit:
	// CHECK14-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])			// CHECK14-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
	// CHECK14-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK14-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK14-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0			// CHECK14-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
	// CHECK14-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK14-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK14: .omp.final.then:			// CHECK14: .omp.final.then:
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	// CHECK14-NEXT: br label [[COND_END]]			// CHECK14-NEXT: br label [[COND_END]]
	// CHECK14: cond.end:			// CHECK14: cond.end:
	// CHECK14-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]			// CHECK14-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
	// CHECK14-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK14-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK14-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK14-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK14-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK14-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK14: omp.inner.for.cond:			// CHECK14: omp.inner.for.cond:
	// CHECK14-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK14-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !17
	// CHECK14-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK14-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !17
	// CHECK14-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK14-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK14-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK14-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK14: omp.inner.for.body:			// CHECK14: omp.inner.for.body:
	// CHECK14-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK14-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !17
	// CHECK14-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK14-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK14-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK14-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !17
	// CHECK14-NEXT: invoke void @_Z3foov()			// CHECK14-NEXT: invoke void @_Z3foov()
	// CHECK14-NEXT: to label [[INVOKE_CONT:%.]] unwind label [[TERMINATE_LPAD:%.]]			// CHECK14-NEXT: to label [[INVOKE_CONT:%.]] unwind label [[TERMINATE_LPAD:%.]], !llvm.access.group !17
	// CHECK14: invoke.cont:			// CHECK14: invoke.cont:
	// CHECK14-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK14-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK14: omp.body.continue:			// CHECK14: omp.body.continue:
	// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK14: omp.inner.for.inc:			// CHECK14: omp.inner.for.inc:
	// CHECK14-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK14-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !17
	// CHECK14-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK14-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK14-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4			// CHECK14-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17
	// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]]			// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]]
	// CHECK14: omp.inner.for.end:			// CHECK14: omp.inner.for.end:
	// CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK14: omp.loop.exit:			// CHECK14: omp.loop.exit:
	// CHECK14-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])			// CHECK14-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
	// CHECK14-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK14-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK14-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK14-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK14-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK14-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK14: .omp.final.then:			// CHECK14: .omp.final.then:
	// CHECK14-NEXT: store i32 100, i32* [[I]], align 4			// CHECK14-NEXT: store i32 100, i32* [[I]], align 4
	// CHECK14-NEXT: br label [[DOTOMP_FINAL_DONE]]			// CHECK14-NEXT: br label [[DOTOMP_FINAL_DONE]]
	// CHECK14: .omp.final.done:			// CHECK14: .omp.final.done:
	// CHECK14-NEXT: ret void			// CHECK14-NEXT: ret void
	// CHECK14: terminate.lpad:			// CHECK14: terminate.lpad:
	// CHECK14-NEXT: [[TMP13:%.]] = landingpad { i8, i32 }			// CHECK14-NEXT: [[TMP13:%.]] = landingpad { i8, i32 }
	// CHECK14-NEXT: catch i8* null			// CHECK14-NEXT: catch i8* null
	// CHECK14-NEXT: [[TMP14:%.]] = extractvalue { i8, i32 } [[TMP13]], 0			// CHECK14-NEXT: [[TMP14:%.]] = extractvalue { i8, i32 } [[TMP13]], 0
	// CHECK14-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10:[0-9]+]]			// CHECK14-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10:[0-9]+]], !llvm.access.group !17
	// CHECK14-NEXT: unreachable			// CHECK14-NEXT: unreachable
	//			//
	//			//
	// CHECK14-LABEL: define {{[^@]+}}@__clang_call_terminate			// CHECK14-LABEL: define {{[^@]+}}@__clang_call_terminate
	// CHECK14-SAME: (i8* [[TMP0:%.*]]) #[[ATTR5:[0-9]+]] comdat {			// CHECK14-SAME: (i8* [[TMP0:%.*]]) #[[ATTR5:[0-9]+]] comdat {
	// CHECK14-NEXT: [[TMP2:%.]] = call i8 @__cxa_begin_catch(i8* [[TMP0]]) #[[ATTR6]]			// CHECK14-NEXT: [[TMP2:%.]] = call i8 @__cxa_begin_catch(i8* [[TMP0]]) #[[ATTR6]]
	// CHECK14-NEXT: call void @_ZSt9terminatev() #[[ATTR10]]			// CHECK14-NEXT: call void @_ZSt9terminatev() #[[ATTR10]]
	// CHECK14-NEXT: unreachable			// CHECK14-NEXT: unreachable
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	// CHECK14-NEXT: br label [[COND_END]]			// CHECK14-NEXT: br label [[COND_END]]
	// CHECK14: cond.end:			// CHECK14: cond.end:
	// CHECK14-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]			// CHECK14-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
	// CHECK14-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK14-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK14-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK14-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK14-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK14-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK14: omp.inner.for.cond:			// CHECK14: omp.inner.for.cond:
	// CHECK14-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK14-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !22
	// CHECK14-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK14-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !22
	// CHECK14-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK14-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK14-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK14-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK14: omp.inner.for.body:			// CHECK14: omp.inner.for.body:
	// CHECK14-NEXT: [[TMP8:%.]] = load i8, i8 [[TMP0]], align 1			// CHECK14-NEXT: [[TMP8:%.]] = load i8, i8 [[TMP0]], align 1, !llvm.access.group !22
	// CHECK14-NEXT: [[TMP9:%.*]] = sext i8 [[TMP8]] to i32			// CHECK14-NEXT: [[TMP9:%.*]] = sext i8 [[TMP8]] to i32
	// CHECK14-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP2]], i32 [[TMP9]])			// CHECK14-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP2]], i32 [[TMP9]]), !llvm.access.group !22
	// CHECK14-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK14-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !22
	// CHECK14-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64			// CHECK14-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
	// CHECK14-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK14-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !22
	// CHECK14-NEXT: [[TMP13:%.*]] = zext i32 [[TMP12]] to i64			// CHECK14-NEXT: [[TMP13:%.*]] = zext i32 [[TMP12]] to i64
	// CHECK14-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..3 to void (i32, i32, ...)*), i64 [[TMP11]], i64 [[TMP13]])			// CHECK14-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..3 to void (i32, i32, ...)*), i64 [[TMP11]], i64 [[TMP13]]), !llvm.access.group !22
	// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK14: omp.inner.for.inc:			// CHECK14: omp.inner.for.inc:
	// CHECK14-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK14-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !22
	// CHECK14-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK14-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !22
	// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP14]], [[TMP15]]			// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP14]], [[TMP15]]
	// CHECK14-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK14-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
	// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]]			// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]]
	// CHECK14: omp.inner.for.end:			// CHECK14: omp.inner.for.end:
	// CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK14: omp.loop.exit:			// CHECK14: omp.loop.exit:
	// CHECK14-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])			// CHECK14-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
	// CHECK14-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK14-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK14-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0			// CHECK14-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0
	// CHECK14-NEXT: br i1 [[TMP17]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK14-NEXT: br i1 [[TMP17]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK14: .omp.final.then:			// CHECK14: .omp.final.then:
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	// CHECK14-NEXT: br label [[COND_END]]			// CHECK14-NEXT: br label [[COND_END]]
	// CHECK14: cond.end:			// CHECK14: cond.end:
	// CHECK14-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]			// CHECK14-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
	// CHECK14-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK14-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK14-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK14-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK14-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK14-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK14: omp.inner.for.cond:			// CHECK14: omp.inner.for.cond:
	// CHECK14-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK14-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !25
	// CHECK14-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK14-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !25
	// CHECK14-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK14-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK14-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK14-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK14: omp.inner.for.body:			// CHECK14: omp.inner.for.body:
	// CHECK14-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK14-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !25
	// CHECK14-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK14-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK14-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK14-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !25
	// CHECK14-NEXT: invoke void @_Z3foov()			// CHECK14-NEXT: invoke void @_Z3foov()
	// CHECK14-NEXT: to label [[INVOKE_CONT:%.]] unwind label [[TERMINATE_LPAD:%.]]			// CHECK14-NEXT: to label [[INVOKE_CONT:%.]] unwind label [[TERMINATE_LPAD:%.]], !llvm.access.group !25
	// CHECK14: invoke.cont:			// CHECK14: invoke.cont:
	// CHECK14-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK14-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK14: omp.body.continue:			// CHECK14: omp.body.continue:
	// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK14: omp.inner.for.inc:			// CHECK14: omp.inner.for.inc:
	// CHECK14-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK14-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !25
	// CHECK14-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK14-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK14-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4			// CHECK14-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25
	// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]]			// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP26:![0-9]+]]
	// CHECK14: omp.inner.for.end:			// CHECK14: omp.inner.for.end:
	// CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK14: omp.loop.exit:			// CHECK14: omp.loop.exit:
	// CHECK14-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])			// CHECK14-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
	// CHECK14-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK14-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK14-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK14-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK14-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK14-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK14: .omp.final.then:			// CHECK14: .omp.final.then:
	// CHECK14-NEXT: store i32 100, i32* [[I]], align 4			// CHECK14-NEXT: store i32 100, i32* [[I]], align 4
	// CHECK14-NEXT: br label [[DOTOMP_FINAL_DONE]]			// CHECK14-NEXT: br label [[DOTOMP_FINAL_DONE]]
	// CHECK14: .omp.final.done:			// CHECK14: .omp.final.done:
	// CHECK14-NEXT: ret void			// CHECK14-NEXT: ret void
	// CHECK14: terminate.lpad:			// CHECK14: terminate.lpad:
	// CHECK14-NEXT: [[TMP13:%.]] = landingpad { i8, i32 }			// CHECK14-NEXT: [[TMP13:%.]] = landingpad { i8, i32 }
	// CHECK14-NEXT: catch i8* null			// CHECK14-NEXT: catch i8* null
	// CHECK14-NEXT: [[TMP14:%.]] = extractvalue { i8, i32 } [[TMP13]], 0			// CHECK14-NEXT: [[TMP14:%.]] = extractvalue { i8, i32 } [[TMP13]], 0
	// CHECK14-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]]			// CHECK14-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]], !llvm.access.group !25
	// CHECK14-NEXT: unreachable			// CHECK14-NEXT: unreachable
	//			//
	//			//
	// CHECK14-LABEL: define {{[^@]+}}@_Z5tmainIcLi5EEiv			// CHECK14-LABEL: define {{[^@]+}}@_Z5tmainIcLi5EEiv
	// CHECK14-SAME: () #[[ATTR7:[0-9]+]] comdat {			// CHECK14-SAME: () #[[ATTR7:[0-9]+]] comdat {
	// CHECK14-NEXT: entry:			// CHECK14-NEXT: entry:
	// CHECK14-NEXT: [[TMP:%.*]] = alloca i32, align 4			// CHECK14-NEXT: [[TMP:%.*]] = alloca i32, align 4
	// CHECK14-NEXT: [[_TMP1:%.*]] = alloca i32, align 4			// CHECK14-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
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	// CHECK14-NEXT: br label [[COND_END]]			// CHECK14-NEXT: br label [[COND_END]]
	// CHECK14: cond.end:			// CHECK14: cond.end:
	// CHECK14-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]			// CHECK14-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
	// CHECK14-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK14-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK14-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK14-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK14-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK14-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK14: omp.inner.for.cond:			// CHECK14: omp.inner.for.cond:
	// CHECK14-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK14-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !28
	// CHECK14-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK14-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !28
	// CHECK14-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK14-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK14-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK14-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK14: omp.inner.for.body:			// CHECK14: omp.inner.for.body:
	// CHECK14-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 5)			// CHECK14-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 5), !llvm.access.group !28
	// CHECK14-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK14-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !28
	// CHECK14-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64			// CHECK14-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
	// CHECK14-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK14-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !28
	// CHECK14-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK14-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK14-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..5 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]])			// CHECK14-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..5 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !28
	// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK14: omp.inner.for.inc:			// CHECK14: omp.inner.for.inc:
	// CHECK14-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK14-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !28
	// CHECK14-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK14-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !28
	// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]			// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
	// CHECK14-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK14-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28
	// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]			// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP29:![0-9]+]]
	// CHECK14: omp.inner.for.end:			// CHECK14: omp.inner.for.end:
	// CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK14: omp.loop.exit:			// CHECK14: omp.loop.exit:
	// CHECK14-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])			// CHECK14-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
	// CHECK14-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK14-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK14-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0			// CHECK14-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
	// CHECK14-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK14-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK14: .omp.final.then:			// CHECK14: .omp.final.then:
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	// CHECK14-NEXT: br label [[COND_END]]			// CHECK14-NEXT: br label [[COND_END]]
	// CHECK14: cond.end:			// CHECK14: cond.end:
	// CHECK14-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]			// CHECK14-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
	// CHECK14-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK14-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK14-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK14-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK14-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK14-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK14: omp.inner.for.cond:			// CHECK14: omp.inner.for.cond:
	// CHECK14-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK14-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !31
	// CHECK14-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK14-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !31
	// CHECK14-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK14-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK14-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK14-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK14: omp.inner.for.body:			// CHECK14: omp.inner.for.body:
	// CHECK14-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK14-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !31
	// CHECK14-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK14-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK14-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK14-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !31
	// CHECK14-NEXT: invoke void @_Z3foov()			// CHECK14-NEXT: invoke void @_Z3foov()
	// CHECK14-NEXT: to label [[INVOKE_CONT:%.]] unwind label [[TERMINATE_LPAD:%.]]			// CHECK14-NEXT: to label [[INVOKE_CONT:%.]] unwind label [[TERMINATE_LPAD:%.]], !llvm.access.group !31
	// CHECK14: invoke.cont:			// CHECK14: invoke.cont:
	// CHECK14-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK14-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK14: omp.body.continue:			// CHECK14: omp.body.continue:
	// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK14: omp.inner.for.inc:			// CHECK14: omp.inner.for.inc:
	// CHECK14-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK14-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !31
	// CHECK14-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK14-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK14-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4			// CHECK14-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !31
	// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]]			// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP32:![0-9]+]]
	// CHECK14: omp.inner.for.end:			// CHECK14: omp.inner.for.end:
	// CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK14: omp.loop.exit:			// CHECK14: omp.loop.exit:
	// CHECK14-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])			// CHECK14-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
	// CHECK14-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK14-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK14-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK14-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK14-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK14-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK14: .omp.final.then:			// CHECK14: .omp.final.then:
	// CHECK14-NEXT: store i32 100, i32* [[I]], align 4			// CHECK14-NEXT: store i32 100, i32* [[I]], align 4
	// CHECK14-NEXT: br label [[DOTOMP_FINAL_DONE]]			// CHECK14-NEXT: br label [[DOTOMP_FINAL_DONE]]
	// CHECK14: .omp.final.done:			// CHECK14: .omp.final.done:
	// CHECK14-NEXT: ret void			// CHECK14-NEXT: ret void
	// CHECK14: terminate.lpad:			// CHECK14: terminate.lpad:
	// CHECK14-NEXT: [[TMP13:%.]] = landingpad { i8, i32 }			// CHECK14-NEXT: [[TMP13:%.]] = landingpad { i8, i32 }
	// CHECK14-NEXT: catch i8* null			// CHECK14-NEXT: catch i8* null
	// CHECK14-NEXT: [[TMP14:%.]] = extractvalue { i8, i32 } [[TMP13]], 0			// CHECK14-NEXT: [[TMP14:%.]] = extractvalue { i8, i32 } [[TMP13]], 0
	// CHECK14-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]]			// CHECK14-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]], !llvm.access.group !31
	// CHECK14-NEXT: unreachable			// CHECK14-NEXT: unreachable
	//			//
	//			//
	// CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l57			// CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l57
	// CHECK14-SAME: () #[[ATTR3]] {			// CHECK14-SAME: () #[[ATTR3]] {
	// CHECK14-NEXT: entry:			// CHECK14-NEXT: entry:
	// CHECK14-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32, i32, ...)* bitcast (void (i32, i32)* @.omp_outlined..6 to void (i32, i32, ...)*))			// CHECK14-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32, i32, ...)* bitcast (void (i32, i32)* @.omp_outlined..6 to void (i32, i32, ...)*))
	// CHECK14-NEXT: ret void			// CHECK14-NEXT: ret void
	Show All 30 Lines
	// CHECK14-NEXT: br label [[COND_END]]			// CHECK14-NEXT: br label [[COND_END]]
	// CHECK14: cond.end:			// CHECK14: cond.end:
	// CHECK14-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]			// CHECK14-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
	// CHECK14-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK14-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK14-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK14-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK14-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK14-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK14: omp.inner.for.cond:			// CHECK14: omp.inner.for.cond:
	// CHECK14-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK14-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !34
	// CHECK14-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK14-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !34
	// CHECK14-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK14-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK14-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK14-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK14: omp.inner.for.body:			// CHECK14: omp.inner.for.body:
	// CHECK14-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 23)			// CHECK14-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 23), !llvm.access.group !34
	// CHECK14-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK14-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !34
	// CHECK14-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64			// CHECK14-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
	// CHECK14-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK14-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !34
	// CHECK14-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK14-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK14-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..7 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]])			// CHECK14-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..7 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !34
	// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK14: omp.inner.for.inc:			// CHECK14: omp.inner.for.inc:
	// CHECK14-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK14-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !34
	// CHECK14-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK14-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !34
	// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]			// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
	// CHECK14-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK14-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !34
	// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]]			// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP35:![0-9]+]]
	// CHECK14: omp.inner.for.end:			// CHECK14: omp.inner.for.end:
	// CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK14: omp.loop.exit:			// CHECK14: omp.loop.exit:
	// CHECK14-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])			// CHECK14-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
	// CHECK14-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK14-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK14-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0			// CHECK14-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
	// CHECK14-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK14-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK14: .omp.final.then:			// CHECK14: .omp.final.then:
	▲ Show 20 Lines • Show All 44 Lines • ▼ Show 20 Lines
	// CHECK14-NEXT: br label [[COND_END]]			// CHECK14-NEXT: br label [[COND_END]]
	// CHECK14: cond.end:			// CHECK14: cond.end:
	// CHECK14-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]			// CHECK14-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
	// CHECK14-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK14-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK14-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK14-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK14-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK14-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK14: omp.inner.for.cond:			// CHECK14: omp.inner.for.cond:
	// CHECK14-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK14-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !37
	// CHECK14-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK14-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !37
	// CHECK14-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK14-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK14-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK14-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK14: omp.inner.for.body:			// CHECK14: omp.inner.for.body:
	// CHECK14-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK14-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !37
	// CHECK14-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK14-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK14-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK14-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !37
	// CHECK14-NEXT: invoke void @_Z3foov()			// CHECK14-NEXT: invoke void @_Z3foov()
	// CHECK14-NEXT: to label [[INVOKE_CONT:%.]] unwind label [[TERMINATE_LPAD:%.]]			// CHECK14-NEXT: to label [[INVOKE_CONT:%.]] unwind label [[TERMINATE_LPAD:%.]], !llvm.access.group !37
	// CHECK14: invoke.cont:			// CHECK14: invoke.cont:
	// CHECK14-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK14-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK14: omp.body.continue:			// CHECK14: omp.body.continue:
	// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK14: omp.inner.for.inc:			// CHECK14: omp.inner.for.inc:
	// CHECK14-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK14-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !37
	// CHECK14-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK14-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK14-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4			// CHECK14-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !37
	// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]]			// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP38:![0-9]+]]
	// CHECK14: omp.inner.for.end:			// CHECK14: omp.inner.for.end:
	// CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK14: omp.loop.exit:			// CHECK14: omp.loop.exit:
	// CHECK14-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])			// CHECK14-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
	// CHECK14-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK14-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK14-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK14-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK14-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK14-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK14: .omp.final.then:			// CHECK14: .omp.final.then:
	// CHECK14-NEXT: store i32 100, i32* [[I]], align 4			// CHECK14-NEXT: store i32 100, i32* [[I]], align 4
	// CHECK14-NEXT: br label [[DOTOMP_FINAL_DONE]]			// CHECK14-NEXT: br label [[DOTOMP_FINAL_DONE]]
	// CHECK14: .omp.final.done:			// CHECK14: .omp.final.done:
	// CHECK14-NEXT: ret void			// CHECK14-NEXT: ret void
	// CHECK14: terminate.lpad:			// CHECK14: terminate.lpad:
	// CHECK14-NEXT: [[TMP13:%.]] = landingpad { i8, i32 }			// CHECK14-NEXT: [[TMP13:%.]] = landingpad { i8, i32 }
	// CHECK14-NEXT: catch i8* null			// CHECK14-NEXT: catch i8* null
	// CHECK14-NEXT: [[TMP14:%.]] = extractvalue { i8, i32 } [[TMP13]], 0			// CHECK14-NEXT: [[TMP14:%.]] = extractvalue { i8, i32 } [[TMP13]], 0
	// CHECK14-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]]			// CHECK14-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]], !llvm.access.group !37
	// CHECK14-NEXT: unreachable			// CHECK14-NEXT: unreachable
	//			//
	//			//
	// CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l52			// CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l52
	// CHECK14-SAME: () #[[ATTR3]] {			// CHECK14-SAME: () #[[ATTR3]] {
	// CHECK14-NEXT: entry:			// CHECK14-NEXT: entry:
	// CHECK14-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32, i32, ...)* bitcast (void (i32, i32)* @.omp_outlined..8 to void (i32, i32, ...)*))			// CHECK14-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32, i32, ...)* bitcast (void (i32, i32)* @.omp_outlined..8 to void (i32, i32, ...)*))
	// CHECK14-NEXT: ret void			// CHECK14-NEXT: ret void
	Show All 30 Lines
	// CHECK14-NEXT: br label [[COND_END]]			// CHECK14-NEXT: br label [[COND_END]]
	// CHECK14: cond.end:			// CHECK14: cond.end:
	// CHECK14-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]			// CHECK14-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
	// CHECK14-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK14-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK14-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK14-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK14-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK14-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK14: omp.inner.for.cond:			// CHECK14: omp.inner.for.cond:
	// CHECK14-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK14-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !40
	// CHECK14-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK14-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !40
	// CHECK14-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK14-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK14-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK14-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK14: omp.inner.for.body:			// CHECK14: omp.inner.for.body:
	// CHECK14-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 1)			// CHECK14-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 1), !llvm.access.group !40
	// CHECK14-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK14-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !40
	// CHECK14-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64			// CHECK14-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
	// CHECK14-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK14-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !40
	// CHECK14-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK14-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK14-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..9 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]])			// CHECK14-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..9 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !40
	// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK14: omp.inner.for.inc:			// CHECK14: omp.inner.for.inc:
	// CHECK14-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK14-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !40
	// CHECK14-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK14-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !40
	// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]			// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
	// CHECK14-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK14-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !40
	// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]]			// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP41:![0-9]+]]
	// CHECK14: omp.inner.for.end:			// CHECK14: omp.inner.for.end:
	// CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK14: omp.loop.exit:			// CHECK14: omp.loop.exit:
	// CHECK14-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])			// CHECK14-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
	// CHECK14-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK14-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK14-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0			// CHECK14-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
	// CHECK14-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK14-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK14: .omp.final.then:			// CHECK14: .omp.final.then:
	▲ Show 20 Lines • Show All 44 Lines • ▼ Show 20 Lines
	// CHECK14-NEXT: br label [[COND_END]]			// CHECK14-NEXT: br label [[COND_END]]
	// CHECK14: cond.end:			// CHECK14: cond.end:
	// CHECK14-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]			// CHECK14-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
	// CHECK14-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK14-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK14-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK14-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK14-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK14-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK14: omp.inner.for.cond:			// CHECK14: omp.inner.for.cond:
	// CHECK14-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK14-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !43
	// CHECK14-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK14-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !43
	// CHECK14-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK14-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK14-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK14-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK14: omp.inner.for.body:			// CHECK14: omp.inner.for.body:
	// CHECK14-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK14-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !43
	// CHECK14-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK14-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK14-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK14-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !43
	// CHECK14-NEXT: invoke void @_Z3foov()			// CHECK14-NEXT: invoke void @_Z3foov()
	// CHECK14-NEXT: to label [[INVOKE_CONT:%.]] unwind label [[TERMINATE_LPAD:%.]]			// CHECK14-NEXT: to label [[INVOKE_CONT:%.]] unwind label [[TERMINATE_LPAD:%.]], !llvm.access.group !43
	// CHECK14: invoke.cont:			// CHECK14: invoke.cont:
	// CHECK14-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK14-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK14: omp.body.continue:			// CHECK14: omp.body.continue:
	// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK14: omp.inner.for.inc:			// CHECK14: omp.inner.for.inc:
	// CHECK14-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK14-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !43
	// CHECK14-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK14-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK14-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4			// CHECK14-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !43
	// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP24:![0-9]+]]			// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP44:![0-9]+]]
	// CHECK14: omp.inner.for.end:			// CHECK14: omp.inner.for.end:
	// CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK14: omp.loop.exit:			// CHECK14: omp.loop.exit:
	// CHECK14-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])			// CHECK14-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
	// CHECK14-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK14-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK14-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK14-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK14-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK14-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK14: .omp.final.then:			// CHECK14: .omp.final.then:
	// CHECK14-NEXT: store i32 100, i32* [[I]], align 4			// CHECK14-NEXT: store i32 100, i32* [[I]], align 4
	// CHECK14-NEXT: br label [[DOTOMP_FINAL_DONE]]			// CHECK14-NEXT: br label [[DOTOMP_FINAL_DONE]]
	// CHECK14: .omp.final.done:			// CHECK14: .omp.final.done:
	// CHECK14-NEXT: ret void			// CHECK14-NEXT: ret void
	// CHECK14: terminate.lpad:			// CHECK14: terminate.lpad:
	// CHECK14-NEXT: [[TMP13:%.]] = landingpad { i8, i32 }			// CHECK14-NEXT: [[TMP13:%.]] = landingpad { i8, i32 }
	// CHECK14-NEXT: catch i8* null			// CHECK14-NEXT: catch i8* null
	// CHECK14-NEXT: [[TMP14:%.]] = extractvalue { i8, i32 } [[TMP13]], 0			// CHECK14-NEXT: [[TMP14:%.]] = extractvalue { i8, i32 } [[TMP13]], 0
	// CHECK14-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]]			// CHECK14-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]], !llvm.access.group !43
	// CHECK14-NEXT: unreachable			// CHECK14-NEXT: unreachable
	//			//
	//			//
	// CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l57			// CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l57
	// CHECK14-SAME: () #[[ATTR3]] {			// CHECK14-SAME: () #[[ATTR3]] {
	// CHECK14-NEXT: entry:			// CHECK14-NEXT: entry:
	// CHECK14-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32, i32, ...)* bitcast (void (i32, i32)* @.omp_outlined..10 to void (i32, i32, ...)*))			// CHECK14-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32, i32, ...)* bitcast (void (i32, i32)* @.omp_outlined..10 to void (i32, i32, ...)*))
	// CHECK14-NEXT: ret void			// CHECK14-NEXT: ret void
	Show All 33 Lines
	// CHECK14-NEXT: br label [[COND_END]]			// CHECK14-NEXT: br label [[COND_END]]
	// CHECK14: cond.end:			// CHECK14: cond.end:
	// CHECK14-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]			// CHECK14-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
	// CHECK14-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK14-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK14-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK14-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK14-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK14-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK14: omp.inner.for.cond:			// CHECK14: omp.inner.for.cond:
	// CHECK14-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK14-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !46
	// CHECK14-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK14-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !46
	// CHECK14-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK14-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK14-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK14-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK14: omp.inner.for.body:			// CHECK14: omp.inner.for.body:
	// CHECK14-NEXT: invoke void @_ZN1SC1El(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]], i64 23)			// CHECK14-NEXT: invoke void @_ZN1SC1El(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]], i64 23)
	// CHECK14-NEXT: to label [[INVOKE_CONT:%.]] unwind label [[TERMINATE_LPAD:%.]]			// CHECK14-NEXT: to label [[INVOKE_CONT:%.]] unwind label [[TERMINATE_LPAD:%.]], !llvm.access.group !46
	// CHECK14: invoke.cont:			// CHECK14: invoke.cont:
	// CHECK14-NEXT: [[CALL:%.]] = invoke i8 @_ZN1ScvcEv(%struct.S nonnull align 8 dereferenceable(24) [[REF_TMP]])			// CHECK14-NEXT: [[CALL:%.]] = invoke i8 @_ZN1ScvcEv(%struct.S nonnull align 8 dereferenceable(24) [[REF_TMP]])
	// CHECK14-NEXT: to label [[INVOKE_CONT2:%.]] unwind label [[LPAD:%.]]			// CHECK14-NEXT: to label [[INVOKE_CONT2:%.]] unwind label [[LPAD:%.]], !llvm.access.group !46
	// CHECK14: invoke.cont2:			// CHECK14: invoke.cont2:
	// CHECK14-NEXT: [[TMP7:%.*]] = sext i8 [[CALL]] to i32			// CHECK14-NEXT: [[TMP7:%.*]] = sext i8 [[CALL]] to i32
	// CHECK14-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 [[TMP7]])			// CHECK14-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 [[TMP7]]), !llvm.access.group !46
	// CHECK14-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR6]]			// CHECK14-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR6]], !llvm.access.group !46
	// CHECK14-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK14-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !46
	// CHECK14-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64			// CHECK14-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
	// CHECK14-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK14-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !46
	// CHECK14-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64			// CHECK14-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
	// CHECK14-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..11 to void (i32, i32, ...)*), i64 [[TMP9]], i64 [[TMP11]])			// CHECK14-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..11 to void (i32, i32, ...)*), i64 [[TMP9]], i64 [[TMP11]]), !llvm.access.group !46
	// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK14: omp.inner.for.inc:			// CHECK14: omp.inner.for.inc:
	// CHECK14-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK14-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !46
	// CHECK14-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK14-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !46
	// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]			// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]
	// CHECK14-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK14-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !46
	// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]]			// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP47:![0-9]+]]
	// CHECK14: lpad:			// CHECK14: lpad:
	// CHECK14-NEXT: [[TMP14:%.]] = landingpad { i8, i32 }			// CHECK14-NEXT: [[TMP14:%.]] = landingpad { i8, i32 }
	// CHECK14-NEXT: catch i8* null			// CHECK14-NEXT: catch i8* null
	// CHECK14-NEXT: [[TMP15:%.]] = extractvalue { i8, i32 } [[TMP14]], 0			// CHECK14-NEXT: [[TMP15:%.]] = extractvalue { i8, i32 } [[TMP14]], 0
	// CHECK14-NEXT: store i8* [[TMP15]], i8** [[EXN_SLOT]], align 8			// CHECK14-NEXT: store i8* [[TMP15]], i8** [[EXN_SLOT]], align 8, !llvm.access.group !46
	// CHECK14-NEXT: [[TMP16:%.]] = extractvalue { i8, i32 } [[TMP14]], 1			// CHECK14-NEXT: [[TMP16:%.]] = extractvalue { i8, i32 } [[TMP14]], 1
	// CHECK14-NEXT: store i32 [[TMP16]], i32* [[EHSELECTOR_SLOT]], align 4			// CHECK14-NEXT: store i32 [[TMP16]], i32* [[EHSELECTOR_SLOT]], align 4, !llvm.access.group !46
	// CHECK14-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR6]]			// CHECK14-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR6]], !llvm.access.group !46
	// CHECK14-NEXT: br label [[TERMINATE_HANDLER:%.*]]			// CHECK14-NEXT: br label [[TERMINATE_HANDLER:%.*]]
	// CHECK14: omp.inner.for.end:			// CHECK14: omp.inner.for.end:
	// CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK14: omp.loop.exit:			// CHECK14: omp.loop.exit:
	// CHECK14-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])			// CHECK14-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
	// CHECK14-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK14-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK14-NEXT: [[TMP18:%.*]] = icmp ne i32 [[TMP17]], 0			// CHECK14-NEXT: [[TMP18:%.*]] = icmp ne i32 [[TMP17]], 0
	// CHECK14-NEXT: br i1 [[TMP18]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK14-NEXT: br i1 [[TMP18]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK14: .omp.final.then:			// CHECK14: .omp.final.then:
	// CHECK14-NEXT: store i32 100, i32* [[I]], align 4			// CHECK14-NEXT: store i32 100, i32* [[I]], align 4
	// CHECK14-NEXT: br label [[DOTOMP_FINAL_DONE]]			// CHECK14-NEXT: br label [[DOTOMP_FINAL_DONE]]
	// CHECK14: .omp.final.done:			// CHECK14: .omp.final.done:
	// CHECK14-NEXT: ret void			// CHECK14-NEXT: ret void
	// CHECK14: terminate.lpad:			// CHECK14: terminate.lpad:
	// CHECK14-NEXT: [[TMP19:%.]] = landingpad { i8, i32 }			// CHECK14-NEXT: [[TMP19:%.]] = landingpad { i8, i32 }
	// CHECK14-NEXT: catch i8* null			// CHECK14-NEXT: catch i8* null
	// CHECK14-NEXT: [[TMP20:%.]] = extractvalue { i8, i32 } [[TMP19]], 0			// CHECK14-NEXT: [[TMP20:%.]] = extractvalue { i8, i32 } [[TMP19]], 0
	// CHECK14-NEXT: call void @__clang_call_terminate(i8* [[TMP20]]) #[[ATTR10]]			// CHECK14-NEXT: call void @__clang_call_terminate(i8* [[TMP20]]) #[[ATTR10]], !llvm.access.group !46
	// CHECK14-NEXT: unreachable			// CHECK14-NEXT: unreachable
	// CHECK14: terminate.handler:			// CHECK14: terminate.handler:
	// CHECK14-NEXT: [[EXN:%.]] = load i8, i8** [[EXN_SLOT]], align 8			// CHECK14-NEXT: [[EXN:%.]] = load i8, i8** [[EXN_SLOT]], align 8, !llvm.access.group !46
	// CHECK14-NEXT: call void @__clang_call_terminate(i8* [[EXN]]) #[[ATTR10]]			// CHECK14-NEXT: call void @__clang_call_terminate(i8* [[EXN]]) #[[ATTR10]], !llvm.access.group !46
	// CHECK14-NEXT: unreachable			// CHECK14-NEXT: unreachable
	//			//
	//			//
	// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..11			// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..11
	// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i64 [[DOTPREVIOUS_LB_:%.]], i64 [[DOTPREVIOUS_UB_:%.]]) #[[ATTR3]] personality i8 bitcast (i32 (...)* @__gxx_personality_v0 to i8*) {			// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i64 [[DOTPREVIOUS_LB_:%.]], i64 [[DOTPREVIOUS_UB_:%.]]) #[[ATTR3]] personality i8 bitcast (i32 (...)* @__gxx_personality_v0 to i8*) {
	// CHECK14-NEXT: entry:			// CHECK14-NEXT: entry:
	// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8			// CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8
	// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8			// CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8
	Show All 33 Lines
	// CHECK14-NEXT: br label [[COND_END]]			// CHECK14-NEXT: br label [[COND_END]]
	// CHECK14: cond.end:			// CHECK14: cond.end:
	// CHECK14-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]			// CHECK14-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
	// CHECK14-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK14-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK14-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK14-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK14-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK14-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK14: omp.inner.for.cond:			// CHECK14: omp.inner.for.cond:
	// CHECK14-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK14-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !49
	// CHECK14-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK14-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !49
	// CHECK14-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK14-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK14-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK14-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK14: omp.inner.for.body:			// CHECK14: omp.inner.for.body:
	// CHECK14-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK14-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !49
	// CHECK14-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK14-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK14-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK14-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !49
	// CHECK14-NEXT: invoke void @_Z3foov()			// CHECK14-NEXT: invoke void @_Z3foov()
	// CHECK14-NEXT: to label [[INVOKE_CONT:%.]] unwind label [[TERMINATE_LPAD:%.]]			// CHECK14-NEXT: to label [[INVOKE_CONT:%.]] unwind label [[TERMINATE_LPAD:%.]], !llvm.access.group !49
	// CHECK14: invoke.cont:			// CHECK14: invoke.cont:
	// CHECK14-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK14-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK14: omp.body.continue:			// CHECK14: omp.body.continue:
	// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK14: omp.inner.for.inc:			// CHECK14: omp.inner.for.inc:
	// CHECK14-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK14-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !49
	// CHECK14-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK14-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK14-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4			// CHECK14-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !49
	// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP26:![0-9]+]]			// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP50:![0-9]+]]
	// CHECK14: omp.inner.for.end:			// CHECK14: omp.inner.for.end:
	// CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK14: omp.loop.exit:			// CHECK14: omp.loop.exit:
	// CHECK14-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])			// CHECK14-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
	// CHECK14-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK14-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK14-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK14-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK14-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK14-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK14: .omp.final.then:			// CHECK14: .omp.final.then:
	// CHECK14-NEXT: store i32 100, i32* [[I]], align 4			// CHECK14-NEXT: store i32 100, i32* [[I]], align 4
	// CHECK14-NEXT: br label [[DOTOMP_FINAL_DONE]]			// CHECK14-NEXT: br label [[DOTOMP_FINAL_DONE]]
	// CHECK14: .omp.final.done:			// CHECK14: .omp.final.done:
	// CHECK14-NEXT: ret void			// CHECK14-NEXT: ret void
	// CHECK14: terminate.lpad:			// CHECK14: terminate.lpad:
	// CHECK14-NEXT: [[TMP13:%.]] = landingpad { i8, i32 }			// CHECK14-NEXT: [[TMP13:%.]] = landingpad { i8, i32 }
	// CHECK14-NEXT: catch i8* null			// CHECK14-NEXT: catch i8* null
	// CHECK14-NEXT: [[TMP14:%.]] = extractvalue { i8, i32 } [[TMP13]], 0			// CHECK14-NEXT: [[TMP14:%.]] = extractvalue { i8, i32 } [[TMP13]], 0
	// CHECK14-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]]			// CHECK14-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]], !llvm.access.group !49
	// CHECK14-NEXT: unreachable			// CHECK14-NEXT: unreachable
	//			//
	//			//
	// CHECK14-LABEL: define {{[^@]+}}@_ZN1SD2Ev			// CHECK14-LABEL: define {{[^@]+}}@_ZN1SD2Ev
	// CHECK14-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR8]] comdat align 2 {			// CHECK14-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR8]] comdat align 2 {
	// CHECK14-NEXT: entry:			// CHECK14-NEXT: entry:
	// CHECK14-NEXT: [[THIS_ADDR:%.]] = alloca %struct.S, align 8			// CHECK14-NEXT: [[THIS_ADDR:%.]] = alloca %struct.S, align 8
	// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8			// CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
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clang/test/OpenMP/distribute_parallel_for_simd_private_codegen.cpp

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	Show First 20 Lines • Show All 193 Lines • ▼ Show 20 Lines
	// CHECK1-NEXT: br label [[COND_END]]			// CHECK1-NEXT: br label [[COND_END]]
	// CHECK1: cond.end:			// CHECK1: cond.end:
	// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]			// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
	// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK1-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK1-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK1: omp.inner.for.cond:			// CHECK1: omp.inner.for.cond:
	// CHECK1-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !4
	// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !4
	// CHECK1-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK1-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK1-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK1-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK1: omp.inner.for.body:			// CHECK1: omp.inner.for.body:
	// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !4
	// CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64			// CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
	// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !4
	// CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK1-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..1 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]])			// CHECK1-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..1 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !4
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK1: omp.inner.for.inc:			// CHECK1: omp.inner.for.inc:
	// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !4
	// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !4
	// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]			// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
	// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]
	// CHECK1: omp.inner.for.end:			// CHECK1: omp.inner.for.end:
	// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK1: omp.loop.exit:			// CHECK1: omp.loop.exit:
	// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])			// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
	// CHECK1-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK1-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK1-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0			// CHECK1-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
	// CHECK1-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK1-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK1: .omp.final.then:			// CHECK1: .omp.final.then:
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	// CHECK1-NEXT: br label [[COND_END]]			// CHECK1-NEXT: br label [[COND_END]]
	// CHECK1: cond.end:			// CHECK1: cond.end:
	// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]			// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
	// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK1-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK1: omp.inner.for.cond:			// CHECK1: omp.inner.for.cond:
	// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !8
	// CHECK1-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK1-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !8
	// CHECK1-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK1-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK1-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK1-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK1: omp.inner.for.body:			// CHECK1: omp.inner.for.body:
	// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !8
	// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !8
	// CHECK1-NEXT: store double 1.000000e+00, double* [[G]], align 8			// CHECK1-NEXT: store double 1.000000e+00, double* [[G]], align 8, !llvm.access.group !8
	// CHECK1-NEXT: [[TMP10:%.]] = load double, double** [[_TMP3]], align 8			// CHECK1-NEXT: [[TMP10:%.]] = load double, double** [[_TMP3]], align 8, !llvm.access.group !8
	// CHECK1-NEXT: store volatile double 1.000000e+00, double* [[TMP10]], align 8			// CHECK1-NEXT: store volatile double 1.000000e+00, double* [[TMP10]], align 8, !llvm.access.group !8
	// CHECK1-NEXT: store i32 3, i32* [[SVAR]], align 4			// CHECK1-NEXT: store i32 3, i32* [[SVAR]], align 4, !llvm.access.group !8
	// CHECK1-NEXT: store float 4.000000e+00, float* [[SFVAR]], align 4			// CHECK1-NEXT: store float 4.000000e+00, float* [[SFVAR]], align 4, !llvm.access.group !8
	// CHECK1-NEXT: [[TMP11:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 0			// CHECK1-NEXT: [[TMP11:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 0
	// CHECK1-NEXT: store double* [[G]], double** [[TMP11]], align 8			// CHECK1-NEXT: store double* [[G]], double** [[TMP11]], align 8, !llvm.access.group !8
	// CHECK1-NEXT: [[TMP12:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 1			// CHECK1-NEXT: [[TMP12:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 1
	// CHECK1-NEXT: [[TMP13:%.]] = load double, double** [[_TMP3]], align 8			// CHECK1-NEXT: [[TMP13:%.]] = load double, double** [[_TMP3]], align 8, !llvm.access.group !8
	// CHECK1-NEXT: store double* [[TMP13]], double** [[TMP12]], align 8			// CHECK1-NEXT: store double* [[TMP13]], double** [[TMP12]], align 8, !llvm.access.group !8
	// CHECK1-NEXT: [[TMP14:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 2			// CHECK1-NEXT: [[TMP14:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 2
	// CHECK1-NEXT: store i32* [[SVAR]], i32** [[TMP14]], align 8			// CHECK1-NEXT: store i32* [[SVAR]], i32** [[TMP14]], align 8, !llvm.access.group !8
	// CHECK1-NEXT: [[TMP15:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 3			// CHECK1-NEXT: [[TMP15:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 3
	// CHECK1-NEXT: store float* [[SFVAR]], float** [[TMP15]], align 8			// CHECK1-NEXT: store float* [[SFVAR]], float** [[TMP15]], align 8, !llvm.access.group !8
	// CHECK1-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(32) [[REF_TMP]])			// CHECK1-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(32) [[REF_TMP]]), !llvm.access.group !8
	// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK1: omp.body.continue:			// CHECK1: omp.body.continue:
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK1: omp.inner.for.inc:			// CHECK1: omp.inner.for.inc:
	// CHECK1-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !8
	// CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP16]], 1			// CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP16]], 1
	// CHECK1-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]
	// CHECK1: omp.inner.for.end:			// CHECK1: omp.inner.for.end:
	// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK1: omp.loop.exit:			// CHECK1: omp.loop.exit:
	// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])			// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
	// CHECK1-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK1-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK1-NEXT: [[TMP18:%.*]] = icmp ne i32 [[TMP17]], 0			// CHECK1-NEXT: [[TMP18:%.*]] = icmp ne i32 [[TMP17]], 0
	// CHECK1-NEXT: br i1 [[TMP18]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK1-NEXT: br i1 [[TMP18]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK1: .omp.final.then:			// CHECK1: .omp.final.then:
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	// CHECK2-NEXT: br label [[COND_END]]			// CHECK2-NEXT: br label [[COND_END]]
	// CHECK2: cond.end:			// CHECK2: cond.end:
	// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]			// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
	// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK2-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK2-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK2-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK2: omp.inner.for.cond:			// CHECK2: omp.inner.for.cond:
	// CHECK2-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !4
	// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !4
	// CHECK2-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK2-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK2-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK2-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK2: omp.inner.for.body:			// CHECK2: omp.inner.for.body:
	// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !4
	// CHECK2-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64			// CHECK2-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
	// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !4
	// CHECK2-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK2-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK2-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..1 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]])			// CHECK2-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..1 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !4
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK2: omp.inner.for.inc:			// CHECK2: omp.inner.for.inc:
	// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !4
	// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !4
	// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]			// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
	// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]
	// CHECK2: omp.inner.for.end:			// CHECK2: omp.inner.for.end:
	// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK2: omp.loop.exit:			// CHECK2: omp.loop.exit:
	// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])			// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
	// CHECK2-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK2-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK2-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0			// CHECK2-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
	// CHECK2-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK2-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK2: .omp.final.then:			// CHECK2: .omp.final.then:
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	// CHECK2-NEXT: br label [[COND_END]]			// CHECK2-NEXT: br label [[COND_END]]
	// CHECK2: cond.end:			// CHECK2: cond.end:
	// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]			// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
	// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK2-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK2: omp.inner.for.cond:			// CHECK2: omp.inner.for.cond:
	// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !8
	// CHECK2-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK2-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !8
	// CHECK2-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK2-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK2-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK2-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK2: omp.inner.for.body:			// CHECK2: omp.inner.for.body:
	// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !8
	// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !8
	// CHECK2-NEXT: store double 1.000000e+00, double* [[G]], align 8			// CHECK2-NEXT: store double 1.000000e+00, double* [[G]], align 8, !llvm.access.group !8
	// CHECK2-NEXT: [[TMP10:%.]] = load double, double** [[_TMP3]], align 8			// CHECK2-NEXT: [[TMP10:%.]] = load double, double** [[_TMP3]], align 8, !llvm.access.group !8
	// CHECK2-NEXT: store volatile double 1.000000e+00, double* [[TMP10]], align 8			// CHECK2-NEXT: store volatile double 1.000000e+00, double* [[TMP10]], align 8, !llvm.access.group !8
	// CHECK2-NEXT: store i32 3, i32* [[SVAR]], align 4			// CHECK2-NEXT: store i32 3, i32* [[SVAR]], align 4, !llvm.access.group !8
	// CHECK2-NEXT: store float 4.000000e+00, float* [[SFVAR]], align 4			// CHECK2-NEXT: store float 4.000000e+00, float* [[SFVAR]], align 4, !llvm.access.group !8
	// CHECK2-NEXT: [[TMP11:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 0			// CHECK2-NEXT: [[TMP11:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 0
	// CHECK2-NEXT: store double* [[G]], double** [[TMP11]], align 8			// CHECK2-NEXT: store double* [[G]], double** [[TMP11]], align 8, !llvm.access.group !8
	// CHECK2-NEXT: [[TMP12:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 1			// CHECK2-NEXT: [[TMP12:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 1
	// CHECK2-NEXT: [[TMP13:%.]] = load double, double** [[_TMP3]], align 8			// CHECK2-NEXT: [[TMP13:%.]] = load double, double** [[_TMP3]], align 8, !llvm.access.group !8
	// CHECK2-NEXT: store double* [[TMP13]], double** [[TMP12]], align 8			// CHECK2-NEXT: store double* [[TMP13]], double** [[TMP12]], align 8, !llvm.access.group !8
	// CHECK2-NEXT: [[TMP14:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 2			// CHECK2-NEXT: [[TMP14:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 2
	// CHECK2-NEXT: store i32* [[SVAR]], i32** [[TMP14]], align 8			// CHECK2-NEXT: store i32* [[SVAR]], i32** [[TMP14]], align 8, !llvm.access.group !8
	// CHECK2-NEXT: [[TMP15:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 3			// CHECK2-NEXT: [[TMP15:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 3
	// CHECK2-NEXT: store float* [[SFVAR]], float** [[TMP15]], align 8			// CHECK2-NEXT: store float* [[SFVAR]], float** [[TMP15]], align 8, !llvm.access.group !8
	// CHECK2-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(32) [[REF_TMP]])			// CHECK2-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(32) [[REF_TMP]]), !llvm.access.group !8
	// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK2: omp.body.continue:			// CHECK2: omp.body.continue:
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK2: omp.inner.for.inc:			// CHECK2: omp.inner.for.inc:
	// CHECK2-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !8
	// CHECK2-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP16]], 1			// CHECK2-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP16]], 1
	// CHECK2-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]
	// CHECK2: omp.inner.for.end:			// CHECK2: omp.inner.for.end:
	// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK2: omp.loop.exit:			// CHECK2: omp.loop.exit:
	// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])			// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
	// CHECK2-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK2-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK2-NEXT: [[TMP18:%.*]] = icmp ne i32 [[TMP17]], 0			// CHECK2-NEXT: [[TMP18:%.*]] = icmp ne i32 [[TMP17]], 0
	// CHECK2-NEXT: br i1 [[TMP18]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK2-NEXT: br i1 [[TMP18]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK2: .omp.final.then:			// CHECK2: .omp.final.then:
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	// CHECK3-NEXT: br label [[COND_END]]			// CHECK3-NEXT: br label [[COND_END]]
	// CHECK3: cond.end:			// CHECK3: cond.end:
	// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]			// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
	// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK3-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK3-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK3: omp.inner.for.cond:			// CHECK3: omp.inner.for.cond:
	// CHECK3-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK3-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK3-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK3-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5
	// CHECK3-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK3-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK3-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK3-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK3: omp.inner.for.body:			// CHECK3: omp.inner.for.body:
	// CHECK3-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK3-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !5
	// CHECK3-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK3-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5
	// CHECK3-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i32, i32)* @.omp_outlined..1 to void (i32, i32, ...)*), i32 [[TMP7]], i32 [[TMP8]])			// CHECK3-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i32, i32)* @.omp_outlined..1 to void (i32, i32, ...)*), i32 [[TMP7]], i32 [[TMP8]]), !llvm.access.group !5
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK3: omp.inner.for.inc:			// CHECK3: omp.inner.for.inc:
	// CHECK3-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK3-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK3-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK3-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !5
	// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], [[TMP10]]			// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], [[TMP10]]
	// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]
	// CHECK3: omp.inner.for.end:			// CHECK3: omp.inner.for.end:
	// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK3: omp.loop.exit:			// CHECK3: omp.loop.exit:
	// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])			// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
	// CHECK3-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK3-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK3-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK3-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK3-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK3-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK3: .omp.final.then:			// CHECK3: .omp.final.then:
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	// CHECK3-NEXT: br label [[COND_END]]			// CHECK3-NEXT: br label [[COND_END]]
	// CHECK3: cond.end:			// CHECK3: cond.end:
	// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]			// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
	// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK3-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK3-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK3-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK3-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK3: omp.inner.for.cond:			// CHECK3: omp.inner.for.cond:
	// CHECK3-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK3-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK3-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK3-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !9
	// CHECK3-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK3-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK3-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK3-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK3: omp.inner.for.body:			// CHECK3: omp.inner.for.body:
	// CHECK3-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK3-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9
	// CHECK3-NEXT: store double 1.000000e+00, double* [[G]], align 8			// CHECK3-NEXT: store double 1.000000e+00, double* [[G]], align 8, !llvm.access.group !9
	// CHECK3-NEXT: [[TMP10:%.]] = load double, double** [[_TMP2]], align 4			// CHECK3-NEXT: [[TMP10:%.]] = load double, double** [[_TMP2]], align 4, !llvm.access.group !9
	// CHECK3-NEXT: store volatile double 1.000000e+00, double* [[TMP10]], align 4			// CHECK3-NEXT: store volatile double 1.000000e+00, double* [[TMP10]], align 4, !llvm.access.group !9
	// CHECK3-NEXT: store i32 3, i32* [[SVAR]], align 4			// CHECK3-NEXT: store i32 3, i32* [[SVAR]], align 4, !llvm.access.group !9
	// CHECK3-NEXT: store float 4.000000e+00, float* [[SFVAR]], align 4			// CHECK3-NEXT: store float 4.000000e+00, float* [[SFVAR]], align 4, !llvm.access.group !9
	// CHECK3-NEXT: [[TMP11:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 0			// CHECK3-NEXT: [[TMP11:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 0
	// CHECK3-NEXT: store double* [[G]], double** [[TMP11]], align 4			// CHECK3-NEXT: store double* [[G]], double** [[TMP11]], align 4, !llvm.access.group !9
	// CHECK3-NEXT: [[TMP12:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 1			// CHECK3-NEXT: [[TMP12:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 1
	// CHECK3-NEXT: [[TMP13:%.]] = load double, double** [[_TMP2]], align 4			// CHECK3-NEXT: [[TMP13:%.]] = load double, double** [[_TMP2]], align 4, !llvm.access.group !9
	// CHECK3-NEXT: store double* [[TMP13]], double** [[TMP12]], align 4			// CHECK3-NEXT: store double* [[TMP13]], double** [[TMP12]], align 4, !llvm.access.group !9
	// CHECK3-NEXT: [[TMP14:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 2			// CHECK3-NEXT: [[TMP14:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 2
	// CHECK3-NEXT: store i32* [[SVAR]], i32** [[TMP14]], align 4			// CHECK3-NEXT: store i32* [[SVAR]], i32** [[TMP14]], align 4, !llvm.access.group !9
	// CHECK3-NEXT: [[TMP15:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 3			// CHECK3-NEXT: [[TMP15:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 3
	// CHECK3-NEXT: store float* [[SFVAR]], float** [[TMP15]], align 4			// CHECK3-NEXT: store float* [[SFVAR]], float** [[TMP15]], align 4, !llvm.access.group !9
	// CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 4 dereferenceable(16) [[REF_TMP]])			// CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 4 dereferenceable(16) [[REF_TMP]]), !llvm.access.group !9
	// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK3: omp.body.continue:			// CHECK3: omp.body.continue:
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK3: omp.inner.for.inc:			// CHECK3: omp.inner.for.inc:
	// CHECK3-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK3-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP16]], 1			// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP16]], 1
	// CHECK3-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4			// CHECK3-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]
	// CHECK3: omp.inner.for.end:			// CHECK3: omp.inner.for.end:
	// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK3: omp.loop.exit:			// CHECK3: omp.loop.exit:
	// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])			// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
	// CHECK3-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK3-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK3-NEXT: [[TMP18:%.*]] = icmp ne i32 [[TMP17]], 0			// CHECK3-NEXT: [[TMP18:%.*]] = icmp ne i32 [[TMP17]], 0
	// CHECK3-NEXT: br i1 [[TMP18]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK3-NEXT: br i1 [[TMP18]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK3: .omp.final.then:			// CHECK3: .omp.final.then:
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	// CHECK4-NEXT: br label [[COND_END]]			// CHECK4-NEXT: br label [[COND_END]]
	// CHECK4: cond.end:			// CHECK4: cond.end:
	// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]			// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
	// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK4-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK4-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK4-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK4-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK4: omp.inner.for.cond:			// CHECK4: omp.inner.for.cond:
	// CHECK4-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK4-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK4-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK4-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5
	// CHECK4-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK4-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK4-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK4-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK4: omp.inner.for.body:			// CHECK4: omp.inner.for.body:
	// CHECK4-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK4-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !5
	// CHECK4-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK4-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5
	// CHECK4-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i32, i32)* @.omp_outlined..1 to void (i32, i32, ...)*), i32 [[TMP7]], i32 [[TMP8]])			// CHECK4-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i32, i32)* @.omp_outlined..1 to void (i32, i32, ...)*), i32 [[TMP7]], i32 [[TMP8]]), !llvm.access.group !5
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK4: omp.inner.for.inc:			// CHECK4: omp.inner.for.inc:
	// CHECK4-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK4-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK4-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK4-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !5
	// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], [[TMP10]]			// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], [[TMP10]]
	// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]
	// CHECK4: omp.inner.for.end:			// CHECK4: omp.inner.for.end:
	// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK4: omp.loop.exit:			// CHECK4: omp.loop.exit:
	// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])			// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
	// CHECK4-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK4-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK4-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK4-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK4-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK4-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK4: .omp.final.then:			// CHECK4: .omp.final.then:
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	// CHECK4-NEXT: br label [[COND_END]]			// CHECK4-NEXT: br label [[COND_END]]
	// CHECK4: cond.end:			// CHECK4: cond.end:
	// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]			// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
	// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK4-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK4-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK4-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK4-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK4: omp.inner.for.cond:			// CHECK4: omp.inner.for.cond:
	// CHECK4-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK4-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK4-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK4-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !9
	// CHECK4-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK4-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK4-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK4-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK4: omp.inner.for.body:			// CHECK4: omp.inner.for.body:
	// CHECK4-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK4-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9
	// CHECK4-NEXT: store double 1.000000e+00, double* [[G]], align 8			// CHECK4-NEXT: store double 1.000000e+00, double* [[G]], align 8, !llvm.access.group !9
	// CHECK4-NEXT: [[TMP10:%.]] = load double, double** [[_TMP2]], align 4			// CHECK4-NEXT: [[TMP10:%.]] = load double, double** [[_TMP2]], align 4, !llvm.access.group !9
	// CHECK4-NEXT: store volatile double 1.000000e+00, double* [[TMP10]], align 4			// CHECK4-NEXT: store volatile double 1.000000e+00, double* [[TMP10]], align 4, !llvm.access.group !9
	// CHECK4-NEXT: store i32 3, i32* [[SVAR]], align 4			// CHECK4-NEXT: store i32 3, i32* [[SVAR]], align 4, !llvm.access.group !9
	// CHECK4-NEXT: store float 4.000000e+00, float* [[SFVAR]], align 4			// CHECK4-NEXT: store float 4.000000e+00, float* [[SFVAR]], align 4, !llvm.access.group !9
	// CHECK4-NEXT: [[TMP11:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 0			// CHECK4-NEXT: [[TMP11:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 0
	// CHECK4-NEXT: store double* [[G]], double** [[TMP11]], align 4			// CHECK4-NEXT: store double* [[G]], double** [[TMP11]], align 4, !llvm.access.group !9
	// CHECK4-NEXT: [[TMP12:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 1			// CHECK4-NEXT: [[TMP12:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 1
	// CHECK4-NEXT: [[TMP13:%.]] = load double, double** [[_TMP2]], align 4			// CHECK4-NEXT: [[TMP13:%.]] = load double, double** [[_TMP2]], align 4, !llvm.access.group !9
	// CHECK4-NEXT: store double* [[TMP13]], double** [[TMP12]], align 4			// CHECK4-NEXT: store double* [[TMP13]], double** [[TMP12]], align 4, !llvm.access.group !9
	// CHECK4-NEXT: [[TMP14:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 2			// CHECK4-NEXT: [[TMP14:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 2
	// CHECK4-NEXT: store i32* [[SVAR]], i32** [[TMP14]], align 4			// CHECK4-NEXT: store i32* [[SVAR]], i32** [[TMP14]], align 4, !llvm.access.group !9
	// CHECK4-NEXT: [[TMP15:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 3			// CHECK4-NEXT: [[TMP15:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 3
	// CHECK4-NEXT: store float* [[SFVAR]], float** [[TMP15]], align 4			// CHECK4-NEXT: store float* [[SFVAR]], float** [[TMP15]], align 4, !llvm.access.group !9
	// CHECK4-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 4 dereferenceable(16) [[REF_TMP]])			// CHECK4-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 4 dereferenceable(16) [[REF_TMP]]), !llvm.access.group !9
	// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK4: omp.body.continue:			// CHECK4: omp.body.continue:
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK4: omp.inner.for.inc:			// CHECK4: omp.inner.for.inc:
	// CHECK4-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK4-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP16]], 1			// CHECK4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP16]], 1
	// CHECK4-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4			// CHECK4-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]
	// CHECK4: omp.inner.for.end:			// CHECK4: omp.inner.for.end:
	// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK4: omp.loop.exit:			// CHECK4: omp.loop.exit:
	// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])			// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
	// CHECK4-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK4-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK4-NEXT: [[TMP18:%.*]] = icmp ne i32 [[TMP17]], 0			// CHECK4-NEXT: [[TMP18:%.*]] = icmp ne i32 [[TMP17]], 0
	// CHECK4-NEXT: br i1 [[TMP18]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK4-NEXT: br i1 [[TMP18]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK4: .omp.final.then:			// CHECK4: .omp.final.then:
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	// CHECK9-NEXT: br label [[COND_END]]			// CHECK9-NEXT: br label [[COND_END]]
	// CHECK9: cond.end:			// CHECK9: cond.end:
	// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]			// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
	// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK9-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK9-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK9: omp.inner.for.cond:			// CHECK9: omp.inner.for.cond:
	// CHECK9-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK9-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK9-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5
	// CHECK9-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK9-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK9-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]			// CHECK9-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]
	// CHECK9: omp.inner.for.cond.cleanup:			// CHECK9: omp.inner.for.cond.cleanup:
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_END:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
	// CHECK9: omp.inner.for.body:			// CHECK9: omp.inner.for.body:
	// CHECK9-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK9-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !5
	// CHECK9-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64			// CHECK9-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
	// CHECK9-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK9-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5
	// CHECK9-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK9-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK9-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..1 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]])			// CHECK9-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..1 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !5
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK9: omp.inner.for.inc:			// CHECK9: omp.inner.for.inc:
	// CHECK9-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK9-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK9-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !5
	// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]			// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
	// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]
	// CHECK9: omp.inner.for.end:			// CHECK9: omp.inner.for.end:
	// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK9: omp.loop.exit:			// CHECK9: omp.loop.exit:
	// CHECK9-NEXT: [[TMP13:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK9-NEXT: [[TMP13:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK9-NEXT: [[TMP14:%.]] = load i32, i32 [[TMP13]], align 4			// CHECK9-NEXT: [[TMP14:%.]] = load i32, i32 [[TMP13]], align 4
	// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP14]])			// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP14]])
	// CHECK9-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK9-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK9-NEXT: [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0			// CHECK9-NEXT: [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0
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	// CHECK9-NEXT: br label [[COND_END]]			// CHECK9-NEXT: br label [[COND_END]]
	// CHECK9: cond.end:			// CHECK9: cond.end:
	// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]			// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
	// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK9-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK9-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK9: omp.inner.for.cond:			// CHECK9: omp.inner.for.cond:
	// CHECK9-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK9-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK9-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !9
	// CHECK9-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK9-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK9-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]			// CHECK9-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]
	// CHECK9: omp.inner.for.cond.cleanup:			// CHECK9: omp.inner.for.cond.cleanup:
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_END:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
	// CHECK9: omp.inner.for.body:			// CHECK9: omp.inner.for.body:
	// CHECK9-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9
	// CHECK9-NEXT: [[TMP10:%.]] = load i32, i32 [[T_VAR]], align 4			// CHECK9-NEXT: [[TMP10:%.]] = load i32, i32 [[T_VAR]], align 4, !llvm.access.group !9
	// CHECK9-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4			// CHECK9-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !9
	// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64			// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64
	// CHECK9-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC]], i64 0, i64 [[IDXPROM]]			// CHECK9-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC]], i64 0, i64 [[IDXPROM]]
	// CHECK9-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4			// CHECK9-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !9
	// CHECK9-NEXT: [[TMP12:%.]] = load %struct.S, %struct.S** [[_TMP3]], align 8			// CHECK9-NEXT: [[TMP12:%.]] = load %struct.S, %struct.S** [[_TMP3]], align 8, !llvm.access.group !9
	// CHECK9-NEXT: [[TMP13:%.]] = load i32, i32 [[I]], align 4			// CHECK9-NEXT: [[TMP13:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !9
	// CHECK9-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP13]] to i64			// CHECK9-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP13]] to i64
	// CHECK9-NEXT: [[ARRAYIDX6:%.]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S] [[S_ARR]], i64 0, i64 [[IDXPROM5]]			// CHECK9-NEXT: [[ARRAYIDX6:%.]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S] [[S_ARR]], i64 0, i64 [[IDXPROM5]]
	// CHECK9-NEXT: [[TMP14:%.]] = bitcast %struct.S [[ARRAYIDX6]] to i8*			// CHECK9-NEXT: [[TMP14:%.]] = bitcast %struct.S [[ARRAYIDX6]] to i8*
	// CHECK9-NEXT: [[TMP15:%.]] = bitcast %struct.S [[TMP12]] to i8*			// CHECK9-NEXT: [[TMP15:%.]] = bitcast %struct.S [[TMP12]] to i8*
	// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP14]], i8* align 4 [[TMP15]], i64 4, i1 false)			// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP14]], i8* align 4 [[TMP15]], i64 4, i1 false), !llvm.access.group !9
	// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK9: omp.body.continue:			// CHECK9: omp.body.continue:
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK9: omp.inner.for.inc:			// CHECK9: omp.inner.for.inc:
	// CHECK9-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK9-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP16]], 1			// CHECK9-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP16]], 1
	// CHECK9-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4			// CHECK9-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]
	// CHECK9: omp.inner.for.end:			// CHECK9: omp.inner.for.end:
	// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK9: omp.loop.exit:			// CHECK9: omp.loop.exit:
	// CHECK9-NEXT: [[TMP17:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK9-NEXT: [[TMP17:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK9-NEXT: [[TMP18:%.]] = load i32, i32 [[TMP17]], align 4			// CHECK9-NEXT: [[TMP18:%.]] = load i32, i32 [[TMP17]], align 4
	// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP18]])			// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP18]])
	// CHECK9-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK9-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK9-NEXT: [[TMP20:%.*]] = icmp ne i32 [[TMP19]], 0			// CHECK9-NEXT: [[TMP20:%.*]] = icmp ne i32 [[TMP19]], 0
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	// CHECK9-NEXT: br label [[COND_END]]			// CHECK9-NEXT: br label [[COND_END]]
	// CHECK9: cond.end:			// CHECK9: cond.end:
	// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]			// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
	// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK9-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK9-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK9: omp.inner.for.cond:			// CHECK9: omp.inner.for.cond:
	// CHECK9-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK9-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK9-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !14
	// CHECK9-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK9-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK9-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]			// CHECK9-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]
	// CHECK9: omp.inner.for.cond.cleanup:			// CHECK9: omp.inner.for.cond.cleanup:
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_END:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
	// CHECK9: omp.inner.for.body:			// CHECK9: omp.inner.for.body:
	// CHECK9-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK9-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !14
	// CHECK9-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64			// CHECK9-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
	// CHECK9-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK9-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !14
	// CHECK9-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK9-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK9-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..3 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]])			// CHECK9-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..3 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !14
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK9: omp.inner.for.inc:			// CHECK9: omp.inner.for.inc:
	// CHECK9-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK9-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK9-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !14
	// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]			// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
	// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]]
	// CHECK9: omp.inner.for.end:			// CHECK9: omp.inner.for.end:
	// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK9: omp.loop.exit:			// CHECK9: omp.loop.exit:
	// CHECK9-NEXT: [[TMP13:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK9-NEXT: [[TMP13:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK9-NEXT: [[TMP14:%.]] = load i32, i32 [[TMP13]], align 4			// CHECK9-NEXT: [[TMP14:%.]] = load i32, i32 [[TMP13]], align 4
	// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP14]])			// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP14]])
	// CHECK9-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK9-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK9-NEXT: [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0			// CHECK9-NEXT: [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0
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	// CHECK9-NEXT: br label [[COND_END]]			// CHECK9-NEXT: br label [[COND_END]]
	// CHECK9: cond.end:			// CHECK9: cond.end:
	// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]			// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
	// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK9-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK9-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK9: omp.inner.for.cond:			// CHECK9: omp.inner.for.cond:
	// CHECK9-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !17
	// CHECK9-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK9-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !17
	// CHECK9-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK9-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK9-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]			// CHECK9-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]
	// CHECK9: omp.inner.for.cond.cleanup:			// CHECK9: omp.inner.for.cond.cleanup:
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_END:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
	// CHECK9: omp.inner.for.body:			// CHECK9: omp.inner.for.body:
	// CHECK9-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !17
	// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !17
	// CHECK9-NEXT: [[TMP10:%.]] = load i32, i32 [[T_VAR]], align 4			// CHECK9-NEXT: [[TMP10:%.]] = load i32, i32 [[T_VAR]], align 4, !llvm.access.group !17
	// CHECK9-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4			// CHECK9-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !17
	// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64			// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64
	// CHECK9-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC]], i64 0, i64 [[IDXPROM]]			// CHECK9-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC]], i64 0, i64 [[IDXPROM]]
	// CHECK9-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4			// CHECK9-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !17
	// CHECK9-NEXT: [[TMP12:%.]] = load %struct.S.0, %struct.S.0** [[_TMP3]], align 8			// CHECK9-NEXT: [[TMP12:%.]] = load %struct.S.0, %struct.S.0** [[_TMP3]], align 8, !llvm.access.group !17
	// CHECK9-NEXT: [[TMP13:%.]] = load i32, i32 [[I]], align 4			// CHECK9-NEXT: [[TMP13:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !17
	// CHECK9-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP13]] to i64			// CHECK9-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP13]] to i64
	// CHECK9-NEXT: [[ARRAYIDX6:%.]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0] [[S_ARR]], i64 0, i64 [[IDXPROM5]]			// CHECK9-NEXT: [[ARRAYIDX6:%.]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0] [[S_ARR]], i64 0, i64 [[IDXPROM5]]
	// CHECK9-NEXT: [[TMP14:%.]] = bitcast %struct.S.0 [[ARRAYIDX6]] to i8*			// CHECK9-NEXT: [[TMP14:%.]] = bitcast %struct.S.0 [[ARRAYIDX6]] to i8*
	// CHECK9-NEXT: [[TMP15:%.]] = bitcast %struct.S.0 [[TMP12]] to i8*			// CHECK9-NEXT: [[TMP15:%.]] = bitcast %struct.S.0 [[TMP12]] to i8*
	// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP14]], i8* align 4 [[TMP15]], i64 4, i1 false)			// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP14]], i8* align 4 [[TMP15]], i64 4, i1 false), !llvm.access.group !17
	// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK9: omp.body.continue:			// CHECK9: omp.body.continue:
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK9: omp.inner.for.inc:			// CHECK9: omp.inner.for.inc:
	// CHECK9-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !17
	// CHECK9-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP16]], 1			// CHECK9-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP16]], 1
	// CHECK9-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4			// CHECK9-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]]
	// CHECK9: omp.inner.for.end:			// CHECK9: omp.inner.for.end:
	// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK9: omp.loop.exit:			// CHECK9: omp.loop.exit:
	// CHECK9-NEXT: [[TMP17:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK9-NEXT: [[TMP17:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK9-NEXT: [[TMP18:%.]] = load i32, i32 [[TMP17]], align 4			// CHECK9-NEXT: [[TMP18:%.]] = load i32, i32 [[TMP17]], align 4
	// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP18]])			// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP18]])
	// CHECK9-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK9-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK9-NEXT: [[TMP20:%.*]] = icmp ne i32 [[TMP19]], 0			// CHECK9-NEXT: [[TMP20:%.*]] = icmp ne i32 [[TMP19]], 0
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	// CHECK10-NEXT: br label [[COND_END]]			// CHECK10-NEXT: br label [[COND_END]]
	// CHECK10: cond.end:			// CHECK10: cond.end:
	// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]			// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
	// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK10-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK10-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK10: omp.inner.for.cond:			// CHECK10: omp.inner.for.cond:
	// CHECK10-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK10-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK10-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5
	// CHECK10-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK10-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK10-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]			// CHECK10-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]
	// CHECK10: omp.inner.for.cond.cleanup:			// CHECK10: omp.inner.for.cond.cleanup:
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_END:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
	// CHECK10: omp.inner.for.body:			// CHECK10: omp.inner.for.body:
	// CHECK10-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK10-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !5
	// CHECK10-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64			// CHECK10-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
	// CHECK10-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK10-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5
	// CHECK10-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK10-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK10-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..1 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]])			// CHECK10-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..1 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !5
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK10: omp.inner.for.inc:			// CHECK10: omp.inner.for.inc:
	// CHECK10-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK10-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK10-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !5
	// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]			// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
	// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]
	// CHECK10: omp.inner.for.end:			// CHECK10: omp.inner.for.end:
	// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK10: omp.loop.exit:			// CHECK10: omp.loop.exit:
	// CHECK10-NEXT: [[TMP13:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK10-NEXT: [[TMP13:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK10-NEXT: [[TMP14:%.]] = load i32, i32 [[TMP13]], align 4			// CHECK10-NEXT: [[TMP14:%.]] = load i32, i32 [[TMP13]], align 4
	// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP14]])			// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP14]])
	// CHECK10-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK10-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK10-NEXT: [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0			// CHECK10-NEXT: [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0
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	// CHECK10-NEXT: br label [[COND_END]]			// CHECK10-NEXT: br label [[COND_END]]
	// CHECK10: cond.end:			// CHECK10: cond.end:
	// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]			// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
	// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK10-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK10-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK10: omp.inner.for.cond:			// CHECK10: omp.inner.for.cond:
	// CHECK10-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK10-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK10-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !9
	// CHECK10-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK10-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK10-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]			// CHECK10-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]
	// CHECK10: omp.inner.for.cond.cleanup:			// CHECK10: omp.inner.for.cond.cleanup:
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_END:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
	// CHECK10: omp.inner.for.body:			// CHECK10: omp.inner.for.body:
	// CHECK10-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9
	// CHECK10-NEXT: [[TMP10:%.]] = load i32, i32 [[T_VAR]], align 4			// CHECK10-NEXT: [[TMP10:%.]] = load i32, i32 [[T_VAR]], align 4, !llvm.access.group !9
	// CHECK10-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4			// CHECK10-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !9
	// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64			// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64
	// CHECK10-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC]], i64 0, i64 [[IDXPROM]]			// CHECK10-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC]], i64 0, i64 [[IDXPROM]]
	// CHECK10-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4			// CHECK10-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !9
	// CHECK10-NEXT: [[TMP12:%.]] = load %struct.S, %struct.S** [[_TMP3]], align 8			// CHECK10-NEXT: [[TMP12:%.]] = load %struct.S, %struct.S** [[_TMP3]], align 8, !llvm.access.group !9
	// CHECK10-NEXT: [[TMP13:%.]] = load i32, i32 [[I]], align 4			// CHECK10-NEXT: [[TMP13:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !9
	// CHECK10-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP13]] to i64			// CHECK10-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP13]] to i64
	// CHECK10-NEXT: [[ARRAYIDX6:%.]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S] [[S_ARR]], i64 0, i64 [[IDXPROM5]]			// CHECK10-NEXT: [[ARRAYIDX6:%.]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S] [[S_ARR]], i64 0, i64 [[IDXPROM5]]
	// CHECK10-NEXT: [[TMP14:%.]] = bitcast %struct.S [[ARRAYIDX6]] to i8*			// CHECK10-NEXT: [[TMP14:%.]] = bitcast %struct.S [[ARRAYIDX6]] to i8*
	// CHECK10-NEXT: [[TMP15:%.]] = bitcast %struct.S [[TMP12]] to i8*			// CHECK10-NEXT: [[TMP15:%.]] = bitcast %struct.S [[TMP12]] to i8*
	// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP14]], i8* align 4 [[TMP15]], i64 4, i1 false)			// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP14]], i8* align 4 [[TMP15]], i64 4, i1 false), !llvm.access.group !9
	// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK10: omp.body.continue:			// CHECK10: omp.body.continue:
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK10: omp.inner.for.inc:			// CHECK10: omp.inner.for.inc:
	// CHECK10-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK10-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP16]], 1			// CHECK10-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP16]], 1
	// CHECK10-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4			// CHECK10-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]
	// CHECK10: omp.inner.for.end:			// CHECK10: omp.inner.for.end:
	// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK10: omp.loop.exit:			// CHECK10: omp.loop.exit:
	// CHECK10-NEXT: [[TMP17:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK10-NEXT: [[TMP17:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK10-NEXT: [[TMP18:%.]] = load i32, i32 [[TMP17]], align 4			// CHECK10-NEXT: [[TMP18:%.]] = load i32, i32 [[TMP17]], align 4
	// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP18]])			// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP18]])
	// CHECK10-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK10-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK10-NEXT: [[TMP20:%.*]] = icmp ne i32 [[TMP19]], 0			// CHECK10-NEXT: [[TMP20:%.*]] = icmp ne i32 [[TMP19]], 0
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	// CHECK10-NEXT: br label [[COND_END]]			// CHECK10-NEXT: br label [[COND_END]]
	// CHECK10: cond.end:			// CHECK10: cond.end:
	// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]			// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
	// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK10-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK10-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK10: omp.inner.for.cond:			// CHECK10: omp.inner.for.cond:
	// CHECK10-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK10-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK10-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !14
	// CHECK10-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK10-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK10-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]			// CHECK10-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]
	// CHECK10: omp.inner.for.cond.cleanup:			// CHECK10: omp.inner.for.cond.cleanup:
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_END:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
	// CHECK10: omp.inner.for.body:			// CHECK10: omp.inner.for.body:
	// CHECK10-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK10-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !14
	// CHECK10-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64			// CHECK10-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
	// CHECK10-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK10-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !14
	// CHECK10-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK10-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK10-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..3 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]])			// CHECK10-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..3 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !14
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK10: omp.inner.for.inc:			// CHECK10: omp.inner.for.inc:
	// CHECK10-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK10-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK10-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !14
	// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]			// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
	// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]]
	// CHECK10: omp.inner.for.end:			// CHECK10: omp.inner.for.end:
	// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK10: omp.loop.exit:			// CHECK10: omp.loop.exit:
	// CHECK10-NEXT: [[TMP13:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK10-NEXT: [[TMP13:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK10-NEXT: [[TMP14:%.]] = load i32, i32 [[TMP13]], align 4			// CHECK10-NEXT: [[TMP14:%.]] = load i32, i32 [[TMP13]], align 4
	// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP14]])			// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP14]])
	// CHECK10-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK10-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK10-NEXT: [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0			// CHECK10-NEXT: [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0
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	// CHECK10-NEXT: br label [[COND_END]]			// CHECK10-NEXT: br label [[COND_END]]
	// CHECK10: cond.end:			// CHECK10: cond.end:
	// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]			// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
	// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK10-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK10-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK10: omp.inner.for.cond:			// CHECK10: omp.inner.for.cond:
	// CHECK10-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !17
	// CHECK10-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK10-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !17
	// CHECK10-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK10-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK10-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]			// CHECK10-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]
	// CHECK10: omp.inner.for.cond.cleanup:			// CHECK10: omp.inner.for.cond.cleanup:
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_END:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
	// CHECK10: omp.inner.for.body:			// CHECK10: omp.inner.for.body:
	// CHECK10-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !17
	// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !17
	// CHECK10-NEXT: [[TMP10:%.]] = load i32, i32 [[T_VAR]], align 4			// CHECK10-NEXT: [[TMP10:%.]] = load i32, i32 [[T_VAR]], align 4, !llvm.access.group !17
	// CHECK10-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4			// CHECK10-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !17
	// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64			// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64
	// CHECK10-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC]], i64 0, i64 [[IDXPROM]]			// CHECK10-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC]], i64 0, i64 [[IDXPROM]]
	// CHECK10-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4			// CHECK10-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !17
	// CHECK10-NEXT: [[TMP12:%.]] = load %struct.S.0, %struct.S.0** [[_TMP3]], align 8			// CHECK10-NEXT: [[TMP12:%.]] = load %struct.S.0, %struct.S.0** [[_TMP3]], align 8, !llvm.access.group !17
	// CHECK10-NEXT: [[TMP13:%.]] = load i32, i32 [[I]], align 4			// CHECK10-NEXT: [[TMP13:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !17
	// CHECK10-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP13]] to i64			// CHECK10-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP13]] to i64
	// CHECK10-NEXT: [[ARRAYIDX6:%.]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0] [[S_ARR]], i64 0, i64 [[IDXPROM5]]			// CHECK10-NEXT: [[ARRAYIDX6:%.]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0] [[S_ARR]], i64 0, i64 [[IDXPROM5]]
	// CHECK10-NEXT: [[TMP14:%.]] = bitcast %struct.S.0 [[ARRAYIDX6]] to i8*			// CHECK10-NEXT: [[TMP14:%.]] = bitcast %struct.S.0 [[ARRAYIDX6]] to i8*
	// CHECK10-NEXT: [[TMP15:%.]] = bitcast %struct.S.0 [[TMP12]] to i8*			// CHECK10-NEXT: [[TMP15:%.]] = bitcast %struct.S.0 [[TMP12]] to i8*
	// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP14]], i8* align 4 [[TMP15]], i64 4, i1 false)			// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP14]], i8* align 4 [[TMP15]], i64 4, i1 false), !llvm.access.group !17
	// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK10: omp.body.continue:			// CHECK10: omp.body.continue:
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK10: omp.inner.for.inc:			// CHECK10: omp.inner.for.inc:
	// CHECK10-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !17
	// CHECK10-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP16]], 1			// CHECK10-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP16]], 1
	// CHECK10-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4			// CHECK10-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]]
	// CHECK10: omp.inner.for.end:			// CHECK10: omp.inner.for.end:
	// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK10: omp.loop.exit:			// CHECK10: omp.loop.exit:
	// CHECK10-NEXT: [[TMP17:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK10-NEXT: [[TMP17:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK10-NEXT: [[TMP18:%.]] = load i32, i32 [[TMP17]], align 4			// CHECK10-NEXT: [[TMP18:%.]] = load i32, i32 [[TMP17]], align 4
	// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP18]])			// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP18]])
	// CHECK10-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK10-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK10-NEXT: [[TMP20:%.*]] = icmp ne i32 [[TMP19]], 0			// CHECK10-NEXT: [[TMP20:%.*]] = icmp ne i32 [[TMP19]], 0
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	// CHECK11-NEXT: br label [[COND_END]]			// CHECK11-NEXT: br label [[COND_END]]
	// CHECK11: cond.end:			// CHECK11: cond.end:
	// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]			// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
	// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK11-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK11-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK11-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK11-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK11: omp.inner.for.cond:			// CHECK11: omp.inner.for.cond:
	// CHECK11-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK11-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !6
	// CHECK11-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK11-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !6
	// CHECK11-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK11-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK11-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]			// CHECK11-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]
	// CHECK11: omp.inner.for.cond.cleanup:			// CHECK11: omp.inner.for.cond.cleanup:
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_END:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
	// CHECK11: omp.inner.for.body:			// CHECK11: omp.inner.for.body:
	// CHECK11-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK11-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !6
	// CHECK11-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK11-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !6
	// CHECK11-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i32, i32)* @.omp_outlined..1 to void (i32, i32, ...)*), i32 [[TMP7]], i32 [[TMP8]])			// CHECK11-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i32, i32)* @.omp_outlined..1 to void (i32, i32, ...)*), i32 [[TMP7]], i32 [[TMP8]]), !llvm.access.group !6
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK11: omp.inner.for.inc:			// CHECK11: omp.inner.for.inc:
	// CHECK11-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK11-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !6
	// CHECK11-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK11-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !6
	// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], [[TMP10]]			// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], [[TMP10]]
	// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]
	// CHECK11: omp.inner.for.end:			// CHECK11: omp.inner.for.end:
	// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK11: omp.loop.exit:			// CHECK11: omp.loop.exit:
	// CHECK11-NEXT: [[TMP11:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4			// CHECK11-NEXT: [[TMP11:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4
	// CHECK11-NEXT: [[TMP12:%.]] = load i32, i32 [[TMP11]], align 4			// CHECK11-NEXT: [[TMP12:%.]] = load i32, i32 [[TMP11]], align 4
	// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP12]])			// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP12]])
	// CHECK11-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK11-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK11-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0			// CHECK11-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
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	// CHECK11-NEXT: br label [[COND_END]]			// CHECK11-NEXT: br label [[COND_END]]
	// CHECK11: cond.end:			// CHECK11: cond.end:
	// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]			// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
	// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK11-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK11-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK11-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK11-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK11: omp.inner.for.cond:			// CHECK11: omp.inner.for.cond:
	// CHECK11-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK11-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK11-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK11-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !10
	// CHECK11-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK11-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK11-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]			// CHECK11-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]
	// CHECK11: omp.inner.for.cond.cleanup:			// CHECK11: omp.inner.for.cond.cleanup:
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_END:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
	// CHECK11: omp.inner.for.body:			// CHECK11: omp.inner.for.body:
	// CHECK11-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK11-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10
	// CHECK11-NEXT: [[TMP10:%.]] = load i32, i32 [[T_VAR]], align 4			// CHECK11-NEXT: [[TMP10:%.]] = load i32, i32 [[T_VAR]], align 4, !llvm.access.group !10
	// CHECK11-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4			// CHECK11-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !10
	// CHECK11-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC]], i32 0, i32 [[TMP11]]			// CHECK11-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC]], i32 0, i32 [[TMP11]]
	// CHECK11-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4			// CHECK11-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !10
	// CHECK11-NEXT: [[TMP12:%.]] = load %struct.S, %struct.S** [[_TMP2]], align 4			// CHECK11-NEXT: [[TMP12:%.]] = load %struct.S, %struct.S** [[_TMP2]], align 4, !llvm.access.group !10
	// CHECK11-NEXT: [[TMP13:%.]] = load i32, i32 [[I]], align 4			// CHECK11-NEXT: [[TMP13:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !10
	// CHECK11-NEXT: [[ARRAYIDX4:%.]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S] [[S_ARR]], i32 0, i32 [[TMP13]]			// CHECK11-NEXT: [[ARRAYIDX4:%.]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S] [[S_ARR]], i32 0, i32 [[TMP13]]
	// CHECK11-NEXT: [[TMP14:%.]] = bitcast %struct.S [[ARRAYIDX4]] to i8*			// CHECK11-NEXT: [[TMP14:%.]] = bitcast %struct.S [[ARRAYIDX4]] to i8*
	// CHECK11-NEXT: [[TMP15:%.]] = bitcast %struct.S [[TMP12]] to i8*			// CHECK11-NEXT: [[TMP15:%.]] = bitcast %struct.S [[TMP12]] to i8*
	// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP14]], i8* align 4 [[TMP15]], i32 4, i1 false)			// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP14]], i8* align 4 [[TMP15]], i32 4, i1 false), !llvm.access.group !10
	// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK11: omp.body.continue:			// CHECK11: omp.body.continue:
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK11: omp.inner.for.inc:			// CHECK11: omp.inner.for.inc:
	// CHECK11-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK11-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK11-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP16]], 1			// CHECK11-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP16]], 1
	// CHECK11-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4			// CHECK11-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]
	// CHECK11: omp.inner.for.end:			// CHECK11: omp.inner.for.end:
	// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK11: omp.loop.exit:			// CHECK11: omp.loop.exit:
	// CHECK11-NEXT: [[TMP17:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4			// CHECK11-NEXT: [[TMP17:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4
	// CHECK11-NEXT: [[TMP18:%.]] = load i32, i32 [[TMP17]], align 4			// CHECK11-NEXT: [[TMP18:%.]] = load i32, i32 [[TMP17]], align 4
	// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP18]])			// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP18]])
	// CHECK11-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK11-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK11-NEXT: [[TMP20:%.*]] = icmp ne i32 [[TMP19]], 0			// CHECK11-NEXT: [[TMP20:%.*]] = icmp ne i32 [[TMP19]], 0
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	// CHECK11-NEXT: br label [[COND_END]]			// CHECK11-NEXT: br label [[COND_END]]
	// CHECK11: cond.end:			// CHECK11: cond.end:
	// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]			// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
	// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK11-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK11-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK11-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK11-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK11: omp.inner.for.cond:			// CHECK11: omp.inner.for.cond:
	// CHECK11-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK11-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK11-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK11-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15
	// CHECK11-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK11-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK11-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]			// CHECK11-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]
	// CHECK11: omp.inner.for.cond.cleanup:			// CHECK11: omp.inner.for.cond.cleanup:
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_END:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
	// CHECK11: omp.inner.for.body:			// CHECK11: omp.inner.for.body:
	// CHECK11-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK11-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !15
	// CHECK11-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK11-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15
	// CHECK11-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i32, i32)* @.omp_outlined..3 to void (i32, i32, ...)*), i32 [[TMP7]], i32 [[TMP8]])			// CHECK11-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i32, i32)* @.omp_outlined..3 to void (i32, i32, ...)*), i32 [[TMP7]], i32 [[TMP8]]), !llvm.access.group !15
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK11: omp.inner.for.inc:			// CHECK11: omp.inner.for.inc:
	// CHECK11-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK11-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK11-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK11-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !15
	// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], [[TMP10]]			// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], [[TMP10]]
	// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]]
	// CHECK11: omp.inner.for.end:			// CHECK11: omp.inner.for.end:
	// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK11: omp.loop.exit:			// CHECK11: omp.loop.exit:
	// CHECK11-NEXT: [[TMP11:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4			// CHECK11-NEXT: [[TMP11:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4
	// CHECK11-NEXT: [[TMP12:%.]] = load i32, i32 [[TMP11]], align 4			// CHECK11-NEXT: [[TMP12:%.]] = load i32, i32 [[TMP11]], align 4
	// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP12]])			// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP12]])
	// CHECK11-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK11-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK11-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0			// CHECK11-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
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	// CHECK11-NEXT: br label [[COND_END]]			// CHECK11-NEXT: br label [[COND_END]]
	// CHECK11: cond.end:			// CHECK11: cond.end:
	// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]			// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
	// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK11-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK11-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK11-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK11-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK11: omp.inner.for.cond:			// CHECK11: omp.inner.for.cond:
	// CHECK11-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK11-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK11-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK11-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !18
	// CHECK11-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK11-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK11-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]			// CHECK11-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]
	// CHECK11: omp.inner.for.cond.cleanup:			// CHECK11: omp.inner.for.cond.cleanup:
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_END:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
	// CHECK11: omp.inner.for.body:			// CHECK11: omp.inner.for.body:
	// CHECK11-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK11-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !18
	// CHECK11-NEXT: [[TMP10:%.]] = load i32, i32 [[T_VAR]], align 4			// CHECK11-NEXT: [[TMP10:%.]] = load i32, i32 [[T_VAR]], align 4, !llvm.access.group !18
	// CHECK11-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4			// CHECK11-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !18
	// CHECK11-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC]], i32 0, i32 [[TMP11]]			// CHECK11-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC]], i32 0, i32 [[TMP11]]
	// CHECK11-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4			// CHECK11-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !18
	// CHECK11-NEXT: [[TMP12:%.]] = load %struct.S.0, %struct.S.0** [[_TMP2]], align 4			// CHECK11-NEXT: [[TMP12:%.]] = load %struct.S.0, %struct.S.0** [[_TMP2]], align 4, !llvm.access.group !18
	// CHECK11-NEXT: [[TMP13:%.]] = load i32, i32 [[I]], align 4			// CHECK11-NEXT: [[TMP13:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !18
	// CHECK11-NEXT: [[ARRAYIDX4:%.]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0] [[S_ARR]], i32 0, i32 [[TMP13]]			// CHECK11-NEXT: [[ARRAYIDX4:%.]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0] [[S_ARR]], i32 0, i32 [[TMP13]]
	// CHECK11-NEXT: [[TMP14:%.]] = bitcast %struct.S.0 [[ARRAYIDX4]] to i8*			// CHECK11-NEXT: [[TMP14:%.]] = bitcast %struct.S.0 [[ARRAYIDX4]] to i8*
	// CHECK11-NEXT: [[TMP15:%.]] = bitcast %struct.S.0 [[TMP12]] to i8*			// CHECK11-NEXT: [[TMP15:%.]] = bitcast %struct.S.0 [[TMP12]] to i8*
	// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP14]], i8* align 4 [[TMP15]], i32 4, i1 false)			// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP14]], i8* align 4 [[TMP15]], i32 4, i1 false), !llvm.access.group !18
	// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK11: omp.body.continue:			// CHECK11: omp.body.continue:
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK11: omp.inner.for.inc:			// CHECK11: omp.inner.for.inc:
	// CHECK11-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK11-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK11-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP16]], 1			// CHECK11-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP16]], 1
	// CHECK11-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4			// CHECK11-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]
	// CHECK11: omp.inner.for.end:			// CHECK11: omp.inner.for.end:
	// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK11: omp.loop.exit:			// CHECK11: omp.loop.exit:
	// CHECK11-NEXT: [[TMP17:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4			// CHECK11-NEXT: [[TMP17:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4
	// CHECK11-NEXT: [[TMP18:%.]] = load i32, i32 [[TMP17]], align 4			// CHECK11-NEXT: [[TMP18:%.]] = load i32, i32 [[TMP17]], align 4
	// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP18]])			// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP18]])
	// CHECK11-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK11-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK11-NEXT: [[TMP20:%.*]] = icmp ne i32 [[TMP19]], 0			// CHECK11-NEXT: [[TMP20:%.*]] = icmp ne i32 [[TMP19]], 0
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	// CHECK12-NEXT: br label [[COND_END]]			// CHECK12-NEXT: br label [[COND_END]]
	// CHECK12: cond.end:			// CHECK12: cond.end:
	// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]			// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
	// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK12-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK12-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK12-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK12-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK12: omp.inner.for.cond:			// CHECK12: omp.inner.for.cond:
	// CHECK12-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK12-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !6
	// CHECK12-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK12-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !6
	// CHECK12-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK12-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK12-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]			// CHECK12-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]
	// CHECK12: omp.inner.for.cond.cleanup:			// CHECK12: omp.inner.for.cond.cleanup:
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_END:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
	// CHECK12: omp.inner.for.body:			// CHECK12: omp.inner.for.body:
	// CHECK12-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK12-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !6
	// CHECK12-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK12-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !6
	// CHECK12-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i32, i32)* @.omp_outlined..1 to void (i32, i32, ...)*), i32 [[TMP7]], i32 [[TMP8]])			// CHECK12-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i32, i32)* @.omp_outlined..1 to void (i32, i32, ...)*), i32 [[TMP7]], i32 [[TMP8]]), !llvm.access.group !6
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK12: omp.inner.for.inc:			// CHECK12: omp.inner.for.inc:
	// CHECK12-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK12-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !6
	// CHECK12-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK12-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !6
	// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], [[TMP10]]			// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], [[TMP10]]
	// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]
	// CHECK12: omp.inner.for.end:			// CHECK12: omp.inner.for.end:
	// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK12: omp.loop.exit:			// CHECK12: omp.loop.exit:
	// CHECK12-NEXT: [[TMP11:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4			// CHECK12-NEXT: [[TMP11:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4
	// CHECK12-NEXT: [[TMP12:%.]] = load i32, i32 [[TMP11]], align 4			// CHECK12-NEXT: [[TMP12:%.]] = load i32, i32 [[TMP11]], align 4
	// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP12]])			// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP12]])
	// CHECK12-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK12-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK12-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0			// CHECK12-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
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	// CHECK12-NEXT: br label [[COND_END]]			// CHECK12-NEXT: br label [[COND_END]]
	// CHECK12: cond.end:			// CHECK12: cond.end:
	// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]			// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
	// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK12-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK12-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK12-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK12-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK12: omp.inner.for.cond:			// CHECK12: omp.inner.for.cond:
	// CHECK12-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK12-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK12-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK12-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !10
	// CHECK12-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK12-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK12-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]			// CHECK12-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]
	// CHECK12: omp.inner.for.cond.cleanup:			// CHECK12: omp.inner.for.cond.cleanup:
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_END:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
	// CHECK12: omp.inner.for.body:			// CHECK12: omp.inner.for.body:
	// CHECK12-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK12-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10
	// CHECK12-NEXT: [[TMP10:%.]] = load i32, i32 [[T_VAR]], align 4			// CHECK12-NEXT: [[TMP10:%.]] = load i32, i32 [[T_VAR]], align 4, !llvm.access.group !10
	// CHECK12-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4			// CHECK12-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !10
	// CHECK12-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC]], i32 0, i32 [[TMP11]]			// CHECK12-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC]], i32 0, i32 [[TMP11]]
	// CHECK12-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4			// CHECK12-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !10
	// CHECK12-NEXT: [[TMP12:%.]] = load %struct.S, %struct.S** [[_TMP2]], align 4			// CHECK12-NEXT: [[TMP12:%.]] = load %struct.S, %struct.S** [[_TMP2]], align 4, !llvm.access.group !10
	// CHECK12-NEXT: [[TMP13:%.]] = load i32, i32 [[I]], align 4			// CHECK12-NEXT: [[TMP13:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !10
	// CHECK12-NEXT: [[ARRAYIDX4:%.]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S] [[S_ARR]], i32 0, i32 [[TMP13]]			// CHECK12-NEXT: [[ARRAYIDX4:%.]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S] [[S_ARR]], i32 0, i32 [[TMP13]]
	// CHECK12-NEXT: [[TMP14:%.]] = bitcast %struct.S [[ARRAYIDX4]] to i8*			// CHECK12-NEXT: [[TMP14:%.]] = bitcast %struct.S [[ARRAYIDX4]] to i8*
	// CHECK12-NEXT: [[TMP15:%.]] = bitcast %struct.S [[TMP12]] to i8*			// CHECK12-NEXT: [[TMP15:%.]] = bitcast %struct.S [[TMP12]] to i8*
	// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP14]], i8* align 4 [[TMP15]], i32 4, i1 false)			// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP14]], i8* align 4 [[TMP15]], i32 4, i1 false), !llvm.access.group !10
	// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK12: omp.body.continue:			// CHECK12: omp.body.continue:
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK12: omp.inner.for.inc:			// CHECK12: omp.inner.for.inc:
	// CHECK12-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK12-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK12-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP16]], 1			// CHECK12-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP16]], 1
	// CHECK12-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4			// CHECK12-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]
	// CHECK12: omp.inner.for.end:			// CHECK12: omp.inner.for.end:
	// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK12: omp.loop.exit:			// CHECK12: omp.loop.exit:
	// CHECK12-NEXT: [[TMP17:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4			// CHECK12-NEXT: [[TMP17:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4
	// CHECK12-NEXT: [[TMP18:%.]] = load i32, i32 [[TMP17]], align 4			// CHECK12-NEXT: [[TMP18:%.]] = load i32, i32 [[TMP17]], align 4
	// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP18]])			// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP18]])
	// CHECK12-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK12-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK12-NEXT: [[TMP20:%.*]] = icmp ne i32 [[TMP19]], 0			// CHECK12-NEXT: [[TMP20:%.*]] = icmp ne i32 [[TMP19]], 0
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	// CHECK12-NEXT: br label [[COND_END]]			// CHECK12-NEXT: br label [[COND_END]]
	// CHECK12: cond.end:			// CHECK12: cond.end:
	// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]			// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
	// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK12-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK12-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK12-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK12-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK12: omp.inner.for.cond:			// CHECK12: omp.inner.for.cond:
	// CHECK12-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK12-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK12-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK12-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15
	// CHECK12-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK12-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK12-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]			// CHECK12-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]
	// CHECK12: omp.inner.for.cond.cleanup:			// CHECK12: omp.inner.for.cond.cleanup:
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_END:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
	// CHECK12: omp.inner.for.body:			// CHECK12: omp.inner.for.body:
	// CHECK12-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK12-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !15
	// CHECK12-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK12-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15
	// CHECK12-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i32, i32)* @.omp_outlined..3 to void (i32, i32, ...)*), i32 [[TMP7]], i32 [[TMP8]])			// CHECK12-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i32, i32)* @.omp_outlined..3 to void (i32, i32, ...)*), i32 [[TMP7]], i32 [[TMP8]]), !llvm.access.group !15
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK12: omp.inner.for.inc:			// CHECK12: omp.inner.for.inc:
	// CHECK12-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK12-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK12-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK12-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !15
	// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], [[TMP10]]			// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], [[TMP10]]
	// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]]
	// CHECK12: omp.inner.for.end:			// CHECK12: omp.inner.for.end:
	// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK12: omp.loop.exit:			// CHECK12: omp.loop.exit:
	// CHECK12-NEXT: [[TMP11:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4			// CHECK12-NEXT: [[TMP11:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4
	// CHECK12-NEXT: [[TMP12:%.]] = load i32, i32 [[TMP11]], align 4			// CHECK12-NEXT: [[TMP12:%.]] = load i32, i32 [[TMP11]], align 4
	// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP12]])			// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP12]])
	// CHECK12-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK12-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK12-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0			// CHECK12-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
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	// CHECK12-NEXT: br label [[COND_END]]			// CHECK12-NEXT: br label [[COND_END]]
	// CHECK12: cond.end:			// CHECK12: cond.end:
	// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]			// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
	// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK12-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK12-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK12-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK12-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK12: omp.inner.for.cond:			// CHECK12: omp.inner.for.cond:
	// CHECK12-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK12-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK12-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK12-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !18
	// CHECK12-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK12-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK12-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]			// CHECK12-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]
	// CHECK12: omp.inner.for.cond.cleanup:			// CHECK12: omp.inner.for.cond.cleanup:
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_END:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
	// CHECK12: omp.inner.for.body:			// CHECK12: omp.inner.for.body:
	// CHECK12-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK12-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !18
	// CHECK12-NEXT: [[TMP10:%.]] = load i32, i32 [[T_VAR]], align 4			// CHECK12-NEXT: [[TMP10:%.]] = load i32, i32 [[T_VAR]], align 4, !llvm.access.group !18
	// CHECK12-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4			// CHECK12-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !18
	// CHECK12-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC]], i32 0, i32 [[TMP11]]			// CHECK12-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC]], i32 0, i32 [[TMP11]]
	// CHECK12-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4			// CHECK12-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !18
	// CHECK12-NEXT: [[TMP12:%.]] = load %struct.S.0, %struct.S.0** [[_TMP2]], align 4			// CHECK12-NEXT: [[TMP12:%.]] = load %struct.S.0, %struct.S.0** [[_TMP2]], align 4, !llvm.access.group !18
	// CHECK12-NEXT: [[TMP13:%.]] = load i32, i32 [[I]], align 4			// CHECK12-NEXT: [[TMP13:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !18
	// CHECK12-NEXT: [[ARRAYIDX4:%.]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0] [[S_ARR]], i32 0, i32 [[TMP13]]			// CHECK12-NEXT: [[ARRAYIDX4:%.]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0] [[S_ARR]], i32 0, i32 [[TMP13]]
	// CHECK12-NEXT: [[TMP14:%.]] = bitcast %struct.S.0 [[ARRAYIDX4]] to i8*			// CHECK12-NEXT: [[TMP14:%.]] = bitcast %struct.S.0 [[ARRAYIDX4]] to i8*
	// CHECK12-NEXT: [[TMP15:%.]] = bitcast %struct.S.0 [[TMP12]] to i8*			// CHECK12-NEXT: [[TMP15:%.]] = bitcast %struct.S.0 [[TMP12]] to i8*
	// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP14]], i8* align 4 [[TMP15]], i32 4, i1 false)			// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP14]], i8* align 4 [[TMP15]], i32 4, i1 false), !llvm.access.group !18
	// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK12: omp.body.continue:			// CHECK12: omp.body.continue:
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK12: omp.inner.for.inc:			// CHECK12: omp.inner.for.inc:
	// CHECK12-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK12-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK12-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP16]], 1			// CHECK12-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP16]], 1
	// CHECK12-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4			// CHECK12-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]
	// CHECK12: omp.inner.for.end:			// CHECK12: omp.inner.for.end:
	// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK12: omp.loop.exit:			// CHECK12: omp.loop.exit:
	// CHECK12-NEXT: [[TMP17:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4			// CHECK12-NEXT: [[TMP17:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4
	// CHECK12-NEXT: [[TMP18:%.]] = load i32, i32 [[TMP17]], align 4			// CHECK12-NEXT: [[TMP18:%.]] = load i32, i32 [[TMP17]], align 4
	// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP18]])			// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP18]])
	// CHECK12-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK12-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK12-NEXT: [[TMP20:%.*]] = icmp ne i32 [[TMP19]], 0			// CHECK12-NEXT: [[TMP20:%.*]] = icmp ne i32 [[TMP19]], 0
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clang/test/OpenMP/distribute_parallel_for_simd_proc_bind_codegen.cpp

	Show First 20 Lines • Show All 117 Lines • ▼ Show 20 Lines
	// CHECK1-NEXT: br label [[COND_END]]			// CHECK1-NEXT: br label [[COND_END]]
	// CHECK1: cond.end:			// CHECK1: cond.end:
	// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 999, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]			// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 999, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
	// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK1-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK1-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK1: omp.inner.for.cond:			// CHECK1: omp.inner.for.cond:
	// CHECK1-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !6
	// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !6
	// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK1: omp.inner.for.body:			// CHECK1: omp.inner.for.body:
	// CHECK1-NEXT: call void @__kmpc_push_proc_bind(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 4)			// CHECK1-NEXT: call void @__kmpc_push_proc_bind(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 4), !llvm.access.group !6
	// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !6
	// CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64			// CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
	// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !6
	// CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK1-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..1 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]])			// CHECK1-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..1 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !6
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK1: omp.inner.for.inc:			// CHECK1: omp.inner.for.inc:
	// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !6
	// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !6
	// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]			// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
	// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]
	// CHECK1: omp.inner.for.end:			// CHECK1: omp.inner.for.end:
	// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK1: omp.loop.exit:			// CHECK1: omp.loop.exit:
	// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])			// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
	// CHECK1-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK1-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK1-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0			// CHECK1-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
	// CHECK1-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK1-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK1: .omp.final.then:			// CHECK1: .omp.final.then:
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	// CHECK1-NEXT: br label [[COND_END]]			// CHECK1-NEXT: br label [[COND_END]]
	// CHECK1: cond.end:			// CHECK1: cond.end:
	// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 999, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]			// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 999, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
	// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK1-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK1: omp.inner.for.cond:			// CHECK1: omp.inner.for.cond:
	// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK1-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK1-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !10
	// CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK1: omp.inner.for.body:			// CHECK1: omp.inner.for.body:
	// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10
	// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK1: omp.body.continue:			// CHECK1: omp.body.continue:
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK1: omp.inner.for.inc:			// CHECK1: omp.inner.for.inc:
	// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]
	// CHECK1: omp.inner.for.end:			// CHECK1: omp.inner.for.end:
	// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK1: omp.loop.exit:			// CHECK1: omp.loop.exit:
	// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])			// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
	// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK1-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK1-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK1-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK1-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK1: .omp.final.then:			// CHECK1: .omp.final.then:
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	// CHECK1-NEXT: br label [[COND_END]]			// CHECK1-NEXT: br label [[COND_END]]
	// CHECK1: cond.end:			// CHECK1: cond.end:
	// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 999, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]			// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 999, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
	// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK1-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK1-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK1: omp.inner.for.cond:			// CHECK1: omp.inner.for.cond:
	// CHECK1-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15
	// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK1: omp.inner.for.body:			// CHECK1: omp.inner.for.body:
	// CHECK1-NEXT: call void @__kmpc_push_proc_bind(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 3)			// CHECK1-NEXT: call void @__kmpc_push_proc_bind(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 3), !llvm.access.group !15
	// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !15
	// CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64			// CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
	// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15
	// CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK1-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..3 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]])			// CHECK1-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..3 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !15
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK1: omp.inner.for.inc:			// CHECK1: omp.inner.for.inc:
	// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !15
	// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]			// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
	// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]]
	// CHECK1: omp.inner.for.end:			// CHECK1: omp.inner.for.end:
	// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK1: omp.loop.exit:			// CHECK1: omp.loop.exit:
	// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])			// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
	// CHECK1-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK1-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK1-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0			// CHECK1-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
	// CHECK1-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK1-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK1: .omp.final.then:			// CHECK1: .omp.final.then:
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	// CHECK1-NEXT: br label [[COND_END]]			// CHECK1-NEXT: br label [[COND_END]]
	// CHECK1: cond.end:			// CHECK1: cond.end:
	// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 999, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]			// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 999, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
	// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK1-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK1: omp.inner.for.cond:			// CHECK1: omp.inner.for.cond:
	// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK1-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK1-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !18
	// CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK1: omp.inner.for.body:			// CHECK1: omp.inner.for.body:
	// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !18
	// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK1: omp.body.continue:			// CHECK1: omp.body.continue:
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK1: omp.inner.for.inc:			// CHECK1: omp.inner.for.inc:
	// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]
	// CHECK1: omp.inner.for.end:			// CHECK1: omp.inner.for.end:
	// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK1: omp.loop.exit:			// CHECK1: omp.loop.exit:
	// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])			// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
	// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK1-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK1-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK1-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK1-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK1: .omp.final.then:			// CHECK1: .omp.final.then:
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	// CHECK1-NEXT: br label [[COND_END]]			// CHECK1-NEXT: br label [[COND_END]]
	// CHECK1: cond.end:			// CHECK1: cond.end:
	// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 999, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]			// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 999, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
	// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK1-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK1-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK1: omp.inner.for.cond:			// CHECK1: omp.inner.for.cond:
	// CHECK1-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !21
	// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !21
	// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK1: omp.inner.for.body:			// CHECK1: omp.inner.for.body:
	// CHECK1-NEXT: call void @__kmpc_push_proc_bind(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 2)			// CHECK1-NEXT: call void @__kmpc_push_proc_bind(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 2), !llvm.access.group !21
	// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !21
	// CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64			// CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
	// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !21
	// CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK1-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..5 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]])			// CHECK1-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..5 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !21
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK1: omp.inner.for.inc:			// CHECK1: omp.inner.for.inc:
	// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !21
	// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !21
	// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]			// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
	// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]]
	// CHECK1: omp.inner.for.end:			// CHECK1: omp.inner.for.end:
	// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK1: omp.loop.exit:			// CHECK1: omp.loop.exit:
	// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])			// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
	// CHECK1-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK1-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK1-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0			// CHECK1-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
	// CHECK1-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK1-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK1: .omp.final.then:			// CHECK1: .omp.final.then:
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	// CHECK1-NEXT: br label [[COND_END]]			// CHECK1-NEXT: br label [[COND_END]]
	// CHECK1: cond.end:			// CHECK1: cond.end:
	// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 999, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]			// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 999, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
	// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK1-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK1: omp.inner.for.cond:			// CHECK1: omp.inner.for.cond:
	// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !24
	// CHECK1-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK1-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !24
	// CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK1: omp.inner.for.body:			// CHECK1: omp.inner.for.body:
	// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !24
	// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !24
	// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK1: omp.body.continue:			// CHECK1: omp.body.continue:
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK1: omp.inner.for.inc:			// CHECK1: omp.inner.for.inc:
	// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !24
	// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]]
	// CHECK1: omp.inner.for.end:			// CHECK1: omp.inner.for.end:
	// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK1: omp.loop.exit:			// CHECK1: omp.loop.exit:
	// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])			// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
	// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK1-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK1-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK1-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK1-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK1: .omp.final.then:			// CHECK1: .omp.final.then:
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	// CHECK2-NEXT: br label [[COND_END]]			// CHECK2-NEXT: br label [[COND_END]]
	// CHECK2: cond.end:			// CHECK2: cond.end:
	// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 999, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]			// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 999, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
	// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK2-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK2-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK2-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK2: omp.inner.for.cond:			// CHECK2: omp.inner.for.cond:
	// CHECK2-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !6
	// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !6
	// CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK2: omp.inner.for.body:			// CHECK2: omp.inner.for.body:
	// CHECK2-NEXT: call void @__kmpc_push_proc_bind(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 4)			// CHECK2-NEXT: call void @__kmpc_push_proc_bind(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 4), !llvm.access.group !6
	// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !6
	// CHECK2-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64			// CHECK2-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
	// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !6
	// CHECK2-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK2-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK2-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..1 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]])			// CHECK2-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..1 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !6
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK2: omp.inner.for.inc:			// CHECK2: omp.inner.for.inc:
	// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !6
	// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !6
	// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]			// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
	// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]
	// CHECK2: omp.inner.for.end:			// CHECK2: omp.inner.for.end:
	// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK2: omp.loop.exit:			// CHECK2: omp.loop.exit:
	// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])			// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
	// CHECK2-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK2-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK2-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0			// CHECK2-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
	// CHECK2-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK2-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK2: .omp.final.then:			// CHECK2: .omp.final.then:
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	// CHECK2-NEXT: br label [[COND_END]]			// CHECK2-NEXT: br label [[COND_END]]
	// CHECK2: cond.end:			// CHECK2: cond.end:
	// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 999, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]			// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 999, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
	// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK2-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK2: omp.inner.for.cond:			// CHECK2: omp.inner.for.cond:
	// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK2-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK2-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !10
	// CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK2: omp.inner.for.body:			// CHECK2: omp.inner.for.body:
	// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10
	// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK2: omp.body.continue:			// CHECK2: omp.body.continue:
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK2: omp.inner.for.inc:			// CHECK2: omp.inner.for.inc:
	// CHECK2-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]
	// CHECK2: omp.inner.for.end:			// CHECK2: omp.inner.for.end:
	// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK2: omp.loop.exit:			// CHECK2: omp.loop.exit:
	// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])			// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
	// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK2-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK2-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK2-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK2-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK2: .omp.final.then:			// CHECK2: .omp.final.then:
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	// CHECK2-NEXT: br label [[COND_END]]			// CHECK2-NEXT: br label [[COND_END]]
	// CHECK2: cond.end:			// CHECK2: cond.end:
	// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 999, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]			// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 999, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
	// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK2-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK2-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK2-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK2: omp.inner.for.cond:			// CHECK2: omp.inner.for.cond:
	// CHECK2-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15
	// CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK2: omp.inner.for.body:			// CHECK2: omp.inner.for.body:
	// CHECK2-NEXT: call void @__kmpc_push_proc_bind(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 3)			// CHECK2-NEXT: call void @__kmpc_push_proc_bind(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 3), !llvm.access.group !15
	// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !15
	// CHECK2-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64			// CHECK2-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
	// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15
	// CHECK2-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK2-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK2-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..3 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]])			// CHECK2-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..3 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !15
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK2: omp.inner.for.inc:			// CHECK2: omp.inner.for.inc:
	// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !15
	// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]			// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
	// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]]
	// CHECK2: omp.inner.for.end:			// CHECK2: omp.inner.for.end:
	// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK2: omp.loop.exit:			// CHECK2: omp.loop.exit:
	// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])			// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
	// CHECK2-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK2-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK2-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0			// CHECK2-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
	// CHECK2-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK2-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK2: .omp.final.then:			// CHECK2: .omp.final.then:
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	// CHECK2-NEXT: br label [[COND_END]]			// CHECK2-NEXT: br label [[COND_END]]
	// CHECK2: cond.end:			// CHECK2: cond.end:
	// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 999, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]			// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 999, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
	// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK2-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK2: omp.inner.for.cond:			// CHECK2: omp.inner.for.cond:
	// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK2-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK2-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !18
	// CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK2: omp.inner.for.body:			// CHECK2: omp.inner.for.body:
	// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !18
	// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK2: omp.body.continue:			// CHECK2: omp.body.continue:
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK2: omp.inner.for.inc:			// CHECK2: omp.inner.for.inc:
	// CHECK2-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]
	// CHECK2: omp.inner.for.end:			// CHECK2: omp.inner.for.end:
	// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK2: omp.loop.exit:			// CHECK2: omp.loop.exit:
	// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])			// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
	// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK2-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK2-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK2-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK2-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK2: .omp.final.then:			// CHECK2: .omp.final.then:
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	// CHECK2-NEXT: br label [[COND_END]]			// CHECK2-NEXT: br label [[COND_END]]
	// CHECK2: cond.end:			// CHECK2: cond.end:
	// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 999, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]			// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 999, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
	// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK2-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK2-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK2-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK2: omp.inner.for.cond:			// CHECK2: omp.inner.for.cond:
	// CHECK2-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !21
	// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !21
	// CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK2: omp.inner.for.body:			// CHECK2: omp.inner.for.body:
	// CHECK2-NEXT: call void @__kmpc_push_proc_bind(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 2)			// CHECK2-NEXT: call void @__kmpc_push_proc_bind(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 2), !llvm.access.group !21
	// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !21
	// CHECK2-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64			// CHECK2-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
	// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !21
	// CHECK2-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK2-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK2-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..5 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]])			// CHECK2-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..5 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !21
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK2: omp.inner.for.inc:			// CHECK2: omp.inner.for.inc:
	// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !21
	// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !21
	// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]			// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
	// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]]
	// CHECK2: omp.inner.for.end:			// CHECK2: omp.inner.for.end:
	// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK2: omp.loop.exit:			// CHECK2: omp.loop.exit:
	// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])			// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
	// CHECK2-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK2-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK2-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0			// CHECK2-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
	// CHECK2-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK2-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK2: .omp.final.then:			// CHECK2: .omp.final.then:
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	// CHECK2-NEXT: br label [[COND_END]]			// CHECK2-NEXT: br label [[COND_END]]
	// CHECK2: cond.end:			// CHECK2: cond.end:
	// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 999, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]			// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 999, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
	// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK2-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK2: omp.inner.for.cond:			// CHECK2: omp.inner.for.cond:
	// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !24
	// CHECK2-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK2-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !24
	// CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK2: omp.inner.for.body:			// CHECK2: omp.inner.for.body:
	// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !24
	// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !24
	// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK2: omp.body.continue:			// CHECK2: omp.body.continue:
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK2: omp.inner.for.inc:			// CHECK2: omp.inner.for.inc:
	// CHECK2-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !24
	// CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]]
	// CHECK2: omp.inner.for.end:			// CHECK2: omp.inner.for.end:
	// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK2: omp.loop.exit:			// CHECK2: omp.loop.exit:
	// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])			// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
	// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK2-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK2-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK2-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK2-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK2: .omp.final.then:			// CHECK2: .omp.final.then:
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clang/test/OpenMP/distribute_private_codegen.cpp

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	//			//
	//			//
	// CHECK12-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg			// CHECK12-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
	// CHECK12-SAME: () #[[ATTR6:[0-9]+]] {			// CHECK12-SAME: () #[[ATTR6:[0-9]+]] {
	// CHECK12-NEXT: entry:			// CHECK12-NEXT: entry:
	// CHECK12-NEXT: call void @__tgt_register_requires(i64 1)			// CHECK12-NEXT: call void @__tgt_register_requires(i64 1)
	// CHECK12-NEXT: ret void			// CHECK12-NEXT: ret void
	//			//
	//
	No newline at end of file

clang/test/OpenMP/distribute_simd_firstprivate_codegen.cpp

This file is larger than 256 KB, so syntax highlighting is disabled by default.

	Show First 20 Lines • Show All 256 Lines • ▼ Show 20 Lines
	// CHECK1-NEXT: br label [[COND_END]]			// CHECK1-NEXT: br label [[COND_END]]
	// CHECK1: cond.end:			// CHECK1: cond.end:
	// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ]			// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ]
	// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK1-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK1-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK1-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK1: omp.inner.for.cond:			// CHECK1: omp.inner.for.cond:
	// CHECK1-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !4
	// CHECK1-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK1-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !4
	// CHECK1-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]]			// CHECK1-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]]
	// CHECK1-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK1-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK1: omp.inner.for.body:			// CHECK1: omp.inner.for.body:
	// CHECK1-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !4
	// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1			// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1
	// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !4
	// CHECK1-NEXT: [[TMP18:%.]] = load double, double [[G3]], align 8			// CHECK1-NEXT: [[TMP18:%.]] = load double, double [[G3]], align 8, !llvm.access.group !4
	// CHECK1-NEXT: [[ADD9:%.*]] = fadd double [[TMP18]], 1.000000e+00			// CHECK1-NEXT: [[ADD9:%.*]] = fadd double [[TMP18]], 1.000000e+00
	// CHECK1-NEXT: store double [[ADD9]], double* [[G3]], align 8			// CHECK1-NEXT: store double [[ADD9]], double* [[G3]], align 8, !llvm.access.group !4
	// CHECK1-NEXT: [[TMP19:%.]] = load double, double** [[_TMP5]], align 8			// CHECK1-NEXT: [[TMP19:%.]] = load double, double** [[_TMP5]], align 8, !llvm.access.group !4
	// CHECK1-NEXT: [[TMP20:%.]] = load volatile double, double [[TMP19]], align 8			// CHECK1-NEXT: [[TMP20:%.]] = load volatile double, double [[TMP19]], align 8, !llvm.access.group !4
	// CHECK1-NEXT: [[ADD10:%.*]] = fadd double [[TMP20]], 1.000000e+00			// CHECK1-NEXT: [[ADD10:%.*]] = fadd double [[TMP20]], 1.000000e+00
	// CHECK1-NEXT: store volatile double [[ADD10]], double* [[TMP19]], align 8			// CHECK1-NEXT: store volatile double [[ADD10]], double* [[TMP19]], align 8, !llvm.access.group !4
	// CHECK1-NEXT: [[TMP21:%.]] = load i32, i32 [[SVAR6]], align 4			// CHECK1-NEXT: [[TMP21:%.]] = load i32, i32 [[SVAR6]], align 4, !llvm.access.group !4
	// CHECK1-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP21]], 3			// CHECK1-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP21]], 3
	// CHECK1-NEXT: store i32 [[ADD11]], i32* [[SVAR6]], align 4			// CHECK1-NEXT: store i32 [[ADD11]], i32* [[SVAR6]], align 4, !llvm.access.group !4
	// CHECK1-NEXT: [[TMP22:%.]] = load float, float [[SFVAR7]], align 4			// CHECK1-NEXT: [[TMP22:%.]] = load float, float [[SFVAR7]], align 4, !llvm.access.group !4
	// CHECK1-NEXT: [[CONV:%.*]] = fpext float [[TMP22]] to double			// CHECK1-NEXT: [[CONV:%.*]] = fpext float [[TMP22]] to double
	// CHECK1-NEXT: [[ADD12:%.*]] = fadd double [[CONV]], 4.000000e+00			// CHECK1-NEXT: [[ADD12:%.*]] = fadd double [[CONV]], 4.000000e+00
	// CHECK1-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float			// CHECK1-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float
	// CHECK1-NEXT: store float [[CONV13]], float* [[SFVAR7]], align 4			// CHECK1-NEXT: store float [[CONV13]], float* [[SFVAR7]], align 4, !llvm.access.group !4
	// CHECK1-NEXT: [[TMP23:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 0			// CHECK1-NEXT: [[TMP23:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 0
	// CHECK1-NEXT: store double* [[G3]], double** [[TMP23]], align 8			// CHECK1-NEXT: store double* [[G3]], double** [[TMP23]], align 8, !llvm.access.group !4
	// CHECK1-NEXT: [[TMP24:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 1			// CHECK1-NEXT: [[TMP24:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 1
	// CHECK1-NEXT: [[TMP25:%.]] = load double, double** [[_TMP5]], align 8			// CHECK1-NEXT: [[TMP25:%.]] = load double, double** [[_TMP5]], align 8, !llvm.access.group !4
	// CHECK1-NEXT: store double* [[TMP25]], double** [[TMP24]], align 8			// CHECK1-NEXT: store double* [[TMP25]], double** [[TMP24]], align 8, !llvm.access.group !4
	// CHECK1-NEXT: [[TMP26:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 2			// CHECK1-NEXT: [[TMP26:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 2
	// CHECK1-NEXT: store i32* [[SVAR6]], i32** [[TMP26]], align 8			// CHECK1-NEXT: store i32* [[SVAR6]], i32** [[TMP26]], align 8, !llvm.access.group !4
	// CHECK1-NEXT: [[TMP27:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 3			// CHECK1-NEXT: [[TMP27:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 3
	// CHECK1-NEXT: store float* [[SFVAR7]], float** [[TMP27]], align 8			// CHECK1-NEXT: store float* [[SFVAR7]], float** [[TMP27]], align 8, !llvm.access.group !4
	// CHECK1-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(32) [[REF_TMP]])			// CHECK1-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(32) [[REF_TMP]]), !llvm.access.group !4
	// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK1: omp.body.continue:			// CHECK1: omp.body.continue:
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK1: omp.inner.for.inc:			// CHECK1: omp.inner.for.inc:
	// CHECK1-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !4
	// CHECK1-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP28]], 1			// CHECK1-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP28]], 1
	// CHECK1-NEXT: store i32 [[ADD14]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[ADD14]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]
	// CHECK1: omp.inner.for.end:			// CHECK1: omp.inner.for.end:
	// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK1: omp.loop.exit:			// CHECK1: omp.loop.exit:
	// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP11]])			// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP11]])
	// CHECK1-NEXT: [[TMP29:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK1-NEXT: [[TMP29:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK1-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0			// CHECK1-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0
	// CHECK1-NEXT: br i1 [[TMP30]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK1-NEXT: br i1 [[TMP30]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK1: .omp.final.then:			// CHECK1: .omp.final.then:
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	// CHECK2-NEXT: br label [[COND_END]]			// CHECK2-NEXT: br label [[COND_END]]
	// CHECK2: cond.end:			// CHECK2: cond.end:
	// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ]			// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ]
	// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK2-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK2-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK2-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK2: omp.inner.for.cond:			// CHECK2: omp.inner.for.cond:
	// CHECK2-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !4
	// CHECK2-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK2-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !4
	// CHECK2-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]]			// CHECK2-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]]
	// CHECK2-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK2-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK2: omp.inner.for.body:			// CHECK2: omp.inner.for.body:
	// CHECK2-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !4
	// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1			// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1
	// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !4
	// CHECK2-NEXT: [[TMP18:%.]] = load double, double [[G3]], align 8			// CHECK2-NEXT: [[TMP18:%.]] = load double, double [[G3]], align 8, !llvm.access.group !4
	// CHECK2-NEXT: [[ADD9:%.*]] = fadd double [[TMP18]], 1.000000e+00			// CHECK2-NEXT: [[ADD9:%.*]] = fadd double [[TMP18]], 1.000000e+00
	// CHECK2-NEXT: store double [[ADD9]], double* [[G3]], align 8			// CHECK2-NEXT: store double [[ADD9]], double* [[G3]], align 8, !llvm.access.group !4
	// CHECK2-NEXT: [[TMP19:%.]] = load double, double** [[_TMP5]], align 8			// CHECK2-NEXT: [[TMP19:%.]] = load double, double** [[_TMP5]], align 8, !llvm.access.group !4
	// CHECK2-NEXT: [[TMP20:%.]] = load volatile double, double [[TMP19]], align 8			// CHECK2-NEXT: [[TMP20:%.]] = load volatile double, double [[TMP19]], align 8, !llvm.access.group !4
	// CHECK2-NEXT: [[ADD10:%.*]] = fadd double [[TMP20]], 1.000000e+00			// CHECK2-NEXT: [[ADD10:%.*]] = fadd double [[TMP20]], 1.000000e+00
	// CHECK2-NEXT: store volatile double [[ADD10]], double* [[TMP19]], align 8			// CHECK2-NEXT: store volatile double [[ADD10]], double* [[TMP19]], align 8, !llvm.access.group !4
	// CHECK2-NEXT: [[TMP21:%.]] = load i32, i32 [[SVAR6]], align 4			// CHECK2-NEXT: [[TMP21:%.]] = load i32, i32 [[SVAR6]], align 4, !llvm.access.group !4
	// CHECK2-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP21]], 3			// CHECK2-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP21]], 3
	// CHECK2-NEXT: store i32 [[ADD11]], i32* [[SVAR6]], align 4			// CHECK2-NEXT: store i32 [[ADD11]], i32* [[SVAR6]], align 4, !llvm.access.group !4
	// CHECK2-NEXT: [[TMP22:%.]] = load float, float [[SFVAR7]], align 4			// CHECK2-NEXT: [[TMP22:%.]] = load float, float [[SFVAR7]], align 4, !llvm.access.group !4
	// CHECK2-NEXT: [[CONV:%.*]] = fpext float [[TMP22]] to double			// CHECK2-NEXT: [[CONV:%.*]] = fpext float [[TMP22]] to double
	// CHECK2-NEXT: [[ADD12:%.*]] = fadd double [[CONV]], 4.000000e+00			// CHECK2-NEXT: [[ADD12:%.*]] = fadd double [[CONV]], 4.000000e+00
	// CHECK2-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float			// CHECK2-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float
	// CHECK2-NEXT: store float [[CONV13]], float* [[SFVAR7]], align 4			// CHECK2-NEXT: store float [[CONV13]], float* [[SFVAR7]], align 4, !llvm.access.group !4
	// CHECK2-NEXT: [[TMP23:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 0			// CHECK2-NEXT: [[TMP23:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 0
	// CHECK2-NEXT: store double* [[G3]], double** [[TMP23]], align 8			// CHECK2-NEXT: store double* [[G3]], double** [[TMP23]], align 8, !llvm.access.group !4
	// CHECK2-NEXT: [[TMP24:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 1			// CHECK2-NEXT: [[TMP24:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 1
	// CHECK2-NEXT: [[TMP25:%.]] = load double, double** [[_TMP5]], align 8			// CHECK2-NEXT: [[TMP25:%.]] = load double, double** [[_TMP5]], align 8, !llvm.access.group !4
	// CHECK2-NEXT: store double* [[TMP25]], double** [[TMP24]], align 8			// CHECK2-NEXT: store double* [[TMP25]], double** [[TMP24]], align 8, !llvm.access.group !4
	// CHECK2-NEXT: [[TMP26:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 2			// CHECK2-NEXT: [[TMP26:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 2
	// CHECK2-NEXT: store i32* [[SVAR6]], i32** [[TMP26]], align 8			// CHECK2-NEXT: store i32* [[SVAR6]], i32** [[TMP26]], align 8, !llvm.access.group !4
	// CHECK2-NEXT: [[TMP27:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 3			// CHECK2-NEXT: [[TMP27:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 3
	// CHECK2-NEXT: store float* [[SFVAR7]], float** [[TMP27]], align 8			// CHECK2-NEXT: store float* [[SFVAR7]], float** [[TMP27]], align 8, !llvm.access.group !4
	// CHECK2-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(32) [[REF_TMP]])			// CHECK2-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(32) [[REF_TMP]]), !llvm.access.group !4
	// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK2: omp.body.continue:			// CHECK2: omp.body.continue:
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK2: omp.inner.for.inc:			// CHECK2: omp.inner.for.inc:
	// CHECK2-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !4
	// CHECK2-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP28]], 1			// CHECK2-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP28]], 1
	// CHECK2-NEXT: store i32 [[ADD14]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[ADD14]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]
	// CHECK2: omp.inner.for.end:			// CHECK2: omp.inner.for.end:
	// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK2: omp.loop.exit:			// CHECK2: omp.loop.exit:
	// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP11]])			// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP11]])
	// CHECK2-NEXT: [[TMP29:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK2-NEXT: [[TMP29:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK2-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0			// CHECK2-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0
	// CHECK2-NEXT: br i1 [[TMP30]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK2-NEXT: br i1 [[TMP30]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK2: .omp.final.then:			// CHECK2: .omp.final.then:
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	// CHECK3-NEXT: br label [[COND_END]]			// CHECK3-NEXT: br label [[COND_END]]
	// CHECK3: cond.end:			// CHECK3: cond.end:
	// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ]			// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ]
	// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK3-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK3-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK3-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4			// CHECK3-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK3: omp.inner.for.cond:			// CHECK3: omp.inner.for.cond:
	// CHECK3-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK3-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK3-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK3-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !5
	// CHECK3-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]]			// CHECK3-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]]
	// CHECK3-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK3-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK3: omp.inner.for.body:			// CHECK3: omp.inner.for.body:
	// CHECK3-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK3-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1			// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1
	// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !5
	// CHECK3-NEXT: [[TMP18:%.]] = load double, double [[G3]], align 8			// CHECK3-NEXT: [[TMP18:%.]] = load double, double [[G3]], align 8, !llvm.access.group !5
	// CHECK3-NEXT: [[ADD9:%.*]] = fadd double [[TMP18]], 1.000000e+00			// CHECK3-NEXT: [[ADD9:%.*]] = fadd double [[TMP18]], 1.000000e+00
	// CHECK3-NEXT: store double [[ADD9]], double* [[G3]], align 8			// CHECK3-NEXT: store double [[ADD9]], double* [[G3]], align 8, !llvm.access.group !5
	// CHECK3-NEXT: [[TMP19:%.]] = load double, double** [[_TMP5]], align 4			// CHECK3-NEXT: [[TMP19:%.]] = load double, double** [[_TMP5]], align 4, !llvm.access.group !5
	// CHECK3-NEXT: [[TMP20:%.]] = load volatile double, double [[TMP19]], align 4			// CHECK3-NEXT: [[TMP20:%.]] = load volatile double, double [[TMP19]], align 4, !llvm.access.group !5
	// CHECK3-NEXT: [[ADD10:%.*]] = fadd double [[TMP20]], 1.000000e+00			// CHECK3-NEXT: [[ADD10:%.*]] = fadd double [[TMP20]], 1.000000e+00
	// CHECK3-NEXT: store volatile double [[ADD10]], double* [[TMP19]], align 4			// CHECK3-NEXT: store volatile double [[ADD10]], double* [[TMP19]], align 4, !llvm.access.group !5
	// CHECK3-NEXT: [[TMP21:%.]] = load i32, i32 [[SVAR6]], align 4			// CHECK3-NEXT: [[TMP21:%.]] = load i32, i32 [[SVAR6]], align 4, !llvm.access.group !5
	// CHECK3-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP21]], 3			// CHECK3-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP21]], 3
	// CHECK3-NEXT: store i32 [[ADD11]], i32* [[SVAR6]], align 4			// CHECK3-NEXT: store i32 [[ADD11]], i32* [[SVAR6]], align 4, !llvm.access.group !5
	// CHECK3-NEXT: [[TMP22:%.]] = load float, float [[SFVAR7]], align 4			// CHECK3-NEXT: [[TMP22:%.]] = load float, float [[SFVAR7]], align 4, !llvm.access.group !5
	// CHECK3-NEXT: [[CONV:%.*]] = fpext float [[TMP22]] to double			// CHECK3-NEXT: [[CONV:%.*]] = fpext float [[TMP22]] to double
	// CHECK3-NEXT: [[ADD12:%.*]] = fadd double [[CONV]], 4.000000e+00			// CHECK3-NEXT: [[ADD12:%.*]] = fadd double [[CONV]], 4.000000e+00
	// CHECK3-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float			// CHECK3-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float
	// CHECK3-NEXT: store float [[CONV13]], float* [[SFVAR7]], align 4			// CHECK3-NEXT: store float [[CONV13]], float* [[SFVAR7]], align 4, !llvm.access.group !5
	// CHECK3-NEXT: [[TMP23:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 0			// CHECK3-NEXT: [[TMP23:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 0
	// CHECK3-NEXT: store double* [[G3]], double** [[TMP23]], align 4			// CHECK3-NEXT: store double* [[G3]], double** [[TMP23]], align 4, !llvm.access.group !5
	// CHECK3-NEXT: [[TMP24:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 1			// CHECK3-NEXT: [[TMP24:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 1
	// CHECK3-NEXT: [[TMP25:%.]] = load double, double** [[_TMP5]], align 4			// CHECK3-NEXT: [[TMP25:%.]] = load double, double** [[_TMP5]], align 4, !llvm.access.group !5
	// CHECK3-NEXT: store double* [[TMP25]], double** [[TMP24]], align 4			// CHECK3-NEXT: store double* [[TMP25]], double** [[TMP24]], align 4, !llvm.access.group !5
	// CHECK3-NEXT: [[TMP26:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 2			// CHECK3-NEXT: [[TMP26:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 2
	// CHECK3-NEXT: store i32* [[SVAR6]], i32** [[TMP26]], align 4			// CHECK3-NEXT: store i32* [[SVAR6]], i32** [[TMP26]], align 4, !llvm.access.group !5
	// CHECK3-NEXT: [[TMP27:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 3			// CHECK3-NEXT: [[TMP27:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 3
	// CHECK3-NEXT: store float* [[SFVAR7]], float** [[TMP27]], align 4			// CHECK3-NEXT: store float* [[SFVAR7]], float** [[TMP27]], align 4, !llvm.access.group !5
	// CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 4 dereferenceable(16) [[REF_TMP]])			// CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 4 dereferenceable(16) [[REF_TMP]]), !llvm.access.group !5
	// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK3: omp.body.continue:			// CHECK3: omp.body.continue:
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK3: omp.inner.for.inc:			// CHECK3: omp.inner.for.inc:
	// CHECK3-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK3-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK3-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP28]], 1			// CHECK3-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP28]], 1
	// CHECK3-NEXT: store i32 [[ADD14]], i32* [[DOTOMP_IV]], align 4			// CHECK3-NEXT: store i32 [[ADD14]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]
	// CHECK3: omp.inner.for.end:			// CHECK3: omp.inner.for.end:
	// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK3: omp.loop.exit:			// CHECK3: omp.loop.exit:
	// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP11]])			// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP11]])
	// CHECK3-NEXT: [[TMP29:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK3-NEXT: [[TMP29:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK3-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0			// CHECK3-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0
	// CHECK3-NEXT: br i1 [[TMP30]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK3-NEXT: br i1 [[TMP30]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK3: .omp.final.then:			// CHECK3: .omp.final.then:
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	// CHECK4-NEXT: br label [[COND_END]]			// CHECK4-NEXT: br label [[COND_END]]
	// CHECK4: cond.end:			// CHECK4: cond.end:
	// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ]			// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ]
	// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK4-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK4-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK4-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4			// CHECK4-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK4: omp.inner.for.cond:			// CHECK4: omp.inner.for.cond:
	// CHECK4-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK4-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK4-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK4-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !5
	// CHECK4-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]]			// CHECK4-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]]
	// CHECK4-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK4-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK4: omp.inner.for.body:			// CHECK4: omp.inner.for.body:
	// CHECK4-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK4-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1			// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1
	// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !5
	// CHECK4-NEXT: [[TMP18:%.]] = load double, double [[G3]], align 8			// CHECK4-NEXT: [[TMP18:%.]] = load double, double [[G3]], align 8, !llvm.access.group !5
	// CHECK4-NEXT: [[ADD9:%.*]] = fadd double [[TMP18]], 1.000000e+00			// CHECK4-NEXT: [[ADD9:%.*]] = fadd double [[TMP18]], 1.000000e+00
	// CHECK4-NEXT: store double [[ADD9]], double* [[G3]], align 8			// CHECK4-NEXT: store double [[ADD9]], double* [[G3]], align 8, !llvm.access.group !5
	// CHECK4-NEXT: [[TMP19:%.]] = load double, double** [[_TMP5]], align 4			// CHECK4-NEXT: [[TMP19:%.]] = load double, double** [[_TMP5]], align 4, !llvm.access.group !5
	// CHECK4-NEXT: [[TMP20:%.]] = load volatile double, double [[TMP19]], align 4			// CHECK4-NEXT: [[TMP20:%.]] = load volatile double, double [[TMP19]], align 4, !llvm.access.group !5
	// CHECK4-NEXT: [[ADD10:%.*]] = fadd double [[TMP20]], 1.000000e+00			// CHECK4-NEXT: [[ADD10:%.*]] = fadd double [[TMP20]], 1.000000e+00
	// CHECK4-NEXT: store volatile double [[ADD10]], double* [[TMP19]], align 4			// CHECK4-NEXT: store volatile double [[ADD10]], double* [[TMP19]], align 4, !llvm.access.group !5
	// CHECK4-NEXT: [[TMP21:%.]] = load i32, i32 [[SVAR6]], align 4			// CHECK4-NEXT: [[TMP21:%.]] = load i32, i32 [[SVAR6]], align 4, !llvm.access.group !5
	// CHECK4-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP21]], 3			// CHECK4-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP21]], 3
	// CHECK4-NEXT: store i32 [[ADD11]], i32* [[SVAR6]], align 4			// CHECK4-NEXT: store i32 [[ADD11]], i32* [[SVAR6]], align 4, !llvm.access.group !5
	// CHECK4-NEXT: [[TMP22:%.]] = load float, float [[SFVAR7]], align 4			// CHECK4-NEXT: [[TMP22:%.]] = load float, float [[SFVAR7]], align 4, !llvm.access.group !5
	// CHECK4-NEXT: [[CONV:%.*]] = fpext float [[TMP22]] to double			// CHECK4-NEXT: [[CONV:%.*]] = fpext float [[TMP22]] to double
	// CHECK4-NEXT: [[ADD12:%.*]] = fadd double [[CONV]], 4.000000e+00			// CHECK4-NEXT: [[ADD12:%.*]] = fadd double [[CONV]], 4.000000e+00
	// CHECK4-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float			// CHECK4-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float
	// CHECK4-NEXT: store float [[CONV13]], float* [[SFVAR7]], align 4			// CHECK4-NEXT: store float [[CONV13]], float* [[SFVAR7]], align 4, !llvm.access.group !5
	// CHECK4-NEXT: [[TMP23:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 0			// CHECK4-NEXT: [[TMP23:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 0
	// CHECK4-NEXT: store double* [[G3]], double** [[TMP23]], align 4			// CHECK4-NEXT: store double* [[G3]], double** [[TMP23]], align 4, !llvm.access.group !5
	// CHECK4-NEXT: [[TMP24:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 1			// CHECK4-NEXT: [[TMP24:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 1
	// CHECK4-NEXT: [[TMP25:%.]] = load double, double** [[_TMP5]], align 4			// CHECK4-NEXT: [[TMP25:%.]] = load double, double** [[_TMP5]], align 4, !llvm.access.group !5
	// CHECK4-NEXT: store double* [[TMP25]], double** [[TMP24]], align 4			// CHECK4-NEXT: store double* [[TMP25]], double** [[TMP24]], align 4, !llvm.access.group !5
	// CHECK4-NEXT: [[TMP26:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 2			// CHECK4-NEXT: [[TMP26:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 2
	// CHECK4-NEXT: store i32* [[SVAR6]], i32** [[TMP26]], align 4			// CHECK4-NEXT: store i32* [[SVAR6]], i32** [[TMP26]], align 4, !llvm.access.group !5
	// CHECK4-NEXT: [[TMP27:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 3			// CHECK4-NEXT: [[TMP27:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 3
	// CHECK4-NEXT: store float* [[SFVAR7]], float** [[TMP27]], align 4			// CHECK4-NEXT: store float* [[SFVAR7]], float** [[TMP27]], align 4, !llvm.access.group !5
	// CHECK4-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 4 dereferenceable(16) [[REF_TMP]])			// CHECK4-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 4 dereferenceable(16) [[REF_TMP]]), !llvm.access.group !5
	// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK4: omp.body.continue:			// CHECK4: omp.body.continue:
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK4: omp.inner.for.inc:			// CHECK4: omp.inner.for.inc:
	// CHECK4-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK4-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK4-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP28]], 1			// CHECK4-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP28]], 1
	// CHECK4-NEXT: store i32 [[ADD14]], i32* [[DOTOMP_IV]], align 4			// CHECK4-NEXT: store i32 [[ADD14]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]
	// CHECK4: omp.inner.for.end:			// CHECK4: omp.inner.for.end:
	// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK4: omp.loop.exit:			// CHECK4: omp.loop.exit:
	// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP11]])			// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP11]])
	// CHECK4-NEXT: [[TMP29:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK4-NEXT: [[TMP29:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK4-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0			// CHECK4-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0
	// CHECK4-NEXT: br i1 [[TMP30]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK4-NEXT: br i1 [[TMP30]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK4: .omp.final.then:			// CHECK4: .omp.final.then:
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	// CHECK9-NEXT: br label [[COND_END]]			// CHECK9-NEXT: br label [[COND_END]]
	// CHECK9: cond.end:			// CHECK9: cond.end:
	// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP20]], [[COND_FALSE]] ]			// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP20]], [[COND_FALSE]] ]
	// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK9-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK9-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK9-NEXT: store i32 [[TMP21]], i32* [[DOTOMP_IV]], align 4			// CHECK9-NEXT: store i32 [[TMP21]], i32* [[DOTOMP_IV]], align 4
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK9: omp.inner.for.cond:			// CHECK9: omp.inner.for.cond:
	// CHECK9-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK9-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK9-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !5
	// CHECK9-NEXT: [[CMP10:%.*]] = icmp sle i32 [[TMP22]], [[TMP23]]			// CHECK9-NEXT: [[CMP10:%.*]] = icmp sle i32 [[TMP22]], [[TMP23]]
	// CHECK9-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]			// CHECK9-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]
	// CHECK9: omp.inner.for.cond.cleanup:			// CHECK9: omp.inner.for.cond.cleanup:
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_END:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
	// CHECK9: omp.inner.for.body:			// CHECK9: omp.inner.for.body:
	// CHECK9-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP24]], 1			// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP24]], 1
	// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !5
	// CHECK9-NEXT: [[TMP25:%.]] = load i32, i32 [[T_VAR3]], align 4			// CHECK9-NEXT: [[TMP25:%.]] = load i32, i32 [[T_VAR3]], align 4, !llvm.access.group !5
	// CHECK9-NEXT: [[TMP26:%.]] = load i32, i32 [[I]], align 4			// CHECK9-NEXT: [[TMP26:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !5
	// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP26]] to i64			// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP26]] to i64
	// CHECK9-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC4]], i64 0, i64 [[IDXPROM]]			// CHECK9-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC4]], i64 0, i64 [[IDXPROM]]
	// CHECK9-NEXT: store i32 [[TMP25]], i32* [[ARRAYIDX]], align 4			// CHECK9-NEXT: store i32 [[TMP25]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !5
	// CHECK9-NEXT: [[TMP27:%.]] = load %struct.S, %struct.S** [[_TMP8]], align 8			// CHECK9-NEXT: [[TMP27:%.]] = load %struct.S, %struct.S** [[_TMP8]], align 8, !llvm.access.group !5
	// CHECK9-NEXT: [[TMP28:%.]] = load i32, i32 [[I]], align 4			// CHECK9-NEXT: [[TMP28:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !5
	// CHECK9-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP28]] to i64			// CHECK9-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP28]] to i64
	// CHECK9-NEXT: [[ARRAYIDX12:%.]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S] [[S_ARR5]], i64 0, i64 [[IDXPROM11]]			// CHECK9-NEXT: [[ARRAYIDX12:%.]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S] [[S_ARR5]], i64 0, i64 [[IDXPROM11]]
	// CHECK9-NEXT: [[TMP29:%.]] = bitcast %struct.S [[ARRAYIDX12]] to i8*			// CHECK9-NEXT: [[TMP29:%.]] = bitcast %struct.S [[ARRAYIDX12]] to i8*
	// CHECK9-NEXT: [[TMP30:%.]] = bitcast %struct.S [[TMP27]] to i8*			// CHECK9-NEXT: [[TMP30:%.]] = bitcast %struct.S [[TMP27]] to i8*
	// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP29]], i8* align 4 [[TMP30]], i64 4, i1 false)			// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP29]], i8* align 4 [[TMP30]], i64 4, i1 false), !llvm.access.group !5
	// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK9: omp.body.continue:			// CHECK9: omp.body.continue:
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK9: omp.inner.for.inc:			// CHECK9: omp.inner.for.inc:
	// CHECK9-NEXT: [[TMP31:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP31:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK9-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP31]], 1			// CHECK9-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP31]], 1
	// CHECK9-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_IV]], align 4			// CHECK9-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]
	// CHECK9: omp.inner.for.end:			// CHECK9: omp.inner.for.end:
	// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK9: omp.loop.exit:			// CHECK9: omp.loop.exit:
	// CHECK9-NEXT: [[TMP32:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK9-NEXT: [[TMP32:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK9-NEXT: [[TMP33:%.]] = load i32, i32 [[TMP32]], align 4			// CHECK9-NEXT: [[TMP33:%.]] = load i32, i32 [[TMP32]], align 4
	// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP33]])			// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP33]])
	// CHECK9-NEXT: [[TMP34:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK9-NEXT: [[TMP34:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK9-NEXT: [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0			// CHECK9-NEXT: [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0
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	// CHECK9-NEXT: br label [[COND_END]]			// CHECK9-NEXT: br label [[COND_END]]
	// CHECK9: cond.end:			// CHECK9: cond.end:
	// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP18]], [[COND_FALSE]] ]			// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP18]], [[COND_FALSE]] ]
	// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK9-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK9-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK9-NEXT: store i32 [[TMP19]], i32* [[DOTOMP_IV]], align 4			// CHECK9-NEXT: store i32 [[TMP19]], i32* [[DOTOMP_IV]], align 4
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK9: omp.inner.for.cond:			// CHECK9: omp.inner.for.cond:
	// CHECK9-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11
	// CHECK9-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK9-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !11
	// CHECK9-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP20]], [[TMP21]]			// CHECK9-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP20]], [[TMP21]]
	// CHECK9-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]			// CHECK9-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]
	// CHECK9: omp.inner.for.cond.cleanup:			// CHECK9: omp.inner.for.cond.cleanup:
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_END:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
	// CHECK9: omp.inner.for.body:			// CHECK9: omp.inner.for.body:
	// CHECK9-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11
	// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP22]], 1			// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP22]], 1
	// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11
	// CHECK9-NEXT: [[TMP23:%.]] = load i32, i32 [[T_VAR3]], align 4			// CHECK9-NEXT: [[TMP23:%.]] = load i32, i32 [[T_VAR3]], align 4, !llvm.access.group !11
	// CHECK9-NEXT: [[TMP24:%.]] = load i32, i32 [[I]], align 4			// CHECK9-NEXT: [[TMP24:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !11
	// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP24]] to i64			// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP24]] to i64
	// CHECK9-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC4]], i64 0, i64 [[IDXPROM]]			// CHECK9-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC4]], i64 0, i64 [[IDXPROM]]
	// CHECK9-NEXT: store i32 [[TMP23]], i32* [[ARRAYIDX]], align 4			// CHECK9-NEXT: store i32 [[TMP23]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !11
	// CHECK9-NEXT: [[TMP25:%.]] = load %struct.S.0, %struct.S.0** [[_TMP8]], align 8			// CHECK9-NEXT: [[TMP25:%.]] = load %struct.S.0, %struct.S.0** [[_TMP8]], align 8, !llvm.access.group !11
	// CHECK9-NEXT: [[TMP26:%.]] = load i32, i32 [[I]], align 4			// CHECK9-NEXT: [[TMP26:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !11
	// CHECK9-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP26]] to i64			// CHECK9-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP26]] to i64
	// CHECK9-NEXT: [[ARRAYIDX11:%.]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0] [[S_ARR5]], i64 0, i64 [[IDXPROM10]]			// CHECK9-NEXT: [[ARRAYIDX11:%.]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0] [[S_ARR5]], i64 0, i64 [[IDXPROM10]]
	// CHECK9-NEXT: [[TMP27:%.]] = bitcast %struct.S.0 [[ARRAYIDX11]] to i8*			// CHECK9-NEXT: [[TMP27:%.]] = bitcast %struct.S.0 [[ARRAYIDX11]] to i8*
	// CHECK9-NEXT: [[TMP28:%.]] = bitcast %struct.S.0 [[TMP25]] to i8*			// CHECK9-NEXT: [[TMP28:%.]] = bitcast %struct.S.0 [[TMP25]] to i8*
	// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP27]], i8* align 4 [[TMP28]], i64 4, i1 false)			// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP27]], i8* align 4 [[TMP28]], i64 4, i1 false), !llvm.access.group !11
	// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK9: omp.body.continue:			// CHECK9: omp.body.continue:
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK9: omp.inner.for.inc:			// CHECK9: omp.inner.for.inc:
	// CHECK9-NEXT: [[TMP29:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP29:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11
	// CHECK9-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP29]], 1			// CHECK9-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP29]], 1
	// CHECK9-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4			// CHECK9-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]
	// CHECK9: omp.inner.for.end:			// CHECK9: omp.inner.for.end:
	// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK9: omp.loop.exit:			// CHECK9: omp.loop.exit:
	// CHECK9-NEXT: [[TMP30:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK9-NEXT: [[TMP30:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK9-NEXT: [[TMP31:%.]] = load i32, i32 [[TMP30]], align 4			// CHECK9-NEXT: [[TMP31:%.]] = load i32, i32 [[TMP30]], align 4
	// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP31]])			// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP31]])
	// CHECK9-NEXT: [[TMP32:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK9-NEXT: [[TMP32:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK9-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0			// CHECK9-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0
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	// CHECK10-NEXT: br label [[COND_END]]			// CHECK10-NEXT: br label [[COND_END]]
	// CHECK10: cond.end:			// CHECK10: cond.end:
	// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP20]], [[COND_FALSE]] ]			// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP20]], [[COND_FALSE]] ]
	// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK10-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK10-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK10-NEXT: store i32 [[TMP21]], i32* [[DOTOMP_IV]], align 4			// CHECK10-NEXT: store i32 [[TMP21]], i32* [[DOTOMP_IV]], align 4
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK10: omp.inner.for.cond:			// CHECK10: omp.inner.for.cond:
	// CHECK10-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK10-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK10-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !5
	// CHECK10-NEXT: [[CMP10:%.*]] = icmp sle i32 [[TMP22]], [[TMP23]]			// CHECK10-NEXT: [[CMP10:%.*]] = icmp sle i32 [[TMP22]], [[TMP23]]
	// CHECK10-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]			// CHECK10-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]
	// CHECK10: omp.inner.for.cond.cleanup:			// CHECK10: omp.inner.for.cond.cleanup:
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_END:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
	// CHECK10: omp.inner.for.body:			// CHECK10: omp.inner.for.body:
	// CHECK10-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP24]], 1			// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP24]], 1
	// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !5
	// CHECK10-NEXT: [[TMP25:%.]] = load i32, i32 [[T_VAR3]], align 4			// CHECK10-NEXT: [[TMP25:%.]] = load i32, i32 [[T_VAR3]], align 4, !llvm.access.group !5
	// CHECK10-NEXT: [[TMP26:%.]] = load i32, i32 [[I]], align 4			// CHECK10-NEXT: [[TMP26:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !5
	// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP26]] to i64			// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP26]] to i64
	// CHECK10-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC4]], i64 0, i64 [[IDXPROM]]			// CHECK10-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC4]], i64 0, i64 [[IDXPROM]]
	// CHECK10-NEXT: store i32 [[TMP25]], i32* [[ARRAYIDX]], align 4			// CHECK10-NEXT: store i32 [[TMP25]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !5
	// CHECK10-NEXT: [[TMP27:%.]] = load %struct.S, %struct.S** [[_TMP8]], align 8			// CHECK10-NEXT: [[TMP27:%.]] = load %struct.S, %struct.S** [[_TMP8]], align 8, !llvm.access.group !5
	// CHECK10-NEXT: [[TMP28:%.]] = load i32, i32 [[I]], align 4			// CHECK10-NEXT: [[TMP28:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !5
	// CHECK10-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP28]] to i64			// CHECK10-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP28]] to i64
	// CHECK10-NEXT: [[ARRAYIDX12:%.]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S] [[S_ARR5]], i64 0, i64 [[IDXPROM11]]			// CHECK10-NEXT: [[ARRAYIDX12:%.]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S] [[S_ARR5]], i64 0, i64 [[IDXPROM11]]
	// CHECK10-NEXT: [[TMP29:%.]] = bitcast %struct.S [[ARRAYIDX12]] to i8*			// CHECK10-NEXT: [[TMP29:%.]] = bitcast %struct.S [[ARRAYIDX12]] to i8*
	// CHECK10-NEXT: [[TMP30:%.]] = bitcast %struct.S [[TMP27]] to i8*			// CHECK10-NEXT: [[TMP30:%.]] = bitcast %struct.S [[TMP27]] to i8*
	// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP29]], i8* align 4 [[TMP30]], i64 4, i1 false)			// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP29]], i8* align 4 [[TMP30]], i64 4, i1 false), !llvm.access.group !5
	// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK10: omp.body.continue:			// CHECK10: omp.body.continue:
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK10: omp.inner.for.inc:			// CHECK10: omp.inner.for.inc:
	// CHECK10-NEXT: [[TMP31:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP31:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK10-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP31]], 1			// CHECK10-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP31]], 1
	// CHECK10-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_IV]], align 4			// CHECK10-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]
	// CHECK10: omp.inner.for.end:			// CHECK10: omp.inner.for.end:
	// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK10: omp.loop.exit:			// CHECK10: omp.loop.exit:
	// CHECK10-NEXT: [[TMP32:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK10-NEXT: [[TMP32:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK10-NEXT: [[TMP33:%.]] = load i32, i32 [[TMP32]], align 4			// CHECK10-NEXT: [[TMP33:%.]] = load i32, i32 [[TMP32]], align 4
	// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP33]])			// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP33]])
	// CHECK10-NEXT: [[TMP34:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK10-NEXT: [[TMP34:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK10-NEXT: [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0			// CHECK10-NEXT: [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0
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	// CHECK10-NEXT: br label [[COND_END]]			// CHECK10-NEXT: br label [[COND_END]]
	// CHECK10: cond.end:			// CHECK10: cond.end:
	// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP18]], [[COND_FALSE]] ]			// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP18]], [[COND_FALSE]] ]
	// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK10-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK10-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK10-NEXT: store i32 [[TMP19]], i32* [[DOTOMP_IV]], align 4			// CHECK10-NEXT: store i32 [[TMP19]], i32* [[DOTOMP_IV]], align 4
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK10: omp.inner.for.cond:			// CHECK10: omp.inner.for.cond:
	// CHECK10-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11
	// CHECK10-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK10-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !11
	// CHECK10-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP20]], [[TMP21]]			// CHECK10-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP20]], [[TMP21]]
	// CHECK10-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]			// CHECK10-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]
	// CHECK10: omp.inner.for.cond.cleanup:			// CHECK10: omp.inner.for.cond.cleanup:
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_END:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
	// CHECK10: omp.inner.for.body:			// CHECK10: omp.inner.for.body:
	// CHECK10-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11
	// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP22]], 1			// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP22]], 1
	// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11
	// CHECK10-NEXT: [[TMP23:%.]] = load i32, i32 [[T_VAR3]], align 4			// CHECK10-NEXT: [[TMP23:%.]] = load i32, i32 [[T_VAR3]], align 4, !llvm.access.group !11
	// CHECK10-NEXT: [[TMP24:%.]] = load i32, i32 [[I]], align 4			// CHECK10-NEXT: [[TMP24:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !11
	// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP24]] to i64			// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP24]] to i64
	// CHECK10-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC4]], i64 0, i64 [[IDXPROM]]			// CHECK10-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC4]], i64 0, i64 [[IDXPROM]]
	// CHECK10-NEXT: store i32 [[TMP23]], i32* [[ARRAYIDX]], align 4			// CHECK10-NEXT: store i32 [[TMP23]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !11
	// CHECK10-NEXT: [[TMP25:%.]] = load %struct.S.0, %struct.S.0** [[_TMP8]], align 8			// CHECK10-NEXT: [[TMP25:%.]] = load %struct.S.0, %struct.S.0** [[_TMP8]], align 8, !llvm.access.group !11
	// CHECK10-NEXT: [[TMP26:%.]] = load i32, i32 [[I]], align 4			// CHECK10-NEXT: [[TMP26:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !11
	// CHECK10-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP26]] to i64			// CHECK10-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP26]] to i64
	// CHECK10-NEXT: [[ARRAYIDX11:%.]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0] [[S_ARR5]], i64 0, i64 [[IDXPROM10]]			// CHECK10-NEXT: [[ARRAYIDX11:%.]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0] [[S_ARR5]], i64 0, i64 [[IDXPROM10]]
	// CHECK10-NEXT: [[TMP27:%.]] = bitcast %struct.S.0 [[ARRAYIDX11]] to i8*			// CHECK10-NEXT: [[TMP27:%.]] = bitcast %struct.S.0 [[ARRAYIDX11]] to i8*
	// CHECK10-NEXT: [[TMP28:%.]] = bitcast %struct.S.0 [[TMP25]] to i8*			// CHECK10-NEXT: [[TMP28:%.]] = bitcast %struct.S.0 [[TMP25]] to i8*
	// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP27]], i8* align 4 [[TMP28]], i64 4, i1 false)			// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP27]], i8* align 4 [[TMP28]], i64 4, i1 false), !llvm.access.group !11
	// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK10: omp.body.continue:			// CHECK10: omp.body.continue:
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK10: omp.inner.for.inc:			// CHECK10: omp.inner.for.inc:
	// CHECK10-NEXT: [[TMP29:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP29:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11
	// CHECK10-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP29]], 1			// CHECK10-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP29]], 1
	// CHECK10-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4			// CHECK10-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]
	// CHECK10: omp.inner.for.end:			// CHECK10: omp.inner.for.end:
	// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK10: omp.loop.exit:			// CHECK10: omp.loop.exit:
	// CHECK10-NEXT: [[TMP30:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK10-NEXT: [[TMP30:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK10-NEXT: [[TMP31:%.]] = load i32, i32 [[TMP30]], align 4			// CHECK10-NEXT: [[TMP31:%.]] = load i32, i32 [[TMP30]], align 4
	// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP31]])			// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP31]])
	// CHECK10-NEXT: [[TMP32:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK10-NEXT: [[TMP32:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK10-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0			// CHECK10-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0
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	// CHECK11-NEXT: br label [[COND_END]]			// CHECK11-NEXT: br label [[COND_END]]
	// CHECK11: cond.end:			// CHECK11: cond.end:
	// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP20]], [[COND_FALSE]] ]			// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP20]], [[COND_FALSE]] ]
	// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK11-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK11-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK11-NEXT: store i32 [[TMP21]], i32* [[DOTOMP_IV]], align 4			// CHECK11-NEXT: store i32 [[TMP21]], i32* [[DOTOMP_IV]], align 4
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK11: omp.inner.for.cond:			// CHECK11: omp.inner.for.cond:
	// CHECK11-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK11-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !6
	// CHECK11-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK11-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !6
	// CHECK11-NEXT: [[CMP10:%.*]] = icmp sle i32 [[TMP22]], [[TMP23]]			// CHECK11-NEXT: [[CMP10:%.*]] = icmp sle i32 [[TMP22]], [[TMP23]]
	// CHECK11-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]			// CHECK11-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]
	// CHECK11: omp.inner.for.cond.cleanup:			// CHECK11: omp.inner.for.cond.cleanup:
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_END:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
	// CHECK11: omp.inner.for.body:			// CHECK11: omp.inner.for.body:
	// CHECK11-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK11-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !6
	// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP24]], 1			// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP24]], 1
	// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !6
	// CHECK11-NEXT: [[TMP25:%.]] = load i32, i32 [[T_VAR3]], align 4			// CHECK11-NEXT: [[TMP25:%.]] = load i32, i32 [[T_VAR3]], align 4, !llvm.access.group !6
	// CHECK11-NEXT: [[TMP26:%.]] = load i32, i32 [[I]], align 4			// CHECK11-NEXT: [[TMP26:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !6
	// CHECK11-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC4]], i32 0, i32 [[TMP26]]			// CHECK11-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC4]], i32 0, i32 [[TMP26]]
	// CHECK11-NEXT: store i32 [[TMP25]], i32* [[ARRAYIDX]], align 4			// CHECK11-NEXT: store i32 [[TMP25]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !6
	// CHECK11-NEXT: [[TMP27:%.]] = load %struct.S, %struct.S** [[_TMP8]], align 4			// CHECK11-NEXT: [[TMP27:%.]] = load %struct.S, %struct.S** [[_TMP8]], align 4, !llvm.access.group !6
	// CHECK11-NEXT: [[TMP28:%.]] = load i32, i32 [[I]], align 4			// CHECK11-NEXT: [[TMP28:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !6
	// CHECK11-NEXT: [[ARRAYIDX11:%.]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S] [[S_ARR5]], i32 0, i32 [[TMP28]]			// CHECK11-NEXT: [[ARRAYIDX11:%.]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S] [[S_ARR5]], i32 0, i32 [[TMP28]]
	// CHECK11-NEXT: [[TMP29:%.]] = bitcast %struct.S [[ARRAYIDX11]] to i8*			// CHECK11-NEXT: [[TMP29:%.]] = bitcast %struct.S [[ARRAYIDX11]] to i8*
	// CHECK11-NEXT: [[TMP30:%.]] = bitcast %struct.S [[TMP27]] to i8*			// CHECK11-NEXT: [[TMP30:%.]] = bitcast %struct.S [[TMP27]] to i8*
	// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP29]], i8* align 4 [[TMP30]], i32 4, i1 false)			// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP29]], i8* align 4 [[TMP30]], i32 4, i1 false), !llvm.access.group !6
	// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK11: omp.body.continue:			// CHECK11: omp.body.continue:
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK11: omp.inner.for.inc:			// CHECK11: omp.inner.for.inc:
	// CHECK11-NEXT: [[TMP31:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK11-NEXT: [[TMP31:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !6
	// CHECK11-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP31]], 1			// CHECK11-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP31]], 1
	// CHECK11-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4			// CHECK11-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]
	// CHECK11: omp.inner.for.end:			// CHECK11: omp.inner.for.end:
	// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK11: omp.loop.exit:			// CHECK11: omp.loop.exit:
	// CHECK11-NEXT: [[TMP32:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4			// CHECK11-NEXT: [[TMP32:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4
	// CHECK11-NEXT: [[TMP33:%.]] = load i32, i32 [[TMP32]], align 4			// CHECK11-NEXT: [[TMP33:%.]] = load i32, i32 [[TMP32]], align 4
	// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP33]])			// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP33]])
	// CHECK11-NEXT: [[TMP34:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK11-NEXT: [[TMP34:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK11-NEXT: [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0			// CHECK11-NEXT: [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0
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	// CHECK11-NEXT: br label [[COND_END]]			// CHECK11-NEXT: br label [[COND_END]]
	// CHECK11: cond.end:			// CHECK11: cond.end:
	// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP18]], [[COND_FALSE]] ]			// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP18]], [[COND_FALSE]] ]
	// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK11-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK11-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK11-NEXT: store i32 [[TMP19]], i32* [[DOTOMP_IV]], align 4			// CHECK11-NEXT: store i32 [[TMP19]], i32* [[DOTOMP_IV]], align 4
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK11: omp.inner.for.cond:			// CHECK11: omp.inner.for.cond:
	// CHECK11-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK11-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12
	// CHECK11-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK11-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !12
	// CHECK11-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP20]], [[TMP21]]			// CHECK11-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP20]], [[TMP21]]
	// CHECK11-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]			// CHECK11-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]
	// CHECK11: omp.inner.for.cond.cleanup:			// CHECK11: omp.inner.for.cond.cleanup:
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_END:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
	// CHECK11: omp.inner.for.body:			// CHECK11: omp.inner.for.body:
	// CHECK11-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK11-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12
	// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP22]], 1			// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP22]], 1
	// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !12
	// CHECK11-NEXT: [[TMP23:%.]] = load i32, i32 [[T_VAR3]], align 4			// CHECK11-NEXT: [[TMP23:%.]] = load i32, i32 [[T_VAR3]], align 4, !llvm.access.group !12
	// CHECK11-NEXT: [[TMP24:%.]] = load i32, i32 [[I]], align 4			// CHECK11-NEXT: [[TMP24:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !12
	// CHECK11-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC4]], i32 0, i32 [[TMP24]]			// CHECK11-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC4]], i32 0, i32 [[TMP24]]
	// CHECK11-NEXT: store i32 [[TMP23]], i32* [[ARRAYIDX]], align 4			// CHECK11-NEXT: store i32 [[TMP23]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !12
	// CHECK11-NEXT: [[TMP25:%.]] = load %struct.S.0, %struct.S.0** [[_TMP8]], align 4			// CHECK11-NEXT: [[TMP25:%.]] = load %struct.S.0, %struct.S.0** [[_TMP8]], align 4, !llvm.access.group !12
	// CHECK11-NEXT: [[TMP26:%.]] = load i32, i32 [[I]], align 4			// CHECK11-NEXT: [[TMP26:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !12
	// CHECK11-NEXT: [[ARRAYIDX10:%.]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0] [[S_ARR5]], i32 0, i32 [[TMP26]]			// CHECK11-NEXT: [[ARRAYIDX10:%.]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0] [[S_ARR5]], i32 0, i32 [[TMP26]]
	// CHECK11-NEXT: [[TMP27:%.]] = bitcast %struct.S.0 [[ARRAYIDX10]] to i8*			// CHECK11-NEXT: [[TMP27:%.]] = bitcast %struct.S.0 [[ARRAYIDX10]] to i8*
	// CHECK11-NEXT: [[TMP28:%.]] = bitcast %struct.S.0 [[TMP25]] to i8*			// CHECK11-NEXT: [[TMP28:%.]] = bitcast %struct.S.0 [[TMP25]] to i8*
	// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP27]], i8* align 4 [[TMP28]], i32 4, i1 false)			// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP27]], i8* align 4 [[TMP28]], i32 4, i1 false), !llvm.access.group !12
	// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK11: omp.body.continue:			// CHECK11: omp.body.continue:
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK11: omp.inner.for.inc:			// CHECK11: omp.inner.for.inc:
	// CHECK11-NEXT: [[TMP29:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK11-NEXT: [[TMP29:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12
	// CHECK11-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP29]], 1			// CHECK11-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP29]], 1
	// CHECK11-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4			// CHECK11-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]
	// CHECK11: omp.inner.for.end:			// CHECK11: omp.inner.for.end:
	// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK11: omp.loop.exit:			// CHECK11: omp.loop.exit:
	// CHECK11-NEXT: [[TMP30:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4			// CHECK11-NEXT: [[TMP30:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4
	// CHECK11-NEXT: [[TMP31:%.]] = load i32, i32 [[TMP30]], align 4			// CHECK11-NEXT: [[TMP31:%.]] = load i32, i32 [[TMP30]], align 4
	// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP31]])			// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP31]])
	// CHECK11-NEXT: [[TMP32:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK11-NEXT: [[TMP32:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK11-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0			// CHECK11-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0
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	// CHECK12-NEXT: br label [[COND_END]]			// CHECK12-NEXT: br label [[COND_END]]
	// CHECK12: cond.end:			// CHECK12: cond.end:
	// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP20]], [[COND_FALSE]] ]			// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP20]], [[COND_FALSE]] ]
	// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK12-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK12-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK12-NEXT: store i32 [[TMP21]], i32* [[DOTOMP_IV]], align 4			// CHECK12-NEXT: store i32 [[TMP21]], i32* [[DOTOMP_IV]], align 4
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK12: omp.inner.for.cond:			// CHECK12: omp.inner.for.cond:
	// CHECK12-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK12-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !6
	// CHECK12-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK12-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !6
	// CHECK12-NEXT: [[CMP10:%.*]] = icmp sle i32 [[TMP22]], [[TMP23]]			// CHECK12-NEXT: [[CMP10:%.*]] = icmp sle i32 [[TMP22]], [[TMP23]]
	// CHECK12-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]			// CHECK12-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]
	// CHECK12: omp.inner.for.cond.cleanup:			// CHECK12: omp.inner.for.cond.cleanup:
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_END:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
	// CHECK12: omp.inner.for.body:			// CHECK12: omp.inner.for.body:
	// CHECK12-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK12-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !6
	// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP24]], 1			// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP24]], 1
	// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !6
	// CHECK12-NEXT: [[TMP25:%.]] = load i32, i32 [[T_VAR3]], align 4			// CHECK12-NEXT: [[TMP25:%.]] = load i32, i32 [[T_VAR3]], align 4, !llvm.access.group !6
	// CHECK12-NEXT: [[TMP26:%.]] = load i32, i32 [[I]], align 4			// CHECK12-NEXT: [[TMP26:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !6
	// CHECK12-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC4]], i32 0, i32 [[TMP26]]			// CHECK12-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC4]], i32 0, i32 [[TMP26]]
	// CHECK12-NEXT: store i32 [[TMP25]], i32* [[ARRAYIDX]], align 4			// CHECK12-NEXT: store i32 [[TMP25]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !6
	// CHECK12-NEXT: [[TMP27:%.]] = load %struct.S, %struct.S** [[_TMP8]], align 4			// CHECK12-NEXT: [[TMP27:%.]] = load %struct.S, %struct.S** [[_TMP8]], align 4, !llvm.access.group !6
	// CHECK12-NEXT: [[TMP28:%.]] = load i32, i32 [[I]], align 4			// CHECK12-NEXT: [[TMP28:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !6
	// CHECK12-NEXT: [[ARRAYIDX11:%.]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S] [[S_ARR5]], i32 0, i32 [[TMP28]]			// CHECK12-NEXT: [[ARRAYIDX11:%.]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S] [[S_ARR5]], i32 0, i32 [[TMP28]]
	// CHECK12-NEXT: [[TMP29:%.]] = bitcast %struct.S [[ARRAYIDX11]] to i8*			// CHECK12-NEXT: [[TMP29:%.]] = bitcast %struct.S [[ARRAYIDX11]] to i8*
	// CHECK12-NEXT: [[TMP30:%.]] = bitcast %struct.S [[TMP27]] to i8*			// CHECK12-NEXT: [[TMP30:%.]] = bitcast %struct.S [[TMP27]] to i8*
	// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP29]], i8* align 4 [[TMP30]], i32 4, i1 false)			// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP29]], i8* align 4 [[TMP30]], i32 4, i1 false), !llvm.access.group !6
	// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK12: omp.body.continue:			// CHECK12: omp.body.continue:
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK12: omp.inner.for.inc:			// CHECK12: omp.inner.for.inc:
	// CHECK12-NEXT: [[TMP31:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK12-NEXT: [[TMP31:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !6
	// CHECK12-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP31]], 1			// CHECK12-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP31]], 1
	// CHECK12-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4			// CHECK12-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]
	// CHECK12: omp.inner.for.end:			// CHECK12: omp.inner.for.end:
	// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK12: omp.loop.exit:			// CHECK12: omp.loop.exit:
	// CHECK12-NEXT: [[TMP32:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4			// CHECK12-NEXT: [[TMP32:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4
	// CHECK12-NEXT: [[TMP33:%.]] = load i32, i32 [[TMP32]], align 4			// CHECK12-NEXT: [[TMP33:%.]] = load i32, i32 [[TMP32]], align 4
	// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP33]])			// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP33]])
	// CHECK12-NEXT: [[TMP34:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK12-NEXT: [[TMP34:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK12-NEXT: [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0			// CHECK12-NEXT: [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0
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	// CHECK12-NEXT: br label [[COND_END]]			// CHECK12-NEXT: br label [[COND_END]]
	// CHECK12: cond.end:			// CHECK12: cond.end:
	// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP18]], [[COND_FALSE]] ]			// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP18]], [[COND_FALSE]] ]
	// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK12-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK12-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK12-NEXT: store i32 [[TMP19]], i32* [[DOTOMP_IV]], align 4			// CHECK12-NEXT: store i32 [[TMP19]], i32* [[DOTOMP_IV]], align 4
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK12: omp.inner.for.cond:			// CHECK12: omp.inner.for.cond:
	// CHECK12-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK12-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12
	// CHECK12-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK12-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !12
	// CHECK12-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP20]], [[TMP21]]			// CHECK12-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP20]], [[TMP21]]
	// CHECK12-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]			// CHECK12-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]
	// CHECK12: omp.inner.for.cond.cleanup:			// CHECK12: omp.inner.for.cond.cleanup:
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_END:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
	// CHECK12: omp.inner.for.body:			// CHECK12: omp.inner.for.body:
	// CHECK12-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK12-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12
	// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP22]], 1			// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP22]], 1
	// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !12
	// CHECK12-NEXT: [[TMP23:%.]] = load i32, i32 [[T_VAR3]], align 4			// CHECK12-NEXT: [[TMP23:%.]] = load i32, i32 [[T_VAR3]], align 4, !llvm.access.group !12
	// CHECK12-NEXT: [[TMP24:%.]] = load i32, i32 [[I]], align 4			// CHECK12-NEXT: [[TMP24:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !12
	// CHECK12-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC4]], i32 0, i32 [[TMP24]]			// CHECK12-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC4]], i32 0, i32 [[TMP24]]
	// CHECK12-NEXT: store i32 [[TMP23]], i32* [[ARRAYIDX]], align 4			// CHECK12-NEXT: store i32 [[TMP23]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !12
	// CHECK12-NEXT: [[TMP25:%.]] = load %struct.S.0, %struct.S.0** [[_TMP8]], align 4			// CHECK12-NEXT: [[TMP25:%.]] = load %struct.S.0, %struct.S.0** [[_TMP8]], align 4, !llvm.access.group !12
	// CHECK12-NEXT: [[TMP26:%.]] = load i32, i32 [[I]], align 4			// CHECK12-NEXT: [[TMP26:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !12
	// CHECK12-NEXT: [[ARRAYIDX10:%.]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0] [[S_ARR5]], i32 0, i32 [[TMP26]]			// CHECK12-NEXT: [[ARRAYIDX10:%.]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0] [[S_ARR5]], i32 0, i32 [[TMP26]]
	// CHECK12-NEXT: [[TMP27:%.]] = bitcast %struct.S.0 [[ARRAYIDX10]] to i8*			// CHECK12-NEXT: [[TMP27:%.]] = bitcast %struct.S.0 [[ARRAYIDX10]] to i8*
	// CHECK12-NEXT: [[TMP28:%.]] = bitcast %struct.S.0 [[TMP25]] to i8*			// CHECK12-NEXT: [[TMP28:%.]] = bitcast %struct.S.0 [[TMP25]] to i8*
	// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP27]], i8* align 4 [[TMP28]], i32 4, i1 false)			// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP27]], i8* align 4 [[TMP28]], i32 4, i1 false), !llvm.access.group !12
	// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK12: omp.body.continue:			// CHECK12: omp.body.continue:
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK12: omp.inner.for.inc:			// CHECK12: omp.inner.for.inc:
	// CHECK12-NEXT: [[TMP29:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK12-NEXT: [[TMP29:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12
	// CHECK12-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP29]], 1			// CHECK12-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP29]], 1
	// CHECK12-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4			// CHECK12-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]
	// CHECK12: omp.inner.for.end:			// CHECK12: omp.inner.for.end:
	// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK12: omp.loop.exit:			// CHECK12: omp.loop.exit:
	// CHECK12-NEXT: [[TMP30:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4			// CHECK12-NEXT: [[TMP30:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4
	// CHECK12-NEXT: [[TMP31:%.]] = load i32, i32 [[TMP30]], align 4			// CHECK12-NEXT: [[TMP31:%.]] = load i32, i32 [[TMP30]], align 4
	// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP31]])			// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP31]])
	// CHECK12-NEXT: [[TMP32:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK12-NEXT: [[TMP32:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK12-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0			// CHECK12-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0
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clang/test/OpenMP/distribute_simd_lastprivate_codegen.cpp

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	// CHECK1-NEXT: br label [[COND_END]]			// CHECK1-NEXT: br label [[COND_END]]
	// CHECK1: cond.end:			// CHECK1: cond.end:
	// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ]			// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ]
	// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK1-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK1: omp.inner.for.cond:			// CHECK1: omp.inner.for.cond:
	// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !4
	// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !4
	// CHECK1-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]]			// CHECK1-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]]
	// CHECK1-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK1-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK1: omp.inner.for.body:			// CHECK1: omp.inner.for.body:
	// CHECK1-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !4
	// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP13]], 1			// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP13]], 1
	// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !4
	// CHECK1-NEXT: store double 1.000000e+00, double* [[G3]], align 8			// CHECK1-NEXT: store double 1.000000e+00, double* [[G3]], align 8, !llvm.access.group !4
	// CHECK1-NEXT: [[TMP14:%.]] = load double, double** [[_TMP5]], align 8			// CHECK1-NEXT: [[TMP14:%.]] = load double, double** [[_TMP5]], align 8, !llvm.access.group !4
	// CHECK1-NEXT: store volatile double 1.000000e+00, double* [[TMP14]], align 8			// CHECK1-NEXT: store volatile double 1.000000e+00, double* [[TMP14]], align 8, !llvm.access.group !4
	// CHECK1-NEXT: store i32 3, i32* [[SVAR6]], align 4			// CHECK1-NEXT: store i32 3, i32* [[SVAR6]], align 4, !llvm.access.group !4
	// CHECK1-NEXT: store float 4.000000e+00, float* [[SFVAR7]], align 4			// CHECK1-NEXT: store float 4.000000e+00, float* [[SFVAR7]], align 4, !llvm.access.group !4
	// CHECK1-NEXT: [[TMP15:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 0			// CHECK1-NEXT: [[TMP15:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 0
	// CHECK1-NEXT: store double* [[G3]], double** [[TMP15]], align 8			// CHECK1-NEXT: store double* [[G3]], double** [[TMP15]], align 8, !llvm.access.group !4
	// CHECK1-NEXT: [[TMP16:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 1			// CHECK1-NEXT: [[TMP16:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 1
	// CHECK1-NEXT: [[TMP17:%.]] = load double, double** [[_TMP5]], align 8			// CHECK1-NEXT: [[TMP17:%.]] = load double, double** [[_TMP5]], align 8, !llvm.access.group !4
	// CHECK1-NEXT: store double* [[TMP17]], double** [[TMP16]], align 8			// CHECK1-NEXT: store double* [[TMP17]], double** [[TMP16]], align 8, !llvm.access.group !4
	// CHECK1-NEXT: [[TMP18:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 2			// CHECK1-NEXT: [[TMP18:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 2
	// CHECK1-NEXT: store i32* [[SVAR6]], i32** [[TMP18]], align 8			// CHECK1-NEXT: store i32* [[SVAR6]], i32** [[TMP18]], align 8, !llvm.access.group !4
	// CHECK1-NEXT: [[TMP19:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 3			// CHECK1-NEXT: [[TMP19:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 3
	// CHECK1-NEXT: store float* [[SFVAR7]], float** [[TMP19]], align 8			// CHECK1-NEXT: store float* [[SFVAR7]], float** [[TMP19]], align 8, !llvm.access.group !4
	// CHECK1-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(32) [[REF_TMP]])			// CHECK1-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(32) [[REF_TMP]]), !llvm.access.group !4
	// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK1: omp.body.continue:			// CHECK1: omp.body.continue:
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK1: omp.inner.for.inc:			// CHECK1: omp.inner.for.inc:
	// CHECK1-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !4
	// CHECK1-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP20]], 1			// CHECK1-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP20]], 1
	// CHECK1-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]
	// CHECK1: omp.inner.for.end:			// CHECK1: omp.inner.for.end:
	// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK1: omp.loop.exit:			// CHECK1: omp.loop.exit:
	// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP7]])			// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP7]])
	// CHECK1-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK1-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK1-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0			// CHECK1-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0
	// CHECK1-NEXT: br i1 [[TMP22]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK1-NEXT: br i1 [[TMP22]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK1: .omp.final.then:			// CHECK1: .omp.final.then:
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	// CHECK2-NEXT: br label [[COND_END]]			// CHECK2-NEXT: br label [[COND_END]]
	// CHECK2: cond.end:			// CHECK2: cond.end:
	// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ]			// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ]
	// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK2-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK2-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK2-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK2: omp.inner.for.cond:			// CHECK2: omp.inner.for.cond:
	// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !4
	// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !4
	// CHECK2-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]]			// CHECK2-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]]
	// CHECK2-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK2-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK2: omp.inner.for.body:			// CHECK2: omp.inner.for.body:
	// CHECK2-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !4
	// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP13]], 1			// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP13]], 1
	// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !4
	// CHECK2-NEXT: store double 1.000000e+00, double* [[G3]], align 8			// CHECK2-NEXT: store double 1.000000e+00, double* [[G3]], align 8, !llvm.access.group !4
	// CHECK2-NEXT: [[TMP14:%.]] = load double, double** [[_TMP5]], align 8			// CHECK2-NEXT: [[TMP14:%.]] = load double, double** [[_TMP5]], align 8, !llvm.access.group !4
	// CHECK2-NEXT: store volatile double 1.000000e+00, double* [[TMP14]], align 8			// CHECK2-NEXT: store volatile double 1.000000e+00, double* [[TMP14]], align 8, !llvm.access.group !4
	// CHECK2-NEXT: store i32 3, i32* [[SVAR6]], align 4			// CHECK2-NEXT: store i32 3, i32* [[SVAR6]], align 4, !llvm.access.group !4
	// CHECK2-NEXT: store float 4.000000e+00, float* [[SFVAR7]], align 4			// CHECK2-NEXT: store float 4.000000e+00, float* [[SFVAR7]], align 4, !llvm.access.group !4
	// CHECK2-NEXT: [[TMP15:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 0			// CHECK2-NEXT: [[TMP15:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 0
	// CHECK2-NEXT: store double* [[G3]], double** [[TMP15]], align 8			// CHECK2-NEXT: store double* [[G3]], double** [[TMP15]], align 8, !llvm.access.group !4
	// CHECK2-NEXT: [[TMP16:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 1			// CHECK2-NEXT: [[TMP16:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 1
	// CHECK2-NEXT: [[TMP17:%.]] = load double, double** [[_TMP5]], align 8			// CHECK2-NEXT: [[TMP17:%.]] = load double, double** [[_TMP5]], align 8, !llvm.access.group !4
	// CHECK2-NEXT: store double* [[TMP17]], double** [[TMP16]], align 8			// CHECK2-NEXT: store double* [[TMP17]], double** [[TMP16]], align 8, !llvm.access.group !4
	// CHECK2-NEXT: [[TMP18:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 2			// CHECK2-NEXT: [[TMP18:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 2
	// CHECK2-NEXT: store i32* [[SVAR6]], i32** [[TMP18]], align 8			// CHECK2-NEXT: store i32* [[SVAR6]], i32** [[TMP18]], align 8, !llvm.access.group !4
	// CHECK2-NEXT: [[TMP19:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 3			// CHECK2-NEXT: [[TMP19:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 3
	// CHECK2-NEXT: store float* [[SFVAR7]], float** [[TMP19]], align 8			// CHECK2-NEXT: store float* [[SFVAR7]], float** [[TMP19]], align 8, !llvm.access.group !4
	// CHECK2-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(32) [[REF_TMP]])			// CHECK2-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(32) [[REF_TMP]]), !llvm.access.group !4
	// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK2: omp.body.continue:			// CHECK2: omp.body.continue:
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK2: omp.inner.for.inc:			// CHECK2: omp.inner.for.inc:
	// CHECK2-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !4
	// CHECK2-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP20]], 1			// CHECK2-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP20]], 1
	// CHECK2-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]
	// CHECK2: omp.inner.for.end:			// CHECK2: omp.inner.for.end:
	// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK2: omp.loop.exit:			// CHECK2: omp.loop.exit:
	// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP7]])			// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP7]])
	// CHECK2-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK2-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK2-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0			// CHECK2-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0
	// CHECK2-NEXT: br i1 [[TMP22]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK2-NEXT: br i1 [[TMP22]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK2: .omp.final.then:			// CHECK2: .omp.final.then:
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	// CHECK3-NEXT: br label [[COND_END]]			// CHECK3-NEXT: br label [[COND_END]]
	// CHECK3: cond.end:			// CHECK3: cond.end:
	// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ]			// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ]
	// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK3-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK3-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK3-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4			// CHECK3-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK3: omp.inner.for.cond:			// CHECK3: omp.inner.for.cond:
	// CHECK3-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK3-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK3-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK3-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !5
	// CHECK3-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]]			// CHECK3-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]]
	// CHECK3-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK3-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK3: omp.inner.for.body:			// CHECK3: omp.inner.for.body:
	// CHECK3-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK3-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP13]], 1			// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP13]], 1
	// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !5
	// CHECK3-NEXT: store double 1.000000e+00, double* [[G3]], align 8			// CHECK3-NEXT: store double 1.000000e+00, double* [[G3]], align 8, !llvm.access.group !5
	// CHECK3-NEXT: [[TMP14:%.]] = load double, double** [[_TMP5]], align 4			// CHECK3-NEXT: [[TMP14:%.]] = load double, double** [[_TMP5]], align 4, !llvm.access.group !5
	// CHECK3-NEXT: store volatile double 1.000000e+00, double* [[TMP14]], align 4			// CHECK3-NEXT: store volatile double 1.000000e+00, double* [[TMP14]], align 4, !llvm.access.group !5
	// CHECK3-NEXT: store i32 3, i32* [[SVAR6]], align 4			// CHECK3-NEXT: store i32 3, i32* [[SVAR6]], align 4, !llvm.access.group !5
	// CHECK3-NEXT: store float 4.000000e+00, float* [[SFVAR7]], align 4			// CHECK3-NEXT: store float 4.000000e+00, float* [[SFVAR7]], align 4, !llvm.access.group !5
	// CHECK3-NEXT: [[TMP15:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 0			// CHECK3-NEXT: [[TMP15:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 0
	// CHECK3-NEXT: store double* [[G3]], double** [[TMP15]], align 4			// CHECK3-NEXT: store double* [[G3]], double** [[TMP15]], align 4, !llvm.access.group !5
	// CHECK3-NEXT: [[TMP16:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 1			// CHECK3-NEXT: [[TMP16:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 1
	// CHECK3-NEXT: [[TMP17:%.]] = load double, double** [[_TMP5]], align 4			// CHECK3-NEXT: [[TMP17:%.]] = load double, double** [[_TMP5]], align 4, !llvm.access.group !5
	// CHECK3-NEXT: store double* [[TMP17]], double** [[TMP16]], align 4			// CHECK3-NEXT: store double* [[TMP17]], double** [[TMP16]], align 4, !llvm.access.group !5
	// CHECK3-NEXT: [[TMP18:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 2			// CHECK3-NEXT: [[TMP18:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 2
	// CHECK3-NEXT: store i32* [[SVAR6]], i32** [[TMP18]], align 4			// CHECK3-NEXT: store i32* [[SVAR6]], i32** [[TMP18]], align 4, !llvm.access.group !5
	// CHECK3-NEXT: [[TMP19:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 3			// CHECK3-NEXT: [[TMP19:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 3
	// CHECK3-NEXT: store float* [[SFVAR7]], float** [[TMP19]], align 4			// CHECK3-NEXT: store float* [[SFVAR7]], float** [[TMP19]], align 4, !llvm.access.group !5
	// CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 4 dereferenceable(16) [[REF_TMP]])			// CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 4 dereferenceable(16) [[REF_TMP]]), !llvm.access.group !5
	// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK3: omp.body.continue:			// CHECK3: omp.body.continue:
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK3: omp.inner.for.inc:			// CHECK3: omp.inner.for.inc:
	// CHECK3-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK3-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK3-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP20]], 1			// CHECK3-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP20]], 1
	// CHECK3-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4			// CHECK3-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]
	// CHECK3: omp.inner.for.end:			// CHECK3: omp.inner.for.end:
	// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK3: omp.loop.exit:			// CHECK3: omp.loop.exit:
	// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP7]])			// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP7]])
	// CHECK3-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK3-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK3-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0			// CHECK3-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0
	// CHECK3-NEXT: br i1 [[TMP22]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK3-NEXT: br i1 [[TMP22]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK3: .omp.final.then:			// CHECK3: .omp.final.then:
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	// CHECK4-NEXT: br label [[COND_END]]			// CHECK4-NEXT: br label [[COND_END]]
	// CHECK4: cond.end:			// CHECK4: cond.end:
	// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ]			// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ]
	// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK4-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK4-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK4-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4			// CHECK4-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK4: omp.inner.for.cond:			// CHECK4: omp.inner.for.cond:
	// CHECK4-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK4-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK4-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK4-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !5
	// CHECK4-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]]			// CHECK4-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]]
	// CHECK4-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK4-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK4: omp.inner.for.body:			// CHECK4: omp.inner.for.body:
	// CHECK4-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK4-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP13]], 1			// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP13]], 1
	// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !5
	// CHECK4-NEXT: store double 1.000000e+00, double* [[G3]], align 8			// CHECK4-NEXT: store double 1.000000e+00, double* [[G3]], align 8, !llvm.access.group !5
	// CHECK4-NEXT: [[TMP14:%.]] = load double, double** [[_TMP5]], align 4			// CHECK4-NEXT: [[TMP14:%.]] = load double, double** [[_TMP5]], align 4, !llvm.access.group !5
	// CHECK4-NEXT: store volatile double 1.000000e+00, double* [[TMP14]], align 4			// CHECK4-NEXT: store volatile double 1.000000e+00, double* [[TMP14]], align 4, !llvm.access.group !5
	// CHECK4-NEXT: store i32 3, i32* [[SVAR6]], align 4			// CHECK4-NEXT: store i32 3, i32* [[SVAR6]], align 4, !llvm.access.group !5
	// CHECK4-NEXT: store float 4.000000e+00, float* [[SFVAR7]], align 4			// CHECK4-NEXT: store float 4.000000e+00, float* [[SFVAR7]], align 4, !llvm.access.group !5
	// CHECK4-NEXT: [[TMP15:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 0			// CHECK4-NEXT: [[TMP15:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 0
	// CHECK4-NEXT: store double* [[G3]], double** [[TMP15]], align 4			// CHECK4-NEXT: store double* [[G3]], double** [[TMP15]], align 4, !llvm.access.group !5
	// CHECK4-NEXT: [[TMP16:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 1			// CHECK4-NEXT: [[TMP16:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 1
	// CHECK4-NEXT: [[TMP17:%.]] = load double, double** [[_TMP5]], align 4			// CHECK4-NEXT: [[TMP17:%.]] = load double, double** [[_TMP5]], align 4, !llvm.access.group !5
	// CHECK4-NEXT: store double* [[TMP17]], double** [[TMP16]], align 4			// CHECK4-NEXT: store double* [[TMP17]], double** [[TMP16]], align 4, !llvm.access.group !5
	// CHECK4-NEXT: [[TMP18:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 2			// CHECK4-NEXT: [[TMP18:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 2
	// CHECK4-NEXT: store i32* [[SVAR6]], i32** [[TMP18]], align 4			// CHECK4-NEXT: store i32* [[SVAR6]], i32** [[TMP18]], align 4, !llvm.access.group !5
	// CHECK4-NEXT: [[TMP19:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 3			// CHECK4-NEXT: [[TMP19:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 3
	// CHECK4-NEXT: store float* [[SFVAR7]], float** [[TMP19]], align 4			// CHECK4-NEXT: store float* [[SFVAR7]], float** [[TMP19]], align 4, !llvm.access.group !5
	// CHECK4-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 4 dereferenceable(16) [[REF_TMP]])			// CHECK4-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 4 dereferenceable(16) [[REF_TMP]]), !llvm.access.group !5
	// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK4: omp.body.continue:			// CHECK4: omp.body.continue:
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK4: omp.inner.for.inc:			// CHECK4: omp.inner.for.inc:
	// CHECK4-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK4-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK4-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP20]], 1			// CHECK4-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP20]], 1
	// CHECK4-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4			// CHECK4-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]
	// CHECK4: omp.inner.for.end:			// CHECK4: omp.inner.for.end:
	// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK4: omp.loop.exit:			// CHECK4: omp.loop.exit:
	// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP7]])			// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP7]])
	// CHECK4-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK4-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK4-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0			// CHECK4-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0
	// CHECK4-NEXT: br i1 [[TMP22]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK4-NEXT: br i1 [[TMP22]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK4: .omp.final.then:			// CHECK4: .omp.final.then:
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	// CHECK9-NEXT: br label [[COND_END]]			// CHECK9-NEXT: br label [[COND_END]]
	// CHECK9: cond.end:			// CHECK9: cond.end:
	// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ]			// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ]
	// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK9-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK9-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK9-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4			// CHECK9-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK9: omp.inner.for.cond:			// CHECK9: omp.inner.for.cond:
	// CHECK9-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK9-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK9-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !5
	// CHECK9-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]]			// CHECK9-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]]
	// CHECK9-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]			// CHECK9-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]
	// CHECK9: omp.inner.for.cond.cleanup:			// CHECK9: omp.inner.for.cond.cleanup:
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_END:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
	// CHECK9: omp.inner.for.body:			// CHECK9: omp.inner.for.body:
	// CHECK9-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1			// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1
	// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !5
	// CHECK9-NEXT: [[TMP15:%.]] = load i32, i32 [[T_VAR3]], align 4			// CHECK9-NEXT: [[TMP15:%.]] = load i32, i32 [[T_VAR3]], align 4, !llvm.access.group !5
	// CHECK9-NEXT: [[TMP16:%.]] = load i32, i32 [[I]], align 4			// CHECK9-NEXT: [[TMP16:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !5
	// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64			// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64
	// CHECK9-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC4]], i64 0, i64 [[IDXPROM]]			// CHECK9-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC4]], i64 0, i64 [[IDXPROM]]
	// CHECK9-NEXT: store i32 [[TMP15]], i32* [[ARRAYIDX]], align 4			// CHECK9-NEXT: store i32 [[TMP15]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !5
	// CHECK9-NEXT: [[TMP17:%.]] = load %struct.S, %struct.S** [[_TMP7]], align 8			// CHECK9-NEXT: [[TMP17:%.]] = load %struct.S, %struct.S** [[_TMP7]], align 8, !llvm.access.group !5
	// CHECK9-NEXT: [[TMP18:%.]] = load i32, i32 [[I]], align 4			// CHECK9-NEXT: [[TMP18:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !5
	// CHECK9-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP18]] to i64			// CHECK9-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP18]] to i64
	// CHECK9-NEXT: [[ARRAYIDX11:%.]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S] [[S_ARR5]], i64 0, i64 [[IDXPROM10]]			// CHECK9-NEXT: [[ARRAYIDX11:%.]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S] [[S_ARR5]], i64 0, i64 [[IDXPROM10]]
	// CHECK9-NEXT: [[TMP19:%.]] = bitcast %struct.S [[ARRAYIDX11]] to i8*			// CHECK9-NEXT: [[TMP19:%.]] = bitcast %struct.S [[ARRAYIDX11]] to i8*
	// CHECK9-NEXT: [[TMP20:%.]] = bitcast %struct.S [[TMP17]] to i8*			// CHECK9-NEXT: [[TMP20:%.]] = bitcast %struct.S [[TMP17]] to i8*
	// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP19]], i8* align 4 [[TMP20]], i64 4, i1 false)			// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP19]], i8* align 4 [[TMP20]], i64 4, i1 false), !llvm.access.group !5
	// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK9: omp.body.continue:			// CHECK9: omp.body.continue:
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK9: omp.inner.for.inc:			// CHECK9: omp.inner.for.inc:
	// CHECK9-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK9-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP21]], 1			// CHECK9-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP21]], 1
	// CHECK9-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4			// CHECK9-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]
	// CHECK9: omp.inner.for.end:			// CHECK9: omp.inner.for.end:
	// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK9: omp.loop.exit:			// CHECK9: omp.loop.exit:
	// CHECK9-NEXT: [[TMP22:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK9-NEXT: [[TMP22:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK9-NEXT: [[TMP23:%.]] = load i32, i32 [[TMP22]], align 4			// CHECK9-NEXT: [[TMP23:%.]] = load i32, i32 [[TMP22]], align 4
	// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]])			// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]])
	// CHECK9-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK9-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK9-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0			// CHECK9-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0
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	// CHECK9-NEXT: br label [[COND_END]]			// CHECK9-NEXT: br label [[COND_END]]
	// CHECK9: cond.end:			// CHECK9: cond.end:
	// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ]			// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ]
	// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK9-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK9-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK9-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4			// CHECK9-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK9: omp.inner.for.cond:			// CHECK9: omp.inner.for.cond:
	// CHECK9-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11
	// CHECK9-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK9-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !11
	// CHECK9-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]]			// CHECK9-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]]
	// CHECK9-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]			// CHECK9-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]
	// CHECK9: omp.inner.for.cond.cleanup:			// CHECK9: omp.inner.for.cond.cleanup:
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_END:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
	// CHECK9: omp.inner.for.body:			// CHECK9: omp.inner.for.body:
	// CHECK9-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11
	// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP13]], 1			// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP13]], 1
	// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11
	// CHECK9-NEXT: [[TMP14:%.]] = load i32, i32 [[T_VAR3]], align 4			// CHECK9-NEXT: [[TMP14:%.]] = load i32, i32 [[T_VAR3]], align 4, !llvm.access.group !11
	// CHECK9-NEXT: [[TMP15:%.]] = load i32, i32 [[I]], align 4			// CHECK9-NEXT: [[TMP15:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !11
	// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP15]] to i64			// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP15]] to i64
	// CHECK9-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC4]], i64 0, i64 [[IDXPROM]]			// CHECK9-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC4]], i64 0, i64 [[IDXPROM]]
	// CHECK9-NEXT: store i32 [[TMP14]], i32* [[ARRAYIDX]], align 4			// CHECK9-NEXT: store i32 [[TMP14]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !11
	// CHECK9-NEXT: [[TMP16:%.]] = load %struct.S.0, %struct.S.0** [[_TMP7]], align 8			// CHECK9-NEXT: [[TMP16:%.]] = load %struct.S.0, %struct.S.0** [[_TMP7]], align 8, !llvm.access.group !11
	// CHECK9-NEXT: [[TMP17:%.]] = load i32, i32 [[I]], align 4			// CHECK9-NEXT: [[TMP17:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !11
	// CHECK9-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP17]] to i64			// CHECK9-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP17]] to i64
	// CHECK9-NEXT: [[ARRAYIDX10:%.]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0] [[S_ARR5]], i64 0, i64 [[IDXPROM9]]			// CHECK9-NEXT: [[ARRAYIDX10:%.]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0] [[S_ARR5]], i64 0, i64 [[IDXPROM9]]
	// CHECK9-NEXT: [[TMP18:%.]] = bitcast %struct.S.0 [[ARRAYIDX10]] to i8*			// CHECK9-NEXT: [[TMP18:%.]] = bitcast %struct.S.0 [[ARRAYIDX10]] to i8*
	// CHECK9-NEXT: [[TMP19:%.]] = bitcast %struct.S.0 [[TMP16]] to i8*			// CHECK9-NEXT: [[TMP19:%.]] = bitcast %struct.S.0 [[TMP16]] to i8*
	// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP18]], i8* align 4 [[TMP19]], i64 4, i1 false)			// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP18]], i8* align 4 [[TMP19]], i64 4, i1 false), !llvm.access.group !11
	// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK9: omp.body.continue:			// CHECK9: omp.body.continue:
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK9: omp.inner.for.inc:			// CHECK9: omp.inner.for.inc:
	// CHECK9-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11
	// CHECK9-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP20]], 1			// CHECK9-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP20]], 1
	// CHECK9-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4			// CHECK9-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]
	// CHECK9: omp.inner.for.end:			// CHECK9: omp.inner.for.end:
	// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK9: omp.loop.exit:			// CHECK9: omp.loop.exit:
	// CHECK9-NEXT: [[TMP21:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK9-NEXT: [[TMP21:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK9-NEXT: [[TMP22:%.]] = load i32, i32 [[TMP21]], align 4			// CHECK9-NEXT: [[TMP22:%.]] = load i32, i32 [[TMP21]], align 4
	// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]])			// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]])
	// CHECK9-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK9-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK9-NEXT: [[TMP24:%.*]] = icmp ne i32 [[TMP23]], 0			// CHECK9-NEXT: [[TMP24:%.*]] = icmp ne i32 [[TMP23]], 0
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	// CHECK10-NEXT: br label [[COND_END]]			// CHECK10-NEXT: br label [[COND_END]]
	// CHECK10: cond.end:			// CHECK10: cond.end:
	// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ]			// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ]
	// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK10-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK10-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK10-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4			// CHECK10-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK10: omp.inner.for.cond:			// CHECK10: omp.inner.for.cond:
	// CHECK10-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK10-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK10-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !5
	// CHECK10-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]]			// CHECK10-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]]
	// CHECK10-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]			// CHECK10-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]
	// CHECK10: omp.inner.for.cond.cleanup:			// CHECK10: omp.inner.for.cond.cleanup:
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_END:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
	// CHECK10: omp.inner.for.body:			// CHECK10: omp.inner.for.body:
	// CHECK10-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1			// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1
	// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !5
	// CHECK10-NEXT: [[TMP15:%.]] = load i32, i32 [[T_VAR3]], align 4			// CHECK10-NEXT: [[TMP15:%.]] = load i32, i32 [[T_VAR3]], align 4, !llvm.access.group !5
	// CHECK10-NEXT: [[TMP16:%.]] = load i32, i32 [[I]], align 4			// CHECK10-NEXT: [[TMP16:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !5
	// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64			// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64
	// CHECK10-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC4]], i64 0, i64 [[IDXPROM]]			// CHECK10-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC4]], i64 0, i64 [[IDXPROM]]
	// CHECK10-NEXT: store i32 [[TMP15]], i32* [[ARRAYIDX]], align 4			// CHECK10-NEXT: store i32 [[TMP15]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !5
	// CHECK10-NEXT: [[TMP17:%.]] = load %struct.S, %struct.S** [[_TMP7]], align 8			// CHECK10-NEXT: [[TMP17:%.]] = load %struct.S, %struct.S** [[_TMP7]], align 8, !llvm.access.group !5
	// CHECK10-NEXT: [[TMP18:%.]] = load i32, i32 [[I]], align 4			// CHECK10-NEXT: [[TMP18:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !5
	// CHECK10-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP18]] to i64			// CHECK10-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP18]] to i64
	// CHECK10-NEXT: [[ARRAYIDX11:%.]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S] [[S_ARR5]], i64 0, i64 [[IDXPROM10]]			// CHECK10-NEXT: [[ARRAYIDX11:%.]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S] [[S_ARR5]], i64 0, i64 [[IDXPROM10]]
	// CHECK10-NEXT: [[TMP19:%.]] = bitcast %struct.S [[ARRAYIDX11]] to i8*			// CHECK10-NEXT: [[TMP19:%.]] = bitcast %struct.S [[ARRAYIDX11]] to i8*
	// CHECK10-NEXT: [[TMP20:%.]] = bitcast %struct.S [[TMP17]] to i8*			// CHECK10-NEXT: [[TMP20:%.]] = bitcast %struct.S [[TMP17]] to i8*
	// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP19]], i8* align 4 [[TMP20]], i64 4, i1 false)			// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP19]], i8* align 4 [[TMP20]], i64 4, i1 false), !llvm.access.group !5
	// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK10: omp.body.continue:			// CHECK10: omp.body.continue:
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK10: omp.inner.for.inc:			// CHECK10: omp.inner.for.inc:
	// CHECK10-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK10-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP21]], 1			// CHECK10-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP21]], 1
	// CHECK10-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4			// CHECK10-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]
	// CHECK10: omp.inner.for.end:			// CHECK10: omp.inner.for.end:
	// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK10: omp.loop.exit:			// CHECK10: omp.loop.exit:
	// CHECK10-NEXT: [[TMP22:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK10-NEXT: [[TMP22:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK10-NEXT: [[TMP23:%.]] = load i32, i32 [[TMP22]], align 4			// CHECK10-NEXT: [[TMP23:%.]] = load i32, i32 [[TMP22]], align 4
	// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]])			// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]])
	// CHECK10-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK10-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK10-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0			// CHECK10-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0
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	// CHECK10-NEXT: br label [[COND_END]]			// CHECK10-NEXT: br label [[COND_END]]
	// CHECK10: cond.end:			// CHECK10: cond.end:
	// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ]			// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ]
	// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK10-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK10-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK10-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4			// CHECK10-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK10: omp.inner.for.cond:			// CHECK10: omp.inner.for.cond:
	// CHECK10-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11
	// CHECK10-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK10-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !11
	// CHECK10-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]]			// CHECK10-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]]
	// CHECK10-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]			// CHECK10-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]
	// CHECK10: omp.inner.for.cond.cleanup:			// CHECK10: omp.inner.for.cond.cleanup:
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_END:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
	// CHECK10: omp.inner.for.body:			// CHECK10: omp.inner.for.body:
	// CHECK10-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11
	// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP13]], 1			// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP13]], 1
	// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11
	// CHECK10-NEXT: [[TMP14:%.]] = load i32, i32 [[T_VAR3]], align 4			// CHECK10-NEXT: [[TMP14:%.]] = load i32, i32 [[T_VAR3]], align 4, !llvm.access.group !11
	// CHECK10-NEXT: [[TMP15:%.]] = load i32, i32 [[I]], align 4			// CHECK10-NEXT: [[TMP15:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !11
	// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP15]] to i64			// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP15]] to i64
	// CHECK10-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC4]], i64 0, i64 [[IDXPROM]]			// CHECK10-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC4]], i64 0, i64 [[IDXPROM]]
	// CHECK10-NEXT: store i32 [[TMP14]], i32* [[ARRAYIDX]], align 4			// CHECK10-NEXT: store i32 [[TMP14]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !11
	// CHECK10-NEXT: [[TMP16:%.]] = load %struct.S.0, %struct.S.0** [[_TMP7]], align 8			// CHECK10-NEXT: [[TMP16:%.]] = load %struct.S.0, %struct.S.0** [[_TMP7]], align 8, !llvm.access.group !11
	// CHECK10-NEXT: [[TMP17:%.]] = load i32, i32 [[I]], align 4			// CHECK10-NEXT: [[TMP17:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !11
	// CHECK10-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP17]] to i64			// CHECK10-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP17]] to i64
	// CHECK10-NEXT: [[ARRAYIDX10:%.]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0] [[S_ARR5]], i64 0, i64 [[IDXPROM9]]			// CHECK10-NEXT: [[ARRAYIDX10:%.]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0] [[S_ARR5]], i64 0, i64 [[IDXPROM9]]
	// CHECK10-NEXT: [[TMP18:%.]] = bitcast %struct.S.0 [[ARRAYIDX10]] to i8*			// CHECK10-NEXT: [[TMP18:%.]] = bitcast %struct.S.0 [[ARRAYIDX10]] to i8*
	// CHECK10-NEXT: [[TMP19:%.]] = bitcast %struct.S.0 [[TMP16]] to i8*			// CHECK10-NEXT: [[TMP19:%.]] = bitcast %struct.S.0 [[TMP16]] to i8*
	// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP18]], i8* align 4 [[TMP19]], i64 4, i1 false)			// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP18]], i8* align 4 [[TMP19]], i64 4, i1 false), !llvm.access.group !11
	// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK10: omp.body.continue:			// CHECK10: omp.body.continue:
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK10: omp.inner.for.inc:			// CHECK10: omp.inner.for.inc:
	// CHECK10-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11
	// CHECK10-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP20]], 1			// CHECK10-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP20]], 1
	// CHECK10-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4			// CHECK10-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]
	// CHECK10: omp.inner.for.end:			// CHECK10: omp.inner.for.end:
	// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK10: omp.loop.exit:			// CHECK10: omp.loop.exit:
	// CHECK10-NEXT: [[TMP21:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK10-NEXT: [[TMP21:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK10-NEXT: [[TMP22:%.]] = load i32, i32 [[TMP21]], align 4			// CHECK10-NEXT: [[TMP22:%.]] = load i32, i32 [[TMP21]], align 4
	// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]])			// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]])
	// CHECK10-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK10-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK10-NEXT: [[TMP24:%.*]] = icmp ne i32 [[TMP23]], 0			// CHECK10-NEXT: [[TMP24:%.*]] = icmp ne i32 [[TMP23]], 0
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	// CHECK11-NEXT: br label [[COND_END]]			// CHECK11-NEXT: br label [[COND_END]]
	// CHECK11: cond.end:			// CHECK11: cond.end:
	// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ]			// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ]
	// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK11-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK11-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK11-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4			// CHECK11-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK11: omp.inner.for.cond:			// CHECK11: omp.inner.for.cond:
	// CHECK11-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK11-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !6
	// CHECK11-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK11-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !6
	// CHECK11-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]]			// CHECK11-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]]
	// CHECK11-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]			// CHECK11-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]
	// CHECK11: omp.inner.for.cond.cleanup:			// CHECK11: omp.inner.for.cond.cleanup:
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_END:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
	// CHECK11: omp.inner.for.body:			// CHECK11: omp.inner.for.body:
	// CHECK11-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK11-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !6
	// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1			// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1
	// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !6
	// CHECK11-NEXT: [[TMP15:%.]] = load i32, i32 [[T_VAR3]], align 4			// CHECK11-NEXT: [[TMP15:%.]] = load i32, i32 [[T_VAR3]], align 4, !llvm.access.group !6
	// CHECK11-NEXT: [[TMP16:%.]] = load i32, i32 [[I]], align 4			// CHECK11-NEXT: [[TMP16:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !6
	// CHECK11-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC4]], i32 0, i32 [[TMP16]]			// CHECK11-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC4]], i32 0, i32 [[TMP16]]
	// CHECK11-NEXT: store i32 [[TMP15]], i32* [[ARRAYIDX]], align 4			// CHECK11-NEXT: store i32 [[TMP15]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !6
	// CHECK11-NEXT: [[TMP17:%.]] = load %struct.S, %struct.S** [[_TMP7]], align 4			// CHECK11-NEXT: [[TMP17:%.]] = load %struct.S, %struct.S** [[_TMP7]], align 4, !llvm.access.group !6
	// CHECK11-NEXT: [[TMP18:%.]] = load i32, i32 [[I]], align 4			// CHECK11-NEXT: [[TMP18:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !6
	// CHECK11-NEXT: [[ARRAYIDX10:%.]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S] [[S_ARR5]], i32 0, i32 [[TMP18]]			// CHECK11-NEXT: [[ARRAYIDX10:%.]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S] [[S_ARR5]], i32 0, i32 [[TMP18]]
	// CHECK11-NEXT: [[TMP19:%.]] = bitcast %struct.S [[ARRAYIDX10]] to i8*			// CHECK11-NEXT: [[TMP19:%.]] = bitcast %struct.S [[ARRAYIDX10]] to i8*
	// CHECK11-NEXT: [[TMP20:%.]] = bitcast %struct.S [[TMP17]] to i8*			// CHECK11-NEXT: [[TMP20:%.]] = bitcast %struct.S [[TMP17]] to i8*
	// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP19]], i8* align 4 [[TMP20]], i32 4, i1 false)			// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP19]], i8* align 4 [[TMP20]], i32 4, i1 false), !llvm.access.group !6
	// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK11: omp.body.continue:			// CHECK11: omp.body.continue:
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK11: omp.inner.for.inc:			// CHECK11: omp.inner.for.inc:
	// CHECK11-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK11-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !6
	// CHECK11-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP21]], 1			// CHECK11-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP21]], 1
	// CHECK11-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4			// CHECK11-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]
	// CHECK11: omp.inner.for.end:			// CHECK11: omp.inner.for.end:
	// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK11: omp.loop.exit:			// CHECK11: omp.loop.exit:
	// CHECK11-NEXT: [[TMP22:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4			// CHECK11-NEXT: [[TMP22:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4
	// CHECK11-NEXT: [[TMP23:%.]] = load i32, i32 [[TMP22]], align 4			// CHECK11-NEXT: [[TMP23:%.]] = load i32, i32 [[TMP22]], align 4
	// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]])			// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]])
	// CHECK11-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK11-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK11-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0			// CHECK11-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0
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	// CHECK11-NEXT: br label [[COND_END]]			// CHECK11-NEXT: br label [[COND_END]]
	// CHECK11: cond.end:			// CHECK11: cond.end:
	// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ]			// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ]
	// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK11-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK11-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK11-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4			// CHECK11-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK11: omp.inner.for.cond:			// CHECK11: omp.inner.for.cond:
	// CHECK11-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK11-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12
	// CHECK11-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK11-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !12
	// CHECK11-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]]			// CHECK11-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]]
	// CHECK11-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]			// CHECK11-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]
	// CHECK11: omp.inner.for.cond.cleanup:			// CHECK11: omp.inner.for.cond.cleanup:
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_END:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
	// CHECK11: omp.inner.for.body:			// CHECK11: omp.inner.for.body:
	// CHECK11-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK11-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12
	// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP13]], 1			// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP13]], 1
	// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !12
	// CHECK11-NEXT: [[TMP14:%.]] = load i32, i32 [[T_VAR3]], align 4			// CHECK11-NEXT: [[TMP14:%.]] = load i32, i32 [[T_VAR3]], align 4, !llvm.access.group !12
	// CHECK11-NEXT: [[TMP15:%.]] = load i32, i32 [[I]], align 4			// CHECK11-NEXT: [[TMP15:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !12
	// CHECK11-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC4]], i32 0, i32 [[TMP15]]			// CHECK11-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC4]], i32 0, i32 [[TMP15]]
	// CHECK11-NEXT: store i32 [[TMP14]], i32* [[ARRAYIDX]], align 4			// CHECK11-NEXT: store i32 [[TMP14]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !12
	// CHECK11-NEXT: [[TMP16:%.]] = load %struct.S.0, %struct.S.0** [[_TMP7]], align 4			// CHECK11-NEXT: [[TMP16:%.]] = load %struct.S.0, %struct.S.0** [[_TMP7]], align 4, !llvm.access.group !12
	// CHECK11-NEXT: [[TMP17:%.]] = load i32, i32 [[I]], align 4			// CHECK11-NEXT: [[TMP17:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !12
	// CHECK11-NEXT: [[ARRAYIDX9:%.]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0] [[S_ARR5]], i32 0, i32 [[TMP17]]			// CHECK11-NEXT: [[ARRAYIDX9:%.]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0] [[S_ARR5]], i32 0, i32 [[TMP17]]
	// CHECK11-NEXT: [[TMP18:%.]] = bitcast %struct.S.0 [[ARRAYIDX9]] to i8*			// CHECK11-NEXT: [[TMP18:%.]] = bitcast %struct.S.0 [[ARRAYIDX9]] to i8*
	// CHECK11-NEXT: [[TMP19:%.]] = bitcast %struct.S.0 [[TMP16]] to i8*			// CHECK11-NEXT: [[TMP19:%.]] = bitcast %struct.S.0 [[TMP16]] to i8*
	// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP18]], i8* align 4 [[TMP19]], i32 4, i1 false)			// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP18]], i8* align 4 [[TMP19]], i32 4, i1 false), !llvm.access.group !12
	// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK11: omp.body.continue:			// CHECK11: omp.body.continue:
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK11: omp.inner.for.inc:			// CHECK11: omp.inner.for.inc:
	// CHECK11-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK11-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12
	// CHECK11-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP20]], 1			// CHECK11-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP20]], 1
	// CHECK11-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4			// CHECK11-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]
	// CHECK11: omp.inner.for.end:			// CHECK11: omp.inner.for.end:
	// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK11: omp.loop.exit:			// CHECK11: omp.loop.exit:
	// CHECK11-NEXT: [[TMP21:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4			// CHECK11-NEXT: [[TMP21:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4
	// CHECK11-NEXT: [[TMP22:%.]] = load i32, i32 [[TMP21]], align 4			// CHECK11-NEXT: [[TMP22:%.]] = load i32, i32 [[TMP21]], align 4
	// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]])			// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]])
	// CHECK11-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK11-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK11-NEXT: [[TMP24:%.*]] = icmp ne i32 [[TMP23]], 0			// CHECK11-NEXT: [[TMP24:%.*]] = icmp ne i32 [[TMP23]], 0
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	// CHECK12-NEXT: br label [[COND_END]]			// CHECK12-NEXT: br label [[COND_END]]
	// CHECK12: cond.end:			// CHECK12: cond.end:
	// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ]			// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ]
	// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK12-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK12-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK12-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4			// CHECK12-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK12: omp.inner.for.cond:			// CHECK12: omp.inner.for.cond:
	// CHECK12-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK12-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !6
	// CHECK12-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK12-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !6
	// CHECK12-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]]			// CHECK12-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]]
	// CHECK12-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]			// CHECK12-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]
	// CHECK12: omp.inner.for.cond.cleanup:			// CHECK12: omp.inner.for.cond.cleanup:
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_END:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
	// CHECK12: omp.inner.for.body:			// CHECK12: omp.inner.for.body:
	// CHECK12-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK12-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !6
	// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1			// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1
	// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !6
	// CHECK12-NEXT: [[TMP15:%.]] = load i32, i32 [[T_VAR3]], align 4			// CHECK12-NEXT: [[TMP15:%.]] = load i32, i32 [[T_VAR3]], align 4, !llvm.access.group !6
	// CHECK12-NEXT: [[TMP16:%.]] = load i32, i32 [[I]], align 4			// CHECK12-NEXT: [[TMP16:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !6
	// CHECK12-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC4]], i32 0, i32 [[TMP16]]			// CHECK12-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC4]], i32 0, i32 [[TMP16]]
	// CHECK12-NEXT: store i32 [[TMP15]], i32* [[ARRAYIDX]], align 4			// CHECK12-NEXT: store i32 [[TMP15]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !6
	// CHECK12-NEXT: [[TMP17:%.]] = load %struct.S, %struct.S** [[_TMP7]], align 4			// CHECK12-NEXT: [[TMP17:%.]] = load %struct.S, %struct.S** [[_TMP7]], align 4, !llvm.access.group !6
	// CHECK12-NEXT: [[TMP18:%.]] = load i32, i32 [[I]], align 4			// CHECK12-NEXT: [[TMP18:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !6
	// CHECK12-NEXT: [[ARRAYIDX10:%.]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S] [[S_ARR5]], i32 0, i32 [[TMP18]]			// CHECK12-NEXT: [[ARRAYIDX10:%.]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S] [[S_ARR5]], i32 0, i32 [[TMP18]]
	// CHECK12-NEXT: [[TMP19:%.]] = bitcast %struct.S [[ARRAYIDX10]] to i8*			// CHECK12-NEXT: [[TMP19:%.]] = bitcast %struct.S [[ARRAYIDX10]] to i8*
	// CHECK12-NEXT: [[TMP20:%.]] = bitcast %struct.S [[TMP17]] to i8*			// CHECK12-NEXT: [[TMP20:%.]] = bitcast %struct.S [[TMP17]] to i8*
	// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP19]], i8* align 4 [[TMP20]], i32 4, i1 false)			// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP19]], i8* align 4 [[TMP20]], i32 4, i1 false), !llvm.access.group !6
	// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK12: omp.body.continue:			// CHECK12: omp.body.continue:
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK12: omp.inner.for.inc:			// CHECK12: omp.inner.for.inc:
	// CHECK12-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK12-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !6
	// CHECK12-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP21]], 1			// CHECK12-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP21]], 1
	// CHECK12-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4			// CHECK12-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]
	// CHECK12: omp.inner.for.end:			// CHECK12: omp.inner.for.end:
	// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK12: omp.loop.exit:			// CHECK12: omp.loop.exit:
	// CHECK12-NEXT: [[TMP22:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4			// CHECK12-NEXT: [[TMP22:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4
	// CHECK12-NEXT: [[TMP23:%.]] = load i32, i32 [[TMP22]], align 4			// CHECK12-NEXT: [[TMP23:%.]] = load i32, i32 [[TMP22]], align 4
	// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]])			// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]])
	// CHECK12-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK12-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK12-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0			// CHECK12-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0
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	// CHECK12-NEXT: br label [[COND_END]]			// CHECK12-NEXT: br label [[COND_END]]
	// CHECK12: cond.end:			// CHECK12: cond.end:
	// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ]			// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ]
	// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK12-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK12-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK12-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4			// CHECK12-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK12: omp.inner.for.cond:			// CHECK12: omp.inner.for.cond:
	// CHECK12-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK12-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12
	// CHECK12-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK12-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !12
	// CHECK12-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]]			// CHECK12-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]]
	// CHECK12-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]			// CHECK12-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]
	// CHECK12: omp.inner.for.cond.cleanup:			// CHECK12: omp.inner.for.cond.cleanup:
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_END:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
	// CHECK12: omp.inner.for.body:			// CHECK12: omp.inner.for.body:
	// CHECK12-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK12-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12
	// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP13]], 1			// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP13]], 1
	// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !12
	// CHECK12-NEXT: [[TMP14:%.]] = load i32, i32 [[T_VAR3]], align 4			// CHECK12-NEXT: [[TMP14:%.]] = load i32, i32 [[T_VAR3]], align 4, !llvm.access.group !12
	// CHECK12-NEXT: [[TMP15:%.]] = load i32, i32 [[I]], align 4			// CHECK12-NEXT: [[TMP15:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !12
	// CHECK12-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC4]], i32 0, i32 [[TMP15]]			// CHECK12-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC4]], i32 0, i32 [[TMP15]]
	// CHECK12-NEXT: store i32 [[TMP14]], i32* [[ARRAYIDX]], align 4			// CHECK12-NEXT: store i32 [[TMP14]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !12
	// CHECK12-NEXT: [[TMP16:%.]] = load %struct.S.0, %struct.S.0** [[_TMP7]], align 4			// CHECK12-NEXT: [[TMP16:%.]] = load %struct.S.0, %struct.S.0** [[_TMP7]], align 4, !llvm.access.group !12
	// CHECK12-NEXT: [[TMP17:%.]] = load i32, i32 [[I]], align 4			// CHECK12-NEXT: [[TMP17:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !12
	// CHECK12-NEXT: [[ARRAYIDX9:%.]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0] [[S_ARR5]], i32 0, i32 [[TMP17]]			// CHECK12-NEXT: [[ARRAYIDX9:%.]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0] [[S_ARR5]], i32 0, i32 [[TMP17]]
	// CHECK12-NEXT: [[TMP18:%.]] = bitcast %struct.S.0 [[ARRAYIDX9]] to i8*			// CHECK12-NEXT: [[TMP18:%.]] = bitcast %struct.S.0 [[ARRAYIDX9]] to i8*
	// CHECK12-NEXT: [[TMP19:%.]] = bitcast %struct.S.0 [[TMP16]] to i8*			// CHECK12-NEXT: [[TMP19:%.]] = bitcast %struct.S.0 [[TMP16]] to i8*
	// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP18]], i8* align 4 [[TMP19]], i32 4, i1 false)			// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP18]], i8* align 4 [[TMP19]], i32 4, i1 false), !llvm.access.group !12
	// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK12: omp.body.continue:			// CHECK12: omp.body.continue:
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK12: omp.inner.for.inc:			// CHECK12: omp.inner.for.inc:
	// CHECK12-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK12-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12
	// CHECK12-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP20]], 1			// CHECK12-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP20]], 1
	// CHECK12-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4			// CHECK12-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]
	// CHECK12: omp.inner.for.end:			// CHECK12: omp.inner.for.end:
	// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK12: omp.loop.exit:			// CHECK12: omp.loop.exit:
	// CHECK12-NEXT: [[TMP21:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4			// CHECK12-NEXT: [[TMP21:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4
	// CHECK12-NEXT: [[TMP22:%.]] = load i32, i32 [[TMP21]], align 4			// CHECK12-NEXT: [[TMP22:%.]] = load i32, i32 [[TMP21]], align 4
	// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]])			// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]])
	// CHECK12-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK12-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK12-NEXT: [[TMP24:%.*]] = icmp ne i32 [[TMP23]], 0			// CHECK12-NEXT: [[TMP24:%.*]] = icmp ne i32 [[TMP23]], 0
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clang/test/OpenMP/distribute_simd_private_codegen.cpp

This file is larger than 256 KB, so syntax highlighting is disabled by default.

	Show First 20 Lines • Show All 174 Lines • ▼ Show 20 Lines
	// CHECK1-NEXT: br label [[COND_END]]			// CHECK1-NEXT: br label [[COND_END]]
	// CHECK1: cond.end:			// CHECK1: cond.end:
	// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]			// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
	// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK1-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK1-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK1: omp.inner.for.cond:			// CHECK1: omp.inner.for.cond:
	// CHECK1-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !4
	// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !4
	// CHECK1-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK1-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK1-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK1-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK1: omp.inner.for.body:			// CHECK1: omp.inner.for.body:
	// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !4
	// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1			// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
	// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !4
	// CHECK1-NEXT: store double 1.000000e+00, double* [[G]], align 8			// CHECK1-NEXT: store double 1.000000e+00, double* [[G]], align 8, !llvm.access.group !4
	// CHECK1-NEXT: [[TMP8:%.]] = load double, double** [[_TMP2]], align 8			// CHECK1-NEXT: [[TMP8:%.]] = load double, double** [[_TMP2]], align 8, !llvm.access.group !4
	// CHECK1-NEXT: store volatile double 1.000000e+00, double* [[TMP8]], align 8			// CHECK1-NEXT: store volatile double 1.000000e+00, double* [[TMP8]], align 8, !llvm.access.group !4
	// CHECK1-NEXT: store i32 3, i32* [[SVAR]], align 4			// CHECK1-NEXT: store i32 3, i32* [[SVAR]], align 4, !llvm.access.group !4
	// CHECK1-NEXT: store float 4.000000e+00, float* [[SFVAR]], align 4			// CHECK1-NEXT: store float 4.000000e+00, float* [[SFVAR]], align 4, !llvm.access.group !4
	// CHECK1-NEXT: [[TMP9:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 0			// CHECK1-NEXT: [[TMP9:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 0
	// CHECK1-NEXT: store double* [[G]], double** [[TMP9]], align 8			// CHECK1-NEXT: store double* [[G]], double** [[TMP9]], align 8, !llvm.access.group !4
	// CHECK1-NEXT: [[TMP10:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 1			// CHECK1-NEXT: [[TMP10:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 1
	// CHECK1-NEXT: [[TMP11:%.]] = load double, double** [[_TMP2]], align 8			// CHECK1-NEXT: [[TMP11:%.]] = load double, double** [[_TMP2]], align 8, !llvm.access.group !4
	// CHECK1-NEXT: store double* [[TMP11]], double** [[TMP10]], align 8			// CHECK1-NEXT: store double* [[TMP11]], double** [[TMP10]], align 8, !llvm.access.group !4
	// CHECK1-NEXT: [[TMP12:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 2			// CHECK1-NEXT: [[TMP12:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 2
	// CHECK1-NEXT: store i32* [[SVAR]], i32** [[TMP12]], align 8			// CHECK1-NEXT: store i32* [[SVAR]], i32** [[TMP12]], align 8, !llvm.access.group !4
	// CHECK1-NEXT: [[TMP13:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 3			// CHECK1-NEXT: [[TMP13:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 3
	// CHECK1-NEXT: store float* [[SFVAR]], float** [[TMP13]], align 8			// CHECK1-NEXT: store float* [[SFVAR]], float** [[TMP13]], align 8, !llvm.access.group !4
	// CHECK1-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(32) [[REF_TMP]])			// CHECK1-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(32) [[REF_TMP]]), !llvm.access.group !4
	// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK1: omp.body.continue:			// CHECK1: omp.body.continue:
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK1: omp.inner.for.inc:			// CHECK1: omp.inner.for.inc:
	// CHECK1-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !4
	// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP14]], 1			// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP14]], 1
	// CHECK1-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]
	// CHECK1: omp.inner.for.end:			// CHECK1: omp.inner.for.end:
	// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK1: omp.loop.exit:			// CHECK1: omp.loop.exit:
	// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])			// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
	// CHECK1-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK1-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK1-NEXT: [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0			// CHECK1-NEXT: [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0
	// CHECK1-NEXT: br i1 [[TMP16]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK1-NEXT: br i1 [[TMP16]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK1: .omp.final.then:			// CHECK1: .omp.final.then:
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	// CHECK2-NEXT: br label [[COND_END]]			// CHECK2-NEXT: br label [[COND_END]]
	// CHECK2: cond.end:			// CHECK2: cond.end:
	// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]			// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
	// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK2-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK2-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK2-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK2: omp.inner.for.cond:			// CHECK2: omp.inner.for.cond:
	// CHECK2-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !4
	// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !4
	// CHECK2-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK2-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK2-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK2-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK2: omp.inner.for.body:			// CHECK2: omp.inner.for.body:
	// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !4
	// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1			// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
	// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !4
	// CHECK2-NEXT: store double 1.000000e+00, double* [[G]], align 8			// CHECK2-NEXT: store double 1.000000e+00, double* [[G]], align 8, !llvm.access.group !4
	// CHECK2-NEXT: [[TMP8:%.]] = load double, double** [[_TMP2]], align 8			// CHECK2-NEXT: [[TMP8:%.]] = load double, double** [[_TMP2]], align 8, !llvm.access.group !4
	// CHECK2-NEXT: store volatile double 1.000000e+00, double* [[TMP8]], align 8			// CHECK2-NEXT: store volatile double 1.000000e+00, double* [[TMP8]], align 8, !llvm.access.group !4
	// CHECK2-NEXT: store i32 3, i32* [[SVAR]], align 4			// CHECK2-NEXT: store i32 3, i32* [[SVAR]], align 4, !llvm.access.group !4
	// CHECK2-NEXT: store float 4.000000e+00, float* [[SFVAR]], align 4			// CHECK2-NEXT: store float 4.000000e+00, float* [[SFVAR]], align 4, !llvm.access.group !4
	// CHECK2-NEXT: [[TMP9:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 0			// CHECK2-NEXT: [[TMP9:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 0
	// CHECK2-NEXT: store double* [[G]], double** [[TMP9]], align 8			// CHECK2-NEXT: store double* [[G]], double** [[TMP9]], align 8, !llvm.access.group !4
	// CHECK2-NEXT: [[TMP10:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 1			// CHECK2-NEXT: [[TMP10:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 1
	// CHECK2-NEXT: [[TMP11:%.]] = load double, double** [[_TMP2]], align 8			// CHECK2-NEXT: [[TMP11:%.]] = load double, double** [[_TMP2]], align 8, !llvm.access.group !4
	// CHECK2-NEXT: store double* [[TMP11]], double** [[TMP10]], align 8			// CHECK2-NEXT: store double* [[TMP11]], double** [[TMP10]], align 8, !llvm.access.group !4
	// CHECK2-NEXT: [[TMP12:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 2			// CHECK2-NEXT: [[TMP12:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 2
	// CHECK2-NEXT: store i32* [[SVAR]], i32** [[TMP12]], align 8			// CHECK2-NEXT: store i32* [[SVAR]], i32** [[TMP12]], align 8, !llvm.access.group !4
	// CHECK2-NEXT: [[TMP13:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 3			// CHECK2-NEXT: [[TMP13:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 3
	// CHECK2-NEXT: store float* [[SFVAR]], float** [[TMP13]], align 8			// CHECK2-NEXT: store float* [[SFVAR]], float** [[TMP13]], align 8, !llvm.access.group !4
	// CHECK2-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(32) [[REF_TMP]])			// CHECK2-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(32) [[REF_TMP]]), !llvm.access.group !4
	// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK2: omp.body.continue:			// CHECK2: omp.body.continue:
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK2: omp.inner.for.inc:			// CHECK2: omp.inner.for.inc:
	// CHECK2-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !4
	// CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP14]], 1			// CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP14]], 1
	// CHECK2-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]
	// CHECK2: omp.inner.for.end:			// CHECK2: omp.inner.for.end:
	// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK2: omp.loop.exit:			// CHECK2: omp.loop.exit:
	// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])			// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
	// CHECK2-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK2-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK2-NEXT: [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0			// CHECK2-NEXT: [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0
	// CHECK2-NEXT: br i1 [[TMP16]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK2-NEXT: br i1 [[TMP16]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK2: .omp.final.then:			// CHECK2: .omp.final.then:
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	// CHECK3-NEXT: br label [[COND_END]]			// CHECK3-NEXT: br label [[COND_END]]
	// CHECK3: cond.end:			// CHECK3: cond.end:
	// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]			// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
	// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK3-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK3-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK3: omp.inner.for.cond:			// CHECK3: omp.inner.for.cond:
	// CHECK3-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK3-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK3-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK3-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !5
	// CHECK3-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK3-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK3-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK3-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK3: omp.inner.for.body:			// CHECK3: omp.inner.for.body:
	// CHECK3-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK3-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1			// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
	// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !5
	// CHECK3-NEXT: store double 1.000000e+00, double* [[G]], align 8			// CHECK3-NEXT: store double 1.000000e+00, double* [[G]], align 8, !llvm.access.group !5
	// CHECK3-NEXT: [[TMP8:%.]] = load double, double** [[_TMP2]], align 4			// CHECK3-NEXT: [[TMP8:%.]] = load double, double** [[_TMP2]], align 4, !llvm.access.group !5
	// CHECK3-NEXT: store volatile double 1.000000e+00, double* [[TMP8]], align 4			// CHECK3-NEXT: store volatile double 1.000000e+00, double* [[TMP8]], align 4, !llvm.access.group !5
	// CHECK3-NEXT: store i32 3, i32* [[SVAR]], align 4			// CHECK3-NEXT: store i32 3, i32* [[SVAR]], align 4, !llvm.access.group !5
	// CHECK3-NEXT: store float 4.000000e+00, float* [[SFVAR]], align 4			// CHECK3-NEXT: store float 4.000000e+00, float* [[SFVAR]], align 4, !llvm.access.group !5
	// CHECK3-NEXT: [[TMP9:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 0			// CHECK3-NEXT: [[TMP9:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 0
	// CHECK3-NEXT: store double* [[G]], double** [[TMP9]], align 4			// CHECK3-NEXT: store double* [[G]], double** [[TMP9]], align 4, !llvm.access.group !5
	// CHECK3-NEXT: [[TMP10:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 1			// CHECK3-NEXT: [[TMP10:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 1
	// CHECK3-NEXT: [[TMP11:%.]] = load double, double** [[_TMP2]], align 4			// CHECK3-NEXT: [[TMP11:%.]] = load double, double** [[_TMP2]], align 4, !llvm.access.group !5
	// CHECK3-NEXT: store double* [[TMP11]], double** [[TMP10]], align 4			// CHECK3-NEXT: store double* [[TMP11]], double** [[TMP10]], align 4, !llvm.access.group !5
	// CHECK3-NEXT: [[TMP12:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 2			// CHECK3-NEXT: [[TMP12:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 2
	// CHECK3-NEXT: store i32* [[SVAR]], i32** [[TMP12]], align 4			// CHECK3-NEXT: store i32* [[SVAR]], i32** [[TMP12]], align 4, !llvm.access.group !5
	// CHECK3-NEXT: [[TMP13:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 3			// CHECK3-NEXT: [[TMP13:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 3
	// CHECK3-NEXT: store float* [[SFVAR]], float** [[TMP13]], align 4			// CHECK3-NEXT: store float* [[SFVAR]], float** [[TMP13]], align 4, !llvm.access.group !5
	// CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 4 dereferenceable(16) [[REF_TMP]])			// CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 4 dereferenceable(16) [[REF_TMP]]), !llvm.access.group !5
	// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK3: omp.body.continue:			// CHECK3: omp.body.continue:
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK3: omp.inner.for.inc:			// CHECK3: omp.inner.for.inc:
	// CHECK3-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK3-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP14]], 1			// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP14]], 1
	// CHECK3-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4			// CHECK3-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]
	// CHECK3: omp.inner.for.end:			// CHECK3: omp.inner.for.end:
	// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK3: omp.loop.exit:			// CHECK3: omp.loop.exit:
	// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])			// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
	// CHECK3-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK3-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK3-NEXT: [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0			// CHECK3-NEXT: [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0
	// CHECK3-NEXT: br i1 [[TMP16]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK3-NEXT: br i1 [[TMP16]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK3: .omp.final.then:			// CHECK3: .omp.final.then:
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	// CHECK4-NEXT: br label [[COND_END]]			// CHECK4-NEXT: br label [[COND_END]]
	// CHECK4: cond.end:			// CHECK4: cond.end:
	// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]			// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
	// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK4-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK4-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK4-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK4-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK4: omp.inner.for.cond:			// CHECK4: omp.inner.for.cond:
	// CHECK4-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK4-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK4-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK4-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !5
	// CHECK4-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK4-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK4-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK4-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK4: omp.inner.for.body:			// CHECK4: omp.inner.for.body:
	// CHECK4-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK4-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1			// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
	// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !5
	// CHECK4-NEXT: store double 1.000000e+00, double* [[G]], align 8			// CHECK4-NEXT: store double 1.000000e+00, double* [[G]], align 8, !llvm.access.group !5
	// CHECK4-NEXT: [[TMP8:%.]] = load double, double** [[_TMP2]], align 4			// CHECK4-NEXT: [[TMP8:%.]] = load double, double** [[_TMP2]], align 4, !llvm.access.group !5
	// CHECK4-NEXT: store volatile double 1.000000e+00, double* [[TMP8]], align 4			// CHECK4-NEXT: store volatile double 1.000000e+00, double* [[TMP8]], align 4, !llvm.access.group !5
	// CHECK4-NEXT: store i32 3, i32* [[SVAR]], align 4			// CHECK4-NEXT: store i32 3, i32* [[SVAR]], align 4, !llvm.access.group !5
	// CHECK4-NEXT: store float 4.000000e+00, float* [[SFVAR]], align 4			// CHECK4-NEXT: store float 4.000000e+00, float* [[SFVAR]], align 4, !llvm.access.group !5
	// CHECK4-NEXT: [[TMP9:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 0			// CHECK4-NEXT: [[TMP9:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 0
	// CHECK4-NEXT: store double* [[G]], double** [[TMP9]], align 4			// CHECK4-NEXT: store double* [[G]], double** [[TMP9]], align 4, !llvm.access.group !5
	// CHECK4-NEXT: [[TMP10:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 1			// CHECK4-NEXT: [[TMP10:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 1
	// CHECK4-NEXT: [[TMP11:%.]] = load double, double** [[_TMP2]], align 4			// CHECK4-NEXT: [[TMP11:%.]] = load double, double** [[_TMP2]], align 4, !llvm.access.group !5
	// CHECK4-NEXT: store double* [[TMP11]], double** [[TMP10]], align 4			// CHECK4-NEXT: store double* [[TMP11]], double** [[TMP10]], align 4, !llvm.access.group !5
	// CHECK4-NEXT: [[TMP12:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 2			// CHECK4-NEXT: [[TMP12:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 2
	// CHECK4-NEXT: store i32* [[SVAR]], i32** [[TMP12]], align 4			// CHECK4-NEXT: store i32* [[SVAR]], i32** [[TMP12]], align 4, !llvm.access.group !5
	// CHECK4-NEXT: [[TMP13:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 3			// CHECK4-NEXT: [[TMP13:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 3
	// CHECK4-NEXT: store float* [[SFVAR]], float** [[TMP13]], align 4			// CHECK4-NEXT: store float* [[SFVAR]], float** [[TMP13]], align 4, !llvm.access.group !5
	// CHECK4-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 4 dereferenceable(16) [[REF_TMP]])			// CHECK4-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 4 dereferenceable(16) [[REF_TMP]]), !llvm.access.group !5
	// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK4: omp.body.continue:			// CHECK4: omp.body.continue:
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK4: omp.inner.for.inc:			// CHECK4: omp.inner.for.inc:
	// CHECK4-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK4-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP14]], 1			// CHECK4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP14]], 1
	// CHECK4-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4			// CHECK4-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]
	// CHECK4: omp.inner.for.end:			// CHECK4: omp.inner.for.end:
	// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK4: omp.loop.exit:			// CHECK4: omp.loop.exit:
	// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])			// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
	// CHECK4-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK4-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK4-NEXT: [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0			// CHECK4-NEXT: [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0
	// CHECK4-NEXT: br i1 [[TMP16]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK4-NEXT: br i1 [[TMP16]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK4: .omp.final.then:			// CHECK4: .omp.final.then:
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	// CHECK9-NEXT: br label [[COND_END]]			// CHECK9-NEXT: br label [[COND_END]]
	// CHECK9: cond.end:			// CHECK9: cond.end:
	// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]			// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
	// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK9-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK9-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK9: omp.inner.for.cond:			// CHECK9: omp.inner.for.cond:
	// CHECK9-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !6
	// CHECK9-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK9-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !6
	// CHECK9-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK9-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK9-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]			// CHECK9-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]
	// CHECK9: omp.inner.for.cond.cleanup:			// CHECK9: omp.inner.for.cond.cleanup:
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_END:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
	// CHECK9: omp.inner.for.body:			// CHECK9: omp.inner.for.body:
	// CHECK9-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !6
	// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1			// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
	// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !6
	// CHECK9-NEXT: [[TMP8:%.]] = load i32, i32 [[T_VAR]], align 4			// CHECK9-NEXT: [[TMP8:%.]] = load i32, i32 [[T_VAR]], align 4, !llvm.access.group !6
	// CHECK9-NEXT: [[TMP9:%.]] = load i32, i32 [[I]], align 4			// CHECK9-NEXT: [[TMP9:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !6
	// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64			// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64
	// CHECK9-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC]], i64 0, i64 [[IDXPROM]]			// CHECK9-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC]], i64 0, i64 [[IDXPROM]]
	// CHECK9-NEXT: store i32 [[TMP8]], i32* [[ARRAYIDX]], align 4			// CHECK9-NEXT: store i32 [[TMP8]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !6
	// CHECK9-NEXT: [[TMP10:%.]] = load %struct.S, %struct.S** [[_TMP2]], align 8			// CHECK9-NEXT: [[TMP10:%.]] = load %struct.S, %struct.S** [[_TMP2]], align 8, !llvm.access.group !6
	// CHECK9-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4			// CHECK9-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !6
	// CHECK9-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP11]] to i64			// CHECK9-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP11]] to i64
	// CHECK9-NEXT: [[ARRAYIDX5:%.]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S] [[S_ARR]], i64 0, i64 [[IDXPROM4]]			// CHECK9-NEXT: [[ARRAYIDX5:%.]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S] [[S_ARR]], i64 0, i64 [[IDXPROM4]]
	// CHECK9-NEXT: [[TMP12:%.]] = bitcast %struct.S [[ARRAYIDX5]] to i8*			// CHECK9-NEXT: [[TMP12:%.]] = bitcast %struct.S [[ARRAYIDX5]] to i8*
	// CHECK9-NEXT: [[TMP13:%.]] = bitcast %struct.S [[TMP10]] to i8*			// CHECK9-NEXT: [[TMP13:%.]] = bitcast %struct.S [[TMP10]] to i8*
	// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i64 4, i1 false)			// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i64 4, i1 false), !llvm.access.group !6
	// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK9: omp.body.continue:			// CHECK9: omp.body.continue:
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK9: omp.inner.for.inc:			// CHECK9: omp.inner.for.inc:
	// CHECK9-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !6
	// CHECK9-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP14]], 1			// CHECK9-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP14]], 1
	// CHECK9-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4			// CHECK9-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]
	// CHECK9: omp.inner.for.end:			// CHECK9: omp.inner.for.end:
	// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK9: omp.loop.exit:			// CHECK9: omp.loop.exit:
	// CHECK9-NEXT: [[TMP15:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK9-NEXT: [[TMP15:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK9-NEXT: [[TMP16:%.]] = load i32, i32 [[TMP15]], align 4			// CHECK9-NEXT: [[TMP16:%.]] = load i32, i32 [[TMP15]], align 4
	// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP16]])			// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP16]])
	// CHECK9-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK9-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK9-NEXT: [[TMP18:%.*]] = icmp ne i32 [[TMP17]], 0			// CHECK9-NEXT: [[TMP18:%.*]] = icmp ne i32 [[TMP17]], 0
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	// CHECK9-NEXT: br label [[COND_END]]			// CHECK9-NEXT: br label [[COND_END]]
	// CHECK9: cond.end:			// CHECK9: cond.end:
	// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]			// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
	// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK9-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK9-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK9: omp.inner.for.cond:			// CHECK9: omp.inner.for.cond:
	// CHECK9-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12
	// CHECK9-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK9-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !12
	// CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK9: omp.inner.for.body:			// CHECK9: omp.inner.for.body:
	// CHECK9-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12
	// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1			// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
	// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK9-NEXT: store i32 [[ADD]], i32* [[I1]], align 4			// CHECK9-NEXT: store i32 [[ADD]], i32* [[I1]], align 4, !llvm.access.group !12
	// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK9: omp.body.continue:			// CHECK9: omp.body.continue:
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK9: omp.inner.for.inc:			// CHECK9: omp.inner.for.inc:
	// CHECK9-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12
	// CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1			// CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1
	// CHECK9-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4			// CHECK9-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]
	// CHECK9: omp.inner.for.end:			// CHECK9: omp.inner.for.end:
	// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK9: omp.loop.exit:			// CHECK9: omp.loop.exit:
	// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])			// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
	// CHECK9-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK9-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK9-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0			// CHECK9-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0
	// CHECK9-NEXT: br i1 [[TMP11]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK9-NEXT: br i1 [[TMP11]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK9: .omp.final.then:			// CHECK9: .omp.final.then:
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	// CHECK9-NEXT: br label [[COND_END]]			// CHECK9-NEXT: br label [[COND_END]]
	// CHECK9: cond.end:			// CHECK9: cond.end:
	// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]			// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
	// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK9-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK9-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK9: omp.inner.for.cond:			// CHECK9: omp.inner.for.cond:
	// CHECK9-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK9-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK9-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !15
	// CHECK9-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK9-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK9-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]			// CHECK9-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]
	// CHECK9: omp.inner.for.cond.cleanup:			// CHECK9: omp.inner.for.cond.cleanup:
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_END:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
	// CHECK9: omp.inner.for.body:			// CHECK9: omp.inner.for.body:
	// CHECK9-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1			// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
	// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !15
	// CHECK9-NEXT: [[TMP8:%.]] = load i32, i32 [[T_VAR]], align 4			// CHECK9-NEXT: [[TMP8:%.]] = load i32, i32 [[T_VAR]], align 4, !llvm.access.group !15
	// CHECK9-NEXT: [[TMP9:%.]] = load i32, i32 [[I]], align 4			// CHECK9-NEXT: [[TMP9:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !15
	// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64			// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64
	// CHECK9-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC]], i64 0, i64 [[IDXPROM]]			// CHECK9-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC]], i64 0, i64 [[IDXPROM]]
	// CHECK9-NEXT: store i32 [[TMP8]], i32* [[ARRAYIDX]], align 4			// CHECK9-NEXT: store i32 [[TMP8]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !15
	// CHECK9-NEXT: [[TMP10:%.]] = load %struct.S.0, %struct.S.0** [[_TMP2]], align 8			// CHECK9-NEXT: [[TMP10:%.]] = load %struct.S.0, %struct.S.0** [[_TMP2]], align 8, !llvm.access.group !15
	// CHECK9-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4			// CHECK9-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !15
	// CHECK9-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP11]] to i64			// CHECK9-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP11]] to i64
	// CHECK9-NEXT: [[ARRAYIDX5:%.]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0] [[S_ARR]], i64 0, i64 [[IDXPROM4]]			// CHECK9-NEXT: [[ARRAYIDX5:%.]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0] [[S_ARR]], i64 0, i64 [[IDXPROM4]]
	// CHECK9-NEXT: [[TMP12:%.]] = bitcast %struct.S.0 [[ARRAYIDX5]] to i8*			// CHECK9-NEXT: [[TMP12:%.]] = bitcast %struct.S.0 [[ARRAYIDX5]] to i8*
	// CHECK9-NEXT: [[TMP13:%.]] = bitcast %struct.S.0 [[TMP10]] to i8*			// CHECK9-NEXT: [[TMP13:%.]] = bitcast %struct.S.0 [[TMP10]] to i8*
	// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i64 4, i1 false)			// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i64 4, i1 false), !llvm.access.group !15
	// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK9: omp.body.continue:			// CHECK9: omp.body.continue:
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK9: omp.inner.for.inc:			// CHECK9: omp.inner.for.inc:
	// CHECK9-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK9-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP14]], 1			// CHECK9-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP14]], 1
	// CHECK9-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4			// CHECK9-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]]
	// CHECK9: omp.inner.for.end:			// CHECK9: omp.inner.for.end:
	// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK9: omp.loop.exit:			// CHECK9: omp.loop.exit:
	// CHECK9-NEXT: [[TMP15:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK9-NEXT: [[TMP15:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK9-NEXT: [[TMP16:%.]] = load i32, i32 [[TMP15]], align 4			// CHECK9-NEXT: [[TMP16:%.]] = load i32, i32 [[TMP15]], align 4
	// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP16]])			// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP16]])
	// CHECK9-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK9-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK9-NEXT: [[TMP18:%.*]] = icmp ne i32 [[TMP17]], 0			// CHECK9-NEXT: [[TMP18:%.*]] = icmp ne i32 [[TMP17]], 0
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	// CHECK10-NEXT: br label [[COND_END]]			// CHECK10-NEXT: br label [[COND_END]]
	// CHECK10: cond.end:			// CHECK10: cond.end:
	// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]			// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
	// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK10-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK10-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK10: omp.inner.for.cond:			// CHECK10: omp.inner.for.cond:
	// CHECK10-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !6
	// CHECK10-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK10-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !6
	// CHECK10-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK10-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK10-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]			// CHECK10-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]
	// CHECK10: omp.inner.for.cond.cleanup:			// CHECK10: omp.inner.for.cond.cleanup:
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_END:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
	// CHECK10: omp.inner.for.body:			// CHECK10: omp.inner.for.body:
	// CHECK10-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !6
	// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1			// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
	// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !6
	// CHECK10-NEXT: [[TMP8:%.]] = load i32, i32 [[T_VAR]], align 4			// CHECK10-NEXT: [[TMP8:%.]] = load i32, i32 [[T_VAR]], align 4, !llvm.access.group !6
	// CHECK10-NEXT: [[TMP9:%.]] = load i32, i32 [[I]], align 4			// CHECK10-NEXT: [[TMP9:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !6
	// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64			// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64
	// CHECK10-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC]], i64 0, i64 [[IDXPROM]]			// CHECK10-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC]], i64 0, i64 [[IDXPROM]]
	// CHECK10-NEXT: store i32 [[TMP8]], i32* [[ARRAYIDX]], align 4			// CHECK10-NEXT: store i32 [[TMP8]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !6
	// CHECK10-NEXT: [[TMP10:%.]] = load %struct.S, %struct.S** [[_TMP2]], align 8			// CHECK10-NEXT: [[TMP10:%.]] = load %struct.S, %struct.S** [[_TMP2]], align 8, !llvm.access.group !6
	// CHECK10-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4			// CHECK10-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !6
	// CHECK10-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP11]] to i64			// CHECK10-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP11]] to i64
	// CHECK10-NEXT: [[ARRAYIDX5:%.]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S] [[S_ARR]], i64 0, i64 [[IDXPROM4]]			// CHECK10-NEXT: [[ARRAYIDX5:%.]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S] [[S_ARR]], i64 0, i64 [[IDXPROM4]]
	// CHECK10-NEXT: [[TMP12:%.]] = bitcast %struct.S [[ARRAYIDX5]] to i8*			// CHECK10-NEXT: [[TMP12:%.]] = bitcast %struct.S [[ARRAYIDX5]] to i8*
	// CHECK10-NEXT: [[TMP13:%.]] = bitcast %struct.S [[TMP10]] to i8*			// CHECK10-NEXT: [[TMP13:%.]] = bitcast %struct.S [[TMP10]] to i8*
	// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i64 4, i1 false)			// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i64 4, i1 false), !llvm.access.group !6
	// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK10: omp.body.continue:			// CHECK10: omp.body.continue:
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK10: omp.inner.for.inc:			// CHECK10: omp.inner.for.inc:
	// CHECK10-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !6
	// CHECK10-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP14]], 1			// CHECK10-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP14]], 1
	// CHECK10-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4			// CHECK10-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]
	// CHECK10: omp.inner.for.end:			// CHECK10: omp.inner.for.end:
	// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK10: omp.loop.exit:			// CHECK10: omp.loop.exit:
	// CHECK10-NEXT: [[TMP15:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK10-NEXT: [[TMP15:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK10-NEXT: [[TMP16:%.]] = load i32, i32 [[TMP15]], align 4			// CHECK10-NEXT: [[TMP16:%.]] = load i32, i32 [[TMP15]], align 4
	// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP16]])			// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP16]])
	// CHECK10-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK10-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK10-NEXT: [[TMP18:%.*]] = icmp ne i32 [[TMP17]], 0			// CHECK10-NEXT: [[TMP18:%.*]] = icmp ne i32 [[TMP17]], 0
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	// CHECK10-NEXT: br label [[COND_END]]			// CHECK10-NEXT: br label [[COND_END]]
	// CHECK10: cond.end:			// CHECK10: cond.end:
	// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]			// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
	// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK10-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK10-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK10-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK10-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK10: omp.inner.for.cond:			// CHECK10: omp.inner.for.cond:
	// CHECK10-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12
	// CHECK10-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK10-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !12
	// CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK10: omp.inner.for.body:			// CHECK10: omp.inner.for.body:
	// CHECK10-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12
	// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1			// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
	// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK10-NEXT: store i32 [[ADD]], i32* [[I1]], align 4			// CHECK10-NEXT: store i32 [[ADD]], i32* [[I1]], align 4, !llvm.access.group !12
	// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK10: omp.body.continue:			// CHECK10: omp.body.continue:
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK10: omp.inner.for.inc:			// CHECK10: omp.inner.for.inc:
	// CHECK10-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12
	// CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1			// CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1
	// CHECK10-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4			// CHECK10-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]
	// CHECK10: omp.inner.for.end:			// CHECK10: omp.inner.for.end:
	// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK10: omp.loop.exit:			// CHECK10: omp.loop.exit:
	// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])			// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
	// CHECK10-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK10-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK10-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0			// CHECK10-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0
	// CHECK10-NEXT: br i1 [[TMP11]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK10-NEXT: br i1 [[TMP11]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK10: .omp.final.then:			// CHECK10: .omp.final.then:
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	// CHECK10-NEXT: br label [[COND_END]]			// CHECK10-NEXT: br label [[COND_END]]
	// CHECK10: cond.end:			// CHECK10: cond.end:
	// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]			// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
	// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK10-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK10-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK10: omp.inner.for.cond:			// CHECK10: omp.inner.for.cond:
	// CHECK10-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK10-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK10-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !15
	// CHECK10-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK10-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK10-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]			// CHECK10-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]
	// CHECK10: omp.inner.for.cond.cleanup:			// CHECK10: omp.inner.for.cond.cleanup:
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_END:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
	// CHECK10: omp.inner.for.body:			// CHECK10: omp.inner.for.body:
	// CHECK10-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1			// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
	// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !15
	// CHECK10-NEXT: [[TMP8:%.]] = load i32, i32 [[T_VAR]], align 4			// CHECK10-NEXT: [[TMP8:%.]] = load i32, i32 [[T_VAR]], align 4, !llvm.access.group !15
	// CHECK10-NEXT: [[TMP9:%.]] = load i32, i32 [[I]], align 4			// CHECK10-NEXT: [[TMP9:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !15
	// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64			// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64
	// CHECK10-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC]], i64 0, i64 [[IDXPROM]]			// CHECK10-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC]], i64 0, i64 [[IDXPROM]]
	// CHECK10-NEXT: store i32 [[TMP8]], i32* [[ARRAYIDX]], align 4			// CHECK10-NEXT: store i32 [[TMP8]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !15
	// CHECK10-NEXT: [[TMP10:%.]] = load %struct.S.0, %struct.S.0** [[_TMP2]], align 8			// CHECK10-NEXT: [[TMP10:%.]] = load %struct.S.0, %struct.S.0** [[_TMP2]], align 8, !llvm.access.group !15
	// CHECK10-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4			// CHECK10-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !15
	// CHECK10-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP11]] to i64			// CHECK10-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP11]] to i64
	// CHECK10-NEXT: [[ARRAYIDX5:%.]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0] [[S_ARR]], i64 0, i64 [[IDXPROM4]]			// CHECK10-NEXT: [[ARRAYIDX5:%.]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0] [[S_ARR]], i64 0, i64 [[IDXPROM4]]
	// CHECK10-NEXT: [[TMP12:%.]] = bitcast %struct.S.0 [[ARRAYIDX5]] to i8*			// CHECK10-NEXT: [[TMP12:%.]] = bitcast %struct.S.0 [[ARRAYIDX5]] to i8*
	// CHECK10-NEXT: [[TMP13:%.]] = bitcast %struct.S.0 [[TMP10]] to i8*			// CHECK10-NEXT: [[TMP13:%.]] = bitcast %struct.S.0 [[TMP10]] to i8*
	// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i64 4, i1 false)			// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i64 4, i1 false), !llvm.access.group !15
	// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK10: omp.body.continue:			// CHECK10: omp.body.continue:
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK10: omp.inner.for.inc:			// CHECK10: omp.inner.for.inc:
	// CHECK10-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK10-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP14]], 1			// CHECK10-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP14]], 1
	// CHECK10-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4			// CHECK10-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]]
	// CHECK10: omp.inner.for.end:			// CHECK10: omp.inner.for.end:
	// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK10: omp.loop.exit:			// CHECK10: omp.loop.exit:
	// CHECK10-NEXT: [[TMP15:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK10-NEXT: [[TMP15:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK10-NEXT: [[TMP16:%.]] = load i32, i32 [[TMP15]], align 4			// CHECK10-NEXT: [[TMP16:%.]] = load i32, i32 [[TMP15]], align 4
	// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP16]])			// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP16]])
	// CHECK10-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK10-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK10-NEXT: [[TMP18:%.*]] = icmp ne i32 [[TMP17]], 0			// CHECK10-NEXT: [[TMP18:%.*]] = icmp ne i32 [[TMP17]], 0
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	// CHECK11-NEXT: br label [[COND_END]]			// CHECK11-NEXT: br label [[COND_END]]
	// CHECK11: cond.end:			// CHECK11: cond.end:
	// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]			// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
	// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK11-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK11-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK11-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK11-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK11: omp.inner.for.cond:			// CHECK11: omp.inner.for.cond:
	// CHECK11-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK11-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !7
	// CHECK11-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK11-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !7
	// CHECK11-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK11-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK11-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]			// CHECK11-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]
	// CHECK11: omp.inner.for.cond.cleanup:			// CHECK11: omp.inner.for.cond.cleanup:
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_END:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
	// CHECK11: omp.inner.for.body:			// CHECK11: omp.inner.for.body:
	// CHECK11-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK11-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !7
	// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1			// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
	// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !7
	// CHECK11-NEXT: [[TMP8:%.]] = load i32, i32 [[T_VAR]], align 4			// CHECK11-NEXT: [[TMP8:%.]] = load i32, i32 [[T_VAR]], align 4, !llvm.access.group !7
	// CHECK11-NEXT: [[TMP9:%.]] = load i32, i32 [[I]], align 4			// CHECK11-NEXT: [[TMP9:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !7
	// CHECK11-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC]], i32 0, i32 [[TMP9]]			// CHECK11-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC]], i32 0, i32 [[TMP9]]
	// CHECK11-NEXT: store i32 [[TMP8]], i32* [[ARRAYIDX]], align 4			// CHECK11-NEXT: store i32 [[TMP8]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !7
	// CHECK11-NEXT: [[TMP10:%.]] = load %struct.S, %struct.S** [[_TMP2]], align 4			// CHECK11-NEXT: [[TMP10:%.]] = load %struct.S, %struct.S** [[_TMP2]], align 4, !llvm.access.group !7
	// CHECK11-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4			// CHECK11-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !7
	// CHECK11-NEXT: [[ARRAYIDX4:%.]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S] [[S_ARR]], i32 0, i32 [[TMP11]]			// CHECK11-NEXT: [[ARRAYIDX4:%.]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S] [[S_ARR]], i32 0, i32 [[TMP11]]
	// CHECK11-NEXT: [[TMP12:%.]] = bitcast %struct.S [[ARRAYIDX4]] to i8*			// CHECK11-NEXT: [[TMP12:%.]] = bitcast %struct.S [[ARRAYIDX4]] to i8*
	// CHECK11-NEXT: [[TMP13:%.]] = bitcast %struct.S [[TMP10]] to i8*			// CHECK11-NEXT: [[TMP13:%.]] = bitcast %struct.S [[TMP10]] to i8*
	// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i32 4, i1 false)			// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i32 4, i1 false), !llvm.access.group !7
	// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK11: omp.body.continue:			// CHECK11: omp.body.continue:
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK11: omp.inner.for.inc:			// CHECK11: omp.inner.for.inc:
	// CHECK11-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK11-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !7
	// CHECK11-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP14]], 1			// CHECK11-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP14]], 1
	// CHECK11-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4			// CHECK11-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]]
	// CHECK11: omp.inner.for.end:			// CHECK11: omp.inner.for.end:
	// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK11: omp.loop.exit:			// CHECK11: omp.loop.exit:
	// CHECK11-NEXT: [[TMP15:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4			// CHECK11-NEXT: [[TMP15:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4
	// CHECK11-NEXT: [[TMP16:%.]] = load i32, i32 [[TMP15]], align 4			// CHECK11-NEXT: [[TMP16:%.]] = load i32, i32 [[TMP15]], align 4
	// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP16]])			// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP16]])
	// CHECK11-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK11-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK11-NEXT: [[TMP18:%.*]] = icmp ne i32 [[TMP17]], 0			// CHECK11-NEXT: [[TMP18:%.*]] = icmp ne i32 [[TMP17]], 0
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	// CHECK11-NEXT: br label [[COND_END]]			// CHECK11-NEXT: br label [[COND_END]]
	// CHECK11: cond.end:			// CHECK11: cond.end:
	// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]			// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
	// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK11-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK11-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK11-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK11-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK11: omp.inner.for.cond:			// CHECK11: omp.inner.for.cond:
	// CHECK11-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK11-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK11-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK11-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !13
	// CHECK11-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK11-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK11-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK11-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK11: omp.inner.for.body:			// CHECK11: omp.inner.for.body:
	// CHECK11-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK11-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1			// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
	// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK11-NEXT: store i32 [[ADD]], i32* [[I1]], align 4			// CHECK11-NEXT: store i32 [[ADD]], i32* [[I1]], align 4, !llvm.access.group !13
	// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK11: omp.body.continue:			// CHECK11: omp.body.continue:
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK11: omp.inner.for.inc:			// CHECK11: omp.inner.for.inc:
	// CHECK11-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK11-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK11-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1			// CHECK11-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1
	// CHECK11-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4			// CHECK11-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]]
	// CHECK11: omp.inner.for.end:			// CHECK11: omp.inner.for.end:
	// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK11: omp.loop.exit:			// CHECK11: omp.loop.exit:
	// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])			// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
	// CHECK11-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK11-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK11-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0			// CHECK11-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0
	// CHECK11-NEXT: br i1 [[TMP11]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK11-NEXT: br i1 [[TMP11]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK11: .omp.final.then:			// CHECK11: .omp.final.then:
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	// CHECK11-NEXT: br label [[COND_END]]			// CHECK11-NEXT: br label [[COND_END]]
	// CHECK11: cond.end:			// CHECK11: cond.end:
	// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]			// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
	// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK11-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK11-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK11-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK11-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK11: omp.inner.for.cond:			// CHECK11: omp.inner.for.cond:
	// CHECK11-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK11-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !16
	// CHECK11-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK11-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !16
	// CHECK11-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK11-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK11-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]			// CHECK11-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]
	// CHECK11: omp.inner.for.cond.cleanup:			// CHECK11: omp.inner.for.cond.cleanup:
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_END:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
	// CHECK11: omp.inner.for.body:			// CHECK11: omp.inner.for.body:
	// CHECK11-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK11-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !16
	// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1			// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
	// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !16
	// CHECK11-NEXT: [[TMP8:%.]] = load i32, i32 [[T_VAR]], align 4			// CHECK11-NEXT: [[TMP8:%.]] = load i32, i32 [[T_VAR]], align 4, !llvm.access.group !16
	// CHECK11-NEXT: [[TMP9:%.]] = load i32, i32 [[I]], align 4			// CHECK11-NEXT: [[TMP9:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !16
	// CHECK11-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC]], i32 0, i32 [[TMP9]]			// CHECK11-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC]], i32 0, i32 [[TMP9]]
	// CHECK11-NEXT: store i32 [[TMP8]], i32* [[ARRAYIDX]], align 4			// CHECK11-NEXT: store i32 [[TMP8]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !16
	// CHECK11-NEXT: [[TMP10:%.]] = load %struct.S.0, %struct.S.0** [[_TMP2]], align 4			// CHECK11-NEXT: [[TMP10:%.]] = load %struct.S.0, %struct.S.0** [[_TMP2]], align 4, !llvm.access.group !16
	// CHECK11-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4			// CHECK11-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !16
	// CHECK11-NEXT: [[ARRAYIDX4:%.]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0] [[S_ARR]], i32 0, i32 [[TMP11]]			// CHECK11-NEXT: [[ARRAYIDX4:%.]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0] [[S_ARR]], i32 0, i32 [[TMP11]]
	// CHECK11-NEXT: [[TMP12:%.]] = bitcast %struct.S.0 [[ARRAYIDX4]] to i8*			// CHECK11-NEXT: [[TMP12:%.]] = bitcast %struct.S.0 [[ARRAYIDX4]] to i8*
	// CHECK11-NEXT: [[TMP13:%.]] = bitcast %struct.S.0 [[TMP10]] to i8*			// CHECK11-NEXT: [[TMP13:%.]] = bitcast %struct.S.0 [[TMP10]] to i8*
	// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i32 4, i1 false)			// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i32 4, i1 false), !llvm.access.group !16
	// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK11: omp.body.continue:			// CHECK11: omp.body.continue:
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK11: omp.inner.for.inc:			// CHECK11: omp.inner.for.inc:
	// CHECK11-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK11-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !16
	// CHECK11-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP14]], 1			// CHECK11-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP14]], 1
	// CHECK11-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4			// CHECK11-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !16
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]]
	// CHECK11: omp.inner.for.end:			// CHECK11: omp.inner.for.end:
	// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK11: omp.loop.exit:			// CHECK11: omp.loop.exit:
	// CHECK11-NEXT: [[TMP15:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4			// CHECK11-NEXT: [[TMP15:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4
	// CHECK11-NEXT: [[TMP16:%.]] = load i32, i32 [[TMP15]], align 4			// CHECK11-NEXT: [[TMP16:%.]] = load i32, i32 [[TMP15]], align 4
	// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP16]])			// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP16]])
	// CHECK11-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK11-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK11-NEXT: [[TMP18:%.*]] = icmp ne i32 [[TMP17]], 0			// CHECK11-NEXT: [[TMP18:%.*]] = icmp ne i32 [[TMP17]], 0
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	// CHECK12-NEXT: br label [[COND_END]]			// CHECK12-NEXT: br label [[COND_END]]
	// CHECK12: cond.end:			// CHECK12: cond.end:
	// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]			// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
	// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK12-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK12-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK12-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK12-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK12: omp.inner.for.cond:			// CHECK12: omp.inner.for.cond:
	// CHECK12-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK12-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !7
	// CHECK12-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK12-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !7
	// CHECK12-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK12-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK12-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]			// CHECK12-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]
	// CHECK12: omp.inner.for.cond.cleanup:			// CHECK12: omp.inner.for.cond.cleanup:
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_END:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
	// CHECK12: omp.inner.for.body:			// CHECK12: omp.inner.for.body:
	// CHECK12-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK12-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !7
	// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1			// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
	// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !7
	// CHECK12-NEXT: [[TMP8:%.]] = load i32, i32 [[T_VAR]], align 4			// CHECK12-NEXT: [[TMP8:%.]] = load i32, i32 [[T_VAR]], align 4, !llvm.access.group !7
	// CHECK12-NEXT: [[TMP9:%.]] = load i32, i32 [[I]], align 4			// CHECK12-NEXT: [[TMP9:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !7
	// CHECK12-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC]], i32 0, i32 [[TMP9]]			// CHECK12-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC]], i32 0, i32 [[TMP9]]
	// CHECK12-NEXT: store i32 [[TMP8]], i32* [[ARRAYIDX]], align 4			// CHECK12-NEXT: store i32 [[TMP8]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !7
	// CHECK12-NEXT: [[TMP10:%.]] = load %struct.S, %struct.S** [[_TMP2]], align 4			// CHECK12-NEXT: [[TMP10:%.]] = load %struct.S, %struct.S** [[_TMP2]], align 4, !llvm.access.group !7
	// CHECK12-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4			// CHECK12-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !7
	// CHECK12-NEXT: [[ARRAYIDX4:%.]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S] [[S_ARR]], i32 0, i32 [[TMP11]]			// CHECK12-NEXT: [[ARRAYIDX4:%.]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S] [[S_ARR]], i32 0, i32 [[TMP11]]
	// CHECK12-NEXT: [[TMP12:%.]] = bitcast %struct.S [[ARRAYIDX4]] to i8*			// CHECK12-NEXT: [[TMP12:%.]] = bitcast %struct.S [[ARRAYIDX4]] to i8*
	// CHECK12-NEXT: [[TMP13:%.]] = bitcast %struct.S [[TMP10]] to i8*			// CHECK12-NEXT: [[TMP13:%.]] = bitcast %struct.S [[TMP10]] to i8*
	// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i32 4, i1 false)			// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i32 4, i1 false), !llvm.access.group !7
	// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK12: omp.body.continue:			// CHECK12: omp.body.continue:
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK12: omp.inner.for.inc:			// CHECK12: omp.inner.for.inc:
	// CHECK12-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK12-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !7
	// CHECK12-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP14]], 1			// CHECK12-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP14]], 1
	// CHECK12-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4			// CHECK12-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]]
	// CHECK12: omp.inner.for.end:			// CHECK12: omp.inner.for.end:
	// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK12: omp.loop.exit:			// CHECK12: omp.loop.exit:
	// CHECK12-NEXT: [[TMP15:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4			// CHECK12-NEXT: [[TMP15:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4
	// CHECK12-NEXT: [[TMP16:%.]] = load i32, i32 [[TMP15]], align 4			// CHECK12-NEXT: [[TMP16:%.]] = load i32, i32 [[TMP15]], align 4
	// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP16]])			// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP16]])
	// CHECK12-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK12-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK12-NEXT: [[TMP18:%.*]] = icmp ne i32 [[TMP17]], 0			// CHECK12-NEXT: [[TMP18:%.*]] = icmp ne i32 [[TMP17]], 0
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	// CHECK12-NEXT: br label [[COND_END]]			// CHECK12-NEXT: br label [[COND_END]]
	// CHECK12: cond.end:			// CHECK12: cond.end:
	// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]			// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
	// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK12-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK12-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK12-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK12-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK12: omp.inner.for.cond:			// CHECK12: omp.inner.for.cond:
	// CHECK12-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK12-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK12-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK12-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !13
	// CHECK12-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK12-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK12-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK12-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK12: omp.inner.for.body:			// CHECK12: omp.inner.for.body:
	// CHECK12-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK12-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1			// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
	// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK12-NEXT: store i32 [[ADD]], i32* [[I1]], align 4			// CHECK12-NEXT: store i32 [[ADD]], i32* [[I1]], align 4, !llvm.access.group !13
	// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK12: omp.body.continue:			// CHECK12: omp.body.continue:
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK12: omp.inner.for.inc:			// CHECK12: omp.inner.for.inc:
	// CHECK12-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK12-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK12-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1			// CHECK12-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1
	// CHECK12-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4			// CHECK12-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]]
	// CHECK12: omp.inner.for.end:			// CHECK12: omp.inner.for.end:
	// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK12: omp.loop.exit:			// CHECK12: omp.loop.exit:
	// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])			// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
	// CHECK12-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK12-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK12-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0			// CHECK12-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0
	// CHECK12-NEXT: br i1 [[TMP11]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK12-NEXT: br i1 [[TMP11]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK12: .omp.final.then:			// CHECK12: .omp.final.then:
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	// CHECK12-NEXT: br label [[COND_END]]			// CHECK12-NEXT: br label [[COND_END]]
	// CHECK12: cond.end:			// CHECK12: cond.end:
	// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]			// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
	// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK12-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK12-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK12-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK12-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK12: omp.inner.for.cond:			// CHECK12: omp.inner.for.cond:
	// CHECK12-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK12-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !16
	// CHECK12-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK12-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !16
	// CHECK12-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK12-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK12-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]			// CHECK12-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]
	// CHECK12: omp.inner.for.cond.cleanup:			// CHECK12: omp.inner.for.cond.cleanup:
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_END:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
	// CHECK12: omp.inner.for.body:			// CHECK12: omp.inner.for.body:
	// CHECK12-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK12-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !16
	// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1			// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
	// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !16
	// CHECK12-NEXT: [[TMP8:%.]] = load i32, i32 [[T_VAR]], align 4			// CHECK12-NEXT: [[TMP8:%.]] = load i32, i32 [[T_VAR]], align 4, !llvm.access.group !16
	// CHECK12-NEXT: [[TMP9:%.]] = load i32, i32 [[I]], align 4			// CHECK12-NEXT: [[TMP9:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !16
	// CHECK12-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC]], i32 0, i32 [[TMP9]]			// CHECK12-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC]], i32 0, i32 [[TMP9]]
	// CHECK12-NEXT: store i32 [[TMP8]], i32* [[ARRAYIDX]], align 4			// CHECK12-NEXT: store i32 [[TMP8]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !16
	// CHECK12-NEXT: [[TMP10:%.]] = load %struct.S.0, %struct.S.0** [[_TMP2]], align 4			// CHECK12-NEXT: [[TMP10:%.]] = load %struct.S.0, %struct.S.0** [[_TMP2]], align 4, !llvm.access.group !16
	// CHECK12-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4			// CHECK12-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !16
	// CHECK12-NEXT: [[ARRAYIDX4:%.]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0] [[S_ARR]], i32 0, i32 [[TMP11]]			// CHECK12-NEXT: [[ARRAYIDX4:%.]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0] [[S_ARR]], i32 0, i32 [[TMP11]]
	// CHECK12-NEXT: [[TMP12:%.]] = bitcast %struct.S.0 [[ARRAYIDX4]] to i8*			// CHECK12-NEXT: [[TMP12:%.]] = bitcast %struct.S.0 [[ARRAYIDX4]] to i8*
	// CHECK12-NEXT: [[TMP13:%.]] = bitcast %struct.S.0 [[TMP10]] to i8*			// CHECK12-NEXT: [[TMP13:%.]] = bitcast %struct.S.0 [[TMP10]] to i8*
	// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i32 4, i1 false)			// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i32 4, i1 false), !llvm.access.group !16
	// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK12: omp.body.continue:			// CHECK12: omp.body.continue:
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK12: omp.inner.for.inc:			// CHECK12: omp.inner.for.inc:
	// CHECK12-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK12-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !16
	// CHECK12-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP14]], 1			// CHECK12-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP14]], 1
	// CHECK12-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4			// CHECK12-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !16
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]]
	// CHECK12: omp.inner.for.end:			// CHECK12: omp.inner.for.end:
	// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK12: omp.loop.exit:			// CHECK12: omp.loop.exit:
	// CHECK12-NEXT: [[TMP15:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4			// CHECK12-NEXT: [[TMP15:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4
	// CHECK12-NEXT: [[TMP16:%.]] = load i32, i32 [[TMP15]], align 4			// CHECK12-NEXT: [[TMP16:%.]] = load i32, i32 [[TMP15]], align 4
	// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP16]])			// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP16]])
	// CHECK12-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK12-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK12-NEXT: [[TMP18:%.*]] = icmp ne i32 [[TMP17]], 0			// CHECK12-NEXT: [[TMP18:%.*]] = icmp ne i32 [[TMP17]], 0
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clang/test/OpenMP/distribute_simd_reduction_codegen.cpp

	Show First 20 Lines • Show All 163 Lines • ▼ Show 20 Lines
	// CHECK1-NEXT: br label [[COND_END]]			// CHECK1-NEXT: br label [[COND_END]]
	// CHECK1: cond.end:			// CHECK1: cond.end:
	// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]			// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
	// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK1-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK1-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK1-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK1: omp.inner.for.cond:			// CHECK1: omp.inner.for.cond:
	// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !5
	// CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK1: omp.inner.for.body:			// CHECK1: omp.inner.for.body:
	// CHECK1-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1			// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
	// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !5
	// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[I]], align 4			// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !5
	// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[SIVAR1]], align 4			// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[SIVAR1]], align 4, !llvm.access.group !5
	// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]]			// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]]
	// CHECK1-NEXT: store i32 [[ADD3]], i32* [[SIVAR1]], align 4			// CHECK1-NEXT: store i32 [[ADD3]], i32* [[SIVAR1]], align 4, !llvm.access.group !5
	// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK1: omp.body.continue:			// CHECK1: omp.body.continue:
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK1: omp.inner.for.inc:			// CHECK1: omp.inner.for.inc:
	// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1			// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1
	// CHECK1-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]
	// CHECK1: omp.inner.for.end:			// CHECK1: omp.inner.for.end:
	// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK1: omp.loop.exit:			// CHECK1: omp.loop.exit:
	// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])			// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
	// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK1-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0			// CHECK1-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0
	// CHECK1-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK1-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK1: .omp.final.then:			// CHECK1: .omp.final.then:
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	// CHECK1-NEXT: br label [[COND_END]]			// CHECK1-NEXT: br label [[COND_END]]
	// CHECK1: cond.end:			// CHECK1: cond.end:
	// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]			// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
	// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK1-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK1-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK1-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK1: omp.inner.for.cond:			// CHECK1: omp.inner.for.cond:
	// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11
	// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !11
	// CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK1: omp.inner.for.body:			// CHECK1: omp.inner.for.body:
	// CHECK1-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11
	// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1			// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
	// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11
	// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[I]], align 4			// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !11
	// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[T_VAR1]], align 4			// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[T_VAR1]], align 4, !llvm.access.group !11
	// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]]			// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]]
	// CHECK1-NEXT: store i32 [[ADD3]], i32* [[T_VAR1]], align 4			// CHECK1-NEXT: store i32 [[ADD3]], i32* [[T_VAR1]], align 4, !llvm.access.group !11
	// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK1: omp.body.continue:			// CHECK1: omp.body.continue:
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK1: omp.inner.for.inc:			// CHECK1: omp.inner.for.inc:
	// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11
	// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1			// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1
	// CHECK1-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]
	// CHECK1: omp.inner.for.end:			// CHECK1: omp.inner.for.end:
	// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK1: omp.loop.exit:			// CHECK1: omp.loop.exit:
	// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])			// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
	// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK1-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0			// CHECK1-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0
	// CHECK1-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK1-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK1: .omp.final.then:			// CHECK1: .omp.final.then:
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	// CHECK2-NEXT: br label [[COND_END]]			// CHECK2-NEXT: br label [[COND_END]]
	// CHECK2: cond.end:			// CHECK2: cond.end:
	// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]			// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
	// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK2-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK2-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK2-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK2: omp.inner.for.cond:			// CHECK2: omp.inner.for.cond:
	// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !5
	// CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK2: omp.inner.for.body:			// CHECK2: omp.inner.for.body:
	// CHECK2-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1			// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
	// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !5
	// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[I]], align 4			// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !5
	// CHECK2-NEXT: [[TMP10:%.]] = load i32, i32 [[SIVAR1]], align 4			// CHECK2-NEXT: [[TMP10:%.]] = load i32, i32 [[SIVAR1]], align 4, !llvm.access.group !5
	// CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]]			// CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]]
	// CHECK2-NEXT: store i32 [[ADD3]], i32* [[SIVAR1]], align 4			// CHECK2-NEXT: store i32 [[ADD3]], i32* [[SIVAR1]], align 4, !llvm.access.group !5
	// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK2: omp.body.continue:			// CHECK2: omp.body.continue:
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK2: omp.inner.for.inc:			// CHECK2: omp.inner.for.inc:
	// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1			// CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1
	// CHECK2-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]
	// CHECK2: omp.inner.for.end:			// CHECK2: omp.inner.for.end:
	// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK2: omp.loop.exit:			// CHECK2: omp.loop.exit:
	// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])			// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
	// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK2-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0			// CHECK2-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0
	// CHECK2-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK2-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK2: .omp.final.then:			// CHECK2: .omp.final.then:
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	// CHECK2-NEXT: br label [[COND_END]]			// CHECK2-NEXT: br label [[COND_END]]
	// CHECK2: cond.end:			// CHECK2: cond.end:
	// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]			// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
	// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK2-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK2-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK2-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK2: omp.inner.for.cond:			// CHECK2: omp.inner.for.cond:
	// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11
	// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !11
	// CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK2: omp.inner.for.body:			// CHECK2: omp.inner.for.body:
	// CHECK2-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11
	// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1			// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
	// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11
	// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[I]], align 4			// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !11
	// CHECK2-NEXT: [[TMP10:%.]] = load i32, i32 [[T_VAR1]], align 4			// CHECK2-NEXT: [[TMP10:%.]] = load i32, i32 [[T_VAR1]], align 4, !llvm.access.group !11
	// CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]]			// CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]]
	// CHECK2-NEXT: store i32 [[ADD3]], i32* [[T_VAR1]], align 4			// CHECK2-NEXT: store i32 [[ADD3]], i32* [[T_VAR1]], align 4, !llvm.access.group !11
	// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK2: omp.body.continue:			// CHECK2: omp.body.continue:
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK2: omp.inner.for.inc:			// CHECK2: omp.inner.for.inc:
	// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11
	// CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1			// CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1
	// CHECK2-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]
	// CHECK2: omp.inner.for.end:			// CHECK2: omp.inner.for.end:
	// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK2: omp.loop.exit:			// CHECK2: omp.loop.exit:
	// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])			// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
	// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK2-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0			// CHECK2-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0
	// CHECK2-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK2-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK2: .omp.final.then:			// CHECK2: .omp.final.then:
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	// CHECK3-NEXT: br label [[COND_END]]			// CHECK3-NEXT: br label [[COND_END]]
	// CHECK3: cond.end:			// CHECK3: cond.end:
	// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]			// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
	// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK3-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK3-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK3-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK3-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK3: omp.inner.for.cond:			// CHECK3: omp.inner.for.cond:
	// CHECK3-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK3-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !6
	// CHECK3-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK3-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !6
	// CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK3: omp.inner.for.body:			// CHECK3: omp.inner.for.body:
	// CHECK3-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK3-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !6
	// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1			// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
	// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !6
	// CHECK3-NEXT: [[TMP9:%.]] = load i32, i32 [[I]], align 4			// CHECK3-NEXT: [[TMP9:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !6
	// CHECK3-NEXT: [[TMP10:%.]] = load i32, i32 [[SIVAR1]], align 4			// CHECK3-NEXT: [[TMP10:%.]] = load i32, i32 [[SIVAR1]], align 4, !llvm.access.group !6
	// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]]			// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]]
	// CHECK3-NEXT: store i32 [[ADD3]], i32* [[SIVAR1]], align 4			// CHECK3-NEXT: store i32 [[ADD3]], i32* [[SIVAR1]], align 4, !llvm.access.group !6
	// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK3: omp.body.continue:			// CHECK3: omp.body.continue:
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK3: omp.inner.for.inc:			// CHECK3: omp.inner.for.inc:
	// CHECK3-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK3-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !6
	// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1			// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1
	// CHECK3-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4			// CHECK3-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]
	// CHECK3: omp.inner.for.end:			// CHECK3: omp.inner.for.end:
	// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK3: omp.loop.exit:			// CHECK3: omp.loop.exit:
	// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])			// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
	// CHECK3-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK3-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK3-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0			// CHECK3-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0
	// CHECK3-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK3-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK3: .omp.final.then:			// CHECK3: .omp.final.then:
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	// CHECK3-NEXT: br label [[COND_END]]			// CHECK3-NEXT: br label [[COND_END]]
	// CHECK3: cond.end:			// CHECK3: cond.end:
	// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]			// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
	// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK3-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK3-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK3-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK3-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK3: omp.inner.for.cond:			// CHECK3: omp.inner.for.cond:
	// CHECK3-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK3-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12
	// CHECK3-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK3-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !12
	// CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK3: omp.inner.for.body:			// CHECK3: omp.inner.for.body:
	// CHECK3-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK3-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12
	// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1			// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
	// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !12
	// CHECK3-NEXT: [[TMP9:%.]] = load i32, i32 [[I]], align 4			// CHECK3-NEXT: [[TMP9:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !12
	// CHECK3-NEXT: [[TMP10:%.]] = load i32, i32 [[T_VAR1]], align 4			// CHECK3-NEXT: [[TMP10:%.]] = load i32, i32 [[T_VAR1]], align 4, !llvm.access.group !12
	// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]]			// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]]
	// CHECK3-NEXT: store i32 [[ADD3]], i32* [[T_VAR1]], align 4			// CHECK3-NEXT: store i32 [[ADD3]], i32* [[T_VAR1]], align 4, !llvm.access.group !12
	// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK3: omp.body.continue:			// CHECK3: omp.body.continue:
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK3: omp.inner.for.inc:			// CHECK3: omp.inner.for.inc:
	// CHECK3-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK3-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12
	// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1			// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1
	// CHECK3-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4			// CHECK3-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]
	// CHECK3: omp.inner.for.end:			// CHECK3: omp.inner.for.end:
	// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK3: omp.loop.exit:			// CHECK3: omp.loop.exit:
	// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])			// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
	// CHECK3-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK3-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK3-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0			// CHECK3-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0
	// CHECK3-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK3-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK3: .omp.final.then:			// CHECK3: .omp.final.then:
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	// CHECK4-NEXT: br label [[COND_END]]			// CHECK4-NEXT: br label [[COND_END]]
	// CHECK4: cond.end:			// CHECK4: cond.end:
	// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]			// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
	// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK4-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK4-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK4-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK4-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK4: omp.inner.for.cond:			// CHECK4: omp.inner.for.cond:
	// CHECK4-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK4-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !6
	// CHECK4-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK4-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !6
	// CHECK4-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK4-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK4-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK4-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK4: omp.inner.for.body:			// CHECK4: omp.inner.for.body:
	// CHECK4-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK4-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !6
	// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1			// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
	// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !6
	// CHECK4-NEXT: [[TMP9:%.]] = load i32, i32 [[I]], align 4			// CHECK4-NEXT: [[TMP9:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !6
	// CHECK4-NEXT: [[TMP10:%.]] = load i32, i32 [[SIVAR1]], align 4			// CHECK4-NEXT: [[TMP10:%.]] = load i32, i32 [[SIVAR1]], align 4, !llvm.access.group !6
	// CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]]			// CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]]
	// CHECK4-NEXT: store i32 [[ADD3]], i32* [[SIVAR1]], align 4			// CHECK4-NEXT: store i32 [[ADD3]], i32* [[SIVAR1]], align 4, !llvm.access.group !6
	// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK4: omp.body.continue:			// CHECK4: omp.body.continue:
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK4: omp.inner.for.inc:			// CHECK4: omp.inner.for.inc:
	// CHECK4-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK4-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !6
	// CHECK4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1			// CHECK4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1
	// CHECK4-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4			// CHECK4-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]
	// CHECK4: omp.inner.for.end:			// CHECK4: omp.inner.for.end:
	// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK4: omp.loop.exit:			// CHECK4: omp.loop.exit:
	// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])			// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
	// CHECK4-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK4-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK4-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0			// CHECK4-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0
	// CHECK4-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK4-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK4: .omp.final.then:			// CHECK4: .omp.final.then:
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	// CHECK4-NEXT: br label [[COND_END]]			// CHECK4-NEXT: br label [[COND_END]]
	// CHECK4: cond.end:			// CHECK4: cond.end:
	// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]			// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
	// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK4-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK4-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK4-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK4-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK4: omp.inner.for.cond:			// CHECK4: omp.inner.for.cond:
	// CHECK4-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK4-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12
	// CHECK4-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK4-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !12
	// CHECK4-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK4-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK4-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK4-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK4: omp.inner.for.body:			// CHECK4: omp.inner.for.body:
	// CHECK4-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK4-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12
	// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1			// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
	// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !12
	// CHECK4-NEXT: [[TMP9:%.]] = load i32, i32 [[I]], align 4			// CHECK4-NEXT: [[TMP9:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !12
	// CHECK4-NEXT: [[TMP10:%.]] = load i32, i32 [[T_VAR1]], align 4			// CHECK4-NEXT: [[TMP10:%.]] = load i32, i32 [[T_VAR1]], align 4, !llvm.access.group !12
	// CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]]			// CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]]
	// CHECK4-NEXT: store i32 [[ADD3]], i32* [[T_VAR1]], align 4			// CHECK4-NEXT: store i32 [[ADD3]], i32* [[T_VAR1]], align 4, !llvm.access.group !12
	// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK4: omp.body.continue:			// CHECK4: omp.body.continue:
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK4: omp.inner.for.inc:			// CHECK4: omp.inner.for.inc:
	// CHECK4-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK4-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12
	// CHECK4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1			// CHECK4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1
	// CHECK4-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4			// CHECK4-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]
	// CHECK4: omp.inner.for.end:			// CHECK4: omp.inner.for.end:
	// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK4: omp.loop.exit:			// CHECK4: omp.loop.exit:
	// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])			// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
	// CHECK4-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK4-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK4-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0			// CHECK4-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0
	// CHECK4-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK4-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK4: .omp.final.then:			// CHECK4: .omp.final.then:
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	// CHECK9-NEXT: br label [[COND_END]]			// CHECK9-NEXT: br label [[COND_END]]
	// CHECK9: cond.end:			// CHECK9: cond.end:
	// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]			// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
	// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK9-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK9-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK9: omp.inner.for.cond:			// CHECK9: omp.inner.for.cond:
	// CHECK9-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !4
	// CHECK9-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK9-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !4
	// CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK9: omp.inner.for.body:			// CHECK9: omp.inner.for.body:
	// CHECK9-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !4
	// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1			// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
	// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !4
	// CHECK9-NEXT: [[TMP9:%.]] = load i32, i32 [[I]], align 4			// CHECK9-NEXT: [[TMP9:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !4
	// CHECK9-NEXT: [[TMP10:%.]] = load i32, i32 [[SIVAR1]], align 4			// CHECK9-NEXT: [[TMP10:%.]] = load i32, i32 [[SIVAR1]], align 4, !llvm.access.group !4
	// CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]]			// CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]]
	// CHECK9-NEXT: store i32 [[ADD3]], i32* [[SIVAR1]], align 4			// CHECK9-NEXT: store i32 [[ADD3]], i32* [[SIVAR1]], align 4, !llvm.access.group !4
	// CHECK9-NEXT: [[TMP11:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 0			// CHECK9-NEXT: [[TMP11:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 0
	// CHECK9-NEXT: store i32* [[SIVAR1]], i32** [[TMP11]], align 8			// CHECK9-NEXT: store i32* [[SIVAR1]], i32** [[TMP11]], align 8, !llvm.access.group !4
	// CHECK9-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(8) [[REF_TMP]])			// CHECK9-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(8) [[REF_TMP]]), !llvm.access.group !4
	// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK9: omp.body.continue:			// CHECK9: omp.body.continue:
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK9: omp.inner.for.inc:			// CHECK9: omp.inner.for.inc:
	// CHECK9-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !4
	// CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1			// CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1
	// CHECK9-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4			// CHECK9-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]
	// CHECK9: omp.inner.for.end:			// CHECK9: omp.inner.for.end:
	// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK9: omp.loop.exit:			// CHECK9: omp.loop.exit:
	// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])			// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
	// CHECK9-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK9-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK9-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0			// CHECK9-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
	// CHECK9-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK9-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK9: .omp.final.then:			// CHECK9: .omp.final.then:
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	// CHECK10-NEXT: br label [[COND_END]]			// CHECK10-NEXT: br label [[COND_END]]
	// CHECK10: cond.end:			// CHECK10: cond.end:
	// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]			// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
	// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK10-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK10-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK10-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK10-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK10: omp.inner.for.cond:			// CHECK10: omp.inner.for.cond:
	// CHECK10-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !4
	// CHECK10-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK10-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !4
	// CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK10: omp.inner.for.body:			// CHECK10: omp.inner.for.body:
	// CHECK10-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !4
	// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1			// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
	// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !4
	// CHECK10-NEXT: [[TMP9:%.]] = load i32, i32 [[I]], align 4			// CHECK10-NEXT: [[TMP9:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !4
	// CHECK10-NEXT: [[TMP10:%.]] = load i32, i32 [[SIVAR1]], align 4			// CHECK10-NEXT: [[TMP10:%.]] = load i32, i32 [[SIVAR1]], align 4, !llvm.access.group !4
	// CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]]			// CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]]
	// CHECK10-NEXT: store i32 [[ADD3]], i32* [[SIVAR1]], align 4			// CHECK10-NEXT: store i32 [[ADD3]], i32* [[SIVAR1]], align 4, !llvm.access.group !4
	// CHECK10-NEXT: [[TMP11:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 0			// CHECK10-NEXT: [[TMP11:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 0
	// CHECK10-NEXT: store i32* [[SIVAR1]], i32** [[TMP11]], align 8			// CHECK10-NEXT: store i32* [[SIVAR1]], i32** [[TMP11]], align 8, !llvm.access.group !4
	// CHECK10-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(8) [[REF_TMP]])			// CHECK10-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(8) [[REF_TMP]]), !llvm.access.group !4
	// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK10: omp.body.continue:			// CHECK10: omp.body.continue:
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK10: omp.inner.for.inc:			// CHECK10: omp.inner.for.inc:
	// CHECK10-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !4
	// CHECK10-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1			// CHECK10-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1
	// CHECK10-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4			// CHECK10-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]
	// CHECK10: omp.inner.for.end:			// CHECK10: omp.inner.for.end:
	// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK10: omp.loop.exit:			// CHECK10: omp.loop.exit:
	// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])			// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
	// CHECK10-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK10-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK10-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0			// CHECK10-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
	// CHECK10-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK10-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK10: .omp.final.then:			// CHECK10: .omp.final.then:
	Show All 36 Lines

clang/test/OpenMP/for_lastprivate_codegen.cpp

This file is larger than 256 KB, so syntax highlighting is disabled by default.

	Show First 20 Lines • Show All 7,852 Lines • ▼ Show 20 Lines
	// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]]			// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]]
	// CHECK8: omp.inner.for.end:			// CHECK8: omp.inner.for.end:
	// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK8: omp.loop.exit:			// CHECK8: omp.loop.exit:
	// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]])			// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]])
	// CHECK8-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]])			// CHECK8-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]])
	// CHECK8-NEXT: ret void			// CHECK8-NEXT: ret void
	//			//
	//
	No newline at end of file

clang/test/OpenMP/for_private_codegen.cpp

	Show First 20 Lines • Show All 1,320 Lines • ▼ Show 20 Lines
	// CHECK4-NEXT: [[TMP0:%.]] = load double, double** [[BLOCK_CAPTURE_ADDR1]], align 8			// CHECK4-NEXT: [[TMP0:%.]] = load double, double** [[BLOCK_CAPTURE_ADDR1]], align 8
	// CHECK4-NEXT: store double 2.000000e+00, double* [[TMP0]], align 8			// CHECK4-NEXT: store double 2.000000e+00, double* [[TMP0]], align 8
	// CHECK4-NEXT: [[BLOCK_CAPTURE_ADDR2:%.]] = getelementptr inbounds <{ i8, i32, i32, i8, %struct.__block_descriptor, double, double, i32, float }>, <{ i8, i32, i32, i8, %struct.__block_descriptor, double, double, i32, float }> [[BLOCK]], i32 0, i32 7			// CHECK4-NEXT: [[BLOCK_CAPTURE_ADDR2:%.]] = getelementptr inbounds <{ i8, i32, i32, i8, %struct.__block_descriptor, double, double, i32, float }>, <{ i8, i32, i32, i8, %struct.__block_descriptor, double, double, i32, float }> [[BLOCK]], i32 0, i32 7
	// CHECK4-NEXT: store i32 4, i32* [[BLOCK_CAPTURE_ADDR2]], align 8			// CHECK4-NEXT: store i32 4, i32* [[BLOCK_CAPTURE_ADDR2]], align 8
	// CHECK4-NEXT: [[BLOCK_CAPTURE_ADDR3:%.]] = getelementptr inbounds <{ i8, i32, i32, i8, %struct.__block_descriptor, double, double, i32, float }>, <{ i8, i32, i32, i8, %struct.__block_descriptor, double, double, i32, float }> [[BLOCK]], i32 0, i32 8			// CHECK4-NEXT: [[BLOCK_CAPTURE_ADDR3:%.]] = getelementptr inbounds <{ i8, i32, i32, i8, %struct.__block_descriptor, double, double, i32, float }>, <{ i8, i32, i32, i8, %struct.__block_descriptor, double, double, i32, float }> [[BLOCK]], i32 0, i32 8
	// CHECK4-NEXT: store float 9.000000e+00, float* [[BLOCK_CAPTURE_ADDR3]], align 4			// CHECK4-NEXT: store float 9.000000e+00, float* [[BLOCK_CAPTURE_ADDR3]], align 4
	// CHECK4-NEXT: ret void			// CHECK4-NEXT: ret void
	//			//
	//
	No newline at end of file

clang/test/OpenMP/nvptx_SPMD_codegen.cpp

	Show All 15 Lines
	// CHECK-DAG: [[LIGHT:@.+]] = private unnamed_addr constant %struct.ident_t { i32 0, i32 2, i32 3, i32 {{[0-9]+}}, i8* getelementptr inbounds			// CHECK-DAG: [[LIGHT:@.+]] = private unnamed_addr constant %struct.ident_t { i32 0, i32 2, i32 3, i32 {{[0-9]+}}, i8* getelementptr inbounds
	// CHECK-DAG: [[DISTR_FULL:@.+]] = private unnamed_addr constant %struct.ident_t { i32 0, i32 2050, i32 1, i32 {{[0-9]+}}, i8* getelementptr inbounds			// CHECK-DAG: [[DISTR_FULL:@.+]] = private unnamed_addr constant %struct.ident_t { i32 0, i32 2050, i32 1, i32 {{[0-9]+}}, i8* getelementptr inbounds
	// CHECK-DAG: [[FULL:@.+]] = private unnamed_addr constant %struct.ident_t { i32 0, i32 2, i32 1, i32 {{[0-9]+}}, i8* getelementptr inbounds			// CHECK-DAG: [[FULL:@.+]] = private unnamed_addr constant %struct.ident_t { i32 0, i32 2, i32 1, i32 {{[0-9]+}}, i8* getelementptr inbounds
	// CHECK-DAG: [[BAR_LIGHT:@.+]] = private unnamed_addr constant %struct.ident_t { i32 0, i32 66, i32 3, i32 {{[0-9]+}}, i8* getelementptr inbounds			// CHECK-DAG: [[BAR_LIGHT:@.+]] = private unnamed_addr constant %struct.ident_t { i32 0, i32 66, i32 3, i32 {{[0-9]+}}, i8* getelementptr inbounds
	// CHECK-DAG: [[BAR_FULL:@.+]] = private unnamed_addr constant %struct.ident_t { i32 0, i32 66, i32 1, i32 {{[0-9]+}}, i8* getelementptr inbounds			// CHECK-DAG: [[BAR_FULL:@.+]] = private unnamed_addr constant %struct.ident_t { i32 0, i32 66, i32 1, i32 {{[0-9]+}}, i8* getelementptr inbounds
	// CHECK-NOT: @__omp_offloading_{{.+}}_exec_mode = weak constant i8 1			// CHECK-NOT: @__omp_offloading_{{.+}}_exec_mode = weak constant i8 1

	void foo() {			void foo() {
	// CHECK: call i32 @__kmpc_target_init({{.*}}, i8 2, i1 false, i1 false)			// CHECK: call i32 @__kmpc_target_init({{.*}}, i1 false)
	// CHECK-DAG: [[DISTR_LIGHT]]			// CHECK-DAG: [[DISTR_LIGHT]]
	// CHECK-DAG: [[FOR_LIGHT]]			// CHECK-DAG: [[FOR_LIGHT]]
	// CHECK-DAG: [[LIGHT]]			// CHECK-DAG: [[LIGHT]]
	// CHECK: call i32 @__kmpc_target_init({{.*}}, i8 2, i1 false, i1 false)			// CHECK: call i32 @__kmpc_target_init({{.*}}, i1 false)
	// CHECK-DAG: [[DISTR_LIGHT]]			// CHECK-DAG: [[DISTR_LIGHT]]
	// CHECK-DAG: [[FOR_LIGHT]]			// CHECK-DAG: [[FOR_LIGHT]]
	// CHECK-DAG: [[LIGHT]]			// CHECK-DAG: [[LIGHT]]
	// CHECK: call i32 @__kmpc_target_init({{.*}}, i8 2, i1 false, i1 false)			// CHECK: call i32 @__kmpc_target_init({{.*}}, i1 false)
	// CHECK-DAG: [[DISTR_LIGHT]]			// CHECK-DAG: [[DISTR_LIGHT]]
	// CHECK-DAG: [[FOR_LIGHT]]			// CHECK-DAG: [[FOR_LIGHT]]
	// CHECK-DAG: [[LIGHT]]			// CHECK-DAG: [[LIGHT]]
	// CHECK: call i32 @__kmpc_target_init({{.*}}, i8 2, i1 false, i1 true)			// CHECK: call i32 @__kmpc_target_init({{.*}}, i1 true)
	// CHECK-DAG: [[DISTR_FULL]]			// CHECK-DAG: [[DISTR_FULL]]
	// CHECK-DAG: [[FULL]]			// CHECK-DAG: [[FULL]]
	// CHECK: call i32 @__kmpc_target_init({{.*}}, i8 2, i1 false, i1 true)			// CHECK: call i32 @__kmpc_target_init({{.*}}, i1 true)
	// CHECK-DAG: [[DISTR_FULL]]			// CHECK-DAG: [[DISTR_FULL]]
	// CHECK-DAG: [[FULL]]			// CHECK-DAG: [[FULL]]
	// CHECK: call i32 @__kmpc_target_init({{.*}}, i8 2, i1 false, i1 true)			// CHECK: call i32 @__kmpc_target_init({{.*}}, i1 true)
	// CHECK-DAG: [[DISTR_FULL]]			// CHECK-DAG: [[DISTR_FULL]]
	// CHECK-DAG: [[FULL]]			// CHECK-DAG: [[FULL]]
	// CHECK: call i32 @__kmpc_target_init({{.*}}, i8 2, i1 false, i1 true)			// CHECK: call i32 @__kmpc_target_init({{.*}}, i1 true)
	// CHECK-DAG: [[DISTR_FULL]]			// CHECK-DAG: [[DISTR_FULL]]
	// CHECK-DAG: [[FULL]]			// CHECK-DAG: [[FULL]]
	#pragma omp target teams distribute parallel for simd if(a)			#pragma omp target teams distribute parallel for simd if(a)
	for (int i = 0; i < 10; ++i)			for (int i = 0; i < 10; ++i)
	;			;
	#pragma omp target teams distribute parallel for simd schedule(static)			#pragma omp target teams distribute parallel for simd schedule(static)
	for (int i = 0; i < 10; ++i)			for (int i = 0; i < 10; ++i)
	;			;
	#pragma omp target teams distribute parallel for simd schedule(static, 1)			#pragma omp target teams distribute parallel for simd schedule(static, 1)
	for (int i = 0; i < 10; ++i)			for (int i = 0; i < 10; ++i)
	;			;
	#pragma omp target teams distribute parallel for simd schedule(auto)			#pragma omp target teams distribute parallel for simd schedule(auto)
	for (int i = 0; i < 10; ++i)			for (int i = 0; i < 10; ++i)
	;			;
	#pragma omp target teams distribute parallel for simd schedule(runtime)			#pragma omp target teams distribute parallel for simd schedule(runtime)
	for (int i = 0; i < 10; ++i)			for (int i = 0; i < 10; ++i)
	;			;
	#pragma omp target teams distribute parallel for simd schedule(dynamic)			#pragma omp target teams distribute parallel for simd schedule(dynamic)
	for (int i = 0; i < 10; ++i)			for (int i = 0; i < 10; ++i)
	;			;
	#pragma omp target teams distribute parallel for simd schedule(guided)			#pragma omp target teams distribute parallel for simd schedule(guided)
	for (int i = 0; i < 10; ++i)			for (int i = 0; i < 10; ++i)
	;			;
	int a;			int a;
	// CHECK: call i32 @__kmpc_target_init({{.*}}, i8 2, i1 false, i1 false)			// CHECK: call i32 @__kmpc_target_init({{.*}}, i1 false)
	// CHECK-DAG: [[DISTR_LIGHT]]			// CHECK-DAG: [[DISTR_LIGHT]]
	// CHECK-DAG: [[FOR_LIGHT]]			// CHECK-DAG: [[FOR_LIGHT]]
	// CHECK-DAG: [[LIGHT]]			// CHECK-DAG: [[LIGHT]]
	// CHECK: call i32 @__kmpc_target_init({{.*}}, i8 2, i1 false, i1 false)			// CHECK: call i32 @__kmpc_target_init({{.*}}, i1 false)
	// CHECK-DAG: [[DISTR_LIGHT]]			// CHECK-DAG: [[DISTR_LIGHT]]
	// CHECK-DAG: [[FOR_LIGHT]]			// CHECK-DAG: [[FOR_LIGHT]]
	// CHECK-DAG: [[LIGHT]]			// CHECK-DAG: [[LIGHT]]
	// CHECK: call i32 @__kmpc_target_init({{.*}}, i8 2, i1 false, i1 false)			// CHECK: call i32 @__kmpc_target_init({{.*}}, i1 false)
	// CHECK-DAG: [[DISTR_LIGHT]]			// CHECK-DAG: [[DISTR_LIGHT]]
	// CHECK-DAG: [[FOR_LIGHT]]			// CHECK-DAG: [[FOR_LIGHT]]
	// CHECK-DAG: [[LIGHT]]			// CHECK-DAG: [[LIGHT]]
	// CHECK: call i32 @__kmpc_target_init({{.*}}, i8 2, i1 false, i1 true)			// CHECK: call i32 @__kmpc_target_init({{.*}}, i1 true)
	// CHECK-DAG: [[DISTR_FULL]]			// CHECK-DAG: [[DISTR_FULL]]
	// CHECK-DAG: [[FULL]]			// CHECK-DAG: [[FULL]]
	// CHECK: call i32 @__kmpc_target_init({{.*}}, i8 2, i1 false, i1 true)			// CHECK: call i32 @__kmpc_target_init({{.*}}, i1 true)
	// CHECK-DAG: [[DISTR_FULL]]			// CHECK-DAG: [[DISTR_FULL]]
	// CHECK-DAG: [[FULL]]			// CHECK-DAG: [[FULL]]
	// CHECK: call i32 @__kmpc_target_init({{.*}}, i8 2, i1 false, i1 true)			// CHECK: call i32 @__kmpc_target_init({{.*}}, i1 true)
	// CHECK-DAG: [[DISTR_FULL]]			// CHECK-DAG: [[DISTR_FULL]]
	// CHECK-DAG: [[FULL]]			// CHECK-DAG: [[FULL]]
	// CHECK: call i32 @__kmpc_target_init({{.*}}, i8 2, i1 false, i1 true)			// CHECK: call i32 @__kmpc_target_init({{.*}}, i1 true)
	// CHECK-DAG: [[DISTR_FULL]]			// CHECK-DAG: [[DISTR_FULL]]
	// CHECK-DAG: [[FULL]]			// CHECK-DAG: [[FULL]]
	#pragma omp target teams distribute parallel for lastprivate(a)			#pragma omp target teams distribute parallel for lastprivate(a)
	for (int i = 0; i < 10; ++i)			for (int i = 0; i < 10; ++i)
	a = i;			a = i;
	#pragma omp target teams distribute parallel for schedule(static)			#pragma omp target teams distribute parallel for schedule(static)
	for (int i = 0; i < 10; ++i)			for (int i = 0; i < 10; ++i)
	;			;
	#pragma omp target teams distribute parallel for schedule(static, 1)			#pragma omp target teams distribute parallel for schedule(static, 1)
	for (int i = 0; i < 10; ++i)			for (int i = 0; i < 10; ++i)
	;			;
	#pragma omp target teams distribute parallel for schedule(auto)			#pragma omp target teams distribute parallel for schedule(auto)
	for (int i = 0; i < 10; ++i)			for (int i = 0; i < 10; ++i)
	;			;
	#pragma omp target teams distribute parallel for schedule(runtime)			#pragma omp target teams distribute parallel for schedule(runtime)
	for (int i = 0; i < 10; ++i)			for (int i = 0; i < 10; ++i)
	;			;
	#pragma omp target teams distribute parallel for schedule(dynamic)			#pragma omp target teams distribute parallel for schedule(dynamic)
	for (int i = 0; i < 10; ++i)			for (int i = 0; i < 10; ++i)
	;			;
	#pragma omp target teams distribute parallel for schedule(guided)			#pragma omp target teams distribute parallel for schedule(guided)
	for (int i = 0; i < 10; ++i)			for (int i = 0; i < 10; ++i)
	;			;
	// CHECK: call i32 @__kmpc_target_init({{.*}}, i8 2, i1 false, i1 false)			// CHECK: call i32 @__kmpc_target_init({{.*}}, i1 false)
	// CHECK-DAG: [[DISTR_LIGHT]]			// CHECK-DAG: [[DISTR_LIGHT]]
	// CHECK-DAG: [[FOR_LIGHT]]			// CHECK-DAG: [[FOR_LIGHT]]
	// CHECK-DAG: [[LIGHT]]			// CHECK-DAG: [[LIGHT]]
	// CHECK: call i32 @__kmpc_target_init({{.*}}, i8 2, i1 false, i1 false)			// CHECK: call i32 @__kmpc_target_init({{.*}}, i1 false)
	// CHECK-DAG: [[DISTR_LIGHT]]			// CHECK-DAG: [[DISTR_LIGHT]]
	// CHECK-DAG: [[FOR_LIGHT]]			// CHECK-DAG: [[FOR_LIGHT]]
	// CHECK-DAG: [[LIGHT]]			// CHECK-DAG: [[LIGHT]]
	// CHECK: call i32 @__kmpc_target_init(			// CHECK: call i32 @__kmpc_target_init(
	// CHECK: call i32 @__kmpc_target_init({{.*}}, i8 2, i1 false, i1 true)			// CHECK: call i32 @__kmpc_target_init({{.*}}, i1 true)
	// CHECK-DAG: [[DISTR_FULL]]			// CHECK-DAG: [[DISTR_FULL]]
	// CHECK-DAG: [[FULL]]			// CHECK-DAG: [[FULL]]
	// CHECK: call i32 @__kmpc_target_init({{.*}}, i8 2, i1 false, i1 true)			// CHECK: call i32 @__kmpc_target_init({{.*}}, i1 true)
	// CHECK-DAG: [[DISTR_FULL]]			// CHECK-DAG: [[DISTR_FULL]]
	// CHECK-DAG: [[FULL]]			// CHECK-DAG: [[FULL]]
	// CHECK: call i32 @__kmpc_target_init({{.*}}, i8 2, i1 false, i1 true)			// CHECK: call i32 @__kmpc_target_init({{.*}}, i1 true)
	// CHECK-DAG: [[DISTR_FULL]]			// CHECK-DAG: [[DISTR_FULL]]
	// CHECK-DAG: [[FULL]]			// CHECK-DAG: [[FULL]]
	// CHECK: call i32 @__kmpc_target_init({{.*}}, i8 2, i1 false, i1 true)			// CHECK: call i32 @__kmpc_target_init({{.*}}, i1 true)
	// CHECK-DAG: [[DISTR_FULL]]			// CHECK-DAG: [[DISTR_FULL]]
	// CHECK-DAG: [[FULL]]			// CHECK-DAG: [[FULL]]
	#pragma omp target teams			#pragma omp target teams
	{			{
	int b;			int b;
	#pragma omp distribute parallel for simd			#pragma omp distribute parallel for simd
	for (int i = 0; i < 10; ++i)			for (int i = 0; i < 10; ++i)
	;			;
	Show All 25 Lines
	#pragma omp target teams			#pragma omp target teams
	#pragma omp distribute parallel for simd schedule(dynamic)			#pragma omp distribute parallel for simd schedule(dynamic)
	for (int i = 0; i < 10; ++i)			for (int i = 0; i < 10; ++i)
	;			;
	#pragma omp target teams			#pragma omp target teams
	#pragma omp distribute parallel for simd schedule(guided)			#pragma omp distribute parallel for simd schedule(guided)
	for (int i = 0; i < 10; ++i)			for (int i = 0; i < 10; ++i)
	;			;
	// CHECK: call i32 @__kmpc_target_init({{.*}}, i8 2, i1 false, i1 false)			// CHECK: call i32 @__kmpc_target_init({{.*}}, i1 false)
	// CHECK-DAG: [[DISTR_LIGHT]]			// CHECK-DAG: [[DISTR_LIGHT]]
	// CHECK-DAG: [[FOR_LIGHT]]			// CHECK-DAG: [[FOR_LIGHT]]
	// CHECK-DAG: [[LIGHT]]			// CHECK-DAG: [[LIGHT]]
	// CHECK: call i32 @__kmpc_target_init({{.*}}, i8 2, i1 false, i1 false)			// CHECK: call i32 @__kmpc_target_init({{.*}}, i1 false)
	// CHECK-DAG: [[DISTR_LIGHT]]			// CHECK-DAG: [[DISTR_LIGHT]]
	// CHECK-DAG: [[FOR_LIGHT]]			// CHECK-DAG: [[FOR_LIGHT]]
	// CHECK-DAG: [[LIGHT]]			// CHECK-DAG: [[LIGHT]]
	// CHECK: call i32 @__kmpc_target_init({{.*}}, i8 2, i1 false, i1 false)			// CHECK: call i32 @__kmpc_target_init({{.*}}, i1 false)
	// CHECK-DAG: [[DISTR_LIGHT]]			// CHECK-DAG: [[DISTR_LIGHT]]
	// CHECK-DAG: [[FOR_LIGHT]]			// CHECK-DAG: [[FOR_LIGHT]]
	// CHECK-DAG: [[LIGHT]]			// CHECK-DAG: [[LIGHT]]
	// CHECK: call i32 @__kmpc_target_init({{.*}}, i8 2, i1 false, i1 true)			// CHECK: call i32 @__kmpc_target_init({{.*}}, i1 true)
	// CHECK-DAG: [[DISTR_FULL]]			// CHECK-DAG: [[DISTR_FULL]]
	// CHECK-DAG: [[FULL]]			// CHECK-DAG: [[FULL]]
	// CHECK: call i32 @__kmpc_target_init({{.*}}, i8 2, i1 false, i1 true)			// CHECK: call i32 @__kmpc_target_init({{.*}}, i1 true)
	// CHECK-DAG: [[DISTR_FULL]]			// CHECK-DAG: [[DISTR_FULL]]
	// CHECK-DAG: [[FULL]]			// CHECK-DAG: [[FULL]]
	// CHECK: call i32 @__kmpc_target_init({{.*}}, i8 2, i1 false, i1 true)			// CHECK: call i32 @__kmpc_target_init({{.*}}, i1 true)
	// CHECK-DAG: [[DISTR_FULL]]			// CHECK-DAG: [[DISTR_FULL]]
	// CHECK-DAG: [[FULL]]			// CHECK-DAG: [[FULL]]
	// CHECK: call i32 @__kmpc_target_init({{.*}}, i8 2, i1 false, i1 true)			// CHECK: call i32 @__kmpc_target_init({{.*}}, i1 true)
	// CHECK-DAG: [[DISTR_FULL]]			// CHECK-DAG: [[DISTR_FULL]]
	// CHECK-DAG: [[FULL]]			// CHECK-DAG: [[FULL]]
	#pragma omp target teams			#pragma omp target teams
	#pragma omp distribute parallel for			#pragma omp distribute parallel for
	for (int i = 0; i < 10; ++i)			for (int i = 0; i < 10; ++i)
	;			;
	#pragma omp target teams			#pragma omp target teams
	#pragma omp distribute parallel for schedule(static)			#pragma omp distribute parallel for schedule(static)
	Show All 14 Lines
	#pragma omp target teams			#pragma omp target teams
	#pragma omp distribute parallel for schedule(dynamic)			#pragma omp distribute parallel for schedule(dynamic)
	for (int i = 0; i < 10; ++i)			for (int i = 0; i < 10; ++i)
	;			;
	#pragma omp target teams			#pragma omp target teams
	#pragma omp distribute parallel for schedule(guided)			#pragma omp distribute parallel for schedule(guided)
	for (int i = 0; i < 10; ++i)			for (int i = 0; i < 10; ++i)
	;			;
	// CHECK: call i32 @__kmpc_target_init({{.*}}, i8 2, i1 false, i1 false)			// CHECK: call i32 @__kmpc_target_init({{.*}}, i1 false)
	// CHECK-DAG: [[DISTR_LIGHT]]			// CHECK-DAG: [[DISTR_LIGHT]]
	// CHECK-DAG: [[FOR_LIGHT]]			// CHECK-DAG: [[FOR_LIGHT]]
	// CHECK-DAG: [[LIGHT]]			// CHECK-DAG: [[LIGHT]]
	// CHECK: call i32 @__kmpc_target_init({{.*}}, i8 2, i1 false, i1 false)			// CHECK: call i32 @__kmpc_target_init({{.*}}, i1 false)
	// CHECK-DAG: [[DISTR_LIGHT]]			// CHECK-DAG: [[DISTR_LIGHT]]
	// CHECK-DAG: [[FOR_LIGHT]]			// CHECK-DAG: [[FOR_LIGHT]]
	// CHECK-DAG: [[LIGHT]]			// CHECK-DAG: [[LIGHT]]
	// CHECK: call i32 @__kmpc_target_init({{.*}}, i8 2, i1 false, i1 false)			// CHECK: call i32 @__kmpc_target_init({{.*}}, i1 false)
	// CHECK-DAG: [[DISTR_LIGHT]]			// CHECK-DAG: [[DISTR_LIGHT]]
	// CHECK-DAG: [[FOR_LIGHT]]			// CHECK-DAG: [[FOR_LIGHT]]
	// CHECK-DAG: [[LIGHT]]			// CHECK-DAG: [[LIGHT]]
	// CHECK: call i32 @__kmpc_target_init({{.*}}, i8 2, i1 false, i1 true)			// CHECK: call i32 @__kmpc_target_init({{.*}}, i1 true)
	// CHECK-DAG: [[DISTR_FULL]]			// CHECK-DAG: [[DISTR_FULL]]
	// CHECK-DAG: [[FULL]]			// CHECK-DAG: [[FULL]]
	// CHECK: call i32 @__kmpc_target_init({{.*}}, i8 2, i1 false, i1 true)			// CHECK: call i32 @__kmpc_target_init({{.*}}, i1 true)
	// CHECK-DAG: [[DISTR_FULL]]			// CHECK-DAG: [[DISTR_FULL]]
	// CHECK-DAG: [[FULL]]			// CHECK-DAG: [[FULL]]
	// CHECK: call i32 @__kmpc_target_init({{.*}}, i8 2, i1 false, i1 true)			// CHECK: call i32 @__kmpc_target_init({{.*}}, i1 true)
	// CHECK-DAG: [[DISTR_FULL]]			// CHECK-DAG: [[DISTR_FULL]]
	// CHECK-DAG: [[FULL]]			// CHECK-DAG: [[FULL]]
	// CHECK: call i32 @__kmpc_target_init({{.*}}, i8 2, i1 false, i1 true)			// CHECK: call i32 @__kmpc_target_init({{.*}}, i1 true)
	// CHECK-DAG: [[DISTR_FULL]]			// CHECK-DAG: [[DISTR_FULL]]
	// CHECK-DAG: [[FULL]]			// CHECK-DAG: [[FULL]]
	#pragma omp target			#pragma omp target
	#pragma omp teams			#pragma omp teams
	#pragma omp distribute parallel for			#pragma omp distribute parallel for
	for (int i = 0; i < 10; ++i)			for (int i = 0; i < 10; ++i)
	;			;
	#pragma omp target			#pragma omp target
	Show All 21 Lines
	#pragma omp distribute parallel for schedule(dynamic)			#pragma omp distribute parallel for schedule(dynamic)
	for (int i = 0; i < 10; ++i)			for (int i = 0; i < 10; ++i)
	;			;
	#pragma omp target			#pragma omp target
	#pragma omp teams			#pragma omp teams
	#pragma omp distribute parallel for schedule(guided)			#pragma omp distribute parallel for schedule(guided)
	for (int i = 0; i < 10; ++i)			for (int i = 0; i < 10; ++i)
	;			;
	// CHECK: call i32 @__kmpc_target_init({{.*}}, i8 2, i1 false, i1 false)			// CHECK: call i32 @__kmpc_target_init({{.*}}, i1 false)
	// CHECK-DAG: [[FOR_LIGHT]]			// CHECK-DAG: [[FOR_LIGHT]]
	// CHECK-DAG: [[LIGHT]]			// CHECK-DAG: [[LIGHT]]
	// CHECK: call i32 @__kmpc_target_init({{.*}}, i8 2, i1 false, i1 false)			// CHECK: call i32 @__kmpc_target_init({{.*}}, i1 false)
	// CHECK-DAG: [[FOR_LIGHT]]			// CHECK-DAG: [[FOR_LIGHT]]
	// CHECK-DAG: [[LIGHT]]			// CHECK-DAG: [[LIGHT]]
	// CHECK: call i32 @__kmpc_target_init({{.*}}, i8 2, i1 false, i1 false)			// CHECK: call i32 @__kmpc_target_init({{.*}}, i1 false)
	// CHECK-DAG: [[FOR_LIGHT]]			// CHECK-DAG: [[FOR_LIGHT]]
	// CHECK-DAG: [[LIGHT]]			// CHECK-DAG: [[LIGHT]]
	// CHECK: call i32 @__kmpc_target_init({{.*}}, i8 2, i1 false, i1 true)			// CHECK: call i32 @__kmpc_target_init({{.*}}, i1 true)
	// CHECK-DAG: [[FULL]]			// CHECK-DAG: [[FULL]]
	// CHECK: call i32 @__kmpc_target_init({{.*}}, i8 2, i1 false, i1 true)			// CHECK: call i32 @__kmpc_target_init({{.*}}, i1 true)
	// CHECK-DAG: [[FULL]]			// CHECK-DAG: [[FULL]]
	// CHECK: call i32 @__kmpc_target_init({{.*}}, i8 2, i1 false, i1 true)			// CHECK: call i32 @__kmpc_target_init({{.*}}, i1 true)
	// CHECK-DAG: [[FULL]]			// CHECK-DAG: [[FULL]]
	// CHECK: call i32 @__kmpc_target_init({{.*}}, i8 2, i1 false, i1 true)			// CHECK: call i32 @__kmpc_target_init({{.*}}, i1 true)
	// CHECK-DAG: [[FULL]]			// CHECK-DAG: [[FULL]]
	#pragma omp target parallel for if(a)			#pragma omp target parallel for if(a)
	for (int i = 0; i < 10; ++i)			for (int i = 0; i < 10; ++i)
	;			;
	#pragma omp target parallel for schedule(static)			#pragma omp target parallel for schedule(static)
	for (int i = 0; i < 10; ++i)			for (int i = 0; i < 10; ++i)
	;			;
	#pragma omp target parallel for schedule(static, 1)			#pragma omp target parallel for schedule(static, 1)
	for (int i = 0; i < 10; ++i)			for (int i = 0; i < 10; ++i)
	;			;
	#pragma omp target parallel for schedule(auto)			#pragma omp target parallel for schedule(auto)
	for (int i = 0; i < 10; ++i)			for (int i = 0; i < 10; ++i)
	;			;
	#pragma omp target parallel for schedule(runtime)			#pragma omp target parallel for schedule(runtime)
	for (int i = 0; i < 10; ++i)			for (int i = 0; i < 10; ++i)
	;			;
	#pragma omp target parallel for schedule(dynamic)			#pragma omp target parallel for schedule(dynamic)
	for (int i = 0; i < 10; ++i)			for (int i = 0; i < 10; ++i)
	;			;
	#pragma omp target parallel for schedule(guided)			#pragma omp target parallel for schedule(guided)
	for (int i = 0; i < 10; ++i)			for (int i = 0; i < 10; ++i)
	;			;
	// CHECK: call i32 @__kmpc_target_init({{.*}}, i8 2, i1 false, i1 false)			// CHECK: call i32 @__kmpc_target_init({{.*}}, i1 false)
	// CHECK-DAG: [[FOR_LIGHT]]			// CHECK-DAG: [[FOR_LIGHT]]
	// CHECK-DAG: [[LIGHT]]			// CHECK-DAG: [[LIGHT]]
	// CHECK-DAG: [[BAR_LIGHT]]			// CHECK-DAG: [[BAR_LIGHT]]
	// CHECK: call i32 @__kmpc_target_init({{.*}}, i8 2, i1 false, i1 false)			// CHECK: call i32 @__kmpc_target_init({{.*}}, i1 false)
	// CHECK-DAG: [[FOR_LIGHT]]			// CHECK-DAG: [[FOR_LIGHT]]
	// CHECK-DAG: [[LIGHT]]			// CHECK-DAG: [[LIGHT]]
	// CHECK-DAG: [[BAR_LIGHT]]			// CHECK-DAG: [[BAR_LIGHT]]
	// CHECK: call i32 @__kmpc_target_init({{.*}}, i8 2, i1 false, i1 false)			// CHECK: call i32 @__kmpc_target_init({{.*}}, i1 false)
	// CHECK-DAG: [[FOR_LIGHT]]			// CHECK-DAG: [[FOR_LIGHT]]
	// CHECK-DAG: [[LIGHT]]			// CHECK-DAG: [[LIGHT]]
	// CHECK-DAG: [[BAR_LIGHT]]			// CHECK-DAG: [[BAR_LIGHT]]
	// CHECK: call i32 @__kmpc_target_init({{.*}}, i8 2, i1 false, i1 true)			// CHECK: call i32 @__kmpc_target_init({{.*}}, i1 true)
	// CHECK-DAG: [[FULL]]			// CHECK-DAG: [[FULL]]
	// CHECK-DAG: [[BAR_FULL]]			// CHECK-DAG: [[BAR_FULL]]
	// CHECK: call i32 @__kmpc_target_init({{.*}}, i8 2, i1 false, i1 true)			// CHECK: call i32 @__kmpc_target_init({{.*}}, i1 true)
	// CHECK-DAG: [[FULL]]			// CHECK-DAG: [[FULL]]
	// CHECK-DAG: [[BAR_FULL]]			// CHECK-DAG: [[BAR_FULL]]
	// CHECK: call i32 @__kmpc_target_init({{.*}}, i8 2, i1 false, i1 true)			// CHECK: call i32 @__kmpc_target_init({{.*}}, i1 true)
	// CHECK-DAG: [[FULL]]			// CHECK-DAG: [[FULL]]
	// CHECK-DAG: [[BAR_FULL]]			// CHECK-DAG: [[BAR_FULL]]
	// CHECK: call i32 @__kmpc_target_init({{.*}}, i8 2, i1 false, i1 true)			// CHECK: call i32 @__kmpc_target_init({{.*}}, i1 true)
	// CHECK-DAG: [[FULL]]			// CHECK-DAG: [[FULL]]
	// CHECK-DAG: [[BAR_FULL]]			// CHECK-DAG: [[BAR_FULL]]
	#pragma omp target parallel if(a)			#pragma omp target parallel if(a)
	#pragma omp for simd			#pragma omp for simd
	for (int i = 0; i < 10; ++i)			for (int i = 0; i < 10; ++i)
	;			;
	#pragma omp target parallel			#pragma omp target parallel
	#pragma omp for simd schedule(static)			#pragma omp for simd schedule(static)
	Show All 14 Lines
	#pragma omp target parallel			#pragma omp target parallel
	#pragma omp for simd schedule(dynamic)			#pragma omp for simd schedule(dynamic)
	for (int i = 0; i < 10; ++i)			for (int i = 0; i < 10; ++i)
	;			;
	#pragma omp target parallel			#pragma omp target parallel
	#pragma omp for simd schedule(guided)			#pragma omp for simd schedule(guided)
	for (int i = 0; i < 10; ++i)			for (int i = 0; i < 10; ++i)
	;			;
	// CHECK: call i32 @__kmpc_target_init({{.*}}, i8 2, i1 false, i1 true)			// CHECK: call i32 @__kmpc_target_init({{.*}}, i1 true)
	// CHECK-DAG: [[FULL]]			// CHECK-DAG: [[FULL]]
	// CHECK-DAG: [[BAR_FULL]]			// CHECK-DAG: [[BAR_FULL]]
	// CHECK: call i32 @__kmpc_target_init({{.*}}, i8 2, i1 false, i1 false)			// CHECK: call i32 @__kmpc_target_init({{.*}}, i1 false)
	// CHECK-DAG: [[FOR_LIGHT]]			// CHECK-DAG: [[FOR_LIGHT]]
	// CHECK-DAG: [[LIGHT]]			// CHECK-DAG: [[LIGHT]]
	// CHECK-DAG: [[BAR_LIGHT]]			// CHECK-DAG: [[BAR_LIGHT]]
	// CHECK: call i32 @__kmpc_target_init({{.*}}, i8 2, i1 false, i1 false)			// CHECK: call i32 @__kmpc_target_init({{.*}}, i1 false)
	// CHECK-DAG: [[FOR_LIGHT]]			// CHECK-DAG: [[FOR_LIGHT]]
	// CHECK-DAG: [[LIGHT]]			// CHECK-DAG: [[LIGHT]]
	// CHECK-DAG: [[BAR_LIGHT]]			// CHECK-DAG: [[BAR_LIGHT]]
	// CHECK: call i32 @__kmpc_target_init({{.*}}, i8 2, i1 false, i1 true)			// CHECK: call i32 @__kmpc_target_init({{.*}}, i1 true)
	// CHECK-DAG: [[FULL]]			// CHECK-DAG: [[FULL]]
	// CHECK-DAG: [[BAR_FULL]]			// CHECK-DAG: [[BAR_FULL]]
	// CHECK: call i32 @__kmpc_target_init({{.*}}, i8 2, i1 false, i1 true)			// CHECK: call i32 @__kmpc_target_init({{.*}}, i1 true)
	// CHECK-DAG: [[FULL]]			// CHECK-DAG: [[FULL]]
	// CHECK-DAG: [[BAR_FULL]]			// CHECK-DAG: [[BAR_FULL]]
	// CHECK: call i32 @__kmpc_target_init({{.*}}, i8 2, i1 false, i1 true)			// CHECK: call i32 @__kmpc_target_init({{.*}}, i1 true)
	// CHECK-DAG: [[FULL]]			// CHECK-DAG: [[FULL]]
	// CHECK-DAG: [[BAR_FULL]]			// CHECK-DAG: [[BAR_FULL]]
	// CHECK: call i32 @__kmpc_target_init({{.*}}, i8 2, i1 false, i1 true)			// CHECK: call i32 @__kmpc_target_init({{.*}}, i1 true)
	// CHECK-DAG: [[FULL]]			// CHECK-DAG: [[FULL]]
	// CHECK-DAG: [[BAR_FULL]]			// CHECK-DAG: [[BAR_FULL]]
	#pragma omp target			#pragma omp target
	#pragma omp parallel			#pragma omp parallel
	#pragma omp for simd ordered			#pragma omp for simd ordered
	for (int i = 0; i < 10; ++i)			for (int i = 0; i < 10; ++i)
	;			;
	#pragma omp target			#pragma omp target
	Show All 21 Lines
	#pragma omp for simd schedule(dynamic)			#pragma omp for simd schedule(dynamic)
	for (int i = 0; i < 10; ++i)			for (int i = 0; i < 10; ++i)
	;			;
	#pragma omp target			#pragma omp target
	#pragma omp parallel			#pragma omp parallel
	#pragma omp for simd schedule(guided)			#pragma omp for simd schedule(guided)
	for (int i = 0; i < 10; ++i)			for (int i = 0; i < 10; ++i)
	;			;
	// CHECK: call i32 @__kmpc_target_init({{.*}}, i8 2, i1 false, i1 false)			// CHECK: call i32 @__kmpc_target_init({{.*}}, i1 false)
	// CHECK-DAG: [[FOR_LIGHT]]			// CHECK-DAG: [[FOR_LIGHT]]
	// CHECK-DAG: [[LIGHT]]			// CHECK-DAG: [[LIGHT]]
	// CHECK: call i32 @__kmpc_target_init({{.*}}, i8 2, i1 false, i1 false)			// CHECK: call i32 @__kmpc_target_init({{.*}}, i1 false)
	// CHECK-DAG: [[FOR_LIGHT]]			// CHECK-DAG: [[FOR_LIGHT]]
	// CHECK-DAG: [[LIGHT]]			// CHECK-DAG: [[LIGHT]]
	// CHECK: call i32 @__kmpc_target_init({{.*}}, i8 2, i1 false, i1 false)			// CHECK: call i32 @__kmpc_target_init({{.*}}, i1 false)
	// CHECK-DAG: [[FOR_LIGHT]]			// CHECK-DAG: [[FOR_LIGHT]]
	// CHECK-DAG: [[LIGHT]]			// CHECK-DAG: [[LIGHT]]
	// CHECK: call i32 @__kmpc_target_init({{.*}}, i8 2, i1 false, i1 true)			// CHECK: call i32 @__kmpc_target_init({{.*}}, i1 true)
	// CHECK-DAG: [[FULL]]			// CHECK-DAG: [[FULL]]
	// CHECK: call i32 @__kmpc_target_init({{.*}}, i8 2, i1 false, i1 true)			// CHECK: call i32 @__kmpc_target_init({{.*}}, i1 true)
	// CHECK-DAG: [[FULL]]			// CHECK-DAG: [[FULL]]
	// CHECK: call i32 @__kmpc_target_init({{.*}}, i8 2, i1 false, i1 true)			// CHECK: call i32 @__kmpc_target_init({{.*}}, i1 true)
	// CHECK-DAG: [[FULL]]			// CHECK-DAG: [[FULL]]
	// CHECK: call i32 @__kmpc_target_init({{.*}}, i8 2, i1 false, i1 true)			// CHECK: call i32 @__kmpc_target_init({{.*}}, i1 true)
	// CHECK-DAG: [[FULL]]			// CHECK-DAG: [[FULL]]
	#pragma omp target			#pragma omp target
	#pragma omp parallel for			#pragma omp parallel for
	for (int i = 0; i < 10; ++i)			for (int i = 0; i < 10; ++i)
	;			;
	#pragma omp target			#pragma omp target
	#pragma omp parallel for schedule(static)			#pragma omp parallel for schedule(static)
	for (int i = 0; i < 10; ++i)			for (int i = 0; i < 10; ++i)
	Show All 25 Lines

clang/test/OpenMP/nvptx_data_sharing.cpp

	Show First 20 Lines • Show All 387 Lines • ▼ Show 20 Lines
	// CHECK2-NEXT: call void @__omp_outlined__1(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]], i32* [[TMP5]], i32* [[TMP8]]) #[[ATTR3]]			// CHECK2-NEXT: call void @__omp_outlined__1(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]], i32* [[TMP5]], i32* [[TMP8]]) #[[ATTR3]]
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	// CHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z7test_dsv_l14			// CHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z7test_dsv_l14
	// CHECK-SAME: () #[[ATTR0:[0-9]+]] {			// CHECK-SAME: () #[[ATTR0:[0-9]+]] {
	// CHECK-NEXT: entry:			// CHECK-NEXT: entry:
	// CHECK-NEXT: [[CAPTURED_VARS_ADDRS:%.]] = alloca [1 x i8], align 8			// CHECK-NEXT: [[CAPTURED_VARS_ADDRS:%.]] = alloca [1 x i8], align 8
	// CHECK-NEXT: [[C:%.*]] = alloca i32, align 4			// CHECK-NEXT: [[C:%.*]] = alloca i32, align 4
	// CHECK-NEXT: [[CAPTURED_VARS_ADDRS1:%.]] = alloca [2 x i8], align 8			// CHECK-NEXT: [[CAPTURED_VARS_ADDRS1:%.]] = alloca [2 x i8], align 8
	// CHECK-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1:[0-9]+]], i8 1, i1 true, i1 true)			// CHECK-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z7test_dsv_l14_kernel_info, i1 true)
	// CHECK-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1			// CHECK-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
	// CHECK-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]			// CHECK-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
	// CHECK: user_code.entry:			// CHECK: user_code.entry:
	// CHECK-NEXT: [[A:%.]] = call align 8 i8 @__kmpc_alloc_shared(i64 4)			// CHECK-NEXT: [[A:%.]] = call align 8 i8 @__kmpc_alloc_shared(i64 4)
	// CHECK-NEXT: [[A_ON_STACK:%.]] = bitcast i8 [[A]] to i32*			// CHECK-NEXT: [[A_ON_STACK:%.]] = bitcast i8 [[A]] to i32*
	// CHECK-NEXT: [[B:%.]] = call align 8 i8 @__kmpc_alloc_shared(i64 4)			// CHECK-NEXT: [[B:%.]] = call align 8 i8 @__kmpc_alloc_shared(i64 4)
	// CHECK-NEXT: [[B_ON_STACK:%.]] = bitcast i8 [[B]] to i32*			// CHECK-NEXT: [[B_ON_STACK:%.]] = bitcast i8 [[B]] to i32*
	// CHECK-NEXT: [[TMP1:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB1]])			// CHECK-NEXT: [[TMP1:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB1:[0-9]+]])
	// CHECK-NEXT: store i32 10, i32* [[A_ON_STACK]], align 4			// CHECK-NEXT: store i32 10, i32* [[A_ON_STACK]], align 4
	// CHECK-NEXT: [[TMP2:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 0			// CHECK-NEXT: [[TMP2:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
	// CHECK-NEXT: [[TMP3:%.]] = bitcast i32 [[A_ON_STACK]] to i8*			// CHECK-NEXT: [[TMP3:%.]] = bitcast i32 [[A_ON_STACK]] to i8*
	// CHECK-NEXT: store i8* [[TMP3]], i8** [[TMP2]], align 8			// CHECK-NEXT: store i8* [[TMP3]], i8** [[TMP2]], align 8
	// CHECK-NEXT: [[TMP4:%.]] = bitcast [1 x i8]* [[CAPTURED_VARS_ADDRS]] to i8**			// CHECK-NEXT: [[TMP4:%.]] = bitcast [1 x i8]* [[CAPTURED_VARS_ADDRS]] to i8**
	// CHECK-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32, i32, i32) @__omp_outlined__ to i8), i8 bitcast (void (i16, i32)* @__omp_outlined___wrapper to i8), i8* [[TMP4]], i64 1)			// CHECK-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32, i32, i32) @__omp_outlined__ to i8), i8 bitcast (void (i16, i32)* @__omp_outlined___wrapper to i8), i8* [[TMP4]], i64 1)
	// CHECK-NEXT: store i32 100, i32* [[B_ON_STACK]], align 4			// CHECK-NEXT: store i32 100, i32* [[B_ON_STACK]], align 4
	// CHECK-NEXT: store i32 1000, i32* [[C]], align 4			// CHECK-NEXT: store i32 1000, i32* [[C]], align 4
	// CHECK-NEXT: [[TMP5:%.]] = getelementptr inbounds [2 x i8], [2 x i8] [[CAPTURED_VARS_ADDRS1]], i64 0, i64 0			// CHECK-NEXT: [[TMP5:%.]] = getelementptr inbounds [2 x i8], [2 x i8] [[CAPTURED_VARS_ADDRS1]], i64 0, i64 0
	// CHECK-NEXT: [[TMP6:%.]] = bitcast i32 [[B_ON_STACK]] to i8*			// CHECK-NEXT: [[TMP6:%.]] = bitcast i32 [[B_ON_STACK]] to i8*
	// CHECK-NEXT: store i8* [[TMP6]], i8** [[TMP5]], align 8			// CHECK-NEXT: store i8* [[TMP6]], i8** [[TMP5]], align 8
	// CHECK-NEXT: [[TMP7:%.]] = getelementptr inbounds [2 x i8], [2 x i8] [[CAPTURED_VARS_ADDRS1]], i64 0, i64 1			// CHECK-NEXT: [[TMP7:%.]] = getelementptr inbounds [2 x i8], [2 x i8] [[CAPTURED_VARS_ADDRS1]], i64 0, i64 1
	// CHECK-NEXT: [[TMP8:%.]] = bitcast i32 [[A_ON_STACK]] to i8*			// CHECK-NEXT: [[TMP8:%.]] = bitcast i32 [[A_ON_STACK]] to i8*
	// CHECK-NEXT: store i8* [[TMP8]], i8** [[TMP7]], align 8			// CHECK-NEXT: store i8* [[TMP8]], i8** [[TMP7]], align 8
	// CHECK-NEXT: [[TMP9:%.]] = bitcast [2 x i8]* [[CAPTURED_VARS_ADDRS1]] to i8**			// CHECK-NEXT: [[TMP9:%.]] = bitcast [2 x i8]* [[CAPTURED_VARS_ADDRS1]] to i8**
	// CHECK-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32, i32, i32, i32)* @__omp_outlined__1 to i8), i8 bitcast (void (i16, i32)* @__omp_outlined__1_wrapper to i8), i8* [[TMP9]], i64 2)			// CHECK-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32, i32, i32, i32)* @__omp_outlined__1 to i8), i8 bitcast (void (i16, i32)* @__omp_outlined__1_wrapper to i8), i8* [[TMP9]], i64 2)
	// CHECK-NEXT: call void @__kmpc_free_shared(i8* [[B]], i64 4)			// CHECK-NEXT: call void @__kmpc_free_shared(i8* [[B]], i64 4)
	// CHECK-NEXT: call void @__kmpc_free_shared(i8* [[A]], i64 4)			// CHECK-NEXT: call void @__kmpc_free_shared(i8* [[A]], i64 4)
	// CHECK-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true)			// CHECK-NEXT: call void @__kmpc_target_deinit(i1 true)
	// CHECK-NEXT: ret void			// CHECK-NEXT: ret void
	// CHECK: worker.exit:			// CHECK: worker.exit:
	// CHECK-NEXT: ret void			// CHECK-NEXT: ret void
	//			//
	//			//
	// CHECK-LABEL: define {{[^@]+}}@__omp_outlined__			// CHECK-LABEL: define {{[^@]+}}@__omp_outlined__
	// CHECK-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i32 nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR0]] {			// CHECK-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i32 nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR0]] {
	// CHECK-NEXT: entry:			// CHECK-NEXT: entry:
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clang/test/OpenMP/nvptx_distribute_parallel_generic_mode_codegen.cpp

This file is larger than 256 KB, so syntax highlighting is disabled by default.

	Show First 20 Lines • Show All 2,988 Lines • ▼ Show 20 Lines
	// CHECK4-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8			// CHECK4-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
	// CHECK4-NEXT: store i64 [[ARGC]], i64* [[ARGC_ADDR]], align 8			// CHECK4-NEXT: store i64 [[ARGC]], i64* [[ARGC_ADDR]], align 8
	// CHECK4-NEXT: store [10 x i32]* [[D]], [10 x i32]** [[D_ADDR]], align 8			// CHECK4-NEXT: store [10 x i32]* [[D]], [10 x i32]** [[D_ADDR]], align 8
	// CHECK4-NEXT: [[TMP0:%.]] = load [10 x i32], [10 x i32]** [[B_ADDR]], align 8			// CHECK4-NEXT: [[TMP0:%.]] = load [10 x i32], [10 x i32]** [[B_ADDR]], align 8
	// CHECK4-NEXT: [[TMP1:%.]] = load [10 x i32], [10 x i32]** [[C_ADDR]], align 8			// CHECK4-NEXT: [[TMP1:%.]] = load [10 x i32], [10 x i32]** [[C_ADDR]], align 8
	// CHECK4-NEXT: [[TMP2:%.]] = load i32, i32** [[A_ADDR]], align 8			// CHECK4-NEXT: [[TMP2:%.]] = load i32, i32** [[A_ADDR]], align 8
	// CHECK4-NEXT: [[CONV:%.]] = bitcast i64 [[ARGC_ADDR]] to i32*			// CHECK4-NEXT: [[CONV:%.]] = bitcast i64 [[ARGC_ADDR]] to i32*
	// CHECK4-NEXT: [[TMP3:%.]] = load [10 x i32], [10 x i32]** [[D_ADDR]], align 8			// CHECK4-NEXT: [[TMP3:%.]] = load [10 x i32], [10 x i32]** [[D_ADDR]], align 8
	// CHECK4-NEXT: [[TMP4:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1:[0-9]+]], i8 2, i1 false, i1 false)			// CHECK4-NEXT: [[TMP4:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l19_kernel_info, i1 false)
	// CHECK4-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP4]], -1			// CHECK4-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP4]], -1
	// CHECK4-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]			// CHECK4-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
	// CHECK4: user_code.entry:			// CHECK4: user_code.entry:
	// CHECK4-NEXT: [[TMP5:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB4:[0-9]+]])			// CHECK4-NEXT: [[TMP5:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB4:[0-9]+]])
	// CHECK4-NEXT: [[TMP6:%.]] = load i32, i32 [[CONV]], align 4			// CHECK4-NEXT: [[TMP6:%.]] = load i32, i32 [[CONV]], align 4
	// CHECK4-NEXT: [[CONV1:%.]] = bitcast i64 [[ARGC_CASTED]] to i32*			// CHECK4-NEXT: [[CONV1:%.]] = bitcast i64 [[ARGC_CASTED]] to i32*
	// CHECK4-NEXT: store i32 [[TMP6]], i32* [[CONV1]], align 4			// CHECK4-NEXT: store i32 [[TMP6]], i32* [[CONV1]], align 4
	// CHECK4-NEXT: [[TMP7:%.]] = load i64, i64 [[ARGC_CASTED]], align 8			// CHECK4-NEXT: [[TMP7:%.]] = load i64, i64 [[ARGC_CASTED]], align 8
	// CHECK4-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4			// CHECK4-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	// CHECK4-NEXT: store i32 [[TMP5]], i32* [[DOTTHREADID_TEMP_]], align 4			// CHECK4-NEXT: store i32 [[TMP5]], i32* [[DOTTHREADID_TEMP_]], align 4
	// CHECK4-NEXT: call void @__omp_outlined__(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], [10 x i32]* [[TMP0]], [10 x i32]* [[TMP1]], i32* [[TMP2]], i64 [[TMP7]], [10 x i32]* [[TMP3]]) #[[ATTR4:[0-9]+]]			// CHECK4-NEXT: call void @__omp_outlined__(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], [10 x i32]* [[TMP0]], [10 x i32]* [[TMP1]], i32* [[TMP2]], i64 [[TMP7]], [10 x i32]* [[TMP3]]) #[[ATTR4:[0-9]+]]
	// CHECK4-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 false)			// CHECK4-NEXT: call void @__kmpc_target_deinit(i1 false)
	// CHECK4-NEXT: ret void			// CHECK4-NEXT: ret void
	// CHECK4: worker.exit:			// CHECK4: worker.exit:
	// CHECK4-NEXT: ret void			// CHECK4-NEXT: ret void
	//			//
	//			//
	// CHECK4-LABEL: define {{[^@]+}}@__omp_outlined__			// CHECK4-LABEL: define {{[^@]+}}@__omp_outlined__
	// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], [10 x i32] nonnull align 4 dereferenceable(40) [[B:%.]], [10 x i32] nonnull align 4 dereferenceable(40) [[C:%.]], i32 nonnull align 4 dereferenceable(4) [[A:%.]], i64 [[ARGC:%.]], [10 x i32]* nonnull align 4 dereferenceable(40) [[D:%.*]]) #[[ATTR0]] {			// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], [10 x i32] nonnull align 4 dereferenceable(40) [[B:%.]], [10 x i32] nonnull align 4 dereferenceable(40) [[C:%.]], i32 nonnull align 4 dereferenceable(4) [[A:%.]], i64 [[ARGC:%.]], [10 x i32]* nonnull align 4 dereferenceable(40) [[D:%.*]]) #[[ATTR0]] {
	// CHECK4-NEXT: entry:			// CHECK4-NEXT: entry:
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	// CHECK5-NEXT: store [10 x i32]* [[C]], [10 x i32]** [[C_ADDR]], align 4			// CHECK5-NEXT: store [10 x i32]* [[C]], [10 x i32]** [[C_ADDR]], align 4
	// CHECK5-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4			// CHECK5-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4
	// CHECK5-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4			// CHECK5-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4
	// CHECK5-NEXT: store [10 x i32]* [[D]], [10 x i32]** [[D_ADDR]], align 4			// CHECK5-NEXT: store [10 x i32]* [[D]], [10 x i32]** [[D_ADDR]], align 4
	// CHECK5-NEXT: [[TMP0:%.]] = load [10 x i32], [10 x i32]** [[B_ADDR]], align 4			// CHECK5-NEXT: [[TMP0:%.]] = load [10 x i32], [10 x i32]** [[B_ADDR]], align 4
	// CHECK5-NEXT: [[TMP1:%.]] = load [10 x i32], [10 x i32]** [[C_ADDR]], align 4			// CHECK5-NEXT: [[TMP1:%.]] = load [10 x i32], [10 x i32]** [[C_ADDR]], align 4
	// CHECK5-NEXT: [[TMP2:%.]] = load i32, i32** [[A_ADDR]], align 4			// CHECK5-NEXT: [[TMP2:%.]] = load i32, i32** [[A_ADDR]], align 4
	// CHECK5-NEXT: [[TMP3:%.]] = load [10 x i32], [10 x i32]** [[D_ADDR]], align 4			// CHECK5-NEXT: [[TMP3:%.]] = load [10 x i32], [10 x i32]** [[D_ADDR]], align 4
	// CHECK5-NEXT: [[TMP4:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1:[0-9]+]], i8 2, i1 false, i1 false)			// CHECK5-NEXT: [[TMP4:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l19_kernel_info, i1 false)
	// CHECK5-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP4]], -1			// CHECK5-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP4]], -1
	// CHECK5-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]			// CHECK5-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
	// CHECK5: user_code.entry:			// CHECK5: user_code.entry:
	// CHECK5-NEXT: [[TMP5:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB4:[0-9]+]])			// CHECK5-NEXT: [[TMP5:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB4:[0-9]+]])
	// CHECK5-NEXT: [[TMP6:%.]] = load i32, i32 [[ARGC_ADDR]], align 4			// CHECK5-NEXT: [[TMP6:%.]] = load i32, i32 [[ARGC_ADDR]], align 4
	// CHECK5-NEXT: store i32 [[TMP6]], i32* [[ARGC_CASTED]], align 4			// CHECK5-NEXT: store i32 [[TMP6]], i32* [[ARGC_CASTED]], align 4
	// CHECK5-NEXT: [[TMP7:%.]] = load i32, i32 [[ARGC_CASTED]], align 4			// CHECK5-NEXT: [[TMP7:%.]] = load i32, i32 [[ARGC_CASTED]], align 4
	// CHECK5-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4			// CHECK5-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	// CHECK5-NEXT: store i32 [[TMP5]], i32* [[DOTTHREADID_TEMP_]], align 4			// CHECK5-NEXT: store i32 [[TMP5]], i32* [[DOTTHREADID_TEMP_]], align 4
	// CHECK5-NEXT: call void @__omp_outlined__(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], [10 x i32]* [[TMP0]], [10 x i32]* [[TMP1]], i32* [[TMP2]], i32 [[TMP7]], [10 x i32]* [[TMP3]]) #[[ATTR4:[0-9]+]]			// CHECK5-NEXT: call void @__omp_outlined__(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], [10 x i32]* [[TMP0]], [10 x i32]* [[TMP1]], i32* [[TMP2]], i32 [[TMP7]], [10 x i32]* [[TMP3]]) #[[ATTR4:[0-9]+]]
	// CHECK5-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 false)			// CHECK5-NEXT: call void @__kmpc_target_deinit(i1 false)
	// CHECK5-NEXT: ret void			// CHECK5-NEXT: ret void
	// CHECK5: worker.exit:			// CHECK5: worker.exit:
	// CHECK5-NEXT: ret void			// CHECK5-NEXT: ret void
	//			//
	//			//
	// CHECK5-LABEL: define {{[^@]+}}@__omp_outlined__			// CHECK5-LABEL: define {{[^@]+}}@__omp_outlined__
	// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], [10 x i32] nonnull align 4 dereferenceable(40) [[B:%.]], [10 x i32] nonnull align 4 dereferenceable(40) [[C:%.]], i32 nonnull align 4 dereferenceable(4) [[A:%.]], i32 [[ARGC:%.]], [10 x i32]* nonnull align 4 dereferenceable(40) [[D:%.*]]) #[[ATTR0]] {			// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], [10 x i32] nonnull align 4 dereferenceable(40) [[B:%.]], [10 x i32] nonnull align 4 dereferenceable(40) [[C:%.]], i32 nonnull align 4 dereferenceable(4) [[A:%.]], i32 [[ARGC:%.]], [10 x i32]* nonnull align 4 dereferenceable(40) [[D:%.*]]) #[[ATTR0]] {
	// CHECK5-NEXT: entry:			// CHECK5-NEXT: entry:
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	// CHECK6-NEXT: store [10 x i32]* [[C]], [10 x i32]** [[C_ADDR]], align 4			// CHECK6-NEXT: store [10 x i32]* [[C]], [10 x i32]** [[C_ADDR]], align 4
	// CHECK6-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4			// CHECK6-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4
	// CHECK6-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4			// CHECK6-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4
	// CHECK6-NEXT: store [10 x i32]* [[D]], [10 x i32]** [[D_ADDR]], align 4			// CHECK6-NEXT: store [10 x i32]* [[D]], [10 x i32]** [[D_ADDR]], align 4
	// CHECK6-NEXT: [[TMP0:%.]] = load [10 x i32], [10 x i32]** [[B_ADDR]], align 4			// CHECK6-NEXT: [[TMP0:%.]] = load [10 x i32], [10 x i32]** [[B_ADDR]], align 4
	// CHECK6-NEXT: [[TMP1:%.]] = load [10 x i32], [10 x i32]** [[C_ADDR]], align 4			// CHECK6-NEXT: [[TMP1:%.]] = load [10 x i32], [10 x i32]** [[C_ADDR]], align 4
	// CHECK6-NEXT: [[TMP2:%.]] = load i32, i32** [[A_ADDR]], align 4			// CHECK6-NEXT: [[TMP2:%.]] = load i32, i32** [[A_ADDR]], align 4
	// CHECK6-NEXT: [[TMP3:%.]] = load [10 x i32], [10 x i32]** [[D_ADDR]], align 4			// CHECK6-NEXT: [[TMP3:%.]] = load [10 x i32], [10 x i32]** [[D_ADDR]], align 4
	// CHECK6-NEXT: [[TMP4:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1:[0-9]+]], i8 2, i1 false, i1 false)			// CHECK6-NEXT: [[TMP4:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l19_kernel_info, i1 false)
	// CHECK6-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP4]], -1			// CHECK6-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP4]], -1
	// CHECK6-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]			// CHECK6-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
	// CHECK6: user_code.entry:			// CHECK6: user_code.entry:
	// CHECK6-NEXT: [[TMP5:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB4:[0-9]+]])			// CHECK6-NEXT: [[TMP5:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB4:[0-9]+]])
	// CHECK6-NEXT: [[TMP6:%.]] = load i32, i32 [[ARGC_ADDR]], align 4			// CHECK6-NEXT: [[TMP6:%.]] = load i32, i32 [[ARGC_ADDR]], align 4
	// CHECK6-NEXT: store i32 [[TMP6]], i32* [[ARGC_CASTED]], align 4			// CHECK6-NEXT: store i32 [[TMP6]], i32* [[ARGC_CASTED]], align 4
	// CHECK6-NEXT: [[TMP7:%.]] = load i32, i32 [[ARGC_CASTED]], align 4			// CHECK6-NEXT: [[TMP7:%.]] = load i32, i32 [[ARGC_CASTED]], align 4
	// CHECK6-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4			// CHECK6-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	// CHECK6-NEXT: store i32 [[TMP5]], i32* [[DOTTHREADID_TEMP_]], align 4			// CHECK6-NEXT: store i32 [[TMP5]], i32* [[DOTTHREADID_TEMP_]], align 4
	// CHECK6-NEXT: call void @__omp_outlined__(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], [10 x i32]* [[TMP0]], [10 x i32]* [[TMP1]], i32* [[TMP2]], i32 [[TMP7]], [10 x i32]* [[TMP3]]) #[[ATTR4:[0-9]+]]			// CHECK6-NEXT: call void @__omp_outlined__(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], [10 x i32]* [[TMP0]], [10 x i32]* [[TMP1]], i32* [[TMP2]], i32 [[TMP7]], [10 x i32]* [[TMP3]]) #[[ATTR4:[0-9]+]]
	// CHECK6-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 false)			// CHECK6-NEXT: call void @__kmpc_target_deinit(i1 false)
	// CHECK6-NEXT: ret void			// CHECK6-NEXT: ret void
	// CHECK6: worker.exit:			// CHECK6: worker.exit:
	// CHECK6-NEXT: ret void			// CHECK6-NEXT: ret void
	//			//
	//			//
	// CHECK6-LABEL: define {{[^@]+}}@__omp_outlined__			// CHECK6-LABEL: define {{[^@]+}}@__omp_outlined__
	// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], [10 x i32] nonnull align 4 dereferenceable(40) [[B:%.]], [10 x i32] nonnull align 4 dereferenceable(40) [[C:%.]], i32 nonnull align 4 dereferenceable(4) [[A:%.]], i32 [[ARGC:%.]], [10 x i32]* nonnull align 4 dereferenceable(40) [[D:%.*]]) #[[ATTR0]] {			// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], [10 x i32] nonnull align 4 dereferenceable(40) [[B:%.]], [10 x i32] nonnull align 4 dereferenceable(40) [[C:%.]], i32 nonnull align 4 dereferenceable(4) [[A:%.]], i32 [[ARGC:%.]], [10 x i32]* nonnull align 4 dereferenceable(40) [[D:%.*]]) #[[ATTR0]] {
	// CHECK6-NEXT: entry:			// CHECK6-NEXT: entry:
	▲ Show 20 Lines • Show All 282 Lines • Show Last 20 Lines

clang/test/OpenMP/nvptx_force_full_runtime_SPMD_codegen.cpp

	// Test target codegen - host bc file has to be created first.			// Test target codegen - host bc file has to be created first.
	// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm-bc %s -o %t-ppc-host.bc			// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm-bc %s -o %t-ppc-host.bc
	// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple nvptx64-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - -fopenmp-cuda-force-full-runtime \| FileCheck %s			// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple nvptx64-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - -fopenmp-cuda-force-full-runtime \| FileCheck %s
	// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm-bc %s -o %t-x86-host.bc			// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm-bc %s -o %t-x86-host.bc
	// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple nvptx-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - -fopenmp-cuda-force-full-runtime \| FileCheck %s			// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple nvptx-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - -fopenmp-cuda-force-full-runtime \| FileCheck %s
	// RUN: %clang_cc1 -verify -fopenmp -fexceptions -fcxx-exceptions -x c++ -triple nvptx-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - -fopenmp-cuda-force-full-runtime \| FileCheck %s			// RUN: %clang_cc1 -verify -fopenmp -fexceptions -fcxx-exceptions -x c++ -triple nvptx-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - -fopenmp-cuda-force-full-runtime \| FileCheck %s
	// expected-no-diagnostics			// expected-no-diagnostics
	#ifndef HEADER			#ifndef HEADER
	#define HEADER			#define HEADER

	// CHECK-NOT: @__omp_offloading_{{.+}}_exec_mode = weak constant i8 1			// CHECK-NOT: @__omp_offloading_{{.+}}_exec_mode = weak constant i8 1

	void foo() {			void foo() {
	// CHECK: call i32 @__kmpc_target_init({{.*}}, i8 2, i1 false, i1 true)			// CHECK: call i32 @__kmpc_target_init({{.*}}, i1 true)
	// CHECK: call i32 @__kmpc_target_init({{.*}}, i8 2, i1 false, i1 true)			// CHECK: call i32 @__kmpc_target_init({{.*}}, i1 true)
	// CHECK: call i32 @__kmpc_target_init({{.*}}, i8 2, i1 false, i1 true)			// CHECK: call i32 @__kmpc_target_init({{.*}}, i1 true)
	// CHECK: call i32 @__kmpc_target_init({{.*}}, i8 2, i1 false, i1 true)			// CHECK: call i32 @__kmpc_target_init({{.*}}, i1 true)
	// CHECK: call i32 @__kmpc_target_init({{.*}}, i8 2, i1 false, i1 true)			// CHECK: call i32 @__kmpc_target_init({{.*}}, i1 true)
	// CHECK: call i32 @__kmpc_target_init({{.*}}, i8 2, i1 false, i1 true)			// CHECK: call i32 @__kmpc_target_init({{.*}}, i1 true)
	// CHECK: call i32 @__kmpc_target_init({{.*}}, i8 2, i1 false, i1 true)			// CHECK: call i32 @__kmpc_target_init({{.*}}, i1 true)
	#pragma omp target teams distribute parallel for simd			#pragma omp target teams distribute parallel for simd
	for (int i = 0; i < 10; ++i)			for (int i = 0; i < 10; ++i)
	;			;
	#pragma omp target teams distribute parallel for simd schedule(static)			#pragma omp target teams distribute parallel for simd schedule(static)
	for (int i = 0; i < 10; ++i)			for (int i = 0; i < 10; ++i)
	;			;
	#pragma omp target teams distribute parallel for simd schedule(static, 1)			#pragma omp target teams distribute parallel for simd schedule(static, 1)
	for (int i = 0; i < 10; ++i)			for (int i = 0; i < 10; ++i)
	;			;
	#pragma omp target teams distribute parallel for simd schedule(auto)			#pragma omp target teams distribute parallel for simd schedule(auto)
	for (int i = 0; i < 10; ++i)			for (int i = 0; i < 10; ++i)
	;			;
	#pragma omp target teams distribute parallel for simd schedule(runtime)			#pragma omp target teams distribute parallel for simd schedule(runtime)
	for (int i = 0; i < 10; ++i)			for (int i = 0; i < 10; ++i)
	;			;
	#pragma omp target teams distribute parallel for simd schedule(dynamic)			#pragma omp target teams distribute parallel for simd schedule(dynamic)
	for (int i = 0; i < 10; ++i)			for (int i = 0; i < 10; ++i)
	;			;
	#pragma omp target teams distribute parallel for simd schedule(guided)			#pragma omp target teams distribute parallel for simd schedule(guided)
	for (int i = 0; i < 10; ++i)			for (int i = 0; i < 10; ++i)
	;			;
	int a;			int a;
	// CHECK: call i32 @__kmpc_target_init({{.*}}, i8 2, i1 false, i1 true)			// CHECK: call i32 @__kmpc_target_init({{.*}}, i1 true)
	// CHECK: call i32 @__kmpc_target_init({{.*}}, i8 2, i1 false, i1 true)			// CHECK: call i32 @__kmpc_target_init({{.*}}, i1 true)
	// CHECK: call i32 @__kmpc_target_init({{.*}}, i8 2, i1 false, i1 true)			// CHECK: call i32 @__kmpc_target_init({{.*}}, i1 true)
	// CHECK: call i32 @__kmpc_target_init({{.*}}, i8 2, i1 false, i1 true)			// CHECK: call i32 @__kmpc_target_init({{.*}}, i1 true)
	// CHECK: call i32 @__kmpc_target_init({{.*}}, i8 2, i1 false, i1 true)			// CHECK: call i32 @__kmpc_target_init({{.*}}, i1 true)
	// CHECK: call i32 @__kmpc_target_init({{.*}}, i8 2, i1 false, i1 true)			// CHECK: call i32 @__kmpc_target_init({{.*}}, i1 true)
	// CHECK: call i32 @__kmpc_target_init({{.*}}, i8 2, i1 false, i1 true)			// CHECK: call i32 @__kmpc_target_init({{.*}}, i1 true)
	#pragma omp target teams distribute parallel for lastprivate(a)			#pragma omp target teams distribute parallel for lastprivate(a)
	for (int i = 0; i < 10; ++i)			for (int i = 0; i < 10; ++i)
	a = i;			a = i;
	#pragma omp target teams distribute parallel for schedule(static)			#pragma omp target teams distribute parallel for schedule(static)
	for (int i = 0; i < 10; ++i)			for (int i = 0; i < 10; ++i)
	;			;
	#pragma omp target teams distribute parallel for schedule(static, 1)			#pragma omp target teams distribute parallel for schedule(static, 1)
	for (int i = 0; i < 10; ++i)			for (int i = 0; i < 10; ++i)
	;			;
	#pragma omp target teams distribute parallel for schedule(auto)			#pragma omp target teams distribute parallel for schedule(auto)
	for (int i = 0; i < 10; ++i)			for (int i = 0; i < 10; ++i)
	;			;
	#pragma omp target teams distribute parallel for schedule(runtime)			#pragma omp target teams distribute parallel for schedule(runtime)
	for (int i = 0; i < 10; ++i)			for (int i = 0; i < 10; ++i)
	;			;
	#pragma omp target teams distribute parallel for schedule(dynamic)			#pragma omp target teams distribute parallel for schedule(dynamic)
	for (int i = 0; i < 10; ++i)			for (int i = 0; i < 10; ++i)
	;			;
	#pragma omp target teams distribute parallel for schedule(guided)			#pragma omp target teams distribute parallel for schedule(guided)
	for (int i = 0; i < 10; ++i)			for (int i = 0; i < 10; ++i)
	;			;
	// CHECK: call i32 @__kmpc_target_init({{.*}}, i8 2, i1 false, i1 true)			// CHECK: call i32 @__kmpc_target_init({{.*}}, i1 true)
	// CHECK: call i32 @__kmpc_target_init({{.*}}, i8 2, i1 false, i1 true)			// CHECK: call i32 @__kmpc_target_init({{.*}}, i1 true)
	// CHECK: call i32 @__kmpc_target_init({{.*}}, i8 2, i1 false, i1 true)			// CHECK: call i32 @__kmpc_target_init({{.*}}, i1 true)
	// CHECK: call i32 @__kmpc_target_init({{.*}}, i8 2, i1 false, i1 true)			// CHECK: call i32 @__kmpc_target_init({{.*}}, i1 true)
	// CHECK: call i32 @__kmpc_target_init({{.*}}, i8 2, i1 false, i1 true)			// CHECK: call i32 @__kmpc_target_init({{.*}}, i1 true)
	// CHECK: call i32 @__kmpc_target_init({{.*}}, i8 2, i1 false, i1 true)			// CHECK: call i32 @__kmpc_target_init({{.*}}, i1 true)
	// CHECK: call i32 @__kmpc_target_init({{.*}}, i8 2, i1 false, i1 true)			// CHECK: call i32 @__kmpc_target_init({{.*}}, i1 true)
	#pragma omp target teams			#pragma omp target teams
	#pragma omp distribute parallel for simd			#pragma omp distribute parallel for simd
	for (int i = 0; i < 10; ++i)			for (int i = 0; i < 10; ++i)
	;			;
	#pragma omp target teams			#pragma omp target teams
	#pragma omp distribute parallel for simd schedule(static)			#pragma omp distribute parallel for simd schedule(static)
	for (int i = 0; i < 10; ++i)			for (int i = 0; i < 10; ++i)
	;			;
	Show All 12 Lines
	#pragma omp target teams			#pragma omp target teams
	#pragma omp distribute parallel for simd schedule(dynamic)			#pragma omp distribute parallel for simd schedule(dynamic)
	for (int i = 0; i < 10; ++i)			for (int i = 0; i < 10; ++i)
	;			;
	#pragma omp target teams			#pragma omp target teams
	#pragma omp distribute parallel for simd schedule(guided)			#pragma omp distribute parallel for simd schedule(guided)
	for (int i = 0; i < 10; ++i)			for (int i = 0; i < 10; ++i)
	;			;
	// CHECK: call i32 @__kmpc_target_init({{.*}}, i8 2, i1 false, i1 true)			// CHECK: call i32 @__kmpc_target_init({{.*}}, i1 true)
	// CHECK: call i32 @__kmpc_target_init({{.*}}, i8 2, i1 false, i1 true)			// CHECK: call i32 @__kmpc_target_init({{.*}}, i1 true)
	// CHECK: call i32 @__kmpc_target_init({{.*}}, i8 2, i1 false, i1 true)			// CHECK: call i32 @__kmpc_target_init({{.*}}, i1 true)
	// CHECK: call i32 @__kmpc_target_init({{.*}}, i8 2, i1 false, i1 true)			// CHECK: call i32 @__kmpc_target_init({{.*}}, i1 true)
	// CHECK: call i32 @__kmpc_target_init({{.*}}, i8 2, i1 false, i1 true)			// CHECK: call i32 @__kmpc_target_init({{.*}}, i1 true)
	// CHECK: call i32 @__kmpc_target_init({{.*}}, i8 2, i1 false, i1 true)			// CHECK: call i32 @__kmpc_target_init({{.*}}, i1 true)
	// CHECK: call i32 @__kmpc_target_init({{.*}}, i8 2, i1 false, i1 true)			// CHECK: call i32 @__kmpc_target_init({{.*}}, i1 true)
	#pragma omp target teams			#pragma omp target teams
	#pragma omp distribute parallel for			#pragma omp distribute parallel for
	for (int i = 0; i < 10; ++i)			for (int i = 0; i < 10; ++i)
	;			;
	#pragma omp target teams			#pragma omp target teams
	#pragma omp distribute parallel for schedule(static)			#pragma omp distribute parallel for schedule(static)
	for (int i = 0; i < 10; ++i)			for (int i = 0; i < 10; ++i)
	;			;
	Show All 12 Lines
	#pragma omp target teams			#pragma omp target teams
	#pragma omp distribute parallel for schedule(dynamic)			#pragma omp distribute parallel for schedule(dynamic)
	for (int i = 0; i < 10; ++i)			for (int i = 0; i < 10; ++i)
	;			;
	#pragma omp target teams			#pragma omp target teams
	#pragma omp distribute parallel for schedule(guided)			#pragma omp distribute parallel for schedule(guided)
	for (int i = 0; i < 10; ++i)			for (int i = 0; i < 10; ++i)
	;			;
	// CHECK: call i32 @__kmpc_target_init({{.*}}, i8 2, i1 false, i1 true)			// CHECK: call i32 @__kmpc_target_init({{.*}}, i1 true)
	// CHECK: call i32 @__kmpc_target_init({{.*}}, i8 2, i1 false, i1 true)			// CHECK: call i32 @__kmpc_target_init({{.*}}, i1 true)
	// CHECK: call i32 @__kmpc_target_init({{.*}}, i8 2, i1 false, i1 true)			// CHECK: call i32 @__kmpc_target_init({{.*}}, i1 true)
	// CHECK: call i32 @__kmpc_target_init({{.*}}, i8 2, i1 false, i1 true)			// CHECK: call i32 @__kmpc_target_init({{.*}}, i1 true)
	// CHECK: call i32 @__kmpc_target_init({{.*}}, i8 2, i1 false, i1 true)			// CHECK: call i32 @__kmpc_target_init({{.*}}, i1 true)
	// CHECK: call i32 @__kmpc_target_init({{.*}}, i8 2, i1 false, i1 true)			// CHECK: call i32 @__kmpc_target_init({{.*}}, i1 true)
	// CHECK: call i32 @__kmpc_target_init({{.*}}, i8 2, i1 false, i1 true)			// CHECK: call i32 @__kmpc_target_init({{.*}}, i1 true)
	#pragma omp target			#pragma omp target
	#pragma omp teams			#pragma omp teams
	#pragma omp distribute parallel for			#pragma omp distribute parallel for
	for (int i = 0; i < 10; ++i)			for (int i = 0; i < 10; ++i)
	;			;
	#pragma omp target			#pragma omp target
	#pragma omp teams			#pragma omp teams
	#pragma omp distribute parallel for schedule(static)			#pragma omp distribute parallel for schedule(static)
	Show All 19 Lines
	#pragma omp distribute parallel for schedule(dynamic)			#pragma omp distribute parallel for schedule(dynamic)
	for (int i = 0; i < 10; ++i)			for (int i = 0; i < 10; ++i)
	;			;
	#pragma omp target			#pragma omp target
	#pragma omp teams			#pragma omp teams
	#pragma omp distribute parallel for schedule(guided)			#pragma omp distribute parallel for schedule(guided)
	for (int i = 0; i < 10; ++i)			for (int i = 0; i < 10; ++i)
	;			;
	// CHECK: call i32 @__kmpc_target_init({{.*}}, i8 2, i1 false, i1 true)			// CHECK: call i32 @__kmpc_target_init({{.*}}, i1 true)
	// CHECK: call i32 @__kmpc_target_init({{.*}}, i8 2, i1 false, i1 true)			// CHECK: call i32 @__kmpc_target_init({{.*}}, i1 true)
	// CHECK: call i32 @__kmpc_target_init({{.*}}, i8 2, i1 false, i1 true)			// CHECK: call i32 @__kmpc_target_init({{.*}}, i1 true)
	// CHECK: call i32 @__kmpc_target_init({{.*}}, i8 2, i1 false, i1 true)			// CHECK: call i32 @__kmpc_target_init({{.*}}, i1 true)
	// CHECK: call i32 @__kmpc_target_init({{.*}}, i8 2, i1 false, i1 true)			// CHECK: call i32 @__kmpc_target_init({{.*}}, i1 true)
	// CHECK: call i32 @__kmpc_target_init({{.*}}, i8 2, i1 false, i1 true)			// CHECK: call i32 @__kmpc_target_init({{.*}}, i1 true)
	// CHECK: call i32 @__kmpc_target_init({{.*}}, i8 2, i1 false, i1 true)			// CHECK: call i32 @__kmpc_target_init({{.*}}, i1 true)
	#pragma omp target parallel for			#pragma omp target parallel for
	for (int i = 0; i < 10; ++i)			for (int i = 0; i < 10; ++i)
	;			;
	#pragma omp target parallel for schedule(static)			#pragma omp target parallel for schedule(static)
	for (int i = 0; i < 10; ++i)			for (int i = 0; i < 10; ++i)
	;			;
	#pragma omp target parallel for schedule(static, 1)			#pragma omp target parallel for schedule(static, 1)
	for (int i = 0; i < 10; ++i)			for (int i = 0; i < 10; ++i)
	;			;
	#pragma omp target parallel for schedule(auto)			#pragma omp target parallel for schedule(auto)
	for (int i = 0; i < 10; ++i)			for (int i = 0; i < 10; ++i)
	;			;
	#pragma omp target parallel for schedule(runtime)			#pragma omp target parallel for schedule(runtime)
	for (int i = 0; i < 10; ++i)			for (int i = 0; i < 10; ++i)
	;			;
	#pragma omp target parallel for schedule(dynamic)			#pragma omp target parallel for schedule(dynamic)
	for (int i = 0; i < 10; ++i)			for (int i = 0; i < 10; ++i)
	;			;
	#pragma omp target parallel for schedule(guided)			#pragma omp target parallel for schedule(guided)
	for (int i = 0; i < 10; ++i)			for (int i = 0; i < 10; ++i)
	;			;
	// CHECK: call i32 @__kmpc_target_init({{.*}}, i8 2, i1 false, i1 true)			// CHECK: call i32 @__kmpc_target_init({{.*}}, i1 true)
	// CHECK: call i32 @__kmpc_target_init({{.*}}, i8 2, i1 false, i1 true)			// CHECK: call i32 @__kmpc_target_init({{.*}}, i1 true)
	// CHECK: call i32 @__kmpc_target_init({{.*}}, i8 2, i1 false, i1 true)			// CHECK: call i32 @__kmpc_target_init({{.*}}, i1 true)
	// CHECK: call i32 @__kmpc_target_init({{.*}}, i8 2, i1 false, i1 true)			// CHECK: call i32 @__kmpc_target_init({{.*}}, i1 true)
	// CHECK: call i32 @__kmpc_target_init({{.*}}, i8 2, i1 false, i1 true)			// CHECK: call i32 @__kmpc_target_init({{.*}}, i1 true)
	// CHECK: call i32 @__kmpc_target_init({{.*}}, i8 2, i1 false, i1 true)			// CHECK: call i32 @__kmpc_target_init({{.*}}, i1 true)
	// CHECK: call i32 @__kmpc_target_init({{.*}}, i8 2, i1 false, i1 true)			// CHECK: call i32 @__kmpc_target_init({{.*}}, i1 true)
	#pragma omp target parallel			#pragma omp target parallel
	#pragma omp for simd			#pragma omp for simd
	for (int i = 0; i < 10; ++i)			for (int i = 0; i < 10; ++i)
	;			;
	#pragma omp target parallel			#pragma omp target parallel
	#pragma omp for simd schedule(static)			#pragma omp for simd schedule(static)
	for (int i = 0; i < 10; ++i)			for (int i = 0; i < 10; ++i)
	;			;
	Show All 12 Lines
	#pragma omp target parallel			#pragma omp target parallel
	#pragma omp for simd schedule(dynamic)			#pragma omp for simd schedule(dynamic)
	for (int i = 0; i < 10; ++i)			for (int i = 0; i < 10; ++i)
	;			;
	#pragma omp target parallel			#pragma omp target parallel
	#pragma omp for simd schedule(guided)			#pragma omp for simd schedule(guided)
	for (int i = 0; i < 10; ++i)			for (int i = 0; i < 10; ++i)
	;			;
	// CHECK: call i32 @__kmpc_target_init({{.*}}, i8 2, i1 false, i1 true)			// CHECK: call i32 @__kmpc_target_init({{.*}}, i1 true)
	// CHECK: call i32 @__kmpc_target_init({{.*}}, i8 2, i1 false, i1 true)			// CHECK: call i32 @__kmpc_target_init({{.*}}, i1 true)
	// CHECK: call i32 @__kmpc_target_init({{.*}}, i8 2, i1 false, i1 true)			// CHECK: call i32 @__kmpc_target_init({{.*}}, i1 true)
	// CHECK: call i32 @__kmpc_target_init({{.*}}, i8 2, i1 false, i1 true)			// CHECK: call i32 @__kmpc_target_init({{.*}}, i1 true)
	// CHECK: call i32 @__kmpc_target_init({{.*}}, i8 2, i1 false, i1 true)			// CHECK: call i32 @__kmpc_target_init({{.*}}, i1 true)
	// CHECK: call i32 @__kmpc_target_init({{.*}}, i8 2, i1 false, i1 true)			// CHECK: call i32 @__kmpc_target_init({{.*}}, i1 true)
	// CHECK: call i32 @__kmpc_target_init({{.*}}, i8 2, i1 false, i1 true)			// CHECK: call i32 @__kmpc_target_init({{.*}}, i1 true)
	#pragma omp target			#pragma omp target
	#pragma omp parallel			#pragma omp parallel
	#pragma omp for simd ordered			#pragma omp for simd ordered
	for (int i = 0; i < 10; ++i)			for (int i = 0; i < 10; ++i)
	;			;
	#pragma omp target			#pragma omp target
	#pragma omp parallel			#pragma omp parallel
	#pragma omp for simd schedule(static)			#pragma omp for simd schedule(static)
	Show All 19 Lines
	#pragma omp for simd schedule(dynamic)			#pragma omp for simd schedule(dynamic)
	for (int i = 0; i < 10; ++i)			for (int i = 0; i < 10; ++i)
	;			;
	#pragma omp target			#pragma omp target
	#pragma omp parallel			#pragma omp parallel
	#pragma omp for simd schedule(guided)			#pragma omp for simd schedule(guided)
	for (int i = 0; i < 10; ++i)			for (int i = 0; i < 10; ++i)
	;			;
	// CHECK: call i32 @__kmpc_target_init({{.*}}, i8 2, i1 false, i1 true)			// CHECK: call i32 @__kmpc_target_init({{.*}}, i1 true)
	// CHECK: call i32 @__kmpc_target_init({{.*}}, i8 2, i1 false, i1 true)			// CHECK: call i32 @__kmpc_target_init({{.*}}, i1 true)
	// CHECK: call i32 @__kmpc_target_init({{.*}}, i8 2, i1 false, i1 true)			// CHECK: call i32 @__kmpc_target_init({{.*}}, i1 true)
	// CHECK: call i32 @__kmpc_target_init({{.*}}, i8 2, i1 false, i1 true)			// CHECK: call i32 @__kmpc_target_init({{.*}}, i1 true)
	// CHECK: call i32 @__kmpc_target_init({{.*}}, i8 2, i1 false, i1 true)			// CHECK: call i32 @__kmpc_target_init({{.*}}, i1 true)
	// CHECK: call i32 @__kmpc_target_init({{.*}}, i8 2, i1 false, i1 true)			// CHECK: call i32 @__kmpc_target_init({{.*}}, i1 true)
	// CHECK: call i32 @__kmpc_target_init({{.*}}, i8 2, i1 false, i1 true)			// CHECK: call i32 @__kmpc_target_init({{.*}}, i1 true)
	#pragma omp target			#pragma omp target
	#pragma omp parallel for			#pragma omp parallel for
	for (int i = 0; i < 10; ++i)			for (int i = 0; i < 10; ++i)
	;			;
	#pragma omp target			#pragma omp target
	#pragma omp parallel for schedule(static)			#pragma omp parallel for schedule(static)
	for (int i = 0; i < 10; ++i)			for (int i = 0; i < 10; ++i)
	;			;
	Show All 24 Lines

clang/test/OpenMP/nvptx_lambda_capturing.cpp

	Show First 20 Lines • Show All 765 Lines • ▼ Show 20 Lines
	// CHECK2-NEXT: [[TMP:%.]] = alloca %class.anon, align 8			// CHECK2-NEXT: [[TMP:%.]] = alloca %class.anon, align 8
	// CHECK2-NEXT: [[L1:%.]] = alloca [[CLASS_ANON:%.]], align 8			// CHECK2-NEXT: [[L1:%.]] = alloca [[CLASS_ANON:%.]], align 8
	// CHECK2-NEXT: [[_TMP2:%.]] = alloca %class.anon, align 8			// CHECK2-NEXT: [[_TMP2:%.]] = alloca %class.anon, align 8
	// CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8			// CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
	// CHECK2-NEXT: store %class.anon* [[L]], %class.anon** [[L_ADDR]], align 8			// CHECK2-NEXT: store %class.anon* [[L]], %class.anon** [[L_ADDR]], align 8
	// CHECK2-NEXT: [[TMP0:%.]] = load %struct.S, %struct.S** [[THIS_ADDR]], align 8			// CHECK2-NEXT: [[TMP0:%.]] = load %struct.S, %struct.S** [[THIS_ADDR]], align 8
	// CHECK2-NEXT: [[TMP1:%.]] = load %class.anon, %class.anon** [[L_ADDR]], align 8			// CHECK2-NEXT: [[TMP1:%.]] = load %class.anon, %class.anon** [[L_ADDR]], align 8
	// CHECK2-NEXT: store %class.anon* [[TMP1]], %class.anon** [[TMP]], align 8			// CHECK2-NEXT: store %class.anon* [[TMP1]], %class.anon** [[TMP]], align 8
	// CHECK2-NEXT: [[TMP2:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1:[0-9]+]], i8 1, i1 true, i1 true)			// CHECK2-NEXT: [[TMP2:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN1S3fooEv_l27_kernel_info, i1 true)
	// CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP2]], -1			// CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP2]], -1
	// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]			// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
	// CHECK2: user_code.entry:			// CHECK2: user_code.entry:
	// CHECK2-NEXT: [[TMP3:%.]] = load %class.anon, %class.anon** [[TMP]], align 8			// CHECK2-NEXT: [[TMP3:%.]] = load %class.anon, %class.anon** [[TMP]], align 8
	// CHECK2-NEXT: [[TMP4:%.]] = bitcast %class.anon [[L1]] to i8*			// CHECK2-NEXT: [[TMP4:%.]] = bitcast %class.anon [[L1]] to i8*
	// CHECK2-NEXT: [[TMP5:%.]] = bitcast %class.anon [[TMP3]] to i8*			// CHECK2-NEXT: [[TMP5:%.]] = bitcast %class.anon [[TMP3]] to i8*
	// CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP4]], i8* align 8 [[TMP5]], i64 8, i1 false)			// CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP4]], i8* align 8 [[TMP5]], i64 8, i1 false)
	// CHECK2-NEXT: store %class.anon* [[L1]], %class.anon** [[_TMP2]], align 8			// CHECK2-NEXT: store %class.anon* [[L1]], %class.anon** [[_TMP2]], align 8
	// CHECK2-NEXT: [[TMP6:%.]] = load %class.anon, %class.anon** [[_TMP2]], align 8			// CHECK2-NEXT: [[TMP6:%.]] = load %class.anon, %class.anon** [[_TMP2]], align 8
	// CHECK2-NEXT: [[TMP7:%.]] = getelementptr inbounds [[CLASS_ANON]], %class.anon [[TMP6]], i32 0, i32 0			// CHECK2-NEXT: [[TMP7:%.]] = getelementptr inbounds [[CLASS_ANON]], %class.anon [[TMP6]], i32 0, i32 0
	// CHECK2-NEXT: store %struct.S* [[TMP0]], %struct.S** [[TMP7]], align 8			// CHECK2-NEXT: store %struct.S* [[TMP0]], %struct.S** [[TMP7]], align 8
	// CHECK2-NEXT: [[TMP8:%.]] = load %class.anon, %class.anon** [[_TMP2]], align 8			// CHECK2-NEXT: [[TMP8:%.]] = load %class.anon, %class.anon** [[_TMP2]], align 8
	// CHECK2-NEXT: [[CALL:%.]] = call i32 @_ZZN1S3fooEvENKUlvE_clEv(%class.anon nonnull align 8 dereferenceable(8) [[TMP8]]) #[[ATTR6:[0-9]+]]			// CHECK2-NEXT: [[CALL:%.]] = call i32 @_ZZN1S3fooEvENKUlvE_clEv(%class.anon nonnull align 8 dereferenceable(8) [[TMP8]]) #[[ATTR6:[0-9]+]]
	// CHECK2-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true)			// CHECK2-NEXT: call void @__kmpc_target_deinit(i1 true)
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	// CHECK2: worker.exit:			// CHECK2: worker.exit:
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@_ZZN1S3fooEvENKUlvE_clEv			// CHECK2-LABEL: define {{[^@]+}}@_ZZN1S3fooEvENKUlvE_clEv
	// CHECK2-SAME: (%class.anon* nonnull align 8 dereferenceable(8) [[THIS:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 {			// CHECK2-SAME: (%class.anon* nonnull align 8 dereferenceable(8) [[THIS:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	Show All 14 Lines
	// CHECK2-NEXT: [[L_ADDR:%.]] = alloca %class.anon, align 8			// CHECK2-NEXT: [[L_ADDR:%.]] = alloca %class.anon, align 8
	// CHECK2-NEXT: [[TMP:%.]] = alloca %class.anon, align 8			// CHECK2-NEXT: [[TMP:%.]] = alloca %class.anon, align 8
	// CHECK2-NEXT: [[CAPTURED_VARS_ADDRS:%.]] = alloca [2 x i8], align 8			// CHECK2-NEXT: [[CAPTURED_VARS_ADDRS:%.]] = alloca [2 x i8], align 8
	// CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8			// CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
	// CHECK2-NEXT: store %class.anon* [[L]], %class.anon** [[L_ADDR]], align 8			// CHECK2-NEXT: store %class.anon* [[L]], %class.anon** [[L_ADDR]], align 8
	// CHECK2-NEXT: [[TMP0:%.]] = load %struct.S, %struct.S** [[THIS_ADDR]], align 8			// CHECK2-NEXT: [[TMP0:%.]] = load %struct.S, %struct.S** [[THIS_ADDR]], align 8
	// CHECK2-NEXT: [[TMP1:%.]] = load %class.anon, %class.anon** [[L_ADDR]], align 8			// CHECK2-NEXT: [[TMP1:%.]] = load %class.anon, %class.anon** [[L_ADDR]], align 8
	// CHECK2-NEXT: store %class.anon* [[TMP1]], %class.anon** [[TMP]], align 8			// CHECK2-NEXT: store %class.anon* [[TMP1]], %class.anon** [[TMP]], align 8
	// CHECK2-NEXT: [[TMP2:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 2, i1 false, i1 true)			// CHECK2-NEXT: [[TMP2:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN1S3fooEv_l29_kernel_info, i1 true)
	// CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP2]], -1			// CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP2]], -1
	// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]			// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
	// CHECK2: user_code.entry:			// CHECK2: user_code.entry:
	// CHECK2-NEXT: [[TMP3:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB2:[0-9]+]])			// CHECK2-NEXT: [[TMP3:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB1:[0-9]+]])
	// CHECK2-NEXT: [[TMP4:%.]] = load %class.anon, %class.anon** [[TMP]], align 8			// CHECK2-NEXT: [[TMP4:%.]] = load %class.anon, %class.anon** [[TMP]], align 8
	// CHECK2-NEXT: [[TMP5:%.]] = getelementptr inbounds [2 x i8], [2 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 0			// CHECK2-NEXT: [[TMP5:%.]] = getelementptr inbounds [2 x i8], [2 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
	// CHECK2-NEXT: [[TMP6:%.]] = bitcast %struct.S [[TMP0]] to i8*			// CHECK2-NEXT: [[TMP6:%.]] = bitcast %struct.S [[TMP0]] to i8*
	// CHECK2-NEXT: store i8* [[TMP6]], i8** [[TMP5]], align 8			// CHECK2-NEXT: store i8* [[TMP6]], i8** [[TMP5]], align 8
	// CHECK2-NEXT: [[TMP7:%.]] = getelementptr inbounds [2 x i8], [2 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 1			// CHECK2-NEXT: [[TMP7:%.]] = getelementptr inbounds [2 x i8], [2 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
	// CHECK2-NEXT: [[TMP8:%.]] = bitcast %class.anon [[TMP4]] to i8*			// CHECK2-NEXT: [[TMP8:%.]] = bitcast %class.anon [[TMP4]] to i8*
	// CHECK2-NEXT: store i8* [[TMP8]], i8** [[TMP7]], align 8			// CHECK2-NEXT: store i8* [[TMP8]], i8** [[TMP7]], align 8
	// CHECK2-NEXT: [[TMP9:%.]] = bitcast [2 x i8]* [[CAPTURED_VARS_ADDRS]] to i8**			// CHECK2-NEXT: [[TMP9:%.]] = bitcast [2 x i8]* [[CAPTURED_VARS_ADDRS]] to i8**
	// CHECK2-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32, i32, %struct.S, %class.anon)* @__omp_outlined__ to i8), i8 null, i8** [[TMP9]], i64 2)			// CHECK2-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32, i32, %struct.S, %class.anon)* @__omp_outlined__ to i8), i8 null, i8** [[TMP9]], i64 2)
	// CHECK2-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 true)			// CHECK2-NEXT: call void @__kmpc_target_deinit(i1 true)
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	// CHECK2: worker.exit:			// CHECK2: worker.exit:
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__			// CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__
	// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], %struct.S [[THIS:%.]], %class.anon nonnull align 8 dereferenceable(8) [[L:%.*]]) #[[ATTR0]] {			// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], %struct.S [[THIS:%.]], %class.anon nonnull align 8 dereferenceable(8) [[L:%.*]]) #[[ATTR0]] {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	▲ Show 20 Lines • Show All 51 Lines • ▼ Show 20 Lines
	// CHECK2-NEXT: [[CONV:%.]] = bitcast i64 [[ARGC_ADDR]] to i32*			// CHECK2-NEXT: [[CONV:%.]] = bitcast i64 [[ARGC_ADDR]] to i32*
	// CHECK2-NEXT: [[TMP0:%.]] = load i32, i32** [[B_ADDR]], align 8			// CHECK2-NEXT: [[TMP0:%.]] = load i32, i32** [[B_ADDR]], align 8
	// CHECK2-NEXT: [[TMP1:%.]] = load i32, i32** [[C_ADDR]], align 8			// CHECK2-NEXT: [[TMP1:%.]] = load i32, i32** [[C_ADDR]], align 8
	// CHECK2-NEXT: [[TMP2:%.]] = load i32, i32** [[A_ADDR]], align 8			// CHECK2-NEXT: [[TMP2:%.]] = load i32, i32** [[A_ADDR]], align 8
	// CHECK2-NEXT: [[TMP3:%.]] = load %class.anon.0, %class.anon.0** [[L_ADDR]], align 8			// CHECK2-NEXT: [[TMP3:%.]] = load %class.anon.0, %class.anon.0** [[L_ADDR]], align 8
	// CHECK2-NEXT: store i32* [[TMP0]], i32** [[TMP]], align 8			// CHECK2-NEXT: store i32* [[TMP0]], i32** [[TMP]], align 8
	// CHECK2-NEXT: store i32* [[TMP1]], i32** [[_TMP1]], align 8			// CHECK2-NEXT: store i32* [[TMP1]], i32** [[_TMP1]], align 8
	// CHECK2-NEXT: store %class.anon.0* [[TMP3]], %class.anon.0** [[_TMP2]], align 8			// CHECK2-NEXT: store %class.anon.0* [[TMP3]], %class.anon.0** [[_TMP2]], align 8
	// CHECK2-NEXT: [[TMP4:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 1, i1 true, i1 true)			// CHECK2-NEXT: [[TMP4:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l41_kernel_info, i1 true)
	// CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP4]], -1			// CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP4]], -1
	// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]			// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
	// CHECK2: user_code.entry:			// CHECK2: user_code.entry:
	// CHECK2-NEXT: [[TMP5:%.]] = load %class.anon.0, %class.anon.0** [[_TMP2]], align 8			// CHECK2-NEXT: [[TMP5:%.]] = load %class.anon.0, %class.anon.0** [[_TMP2]], align 8
	// CHECK2-NEXT: [[TMP6:%.]] = bitcast %class.anon.0 [[L3]] to i8*			// CHECK2-NEXT: [[TMP6:%.]] = bitcast %class.anon.0 [[L3]] to i8*
	// CHECK2-NEXT: [[TMP7:%.]] = bitcast %class.anon.0 [[TMP5]] to i8*			// CHECK2-NEXT: [[TMP7:%.]] = bitcast %class.anon.0 [[TMP5]] to i8*
	// CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP6]], i8* align 8 [[TMP7]], i64 40, i1 false)			// CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP6]], i8* align 8 [[TMP7]], i64 40, i1 false)
	// CHECK2-NEXT: store %class.anon.0* [[L3]], %class.anon.0** [[_TMP4]], align 8			// CHECK2-NEXT: store %class.anon.0* [[L3]], %class.anon.0** [[_TMP4]], align 8
	Show All 15 Lines
	// CHECK2-NEXT: [[TMP17:%.]] = load i32, i32** [[_TMP8]], align 8			// CHECK2-NEXT: [[TMP17:%.]] = load i32, i32** [[_TMP8]], align 8
	// CHECK2-NEXT: store i32* [[TMP17]], i32** [[TMP16]], align 8			// CHECK2-NEXT: store i32* [[TMP17]], i32** [[TMP16]], align 8
	// CHECK2-NEXT: [[TMP18:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[TMP12]], i32 0, i32 3			// CHECK2-NEXT: [[TMP18:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[TMP12]], i32 0, i32 3
	// CHECK2-NEXT: store i32 [[D_ADDR]], i32* [[TMP18]], align 8			// CHECK2-NEXT: store i32 [[D_ADDR]], i32* [[TMP18]], align 8
	// CHECK2-NEXT: [[TMP19:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[TMP12]], i32 0, i32 4			// CHECK2-NEXT: [[TMP19:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[TMP12]], i32 0, i32 4
	// CHECK2-NEXT: store i32* [[TMP2]], i32** [[TMP19]], align 8			// CHECK2-NEXT: store i32* [[TMP2]], i32** [[TMP19]], align 8
	// CHECK2-NEXT: [[TMP20:%.]] = load %class.anon.0, %class.anon.0** [[_TMP4]], align 8			// CHECK2-NEXT: [[TMP20:%.]] = load %class.anon.0, %class.anon.0** [[_TMP4]], align 8
	// CHECK2-NEXT: [[CALL:%.]] = call i64 @"_ZZ4mainENK3$_0clEv"(%class.anon.0 nonnull align 8 dereferenceable(40) [[TMP20]]) #[[ATTR6]]			// CHECK2-NEXT: [[CALL:%.]] = call i64 @"_ZZ4mainENK3$_0clEv"(%class.anon.0 nonnull align 8 dereferenceable(40) [[TMP20]]) #[[ATTR6]]
	// CHECK2-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true)			// CHECK2-NEXT: call void @__kmpc_target_deinit(i1 true)
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	// CHECK2: worker.exit:			// CHECK2: worker.exit:
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l43			// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l43
	// CHECK2-SAME: (i32* nonnull align 4 dereferenceable(4) [[ARGC:%.]], i32 nonnull align 4 dereferenceable(4) [[B:%.]], i32 nonnull align 4 dereferenceable(4) [[C:%.]], i32 [[D:%.]], i32 nonnull align 4 dereferenceable(4) [[A:%.]], %class.anon.0 nonnull align 8 dereferenceable(40) [[L:%.*]]) #[[ATTR3]] {			// CHECK2-SAME: (i32* nonnull align 4 dereferenceable(4) [[ARGC:%.]], i32 nonnull align 4 dereferenceable(4) [[B:%.]], i32 nonnull align 4 dereferenceable(4) [[C:%.]], i32 [[D:%.]], i32 nonnull align 4 dereferenceable(4) [[A:%.]], %class.anon.0 nonnull align 8 dereferenceable(40) [[L:%.*]]) #[[ATTR3]] {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
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	// CHECK2-NEXT: [[TMP0:%.]] = load i32, i32** [[ARGC_ADDR]], align 8			// CHECK2-NEXT: [[TMP0:%.]] = load i32, i32** [[ARGC_ADDR]], align 8
	// CHECK2-NEXT: [[TMP1:%.]] = load i32, i32** [[B_ADDR]], align 8			// CHECK2-NEXT: [[TMP1:%.]] = load i32, i32** [[B_ADDR]], align 8
	// CHECK2-NEXT: [[TMP2:%.]] = load i32, i32** [[C_ADDR]], align 8			// CHECK2-NEXT: [[TMP2:%.]] = load i32, i32** [[C_ADDR]], align 8
	// CHECK2-NEXT: [[TMP3:%.]] = load i32, i32** [[A_ADDR]], align 8			// CHECK2-NEXT: [[TMP3:%.]] = load i32, i32** [[A_ADDR]], align 8
	// CHECK2-NEXT: [[TMP4:%.]] = load %class.anon.0, %class.anon.0** [[L_ADDR]], align 8			// CHECK2-NEXT: [[TMP4:%.]] = load %class.anon.0, %class.anon.0** [[L_ADDR]], align 8
	// CHECK2-NEXT: store i32* [[TMP1]], i32** [[TMP]], align 8			// CHECK2-NEXT: store i32* [[TMP1]], i32** [[TMP]], align 8
	// CHECK2-NEXT: store i32* [[TMP2]], i32** [[_TMP1]], align 8			// CHECK2-NEXT: store i32* [[TMP2]], i32** [[_TMP1]], align 8
	// CHECK2-NEXT: store %class.anon.0* [[TMP4]], %class.anon.0** [[_TMP2]], align 8			// CHECK2-NEXT: store %class.anon.0* [[TMP4]], %class.anon.0** [[_TMP2]], align 8
	// CHECK2-NEXT: [[TMP5:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 2, i1 false, i1 true)			// CHECK2-NEXT: [[TMP5:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l43_kernel_info, i1 true)
	// CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP5]], -1			// CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP5]], -1
	// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]			// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
	// CHECK2: user_code.entry:			// CHECK2: user_code.entry:
	// CHECK2-NEXT: [[TMP6:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB2]])			// CHECK2-NEXT: [[TMP6:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB1]])
	// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32** [[TMP]], align 8			// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32** [[TMP]], align 8
	// CHECK2-NEXT: [[TMP8:%.]] = load i32, i32** [[_TMP1]], align 8			// CHECK2-NEXT: [[TMP8:%.]] = load i32, i32** [[_TMP1]], align 8
	// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32** [[D_ADDR]], align 8			// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32** [[D_ADDR]], align 8
	// CHECK2-NEXT: [[TMP10:%.]] = load %class.anon.0, %class.anon.0** [[_TMP2]], align 8			// CHECK2-NEXT: [[TMP10:%.]] = load %class.anon.0, %class.anon.0** [[_TMP2]], align 8
	// CHECK2-NEXT: [[TMP11:%.]] = getelementptr inbounds [6 x i8], [6 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 0			// CHECK2-NEXT: [[TMP11:%.]] = getelementptr inbounds [6 x i8], [6 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
	// CHECK2-NEXT: [[TMP12:%.]] = bitcast i32 [[TMP0]] to i8*			// CHECK2-NEXT: [[TMP12:%.]] = bitcast i32 [[TMP0]] to i8*
	// CHECK2-NEXT: store i8* [[TMP12]], i8** [[TMP11]], align 8			// CHECK2-NEXT: store i8* [[TMP12]], i8** [[TMP11]], align 8
	// CHECK2-NEXT: [[TMP13:%.]] = getelementptr inbounds [6 x i8], [6 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 1			// CHECK2-NEXT: [[TMP13:%.]] = getelementptr inbounds [6 x i8], [6 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
	// CHECK2-NEXT: [[TMP14:%.]] = bitcast i32 [[TMP7]] to i8*			// CHECK2-NEXT: [[TMP14:%.]] = bitcast i32 [[TMP7]] to i8*
	// CHECK2-NEXT: store i8* [[TMP14]], i8** [[TMP13]], align 8			// CHECK2-NEXT: store i8* [[TMP14]], i8** [[TMP13]], align 8
	// CHECK2-NEXT: [[TMP15:%.]] = getelementptr inbounds [6 x i8], [6 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 2			// CHECK2-NEXT: [[TMP15:%.]] = getelementptr inbounds [6 x i8], [6 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 2
	// CHECK2-NEXT: [[TMP16:%.]] = bitcast i32 [[TMP8]] to i8*			// CHECK2-NEXT: [[TMP16:%.]] = bitcast i32 [[TMP8]] to i8*
	// CHECK2-NEXT: store i8* [[TMP16]], i8** [[TMP15]], align 8			// CHECK2-NEXT: store i8* [[TMP16]], i8** [[TMP15]], align 8
	// CHECK2-NEXT: [[TMP17:%.]] = getelementptr inbounds [6 x i8], [6 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 3			// CHECK2-NEXT: [[TMP17:%.]] = getelementptr inbounds [6 x i8], [6 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 3
	// CHECK2-NEXT: [[TMP18:%.]] = bitcast i32 [[TMP9]] to i8*			// CHECK2-NEXT: [[TMP18:%.]] = bitcast i32 [[TMP9]] to i8*
	// CHECK2-NEXT: store i8* [[TMP18]], i8** [[TMP17]], align 8			// CHECK2-NEXT: store i8* [[TMP18]], i8** [[TMP17]], align 8
	// CHECK2-NEXT: [[TMP19:%.]] = getelementptr inbounds [6 x i8], [6 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 4			// CHECK2-NEXT: [[TMP19:%.]] = getelementptr inbounds [6 x i8], [6 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 4
	// CHECK2-NEXT: [[TMP20:%.]] = bitcast i32 [[TMP3]] to i8*			// CHECK2-NEXT: [[TMP20:%.]] = bitcast i32 [[TMP3]] to i8*
	// CHECK2-NEXT: store i8* [[TMP20]], i8** [[TMP19]], align 8			// CHECK2-NEXT: store i8* [[TMP20]], i8** [[TMP19]], align 8
	// CHECK2-NEXT: [[TMP21:%.]] = getelementptr inbounds [6 x i8], [6 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 5			// CHECK2-NEXT: [[TMP21:%.]] = getelementptr inbounds [6 x i8], [6 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 5
	// CHECK2-NEXT: [[TMP22:%.]] = bitcast %class.anon.0 [[TMP10]] to i8*			// CHECK2-NEXT: [[TMP22:%.]] = bitcast %class.anon.0 [[TMP10]] to i8*
	// CHECK2-NEXT: store i8* [[TMP22]], i8** [[TMP21]], align 8			// CHECK2-NEXT: store i8* [[TMP22]], i8** [[TMP21]], align 8
	// CHECK2-NEXT: [[TMP23:%.]] = bitcast [6 x i8]* [[CAPTURED_VARS_ADDRS]] to i8**			// CHECK2-NEXT: [[TMP23:%.]] = bitcast [6 x i8]* [[CAPTURED_VARS_ADDRS]] to i8**
	// CHECK2-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP6]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32, i32, i32, i32, i32, i32, i32, %class.anon.0)* @__omp_outlined__1 to i8), i8 null, i8** [[TMP23]], i64 6)			// CHECK2-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32, i32, i32, i32, i32, i32, i32, %class.anon.0)* @__omp_outlined__1 to i8), i8 null, i8** [[TMP23]], i64 6)
	// CHECK2-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 true)			// CHECK2-NEXT: call void @__kmpc_target_deinit(i1 true)
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	// CHECK2: worker.exit:			// CHECK2: worker.exit:
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__1			// CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__1
	// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i32 nonnull align 4 dereferenceable(4) [[ARGC:%.]], i32 nonnull align 4 dereferenceable(4) [[B:%.]], i32 nonnull align 4 dereferenceable(4) [[C:%.]], i32 [[D:%.]], i32 nonnull align 4 dereferenceable(4) [[A:%.]], %class.anon.0 nonnull align 8 dereferenceable(40) [[L:%.*]]) #[[ATTR0]] {			// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i32 nonnull align 4 dereferenceable(4) [[ARGC:%.]], i32 nonnull align 4 dereferenceable(4) [[B:%.]], i32 nonnull align 4 dereferenceable(4) [[C:%.]], i32 [[D:%.]], i32 nonnull align 4 dereferenceable(4) [[A:%.]], %class.anon.0 nonnull align 8 dereferenceable(40) [[L:%.*]]) #[[ATTR0]] {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
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	// CHECK2-SAME: (%class.anon* nonnull align 8 dereferenceable(8) [[T:%.*]]) #[[ATTR3]] {			// CHECK2-SAME: (%class.anon* nonnull align 8 dereferenceable(8) [[T:%.*]]) #[[ATTR3]] {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	// CHECK2-NEXT: [[T_ADDR:%.]] = alloca %class.anon, align 8			// CHECK2-NEXT: [[T_ADDR:%.]] = alloca %class.anon, align 8
	// CHECK2-NEXT: [[TMP:%.]] = alloca %class.anon, align 8			// CHECK2-NEXT: [[TMP:%.]] = alloca %class.anon, align 8
	// CHECK2-NEXT: [[CAPTURED_VARS_ADDRS:%.]] = alloca [1 x i8], align 8			// CHECK2-NEXT: [[CAPTURED_VARS_ADDRS:%.]] = alloca [1 x i8], align 8
	// CHECK2-NEXT: store %class.anon* [[T]], %class.anon** [[T_ADDR]], align 8			// CHECK2-NEXT: store %class.anon* [[T]], %class.anon** [[T_ADDR]], align 8
	// CHECK2-NEXT: [[TMP0:%.]] = load %class.anon, %class.anon** [[T_ADDR]], align 8			// CHECK2-NEXT: [[TMP0:%.]] = load %class.anon, %class.anon** [[T_ADDR]], align 8
	// CHECK2-NEXT: store %class.anon* [[TMP0]], %class.anon** [[TMP]], align 8			// CHECK2-NEXT: store %class.anon* [[TMP0]], %class.anon** [[TMP]], align 8
	// CHECK2-NEXT: [[TMP1:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 2, i1 false, i1 true)			// CHECK2-NEXT: [[TMP1:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIZN1S3fooEvEUlvE_EiRKT__l18_kernel_info, i1 true)
	// CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1			// CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
	// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]			// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
	// CHECK2: user_code.entry:			// CHECK2: user_code.entry:
	// CHECK2-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB2]])			// CHECK2-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB1]])
	// CHECK2-NEXT: [[TMP3:%.]] = load %class.anon, %class.anon** [[TMP]], align 8			// CHECK2-NEXT: [[TMP3:%.]] = load %class.anon, %class.anon** [[TMP]], align 8
	// CHECK2-NEXT: [[TMP4:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 0			// CHECK2-NEXT: [[TMP4:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
	// CHECK2-NEXT: [[TMP5:%.]] = bitcast %class.anon [[TMP3]] to i8*			// CHECK2-NEXT: [[TMP5:%.]] = bitcast %class.anon [[TMP3]] to i8*
	// CHECK2-NEXT: store i8* [[TMP5]], i8** [[TMP4]], align 8			// CHECK2-NEXT: store i8* [[TMP5]], i8** [[TMP4]], align 8
	// CHECK2-NEXT: [[TMP6:%.]] = bitcast [1 x i8]* [[CAPTURED_VARS_ADDRS]] to i8**			// CHECK2-NEXT: [[TMP6:%.]] = bitcast [1 x i8]* [[CAPTURED_VARS_ADDRS]] to i8**
	// CHECK2-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32, i32, %class.anon) @__omp_outlined__2 to i8), i8 null, i8** [[TMP6]], i64 1)			// CHECK2-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32, i32, %class.anon) @__omp_outlined__2 to i8), i8 null, i8** [[TMP6]], i64 1)
	// CHECK2-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 true)			// CHECK2-NEXT: call void @__kmpc_target_deinit(i1 true)
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	// CHECK2: worker.exit:			// CHECK2: worker.exit:
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__2			// CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__2
	// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], %class.anon nonnull align 8 dereferenceable(8) [[T:%.*]]) #[[ATTR0]] {			// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], %class.anon nonnull align 8 dereferenceable(8) [[T:%.*]]) #[[ATTR0]] {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
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	// CHECK3-NEXT: [[CONV:%.]] = bitcast i64 [[ARGC_ADDR]] to i32*			// CHECK3-NEXT: [[CONV:%.]] = bitcast i64 [[ARGC_ADDR]] to i32*
	// CHECK3-NEXT: [[TMP0:%.]] = load i32, i32** [[B_ADDR]], align 8			// CHECK3-NEXT: [[TMP0:%.]] = load i32, i32** [[B_ADDR]], align 8
	// CHECK3-NEXT: [[TMP1:%.]] = load i32, i32** [[C_ADDR]], align 8			// CHECK3-NEXT: [[TMP1:%.]] = load i32, i32** [[C_ADDR]], align 8
	// CHECK3-NEXT: [[TMP2:%.]] = load i32, i32** [[A_ADDR]], align 8			// CHECK3-NEXT: [[TMP2:%.]] = load i32, i32** [[A_ADDR]], align 8
	// CHECK3-NEXT: [[TMP3:%.]] = load %class.anon, %class.anon** [[L_ADDR]], align 8			// CHECK3-NEXT: [[TMP3:%.]] = load %class.anon, %class.anon** [[L_ADDR]], align 8
	// CHECK3-NEXT: store i32* [[TMP0]], i32** [[TMP]], align 8			// CHECK3-NEXT: store i32* [[TMP0]], i32** [[TMP]], align 8
	// CHECK3-NEXT: store i32* [[TMP1]], i32** [[_TMP1]], align 8			// CHECK3-NEXT: store i32* [[TMP1]], i32** [[_TMP1]], align 8
	// CHECK3-NEXT: store %class.anon* [[TMP3]], %class.anon** [[_TMP2]], align 8			// CHECK3-NEXT: store %class.anon* [[TMP3]], %class.anon** [[_TMP2]], align 8
	// CHECK3-NEXT: [[TMP4:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1:[0-9]+]], i8 1, i1 true, i1 true)			// CHECK3-NEXT: [[TMP4:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l41_kernel_info, i1 true)
	// CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP4]], -1			// CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP4]], -1
	// CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]			// CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
	// CHECK3: user_code.entry:			// CHECK3: user_code.entry:
	// CHECK3-NEXT: [[TMP5:%.]] = load %class.anon, %class.anon** [[_TMP2]], align 8			// CHECK3-NEXT: [[TMP5:%.]] = load %class.anon, %class.anon** [[_TMP2]], align 8
	// CHECK3-NEXT: [[TMP6:%.]] = bitcast %class.anon [[L3]] to i8*			// CHECK3-NEXT: [[TMP6:%.]] = bitcast %class.anon [[L3]] to i8*
	// CHECK3-NEXT: [[TMP7:%.]] = bitcast %class.anon [[TMP5]] to i8*			// CHECK3-NEXT: [[TMP7:%.]] = bitcast %class.anon [[TMP5]] to i8*
	// CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP6]], i8* align 8 [[TMP7]], i64 40, i1 false)			// CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP6]], i8* align 8 [[TMP7]], i64 40, i1 false)
	// CHECK3-NEXT: store %class.anon* [[L3]], %class.anon** [[_TMP4]], align 8			// CHECK3-NEXT: store %class.anon* [[L3]], %class.anon** [[_TMP4]], align 8
	Show All 15 Lines
	// CHECK3-NEXT: [[TMP17:%.]] = load i32, i32** [[_TMP8]], align 8			// CHECK3-NEXT: [[TMP17:%.]] = load i32, i32** [[_TMP8]], align 8
	// CHECK3-NEXT: store i32* [[TMP17]], i32** [[TMP16]], align 8			// CHECK3-NEXT: store i32* [[TMP17]], i32** [[TMP16]], align 8
	// CHECK3-NEXT: [[TMP18:%.]] = getelementptr inbounds [[CLASS_ANON]], %class.anon [[TMP12]], i32 0, i32 3			// CHECK3-NEXT: [[TMP18:%.]] = getelementptr inbounds [[CLASS_ANON]], %class.anon [[TMP12]], i32 0, i32 3
	// CHECK3-NEXT: store i32 [[D_ADDR]], i32* [[TMP18]], align 8			// CHECK3-NEXT: store i32 [[D_ADDR]], i32* [[TMP18]], align 8
	// CHECK3-NEXT: [[TMP19:%.]] = getelementptr inbounds [[CLASS_ANON]], %class.anon [[TMP12]], i32 0, i32 4			// CHECK3-NEXT: [[TMP19:%.]] = getelementptr inbounds [[CLASS_ANON]], %class.anon [[TMP12]], i32 0, i32 4
	// CHECK3-NEXT: store i32* [[TMP2]], i32** [[TMP19]], align 8			// CHECK3-NEXT: store i32* [[TMP2]], i32** [[TMP19]], align 8
	// CHECK3-NEXT: [[TMP20:%.]] = load %class.anon, %class.anon** [[_TMP4]], align 8			// CHECK3-NEXT: [[TMP20:%.]] = load %class.anon, %class.anon** [[_TMP4]], align 8
	// CHECK3-NEXT: [[CALL:%.]] = call i64 @"_ZZ4mainENK3$_0clEv"(%class.anon nonnull align 8 dereferenceable(40) [[TMP20]]) #[[ATTR6:[0-9]+]]			// CHECK3-NEXT: [[CALL:%.]] = call i64 @"_ZZ4mainENK3$_0clEv"(%class.anon nonnull align 8 dereferenceable(40) [[TMP20]]) #[[ATTR6:[0-9]+]]
	// CHECK3-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true)			// CHECK3-NEXT: call void @__kmpc_target_deinit(i1 true)
	// CHECK3-NEXT: ret void			// CHECK3-NEXT: ret void
	// CHECK3: worker.exit:			// CHECK3: worker.exit:
	// CHECK3-NEXT: ret void			// CHECK3-NEXT: ret void
	//			//
	//			//
	// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l43			// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l43
	// CHECK3-SAME: (i32* nonnull align 4 dereferenceable(4) [[ARGC:%.]], i32 nonnull align 4 dereferenceable(4) [[B:%.]], i32 nonnull align 4 dereferenceable(4) [[C:%.]], i32 [[D:%.]], i32 nonnull align 4 dereferenceable(4) [[A:%.]], %class.anon nonnull align 8 dereferenceable(40) [[L:%.*]]) #[[ATTR3:[0-9]+]] {			// CHECK3-SAME: (i32* nonnull align 4 dereferenceable(4) [[ARGC:%.]], i32 nonnull align 4 dereferenceable(4) [[B:%.]], i32 nonnull align 4 dereferenceable(4) [[C:%.]], i32 [[D:%.]], i32 nonnull align 4 dereferenceable(4) [[A:%.]], %class.anon nonnull align 8 dereferenceable(40) [[L:%.*]]) #[[ATTR3:[0-9]+]] {
	// CHECK3-NEXT: entry:			// CHECK3-NEXT: entry:
	Show All 16 Lines
	// CHECK3-NEXT: [[TMP0:%.]] = load i32, i32** [[ARGC_ADDR]], align 8			// CHECK3-NEXT: [[TMP0:%.]] = load i32, i32** [[ARGC_ADDR]], align 8
	// CHECK3-NEXT: [[TMP1:%.]] = load i32, i32** [[B_ADDR]], align 8			// CHECK3-NEXT: [[TMP1:%.]] = load i32, i32** [[B_ADDR]], align 8
	// CHECK3-NEXT: [[TMP2:%.]] = load i32, i32** [[C_ADDR]], align 8			// CHECK3-NEXT: [[TMP2:%.]] = load i32, i32** [[C_ADDR]], align 8
	// CHECK3-NEXT: [[TMP3:%.]] = load i32, i32** [[A_ADDR]], align 8			// CHECK3-NEXT: [[TMP3:%.]] = load i32, i32** [[A_ADDR]], align 8
	// CHECK3-NEXT: [[TMP4:%.]] = load %class.anon, %class.anon** [[L_ADDR]], align 8			// CHECK3-NEXT: [[TMP4:%.]] = load %class.anon, %class.anon** [[L_ADDR]], align 8
	// CHECK3-NEXT: store i32* [[TMP1]], i32** [[TMP]], align 8			// CHECK3-NEXT: store i32* [[TMP1]], i32** [[TMP]], align 8
	// CHECK3-NEXT: store i32* [[TMP2]], i32** [[_TMP1]], align 8			// CHECK3-NEXT: store i32* [[TMP2]], i32** [[_TMP1]], align 8
	// CHECK3-NEXT: store %class.anon* [[TMP4]], %class.anon** [[_TMP2]], align 8			// CHECK3-NEXT: store %class.anon* [[TMP4]], %class.anon** [[_TMP2]], align 8
	// CHECK3-NEXT: [[TMP5:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 2, i1 false, i1 true)			// CHECK3-NEXT: [[TMP5:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l43_kernel_info, i1 true)
	// CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP5]], -1			// CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP5]], -1
	// CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]			// CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
	// CHECK3: user_code.entry:			// CHECK3: user_code.entry:
	// CHECK3-NEXT: [[TMP6:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB2:[0-9]+]])			// CHECK3-NEXT: [[TMP6:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB1:[0-9]+]])
	// CHECK3-NEXT: [[TMP7:%.]] = load i32, i32** [[TMP]], align 8			// CHECK3-NEXT: [[TMP7:%.]] = load i32, i32** [[TMP]], align 8
	// CHECK3-NEXT: [[TMP8:%.]] = load i32, i32** [[_TMP1]], align 8			// CHECK3-NEXT: [[TMP8:%.]] = load i32, i32** [[_TMP1]], align 8
	// CHECK3-NEXT: [[TMP9:%.]] = load i32, i32** [[D_ADDR]], align 8			// CHECK3-NEXT: [[TMP9:%.]] = load i32, i32** [[D_ADDR]], align 8
	// CHECK3-NEXT: [[TMP10:%.]] = load %class.anon, %class.anon** [[_TMP2]], align 8			// CHECK3-NEXT: [[TMP10:%.]] = load %class.anon, %class.anon** [[_TMP2]], align 8
	// CHECK3-NEXT: [[TMP11:%.]] = getelementptr inbounds [6 x i8], [6 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 0			// CHECK3-NEXT: [[TMP11:%.]] = getelementptr inbounds [6 x i8], [6 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
	// CHECK3-NEXT: [[TMP12:%.]] = bitcast i32 [[TMP0]] to i8*			// CHECK3-NEXT: [[TMP12:%.]] = bitcast i32 [[TMP0]] to i8*
	// CHECK3-NEXT: store i8* [[TMP12]], i8** [[TMP11]], align 8			// CHECK3-NEXT: store i8* [[TMP12]], i8** [[TMP11]], align 8
	// CHECK3-NEXT: [[TMP13:%.]] = getelementptr inbounds [6 x i8], [6 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 1			// CHECK3-NEXT: [[TMP13:%.]] = getelementptr inbounds [6 x i8], [6 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
	// CHECK3-NEXT: [[TMP14:%.]] = bitcast i32 [[TMP7]] to i8*			// CHECK3-NEXT: [[TMP14:%.]] = bitcast i32 [[TMP7]] to i8*
	// CHECK3-NEXT: store i8* [[TMP14]], i8** [[TMP13]], align 8			// CHECK3-NEXT: store i8* [[TMP14]], i8** [[TMP13]], align 8
	// CHECK3-NEXT: [[TMP15:%.]] = getelementptr inbounds [6 x i8], [6 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 2			// CHECK3-NEXT: [[TMP15:%.]] = getelementptr inbounds [6 x i8], [6 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 2
	// CHECK3-NEXT: [[TMP16:%.]] = bitcast i32 [[TMP8]] to i8*			// CHECK3-NEXT: [[TMP16:%.]] = bitcast i32 [[TMP8]] to i8*
	// CHECK3-NEXT: store i8* [[TMP16]], i8** [[TMP15]], align 8			// CHECK3-NEXT: store i8* [[TMP16]], i8** [[TMP15]], align 8
	// CHECK3-NEXT: [[TMP17:%.]] = getelementptr inbounds [6 x i8], [6 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 3			// CHECK3-NEXT: [[TMP17:%.]] = getelementptr inbounds [6 x i8], [6 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 3
	// CHECK3-NEXT: [[TMP18:%.]] = bitcast i32 [[TMP9]] to i8*			// CHECK3-NEXT: [[TMP18:%.]] = bitcast i32 [[TMP9]] to i8*
	// CHECK3-NEXT: store i8* [[TMP18]], i8** [[TMP17]], align 8			// CHECK3-NEXT: store i8* [[TMP18]], i8** [[TMP17]], align 8
	// CHECK3-NEXT: [[TMP19:%.]] = getelementptr inbounds [6 x i8], [6 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 4			// CHECK3-NEXT: [[TMP19:%.]] = getelementptr inbounds [6 x i8], [6 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 4
	// CHECK3-NEXT: [[TMP20:%.]] = bitcast i32 [[TMP3]] to i8*			// CHECK3-NEXT: [[TMP20:%.]] = bitcast i32 [[TMP3]] to i8*
	// CHECK3-NEXT: store i8* [[TMP20]], i8** [[TMP19]], align 8			// CHECK3-NEXT: store i8* [[TMP20]], i8** [[TMP19]], align 8
	// CHECK3-NEXT: [[TMP21:%.]] = getelementptr inbounds [6 x i8], [6 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 5			// CHECK3-NEXT: [[TMP21:%.]] = getelementptr inbounds [6 x i8], [6 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 5
	// CHECK3-NEXT: [[TMP22:%.]] = bitcast %class.anon [[TMP10]] to i8*			// CHECK3-NEXT: [[TMP22:%.]] = bitcast %class.anon [[TMP10]] to i8*
	// CHECK3-NEXT: store i8* [[TMP22]], i8** [[TMP21]], align 8			// CHECK3-NEXT: store i8* [[TMP22]], i8** [[TMP21]], align 8
	// CHECK3-NEXT: [[TMP23:%.]] = bitcast [6 x i8]* [[CAPTURED_VARS_ADDRS]] to i8**			// CHECK3-NEXT: [[TMP23:%.]] = bitcast [6 x i8]* [[CAPTURED_VARS_ADDRS]] to i8**
	// CHECK3-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP6]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32, i32, i32, i32, i32, i32, i32, %class.anon)* @__omp_outlined__ to i8), i8 null, i8** [[TMP23]], i64 6)			// CHECK3-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32, i32, i32, i32, i32, i32, i32, %class.anon)* @__omp_outlined__ to i8), i8 null, i8** [[TMP23]], i64 6)
	// CHECK3-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 true)			// CHECK3-NEXT: call void @__kmpc_target_deinit(i1 true)
	// CHECK3-NEXT: ret void			// CHECK3-NEXT: ret void
	// CHECK3: worker.exit:			// CHECK3: worker.exit:
	// CHECK3-NEXT: ret void			// CHECK3-NEXT: ret void
	//			//
	//			//
	// CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__			// CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__
	// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i32 nonnull align 4 dereferenceable(4) [[ARGC:%.]], i32 nonnull align 4 dereferenceable(4) [[B:%.]], i32 nonnull align 4 dereferenceable(4) [[C:%.]], i32 [[D:%.]], i32 nonnull align 4 dereferenceable(4) [[A:%.]], %class.anon nonnull align 8 dereferenceable(40) [[L:%.*]]) #[[ATTR0]] {			// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i32 nonnull align 4 dereferenceable(4) [[ARGC:%.]], i32 nonnull align 4 dereferenceable(4) [[B:%.]], i32 nonnull align 4 dereferenceable(4) [[C:%.]], i32 [[D:%.]], i32 nonnull align 4 dereferenceable(4) [[A:%.]], %class.anon nonnull align 8 dereferenceable(40) [[L:%.*]]) #[[ATTR0]] {
	// CHECK3-NEXT: entry:			// CHECK3-NEXT: entry:
	▲ Show 20 Lines • Show All 75 Lines • ▼ Show 20 Lines
	// CHECK3-NEXT: [[TMP:%.]] = alloca %class.anon.0, align 8			// CHECK3-NEXT: [[TMP:%.]] = alloca %class.anon.0, align 8
	// CHECK3-NEXT: [[L1:%.]] = alloca [[CLASS_ANON_0:%.]], align 8			// CHECK3-NEXT: [[L1:%.]] = alloca [[CLASS_ANON_0:%.]], align 8
	// CHECK3-NEXT: [[_TMP2:%.]] = alloca %class.anon.0, align 8			// CHECK3-NEXT: [[_TMP2:%.]] = alloca %class.anon.0, align 8
	// CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8			// CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
	// CHECK3-NEXT: store %class.anon.0* [[L]], %class.anon.0** [[L_ADDR]], align 8			// CHECK3-NEXT: store %class.anon.0* [[L]], %class.anon.0** [[L_ADDR]], align 8
	// CHECK3-NEXT: [[TMP0:%.]] = load %struct.S, %struct.S** [[THIS_ADDR]], align 8			// CHECK3-NEXT: [[TMP0:%.]] = load %struct.S, %struct.S** [[THIS_ADDR]], align 8
	// CHECK3-NEXT: [[TMP1:%.]] = load %class.anon.0, %class.anon.0** [[L_ADDR]], align 8			// CHECK3-NEXT: [[TMP1:%.]] = load %class.anon.0, %class.anon.0** [[L_ADDR]], align 8
	// CHECK3-NEXT: store %class.anon.0* [[TMP1]], %class.anon.0** [[TMP]], align 8			// CHECK3-NEXT: store %class.anon.0* [[TMP1]], %class.anon.0** [[TMP]], align 8
	// CHECK3-NEXT: [[TMP2:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 1, i1 true, i1 true)			// CHECK3-NEXT: [[TMP2:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN1S3fooEv_l27_kernel_info, i1 true)
	// CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP2]], -1			// CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP2]], -1
	// CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]			// CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
	// CHECK3: user_code.entry:			// CHECK3: user_code.entry:
	// CHECK3-NEXT: [[TMP3:%.]] = load %class.anon.0, %class.anon.0** [[TMP]], align 8			// CHECK3-NEXT: [[TMP3:%.]] = load %class.anon.0, %class.anon.0** [[TMP]], align 8
	// CHECK3-NEXT: [[TMP4:%.]] = bitcast %class.anon.0 [[L1]] to i8*			// CHECK3-NEXT: [[TMP4:%.]] = bitcast %class.anon.0 [[L1]] to i8*
	// CHECK3-NEXT: [[TMP5:%.]] = bitcast %class.anon.0 [[TMP3]] to i8*			// CHECK3-NEXT: [[TMP5:%.]] = bitcast %class.anon.0 [[TMP3]] to i8*
	// CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP4]], i8* align 8 [[TMP5]], i64 8, i1 false)			// CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP4]], i8* align 8 [[TMP5]], i64 8, i1 false)
	// CHECK3-NEXT: store %class.anon.0* [[L1]], %class.anon.0** [[_TMP2]], align 8			// CHECK3-NEXT: store %class.anon.0* [[L1]], %class.anon.0** [[_TMP2]], align 8
	// CHECK3-NEXT: [[TMP6:%.]] = load %class.anon.0, %class.anon.0** [[_TMP2]], align 8			// CHECK3-NEXT: [[TMP6:%.]] = load %class.anon.0, %class.anon.0** [[_TMP2]], align 8
	// CHECK3-NEXT: [[TMP7:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[TMP6]], i32 0, i32 0			// CHECK3-NEXT: [[TMP7:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[TMP6]], i32 0, i32 0
	// CHECK3-NEXT: store %struct.S* [[TMP0]], %struct.S** [[TMP7]], align 8			// CHECK3-NEXT: store %struct.S* [[TMP0]], %struct.S** [[TMP7]], align 8
	// CHECK3-NEXT: [[TMP8:%.]] = load %class.anon.0, %class.anon.0** [[_TMP2]], align 8			// CHECK3-NEXT: [[TMP8:%.]] = load %class.anon.0, %class.anon.0** [[_TMP2]], align 8
	// CHECK3-NEXT: [[CALL:%.]] = call i32 @_ZZN1S3fooEvENKUlvE_clEv(%class.anon.0 nonnull align 8 dereferenceable(8) [[TMP8]]) #[[ATTR6]]			// CHECK3-NEXT: [[CALL:%.]] = call i32 @_ZZN1S3fooEvENKUlvE_clEv(%class.anon.0 nonnull align 8 dereferenceable(8) [[TMP8]]) #[[ATTR6]]
	// CHECK3-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true)			// CHECK3-NEXT: call void @__kmpc_target_deinit(i1 true)
	// CHECK3-NEXT: ret void			// CHECK3-NEXT: ret void
	// CHECK3: worker.exit:			// CHECK3: worker.exit:
	// CHECK3-NEXT: ret void			// CHECK3-NEXT: ret void
	//			//
	//			//
	// CHECK3-LABEL: define {{[^@]+}}@_ZZN1S3fooEvENKUlvE_clEv			// CHECK3-LABEL: define {{[^@]+}}@_ZZN1S3fooEvENKUlvE_clEv
	// CHECK3-SAME: (%class.anon.0* nonnull align 8 dereferenceable(8) [[THIS:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 {			// CHECK3-SAME: (%class.anon.0* nonnull align 8 dereferenceable(8) [[THIS:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 {
	// CHECK3-NEXT: entry:			// CHECK3-NEXT: entry:
	Show All 14 Lines
	// CHECK3-NEXT: [[L_ADDR:%.]] = alloca %class.anon.0, align 8			// CHECK3-NEXT: [[L_ADDR:%.]] = alloca %class.anon.0, align 8
	// CHECK3-NEXT: [[TMP:%.]] = alloca %class.anon.0, align 8			// CHECK3-NEXT: [[TMP:%.]] = alloca %class.anon.0, align 8
	// CHECK3-NEXT: [[CAPTURED_VARS_ADDRS:%.]] = alloca [2 x i8], align 8			// CHECK3-NEXT: [[CAPTURED_VARS_ADDRS:%.]] = alloca [2 x i8], align 8
	// CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8			// CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
	// CHECK3-NEXT: store %class.anon.0* [[L]], %class.anon.0** [[L_ADDR]], align 8			// CHECK3-NEXT: store %class.anon.0* [[L]], %class.anon.0** [[L_ADDR]], align 8
	// CHECK3-NEXT: [[TMP0:%.]] = load %struct.S, %struct.S** [[THIS_ADDR]], align 8			// CHECK3-NEXT: [[TMP0:%.]] = load %struct.S, %struct.S** [[THIS_ADDR]], align 8
	// CHECK3-NEXT: [[TMP1:%.]] = load %class.anon.0, %class.anon.0** [[L_ADDR]], align 8			// CHECK3-NEXT: [[TMP1:%.]] = load %class.anon.0, %class.anon.0** [[L_ADDR]], align 8
	// CHECK3-NEXT: store %class.anon.0* [[TMP1]], %class.anon.0** [[TMP]], align 8			// CHECK3-NEXT: store %class.anon.0* [[TMP1]], %class.anon.0** [[TMP]], align 8
	// CHECK3-NEXT: [[TMP2:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 2, i1 false, i1 true)			// CHECK3-NEXT: [[TMP2:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN1S3fooEv_l29_kernel_info, i1 true)
	// CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP2]], -1			// CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP2]], -1
	// CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]			// CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
	// CHECK3: user_code.entry:			// CHECK3: user_code.entry:
	// CHECK3-NEXT: [[TMP3:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB2]])			// CHECK3-NEXT: [[TMP3:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB1]])
	// CHECK3-NEXT: [[TMP4:%.]] = load %class.anon.0, %class.anon.0** [[TMP]], align 8			// CHECK3-NEXT: [[TMP4:%.]] = load %class.anon.0, %class.anon.0** [[TMP]], align 8
	// CHECK3-NEXT: [[TMP5:%.]] = getelementptr inbounds [2 x i8], [2 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 0			// CHECK3-NEXT: [[TMP5:%.]] = getelementptr inbounds [2 x i8], [2 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
	// CHECK3-NEXT: [[TMP6:%.]] = bitcast %struct.S [[TMP0]] to i8*			// CHECK3-NEXT: [[TMP6:%.]] = bitcast %struct.S [[TMP0]] to i8*
	// CHECK3-NEXT: store i8* [[TMP6]], i8** [[TMP5]], align 8			// CHECK3-NEXT: store i8* [[TMP6]], i8** [[TMP5]], align 8
	// CHECK3-NEXT: [[TMP7:%.]] = getelementptr inbounds [2 x i8], [2 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 1			// CHECK3-NEXT: [[TMP7:%.]] = getelementptr inbounds [2 x i8], [2 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
	// CHECK3-NEXT: [[TMP8:%.]] = bitcast %class.anon.0 [[TMP4]] to i8*			// CHECK3-NEXT: [[TMP8:%.]] = bitcast %class.anon.0 [[TMP4]] to i8*
	// CHECK3-NEXT: store i8* [[TMP8]], i8** [[TMP7]], align 8			// CHECK3-NEXT: store i8* [[TMP8]], i8** [[TMP7]], align 8
	// CHECK3-NEXT: [[TMP9:%.]] = bitcast [2 x i8]* [[CAPTURED_VARS_ADDRS]] to i8**			// CHECK3-NEXT: [[TMP9:%.]] = bitcast [2 x i8]* [[CAPTURED_VARS_ADDRS]] to i8**
	// CHECK3-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32, i32, %struct.S, %class.anon.0)* @__omp_outlined__1 to i8), i8 null, i8** [[TMP9]], i64 2)			// CHECK3-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32, i32, %struct.S, %class.anon.0)* @__omp_outlined__1 to i8), i8 null, i8** [[TMP9]], i64 2)
	// CHECK3-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 true)			// CHECK3-NEXT: call void @__kmpc_target_deinit(i1 true)
	// CHECK3-NEXT: ret void			// CHECK3-NEXT: ret void
	// CHECK3: worker.exit:			// CHECK3: worker.exit:
	// CHECK3-NEXT: ret void			// CHECK3-NEXT: ret void
	//			//
	//			//
	// CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__1			// CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__1
	// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], %struct.S [[THIS:%.]], %class.anon.0 nonnull align 8 dereferenceable(8) [[L:%.*]]) #[[ATTR0]] {			// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], %struct.S [[THIS:%.]], %class.anon.0 nonnull align 8 dereferenceable(8) [[L:%.*]]) #[[ATTR0]] {
	// CHECK3-NEXT: entry:			// CHECK3-NEXT: entry:
	Show All 28 Lines
	// CHECK3-SAME: (%class.anon.0* nonnull align 8 dereferenceable(8) [[T:%.*]]) #[[ATTR3]] {			// CHECK3-SAME: (%class.anon.0* nonnull align 8 dereferenceable(8) [[T:%.*]]) #[[ATTR3]] {
	// CHECK3-NEXT: entry:			// CHECK3-NEXT: entry:
	// CHECK3-NEXT: [[T_ADDR:%.]] = alloca %class.anon.0, align 8			// CHECK3-NEXT: [[T_ADDR:%.]] = alloca %class.anon.0, align 8
	// CHECK3-NEXT: [[TMP:%.]] = alloca %class.anon.0, align 8			// CHECK3-NEXT: [[TMP:%.]] = alloca %class.anon.0, align 8
	// CHECK3-NEXT: [[CAPTURED_VARS_ADDRS:%.]] = alloca [1 x i8], align 8			// CHECK3-NEXT: [[CAPTURED_VARS_ADDRS:%.]] = alloca [1 x i8], align 8
	// CHECK3-NEXT: store %class.anon.0* [[T]], %class.anon.0** [[T_ADDR]], align 8			// CHECK3-NEXT: store %class.anon.0* [[T]], %class.anon.0** [[T_ADDR]], align 8
	// CHECK3-NEXT: [[TMP0:%.]] = load %class.anon.0, %class.anon.0** [[T_ADDR]], align 8			// CHECK3-NEXT: [[TMP0:%.]] = load %class.anon.0, %class.anon.0** [[T_ADDR]], align 8
	// CHECK3-NEXT: store %class.anon.0* [[TMP0]], %class.anon.0** [[TMP]], align 8			// CHECK3-NEXT: store %class.anon.0* [[TMP0]], %class.anon.0** [[TMP]], align 8
	// CHECK3-NEXT: [[TMP1:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 2, i1 false, i1 true)			// CHECK3-NEXT: [[TMP1:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIZN1S3fooEvEUlvE_EiRKT__l18_kernel_info, i1 true)
	// CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1			// CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
	// CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]			// CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
	// CHECK3: user_code.entry:			// CHECK3: user_code.entry:
	// CHECK3-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB2]])			// CHECK3-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB1]])
	// CHECK3-NEXT: [[TMP3:%.]] = load %class.anon.0, %class.anon.0** [[TMP]], align 8			// CHECK3-NEXT: [[TMP3:%.]] = load %class.anon.0, %class.anon.0** [[TMP]], align 8
	// CHECK3-NEXT: [[TMP4:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 0			// CHECK3-NEXT: [[TMP4:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
	// CHECK3-NEXT: [[TMP5:%.]] = bitcast %class.anon.0 [[TMP3]] to i8*			// CHECK3-NEXT: [[TMP5:%.]] = bitcast %class.anon.0 [[TMP3]] to i8*
	// CHECK3-NEXT: store i8* [[TMP5]], i8** [[TMP4]], align 8			// CHECK3-NEXT: store i8* [[TMP5]], i8** [[TMP4]], align 8
	// CHECK3-NEXT: [[TMP6:%.]] = bitcast [1 x i8]* [[CAPTURED_VARS_ADDRS]] to i8**			// CHECK3-NEXT: [[TMP6:%.]] = bitcast [1 x i8]* [[CAPTURED_VARS_ADDRS]] to i8**
	// CHECK3-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32, i32, %class.anon.0) @__omp_outlined__2 to i8), i8 null, i8** [[TMP6]], i64 1)			// CHECK3-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32, i32, %class.anon.0) @__omp_outlined__2 to i8), i8 null, i8** [[TMP6]], i64 1)
	// CHECK3-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 true)			// CHECK3-NEXT: call void @__kmpc_target_deinit(i1 true)
	// CHECK3-NEXT: ret void			// CHECK3-NEXT: ret void
	// CHECK3: worker.exit:			// CHECK3: worker.exit:
	// CHECK3-NEXT: ret void			// CHECK3-NEXT: ret void
	//			//
	//			//
	// CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__2			// CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__2
	// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], %class.anon.0 nonnull align 8 dereferenceable(8) [[T:%.*]]) #[[ATTR0]] {			// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], %class.anon.0 nonnull align 8 dereferenceable(8) [[T:%.*]]) #[[ATTR0]] {
	// CHECK3-NEXT: entry:			// CHECK3-NEXT: entry:
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	// CHECK4-NEXT: [[CONV:%.]] = bitcast i64 [[ARGC_ADDR]] to i32*			// CHECK4-NEXT: [[CONV:%.]] = bitcast i64 [[ARGC_ADDR]] to i32*
	// CHECK4-NEXT: [[TMP0:%.]] = load i32, i32** [[B_ADDR]], align 8			// CHECK4-NEXT: [[TMP0:%.]] = load i32, i32** [[B_ADDR]], align 8
	// CHECK4-NEXT: [[TMP1:%.]] = load i32, i32** [[C_ADDR]], align 8			// CHECK4-NEXT: [[TMP1:%.]] = load i32, i32** [[C_ADDR]], align 8
	// CHECK4-NEXT: [[TMP2:%.]] = load i32, i32** [[A_ADDR]], align 8			// CHECK4-NEXT: [[TMP2:%.]] = load i32, i32** [[A_ADDR]], align 8
	// CHECK4-NEXT: [[TMP3:%.]] = load %class.anon, %class.anon** [[L_ADDR]], align 8			// CHECK4-NEXT: [[TMP3:%.]] = load %class.anon, %class.anon** [[L_ADDR]], align 8
	// CHECK4-NEXT: store i32* [[TMP0]], i32** [[TMP]], align 8			// CHECK4-NEXT: store i32* [[TMP0]], i32** [[TMP]], align 8
	// CHECK4-NEXT: store i32* [[TMP1]], i32** [[_TMP1]], align 8			// CHECK4-NEXT: store i32* [[TMP1]], i32** [[_TMP1]], align 8
	// CHECK4-NEXT: store %class.anon* [[TMP3]], %class.anon** [[_TMP2]], align 8			// CHECK4-NEXT: store %class.anon* [[TMP3]], %class.anon** [[_TMP2]], align 8
	// CHECK4-NEXT: [[TMP4:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1:[0-9]+]], i8 1, i1 true, i1 true)			// CHECK4-NEXT: [[TMP4:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l41_kernel_info, i1 true)
	// CHECK4-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP4]], -1			// CHECK4-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP4]], -1
	// CHECK4-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]			// CHECK4-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
	// CHECK4: user_code.entry:			// CHECK4: user_code.entry:
	// CHECK4-NEXT: [[TMP5:%.]] = load %class.anon, %class.anon** [[_TMP2]], align 8			// CHECK4-NEXT: [[TMP5:%.]] = load %class.anon, %class.anon** [[_TMP2]], align 8
	// CHECK4-NEXT: [[TMP6:%.]] = bitcast %class.anon [[L3]] to i8*			// CHECK4-NEXT: [[TMP6:%.]] = bitcast %class.anon [[L3]] to i8*
	// CHECK4-NEXT: [[TMP7:%.]] = bitcast %class.anon [[TMP5]] to i8*			// CHECK4-NEXT: [[TMP7:%.]] = bitcast %class.anon [[TMP5]] to i8*
	// CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP6]], i8* align 8 [[TMP7]], i64 40, i1 false)			// CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP6]], i8* align 8 [[TMP7]], i64 40, i1 false)
	// CHECK4-NEXT: store %class.anon* [[L3]], %class.anon** [[_TMP4]], align 8			// CHECK4-NEXT: store %class.anon* [[L3]], %class.anon** [[_TMP4]], align 8
	Show All 15 Lines
	// CHECK4-NEXT: [[TMP17:%.]] = load i32, i32** [[_TMP8]], align 8			// CHECK4-NEXT: [[TMP17:%.]] = load i32, i32** [[_TMP8]], align 8
	// CHECK4-NEXT: store i32* [[TMP17]], i32** [[TMP16]], align 8			// CHECK4-NEXT: store i32* [[TMP17]], i32** [[TMP16]], align 8
	// CHECK4-NEXT: [[TMP18:%.]] = getelementptr inbounds [[CLASS_ANON]], %class.anon [[TMP12]], i32 0, i32 3			// CHECK4-NEXT: [[TMP18:%.]] = getelementptr inbounds [[CLASS_ANON]], %class.anon [[TMP12]], i32 0, i32 3
	// CHECK4-NEXT: store i32 [[D_ADDR]], i32* [[TMP18]], align 8			// CHECK4-NEXT: store i32 [[D_ADDR]], i32* [[TMP18]], align 8
	// CHECK4-NEXT: [[TMP19:%.]] = getelementptr inbounds [[CLASS_ANON]], %class.anon [[TMP12]], i32 0, i32 4			// CHECK4-NEXT: [[TMP19:%.]] = getelementptr inbounds [[CLASS_ANON]], %class.anon [[TMP12]], i32 0, i32 4
	// CHECK4-NEXT: store i32* [[TMP2]], i32** [[TMP19]], align 8			// CHECK4-NEXT: store i32* [[TMP2]], i32** [[TMP19]], align 8
	// CHECK4-NEXT: [[TMP20:%.]] = load %class.anon, %class.anon** [[_TMP4]], align 8			// CHECK4-NEXT: [[TMP20:%.]] = load %class.anon, %class.anon** [[_TMP4]], align 8
	// CHECK4-NEXT: [[CALL:%.]] = call i64 @"_ZZ4mainENK3$_0clEv"(%class.anon nonnull align 8 dereferenceable(40) [[TMP20]]) #[[ATTR6:[0-9]+]]			// CHECK4-NEXT: [[CALL:%.]] = call i64 @"_ZZ4mainENK3$_0clEv"(%class.anon nonnull align 8 dereferenceable(40) [[TMP20]]) #[[ATTR6:[0-9]+]]
	// CHECK4-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true)			// CHECK4-NEXT: call void @__kmpc_target_deinit(i1 true)
	// CHECK4-NEXT: ret void			// CHECK4-NEXT: ret void
	// CHECK4: worker.exit:			// CHECK4: worker.exit:
	// CHECK4-NEXT: ret void			// CHECK4-NEXT: ret void
	//			//
	//			//
	// CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l43			// CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l43
	// CHECK4-SAME: (i32* nonnull align 4 dereferenceable(4) [[ARGC:%.]], i32 nonnull align 4 dereferenceable(4) [[B:%.]], i32 nonnull align 4 dereferenceable(4) [[C:%.]], i32 [[D:%.]], i32 nonnull align 4 dereferenceable(4) [[A:%.]], %class.anon nonnull align 8 dereferenceable(40) [[L:%.*]]) #[[ATTR3:[0-9]+]] {			// CHECK4-SAME: (i32* nonnull align 4 dereferenceable(4) [[ARGC:%.]], i32 nonnull align 4 dereferenceable(4) [[B:%.]], i32 nonnull align 4 dereferenceable(4) [[C:%.]], i32 [[D:%.]], i32 nonnull align 4 dereferenceable(4) [[A:%.]], %class.anon nonnull align 8 dereferenceable(40) [[L:%.*]]) #[[ATTR3:[0-9]+]] {
	// CHECK4-NEXT: entry:			// CHECK4-NEXT: entry:
	Show All 16 Lines
	// CHECK4-NEXT: [[TMP0:%.]] = load i32, i32** [[ARGC_ADDR]], align 8			// CHECK4-NEXT: [[TMP0:%.]] = load i32, i32** [[ARGC_ADDR]], align 8
	// CHECK4-NEXT: [[TMP1:%.]] = load i32, i32** [[B_ADDR]], align 8			// CHECK4-NEXT: [[TMP1:%.]] = load i32, i32** [[B_ADDR]], align 8
	// CHECK4-NEXT: [[TMP2:%.]] = load i32, i32** [[C_ADDR]], align 8			// CHECK4-NEXT: [[TMP2:%.]] = load i32, i32** [[C_ADDR]], align 8
	// CHECK4-NEXT: [[TMP3:%.]] = load i32, i32** [[A_ADDR]], align 8			// CHECK4-NEXT: [[TMP3:%.]] = load i32, i32** [[A_ADDR]], align 8
	// CHECK4-NEXT: [[TMP4:%.]] = load %class.anon, %class.anon** [[L_ADDR]], align 8			// CHECK4-NEXT: [[TMP4:%.]] = load %class.anon, %class.anon** [[L_ADDR]], align 8
	// CHECK4-NEXT: store i32* [[TMP1]], i32** [[TMP]], align 8			// CHECK4-NEXT: store i32* [[TMP1]], i32** [[TMP]], align 8
	// CHECK4-NEXT: store i32* [[TMP2]], i32** [[_TMP1]], align 8			// CHECK4-NEXT: store i32* [[TMP2]], i32** [[_TMP1]], align 8
	// CHECK4-NEXT: store %class.anon* [[TMP4]], %class.anon** [[_TMP2]], align 8			// CHECK4-NEXT: store %class.anon* [[TMP4]], %class.anon** [[_TMP2]], align 8
	// CHECK4-NEXT: [[TMP5:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 2, i1 false, i1 true)			// CHECK4-NEXT: [[TMP5:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l43_kernel_info, i1 true)
	// CHECK4-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP5]], -1			// CHECK4-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP5]], -1
	// CHECK4-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]			// CHECK4-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
	// CHECK4: user_code.entry:			// CHECK4: user_code.entry:
	// CHECK4-NEXT: [[TMP6:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB2:[0-9]+]])			// CHECK4-NEXT: [[TMP6:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB1:[0-9]+]])
	// CHECK4-NEXT: [[TMP7:%.]] = load i32, i32** [[TMP]], align 8			// CHECK4-NEXT: [[TMP7:%.]] = load i32, i32** [[TMP]], align 8
	// CHECK4-NEXT: [[TMP8:%.]] = load i32, i32** [[_TMP1]], align 8			// CHECK4-NEXT: [[TMP8:%.]] = load i32, i32** [[_TMP1]], align 8
	// CHECK4-NEXT: [[TMP9:%.]] = load i32, i32** [[D_ADDR]], align 8			// CHECK4-NEXT: [[TMP9:%.]] = load i32, i32** [[D_ADDR]], align 8
	// CHECK4-NEXT: [[TMP10:%.]] = load %class.anon, %class.anon** [[_TMP2]], align 8			// CHECK4-NEXT: [[TMP10:%.]] = load %class.anon, %class.anon** [[_TMP2]], align 8
	// CHECK4-NEXT: [[TMP11:%.]] = getelementptr inbounds [6 x i8], [6 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 0			// CHECK4-NEXT: [[TMP11:%.]] = getelementptr inbounds [6 x i8], [6 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
	// CHECK4-NEXT: [[TMP12:%.]] = bitcast i32 [[TMP0]] to i8*			// CHECK4-NEXT: [[TMP12:%.]] = bitcast i32 [[TMP0]] to i8*
	// CHECK4-NEXT: store i8* [[TMP12]], i8** [[TMP11]], align 8			// CHECK4-NEXT: store i8* [[TMP12]], i8** [[TMP11]], align 8
	// CHECK4-NEXT: [[TMP13:%.]] = getelementptr inbounds [6 x i8], [6 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 1			// CHECK4-NEXT: [[TMP13:%.]] = getelementptr inbounds [6 x i8], [6 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
	// CHECK4-NEXT: [[TMP14:%.]] = bitcast i32 [[TMP7]] to i8*			// CHECK4-NEXT: [[TMP14:%.]] = bitcast i32 [[TMP7]] to i8*
	// CHECK4-NEXT: store i8* [[TMP14]], i8** [[TMP13]], align 8			// CHECK4-NEXT: store i8* [[TMP14]], i8** [[TMP13]], align 8
	// CHECK4-NEXT: [[TMP15:%.]] = getelementptr inbounds [6 x i8], [6 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 2			// CHECK4-NEXT: [[TMP15:%.]] = getelementptr inbounds [6 x i8], [6 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 2
	// CHECK4-NEXT: [[TMP16:%.]] = bitcast i32 [[TMP8]] to i8*			// CHECK4-NEXT: [[TMP16:%.]] = bitcast i32 [[TMP8]] to i8*
	// CHECK4-NEXT: store i8* [[TMP16]], i8** [[TMP15]], align 8			// CHECK4-NEXT: store i8* [[TMP16]], i8** [[TMP15]], align 8
	// CHECK4-NEXT: [[TMP17:%.]] = getelementptr inbounds [6 x i8], [6 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 3			// CHECK4-NEXT: [[TMP17:%.]] = getelementptr inbounds [6 x i8], [6 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 3
	// CHECK4-NEXT: [[TMP18:%.]] = bitcast i32 [[TMP9]] to i8*			// CHECK4-NEXT: [[TMP18:%.]] = bitcast i32 [[TMP9]] to i8*
	// CHECK4-NEXT: store i8* [[TMP18]], i8** [[TMP17]], align 8			// CHECK4-NEXT: store i8* [[TMP18]], i8** [[TMP17]], align 8
	// CHECK4-NEXT: [[TMP19:%.]] = getelementptr inbounds [6 x i8], [6 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 4			// CHECK4-NEXT: [[TMP19:%.]] = getelementptr inbounds [6 x i8], [6 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 4
	// CHECK4-NEXT: [[TMP20:%.]] = bitcast i32 [[TMP3]] to i8*			// CHECK4-NEXT: [[TMP20:%.]] = bitcast i32 [[TMP3]] to i8*
	// CHECK4-NEXT: store i8* [[TMP20]], i8** [[TMP19]], align 8			// CHECK4-NEXT: store i8* [[TMP20]], i8** [[TMP19]], align 8
	// CHECK4-NEXT: [[TMP21:%.]] = getelementptr inbounds [6 x i8], [6 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 5			// CHECK4-NEXT: [[TMP21:%.]] = getelementptr inbounds [6 x i8], [6 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 5
	// CHECK4-NEXT: [[TMP22:%.]] = bitcast %class.anon [[TMP10]] to i8*			// CHECK4-NEXT: [[TMP22:%.]] = bitcast %class.anon [[TMP10]] to i8*
	// CHECK4-NEXT: store i8* [[TMP22]], i8** [[TMP21]], align 8			// CHECK4-NEXT: store i8* [[TMP22]], i8** [[TMP21]], align 8
	// CHECK4-NEXT: [[TMP23:%.]] = bitcast [6 x i8]* [[CAPTURED_VARS_ADDRS]] to i8**			// CHECK4-NEXT: [[TMP23:%.]] = bitcast [6 x i8]* [[CAPTURED_VARS_ADDRS]] to i8**
	// CHECK4-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP6]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32, i32, i32, i32, i32, i32, i32, %class.anon)* @__omp_outlined__ to i8), i8 null, i8** [[TMP23]], i64 6)			// CHECK4-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32, i32, i32, i32, i32, i32, i32, %class.anon)* @__omp_outlined__ to i8), i8 null, i8** [[TMP23]], i64 6)
	// CHECK4-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 true)			// CHECK4-NEXT: call void @__kmpc_target_deinit(i1 true)
	// CHECK4-NEXT: ret void			// CHECK4-NEXT: ret void
	// CHECK4: worker.exit:			// CHECK4: worker.exit:
	// CHECK4-NEXT: ret void			// CHECK4-NEXT: ret void
	//			//
	//			//
	// CHECK4-LABEL: define {{[^@]+}}@__omp_outlined__			// CHECK4-LABEL: define {{[^@]+}}@__omp_outlined__
	// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i32 nonnull align 4 dereferenceable(4) [[ARGC:%.]], i32 nonnull align 4 dereferenceable(4) [[B:%.]], i32 nonnull align 4 dereferenceable(4) [[C:%.]], i32 [[D:%.]], i32 nonnull align 4 dereferenceable(4) [[A:%.]], %class.anon nonnull align 8 dereferenceable(40) [[L:%.*]]) #[[ATTR0]] {			// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i32 nonnull align 4 dereferenceable(4) [[ARGC:%.]], i32 nonnull align 4 dereferenceable(4) [[B:%.]], i32 nonnull align 4 dereferenceable(4) [[C:%.]], i32 [[D:%.]], i32 nonnull align 4 dereferenceable(4) [[A:%.]], %class.anon nonnull align 8 dereferenceable(40) [[L:%.*]]) #[[ATTR0]] {
	// CHECK4-NEXT: entry:			// CHECK4-NEXT: entry:
	▲ Show 20 Lines • Show All 75 Lines • ▼ Show 20 Lines
	// CHECK4-NEXT: [[TMP:%.]] = alloca %class.anon.0, align 8			// CHECK4-NEXT: [[TMP:%.]] = alloca %class.anon.0, align 8
	// CHECK4-NEXT: [[L1:%.]] = alloca [[CLASS_ANON_0:%.]], align 8			// CHECK4-NEXT: [[L1:%.]] = alloca [[CLASS_ANON_0:%.]], align 8
	// CHECK4-NEXT: [[_TMP2:%.]] = alloca %class.anon.0, align 8			// CHECK4-NEXT: [[_TMP2:%.]] = alloca %class.anon.0, align 8
	// CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8			// CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
	// CHECK4-NEXT: store %class.anon.0* [[L]], %class.anon.0** [[L_ADDR]], align 8			// CHECK4-NEXT: store %class.anon.0* [[L]], %class.anon.0** [[L_ADDR]], align 8
	// CHECK4-NEXT: [[TMP0:%.]] = load %struct.S, %struct.S** [[THIS_ADDR]], align 8			// CHECK4-NEXT: [[TMP0:%.]] = load %struct.S, %struct.S** [[THIS_ADDR]], align 8
	// CHECK4-NEXT: [[TMP1:%.]] = load %class.anon.0, %class.anon.0** [[L_ADDR]], align 8			// CHECK4-NEXT: [[TMP1:%.]] = load %class.anon.0, %class.anon.0** [[L_ADDR]], align 8
	// CHECK4-NEXT: store %class.anon.0* [[TMP1]], %class.anon.0** [[TMP]], align 8			// CHECK4-NEXT: store %class.anon.0* [[TMP1]], %class.anon.0** [[TMP]], align 8
	// CHECK4-NEXT: [[TMP2:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 1, i1 true, i1 true)			// CHECK4-NEXT: [[TMP2:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN1S3fooEv_l27_kernel_info, i1 true)
	// CHECK4-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP2]], -1			// CHECK4-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP2]], -1
	// CHECK4-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]			// CHECK4-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
	// CHECK4: user_code.entry:			// CHECK4: user_code.entry:
	// CHECK4-NEXT: [[TMP3:%.]] = load %class.anon.0, %class.anon.0** [[TMP]], align 8			// CHECK4-NEXT: [[TMP3:%.]] = load %class.anon.0, %class.anon.0** [[TMP]], align 8
	// CHECK4-NEXT: [[TMP4:%.]] = bitcast %class.anon.0 [[L1]] to i8*			// CHECK4-NEXT: [[TMP4:%.]] = bitcast %class.anon.0 [[L1]] to i8*
	// CHECK4-NEXT: [[TMP5:%.]] = bitcast %class.anon.0 [[TMP3]] to i8*			// CHECK4-NEXT: [[TMP5:%.]] = bitcast %class.anon.0 [[TMP3]] to i8*
	// CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP4]], i8* align 8 [[TMP5]], i64 8, i1 false)			// CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP4]], i8* align 8 [[TMP5]], i64 8, i1 false)
	// CHECK4-NEXT: store %class.anon.0* [[L1]], %class.anon.0** [[_TMP2]], align 8			// CHECK4-NEXT: store %class.anon.0* [[L1]], %class.anon.0** [[_TMP2]], align 8
	// CHECK4-NEXT: [[TMP6:%.]] = load %class.anon.0, %class.anon.0** [[_TMP2]], align 8			// CHECK4-NEXT: [[TMP6:%.]] = load %class.anon.0, %class.anon.0** [[_TMP2]], align 8
	// CHECK4-NEXT: [[TMP7:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[TMP6]], i32 0, i32 0			// CHECK4-NEXT: [[TMP7:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[TMP6]], i32 0, i32 0
	// CHECK4-NEXT: store %struct.S* [[TMP0]], %struct.S** [[TMP7]], align 8			// CHECK4-NEXT: store %struct.S* [[TMP0]], %struct.S** [[TMP7]], align 8
	// CHECK4-NEXT: [[TMP8:%.]] = load %class.anon.0, %class.anon.0** [[_TMP2]], align 8			// CHECK4-NEXT: [[TMP8:%.]] = load %class.anon.0, %class.anon.0** [[_TMP2]], align 8
	// CHECK4-NEXT: [[CALL:%.]] = call i32 @_ZZN1S3fooEvENKUlvE_clEv(%class.anon.0 nonnull align 8 dereferenceable(8) [[TMP8]]) #[[ATTR6]]			// CHECK4-NEXT: [[CALL:%.]] = call i32 @_ZZN1S3fooEvENKUlvE_clEv(%class.anon.0 nonnull align 8 dereferenceable(8) [[TMP8]]) #[[ATTR6]]
	// CHECK4-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true)			// CHECK4-NEXT: call void @__kmpc_target_deinit(i1 true)
	// CHECK4-NEXT: ret void			// CHECK4-NEXT: ret void
	// CHECK4: worker.exit:			// CHECK4: worker.exit:
	// CHECK4-NEXT: ret void			// CHECK4-NEXT: ret void
	//			//
	//			//
	// CHECK4-LABEL: define {{[^@]+}}@_ZZN1S3fooEvENKUlvE_clEv			// CHECK4-LABEL: define {{[^@]+}}@_ZZN1S3fooEvENKUlvE_clEv
	// CHECK4-SAME: (%class.anon.0* nonnull align 8 dereferenceable(8) [[THIS:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 {			// CHECK4-SAME: (%class.anon.0* nonnull align 8 dereferenceable(8) [[THIS:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 {
	// CHECK4-NEXT: entry:			// CHECK4-NEXT: entry:
	Show All 14 Lines
	// CHECK4-NEXT: [[L_ADDR:%.]] = alloca %class.anon.0, align 8			// CHECK4-NEXT: [[L_ADDR:%.]] = alloca %class.anon.0, align 8
	// CHECK4-NEXT: [[TMP:%.]] = alloca %class.anon.0, align 8			// CHECK4-NEXT: [[TMP:%.]] = alloca %class.anon.0, align 8
	// CHECK4-NEXT: [[CAPTURED_VARS_ADDRS:%.]] = alloca [2 x i8], align 8			// CHECK4-NEXT: [[CAPTURED_VARS_ADDRS:%.]] = alloca [2 x i8], align 8
	// CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8			// CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
	// CHECK4-NEXT: store %class.anon.0* [[L]], %class.anon.0** [[L_ADDR]], align 8			// CHECK4-NEXT: store %class.anon.0* [[L]], %class.anon.0** [[L_ADDR]], align 8
	// CHECK4-NEXT: [[TMP0:%.]] = load %struct.S, %struct.S** [[THIS_ADDR]], align 8			// CHECK4-NEXT: [[TMP0:%.]] = load %struct.S, %struct.S** [[THIS_ADDR]], align 8
	// CHECK4-NEXT: [[TMP1:%.]] = load %class.anon.0, %class.anon.0** [[L_ADDR]], align 8			// CHECK4-NEXT: [[TMP1:%.]] = load %class.anon.0, %class.anon.0** [[L_ADDR]], align 8
	// CHECK4-NEXT: store %class.anon.0* [[TMP1]], %class.anon.0** [[TMP]], align 8			// CHECK4-NEXT: store %class.anon.0* [[TMP1]], %class.anon.0** [[TMP]], align 8
	// CHECK4-NEXT: [[TMP2:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 2, i1 false, i1 true)			// CHECK4-NEXT: [[TMP2:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN1S3fooEv_l29_kernel_info, i1 true)
	// CHECK4-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP2]], -1			// CHECK4-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP2]], -1
	// CHECK4-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]			// CHECK4-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
	// CHECK4: user_code.entry:			// CHECK4: user_code.entry:
	// CHECK4-NEXT: [[TMP3:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB2]])			// CHECK4-NEXT: [[TMP3:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB1]])
	// CHECK4-NEXT: [[TMP4:%.]] = load %class.anon.0, %class.anon.0** [[TMP]], align 8			// CHECK4-NEXT: [[TMP4:%.]] = load %class.anon.0, %class.anon.0** [[TMP]], align 8
	// CHECK4-NEXT: [[TMP5:%.]] = getelementptr inbounds [2 x i8], [2 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 0			// CHECK4-NEXT: [[TMP5:%.]] = getelementptr inbounds [2 x i8], [2 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
	// CHECK4-NEXT: [[TMP6:%.]] = bitcast %struct.S [[TMP0]] to i8*			// CHECK4-NEXT: [[TMP6:%.]] = bitcast %struct.S [[TMP0]] to i8*
	// CHECK4-NEXT: store i8* [[TMP6]], i8** [[TMP5]], align 8			// CHECK4-NEXT: store i8* [[TMP6]], i8** [[TMP5]], align 8
	// CHECK4-NEXT: [[TMP7:%.]] = getelementptr inbounds [2 x i8], [2 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 1			// CHECK4-NEXT: [[TMP7:%.]] = getelementptr inbounds [2 x i8], [2 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
	// CHECK4-NEXT: [[TMP8:%.]] = bitcast %class.anon.0 [[TMP4]] to i8*			// CHECK4-NEXT: [[TMP8:%.]] = bitcast %class.anon.0 [[TMP4]] to i8*
	// CHECK4-NEXT: store i8* [[TMP8]], i8** [[TMP7]], align 8			// CHECK4-NEXT: store i8* [[TMP8]], i8** [[TMP7]], align 8
	// CHECK4-NEXT: [[TMP9:%.]] = bitcast [2 x i8]* [[CAPTURED_VARS_ADDRS]] to i8**			// CHECK4-NEXT: [[TMP9:%.]] = bitcast [2 x i8]* [[CAPTURED_VARS_ADDRS]] to i8**
	// CHECK4-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32, i32, %struct.S, %class.anon.0)* @__omp_outlined__1 to i8), i8 null, i8** [[TMP9]], i64 2)			// CHECK4-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32, i32, %struct.S, %class.anon.0)* @__omp_outlined__1 to i8), i8 null, i8** [[TMP9]], i64 2)
	// CHECK4-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 true)			// CHECK4-NEXT: call void @__kmpc_target_deinit(i1 true)
	// CHECK4-NEXT: ret void			// CHECK4-NEXT: ret void
	// CHECK4: worker.exit:			// CHECK4: worker.exit:
	// CHECK4-NEXT: ret void			// CHECK4-NEXT: ret void
	//			//
	//			//
	// CHECK4-LABEL: define {{[^@]+}}@__omp_outlined__1			// CHECK4-LABEL: define {{[^@]+}}@__omp_outlined__1
	// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], %struct.S [[THIS:%.]], %class.anon.0 nonnull align 8 dereferenceable(8) [[L:%.*]]) #[[ATTR0]] {			// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], %struct.S [[THIS:%.]], %class.anon.0 nonnull align 8 dereferenceable(8) [[L:%.*]]) #[[ATTR0]] {
	// CHECK4-NEXT: entry:			// CHECK4-NEXT: entry:
	Show All 28 Lines
	// CHECK4-SAME: (%class.anon.0* nonnull align 8 dereferenceable(8) [[T:%.*]]) #[[ATTR3]] {			// CHECK4-SAME: (%class.anon.0* nonnull align 8 dereferenceable(8) [[T:%.*]]) #[[ATTR3]] {
	// CHECK4-NEXT: entry:			// CHECK4-NEXT: entry:
	// CHECK4-NEXT: [[T_ADDR:%.]] = alloca %class.anon.0, align 8			// CHECK4-NEXT: [[T_ADDR:%.]] = alloca %class.anon.0, align 8
	// CHECK4-NEXT: [[TMP:%.]] = alloca %class.anon.0, align 8			// CHECK4-NEXT: [[TMP:%.]] = alloca %class.anon.0, align 8
	// CHECK4-NEXT: [[CAPTURED_VARS_ADDRS:%.]] = alloca [1 x i8], align 8			// CHECK4-NEXT: [[CAPTURED_VARS_ADDRS:%.]] = alloca [1 x i8], align 8
	// CHECK4-NEXT: store %class.anon.0* [[T]], %class.anon.0** [[T_ADDR]], align 8			// CHECK4-NEXT: store %class.anon.0* [[T]], %class.anon.0** [[T_ADDR]], align 8
	// CHECK4-NEXT: [[TMP0:%.]] = load %class.anon.0, %class.anon.0** [[T_ADDR]], align 8			// CHECK4-NEXT: [[TMP0:%.]] = load %class.anon.0, %class.anon.0** [[T_ADDR]], align 8
	// CHECK4-NEXT: store %class.anon.0* [[TMP0]], %class.anon.0** [[TMP]], align 8			// CHECK4-NEXT: store %class.anon.0* [[TMP0]], %class.anon.0** [[TMP]], align 8
	// CHECK4-NEXT: [[TMP1:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 2, i1 false, i1 true)			// CHECK4-NEXT: [[TMP1:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIZN1S3fooEvEUlvE_EiRKT__l18_kernel_info, i1 true)
	// CHECK4-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1			// CHECK4-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
	// CHECK4-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]			// CHECK4-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
	// CHECK4: user_code.entry:			// CHECK4: user_code.entry:
	// CHECK4-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB2]])			// CHECK4-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB1]])
	// CHECK4-NEXT: [[TMP3:%.]] = load %class.anon.0, %class.anon.0** [[TMP]], align 8			// CHECK4-NEXT: [[TMP3:%.]] = load %class.anon.0, %class.anon.0** [[TMP]], align 8
	// CHECK4-NEXT: [[TMP4:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 0			// CHECK4-NEXT: [[TMP4:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
	// CHECK4-NEXT: [[TMP5:%.]] = bitcast %class.anon.0 [[TMP3]] to i8*			// CHECK4-NEXT: [[TMP5:%.]] = bitcast %class.anon.0 [[TMP3]] to i8*
	// CHECK4-NEXT: store i8* [[TMP5]], i8** [[TMP4]], align 8			// CHECK4-NEXT: store i8* [[TMP5]], i8** [[TMP4]], align 8
	// CHECK4-NEXT: [[TMP6:%.]] = bitcast [1 x i8]* [[CAPTURED_VARS_ADDRS]] to i8**			// CHECK4-NEXT: [[TMP6:%.]] = bitcast [1 x i8]* [[CAPTURED_VARS_ADDRS]] to i8**
	// CHECK4-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32, i32, %class.anon.0) @__omp_outlined__2 to i8), i8 null, i8** [[TMP6]], i64 1)			// CHECK4-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32, i32, %class.anon.0) @__omp_outlined__2 to i8), i8 null, i8** [[TMP6]], i64 1)
	// CHECK4-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 true)			// CHECK4-NEXT: call void @__kmpc_target_deinit(i1 true)
	// CHECK4-NEXT: ret void			// CHECK4-NEXT: ret void
	// CHECK4: worker.exit:			// CHECK4: worker.exit:
	// CHECK4-NEXT: ret void			// CHECK4-NEXT: ret void
	//			//
	//			//
	// CHECK4-LABEL: define {{[^@]+}}@__omp_outlined__2			// CHECK4-LABEL: define {{[^@]+}}@__omp_outlined__2
	// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], %class.anon.0 nonnull align 8 dereferenceable(8) [[T:%.*]]) #[[ATTR0]] {			// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], %class.anon.0 nonnull align 8 dereferenceable(8) [[T:%.*]]) #[[ATTR0]] {
	// CHECK4-NEXT: entry:			// CHECK4-NEXT: entry:
	Show All 21 Lines

clang/test/OpenMP/nvptx_multi_target_parallel_codegen.cpp

Show All 23 Lines	int main() {
{ use(); }		{ use(); }
}		}

#endif		#endif
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l21		// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l21
// CHECK1-SAME: () #[[ATTR0:[0-9]+]] {		// CHECK1-SAME: () #[[ATTR0:[0-9]+]] {
// CHECK1-NEXT: entry:		// CHECK1-NEXT: entry:
// CHECK1-NEXT: [[CAPTURED_VARS_ADDRS:%.]] = alloca [0 x i8], align 8		// CHECK1-NEXT: [[CAPTURED_VARS_ADDRS:%.]] = alloca [0 x i8], align 8
// CHECK1-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1:[0-9]+]], i8 2, i1 false, i1 true)		// CHECK1-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l21_kernel_info, i1 true)
// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1		// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]		// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
// CHECK1: user_code.entry:		// CHECK1: user_code.entry:
// CHECK1-NEXT: [[TMP1:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB2:[0-9]+]])		// CHECK1-NEXT: [[TMP1:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB2:[0-9]+]])
// CHECK1-NEXT: [[TMP2:%.]] = bitcast [0 x i8]* [[CAPTURED_VARS_ADDRS]] to i8**		// CHECK1-NEXT: [[TMP2:%.]] = bitcast [0 x i8]* [[CAPTURED_VARS_ADDRS]] to i8**
// CHECK1-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32, i32)* @__omp_outlined__ to i8), i8 null, i8** [[TMP2]], i64 0)		// CHECK1-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32, i32)* @__omp_outlined__ to i8), i8 null, i8** [[TMP2]], i64 0)
// CHECK1-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 true)		// CHECK1-NEXT: call void @__kmpc_target_deinit(i1 true)
// CHECK1-NEXT: ret void		// CHECK1-NEXT: ret void
// CHECK1: worker.exit:		// CHECK1: worker.exit:
// CHECK1-NEXT: ret void		// CHECK1-NEXT: ret void
//		//
//		//
// CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__		// CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__
// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] {		// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] {
// CHECK1-NEXT: entry:		// CHECK1-NEXT: entry:
Show All 13 Lines
// CHECK1-NEXT: [[TMP1:%.]] = bitcast [0 x i8]* [[CAPTURED_VARS_ADDRS]] to i8**		// CHECK1-NEXT: [[TMP1:%.]] = bitcast [0 x i8]* [[CAPTURED_VARS_ADDRS]] to i8**
// CHECK1-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB3]], i32 [[TMP0]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32, i32)* @__omp_outlined__1 to i8), i8 bitcast (void (i16, i32)* @__omp_outlined__1_wrapper to i8), i8* [[TMP1]], i64 0)		// CHECK1-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB3]], i32 [[TMP0]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32, i32)* @__omp_outlined__1 to i8), i8 bitcast (void (i16, i32)* @__omp_outlined__1_wrapper to i8), i8* [[TMP1]], i64 0)
// CHECK1-NEXT: ret void		// CHECK1-NEXT: ret void
//		//
//		//
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l23		// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l23
// CHECK1-SAME: () #[[ATTR1]] {		// CHECK1-SAME: () #[[ATTR1]] {
// CHECK1-NEXT: entry:		// CHECK1-NEXT: entry:
// CHECK1-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 1, i1 true, i1 true)		// CHECK1-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l23_kernel_info, i1 true)
// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1		// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]		// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
// CHECK1: user_code.entry:		// CHECK1: user_code.entry:
// CHECK1-NEXT: call void @_Z3usev() #[[ATTR7]]		// CHECK1-NEXT: call void @_Z3usev() #[[ATTR7]]
// CHECK1-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true)		// CHECK1-NEXT: call void @__kmpc_target_deinit(i1 true)
// CHECK1-NEXT: ret void		// CHECK1-NEXT: ret void
// CHECK1: worker.exit:		// CHECK1: worker.exit:
// CHECK1-NEXT: ret void		// CHECK1-NEXT: ret void
//		//
//		//
// CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__1		// CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__1
// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {		// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
// CHECK1-NEXT: entry:		// CHECK1-NEXT: entry:
Show All 19 Lines
// CHECK1-NEXT: call void @__omp_outlined__1(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR3:[0-9]+]]		// CHECK1-NEXT: call void @__omp_outlined__1(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR3:[0-9]+]]
// CHECK1-NEXT: ret void		// CHECK1-NEXT: ret void
//		//
//		//
// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l21		// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l21
// CHECK2-SAME: () #[[ATTR0:[0-9]+]] {		// CHECK2-SAME: () #[[ATTR0:[0-9]+]] {
// CHECK2-NEXT: entry:		// CHECK2-NEXT: entry:
// CHECK2-NEXT: [[CAPTURED_VARS_ADDRS:%.]] = alloca [0 x i8], align 4		// CHECK2-NEXT: [[CAPTURED_VARS_ADDRS:%.]] = alloca [0 x i8], align 4
// CHECK2-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1:[0-9]+]], i8 2, i1 false, i1 true)		// CHECK2-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l21_kernel_info, i1 true)
// CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1		// CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]		// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
// CHECK2: user_code.entry:		// CHECK2: user_code.entry:
// CHECK2-NEXT: [[TMP1:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB2:[0-9]+]])		// CHECK2-NEXT: [[TMP1:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB2:[0-9]+]])
// CHECK2-NEXT: [[TMP2:%.]] = bitcast [0 x i8]* [[CAPTURED_VARS_ADDRS]] to i8**		// CHECK2-NEXT: [[TMP2:%.]] = bitcast [0 x i8]* [[CAPTURED_VARS_ADDRS]] to i8**
// CHECK2-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32, i32)* @__omp_outlined__ to i8), i8 null, i8** [[TMP2]], i32 0)		// CHECK2-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32, i32)* @__omp_outlined__ to i8), i8 null, i8** [[TMP2]], i32 0)
// CHECK2-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 true)		// CHECK2-NEXT: call void @__kmpc_target_deinit(i1 true)
// CHECK2-NEXT: ret void		// CHECK2-NEXT: ret void
// CHECK2: worker.exit:		// CHECK2: worker.exit:
// CHECK2-NEXT: ret void		// CHECK2-NEXT: ret void
//		//
//		//
// CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__		// CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__
// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] {		// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] {
// CHECK2-NEXT: entry:		// CHECK2-NEXT: entry:
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// CHECK2-NEXT: [[TMP1:%.]] = bitcast [0 x i8]* [[CAPTURED_VARS_ADDRS]] to i8**		// CHECK2-NEXT: [[TMP1:%.]] = bitcast [0 x i8]* [[CAPTURED_VARS_ADDRS]] to i8**
// CHECK2-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB3]], i32 [[TMP0]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32, i32)* @__omp_outlined__1 to i8), i8 bitcast (void (i16, i32)* @__omp_outlined__1_wrapper to i8), i8* [[TMP1]], i32 0)		// CHECK2-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB3]], i32 [[TMP0]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32, i32)* @__omp_outlined__1 to i8), i8 bitcast (void (i16, i32)* @__omp_outlined__1_wrapper to i8), i8* [[TMP1]], i32 0)
// CHECK2-NEXT: ret void		// CHECK2-NEXT: ret void
//		//
//		//
// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l23		// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l23
// CHECK2-SAME: () #[[ATTR1]] {		// CHECK2-SAME: () #[[ATTR1]] {
// CHECK2-NEXT: entry:		// CHECK2-NEXT: entry:
// CHECK2-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 1, i1 true, i1 true)		// CHECK2-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l23_kernel_info, i1 true)
// CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1		// CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]		// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
// CHECK2: user_code.entry:		// CHECK2: user_code.entry:
// CHECK2-NEXT: call void @_Z3usev() #[[ATTR7]]		// CHECK2-NEXT: call void @_Z3usev() #[[ATTR7]]
// CHECK2-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true)		// CHECK2-NEXT: call void @__kmpc_target_deinit(i1 true)
// CHECK2-NEXT: ret void		// CHECK2-NEXT: ret void
// CHECK2: worker.exit:		// CHECK2: worker.exit:
// CHECK2-NEXT: ret void		// CHECK2-NEXT: ret void
//		//
//		//
// CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__1		// CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__1
// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {		// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
// CHECK2-NEXT: entry:		// CHECK2-NEXT: entry:
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// CHECK2-NEXT: call void @__omp_outlined__1(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR3:[0-9]+]]		// CHECK2-NEXT: call void @__omp_outlined__1(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR3:[0-9]+]]
// CHECK2-NEXT: ret void		// CHECK2-NEXT: ret void
//		//
//		//
// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l21		// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l21
// CHECK3-SAME: () #[[ATTR0:[0-9]+]] {		// CHECK3-SAME: () #[[ATTR0:[0-9]+]] {
// CHECK3-NEXT: entry:		// CHECK3-NEXT: entry:
// CHECK3-NEXT: [[CAPTURED_VARS_ADDRS:%.]] = alloca [0 x i8], align 4		// CHECK3-NEXT: [[CAPTURED_VARS_ADDRS:%.]] = alloca [0 x i8], align 4
// CHECK3-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1:[0-9]+]], i8 2, i1 false, i1 true)		// CHECK3-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l21_kernel_info, i1 true)
// CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1		// CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
// CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]		// CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
// CHECK3: user_code.entry:		// CHECK3: user_code.entry:
// CHECK3-NEXT: [[TMP1:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB2:[0-9]+]])		// CHECK3-NEXT: [[TMP1:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB2:[0-9]+]])
// CHECK3-NEXT: [[TMP2:%.]] = bitcast [0 x i8]* [[CAPTURED_VARS_ADDRS]] to i8**		// CHECK3-NEXT: [[TMP2:%.]] = bitcast [0 x i8]* [[CAPTURED_VARS_ADDRS]] to i8**
// CHECK3-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32, i32)* @__omp_outlined__ to i8), i8 null, i8** [[TMP2]], i32 0)		// CHECK3-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32, i32)* @__omp_outlined__ to i8), i8 null, i8** [[TMP2]], i32 0)
// CHECK3-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 true)		// CHECK3-NEXT: call void @__kmpc_target_deinit(i1 true)
// CHECK3-NEXT: ret void		// CHECK3-NEXT: ret void
// CHECK3: worker.exit:		// CHECK3: worker.exit:
// CHECK3-NEXT: ret void		// CHECK3-NEXT: ret void
//		//
//		//
// CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__		// CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__
// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] {		// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] {
// CHECK3-NEXT: entry:		// CHECK3-NEXT: entry:
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// CHECK3-NEXT: [[TMP1:%.]] = bitcast [0 x i8]* [[CAPTURED_VARS_ADDRS]] to i8**		// CHECK3-NEXT: [[TMP1:%.]] = bitcast [0 x i8]* [[CAPTURED_VARS_ADDRS]] to i8**
// CHECK3-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB3]], i32 [[TMP0]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32, i32)* @__omp_outlined__1 to i8), i8 bitcast (void (i16, i32)* @__omp_outlined__1_wrapper to i8), i8* [[TMP1]], i32 0)		// CHECK3-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB3]], i32 [[TMP0]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32, i32)* @__omp_outlined__1 to i8), i8 bitcast (void (i16, i32)* @__omp_outlined__1_wrapper to i8), i8* [[TMP1]], i32 0)
// CHECK3-NEXT: ret void		// CHECK3-NEXT: ret void
//		//
//		//
// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l23		// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l23
// CHECK3-SAME: () #[[ATTR1]] {		// CHECK3-SAME: () #[[ATTR1]] {
// CHECK3-NEXT: entry:		// CHECK3-NEXT: entry:
// CHECK3-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 1, i1 true, i1 true)		// CHECK3-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l23_kernel_info, i1 true)
// CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1		// CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
// CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]		// CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
// CHECK3: user_code.entry:		// CHECK3: user_code.entry:
// CHECK3-NEXT: call void @_Z3usev() #[[ATTR7]]		// CHECK3-NEXT: call void @_Z3usev() #[[ATTR7]]
// CHECK3-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true)		// CHECK3-NEXT: call void @__kmpc_target_deinit(i1 true)
// CHECK3-NEXT: ret void		// CHECK3-NEXT: ret void
// CHECK3: worker.exit:		// CHECK3: worker.exit:
// CHECK3-NEXT: ret void		// CHECK3-NEXT: ret void
//		//
//		//
// CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__1		// CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__1
// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {		// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
// CHECK3-NEXT: entry:		// CHECK3-NEXT: entry:
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clang/test/OpenMP/nvptx_nested_parallel_codegen.cpp

	Show All 34 Lines
	#endif			#endif
	// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l25			// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l25
	// CHECK1-SAME: (i32* nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR0:[0-9]+]] {			// CHECK1-SAME: (i32* nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR0:[0-9]+]] {
	// CHECK1-NEXT: entry:			// CHECK1-NEXT: entry:
	// CHECK1-NEXT: [[C_ADDR:%.]] = alloca i32, align 8			// CHECK1-NEXT: [[C_ADDR:%.]] = alloca i32, align 8
	// CHECK1-NEXT: [[CAPTURED_VARS_ADDRS:%.]] = alloca [1 x i8], align 8			// CHECK1-NEXT: [[CAPTURED_VARS_ADDRS:%.]] = alloca [1 x i8], align 8
	// CHECK1-NEXT: store i32* [[C]], i32** [[C_ADDR]], align 8			// CHECK1-NEXT: store i32* [[C]], i32** [[C_ADDR]], align 8
	// CHECK1-NEXT: [[TMP0:%.]] = load i32, i32** [[C_ADDR]], align 8			// CHECK1-NEXT: [[TMP0:%.]] = load i32, i32** [[C_ADDR]], align 8
	// CHECK1-NEXT: [[TMP1:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1:[0-9]+]], i8 1, i1 true, i1 true)			// CHECK1-NEXT: [[TMP1:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l25_kernel_info, i1 true)
	// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1			// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
	// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]			// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
	// CHECK1: user_code.entry:			// CHECK1: user_code.entry:
	// CHECK1-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB1]])			// CHECK1-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB1:[0-9]+]])
	// CHECK1-NEXT: call void @_Z3usePi(i32* [[TMP0]]) #[[ATTR6:[0-9]+]]			// CHECK1-NEXT: call void @_Z3usePi(i32* [[TMP0]]) #[[ATTR6:[0-9]+]]
	// CHECK1-NEXT: [[TMP3:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 0			// CHECK1-NEXT: [[TMP3:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
	// CHECK1-NEXT: [[TMP4:%.]] = bitcast i32 [[TMP0]] to i8*			// CHECK1-NEXT: [[TMP4:%.]] = bitcast i32 [[TMP0]] to i8*
	// CHECK1-NEXT: store i8* [[TMP4]], i8** [[TMP3]], align 8			// CHECK1-NEXT: store i8* [[TMP4]], i8** [[TMP3]], align 8
	// CHECK1-NEXT: [[TMP5:%.]] = bitcast [1 x i8]* [[CAPTURED_VARS_ADDRS]] to i8**			// CHECK1-NEXT: [[TMP5:%.]] = bitcast [1 x i8]* [[CAPTURED_VARS_ADDRS]] to i8**
	// CHECK1-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1, i32 2, i32 -1, i8* bitcast (void (i32, i32, i32) @__omp_outlined__ to i8), i8 bitcast (void (i16, i32)* @__omp_outlined___wrapper to i8), i8* [[TMP5]], i64 1)			// CHECK1-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1, i32 2, i32 -1, i8* bitcast (void (i32, i32, i32) @__omp_outlined__ to i8), i8 bitcast (void (i16, i32)* @__omp_outlined___wrapper to i8), i8* [[TMP5]], i64 1)
	// CHECK1-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true)			// CHECK1-NEXT: call void @__kmpc_target_deinit(i1 true)
	// CHECK1-NEXT: ret void			// CHECK1-NEXT: ret void
	// CHECK1: worker.exit:			// CHECK1: worker.exit:
	// CHECK1-NEXT: ret void			// CHECK1-NEXT: ret void
	//			//
	//			//
	// CHECK1-LABEL: define {{[^@]+}}@_Z3usePi			// CHECK1-LABEL: define {{[^@]+}}@_Z3usePi
	// CHECK1-SAME: (i32* [[C:%.*]]) #[[ATTR1:[0-9]+]] {			// CHECK1-SAME: (i32* [[C:%.*]]) #[[ATTR1:[0-9]+]] {
	// CHECK1-NEXT: entry:			// CHECK1-NEXT: entry:
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	//			//
	// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l25			// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l25
	// CHECK2-SAME: (i32* nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR0:[0-9]+]] {			// CHECK2-SAME: (i32* nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR0:[0-9]+]] {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	// CHECK2-NEXT: [[C_ADDR:%.]] = alloca i32, align 4			// CHECK2-NEXT: [[C_ADDR:%.]] = alloca i32, align 4
	// CHECK2-NEXT: [[CAPTURED_VARS_ADDRS:%.]] = alloca [1 x i8], align 4			// CHECK2-NEXT: [[CAPTURED_VARS_ADDRS:%.]] = alloca [1 x i8], align 4
	// CHECK2-NEXT: store i32* [[C]], i32** [[C_ADDR]], align 4			// CHECK2-NEXT: store i32* [[C]], i32** [[C_ADDR]], align 4
	// CHECK2-NEXT: [[TMP0:%.]] = load i32, i32** [[C_ADDR]], align 4			// CHECK2-NEXT: [[TMP0:%.]] = load i32, i32** [[C_ADDR]], align 4
	// CHECK2-NEXT: [[TMP1:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1:[0-9]+]], i8 1, i1 true, i1 true)			// CHECK2-NEXT: [[TMP1:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l25_kernel_info, i1 true)
	// CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1			// CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
	// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]			// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
	// CHECK2: user_code.entry:			// CHECK2: user_code.entry:
	// CHECK2-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB1]])			// CHECK2-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB1:[0-9]+]])
	// CHECK2-NEXT: call void @_Z3usePi(i32* [[TMP0]]) #[[ATTR6:[0-9]+]]			// CHECK2-NEXT: call void @_Z3usePi(i32* [[TMP0]]) #[[ATTR6:[0-9]+]]
	// CHECK2-NEXT: [[TMP3:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[CAPTURED_VARS_ADDRS]], i32 0, i32 0			// CHECK2-NEXT: [[TMP3:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
	// CHECK2-NEXT: [[TMP4:%.]] = bitcast i32 [[TMP0]] to i8*			// CHECK2-NEXT: [[TMP4:%.]] = bitcast i32 [[TMP0]] to i8*
	// CHECK2-NEXT: store i8* [[TMP4]], i8** [[TMP3]], align 4			// CHECK2-NEXT: store i8* [[TMP4]], i8** [[TMP3]], align 4
	// CHECK2-NEXT: [[TMP5:%.]] = bitcast [1 x i8]* [[CAPTURED_VARS_ADDRS]] to i8**			// CHECK2-NEXT: [[TMP5:%.]] = bitcast [1 x i8]* [[CAPTURED_VARS_ADDRS]] to i8**
	// CHECK2-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1, i32 2, i32 -1, i8* bitcast (void (i32, i32, i32) @__omp_outlined__ to i8), i8 bitcast (void (i16, i32)* @__omp_outlined___wrapper to i8), i8* [[TMP5]], i32 1)			// CHECK2-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1, i32 2, i32 -1, i8* bitcast (void (i32, i32, i32) @__omp_outlined__ to i8), i8 bitcast (void (i16, i32)* @__omp_outlined___wrapper to i8), i8* [[TMP5]], i32 1)
	// CHECK2-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true)			// CHECK2-NEXT: call void @__kmpc_target_deinit(i1 true)
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	// CHECK2: worker.exit:			// CHECK2: worker.exit:
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@_Z3usePi			// CHECK2-LABEL: define {{[^@]+}}@_Z3usePi
	// CHECK2-SAME: (i32* [[C:%.*]]) #[[ATTR1:[0-9]+]] {			// CHECK2-SAME: (i32* [[C:%.*]]) #[[ATTR1:[0-9]+]] {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
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	//			//
	// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l25			// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l25
	// CHECK3-SAME: (i32* nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR0:[0-9]+]] {			// CHECK3-SAME: (i32* nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR0:[0-9]+]] {
	// CHECK3-NEXT: entry:			// CHECK3-NEXT: entry:
	// CHECK3-NEXT: [[C_ADDR:%.]] = alloca i32, align 4			// CHECK3-NEXT: [[C_ADDR:%.]] = alloca i32, align 4
	// CHECK3-NEXT: [[CAPTURED_VARS_ADDRS:%.]] = alloca [1 x i8], align 4			// CHECK3-NEXT: [[CAPTURED_VARS_ADDRS:%.]] = alloca [1 x i8], align 4
	// CHECK3-NEXT: store i32* [[C]], i32** [[C_ADDR]], align 4			// CHECK3-NEXT: store i32* [[C]], i32** [[C_ADDR]], align 4
	// CHECK3-NEXT: [[TMP0:%.]] = load i32, i32** [[C_ADDR]], align 4			// CHECK3-NEXT: [[TMP0:%.]] = load i32, i32** [[C_ADDR]], align 4
	// CHECK3-NEXT: [[TMP1:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1:[0-9]+]], i8 1, i1 true, i1 true)			// CHECK3-NEXT: [[TMP1:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l25_kernel_info, i1 true)
	// CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1			// CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
	// CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]			// CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
	// CHECK3: user_code.entry:			// CHECK3: user_code.entry:
	// CHECK3-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB1]])			// CHECK3-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB1:[0-9]+]])
	// CHECK3-NEXT: call void @_Z3usePi(i32* [[TMP0]]) #[[ATTR6:[0-9]+]]			// CHECK3-NEXT: call void @_Z3usePi(i32* [[TMP0]]) #[[ATTR6:[0-9]+]]
	// CHECK3-NEXT: [[TMP3:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[CAPTURED_VARS_ADDRS]], i32 0, i32 0			// CHECK3-NEXT: [[TMP3:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
	// CHECK3-NEXT: [[TMP4:%.]] = bitcast i32 [[TMP0]] to i8*			// CHECK3-NEXT: [[TMP4:%.]] = bitcast i32 [[TMP0]] to i8*
	// CHECK3-NEXT: store i8* [[TMP4]], i8** [[TMP3]], align 4			// CHECK3-NEXT: store i8* [[TMP4]], i8** [[TMP3]], align 4
	// CHECK3-NEXT: [[TMP5:%.]] = bitcast [1 x i8]* [[CAPTURED_VARS_ADDRS]] to i8**			// CHECK3-NEXT: [[TMP5:%.]] = bitcast [1 x i8]* [[CAPTURED_VARS_ADDRS]] to i8**
	// CHECK3-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1, i32 2, i32 -1, i8* bitcast (void (i32, i32, i32) @__omp_outlined__ to i8), i8 bitcast (void (i16, i32)* @__omp_outlined___wrapper to i8), i8* [[TMP5]], i32 1)			// CHECK3-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1, i32 2, i32 -1, i8* bitcast (void (i32, i32, i32) @__omp_outlined__ to i8), i8 bitcast (void (i16, i32)* @__omp_outlined___wrapper to i8), i8* [[TMP5]], i32 1)
	// CHECK3-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true)			// CHECK3-NEXT: call void @__kmpc_target_deinit(i1 true)
	// CHECK3-NEXT: ret void			// CHECK3-NEXT: ret void
	// CHECK3: worker.exit:			// CHECK3: worker.exit:
	// CHECK3-NEXT: ret void			// CHECK3-NEXT: ret void
	//			//
	//			//
	// CHECK3-LABEL: define {{[^@]+}}@_Z3usePi			// CHECK3-LABEL: define {{[^@]+}}@_Z3usePi
	// CHECK3-SAME: (i32* [[C:%.*]]) #[[ATTR1:[0-9]+]] {			// CHECK3-SAME: (i32* [[C:%.*]]) #[[ATTR1:[0-9]+]] {
	// CHECK3-NEXT: entry:			// CHECK3-NEXT: entry:
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clang/test/OpenMP/nvptx_parallel_codegen.cpp

	Show First 20 Lines • Show All 1,440 Lines • ▼ Show 20 Lines
	// CHECK1-SAME: (i64 [[A:%.*]]) #[[ATTR0:[0-9]+]] {			// CHECK1-SAME: (i64 [[A:%.*]]) #[[ATTR0:[0-9]+]] {
	// CHECK1-NEXT: entry:			// CHECK1-NEXT: entry:
	// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8			// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
	// CHECK1-NEXT: [[CAPTURED_VARS_ADDRS:%.]] = alloca [0 x i8], align 8			// CHECK1-NEXT: [[CAPTURED_VARS_ADDRS:%.]] = alloca [0 x i8], align 8
	// CHECK1-NEXT: [[CAPTURED_VARS_ADDRS1:%.]] = alloca [0 x i8], align 8			// CHECK1-NEXT: [[CAPTURED_VARS_ADDRS1:%.]] = alloca [0 x i8], align 8
	// CHECK1-NEXT: [[CAPTURED_VARS_ADDRS2:%.]] = alloca [0 x i8], align 8			// CHECK1-NEXT: [[CAPTURED_VARS_ADDRS2:%.]] = alloca [0 x i8], align 8
	// CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8			// CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
	// CHECK1-NEXT: [[CONV:%.]] = bitcast i64 [[A_ADDR]] to i32*			// CHECK1-NEXT: [[CONV:%.]] = bitcast i64 [[A_ADDR]] to i32*
	// CHECK1-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1:[0-9]+]], i8 1, i1 true, i1 true)			// CHECK1-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l26_kernel_info, i1 true)
	// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1			// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
	// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]			// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
	// CHECK1: user_code.entry:			// CHECK1: user_code.entry:
	// CHECK1-NEXT: [[TMP1:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB1]])			// CHECK1-NEXT: [[TMP1:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB1:[0-9]+]])
	// CHECK1-NEXT: [[TMP2:%.]] = bitcast [0 x i8]* [[CAPTURED_VARS_ADDRS]] to i8**			// CHECK1-NEXT: [[TMP2:%.]] = bitcast [0 x i8]* [[CAPTURED_VARS_ADDRS]] to i8**
	// CHECK1-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32, i32)* @__omp_outlined__ to i8), i8 bitcast (void (i16, i32)* @__omp_outlined___wrapper to i8), i8* [[TMP2]], i64 0)			// CHECK1-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32, i32)* @__omp_outlined__ to i8), i8 bitcast (void (i16, i32)* @__omp_outlined___wrapper to i8), i8* [[TMP2]], i64 0)
	// CHECK1-NEXT: [[TMP3:%.]] = bitcast [0 x i8]* [[CAPTURED_VARS_ADDRS1]] to i8**			// CHECK1-NEXT: [[TMP3:%.]] = bitcast [0 x i8]* [[CAPTURED_VARS_ADDRS1]] to i8**
	// CHECK1-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 0, i32 -1, i32 -1, i8* bitcast (void (i32, i32)* @__omp_outlined__1 to i8), i8 bitcast (void (i16, i32)* @__omp_outlined__1_wrapper to i8), i8* [[TMP3]], i64 0)			// CHECK1-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 0, i32 -1, i32 -1, i8* bitcast (void (i32, i32)* @__omp_outlined__1 to i8), i8 bitcast (void (i16, i32)* @__omp_outlined__1_wrapper to i8), i8* [[TMP3]], i64 0)
	// CHECK1-NEXT: [[TMP4:%.]] = bitcast [0 x i8]* [[CAPTURED_VARS_ADDRS2]] to i8**			// CHECK1-NEXT: [[TMP4:%.]] = bitcast [0 x i8]* [[CAPTURED_VARS_ADDRS2]] to i8**
	// CHECK1-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32, i32)* @__omp_outlined__2 to i8), i8 bitcast (void (i16, i32)* @__omp_outlined__2_wrapper to i8), i8* [[TMP4]], i64 0)			// CHECK1-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32, i32)* @__omp_outlined__2 to i8), i8 bitcast (void (i16, i32)* @__omp_outlined__2_wrapper to i8), i8* [[TMP4]], i64 0)
	// CHECK1-NEXT: [[TMP5:%.]] = load i32, i32 [[CONV]], align 4			// CHECK1-NEXT: [[TMP5:%.]] = load i32, i32 [[CONV]], align 8
	// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP5]], 1			// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP5]], 1
	// CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4			// CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
	// CHECK1-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true)			// CHECK1-NEXT: call void @__kmpc_target_deinit(i1 true)
	// CHECK1-NEXT: ret void			// CHECK1-NEXT: ret void
	// CHECK1: worker.exit:			// CHECK1: worker.exit:
	// CHECK1-NEXT: ret void			// CHECK1-NEXT: ret void
	//			//
	//			//
	// CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__			// CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__
	// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {			// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
	// CHECK1-NEXT: entry:			// CHECK1-NEXT: entry:
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	// CHECK1-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8			// CHECK1-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
	// CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8			// CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
	// CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8			// CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
	// CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8			// CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
	// CHECK1-NEXT: [[CONV:%.]] = bitcast i64 [[N_ADDR]] to i32*			// CHECK1-NEXT: [[CONV:%.]] = bitcast i64 [[N_ADDR]] to i32*
	// CHECK1-NEXT: [[CONV1:%.]] = bitcast i64 [[A_ADDR]] to i32*			// CHECK1-NEXT: [[CONV1:%.]] = bitcast i64 [[A_ADDR]] to i32*
	// CHECK1-NEXT: [[CONV2:%.]] = bitcast i64 [[AA_ADDR]] to i16*			// CHECK1-NEXT: [[CONV2:%.]] = bitcast i64 [[AA_ADDR]] to i16*
	// CHECK1-NEXT: [[TMP0:%.]] = load [10 x i32], [10 x i32]** [[B_ADDR]], align 8			// CHECK1-NEXT: [[TMP0:%.]] = load [10 x i32], [10 x i32]** [[B_ADDR]], align 8
	// CHECK1-NEXT: [[TMP1:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 1, i1 true, i1 true)			// CHECK1-NEXT: [[TMP1:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l43_kernel_info, i1 true)
	// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1			// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
	// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]			// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
	// CHECK1: user_code.entry:			// CHECK1: user_code.entry:
	// CHECK1-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB1]])			// CHECK1-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB1]])
	// CHECK1-NEXT: [[TMP3:%.]] = load i32, i32 [[CONV]], align 4			// CHECK1-NEXT: [[TMP3:%.]] = load i32, i32 [[CONV]], align 8
	// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 1000			// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 1000
	// CHECK1-NEXT: [[TMP4:%.*]] = zext i1 [[CMP]] to i32			// CHECK1-NEXT: [[TMP4:%.*]] = zext i1 [[CMP]] to i32
	// CHECK1-NEXT: [[TMP5:%.]] = bitcast [0 x i8]* [[CAPTURED_VARS_ADDRS]] to i8**			// CHECK1-NEXT: [[TMP5:%.]] = bitcast [0 x i8]* [[CAPTURED_VARS_ADDRS]] to i8**
	// CHECK1-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 [[TMP4]], i32 -1, i32 -1, i8* bitcast (void (i32, i32)* @__omp_outlined__3 to i8), i8 bitcast (void (i16, i32)* @__omp_outlined__3_wrapper to i8), i8* [[TMP5]], i64 0)			// CHECK1-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 [[TMP4]], i32 -1, i32 -1, i8* bitcast (void (i32, i32)* @__omp_outlined__3 to i8), i8 bitcast (void (i16, i32)* @__omp_outlined__3_wrapper to i8), i8* [[TMP5]], i64 0)
	// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[CONV1]], align 4			// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[CONV1]], align 8
	// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], 1			// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], 1
	// CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV1]], align 4			// CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV1]], align 8
	// CHECK1-NEXT: [[TMP7:%.]] = load i16, i16 [[CONV2]], align 2			// CHECK1-NEXT: [[TMP7:%.]] = load i16, i16 [[CONV2]], align 8
	// CHECK1-NEXT: [[CONV3:%.*]] = sext i16 [[TMP7]] to i32			// CHECK1-NEXT: [[CONV3:%.*]] = sext i16 [[TMP7]] to i32
	// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1			// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
	// CHECK1-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16			// CHECK1-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
	// CHECK1-NEXT: store i16 [[CONV5]], i16* [[CONV2]], align 2			// CHECK1-NEXT: store i16 [[CONV5]], i16* [[CONV2]], align 8
	// CHECK1-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i64 0, i64 2			// CHECK1-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i64 0, i64 2
	// CHECK1-NEXT: [[TMP8:%.]] = load i32, i32 [[ARRAYIDX]], align 4			// CHECK1-NEXT: [[TMP8:%.]] = load i32, i32 [[ARRAYIDX]], align 4
	// CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP8]], 1			// CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP8]], 1
	// CHECK1-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4			// CHECK1-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4
	// CHECK1-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true)			// CHECK1-NEXT: call void @__kmpc_target_deinit(i1 true)
	// CHECK1-NEXT: ret void			// CHECK1-NEXT: ret void
	// CHECK1: worker.exit:			// CHECK1: worker.exit:
	// CHECK1-NEXT: ret void			// CHECK1-NEXT: ret void
	//			//
	//			//
	// CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__3			// CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__3
	// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {			// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
	// CHECK1-NEXT: entry:			// CHECK1-NEXT: entry:
	Show All 26 Lines
	//			//
	// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l55			// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l55
	// CHECK1-SAME: (i64 [[A:%.*]]) #[[ATTR0]] {			// CHECK1-SAME: (i64 [[A:%.*]]) #[[ATTR0]] {
	// CHECK1-NEXT: entry:			// CHECK1-NEXT: entry:
	// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8			// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
	// CHECK1-NEXT: [[CAPTURED_VARS_ADDRS:%.]] = alloca [1 x i8], align 8			// CHECK1-NEXT: [[CAPTURED_VARS_ADDRS:%.]] = alloca [1 x i8], align 8
	// CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8			// CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
	// CHECK1-NEXT: [[CONV:%.]] = bitcast i64 [[A_ADDR]] to i32*			// CHECK1-NEXT: [[CONV:%.]] = bitcast i64 [[A_ADDR]] to i32*
	// CHECK1-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 1, i1 true, i1 true)			// CHECK1-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l55_kernel_info, i1 true)
	// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1			// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
	// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]			// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
	// CHECK1: user_code.entry:			// CHECK1: user_code.entry:
	// CHECK1-NEXT: [[TMP1:%.]] = load i32, i32 [[CONV]], align 4			// CHECK1-NEXT: [[TMP1:%.]] = load i32, i32 [[CONV]], align 8
	// CHECK1-NEXT: [[A1:%.]] = call align 16 i8 @__kmpc_alloc_shared(i64 4)			// CHECK1-NEXT: [[A1:%.]] = call align 16 i8 @__kmpc_alloc_shared(i64 4)
	// CHECK1-NEXT: [[A_ON_STACK:%.]] = bitcast i8 [[A1]] to i32*			// CHECK1-NEXT: [[A_ON_STACK:%.]] = bitcast i8 [[A1]] to i32*
	// CHECK1-NEXT: store i32 [[TMP1]], i32* [[A_ON_STACK]], align 4			// CHECK1-NEXT: store i32 [[TMP1]], i32* [[A_ON_STACK]], align 4
	// CHECK1-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB1]])			// CHECK1-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB1]])
	// CHECK1-NEXT: [[TMP3:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 0			// CHECK1-NEXT: [[TMP3:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
	// CHECK1-NEXT: [[TMP4:%.]] = bitcast i32 [[A_ON_STACK]] to i8*			// CHECK1-NEXT: [[TMP4:%.]] = bitcast i32 [[A_ON_STACK]] to i8*
	// CHECK1-NEXT: store i8* [[TMP4]], i8** [[TMP3]], align 8			// CHECK1-NEXT: store i8* [[TMP4]], i8** [[TMP3]], align 8
	// CHECK1-NEXT: [[TMP5:%.]] = bitcast [1 x i8]* [[CAPTURED_VARS_ADDRS]] to i8**			// CHECK1-NEXT: [[TMP5:%.]] = bitcast [1 x i8]* [[CAPTURED_VARS_ADDRS]] to i8**
	// CHECK1-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32, i32, i32) @__omp_outlined__4 to i8), i8 bitcast (void (i16, i32)* @__omp_outlined__4_wrapper to i8), i8* [[TMP5]], i64 1)			// CHECK1-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32, i32, i32) @__omp_outlined__4 to i8), i8 bitcast (void (i16, i32)* @__omp_outlined__4_wrapper to i8), i8* [[TMP5]], i64 1)
	// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[A_ON_STACK]], align 4			// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[A_ON_STACK]], align 4
	// CHECK1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP6]], 1			// CHECK1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP6]], 1
	// CHECK1-NEXT: store i32 [[INC]], i32* [[A_ON_STACK]], align 4			// CHECK1-NEXT: store i32 [[INC]], i32* [[A_ON_STACK]], align 4
	// CHECK1-NEXT: call void @__kmpc_free_shared(i8* [[A1]], i64 4)			// CHECK1-NEXT: call void @__kmpc_free_shared(i8* [[A1]], i64 4)
	// CHECK1-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true)			// CHECK1-NEXT: call void @__kmpc_target_deinit(i1 true)
	// CHECK1-NEXT: ret void			// CHECK1-NEXT: ret void
	// CHECK1: worker.exit:			// CHECK1: worker.exit:
	// CHECK1-NEXT: ret void			// CHECK1-NEXT: ret void
	//			//
	//			//
	// CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__4			// CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__4
	// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i32 nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR0]] {			// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i32 nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR0]] {
	// CHECK1-NEXT: entry:			// CHECK1-NEXT: entry:
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	// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l26			// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l26
	// CHECK2-SAME: (i32 [[A:%.*]]) #[[ATTR0:[0-9]+]] {			// CHECK2-SAME: (i32 [[A:%.*]]) #[[ATTR0:[0-9]+]] {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	// CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4			// CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
	// CHECK2-NEXT: [[CAPTURED_VARS_ADDRS:%.]] = alloca [0 x i8], align 4			// CHECK2-NEXT: [[CAPTURED_VARS_ADDRS:%.]] = alloca [0 x i8], align 4
	// CHECK2-NEXT: [[CAPTURED_VARS_ADDRS1:%.]] = alloca [0 x i8], align 4			// CHECK2-NEXT: [[CAPTURED_VARS_ADDRS1:%.]] = alloca [0 x i8], align 4
	// CHECK2-NEXT: [[CAPTURED_VARS_ADDRS2:%.]] = alloca [0 x i8], align 4			// CHECK2-NEXT: [[CAPTURED_VARS_ADDRS2:%.]] = alloca [0 x i8], align 4
	// CHECK2-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4			// CHECK2-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
	// CHECK2-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1:[0-9]+]], i8 1, i1 true, i1 true)			// CHECK2-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l26_kernel_info, i1 true)
	// CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1			// CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
	// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]			// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
	// CHECK2: user_code.entry:			// CHECK2: user_code.entry:
	// CHECK2-NEXT: [[TMP1:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB1]])			// CHECK2-NEXT: [[TMP1:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB1:[0-9]+]])
	// CHECK2-NEXT: [[TMP2:%.]] = bitcast [0 x i8]* [[CAPTURED_VARS_ADDRS]] to i8**			// CHECK2-NEXT: [[TMP2:%.]] = bitcast [0 x i8]* [[CAPTURED_VARS_ADDRS]] to i8**
	// CHECK2-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32, i32)* @__omp_outlined__ to i8), i8 bitcast (void (i16, i32)* @__omp_outlined___wrapper to i8), i8* [[TMP2]], i32 0)			// CHECK2-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32, i32)* @__omp_outlined__ to i8), i8 bitcast (void (i16, i32)* @__omp_outlined___wrapper to i8), i8* [[TMP2]], i32 0)
	// CHECK2-NEXT: [[TMP3:%.]] = bitcast [0 x i8]* [[CAPTURED_VARS_ADDRS1]] to i8**			// CHECK2-NEXT: [[TMP3:%.]] = bitcast [0 x i8]* [[CAPTURED_VARS_ADDRS1]] to i8**
	// CHECK2-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 0, i32 -1, i32 -1, i8* bitcast (void (i32, i32)* @__omp_outlined__1 to i8), i8 bitcast (void (i16, i32)* @__omp_outlined__1_wrapper to i8), i8* [[TMP3]], i32 0)			// CHECK2-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 0, i32 -1, i32 -1, i8* bitcast (void (i32, i32)* @__omp_outlined__1 to i8), i8 bitcast (void (i16, i32)* @__omp_outlined__1_wrapper to i8), i8* [[TMP3]], i32 0)
	// CHECK2-NEXT: [[TMP4:%.]] = bitcast [0 x i8]* [[CAPTURED_VARS_ADDRS2]] to i8**			// CHECK2-NEXT: [[TMP4:%.]] = bitcast [0 x i8]* [[CAPTURED_VARS_ADDRS2]] to i8**
	// CHECK2-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32, i32)* @__omp_outlined__2 to i8), i8 bitcast (void (i16, i32)* @__omp_outlined__2_wrapper to i8), i8* [[TMP4]], i32 0)			// CHECK2-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32, i32)* @__omp_outlined__2 to i8), i8 bitcast (void (i16, i32)* @__omp_outlined__2_wrapper to i8), i8* [[TMP4]], i32 0)
	// CHECK2-NEXT: [[TMP5:%.]] = load i32, i32 [[A_ADDR]], align 4			// CHECK2-NEXT: [[TMP5:%.]] = load i32, i32 [[A_ADDR]], align 4
	// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP5]], 1			// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP5]], 1
	// CHECK2-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4			// CHECK2-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
	// CHECK2-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true)			// CHECK2-NEXT: call void @__kmpc_target_deinit(i1 true)
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	// CHECK2: worker.exit:			// CHECK2: worker.exit:
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__			// CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__
	// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {			// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
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	// CHECK2-NEXT: [[B_ADDR:%.]] = alloca [10 x i32], align 4			// CHECK2-NEXT: [[B_ADDR:%.]] = alloca [10 x i32], align 4
	// CHECK2-NEXT: [[CAPTURED_VARS_ADDRS:%.]] = alloca [0 x i8], align 4			// CHECK2-NEXT: [[CAPTURED_VARS_ADDRS:%.]] = alloca [0 x i8], align 4
	// CHECK2-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4			// CHECK2-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
	// CHECK2-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4			// CHECK2-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
	// CHECK2-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4			// CHECK2-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
	// CHECK2-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4			// CHECK2-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
	// CHECK2-NEXT: [[CONV:%.]] = bitcast i32 [[AA_ADDR]] to i16*			// CHECK2-NEXT: [[CONV:%.]] = bitcast i32 [[AA_ADDR]] to i16*
	// CHECK2-NEXT: [[TMP0:%.]] = load [10 x i32], [10 x i32]** [[B_ADDR]], align 4			// CHECK2-NEXT: [[TMP0:%.]] = load [10 x i32], [10 x i32]** [[B_ADDR]], align 4
	// CHECK2-NEXT: [[TMP1:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 1, i1 true, i1 true)			// CHECK2-NEXT: [[TMP1:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l43_kernel_info, i1 true)
	// CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1			// CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
	// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]			// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
	// CHECK2: user_code.entry:			// CHECK2: user_code.entry:
	// CHECK2-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB1]])			// CHECK2-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB1]])
	// CHECK2-NEXT: [[TMP3:%.]] = load i32, i32 [[N_ADDR]], align 4			// CHECK2-NEXT: [[TMP3:%.]] = load i32, i32 [[N_ADDR]], align 4
	// CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 1000			// CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 1000
	// CHECK2-NEXT: [[TMP4:%.*]] = zext i1 [[CMP]] to i32			// CHECK2-NEXT: [[TMP4:%.*]] = zext i1 [[CMP]] to i32
	// CHECK2-NEXT: [[TMP5:%.]] = bitcast [0 x i8]* [[CAPTURED_VARS_ADDRS]] to i8**			// CHECK2-NEXT: [[TMP5:%.]] = bitcast [0 x i8]* [[CAPTURED_VARS_ADDRS]] to i8**
	// CHECK2-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 [[TMP4]], i32 -1, i32 -1, i8* bitcast (void (i32, i32)* @__omp_outlined__3 to i8), i8 bitcast (void (i16, i32)* @__omp_outlined__3_wrapper to i8), i8* [[TMP5]], i32 0)			// CHECK2-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 [[TMP4]], i32 -1, i32 -1, i8* bitcast (void (i32, i32)* @__omp_outlined__3 to i8), i8 bitcast (void (i16, i32)* @__omp_outlined__3_wrapper to i8), i8* [[TMP5]], i32 0)
	// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[A_ADDR]], align 4			// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[A_ADDR]], align 4
	// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], 1			// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], 1
	// CHECK2-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4			// CHECK2-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
	// CHECK2-NEXT: [[TMP7:%.]] = load i16, i16 [[CONV]], align 2			// CHECK2-NEXT: [[TMP7:%.]] = load i16, i16 [[CONV]], align 4
	// CHECK2-NEXT: [[CONV1:%.*]] = sext i16 [[TMP7]] to i32			// CHECK2-NEXT: [[CONV1:%.*]] = sext i16 [[TMP7]] to i32
	// CHECK2-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1			// CHECK2-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1
	// CHECK2-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16			// CHECK2-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
	// CHECK2-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2			// CHECK2-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 4
	// CHECK2-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i32 0, i32 2			// CHECK2-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i32 0, i32 2
	// CHECK2-NEXT: [[TMP8:%.]] = load i32, i32 [[ARRAYIDX]], align 4			// CHECK2-NEXT: [[TMP8:%.]] = load i32, i32 [[ARRAYIDX]], align 4
	// CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1			// CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1
	// CHECK2-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4			// CHECK2-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4
	// CHECK2-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true)			// CHECK2-NEXT: call void @__kmpc_target_deinit(i1 true)
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	// CHECK2: worker.exit:			// CHECK2: worker.exit:
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__3			// CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__3
	// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {			// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
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	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l55			// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l55
	// CHECK2-SAME: (i32 [[A:%.*]]) #[[ATTR0]] {			// CHECK2-SAME: (i32 [[A:%.*]]) #[[ATTR0]] {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	// CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4			// CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
	// CHECK2-NEXT: [[CAPTURED_VARS_ADDRS:%.]] = alloca [1 x i8], align 4			// CHECK2-NEXT: [[CAPTURED_VARS_ADDRS:%.]] = alloca [1 x i8], align 4
	// CHECK2-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4			// CHECK2-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
	// CHECK2-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 1, i1 true, i1 true)			// CHECK2-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l55_kernel_info, i1 true)
	// CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1			// CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
	// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]			// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
	// CHECK2: user_code.entry:			// CHECK2: user_code.entry:
	// CHECK2-NEXT: [[TMP1:%.]] = load i32, i32 [[A_ADDR]], align 4			// CHECK2-NEXT: [[TMP1:%.]] = load i32, i32 [[A_ADDR]], align 4
	// CHECK2-NEXT: [[A1:%.]] = call align 4 i8 @__kmpc_alloc_shared(i32 4)			// CHECK2-NEXT: [[A1:%.]] = call align 4 i8 @__kmpc_alloc_shared(i32 4)
	// CHECK2-NEXT: [[A_ON_STACK:%.]] = bitcast i8 [[A1]] to i32*			// CHECK2-NEXT: [[A_ON_STACK:%.]] = bitcast i8 [[A1]] to i32*
	// CHECK2-NEXT: store i32 [[TMP1]], i32* [[A_ON_STACK]], align 4			// CHECK2-NEXT: store i32 [[TMP1]], i32* [[A_ON_STACK]], align 4
	// CHECK2-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB1]])			// CHECK2-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB1]])
	// CHECK2-NEXT: [[TMP3:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[CAPTURED_VARS_ADDRS]], i32 0, i32 0			// CHECK2-NEXT: [[TMP3:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
	// CHECK2-NEXT: [[TMP4:%.]] = bitcast i32 [[A_ON_STACK]] to i8*			// CHECK2-NEXT: [[TMP4:%.]] = bitcast i32 [[A_ON_STACK]] to i8*
	// CHECK2-NEXT: store i8* [[TMP4]], i8** [[TMP3]], align 4			// CHECK2-NEXT: store i8* [[TMP4]], i8** [[TMP3]], align 4
	// CHECK2-NEXT: [[TMP5:%.]] = bitcast [1 x i8]* [[CAPTURED_VARS_ADDRS]] to i8**			// CHECK2-NEXT: [[TMP5:%.]] = bitcast [1 x i8]* [[CAPTURED_VARS_ADDRS]] to i8**
	// CHECK2-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32, i32, i32) @__omp_outlined__4 to i8), i8 bitcast (void (i16, i32)* @__omp_outlined__4_wrapper to i8), i8* [[TMP5]], i32 1)			// CHECK2-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32, i32, i32) @__omp_outlined__4 to i8), i8 bitcast (void (i16, i32)* @__omp_outlined__4_wrapper to i8), i8* [[TMP5]], i32 1)
	// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[A_ON_STACK]], align 4			// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[A_ON_STACK]], align 4
	// CHECK2-NEXT: [[INC:%.*]] = add nsw i32 [[TMP6]], 1			// CHECK2-NEXT: [[INC:%.*]] = add nsw i32 [[TMP6]], 1
	// CHECK2-NEXT: store i32 [[INC]], i32* [[A_ON_STACK]], align 4			// CHECK2-NEXT: store i32 [[INC]], i32* [[A_ON_STACK]], align 4
	// CHECK2-NEXT: call void @__kmpc_free_shared(i8* [[A1]], i32 4)			// CHECK2-NEXT: call void @__kmpc_free_shared(i8* [[A1]], i32 4)
	// CHECK2-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true)			// CHECK2-NEXT: call void @__kmpc_target_deinit(i1 true)
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	// CHECK2: worker.exit:			// CHECK2: worker.exit:
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__4			// CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__4
	// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i32 nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR0]] {			// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i32 nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR0]] {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
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clang/test/OpenMP/nvptx_parallel_for_codegen.cpp

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	// CHECK-NEXT: entry:			// CHECK-NEXT: entry:
	// CHECK-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8			// CHECK-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8
	// CHECK-NEXT: [[B_ADDR:%.]] = alloca [10 x i32], align 8			// CHECK-NEXT: [[B_ADDR:%.]] = alloca [10 x i32], align 8
	// CHECK-NEXT: [[CAPTURED_VARS_ADDRS:%.]] = alloca [2 x i8], align 8			// CHECK-NEXT: [[CAPTURED_VARS_ADDRS:%.]] = alloca [2 x i8], align 8
	// CHECK-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8			// CHECK-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
	// CHECK-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8			// CHECK-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
	// CHECK-NEXT: [[CONV:%.]] = bitcast i64 [[N_ADDR]] to i32*			// CHECK-NEXT: [[CONV:%.]] = bitcast i64 [[N_ADDR]] to i32*
	// CHECK-NEXT: [[TMP0:%.]] = load [10 x i32], [10 x i32]** [[B_ADDR]], align 8			// CHECK-NEXT: [[TMP0:%.]] = load [10 x i32], [10 x i32]** [[B_ADDR]], align 8
	// CHECK-NEXT: [[TMP1:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1:[0-9]+]], i8 1, i1 true, i1 true)			// CHECK-NEXT: [[TMP1:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l13_kernel_info, i1 true)
	// CHECK-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1			// CHECK-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
	// CHECK-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]			// CHECK-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
	// CHECK: user_code.entry:			// CHECK: user_code.entry:
	// CHECK-NEXT: [[D:%.]] = call align 8 i8 @__kmpc_alloc_shared(i64 4)			// CHECK-NEXT: [[D:%.]] = call align 8 i8 @__kmpc_alloc_shared(i64 4)
	// CHECK-NEXT: [[D_ON_STACK:%.]] = bitcast i8 [[D]] to i32*			// CHECK-NEXT: [[D_ON_STACK:%.]] = bitcast i8 [[D]] to i32*
	// CHECK-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB1]])			// CHECK-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB1:[0-9]+]])
	// CHECK-NEXT: [[TMP3:%.]] = load i32, i32 [[CONV]], align 4			// CHECK-NEXT: [[TMP3:%.]] = load i32, i32 [[CONV]], align 8
	// CHECK-NEXT: store i32 [[TMP3]], i32* [[D_ON_STACK]], align 4			// CHECK-NEXT: store i32 [[TMP3]], i32* [[D_ON_STACK]], align 4
	// CHECK-NEXT: [[TMP4:%.]] = getelementptr inbounds [2 x i8], [2 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 0			// CHECK-NEXT: [[TMP4:%.]] = getelementptr inbounds [2 x i8], [2 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
	// CHECK-NEXT: [[TMP5:%.]] = bitcast [10 x i32] [[TMP0]] to i8*			// CHECK-NEXT: [[TMP5:%.]] = bitcast [10 x i32] [[TMP0]] to i8*
	// CHECK-NEXT: store i8* [[TMP5]], i8** [[TMP4]], align 8			// CHECK-NEXT: store i8* [[TMP5]], i8** [[TMP4]], align 8
	// CHECK-NEXT: [[TMP6:%.]] = getelementptr inbounds [2 x i8], [2 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 1			// CHECK-NEXT: [[TMP6:%.]] = getelementptr inbounds [2 x i8], [2 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
	// CHECK-NEXT: [[TMP7:%.]] = bitcast i32 [[D_ON_STACK]] to i8*			// CHECK-NEXT: [[TMP7:%.]] = bitcast i32 [[D_ON_STACK]] to i8*
	// CHECK-NEXT: store i8* [[TMP7]], i8** [[TMP6]], align 8			// CHECK-NEXT: store i8* [[TMP7]], i8** [[TMP6]], align 8
	// CHECK-NEXT: [[TMP8:%.]] = bitcast [2 x i8]* [[CAPTURED_VARS_ADDRS]] to i8**			// CHECK-NEXT: [[TMP8:%.]] = bitcast [2 x i8]* [[CAPTURED_VARS_ADDRS]] to i8**
	// CHECK-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32, i32, [10 x i32], i32)* @__omp_outlined__ to i8), i8 bitcast (void (i16, i32)* @__omp_outlined___wrapper to i8), i8* [[TMP8]], i64 2)			// CHECK-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32, i32, [10 x i32], i32)* @__omp_outlined__ to i8), i8 bitcast (void (i16, i32)* @__omp_outlined___wrapper to i8), i8* [[TMP8]], i64 2)
	// CHECK-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i64 0, i64 3			// CHECK-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i64 0, i64 3
	// CHECK-NEXT: [[TMP9:%.]] = load i32, i32 [[ARRAYIDX]], align 4			// CHECK-NEXT: [[TMP9:%.]] = load i32, i32 [[ARRAYIDX]], align 4
	// CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], 1			// CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], 1
	// CHECK-NEXT: store i32 [[ADD]], i32* [[ARRAYIDX]], align 4			// CHECK-NEXT: store i32 [[ADD]], i32* [[ARRAYIDX]], align 4
	// CHECK-NEXT: call void @__kmpc_free_shared(i8* [[D]], i64 4)			// CHECK-NEXT: call void @__kmpc_free_shared(i8* [[D]], i64 4)
	// CHECK-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true)			// CHECK-NEXT: call void @__kmpc_target_deinit(i1 true)
	// CHECK-NEXT: ret void			// CHECK-NEXT: ret void
	// CHECK: worker.exit:			// CHECK: worker.exit:
	// CHECK-NEXT: ret void			// CHECK-NEXT: ret void
	//			//
	//			//
	// CHECK-LABEL: define {{[^@]+}}@__omp_outlined__			// CHECK-LABEL: define {{[^@]+}}@__omp_outlined__
	// CHECK-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], [10 x i32] nonnull align 4 dereferenceable(40) [[B:%.]], i32 nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR0]] {			// CHECK-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], [10 x i32] nonnull align 4 dereferenceable(40) [[B:%.]], i32 nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR0]] {
	// CHECK-NEXT: entry:			// CHECK-NEXT: entry:
	▲ Show 20 Lines • Show All 108 Lines • Show Last 20 Lines

clang/test/OpenMP/nvptx_target_codegen.cpp

	Show First 20 Lines • Show All 147 Lines • ▼ Show 20 Lines
	// CHECK1-SAME: (i32* [[PTR1:%.]], i32* nonnull align 8 dereferenceable(8) [[PTR2:%.*]]) #[[ATTR0:[0-9]+]] {			// CHECK1-SAME: (i32* [[PTR1:%.]], i32* nonnull align 8 dereferenceable(8) [[PTR2:%.*]]) #[[ATTR0:[0-9]+]] {
	// CHECK1-NEXT: entry:			// CHECK1-NEXT: entry:
	// CHECK1-NEXT: [[PTR1_ADDR:%.]] = alloca i32, align 8			// CHECK1-NEXT: [[PTR1_ADDR:%.]] = alloca i32, align 8
	// CHECK1-NEXT: [[PTR2_ADDR:%.]] = alloca i32*, align 8			// CHECK1-NEXT: [[PTR2_ADDR:%.]] = alloca i32*, align 8
	// CHECK1-NEXT: [[CAPTURED_VARS_ADDRS:%.]] = alloca [2 x i8], align 8			// CHECK1-NEXT: [[CAPTURED_VARS_ADDRS:%.]] = alloca [2 x i8], align 8
	// CHECK1-NEXT: store i32* [[PTR1]], i32** [[PTR1_ADDR]], align 8			// CHECK1-NEXT: store i32* [[PTR1]], i32** [[PTR1_ADDR]], align 8
	// CHECK1-NEXT: store i32 [[PTR2]], i32* [[PTR2_ADDR]], align 8			// CHECK1-NEXT: store i32 [[PTR2]], i32* [[PTR2_ADDR]], align 8
	// CHECK1-NEXT: [[TMP0:%.]] = load i32, i32** [[PTR2_ADDR]], align 8			// CHECK1-NEXT: [[TMP0:%.]] = load i32, i32** [[PTR2_ADDR]], align 8
	// CHECK1-NEXT: [[TMP1:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1:[0-9]+]], i8 2, i1 false, i1 true)			// CHECK1-NEXT: [[TMP1:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9targetBarPiS__l25_kernel_info, i1 true)
	// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1			// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
	// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]			// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
	// CHECK1: user_code.entry:			// CHECK1: user_code.entry:
	// CHECK1-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB2:[0-9]+]])			// CHECK1-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB2:[0-9]+]])
	// CHECK1-NEXT: [[TMP3:%.]] = getelementptr inbounds [2 x i8], [2 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 0			// CHECK1-NEXT: [[TMP3:%.]] = getelementptr inbounds [2 x i8], [2 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
	// CHECK1-NEXT: [[TMP4:%.]] = bitcast i32* [[PTR1_ADDR]] to i8*			// CHECK1-NEXT: [[TMP4:%.]] = bitcast i32* [[PTR1_ADDR]] to i8*
	// CHECK1-NEXT: store i8* [[TMP4]], i8** [[TMP3]], align 8			// CHECK1-NEXT: store i8* [[TMP4]], i8** [[TMP3]], align 8
	// CHECK1-NEXT: [[TMP5:%.]] = getelementptr inbounds [2 x i8], [2 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 1			// CHECK1-NEXT: [[TMP5:%.]] = getelementptr inbounds [2 x i8], [2 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
	// CHECK1-NEXT: [[TMP6:%.]] = bitcast i32* [[TMP0]] to i8*			// CHECK1-NEXT: [[TMP6:%.]] = bitcast i32* [[TMP0]] to i8*
	// CHECK1-NEXT: store i8* [[TMP6]], i8** [[TMP5]], align 8			// CHECK1-NEXT: store i8* [[TMP6]], i8** [[TMP5]], align 8
	// CHECK1-NEXT: [[TMP7:%.]] = bitcast [2 x i8]* [[CAPTURED_VARS_ADDRS]] to i8**			// CHECK1-NEXT: [[TMP7:%.]] = bitcast [2 x i8]* [[CAPTURED_VARS_ADDRS]] to i8**
	// CHECK1-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32 1, i32 2, i32 -1, i8* bitcast (void (i32, i32, i32, i32)* @__omp_outlined__ to i8), i8 null, i8** [[TMP7]], i64 2)			// CHECK1-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32 1, i32 2, i32 -1, i8* bitcast (void (i32, i32, i32, i32)* @__omp_outlined__ to i8), i8 null, i8** [[TMP7]], i64 2)
	// CHECK1-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 true)			// CHECK1-NEXT: call void @__kmpc_target_deinit(i1 true)
	// CHECK1-NEXT: ret void			// CHECK1-NEXT: ret void
	// CHECK1: worker.exit:			// CHECK1: worker.exit:
	// CHECK1-NEXT: ret void			// CHECK1-NEXT: ret void
	//			//
	//			//
	// CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__			// CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__
	// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i32* nonnull align 8 dereferenceable(8) [[PTR1:%.]], i32* nonnull align 8 dereferenceable(8) [[PTR2:%.*]]) #[[ATTR1:[0-9]+]] {			// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i32* nonnull align 8 dereferenceable(8) [[PTR1:%.]], i32* nonnull align 8 dereferenceable(8) [[PTR2:%.*]]) #[[ATTR1:[0-9]+]] {
	// CHECK1-NEXT: entry:			// CHECK1-NEXT: entry:
	Show All 12 Lines
	// CHECK1-NEXT: [[TMP4:%.]] = load i32, i32** [[TMP0]], align 8			// CHECK1-NEXT: [[TMP4:%.]] = load i32, i32** [[TMP0]], align 8
	// CHECK1-NEXT: store i32 [[TMP3]], i32* [[TMP4]], align 4			// CHECK1-NEXT: store i32 [[TMP3]], i32* [[TMP4]], align 4
	// CHECK1-NEXT: ret void			// CHECK1-NEXT: ret void
	//			//
	//			//
	// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l39			// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l39
	// CHECK1-SAME: () #[[ATTR1]] {			// CHECK1-SAME: () #[[ATTR1]] {
	// CHECK1-NEXT: entry:			// CHECK1-NEXT: entry:
	// CHECK1-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 1, i1 true, i1 true)			// CHECK1-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l39_kernel_info, i1 true)
	// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1			// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
	// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]			// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
	// CHECK1: user_code.entry:			// CHECK1: user_code.entry:
	// CHECK1-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true)			// CHECK1-NEXT: call void @__kmpc_target_deinit(i1 true)
	// CHECK1-NEXT: ret void			// CHECK1-NEXT: ret void
	// CHECK1: worker.exit:			// CHECK1: worker.exit:
	// CHECK1-NEXT: ret void			// CHECK1-NEXT: ret void
	//			//
	//			//
	// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l47			// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l47
	// CHECK1-SAME: (i64 [[AA:%.*]]) #[[ATTR1]] {			// CHECK1-SAME: (i64 [[AA:%.*]]) #[[ATTR1]] {
	// CHECK1-NEXT: entry:			// CHECK1-NEXT: entry:
	// CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8			// CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
	// CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8			// CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
	// CHECK1-NEXT: [[CONV:%.]] = bitcast i64 [[AA_ADDR]] to i16*			// CHECK1-NEXT: [[CONV:%.]] = bitcast i64 [[AA_ADDR]] to i16*
	// CHECK1-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 1, i1 true, i1 true)			// CHECK1-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l47_kernel_info, i1 true)
	// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1			// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
	// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]			// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
	// CHECK1: user_code.entry:			// CHECK1: user_code.entry:
	// CHECK1-NEXT: [[TMP1:%.]] = load i16, i16 [[CONV]], align 2			// CHECK1-NEXT: [[TMP1:%.]] = load i16, i16 [[CONV]], align 8
	// CHECK1-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32			// CHECK1-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32
	// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1			// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1
	// CHECK1-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16			// CHECK1-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
	// CHECK1-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2			// CHECK1-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 8
	// CHECK1-NEXT: [[TMP2:%.]] = load i16, i16 [[CONV]], align 2			// CHECK1-NEXT: [[TMP2:%.]] = load i16, i16 [[CONV]], align 8
	// CHECK1-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32			// CHECK1-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32
	// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 2			// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 2
	// CHECK1-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16			// CHECK1-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
	// CHECK1-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2			// CHECK1-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 8
	// CHECK1-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true)			// CHECK1-NEXT: call void @__kmpc_target_deinit(i1 true)
	// CHECK1-NEXT: ret void			// CHECK1-NEXT: ret void
	// CHECK1: worker.exit:			// CHECK1: worker.exit:
	// CHECK1-NEXT: ret void			// CHECK1-NEXT: ret void
	//			//
	//			//
	// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l53			// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l53
	// CHECK1-SAME: (i64 [[A:%.]], [10 x float] nonnull align 4 dereferenceable(40) [[B:%.]], i64 [[VLA:%.]], float* nonnull align 4 dereferenceable(4) [[BN:%.]], [5 x [10 x double]] nonnull align 8 dereferenceable(400) [[C:%.]], i64 [[VLA1:%.]], i64 [[VLA3:%.]], double nonnull align 8 dereferenceable(8) [[CN:%.]], %struct.TT nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR1]] {			// CHECK1-SAME: (i64 [[A:%.]], [10 x float] nonnull align 4 dereferenceable(40) [[B:%.]], i64 [[VLA:%.]], float* nonnull align 4 dereferenceable(4) [[BN:%.]], [5 x [10 x double]] nonnull align 8 dereferenceable(400) [[C:%.]], i64 [[VLA1:%.]], i64 [[VLA3:%.]], double nonnull align 8 dereferenceable(8) [[CN:%.]], %struct.TT nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR1]] {
	// CHECK1-NEXT: entry:			// CHECK1-NEXT: entry:
	Show All 19 Lines
	// CHECK1-NEXT: [[TMP0:%.]] = load [10 x float], [10 x float]** [[B_ADDR]], align 8			// CHECK1-NEXT: [[TMP0:%.]] = load [10 x float], [10 x float]** [[B_ADDR]], align 8
	// CHECK1-NEXT: [[TMP1:%.]] = load i64, i64 [[VLA_ADDR]], align 8			// CHECK1-NEXT: [[TMP1:%.]] = load i64, i64 [[VLA_ADDR]], align 8
	// CHECK1-NEXT: [[TMP2:%.]] = load float, float** [[BN_ADDR]], align 8			// CHECK1-NEXT: [[TMP2:%.]] = load float, float** [[BN_ADDR]], align 8
	// CHECK1-NEXT: [[TMP3:%.]] = load [5 x [10 x double]], [5 x [10 x double]]** [[C_ADDR]], align 8			// CHECK1-NEXT: [[TMP3:%.]] = load [5 x [10 x double]], [5 x [10 x double]]** [[C_ADDR]], align 8
	// CHECK1-NEXT: [[TMP4:%.]] = load i64, i64 [[VLA_ADDR2]], align 8			// CHECK1-NEXT: [[TMP4:%.]] = load i64, i64 [[VLA_ADDR2]], align 8
	// CHECK1-NEXT: [[TMP5:%.]] = load i64, i64 [[VLA_ADDR4]], align 8			// CHECK1-NEXT: [[TMP5:%.]] = load i64, i64 [[VLA_ADDR4]], align 8
	// CHECK1-NEXT: [[TMP6:%.]] = load double, double** [[CN_ADDR]], align 8			// CHECK1-NEXT: [[TMP6:%.]] = load double, double** [[CN_ADDR]], align 8
	// CHECK1-NEXT: [[TMP7:%.]] = load %struct.TT, %struct.TT** [[D_ADDR]], align 8			// CHECK1-NEXT: [[TMP7:%.]] = load %struct.TT, %struct.TT** [[D_ADDR]], align 8
	// CHECK1-NEXT: [[TMP8:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 1, i1 true, i1 true)			// CHECK1-NEXT: [[TMP8:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l53_kernel_info, i1 true)
	// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP8]], -1			// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP8]], -1
	// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]			// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
	// CHECK1: user_code.entry:			// CHECK1: user_code.entry:
	// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[CONV]], align 4			// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[CONV]], align 8
	// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], 1			// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], 1
	// CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4			// CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
	// CHECK1-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x float], [10 x float] [[TMP0]], i64 0, i64 2			// CHECK1-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x float], [10 x float] [[TMP0]], i64 0, i64 2
	// CHECK1-NEXT: [[TMP10:%.]] = load float, float [[ARRAYIDX]], align 4			// CHECK1-NEXT: [[TMP10:%.]] = load float, float [[ARRAYIDX]], align 4
	// CHECK1-NEXT: [[CONV5:%.*]] = fpext float [[TMP10]] to double			// CHECK1-NEXT: [[CONV5:%.*]] = fpext float [[TMP10]] to double
	// CHECK1-NEXT: [[ADD6:%.*]] = fadd double [[CONV5]], 1.000000e+00			// CHECK1-NEXT: [[ADD6:%.*]] = fadd double [[CONV5]], 1.000000e+00
	// CHECK1-NEXT: [[CONV7:%.*]] = fptrunc double [[ADD6]] to float			// CHECK1-NEXT: [[CONV7:%.*]] = fptrunc double [[ADD6]] to float
	// CHECK1-NEXT: store float [[CONV7]], float* [[ARRAYIDX]], align 4			// CHECK1-NEXT: store float [[CONV7]], float* [[ARRAYIDX]], align 4
	// CHECK1-NEXT: [[ARRAYIDX8:%.]] = getelementptr inbounds float, float [[TMP2]], i64 3			// CHECK1-NEXT: [[ARRAYIDX8:%.]] = getelementptr inbounds float, float [[TMP2]], i64 3
	// CHECK1-NEXT: [[TMP11:%.]] = load float, float [[ARRAYIDX8]], align 4			// CHECK1-NEXT: [[TMP11:%.]] = load float, float [[ARRAYIDX8]], align 4
	Show All 21 Lines
	// CHECK1-NEXT: [[CONV19:%.*]] = sext i8 [[TMP16]] to i32			// CHECK1-NEXT: [[CONV19:%.*]] = sext i8 [[TMP16]] to i32
	// CHECK1-NEXT: [[ADD20:%.*]] = add nsw i32 [[CONV19]], 1			// CHECK1-NEXT: [[ADD20:%.*]] = add nsw i32 [[CONV19]], 1
	// CHECK1-NEXT: [[CONV21:%.*]] = trunc i32 [[ADD20]] to i8			// CHECK1-NEXT: [[CONV21:%.*]] = trunc i32 [[ADD20]] to i8
	// CHECK1-NEXT: store i8 [[CONV21]], i8* [[Y]], align 8			// CHECK1-NEXT: store i8 [[CONV21]], i8* [[Y]], align 8
	// CHECK1-NEXT: [[CALL:%.]] = call nonnull align 8 dereferenceable(8) i64 @_ZN2TTIxcEixEi(%struct.TT* nonnull align 8 dereferenceable(16) [[TMP7]], i32 0) #[[ATTR8:[0-9]+]]			// CHECK1-NEXT: [[CALL:%.]] = call nonnull align 8 dereferenceable(8) i64 @_ZN2TTIxcEixEi(%struct.TT* nonnull align 8 dereferenceable(16) [[TMP7]], i32 0) #[[ATTR8:[0-9]+]]
	// CHECK1-NEXT: [[TMP17:%.]] = load i64, i64 [[CALL]], align 8			// CHECK1-NEXT: [[TMP17:%.]] = load i64, i64 [[CALL]], align 8
	// CHECK1-NEXT: [[ADD22:%.*]] = add nsw i64 [[TMP17]], 1			// CHECK1-NEXT: [[ADD22:%.*]] = add nsw i64 [[TMP17]], 1
	// CHECK1-NEXT: store i64 [[ADD22]], i64* [[CALL]], align 8			// CHECK1-NEXT: store i64 [[ADD22]], i64* [[CALL]], align 8
	// CHECK1-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true)			// CHECK1-NEXT: call void @__kmpc_target_deinit(i1 true)
	// CHECK1-NEXT: ret void			// CHECK1-NEXT: ret void
	// CHECK1: worker.exit:			// CHECK1: worker.exit:
	// CHECK1-NEXT: ret void			// CHECK1-NEXT: ret void
	//			//
	//			//
	// CHECK1-LABEL: define {{[^@]+}}@_ZN2TTIxcEixEi			// CHECK1-LABEL: define {{[^@]+}}@_ZN2TTIxcEixEi
	// CHECK1-SAME: (%struct.TT* nonnull align 8 dereferenceable(16) [[THIS:%.]], i32 [[I:%.]]) #[[ATTR4:[0-9]+]] comdat align 2 {			// CHECK1-SAME: (%struct.TT* nonnull align 8 dereferenceable(16) [[THIS:%.]], i32 [[I:%.]]) #[[ATTR4:[0-9]+]] comdat align 2 {
	// CHECK1-NEXT: entry:			// CHECK1-NEXT: entry:
	Show All 16 Lines
	// CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8			// CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
	// CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8			// CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
	// CHECK1-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8			// CHECK1-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
	// CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8			// CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
	// CHECK1-NEXT: [[CONV:%.]] = bitcast i64 [[A_ADDR]] to i32*			// CHECK1-NEXT: [[CONV:%.]] = bitcast i64 [[A_ADDR]] to i32*
	// CHECK1-NEXT: [[CONV1:%.]] = bitcast i64 [[AA_ADDR]] to i16*			// CHECK1-NEXT: [[CONV1:%.]] = bitcast i64 [[AA_ADDR]] to i16*
	// CHECK1-NEXT: [[CONV2:%.]] = bitcast i64 [[AAA_ADDR]] to i8*			// CHECK1-NEXT: [[CONV2:%.]] = bitcast i64 [[AAA_ADDR]] to i8*
	// CHECK1-NEXT: [[TMP0:%.]] = load [10 x i32], [10 x i32]** [[B_ADDR]], align 8			// CHECK1-NEXT: [[TMP0:%.]] = load [10 x i32], [10 x i32]** [[B_ADDR]], align 8
	// CHECK1-NEXT: [[TMP1:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 1, i1 true, i1 true)			// CHECK1-NEXT: [[TMP1:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l90_kernel_info, i1 true)
	// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1			// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
	// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]			// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
	// CHECK1: user_code.entry:			// CHECK1: user_code.entry:
	// CHECK1-NEXT: [[TMP2:%.]] = load i32, i32 [[CONV]], align 4			// CHECK1-NEXT: [[TMP2:%.]] = load i32, i32 [[CONV]], align 8
	// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], 1			// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], 1
	// CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4			// CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
	// CHECK1-NEXT: [[TMP3:%.]] = load i16, i16 [[CONV1]], align 2			// CHECK1-NEXT: [[TMP3:%.]] = load i16, i16 [[CONV1]], align 8
	// CHECK1-NEXT: [[CONV3:%.*]] = sext i16 [[TMP3]] to i32			// CHECK1-NEXT: [[CONV3:%.*]] = sext i16 [[TMP3]] to i32
	// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1			// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
	// CHECK1-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16			// CHECK1-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
	// CHECK1-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 2			// CHECK1-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 8
	// CHECK1-NEXT: [[TMP4:%.]] = load i8, i8 [[CONV2]], align 1			// CHECK1-NEXT: [[TMP4:%.]] = load i8, i8 [[CONV2]], align 8
	// CHECK1-NEXT: [[CONV6:%.*]] = sext i8 [[TMP4]] to i32			// CHECK1-NEXT: [[CONV6:%.*]] = sext i8 [[TMP4]] to i32
	// CHECK1-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1			// CHECK1-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1
	// CHECK1-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i8			// CHECK1-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i8
	// CHECK1-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 1			// CHECK1-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 8
	// CHECK1-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i64 0, i64 2			// CHECK1-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i64 0, i64 2
	// CHECK1-NEXT: [[TMP5:%.]] = load i32, i32 [[ARRAYIDX]], align 4			// CHECK1-NEXT: [[TMP5:%.]] = load i32, i32 [[ARRAYIDX]], align 4
	// CHECK1-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP5]], 1			// CHECK1-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP5]], 1
	// CHECK1-NEXT: store i32 [[ADD9]], i32* [[ARRAYIDX]], align 4			// CHECK1-NEXT: store i32 [[ADD9]], i32* [[ARRAYIDX]], align 4
	// CHECK1-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true)			// CHECK1-NEXT: call void @__kmpc_target_deinit(i1 true)
	// CHECK1-NEXT: ret void			// CHECK1-NEXT: ret void
	// CHECK1: worker.exit:			// CHECK1: worker.exit:
	// CHECK1-NEXT: ret void			// CHECK1-NEXT: ret void
	//			//
	//			//
	// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l108			// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l108
	// CHECK1-SAME: (%struct.S1* [[THIS:%.]], i64 [[B:%.]], i64 [[VLA:%.]], i64 [[VLA1:%.]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] {			// CHECK1-SAME: (%struct.S1* [[THIS:%.]], i64 [[B:%.]], i64 [[VLA:%.]], i64 [[VLA1:%.]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] {
	// CHECK1-NEXT: entry:			// CHECK1-NEXT: entry:
	// CHECK1-NEXT: [[THIS_ADDR:%.]] = alloca %struct.S1, align 8			// CHECK1-NEXT: [[THIS_ADDR:%.]] = alloca %struct.S1, align 8
	// CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8			// CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
	// CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8			// CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
	// CHECK1-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8			// CHECK1-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
	// CHECK1-NEXT: [[C_ADDR:%.]] = alloca i16, align 8			// CHECK1-NEXT: [[C_ADDR:%.]] = alloca i16, align 8
	// CHECK1-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8			// CHECK1-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
	// CHECK1-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8			// CHECK1-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
	// CHECK1-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8			// CHECK1-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
	// CHECK1-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8			// CHECK1-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
	// CHECK1-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8			// CHECK1-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8
	// CHECK1-NEXT: [[TMP0:%.]] = load %struct.S1, %struct.S1** [[THIS_ADDR]], align 8			// CHECK1-NEXT: [[TMP0:%.]] = load %struct.S1, %struct.S1** [[THIS_ADDR]], align 8
	// CHECK1-NEXT: [[CONV:%.]] = bitcast i64 [[B_ADDR]] to i32*			// CHECK1-NEXT: [[CONV:%.]] = bitcast i64 [[B_ADDR]] to i32*
	// CHECK1-NEXT: [[TMP1:%.]] = load i64, i64 [[VLA_ADDR]], align 8			// CHECK1-NEXT: [[TMP1:%.]] = load i64, i64 [[VLA_ADDR]], align 8
	// CHECK1-NEXT: [[TMP2:%.]] = load i64, i64 [[VLA_ADDR2]], align 8			// CHECK1-NEXT: [[TMP2:%.]] = load i64, i64 [[VLA_ADDR2]], align 8
	// CHECK1-NEXT: [[TMP3:%.]] = load i16, i16** [[C_ADDR]], align 8			// CHECK1-NEXT: [[TMP3:%.]] = load i16, i16** [[C_ADDR]], align 8
	// CHECK1-NEXT: [[TMP4:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 1, i1 true, i1 true)			// CHECK1-NEXT: [[TMP4:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l108_kernel_info, i1 true)
	// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP4]], -1			// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP4]], -1
	// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]			// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
	// CHECK1: user_code.entry:			// CHECK1: user_code.entry:
	// CHECK1-NEXT: [[TMP5:%.]] = load i32, i32 [[CONV]], align 4			// CHECK1-NEXT: [[TMP5:%.]] = load i32, i32 [[CONV]], align 8
	// CHECK1-NEXT: [[CONV3:%.*]] = sitofp i32 [[TMP5]] to double			// CHECK1-NEXT: [[CONV3:%.*]] = sitofp i32 [[TMP5]] to double
	// CHECK1-NEXT: [[ADD:%.*]] = fadd double [[CONV3]], 1.500000e+00			// CHECK1-NEXT: [[ADD:%.*]] = fadd double [[CONV3]], 1.500000e+00
	// CHECK1-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_S1:%.]], %struct.S1* [[TMP0]], i32 0, i32 0			// CHECK1-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_S1:%.]], %struct.S1* [[TMP0]], i32 0, i32 0
	// CHECK1-NEXT: store double [[ADD]], double* [[A]], align 8			// CHECK1-NEXT: store double [[ADD]], double* [[A]], align 8
	// CHECK1-NEXT: [[A4:%.]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1 [[TMP0]], i32 0, i32 0			// CHECK1-NEXT: [[A4:%.]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1 [[TMP0]], i32 0, i32 0
	// CHECK1-NEXT: [[TMP6:%.]] = load double, double [[A4]], align 8			// CHECK1-NEXT: [[TMP6:%.]] = load double, double [[A4]], align 8
	// CHECK1-NEXT: [[INC:%.*]] = fadd double [[TMP6]], 1.000000e+00			// CHECK1-NEXT: [[INC:%.*]] = fadd double [[TMP6]], 1.000000e+00
	// CHECK1-NEXT: store double [[INC]], double* [[A4]], align 8			// CHECK1-NEXT: store double [[INC]], double* [[A4]], align 8
	// CHECK1-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16			// CHECK1-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16
	// CHECK1-NEXT: [[TMP7:%.*]] = mul nsw i64 1, [[TMP2]]			// CHECK1-NEXT: [[TMP7:%.*]] = mul nsw i64 1, [[TMP2]]
	// CHECK1-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i16, i16 [[TMP3]], i64 [[TMP7]]			// CHECK1-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i16, i16 [[TMP3]], i64 [[TMP7]]
	// CHECK1-NEXT: [[ARRAYIDX6:%.]] = getelementptr inbounds i16, i16 [[ARRAYIDX]], i64 1			// CHECK1-NEXT: [[ARRAYIDX6:%.]] = getelementptr inbounds i16, i16 [[ARRAYIDX]], i64 1
	// CHECK1-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2			// CHECK1-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2
	// CHECK1-NEXT: [[A7:%.]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1 [[TMP0]], i32 0, i32 0			// CHECK1-NEXT: [[A7:%.]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1 [[TMP0]], i32 0, i32 0
	// CHECK1-NEXT: [[TMP8:%.]] = load double, double [[A7]], align 8			// CHECK1-NEXT: [[TMP8:%.]] = load double, double [[A7]], align 8
	// CHECK1-NEXT: [[CONV8:%.*]] = fptosi double [[TMP8]] to i32			// CHECK1-NEXT: [[CONV8:%.*]] = fptosi double [[TMP8]] to i32
	// CHECK1-NEXT: [[A9:%.]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1 [[TMP0]], i32 0, i32 0			// CHECK1-NEXT: [[A9:%.]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1 [[TMP0]], i32 0, i32 0
	// CHECK1-NEXT: [[CALL:%.]] = call i32 @_Z3baziRd(i32 [[CONV8]], double nonnull align 8 dereferenceable(8) [[A9]]) #[[ATTR8]]			// CHECK1-NEXT: [[CALL:%.]] = call i32 @_Z3baziRd(i32 [[CONV8]], double nonnull align 8 dereferenceable(8) [[A9]]) #[[ATTR8]]
	// CHECK1-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true)			// CHECK1-NEXT: call void @__kmpc_target_deinit(i1 true)
	// CHECK1-NEXT: ret void			// CHECK1-NEXT: ret void
	// CHECK1: worker.exit:			// CHECK1: worker.exit:
	// CHECK1-NEXT: ret void			// CHECK1-NEXT: ret void
	//			//
	//			//
	// CHECK1-LABEL: define {{[^@]+}}@_Z3baziRd			// CHECK1-LABEL: define {{[^@]+}}@_Z3baziRd
	// CHECK1-SAME: (i32 [[F1:%.]], double nonnull align 8 dereferenceable(8) [[A:%.*]]) #[[ATTR4]] {			// CHECK1-SAME: (i32 [[F1:%.]], double nonnull align 8 dereferenceable(8) [[A:%.*]]) #[[ATTR4]] {
	// CHECK1-NEXT: entry:			// CHECK1-NEXT: entry:
	Show All 16 Lines
	// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[F_ON_STACK]], align 4			// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[F_ON_STACK]], align 4
	// CHECK1-NEXT: call void @__kmpc_free_shared(i8* [[F]], i64 4)			// CHECK1-NEXT: call void @__kmpc_free_shared(i8* [[F]], i64 4)
	// CHECK1-NEXT: ret i32 [[TMP7]]			// CHECK1-NEXT: ret i32 [[TMP7]]
	//			//
	//			//
	// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16unreachable_callv_l142			// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16unreachable_callv_l142
	// CHECK1-SAME: () #[[ATTR1]] {			// CHECK1-SAME: () #[[ATTR1]] {
	// CHECK1-NEXT: entry:			// CHECK1-NEXT: entry:
	// CHECK1-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 1, i1 true, i1 true)			// CHECK1-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16unreachable_callv_l142_kernel_info, i1 true)
	// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1			// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
	// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]			// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
	// CHECK1: user_code.entry:			// CHECK1: user_code.entry:
	// CHECK1-NEXT: call void @_Z6asserti(i32 0) #[[ATTR9:[0-9]+]]			// CHECK1-NEXT: call void @_Z6asserti(i32 0) #[[ATTR9:[0-9]+]]
	// CHECK1-NEXT: unreachable			// CHECK1-NEXT: unreachable
	// CHECK1: worker.exit:			// CHECK1: worker.exit:
	// CHECK1-NEXT: ret void			// CHECK1-NEXT: ret void
	// CHECK1: 1:			// CHECK1: 1:
	// CHECK1-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true)			// CHECK1-NEXT: call void @__kmpc_target_deinit(i1 true)
	// CHECK1-NEXT: ret void			// CHECK1-NEXT: ret void
	//			//
	//			//
	// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l74			// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l74
	// CHECK1-SAME: (i64 [[A:%.]], i64 [[AA:%.]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {			// CHECK1-SAME: (i64 [[A:%.]], i64 [[AA:%.]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {
	// CHECK1-NEXT: entry:			// CHECK1-NEXT: entry:
	// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8			// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
	// CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8			// CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
	// CHECK1-NEXT: [[B_ADDR:%.]] = alloca [10 x i32], align 8			// CHECK1-NEXT: [[B_ADDR:%.]] = alloca [10 x i32], align 8
	// CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8			// CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
	// CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8			// CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
	// CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8			// CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
	// CHECK1-NEXT: [[CONV:%.]] = bitcast i64 [[A_ADDR]] to i32*			// CHECK1-NEXT: [[CONV:%.]] = bitcast i64 [[A_ADDR]] to i32*
	// CHECK1-NEXT: [[CONV1:%.]] = bitcast i64 [[AA_ADDR]] to i16*			// CHECK1-NEXT: [[CONV1:%.]] = bitcast i64 [[AA_ADDR]] to i16*
	// CHECK1-NEXT: [[TMP0:%.]] = load [10 x i32], [10 x i32]** [[B_ADDR]], align 8			// CHECK1-NEXT: [[TMP0:%.]] = load [10 x i32], [10 x i32]** [[B_ADDR]], align 8
	// CHECK1-NEXT: [[TMP1:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 1, i1 true, i1 true)			// CHECK1-NEXT: [[TMP1:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l74_kernel_info, i1 true)
	// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1			// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
	// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]			// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
	// CHECK1: user_code.entry:			// CHECK1: user_code.entry:
	// CHECK1-NEXT: [[TMP2:%.]] = load i32, i32 [[CONV]], align 4			// CHECK1-NEXT: [[TMP2:%.]] = load i32, i32 [[CONV]], align 8
	// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], 1			// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], 1
	// CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4			// CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
	// CHECK1-NEXT: [[TMP3:%.]] = load i16, i16 [[CONV1]], align 2			// CHECK1-NEXT: [[TMP3:%.]] = load i16, i16 [[CONV1]], align 8
	// CHECK1-NEXT: [[CONV2:%.*]] = sext i16 [[TMP3]] to i32			// CHECK1-NEXT: [[CONV2:%.*]] = sext i16 [[TMP3]] to i32
	// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1			// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
	// CHECK1-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16			// CHECK1-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
	// CHECK1-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2			// CHECK1-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 8
	// CHECK1-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i64 0, i64 2			// CHECK1-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i64 0, i64 2
	// CHECK1-NEXT: [[TMP4:%.]] = load i32, i32 [[ARRAYIDX]], align 4			// CHECK1-NEXT: [[TMP4:%.]] = load i32, i32 [[ARRAYIDX]], align 4
	// CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP4]], 1			// CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP4]], 1
	// CHECK1-NEXT: store i32 [[ADD5]], i32* [[ARRAYIDX]], align 4			// CHECK1-NEXT: store i32 [[ADD5]], i32* [[ARRAYIDX]], align 4
	// CHECK1-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true)			// CHECK1-NEXT: call void @__kmpc_target_deinit(i1 true)
	// CHECK1-NEXT: ret void			// CHECK1-NEXT: ret void
	// CHECK1: worker.exit:			// CHECK1: worker.exit:
	// CHECK1-NEXT: ret void			// CHECK1-NEXT: ret void
	//			//
	//			//
	// CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__1			// CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__1
	// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i32 nonnull align 4 dereferenceable(4) [[F:%.]], double nonnull align 8 dereferenceable(8) [[A:%.*]]) #[[ATTR1]] {			// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i32 nonnull align 4 dereferenceable(4) [[F:%.]], double nonnull align 8 dereferenceable(8) [[A:%.*]]) #[[ATTR1]] {
	// CHECK1-NEXT: entry:			// CHECK1-NEXT: entry:
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	// CHECK2-SAME: (i32* [[PTR1:%.]], i32* nonnull align 4 dereferenceable(4) [[PTR2:%.*]]) #[[ATTR0:[0-9]+]] {			// CHECK2-SAME: (i32* [[PTR1:%.]], i32* nonnull align 4 dereferenceable(4) [[PTR2:%.*]]) #[[ATTR0:[0-9]+]] {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	// CHECK2-NEXT: [[PTR1_ADDR:%.]] = alloca i32, align 4			// CHECK2-NEXT: [[PTR1_ADDR:%.]] = alloca i32, align 4
	// CHECK2-NEXT: [[PTR2_ADDR:%.]] = alloca i32*, align 4			// CHECK2-NEXT: [[PTR2_ADDR:%.]] = alloca i32*, align 4
	// CHECK2-NEXT: [[CAPTURED_VARS_ADDRS:%.]] = alloca [2 x i8], align 4			// CHECK2-NEXT: [[CAPTURED_VARS_ADDRS:%.]] = alloca [2 x i8], align 4
	// CHECK2-NEXT: store i32* [[PTR1]], i32** [[PTR1_ADDR]], align 4			// CHECK2-NEXT: store i32* [[PTR1]], i32** [[PTR1_ADDR]], align 4
	// CHECK2-NEXT: store i32 [[PTR2]], i32* [[PTR2_ADDR]], align 4			// CHECK2-NEXT: store i32 [[PTR2]], i32* [[PTR2_ADDR]], align 4
	// CHECK2-NEXT: [[TMP0:%.]] = load i32, i32** [[PTR2_ADDR]], align 4			// CHECK2-NEXT: [[TMP0:%.]] = load i32, i32** [[PTR2_ADDR]], align 4
	// CHECK2-NEXT: [[TMP1:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1:[0-9]+]], i8 2, i1 false, i1 true)			// CHECK2-NEXT: [[TMP1:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9targetBarPiS__l25_kernel_info, i1 true)
	// CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1			// CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
	// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]			// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
	// CHECK2: user_code.entry:			// CHECK2: user_code.entry:
	// CHECK2-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB2:[0-9]+]])			// CHECK2-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB2:[0-9]+]])
	// CHECK2-NEXT: [[TMP3:%.]] = getelementptr inbounds [2 x i8], [2 x i8] [[CAPTURED_VARS_ADDRS]], i32 0, i32 0			// CHECK2-NEXT: [[TMP3:%.]] = getelementptr inbounds [2 x i8], [2 x i8] [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
	// CHECK2-NEXT: [[TMP4:%.]] = bitcast i32* [[PTR1_ADDR]] to i8*			// CHECK2-NEXT: [[TMP4:%.]] = bitcast i32* [[PTR1_ADDR]] to i8*
	// CHECK2-NEXT: store i8* [[TMP4]], i8** [[TMP3]], align 4			// CHECK2-NEXT: store i8* [[TMP4]], i8** [[TMP3]], align 4
	// CHECK2-NEXT: [[TMP5:%.]] = getelementptr inbounds [2 x i8], [2 x i8] [[CAPTURED_VARS_ADDRS]], i32 0, i32 1			// CHECK2-NEXT: [[TMP5:%.]] = getelementptr inbounds [2 x i8], [2 x i8] [[CAPTURED_VARS_ADDRS]], i32 0, i32 1
	// CHECK2-NEXT: [[TMP6:%.]] = bitcast i32* [[TMP0]] to i8*			// CHECK2-NEXT: [[TMP6:%.]] = bitcast i32* [[TMP0]] to i8*
	// CHECK2-NEXT: store i8* [[TMP6]], i8** [[TMP5]], align 4			// CHECK2-NEXT: store i8* [[TMP6]], i8** [[TMP5]], align 4
	// CHECK2-NEXT: [[TMP7:%.]] = bitcast [2 x i8]* [[CAPTURED_VARS_ADDRS]] to i8**			// CHECK2-NEXT: [[TMP7:%.]] = bitcast [2 x i8]* [[CAPTURED_VARS_ADDRS]] to i8**
	// CHECK2-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32 1, i32 2, i32 -1, i8* bitcast (void (i32, i32, i32, i32)* @__omp_outlined__ to i8), i8 null, i8** [[TMP7]], i32 2)			// CHECK2-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32 1, i32 2, i32 -1, i8* bitcast (void (i32, i32, i32, i32)* @__omp_outlined__ to i8), i8 null, i8** [[TMP7]], i32 2)
	// CHECK2-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 true)			// CHECK2-NEXT: call void @__kmpc_target_deinit(i1 true)
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	// CHECK2: worker.exit:			// CHECK2: worker.exit:
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__			// CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__
	// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i32* nonnull align 4 dereferenceable(4) [[PTR1:%.]], i32* nonnull align 4 dereferenceable(4) [[PTR2:%.*]]) #[[ATTR1:[0-9]+]] {			// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i32* nonnull align 4 dereferenceable(4) [[PTR1:%.]], i32* nonnull align 4 dereferenceable(4) [[PTR2:%.*]]) #[[ATTR1:[0-9]+]] {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	Show All 12 Lines
	// CHECK2-NEXT: [[TMP4:%.]] = load i32, i32** [[TMP0]], align 4			// CHECK2-NEXT: [[TMP4:%.]] = load i32, i32** [[TMP0]], align 4
	// CHECK2-NEXT: store i32 [[TMP3]], i32* [[TMP4]], align 4			// CHECK2-NEXT: store i32 [[TMP3]], i32* [[TMP4]], align 4
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l39			// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l39
	// CHECK2-SAME: () #[[ATTR1]] {			// CHECK2-SAME: () #[[ATTR1]] {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	// CHECK2-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 1, i1 true, i1 true)			// CHECK2-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l39_kernel_info, i1 true)
	// CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1			// CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
	// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]			// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
	// CHECK2: user_code.entry:			// CHECK2: user_code.entry:
	// CHECK2-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true)			// CHECK2-NEXT: call void @__kmpc_target_deinit(i1 true)
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	// CHECK2: worker.exit:			// CHECK2: worker.exit:
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l47			// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l47
	// CHECK2-SAME: (i32 [[AA:%.*]]) #[[ATTR1]] {			// CHECK2-SAME: (i32 [[AA:%.*]]) #[[ATTR1]] {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	// CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4			// CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
	// CHECK2-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4			// CHECK2-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
	// CHECK2-NEXT: [[CONV:%.]] = bitcast i32 [[AA_ADDR]] to i16*			// CHECK2-NEXT: [[CONV:%.]] = bitcast i32 [[AA_ADDR]] to i16*
	// CHECK2-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 1, i1 true, i1 true)			// CHECK2-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l47_kernel_info, i1 true)
	// CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1			// CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
	// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]			// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
	// CHECK2: user_code.entry:			// CHECK2: user_code.entry:
	// CHECK2-NEXT: [[TMP1:%.]] = load i16, i16 [[CONV]], align 2			// CHECK2-NEXT: [[TMP1:%.]] = load i16, i16 [[CONV]], align 4
	// CHECK2-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32			// CHECK2-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32
	// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1			// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1
	// CHECK2-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16			// CHECK2-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
	// CHECK2-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2			// CHECK2-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 4
	// CHECK2-NEXT: [[TMP2:%.]] = load i16, i16 [[CONV]], align 2			// CHECK2-NEXT: [[TMP2:%.]] = load i16, i16 [[CONV]], align 4
	// CHECK2-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32			// CHECK2-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32
	// CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 2			// CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 2
	// CHECK2-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16			// CHECK2-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
	// CHECK2-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2			// CHECK2-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 4
	// CHECK2-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true)			// CHECK2-NEXT: call void @__kmpc_target_deinit(i1 true)
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	// CHECK2: worker.exit:			// CHECK2: worker.exit:
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l53			// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l53
	// CHECK2-SAME: (i32 [[A:%.]], [10 x float] nonnull align 4 dereferenceable(40) [[B:%.]], i32 [[VLA:%.]], float* nonnull align 4 dereferenceable(4) [[BN:%.]], [5 x [10 x double]] nonnull align 8 dereferenceable(400) [[C:%.]], i32 [[VLA1:%.]], i32 [[VLA3:%.]], double nonnull align 8 dereferenceable(8) [[CN:%.]], %struct.TT nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR1]] {			// CHECK2-SAME: (i32 [[A:%.]], [10 x float] nonnull align 4 dereferenceable(40) [[B:%.]], i32 [[VLA:%.]], float* nonnull align 4 dereferenceable(4) [[BN:%.]], [5 x [10 x double]] nonnull align 8 dereferenceable(400) [[C:%.]], i32 [[VLA1:%.]], i32 [[VLA3:%.]], double nonnull align 8 dereferenceable(8) [[CN:%.]], %struct.TT nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR1]] {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	Show All 18 Lines
	// CHECK2-NEXT: [[TMP0:%.]] = load [10 x float], [10 x float]** [[B_ADDR]], align 4			// CHECK2-NEXT: [[TMP0:%.]] = load [10 x float], [10 x float]** [[B_ADDR]], align 4
	// CHECK2-NEXT: [[TMP1:%.]] = load i32, i32 [[VLA_ADDR]], align 4			// CHECK2-NEXT: [[TMP1:%.]] = load i32, i32 [[VLA_ADDR]], align 4
	// CHECK2-NEXT: [[TMP2:%.]] = load float, float** [[BN_ADDR]], align 4			// CHECK2-NEXT: [[TMP2:%.]] = load float, float** [[BN_ADDR]], align 4
	// CHECK2-NEXT: [[TMP3:%.]] = load [5 x [10 x double]], [5 x [10 x double]]** [[C_ADDR]], align 4			// CHECK2-NEXT: [[TMP3:%.]] = load [5 x [10 x double]], [5 x [10 x double]]** [[C_ADDR]], align 4
	// CHECK2-NEXT: [[TMP4:%.]] = load i32, i32 [[VLA_ADDR2]], align 4			// CHECK2-NEXT: [[TMP4:%.]] = load i32, i32 [[VLA_ADDR2]], align 4
	// CHECK2-NEXT: [[TMP5:%.]] = load i32, i32 [[VLA_ADDR4]], align 4			// CHECK2-NEXT: [[TMP5:%.]] = load i32, i32 [[VLA_ADDR4]], align 4
	// CHECK2-NEXT: [[TMP6:%.]] = load double, double** [[CN_ADDR]], align 4			// CHECK2-NEXT: [[TMP6:%.]] = load double, double** [[CN_ADDR]], align 4
	// CHECK2-NEXT: [[TMP7:%.]] = load %struct.TT, %struct.TT** [[D_ADDR]], align 4			// CHECK2-NEXT: [[TMP7:%.]] = load %struct.TT, %struct.TT** [[D_ADDR]], align 4
	// CHECK2-NEXT: [[TMP8:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 1, i1 true, i1 true)			// CHECK2-NEXT: [[TMP8:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l53_kernel_info, i1 true)
	// CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP8]], -1			// CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP8]], -1
	// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]			// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
	// CHECK2: user_code.entry:			// CHECK2: user_code.entry:
	// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[A_ADDR]], align 4			// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[A_ADDR]], align 4
	// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], 1			// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], 1
	// CHECK2-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4			// CHECK2-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
	// CHECK2-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x float], [10 x float] [[TMP0]], i32 0, i32 2			// CHECK2-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x float], [10 x float] [[TMP0]], i32 0, i32 2
	// CHECK2-NEXT: [[TMP10:%.]] = load float, float [[ARRAYIDX]], align 4			// CHECK2-NEXT: [[TMP10:%.]] = load float, float [[ARRAYIDX]], align 4
	Show All 27 Lines
	// CHECK2-NEXT: [[CONV18:%.*]] = sext i8 [[TMP16]] to i32			// CHECK2-NEXT: [[CONV18:%.*]] = sext i8 [[TMP16]] to i32
	// CHECK2-NEXT: [[ADD19:%.*]] = add nsw i32 [[CONV18]], 1			// CHECK2-NEXT: [[ADD19:%.*]] = add nsw i32 [[CONV18]], 1
	// CHECK2-NEXT: [[CONV20:%.*]] = trunc i32 [[ADD19]] to i8			// CHECK2-NEXT: [[CONV20:%.*]] = trunc i32 [[ADD19]] to i8
	// CHECK2-NEXT: store i8 [[CONV20]], i8* [[Y]], align 8			// CHECK2-NEXT: store i8 [[CONV20]], i8* [[Y]], align 8
	// CHECK2-NEXT: [[CALL:%.]] = call nonnull align 8 dereferenceable(8) i64 @_ZN2TTIxcEixEi(%struct.TT* nonnull align 8 dereferenceable(16) [[TMP7]], i32 0) #[[ATTR8:[0-9]+]]			// CHECK2-NEXT: [[CALL:%.]] = call nonnull align 8 dereferenceable(8) i64 @_ZN2TTIxcEixEi(%struct.TT* nonnull align 8 dereferenceable(16) [[TMP7]], i32 0) #[[ATTR8:[0-9]+]]
	// CHECK2-NEXT: [[TMP17:%.]] = load i64, i64 [[CALL]], align 8			// CHECK2-NEXT: [[TMP17:%.]] = load i64, i64 [[CALL]], align 8
	// CHECK2-NEXT: [[ADD21:%.*]] = add nsw i64 [[TMP17]], 1			// CHECK2-NEXT: [[ADD21:%.*]] = add nsw i64 [[TMP17]], 1
	// CHECK2-NEXT: store i64 [[ADD21]], i64* [[CALL]], align 8			// CHECK2-NEXT: store i64 [[ADD21]], i64* [[CALL]], align 8
	// CHECK2-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true)			// CHECK2-NEXT: call void @__kmpc_target_deinit(i1 true)
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	// CHECK2: worker.exit:			// CHECK2: worker.exit:
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@_ZN2TTIxcEixEi			// CHECK2-LABEL: define {{[^@]+}}@_ZN2TTIxcEixEi
	// CHECK2-SAME: (%struct.TT* nonnull align 8 dereferenceable(16) [[THIS:%.]], i32 [[I:%.]]) #[[ATTR4:[0-9]+]] comdat align 2 {			// CHECK2-SAME: (%struct.TT* nonnull align 8 dereferenceable(16) [[THIS:%.]], i32 [[I:%.]]) #[[ATTR4:[0-9]+]] comdat align 2 {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	Show All 15 Lines
	// CHECK2-NEXT: [[B_ADDR:%.]] = alloca [10 x i32], align 4			// CHECK2-NEXT: [[B_ADDR:%.]] = alloca [10 x i32], align 4
	// CHECK2-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4			// CHECK2-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
	// CHECK2-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4			// CHECK2-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
	// CHECK2-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4			// CHECK2-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
	// CHECK2-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4			// CHECK2-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
	// CHECK2-NEXT: [[CONV:%.]] = bitcast i32 [[AA_ADDR]] to i16*			// CHECK2-NEXT: [[CONV:%.]] = bitcast i32 [[AA_ADDR]] to i16*
	// CHECK2-NEXT: [[CONV1:%.]] = bitcast i32 [[AAA_ADDR]] to i8*			// CHECK2-NEXT: [[CONV1:%.]] = bitcast i32 [[AAA_ADDR]] to i8*
	// CHECK2-NEXT: [[TMP0:%.]] = load [10 x i32], [10 x i32]** [[B_ADDR]], align 4			// CHECK2-NEXT: [[TMP0:%.]] = load [10 x i32], [10 x i32]** [[B_ADDR]], align 4
	// CHECK2-NEXT: [[TMP1:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 1, i1 true, i1 true)			// CHECK2-NEXT: [[TMP1:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l90_kernel_info, i1 true)
	// CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1			// CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
	// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]			// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
	// CHECK2: user_code.entry:			// CHECK2: user_code.entry:
	// CHECK2-NEXT: [[TMP2:%.]] = load i32, i32 [[A_ADDR]], align 4			// CHECK2-NEXT: [[TMP2:%.]] = load i32, i32 [[A_ADDR]], align 4
	// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], 1			// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], 1
	// CHECK2-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4			// CHECK2-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
	// CHECK2-NEXT: [[TMP3:%.]] = load i16, i16 [[CONV]], align 2			// CHECK2-NEXT: [[TMP3:%.]] = load i16, i16 [[CONV]], align 4
	// CHECK2-NEXT: [[CONV2:%.*]] = sext i16 [[TMP3]] to i32			// CHECK2-NEXT: [[CONV2:%.*]] = sext i16 [[TMP3]] to i32
	// CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1			// CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
	// CHECK2-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16			// CHECK2-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
	// CHECK2-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2			// CHECK2-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 4
	// CHECK2-NEXT: [[TMP4:%.]] = load i8, i8 [[CONV1]], align 1			// CHECK2-NEXT: [[TMP4:%.]] = load i8, i8 [[CONV1]], align 4
	// CHECK2-NEXT: [[CONV5:%.*]] = sext i8 [[TMP4]] to i32			// CHECK2-NEXT: [[CONV5:%.*]] = sext i8 [[TMP4]] to i32
	// CHECK2-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1			// CHECK2-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1
	// CHECK2-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i8			// CHECK2-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i8
	// CHECK2-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 1			// CHECK2-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 4
	// CHECK2-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i32 0, i32 2			// CHECK2-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i32 0, i32 2
	// CHECK2-NEXT: [[TMP5:%.]] = load i32, i32 [[ARRAYIDX]], align 4			// CHECK2-NEXT: [[TMP5:%.]] = load i32, i32 [[ARRAYIDX]], align 4
	// CHECK2-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP5]], 1			// CHECK2-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP5]], 1
	// CHECK2-NEXT: store i32 [[ADD8]], i32* [[ARRAYIDX]], align 4			// CHECK2-NEXT: store i32 [[ADD8]], i32* [[ARRAYIDX]], align 4
	// CHECK2-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true)			// CHECK2-NEXT: call void @__kmpc_target_deinit(i1 true)
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	// CHECK2: worker.exit:			// CHECK2: worker.exit:
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l108			// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l108
	// CHECK2-SAME: (%struct.S1* [[THIS:%.]], i32 [[B:%.]], i32 [[VLA:%.]], i32 [[VLA1:%.]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] {			// CHECK2-SAME: (%struct.S1* [[THIS:%.]], i32 [[B:%.]], i32 [[VLA:%.]], i32 [[VLA1:%.]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	// CHECK2-NEXT: [[THIS_ADDR:%.]] = alloca %struct.S1, align 4			// CHECK2-NEXT: [[THIS_ADDR:%.]] = alloca %struct.S1, align 4
	// CHECK2-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4			// CHECK2-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
	// CHECK2-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4			// CHECK2-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
	// CHECK2-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4			// CHECK2-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
	// CHECK2-NEXT: [[C_ADDR:%.]] = alloca i16, align 4			// CHECK2-NEXT: [[C_ADDR:%.]] = alloca i16, align 4
	// CHECK2-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4			// CHECK2-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
	// CHECK2-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4			// CHECK2-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
	// CHECK2-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4			// CHECK2-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
	// CHECK2-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4			// CHECK2-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
	// CHECK2-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4			// CHECK2-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4
	// CHECK2-NEXT: [[TMP0:%.]] = load %struct.S1, %struct.S1** [[THIS_ADDR]], align 4			// CHECK2-NEXT: [[TMP0:%.]] = load %struct.S1, %struct.S1** [[THIS_ADDR]], align 4
	// CHECK2-NEXT: [[TMP1:%.]] = load i32, i32 [[VLA_ADDR]], align 4			// CHECK2-NEXT: [[TMP1:%.]] = load i32, i32 [[VLA_ADDR]], align 4
	// CHECK2-NEXT: [[TMP2:%.]] = load i32, i32 [[VLA_ADDR2]], align 4			// CHECK2-NEXT: [[TMP2:%.]] = load i32, i32 [[VLA_ADDR2]], align 4
	// CHECK2-NEXT: [[TMP3:%.]] = load i16, i16** [[C_ADDR]], align 4			// CHECK2-NEXT: [[TMP3:%.]] = load i16, i16** [[C_ADDR]], align 4
	// CHECK2-NEXT: [[TMP4:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 1, i1 true, i1 true)			// CHECK2-NEXT: [[TMP4:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l108_kernel_info, i1 true)
	// CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP4]], -1			// CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP4]], -1
	// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]			// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
	// CHECK2: user_code.entry:			// CHECK2: user_code.entry:
	// CHECK2-NEXT: [[TMP5:%.]] = load i32, i32 [[B_ADDR]], align 4			// CHECK2-NEXT: [[TMP5:%.]] = load i32, i32 [[B_ADDR]], align 4
	// CHECK2-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP5]] to double			// CHECK2-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP5]] to double
	// CHECK2-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00			// CHECK2-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00
	// CHECK2-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_S1:%.]], %struct.S1* [[TMP0]], i32 0, i32 0			// CHECK2-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_S1:%.]], %struct.S1* [[TMP0]], i32 0, i32 0
	// CHECK2-NEXT: store double [[ADD]], double* [[A]], align 8			// CHECK2-NEXT: store double [[ADD]], double* [[A]], align 8
	// CHECK2-NEXT: [[A3:%.]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1 [[TMP0]], i32 0, i32 0			// CHECK2-NEXT: [[A3:%.]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1 [[TMP0]], i32 0, i32 0
	// CHECK2-NEXT: [[TMP6:%.]] = load double, double [[A3]], align 8			// CHECK2-NEXT: [[TMP6:%.]] = load double, double [[A3]], align 8
	// CHECK2-NEXT: [[INC:%.*]] = fadd double [[TMP6]], 1.000000e+00			// CHECK2-NEXT: [[INC:%.*]] = fadd double [[TMP6]], 1.000000e+00
	// CHECK2-NEXT: store double [[INC]], double* [[A3]], align 8			// CHECK2-NEXT: store double [[INC]], double* [[A3]], align 8
	// CHECK2-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16			// CHECK2-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16
	// CHECK2-NEXT: [[TMP7:%.*]] = mul nsw i32 1, [[TMP2]]			// CHECK2-NEXT: [[TMP7:%.*]] = mul nsw i32 1, [[TMP2]]
	// CHECK2-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i16, i16 [[TMP3]], i32 [[TMP7]]			// CHECK2-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i16, i16 [[TMP3]], i32 [[TMP7]]
	// CHECK2-NEXT: [[ARRAYIDX5:%.]] = getelementptr inbounds i16, i16 [[ARRAYIDX]], i32 1			// CHECK2-NEXT: [[ARRAYIDX5:%.]] = getelementptr inbounds i16, i16 [[ARRAYIDX]], i32 1
	// CHECK2-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2			// CHECK2-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2
	// CHECK2-NEXT: [[A6:%.]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1 [[TMP0]], i32 0, i32 0			// CHECK2-NEXT: [[A6:%.]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1 [[TMP0]], i32 0, i32 0
	// CHECK2-NEXT: [[TMP8:%.]] = load double, double [[A6]], align 8			// CHECK2-NEXT: [[TMP8:%.]] = load double, double [[A6]], align 8
	// CHECK2-NEXT: [[CONV7:%.*]] = fptosi double [[TMP8]] to i32			// CHECK2-NEXT: [[CONV7:%.*]] = fptosi double [[TMP8]] to i32
	// CHECK2-NEXT: [[A8:%.]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1 [[TMP0]], i32 0, i32 0			// CHECK2-NEXT: [[A8:%.]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1 [[TMP0]], i32 0, i32 0
	// CHECK2-NEXT: [[CALL:%.]] = call i32 @_Z3baziRd(i32 [[CONV7]], double nonnull align 8 dereferenceable(8) [[A8]]) #[[ATTR8]]			// CHECK2-NEXT: [[CALL:%.]] = call i32 @_Z3baziRd(i32 [[CONV7]], double nonnull align 8 dereferenceable(8) [[A8]]) #[[ATTR8]]
	// CHECK2-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true)			// CHECK2-NEXT: call void @__kmpc_target_deinit(i1 true)
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	// CHECK2: worker.exit:			// CHECK2: worker.exit:
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@_Z3baziRd			// CHECK2-LABEL: define {{[^@]+}}@_Z3baziRd
	// CHECK2-SAME: (i32 [[F1:%.]], double nonnull align 8 dereferenceable(8) [[A:%.*]]) #[[ATTR4]] {			// CHECK2-SAME: (i32 [[F1:%.]], double nonnull align 8 dereferenceable(8) [[A:%.*]]) #[[ATTR4]] {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	Show All 16 Lines
	// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[F_ON_STACK]], align 4			// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[F_ON_STACK]], align 4
	// CHECK2-NEXT: call void @__kmpc_free_shared(i8* [[F]], i32 4)			// CHECK2-NEXT: call void @__kmpc_free_shared(i8* [[F]], i32 4)
	// CHECK2-NEXT: ret i32 [[TMP7]]			// CHECK2-NEXT: ret i32 [[TMP7]]
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16unreachable_callv_l142			// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16unreachable_callv_l142
	// CHECK2-SAME: () #[[ATTR1]] {			// CHECK2-SAME: () #[[ATTR1]] {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	// CHECK2-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 1, i1 true, i1 true)			// CHECK2-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16unreachable_callv_l142_kernel_info, i1 true)
	// CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1			// CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
	// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]			// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
	// CHECK2: user_code.entry:			// CHECK2: user_code.entry:
	// CHECK2-NEXT: call void @_Z6asserti(i32 0) #[[ATTR9:[0-9]+]]			// CHECK2-NEXT: call void @_Z6asserti(i32 0) #[[ATTR9:[0-9]+]]
	// CHECK2-NEXT: unreachable			// CHECK2-NEXT: unreachable
	// CHECK2: worker.exit:			// CHECK2: worker.exit:
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	// CHECK2: 1:			// CHECK2: 1:
	// CHECK2-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true)			// CHECK2-NEXT: call void @__kmpc_target_deinit(i1 true)
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l74			// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l74
	// CHECK2-SAME: (i32 [[A:%.]], i32 [[AA:%.]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {			// CHECK2-SAME: (i32 [[A:%.]], i32 [[AA:%.]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	// CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4			// CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
	// CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4			// CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
	// CHECK2-NEXT: [[B_ADDR:%.]] = alloca [10 x i32], align 4			// CHECK2-NEXT: [[B_ADDR:%.]] = alloca [10 x i32], align 4
	// CHECK2-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4			// CHECK2-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
	// CHECK2-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4			// CHECK2-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
	// CHECK2-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4			// CHECK2-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
	// CHECK2-NEXT: [[CONV:%.]] = bitcast i32 [[AA_ADDR]] to i16*			// CHECK2-NEXT: [[CONV:%.]] = bitcast i32 [[AA_ADDR]] to i16*
	// CHECK2-NEXT: [[TMP0:%.]] = load [10 x i32], [10 x i32]** [[B_ADDR]], align 4			// CHECK2-NEXT: [[TMP0:%.]] = load [10 x i32], [10 x i32]** [[B_ADDR]], align 4
	// CHECK2-NEXT: [[TMP1:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 1, i1 true, i1 true)			// CHECK2-NEXT: [[TMP1:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l74_kernel_info, i1 true)
	// CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1			// CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
	// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]			// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
	// CHECK2: user_code.entry:			// CHECK2: user_code.entry:
	// CHECK2-NEXT: [[TMP2:%.]] = load i32, i32 [[A_ADDR]], align 4			// CHECK2-NEXT: [[TMP2:%.]] = load i32, i32 [[A_ADDR]], align 4
	// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], 1			// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], 1
	// CHECK2-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4			// CHECK2-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
	// CHECK2-NEXT: [[TMP3:%.]] = load i16, i16 [[CONV]], align 2			// CHECK2-NEXT: [[TMP3:%.]] = load i16, i16 [[CONV]], align 4
	// CHECK2-NEXT: [[CONV1:%.*]] = sext i16 [[TMP3]] to i32			// CHECK2-NEXT: [[CONV1:%.*]] = sext i16 [[TMP3]] to i32
	// CHECK2-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1			// CHECK2-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1
	// CHECK2-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16			// CHECK2-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
	// CHECK2-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2			// CHECK2-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 4
	// CHECK2-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i32 0, i32 2			// CHECK2-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i32 0, i32 2
	// CHECK2-NEXT: [[TMP4:%.]] = load i32, i32 [[ARRAYIDX]], align 4			// CHECK2-NEXT: [[TMP4:%.]] = load i32, i32 [[ARRAYIDX]], align 4
	// CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP4]], 1			// CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP4]], 1
	// CHECK2-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4			// CHECK2-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4
	// CHECK2-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true)			// CHECK2-NEXT: call void @__kmpc_target_deinit(i1 true)
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	// CHECK2: worker.exit:			// CHECK2: worker.exit:
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__1			// CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__1
	// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i32 nonnull align 4 dereferenceable(4) [[F:%.]], double nonnull align 8 dereferenceable(8) [[A:%.*]]) #[[ATTR1]] {			// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i32 nonnull align 4 dereferenceable(4) [[F:%.]], double nonnull align 8 dereferenceable(8) [[A:%.*]]) #[[ATTR1]] {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	▲ Show 20 Lines • Show All 43 Lines • ▼ Show 20 Lines
	// CHECK3-SAME: (i32* [[PTR1:%.]], i32* nonnull align 4 dereferenceable(4) [[PTR2:%.*]]) #[[ATTR0:[0-9]+]] {			// CHECK3-SAME: (i32* [[PTR1:%.]], i32* nonnull align 4 dereferenceable(4) [[PTR2:%.*]]) #[[ATTR0:[0-9]+]] {
	// CHECK3-NEXT: entry:			// CHECK3-NEXT: entry:
	// CHECK3-NEXT: [[PTR1_ADDR:%.]] = alloca i32, align 4			// CHECK3-NEXT: [[PTR1_ADDR:%.]] = alloca i32, align 4
	// CHECK3-NEXT: [[PTR2_ADDR:%.]] = alloca i32*, align 4			// CHECK3-NEXT: [[PTR2_ADDR:%.]] = alloca i32*, align 4
	// CHECK3-NEXT: [[CAPTURED_VARS_ADDRS:%.]] = alloca [2 x i8], align 4			// CHECK3-NEXT: [[CAPTURED_VARS_ADDRS:%.]] = alloca [2 x i8], align 4
	// CHECK3-NEXT: store i32* [[PTR1]], i32** [[PTR1_ADDR]], align 4			// CHECK3-NEXT: store i32* [[PTR1]], i32** [[PTR1_ADDR]], align 4
	// CHECK3-NEXT: store i32 [[PTR2]], i32* [[PTR2_ADDR]], align 4			// CHECK3-NEXT: store i32 [[PTR2]], i32* [[PTR2_ADDR]], align 4
	// CHECK3-NEXT: [[TMP0:%.]] = load i32, i32** [[PTR2_ADDR]], align 4			// CHECK3-NEXT: [[TMP0:%.]] = load i32, i32** [[PTR2_ADDR]], align 4
	// CHECK3-NEXT: [[TMP1:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1:[0-9]+]], i8 2, i1 false, i1 true)			// CHECK3-NEXT: [[TMP1:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9targetBarPiS__l25_kernel_info, i1 true)
	// CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1			// CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
	// CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]			// CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
	// CHECK3: user_code.entry:			// CHECK3: user_code.entry:
	// CHECK3-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB2:[0-9]+]])			// CHECK3-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB2:[0-9]+]])
	// CHECK3-NEXT: [[TMP3:%.]] = getelementptr inbounds [2 x i8], [2 x i8] [[CAPTURED_VARS_ADDRS]], i32 0, i32 0			// CHECK3-NEXT: [[TMP3:%.]] = getelementptr inbounds [2 x i8], [2 x i8] [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
	// CHECK3-NEXT: [[TMP4:%.]] = bitcast i32* [[PTR1_ADDR]] to i8*			// CHECK3-NEXT: [[TMP4:%.]] = bitcast i32* [[PTR1_ADDR]] to i8*
	// CHECK3-NEXT: store i8* [[TMP4]], i8** [[TMP3]], align 4			// CHECK3-NEXT: store i8* [[TMP4]], i8** [[TMP3]], align 4
	// CHECK3-NEXT: [[TMP5:%.]] = getelementptr inbounds [2 x i8], [2 x i8] [[CAPTURED_VARS_ADDRS]], i32 0, i32 1			// CHECK3-NEXT: [[TMP5:%.]] = getelementptr inbounds [2 x i8], [2 x i8] [[CAPTURED_VARS_ADDRS]], i32 0, i32 1
	// CHECK3-NEXT: [[TMP6:%.]] = bitcast i32* [[TMP0]] to i8*			// CHECK3-NEXT: [[TMP6:%.]] = bitcast i32* [[TMP0]] to i8*
	// CHECK3-NEXT: store i8* [[TMP6]], i8** [[TMP5]], align 4			// CHECK3-NEXT: store i8* [[TMP6]], i8** [[TMP5]], align 4
	// CHECK3-NEXT: [[TMP7:%.]] = bitcast [2 x i8]* [[CAPTURED_VARS_ADDRS]] to i8**			// CHECK3-NEXT: [[TMP7:%.]] = bitcast [2 x i8]* [[CAPTURED_VARS_ADDRS]] to i8**
	// CHECK3-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32 1, i32 2, i32 -1, i8* bitcast (void (i32, i32, i32, i32)* @__omp_outlined__ to i8), i8 null, i8** [[TMP7]], i32 2)			// CHECK3-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32 1, i32 2, i32 -1, i8* bitcast (void (i32, i32, i32, i32)* @__omp_outlined__ to i8), i8 null, i8** [[TMP7]], i32 2)
	// CHECK3-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 true)			// CHECK3-NEXT: call void @__kmpc_target_deinit(i1 true)
	// CHECK3-NEXT: ret void			// CHECK3-NEXT: ret void
	// CHECK3: worker.exit:			// CHECK3: worker.exit:
	// CHECK3-NEXT: ret void			// CHECK3-NEXT: ret void
	//			//
	//			//
	// CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__			// CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__
	// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i32* nonnull align 4 dereferenceable(4) [[PTR1:%.]], i32* nonnull align 4 dereferenceable(4) [[PTR2:%.*]]) #[[ATTR1:[0-9]+]] {			// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i32* nonnull align 4 dereferenceable(4) [[PTR1:%.]], i32* nonnull align 4 dereferenceable(4) [[PTR2:%.*]]) #[[ATTR1:[0-9]+]] {
	// CHECK3-NEXT: entry:			// CHECK3-NEXT: entry:
	Show All 12 Lines
	// CHECK3-NEXT: [[TMP4:%.]] = load i32, i32** [[TMP0]], align 4			// CHECK3-NEXT: [[TMP4:%.]] = load i32, i32** [[TMP0]], align 4
	// CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP4]], align 4			// CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP4]], align 4
	// CHECK3-NEXT: ret void			// CHECK3-NEXT: ret void
	//			//
	//			//
	// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l39			// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l39
	// CHECK3-SAME: () #[[ATTR1]] {			// CHECK3-SAME: () #[[ATTR1]] {
	// CHECK3-NEXT: entry:			// CHECK3-NEXT: entry:
	// CHECK3-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 1, i1 true, i1 true)			// CHECK3-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l39_kernel_info, i1 true)
	// CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1			// CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
	// CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]			// CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
	// CHECK3: user_code.entry:			// CHECK3: user_code.entry:
	// CHECK3-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true)			// CHECK3-NEXT: call void @__kmpc_target_deinit(i1 true)
	// CHECK3-NEXT: ret void			// CHECK3-NEXT: ret void
	// CHECK3: worker.exit:			// CHECK3: worker.exit:
	// CHECK3-NEXT: ret void			// CHECK3-NEXT: ret void
	//			//
	//			//
	// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l47			// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l47
	// CHECK3-SAME: (i32 [[AA:%.*]]) #[[ATTR1]] {			// CHECK3-SAME: (i32 [[AA:%.*]]) #[[ATTR1]] {
	// CHECK3-NEXT: entry:			// CHECK3-NEXT: entry:
	// CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4			// CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
	// CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4			// CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
	// CHECK3-NEXT: [[CONV:%.]] = bitcast i32 [[AA_ADDR]] to i16*			// CHECK3-NEXT: [[CONV:%.]] = bitcast i32 [[AA_ADDR]] to i16*
	// CHECK3-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 1, i1 true, i1 true)			// CHECK3-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l47_kernel_info, i1 true)
	// CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1			// CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
	// CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]			// CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
	// CHECK3: user_code.entry:			// CHECK3: user_code.entry:
	// CHECK3-NEXT: [[TMP1:%.]] = load i16, i16 [[CONV]], align 2			// CHECK3-NEXT: [[TMP1:%.]] = load i16, i16 [[CONV]], align 4
	// CHECK3-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32			// CHECK3-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32
	// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1			// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1
	// CHECK3-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16			// CHECK3-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
	// CHECK3-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2			// CHECK3-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 4
	// CHECK3-NEXT: [[TMP2:%.]] = load i16, i16 [[CONV]], align 2			// CHECK3-NEXT: [[TMP2:%.]] = load i16, i16 [[CONV]], align 4
	// CHECK3-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32			// CHECK3-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32
	// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 2			// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 2
	// CHECK3-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16			// CHECK3-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
	// CHECK3-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2			// CHECK3-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 4
	// CHECK3-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true)			// CHECK3-NEXT: call void @__kmpc_target_deinit(i1 true)
	// CHECK3-NEXT: ret void			// CHECK3-NEXT: ret void
	// CHECK3: worker.exit:			// CHECK3: worker.exit:
	// CHECK3-NEXT: ret void			// CHECK3-NEXT: ret void
	//			//
	//			//
	// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l53			// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l53
	// CHECK3-SAME: (i32 [[A:%.]], [10 x float] nonnull align 4 dereferenceable(40) [[B:%.]], i32 [[VLA:%.]], float* nonnull align 4 dereferenceable(4) [[BN:%.]], [5 x [10 x double]] nonnull align 8 dereferenceable(400) [[C:%.]], i32 [[VLA1:%.]], i32 [[VLA3:%.]], double nonnull align 8 dereferenceable(8) [[CN:%.]], %struct.TT nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR1]] {			// CHECK3-SAME: (i32 [[A:%.]], [10 x float] nonnull align 4 dereferenceable(40) [[B:%.]], i32 [[VLA:%.]], float* nonnull align 4 dereferenceable(4) [[BN:%.]], [5 x [10 x double]] nonnull align 8 dereferenceable(400) [[C:%.]], i32 [[VLA1:%.]], i32 [[VLA3:%.]], double nonnull align 8 dereferenceable(8) [[CN:%.]], %struct.TT nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR1]] {
	// CHECK3-NEXT: entry:			// CHECK3-NEXT: entry:
	Show All 18 Lines
	// CHECK3-NEXT: [[TMP0:%.]] = load [10 x float], [10 x float]** [[B_ADDR]], align 4			// CHECK3-NEXT: [[TMP0:%.]] = load [10 x float], [10 x float]** [[B_ADDR]], align 4
	// CHECK3-NEXT: [[TMP1:%.]] = load i32, i32 [[VLA_ADDR]], align 4			// CHECK3-NEXT: [[TMP1:%.]] = load i32, i32 [[VLA_ADDR]], align 4
	// CHECK3-NEXT: [[TMP2:%.]] = load float, float** [[BN_ADDR]], align 4			// CHECK3-NEXT: [[TMP2:%.]] = load float, float** [[BN_ADDR]], align 4
	// CHECK3-NEXT: [[TMP3:%.]] = load [5 x [10 x double]], [5 x [10 x double]]** [[C_ADDR]], align 4			// CHECK3-NEXT: [[TMP3:%.]] = load [5 x [10 x double]], [5 x [10 x double]]** [[C_ADDR]], align 4
	// CHECK3-NEXT: [[TMP4:%.]] = load i32, i32 [[VLA_ADDR2]], align 4			// CHECK3-NEXT: [[TMP4:%.]] = load i32, i32 [[VLA_ADDR2]], align 4
	// CHECK3-NEXT: [[TMP5:%.]] = load i32, i32 [[VLA_ADDR4]], align 4			// CHECK3-NEXT: [[TMP5:%.]] = load i32, i32 [[VLA_ADDR4]], align 4
	// CHECK3-NEXT: [[TMP6:%.]] = load double, double** [[CN_ADDR]], align 4			// CHECK3-NEXT: [[TMP6:%.]] = load double, double** [[CN_ADDR]], align 4
	// CHECK3-NEXT: [[TMP7:%.]] = load %struct.TT, %struct.TT** [[D_ADDR]], align 4			// CHECK3-NEXT: [[TMP7:%.]] = load %struct.TT, %struct.TT** [[D_ADDR]], align 4
	// CHECK3-NEXT: [[TMP8:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 1, i1 true, i1 true)			// CHECK3-NEXT: [[TMP8:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l53_kernel_info, i1 true)
	// CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP8]], -1			// CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP8]], -1
	// CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]			// CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
	// CHECK3: user_code.entry:			// CHECK3: user_code.entry:
	// CHECK3-NEXT: [[TMP9:%.]] = load i32, i32 [[A_ADDR]], align 4			// CHECK3-NEXT: [[TMP9:%.]] = load i32, i32 [[A_ADDR]], align 4
	// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], 1			// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], 1
	// CHECK3-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4			// CHECK3-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
	// CHECK3-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x float], [10 x float] [[TMP0]], i32 0, i32 2			// CHECK3-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x float], [10 x float] [[TMP0]], i32 0, i32 2
	// CHECK3-NEXT: [[TMP10:%.]] = load float, float [[ARRAYIDX]], align 4			// CHECK3-NEXT: [[TMP10:%.]] = load float, float [[ARRAYIDX]], align 4
	Show All 27 Lines
	// CHECK3-NEXT: [[CONV18:%.*]] = sext i8 [[TMP16]] to i32			// CHECK3-NEXT: [[CONV18:%.*]] = sext i8 [[TMP16]] to i32
	// CHECK3-NEXT: [[ADD19:%.*]] = add nsw i32 [[CONV18]], 1			// CHECK3-NEXT: [[ADD19:%.*]] = add nsw i32 [[CONV18]], 1
	// CHECK3-NEXT: [[CONV20:%.*]] = trunc i32 [[ADD19]] to i8			// CHECK3-NEXT: [[CONV20:%.*]] = trunc i32 [[ADD19]] to i8
	// CHECK3-NEXT: store i8 [[CONV20]], i8* [[Y]], align 8			// CHECK3-NEXT: store i8 [[CONV20]], i8* [[Y]], align 8
	// CHECK3-NEXT: [[CALL:%.]] = call nonnull align 8 dereferenceable(8) i64 @_ZN2TTIxcEixEi(%struct.TT* nonnull align 8 dereferenceable(16) [[TMP7]], i32 0) #[[ATTR8:[0-9]+]]			// CHECK3-NEXT: [[CALL:%.]] = call nonnull align 8 dereferenceable(8) i64 @_ZN2TTIxcEixEi(%struct.TT* nonnull align 8 dereferenceable(16) [[TMP7]], i32 0) #[[ATTR8:[0-9]+]]
	// CHECK3-NEXT: [[TMP17:%.]] = load i64, i64 [[CALL]], align 8			// CHECK3-NEXT: [[TMP17:%.]] = load i64, i64 [[CALL]], align 8
	// CHECK3-NEXT: [[ADD21:%.*]] = add nsw i64 [[TMP17]], 1			// CHECK3-NEXT: [[ADD21:%.*]] = add nsw i64 [[TMP17]], 1
	// CHECK3-NEXT: store i64 [[ADD21]], i64* [[CALL]], align 8			// CHECK3-NEXT: store i64 [[ADD21]], i64* [[CALL]], align 8
	// CHECK3-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true)			// CHECK3-NEXT: call void @__kmpc_target_deinit(i1 true)
	// CHECK3-NEXT: ret void			// CHECK3-NEXT: ret void
	// CHECK3: worker.exit:			// CHECK3: worker.exit:
	// CHECK3-NEXT: ret void			// CHECK3-NEXT: ret void
	//			//
	//			//
	// CHECK3-LABEL: define {{[^@]+}}@_ZN2TTIxcEixEi			// CHECK3-LABEL: define {{[^@]+}}@_ZN2TTIxcEixEi
	// CHECK3-SAME: (%struct.TT* nonnull align 8 dereferenceable(16) [[THIS:%.]], i32 [[I:%.]]) #[[ATTR4:[0-9]+]] comdat align 2 {			// CHECK3-SAME: (%struct.TT* nonnull align 8 dereferenceable(16) [[THIS:%.]], i32 [[I:%.]]) #[[ATTR4:[0-9]+]] comdat align 2 {
	// CHECK3-NEXT: entry:			// CHECK3-NEXT: entry:
	Show All 15 Lines
	// CHECK3-NEXT: [[B_ADDR:%.]] = alloca [10 x i32], align 4			// CHECK3-NEXT: [[B_ADDR:%.]] = alloca [10 x i32], align 4
	// CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4			// CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
	// CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4			// CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
	// CHECK3-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4			// CHECK3-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
	// CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4			// CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
	// CHECK3-NEXT: [[CONV:%.]] = bitcast i32 [[AA_ADDR]] to i16*			// CHECK3-NEXT: [[CONV:%.]] = bitcast i32 [[AA_ADDR]] to i16*
	// CHECK3-NEXT: [[CONV1:%.]] = bitcast i32 [[AAA_ADDR]] to i8*			// CHECK3-NEXT: [[CONV1:%.]] = bitcast i32 [[AAA_ADDR]] to i8*
	// CHECK3-NEXT: [[TMP0:%.]] = load [10 x i32], [10 x i32]** [[B_ADDR]], align 4			// CHECK3-NEXT: [[TMP0:%.]] = load [10 x i32], [10 x i32]** [[B_ADDR]], align 4
	// CHECK3-NEXT: [[TMP1:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 1, i1 true, i1 true)			// CHECK3-NEXT: [[TMP1:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l90_kernel_info, i1 true)
	// CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1			// CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
	// CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]			// CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
	// CHECK3: user_code.entry:			// CHECK3: user_code.entry:
	// CHECK3-NEXT: [[TMP2:%.]] = load i32, i32 [[A_ADDR]], align 4			// CHECK3-NEXT: [[TMP2:%.]] = load i32, i32 [[A_ADDR]], align 4
	// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], 1			// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], 1
	// CHECK3-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4			// CHECK3-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
	// CHECK3-NEXT: [[TMP3:%.]] = load i16, i16 [[CONV]], align 2			// CHECK3-NEXT: [[TMP3:%.]] = load i16, i16 [[CONV]], align 4
	// CHECK3-NEXT: [[CONV2:%.*]] = sext i16 [[TMP3]] to i32			// CHECK3-NEXT: [[CONV2:%.*]] = sext i16 [[TMP3]] to i32
	// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1			// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
	// CHECK3-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16			// CHECK3-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
	// CHECK3-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2			// CHECK3-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 4
	// CHECK3-NEXT: [[TMP4:%.]] = load i8, i8 [[CONV1]], align 1			// CHECK3-NEXT: [[TMP4:%.]] = load i8, i8 [[CONV1]], align 4
	// CHECK3-NEXT: [[CONV5:%.*]] = sext i8 [[TMP4]] to i32			// CHECK3-NEXT: [[CONV5:%.*]] = sext i8 [[TMP4]] to i32
	// CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1			// CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1
	// CHECK3-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i8			// CHECK3-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i8
	// CHECK3-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 1			// CHECK3-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 4
	// CHECK3-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i32 0, i32 2			// CHECK3-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i32 0, i32 2
	// CHECK3-NEXT: [[TMP5:%.]] = load i32, i32 [[ARRAYIDX]], align 4			// CHECK3-NEXT: [[TMP5:%.]] = load i32, i32 [[ARRAYIDX]], align 4
	// CHECK3-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP5]], 1			// CHECK3-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP5]], 1
	// CHECK3-NEXT: store i32 [[ADD8]], i32* [[ARRAYIDX]], align 4			// CHECK3-NEXT: store i32 [[ADD8]], i32* [[ARRAYIDX]], align 4
	// CHECK3-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true)			// CHECK3-NEXT: call void @__kmpc_target_deinit(i1 true)
	// CHECK3-NEXT: ret void			// CHECK3-NEXT: ret void
	// CHECK3: worker.exit:			// CHECK3: worker.exit:
	// CHECK3-NEXT: ret void			// CHECK3-NEXT: ret void
	//			//
	//			//
	// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l108			// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l108
	// CHECK3-SAME: (%struct.S1* [[THIS:%.]], i32 [[B:%.]], i32 [[VLA:%.]], i32 [[VLA1:%.]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] {			// CHECK3-SAME: (%struct.S1* [[THIS:%.]], i32 [[B:%.]], i32 [[VLA:%.]], i32 [[VLA1:%.]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] {
	// CHECK3-NEXT: entry:			// CHECK3-NEXT: entry:
	// CHECK3-NEXT: [[THIS_ADDR:%.]] = alloca %struct.S1, align 4			// CHECK3-NEXT: [[THIS_ADDR:%.]] = alloca %struct.S1, align 4
	// CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4			// CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
	// CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4			// CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
	// CHECK3-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4			// CHECK3-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
	// CHECK3-NEXT: [[C_ADDR:%.]] = alloca i16, align 4			// CHECK3-NEXT: [[C_ADDR:%.]] = alloca i16, align 4
	// CHECK3-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4			// CHECK3-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
	// CHECK3-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4			// CHECK3-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
	// CHECK3-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4			// CHECK3-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
	// CHECK3-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4			// CHECK3-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
	// CHECK3-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4			// CHECK3-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4
	// CHECK3-NEXT: [[TMP0:%.]] = load %struct.S1, %struct.S1** [[THIS_ADDR]], align 4			// CHECK3-NEXT: [[TMP0:%.]] = load %struct.S1, %struct.S1** [[THIS_ADDR]], align 4
	// CHECK3-NEXT: [[TMP1:%.]] = load i32, i32 [[VLA_ADDR]], align 4			// CHECK3-NEXT: [[TMP1:%.]] = load i32, i32 [[VLA_ADDR]], align 4
	// CHECK3-NEXT: [[TMP2:%.]] = load i32, i32 [[VLA_ADDR2]], align 4			// CHECK3-NEXT: [[TMP2:%.]] = load i32, i32 [[VLA_ADDR2]], align 4
	// CHECK3-NEXT: [[TMP3:%.]] = load i16, i16** [[C_ADDR]], align 4			// CHECK3-NEXT: [[TMP3:%.]] = load i16, i16** [[C_ADDR]], align 4
	// CHECK3-NEXT: [[TMP4:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 1, i1 true, i1 true)			// CHECK3-NEXT: [[TMP4:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l108_kernel_info, i1 true)
	// CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP4]], -1			// CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP4]], -1
	// CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]			// CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
	// CHECK3: user_code.entry:			// CHECK3: user_code.entry:
	// CHECK3-NEXT: [[TMP5:%.]] = load i32, i32 [[B_ADDR]], align 4			// CHECK3-NEXT: [[TMP5:%.]] = load i32, i32 [[B_ADDR]], align 4
	// CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP5]] to double			// CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP5]] to double
	// CHECK3-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00			// CHECK3-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00
	// CHECK3-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_S1:%.]], %struct.S1* [[TMP0]], i32 0, i32 0			// CHECK3-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_S1:%.]], %struct.S1* [[TMP0]], i32 0, i32 0
	// CHECK3-NEXT: store double [[ADD]], double* [[A]], align 8			// CHECK3-NEXT: store double [[ADD]], double* [[A]], align 8
	// CHECK3-NEXT: [[A3:%.]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1 [[TMP0]], i32 0, i32 0			// CHECK3-NEXT: [[A3:%.]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1 [[TMP0]], i32 0, i32 0
	// CHECK3-NEXT: [[TMP6:%.]] = load double, double [[A3]], align 8			// CHECK3-NEXT: [[TMP6:%.]] = load double, double [[A3]], align 8
	// CHECK3-NEXT: [[INC:%.*]] = fadd double [[TMP6]], 1.000000e+00			// CHECK3-NEXT: [[INC:%.*]] = fadd double [[TMP6]], 1.000000e+00
	// CHECK3-NEXT: store double [[INC]], double* [[A3]], align 8			// CHECK3-NEXT: store double [[INC]], double* [[A3]], align 8
	// CHECK3-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16			// CHECK3-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16
	// CHECK3-NEXT: [[TMP7:%.*]] = mul nsw i32 1, [[TMP2]]			// CHECK3-NEXT: [[TMP7:%.*]] = mul nsw i32 1, [[TMP2]]
	// CHECK3-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i16, i16 [[TMP3]], i32 [[TMP7]]			// CHECK3-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i16, i16 [[TMP3]], i32 [[TMP7]]
	// CHECK3-NEXT: [[ARRAYIDX5:%.]] = getelementptr inbounds i16, i16 [[ARRAYIDX]], i32 1			// CHECK3-NEXT: [[ARRAYIDX5:%.]] = getelementptr inbounds i16, i16 [[ARRAYIDX]], i32 1
	// CHECK3-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2			// CHECK3-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2
	// CHECK3-NEXT: [[A6:%.]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1 [[TMP0]], i32 0, i32 0			// CHECK3-NEXT: [[A6:%.]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1 [[TMP0]], i32 0, i32 0
	// CHECK3-NEXT: [[TMP8:%.]] = load double, double [[A6]], align 8			// CHECK3-NEXT: [[TMP8:%.]] = load double, double [[A6]], align 8
	// CHECK3-NEXT: [[CONV7:%.*]] = fptosi double [[TMP8]] to i32			// CHECK3-NEXT: [[CONV7:%.*]] = fptosi double [[TMP8]] to i32
	// CHECK3-NEXT: [[A8:%.]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1 [[TMP0]], i32 0, i32 0			// CHECK3-NEXT: [[A8:%.]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1 [[TMP0]], i32 0, i32 0
	// CHECK3-NEXT: [[CALL:%.]] = call i32 @_Z3baziRd(i32 [[CONV7]], double nonnull align 8 dereferenceable(8) [[A8]]) #[[ATTR8]]			// CHECK3-NEXT: [[CALL:%.]] = call i32 @_Z3baziRd(i32 [[CONV7]], double nonnull align 8 dereferenceable(8) [[A8]]) #[[ATTR8]]
	// CHECK3-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true)			// CHECK3-NEXT: call void @__kmpc_target_deinit(i1 true)
	// CHECK3-NEXT: ret void			// CHECK3-NEXT: ret void
	// CHECK3: worker.exit:			// CHECK3: worker.exit:
	// CHECK3-NEXT: ret void			// CHECK3-NEXT: ret void
	//			//
	//			//
	// CHECK3-LABEL: define {{[^@]+}}@_Z3baziRd			// CHECK3-LABEL: define {{[^@]+}}@_Z3baziRd
	// CHECK3-SAME: (i32 [[F1:%.]], double nonnull align 8 dereferenceable(8) [[A:%.*]]) #[[ATTR4]] {			// CHECK3-SAME: (i32 [[F1:%.]], double nonnull align 8 dereferenceable(8) [[A:%.*]]) #[[ATTR4]] {
	// CHECK3-NEXT: entry:			// CHECK3-NEXT: entry:
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	// CHECK3-NEXT: [[TMP7:%.]] = load i32, i32 [[F_ON_STACK]], align 4			// CHECK3-NEXT: [[TMP7:%.]] = load i32, i32 [[F_ON_STACK]], align 4
	// CHECK3-NEXT: call void @__kmpc_free_shared(i8* [[F]], i32 4)			// CHECK3-NEXT: call void @__kmpc_free_shared(i8* [[F]], i32 4)
	// CHECK3-NEXT: ret i32 [[TMP7]]			// CHECK3-NEXT: ret i32 [[TMP7]]
	//			//
	//			//
	// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16unreachable_callv_l142			// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16unreachable_callv_l142
	// CHECK3-SAME: () #[[ATTR1]] {			// CHECK3-SAME: () #[[ATTR1]] {
	// CHECK3-NEXT: entry:			// CHECK3-NEXT: entry:
	// CHECK3-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 1, i1 true, i1 true)			// CHECK3-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16unreachable_callv_l142_kernel_info, i1 true)
	// CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1			// CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
	// CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]			// CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
	// CHECK3: user_code.entry:			// CHECK3: user_code.entry:
	// CHECK3-NEXT: call void @_Z6asserti(i32 0) #[[ATTR9:[0-9]+]]			// CHECK3-NEXT: call void @_Z6asserti(i32 0) #[[ATTR9:[0-9]+]]
	// CHECK3-NEXT: unreachable			// CHECK3-NEXT: unreachable
	// CHECK3: worker.exit:			// CHECK3: worker.exit:
	// CHECK3-NEXT: ret void			// CHECK3-NEXT: ret void
	// CHECK3: 1:			// CHECK3: 1:
	// CHECK3-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true)			// CHECK3-NEXT: call void @__kmpc_target_deinit(i1 true)
	// CHECK3-NEXT: ret void			// CHECK3-NEXT: ret void
	//			//
	//			//
	// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l74			// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l74
	// CHECK3-SAME: (i32 [[A:%.]], i32 [[AA:%.]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {			// CHECK3-SAME: (i32 [[A:%.]], i32 [[AA:%.]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {
	// CHECK3-NEXT: entry:			// CHECK3-NEXT: entry:
	// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4			// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
	// CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4			// CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
	// CHECK3-NEXT: [[B_ADDR:%.]] = alloca [10 x i32], align 4			// CHECK3-NEXT: [[B_ADDR:%.]] = alloca [10 x i32], align 4
	// CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4			// CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
	// CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4			// CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
	// CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4			// CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
	// CHECK3-NEXT: [[CONV:%.]] = bitcast i32 [[AA_ADDR]] to i16*			// CHECK3-NEXT: [[CONV:%.]] = bitcast i32 [[AA_ADDR]] to i16*
	// CHECK3-NEXT: [[TMP0:%.]] = load [10 x i32], [10 x i32]** [[B_ADDR]], align 4			// CHECK3-NEXT: [[TMP0:%.]] = load [10 x i32], [10 x i32]** [[B_ADDR]], align 4
	// CHECK3-NEXT: [[TMP1:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 1, i1 true, i1 true)			// CHECK3-NEXT: [[TMP1:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l74_kernel_info, i1 true)
	// CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1			// CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
	// CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]			// CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
	// CHECK3: user_code.entry:			// CHECK3: user_code.entry:
	// CHECK3-NEXT: [[TMP2:%.]] = load i32, i32 [[A_ADDR]], align 4			// CHECK3-NEXT: [[TMP2:%.]] = load i32, i32 [[A_ADDR]], align 4
	// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], 1			// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], 1
	// CHECK3-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4			// CHECK3-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
	// CHECK3-NEXT: [[TMP3:%.]] = load i16, i16 [[CONV]], align 2			// CHECK3-NEXT: [[TMP3:%.]] = load i16, i16 [[CONV]], align 4
	// CHECK3-NEXT: [[CONV1:%.*]] = sext i16 [[TMP3]] to i32			// CHECK3-NEXT: [[CONV1:%.*]] = sext i16 [[TMP3]] to i32
	// CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1			// CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1
	// CHECK3-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16			// CHECK3-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
	// CHECK3-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2			// CHECK3-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 4
	// CHECK3-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i32 0, i32 2			// CHECK3-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i32 0, i32 2
	// CHECK3-NEXT: [[TMP4:%.]] = load i32, i32 [[ARRAYIDX]], align 4			// CHECK3-NEXT: [[TMP4:%.]] = load i32, i32 [[ARRAYIDX]], align 4
	// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP4]], 1			// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP4]], 1
	// CHECK3-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4			// CHECK3-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4
	// CHECK3-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true)			// CHECK3-NEXT: call void @__kmpc_target_deinit(i1 true)
	// CHECK3-NEXT: ret void			// CHECK3-NEXT: ret void
	// CHECK3: worker.exit:			// CHECK3: worker.exit:
	// CHECK3-NEXT: ret void			// CHECK3-NEXT: ret void
	//			//
	//			//
	// CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__1			// CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__1
	// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i32 nonnull align 4 dereferenceable(4) [[F:%.]], double nonnull align 8 dereferenceable(8) [[A:%.*]]) #[[ATTR1]] {			// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i32 nonnull align 4 dereferenceable(4) [[F:%.]], double nonnull align 8 dereferenceable(8) [[A:%.*]]) #[[ATTR1]] {
	// CHECK3-NEXT: entry:			// CHECK3-NEXT: entry:
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clang/test/OpenMP/nvptx_target_parallel_codegen.cpp

	Show First 20 Lines • Show All 52 Lines • ▼ Show 20 Lines
	#endif			#endif
	// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l30			// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l30
	// CHECK1-SAME: (i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0:[0-9]+]] {			// CHECK1-SAME: (i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0:[0-9]+]] {
	// CHECK1-NEXT: entry:			// CHECK1-NEXT: entry:
	// CHECK1-NEXT: [[AA_ADDR:%.]] = alloca i16, align 8			// CHECK1-NEXT: [[AA_ADDR:%.]] = alloca i16, align 8
	// CHECK1-NEXT: [[CAPTURED_VARS_ADDRS:%.]] = alloca [1 x i8], align 8			// CHECK1-NEXT: [[CAPTURED_VARS_ADDRS:%.]] = alloca [1 x i8], align 8
	// CHECK1-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 8			// CHECK1-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 8
	// CHECK1-NEXT: [[TMP0:%.]] = load i16, i16** [[AA_ADDR]], align 8			// CHECK1-NEXT: [[TMP0:%.]] = load i16, i16** [[AA_ADDR]], align 8
	// CHECK1-NEXT: [[TMP1:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1:[0-9]+]], i8 2, i1 false, i1 true)			// CHECK1-NEXT: [[TMP1:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l30_kernel_info, i1 true)
	// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1			// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
	// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]			// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
	// CHECK1: user_code.entry:			// CHECK1: user_code.entry:
	// CHECK1-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB2:[0-9]+]])			// CHECK1-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB2:[0-9]+]])
	// CHECK1-NEXT: [[TMP3:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 0			// CHECK1-NEXT: [[TMP3:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
	// CHECK1-NEXT: [[TMP4:%.]] = bitcast i16 [[TMP0]] to i8*			// CHECK1-NEXT: [[TMP4:%.]] = bitcast i16 [[TMP0]] to i8*
	// CHECK1-NEXT: store i8* [[TMP4]], i8** [[TMP3]], align 8			// CHECK1-NEXT: store i8* [[TMP4]], i8** [[TMP3]], align 8
	// CHECK1-NEXT: [[TMP5:%.]] = bitcast [1 x i8]* [[CAPTURED_VARS_ADDRS]] to i8**			// CHECK1-NEXT: [[TMP5:%.]] = bitcast [1 x i8]* [[CAPTURED_VARS_ADDRS]] to i8**
	// CHECK1-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32, i32, i16) @__omp_outlined__ to i8), i8 null, i8** [[TMP5]], i64 1)			// CHECK1-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32, i32, i16) @__omp_outlined__ to i8), i8 null, i8** [[TMP5]], i64 1)
	// CHECK1-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 true)			// CHECK1-NEXT: call void @__kmpc_target_deinit(i1 true)
	// CHECK1-NEXT: ret void			// CHECK1-NEXT: ret void
	// CHECK1: worker.exit:			// CHECK1: worker.exit:
	// CHECK1-NEXT: ret void			// CHECK1-NEXT: ret void
	//			//
	//			//
	// CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__			// CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__
	// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i16 nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1:[0-9]+]] {			// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i16 nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1:[0-9]+]] {
	// CHECK1-NEXT: entry:			// CHECK1-NEXT: entry:
	Show All 20 Lines
	// CHECK1-NEXT: [[B_ADDR:%.]] = alloca [10 x i32], align 8			// CHECK1-NEXT: [[B_ADDR:%.]] = alloca [10 x i32], align 8
	// CHECK1-NEXT: [[CAPTURED_VARS_ADDRS:%.]] = alloca [3 x i8], align 8			// CHECK1-NEXT: [[CAPTURED_VARS_ADDRS:%.]] = alloca [3 x i8], align 8
	// CHECK1-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8			// CHECK1-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
	// CHECK1-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 8			// CHECK1-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 8
	// CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8			// CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
	// CHECK1-NEXT: [[TMP0:%.]] = load i32, i32** [[A_ADDR]], align 8			// CHECK1-NEXT: [[TMP0:%.]] = load i32, i32** [[A_ADDR]], align 8
	// CHECK1-NEXT: [[TMP1:%.]] = load i16, i16** [[AA_ADDR]], align 8			// CHECK1-NEXT: [[TMP1:%.]] = load i16, i16** [[AA_ADDR]], align 8
	// CHECK1-NEXT: [[TMP2:%.]] = load [10 x i32], [10 x i32]** [[B_ADDR]], align 8			// CHECK1-NEXT: [[TMP2:%.]] = load [10 x i32], [10 x i32]** [[B_ADDR]], align 8
	// CHECK1-NEXT: [[TMP3:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 2, i1 false, i1 true)			// CHECK1-NEXT: [[TMP3:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l35_kernel_info, i1 true)
	// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP3]], -1			// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP3]], -1
	// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]			// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
	// CHECK1: user_code.entry:			// CHECK1: user_code.entry:
	// CHECK1-NEXT: [[TMP4:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB2]])			// CHECK1-NEXT: [[TMP4:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB2]])
	// CHECK1-NEXT: [[TMP5:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 0			// CHECK1-NEXT: [[TMP5:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
	// CHECK1-NEXT: [[TMP6:%.]] = bitcast i32 [[TMP0]] to i8*			// CHECK1-NEXT: [[TMP6:%.]] = bitcast i32 [[TMP0]] to i8*
	// CHECK1-NEXT: store i8* [[TMP6]], i8** [[TMP5]], align 8			// CHECK1-NEXT: store i8* [[TMP6]], i8** [[TMP5]], align 8
	// CHECK1-NEXT: [[TMP7:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 1			// CHECK1-NEXT: [[TMP7:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
	// CHECK1-NEXT: [[TMP8:%.]] = bitcast i16 [[TMP1]] to i8*			// CHECK1-NEXT: [[TMP8:%.]] = bitcast i16 [[TMP1]] to i8*
	// CHECK1-NEXT: store i8* [[TMP8]], i8** [[TMP7]], align 8			// CHECK1-NEXT: store i8* [[TMP8]], i8** [[TMP7]], align 8
	// CHECK1-NEXT: [[TMP9:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 2			// CHECK1-NEXT: [[TMP9:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 2
	// CHECK1-NEXT: [[TMP10:%.]] = bitcast [10 x i32] [[TMP2]] to i8*			// CHECK1-NEXT: [[TMP10:%.]] = bitcast [10 x i32] [[TMP2]] to i8*
	// CHECK1-NEXT: store i8* [[TMP10]], i8** [[TMP9]], align 8			// CHECK1-NEXT: store i8* [[TMP10]], i8** [[TMP9]], align 8
	// CHECK1-NEXT: [[TMP11:%.]] = bitcast [3 x i8]* [[CAPTURED_VARS_ADDRS]] to i8**			// CHECK1-NEXT: [[TMP11:%.]] = bitcast [3 x i8]* [[CAPTURED_VARS_ADDRS]] to i8**
	// CHECK1-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32, i32, i32, i16, [10 x i32]) @__omp_outlined__1 to i8), i8 null, i8** [[TMP11]], i64 3)			// CHECK1-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32, i32, i32, i16, [10 x i32]) @__omp_outlined__1 to i8), i8 null, i8** [[TMP11]], i64 3)
	// CHECK1-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 true)			// CHECK1-NEXT: call void @__kmpc_target_deinit(i1 true)
	// CHECK1-NEXT: ret void			// CHECK1-NEXT: ret void
	// CHECK1: worker.exit:			// CHECK1: worker.exit:
	// CHECK1-NEXT: ret void			// CHECK1-NEXT: ret void
	//			//
	//			//
	// CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__1			// CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__1
	// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i32 nonnull align 4 dereferenceable(4) [[A:%.]], i16 nonnull align 2 dereferenceable(2) [[AA:%.]], [10 x i32] nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {			// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i32 nonnull align 4 dereferenceable(4) [[A:%.]], i16 nonnull align 2 dereferenceable(2) [[AA:%.]], [10 x i32] nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {
	// CHECK1-NEXT: entry:			// CHECK1-NEXT: entry:
	Show All 27 Lines
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l30			// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l30
	// CHECK2-SAME: (i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0:[0-9]+]] {			// CHECK2-SAME: (i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0:[0-9]+]] {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	// CHECK2-NEXT: [[AA_ADDR:%.]] = alloca i16, align 4			// CHECK2-NEXT: [[AA_ADDR:%.]] = alloca i16, align 4
	// CHECK2-NEXT: [[CAPTURED_VARS_ADDRS:%.]] = alloca [1 x i8], align 4			// CHECK2-NEXT: [[CAPTURED_VARS_ADDRS:%.]] = alloca [1 x i8], align 4
	// CHECK2-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 4			// CHECK2-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 4
	// CHECK2-NEXT: [[TMP0:%.]] = load i16, i16** [[AA_ADDR]], align 4			// CHECK2-NEXT: [[TMP0:%.]] = load i16, i16** [[AA_ADDR]], align 4
	// CHECK2-NEXT: [[TMP1:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1:[0-9]+]], i8 2, i1 false, i1 true)			// CHECK2-NEXT: [[TMP1:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l30_kernel_info, i1 true)
	// CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1			// CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
	// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]			// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
	// CHECK2: user_code.entry:			// CHECK2: user_code.entry:
	// CHECK2-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB2:[0-9]+]])			// CHECK2-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB2:[0-9]+]])
	// CHECK2-NEXT: [[TMP3:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[CAPTURED_VARS_ADDRS]], i32 0, i32 0			// CHECK2-NEXT: [[TMP3:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
	// CHECK2-NEXT: [[TMP4:%.]] = bitcast i16 [[TMP0]] to i8*			// CHECK2-NEXT: [[TMP4:%.]] = bitcast i16 [[TMP0]] to i8*
	// CHECK2-NEXT: store i8* [[TMP4]], i8** [[TMP3]], align 4			// CHECK2-NEXT: store i8* [[TMP4]], i8** [[TMP3]], align 4
	// CHECK2-NEXT: [[TMP5:%.]] = bitcast [1 x i8]* [[CAPTURED_VARS_ADDRS]] to i8**			// CHECK2-NEXT: [[TMP5:%.]] = bitcast [1 x i8]* [[CAPTURED_VARS_ADDRS]] to i8**
	// CHECK2-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32, i32, i16) @__omp_outlined__ to i8), i8 null, i8** [[TMP5]], i32 1)			// CHECK2-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32, i32, i16) @__omp_outlined__ to i8), i8 null, i8** [[TMP5]], i32 1)
	// CHECK2-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 true)			// CHECK2-NEXT: call void @__kmpc_target_deinit(i1 true)
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	// CHECK2: worker.exit:			// CHECK2: worker.exit:
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__			// CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__
	// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i16 nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1:[0-9]+]] {			// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i16 nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1:[0-9]+]] {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	Show All 20 Lines
	// CHECK2-NEXT: [[B_ADDR:%.]] = alloca [10 x i32], align 4			// CHECK2-NEXT: [[B_ADDR:%.]] = alloca [10 x i32], align 4
	// CHECK2-NEXT: [[CAPTURED_VARS_ADDRS:%.]] = alloca [3 x i8], align 4			// CHECK2-NEXT: [[CAPTURED_VARS_ADDRS:%.]] = alloca [3 x i8], align 4
	// CHECK2-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4			// CHECK2-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4
	// CHECK2-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 4			// CHECK2-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 4
	// CHECK2-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4			// CHECK2-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
	// CHECK2-NEXT: [[TMP0:%.]] = load i32, i32** [[A_ADDR]], align 4			// CHECK2-NEXT: [[TMP0:%.]] = load i32, i32** [[A_ADDR]], align 4
	// CHECK2-NEXT: [[TMP1:%.]] = load i16, i16** [[AA_ADDR]], align 4			// CHECK2-NEXT: [[TMP1:%.]] = load i16, i16** [[AA_ADDR]], align 4
	// CHECK2-NEXT: [[TMP2:%.]] = load [10 x i32], [10 x i32]** [[B_ADDR]], align 4			// CHECK2-NEXT: [[TMP2:%.]] = load [10 x i32], [10 x i32]** [[B_ADDR]], align 4
	// CHECK2-NEXT: [[TMP3:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 2, i1 false, i1 true)			// CHECK2-NEXT: [[TMP3:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l35_kernel_info, i1 true)
	// CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP3]], -1			// CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP3]], -1
	// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]			// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
	// CHECK2: user_code.entry:			// CHECK2: user_code.entry:
	// CHECK2-NEXT: [[TMP4:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB2]])			// CHECK2-NEXT: [[TMP4:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB2]])
	// CHECK2-NEXT: [[TMP5:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[CAPTURED_VARS_ADDRS]], i32 0, i32 0			// CHECK2-NEXT: [[TMP5:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
	// CHECK2-NEXT: [[TMP6:%.]] = bitcast i32 [[TMP0]] to i8*			// CHECK2-NEXT: [[TMP6:%.]] = bitcast i32 [[TMP0]] to i8*
	// CHECK2-NEXT: store i8* [[TMP6]], i8** [[TMP5]], align 4			// CHECK2-NEXT: store i8* [[TMP6]], i8** [[TMP5]], align 4
	// CHECK2-NEXT: [[TMP7:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[CAPTURED_VARS_ADDRS]], i32 0, i32 1			// CHECK2-NEXT: [[TMP7:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[CAPTURED_VARS_ADDRS]], i32 0, i32 1
	// CHECK2-NEXT: [[TMP8:%.]] = bitcast i16 [[TMP1]] to i8*			// CHECK2-NEXT: [[TMP8:%.]] = bitcast i16 [[TMP1]] to i8*
	// CHECK2-NEXT: store i8* [[TMP8]], i8** [[TMP7]], align 4			// CHECK2-NEXT: store i8* [[TMP8]], i8** [[TMP7]], align 4
	// CHECK2-NEXT: [[TMP9:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[CAPTURED_VARS_ADDRS]], i32 0, i32 2			// CHECK2-NEXT: [[TMP9:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[CAPTURED_VARS_ADDRS]], i32 0, i32 2
	// CHECK2-NEXT: [[TMP10:%.]] = bitcast [10 x i32] [[TMP2]] to i8*			// CHECK2-NEXT: [[TMP10:%.]] = bitcast [10 x i32] [[TMP2]] to i8*
	// CHECK2-NEXT: store i8* [[TMP10]], i8** [[TMP9]], align 4			// CHECK2-NEXT: store i8* [[TMP10]], i8** [[TMP9]], align 4
	// CHECK2-NEXT: [[TMP11:%.]] = bitcast [3 x i8]* [[CAPTURED_VARS_ADDRS]] to i8**			// CHECK2-NEXT: [[TMP11:%.]] = bitcast [3 x i8]* [[CAPTURED_VARS_ADDRS]] to i8**
	// CHECK2-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32, i32, i32, i16, [10 x i32]) @__omp_outlined__1 to i8), i8 null, i8** [[TMP11]], i32 3)			// CHECK2-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32, i32, i32, i16, [10 x i32]) @__omp_outlined__1 to i8), i8 null, i8** [[TMP11]], i32 3)
	// CHECK2-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 true)			// CHECK2-NEXT: call void @__kmpc_target_deinit(i1 true)
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	// CHECK2: worker.exit:			// CHECK2: worker.exit:
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__1			// CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__1
	// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i32 nonnull align 4 dereferenceable(4) [[A:%.]], i16 nonnull align 2 dereferenceable(2) [[AA:%.]], [10 x i32] nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {			// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i32 nonnull align 4 dereferenceable(4) [[A:%.]], i16 nonnull align 2 dereferenceable(2) [[AA:%.]], [10 x i32] nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	Show All 27 Lines
	//			//
	// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l30			// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l30
	// CHECK3-SAME: (i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0:[0-9]+]] {			// CHECK3-SAME: (i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0:[0-9]+]] {
	// CHECK3-NEXT: entry:			// CHECK3-NEXT: entry:
	// CHECK3-NEXT: [[AA_ADDR:%.]] = alloca i16, align 4			// CHECK3-NEXT: [[AA_ADDR:%.]] = alloca i16, align 4
	// CHECK3-NEXT: [[CAPTURED_VARS_ADDRS:%.]] = alloca [1 x i8], align 4			// CHECK3-NEXT: [[CAPTURED_VARS_ADDRS:%.]] = alloca [1 x i8], align 4
	// CHECK3-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 4			// CHECK3-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 4
	// CHECK3-NEXT: [[TMP0:%.]] = load i16, i16** [[AA_ADDR]], align 4			// CHECK3-NEXT: [[TMP0:%.]] = load i16, i16** [[AA_ADDR]], align 4
	// CHECK3-NEXT: [[TMP1:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1:[0-9]+]], i8 2, i1 false, i1 true)			// CHECK3-NEXT: [[TMP1:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l30_kernel_info, i1 true)
	// CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1			// CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
	// CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]			// CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
	// CHECK3: user_code.entry:			// CHECK3: user_code.entry:
	// CHECK3-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB2:[0-9]+]])			// CHECK3-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB2:[0-9]+]])
	// CHECK3-NEXT: [[TMP3:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[CAPTURED_VARS_ADDRS]], i32 0, i32 0			// CHECK3-NEXT: [[TMP3:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
	// CHECK3-NEXT: [[TMP4:%.]] = bitcast i16 [[TMP0]] to i8*			// CHECK3-NEXT: [[TMP4:%.]] = bitcast i16 [[TMP0]] to i8*
	// CHECK3-NEXT: store i8* [[TMP4]], i8** [[TMP3]], align 4			// CHECK3-NEXT: store i8* [[TMP4]], i8** [[TMP3]], align 4
	// CHECK3-NEXT: [[TMP5:%.]] = bitcast [1 x i8]* [[CAPTURED_VARS_ADDRS]] to i8**			// CHECK3-NEXT: [[TMP5:%.]] = bitcast [1 x i8]* [[CAPTURED_VARS_ADDRS]] to i8**
	// CHECK3-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32, i32, i16) @__omp_outlined__ to i8), i8 null, i8** [[TMP5]], i32 1)			// CHECK3-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32, i32, i16) @__omp_outlined__ to i8), i8 null, i8** [[TMP5]], i32 1)
	// CHECK3-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 true)			// CHECK3-NEXT: call void @__kmpc_target_deinit(i1 true)
	// CHECK3-NEXT: ret void			// CHECK3-NEXT: ret void
	// CHECK3: worker.exit:			// CHECK3: worker.exit:
	// CHECK3-NEXT: ret void			// CHECK3-NEXT: ret void
	//			//
	//			//
	// CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__			// CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__
	// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i16 nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1:[0-9]+]] {			// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i16 nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1:[0-9]+]] {
	// CHECK3-NEXT: entry:			// CHECK3-NEXT: entry:
	Show All 20 Lines
	// CHECK3-NEXT: [[B_ADDR:%.]] = alloca [10 x i32], align 4			// CHECK3-NEXT: [[B_ADDR:%.]] = alloca [10 x i32], align 4
	// CHECK3-NEXT: [[CAPTURED_VARS_ADDRS:%.]] = alloca [3 x i8], align 4			// CHECK3-NEXT: [[CAPTURED_VARS_ADDRS:%.]] = alloca [3 x i8], align 4
	// CHECK3-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4			// CHECK3-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4
	// CHECK3-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 4			// CHECK3-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 4
	// CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4			// CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
	// CHECK3-NEXT: [[TMP0:%.]] = load i32, i32** [[A_ADDR]], align 4			// CHECK3-NEXT: [[TMP0:%.]] = load i32, i32** [[A_ADDR]], align 4
	// CHECK3-NEXT: [[TMP1:%.]] = load i16, i16** [[AA_ADDR]], align 4			// CHECK3-NEXT: [[TMP1:%.]] = load i16, i16** [[AA_ADDR]], align 4
	// CHECK3-NEXT: [[TMP2:%.]] = load [10 x i32], [10 x i32]** [[B_ADDR]], align 4			// CHECK3-NEXT: [[TMP2:%.]] = load [10 x i32], [10 x i32]** [[B_ADDR]], align 4
	// CHECK3-NEXT: [[TMP3:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 2, i1 false, i1 true)			// CHECK3-NEXT: [[TMP3:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l35_kernel_info, i1 true)
	// CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP3]], -1			// CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP3]], -1
	// CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]			// CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
	// CHECK3: user_code.entry:			// CHECK3: user_code.entry:
	// CHECK3-NEXT: [[TMP4:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB2]])			// CHECK3-NEXT: [[TMP4:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB2]])
	// CHECK3-NEXT: [[TMP5:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[CAPTURED_VARS_ADDRS]], i32 0, i32 0			// CHECK3-NEXT: [[TMP5:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
	// CHECK3-NEXT: [[TMP6:%.]] = bitcast i32 [[TMP0]] to i8*			// CHECK3-NEXT: [[TMP6:%.]] = bitcast i32 [[TMP0]] to i8*
	// CHECK3-NEXT: store i8* [[TMP6]], i8** [[TMP5]], align 4			// CHECK3-NEXT: store i8* [[TMP6]], i8** [[TMP5]], align 4
	// CHECK3-NEXT: [[TMP7:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[CAPTURED_VARS_ADDRS]], i32 0, i32 1			// CHECK3-NEXT: [[TMP7:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[CAPTURED_VARS_ADDRS]], i32 0, i32 1
	// CHECK3-NEXT: [[TMP8:%.]] = bitcast i16 [[TMP1]] to i8*			// CHECK3-NEXT: [[TMP8:%.]] = bitcast i16 [[TMP1]] to i8*
	// CHECK3-NEXT: store i8* [[TMP8]], i8** [[TMP7]], align 4			// CHECK3-NEXT: store i8* [[TMP8]], i8** [[TMP7]], align 4
	// CHECK3-NEXT: [[TMP9:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[CAPTURED_VARS_ADDRS]], i32 0, i32 2			// CHECK3-NEXT: [[TMP9:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[CAPTURED_VARS_ADDRS]], i32 0, i32 2
	// CHECK3-NEXT: [[TMP10:%.]] = bitcast [10 x i32] [[TMP2]] to i8*			// CHECK3-NEXT: [[TMP10:%.]] = bitcast [10 x i32] [[TMP2]] to i8*
	// CHECK3-NEXT: store i8* [[TMP10]], i8** [[TMP9]], align 4			// CHECK3-NEXT: store i8* [[TMP10]], i8** [[TMP9]], align 4
	// CHECK3-NEXT: [[TMP11:%.]] = bitcast [3 x i8]* [[CAPTURED_VARS_ADDRS]] to i8**			// CHECK3-NEXT: [[TMP11:%.]] = bitcast [3 x i8]* [[CAPTURED_VARS_ADDRS]] to i8**
	// CHECK3-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32, i32, i32, i16, [10 x i32]) @__omp_outlined__1 to i8), i8 null, i8** [[TMP11]], i32 3)			// CHECK3-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32, i32, i32, i16, [10 x i32]) @__omp_outlined__1 to i8), i8 null, i8** [[TMP11]], i32 3)
	// CHECK3-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 true)			// CHECK3-NEXT: call void @__kmpc_target_deinit(i1 true)
	// CHECK3-NEXT: ret void			// CHECK3-NEXT: ret void
	// CHECK3: worker.exit:			// CHECK3: worker.exit:
	// CHECK3-NEXT: ret void			// CHECK3-NEXT: ret void
	//			//
	//			//
	// CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__1			// CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__1
	// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i32 nonnull align 4 dereferenceable(4) [[A:%.]], i16 nonnull align 2 dereferenceable(2) [[AA:%.]], [10 x i32] nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {			// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i32 nonnull align 4 dereferenceable(4) [[A:%.]], i16 nonnull align 2 dereferenceable(2) [[AA:%.]], [10 x i32] nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {
	// CHECK3-NEXT: entry:			// CHECK3-NEXT: entry:
	Show All 27 Lines
	//			//
	// CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l30			// CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l30
	// CHECK4-SAME: (i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0:[0-9]+]] {			// CHECK4-SAME: (i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0:[0-9]+]] {
	// CHECK4-NEXT: entry:			// CHECK4-NEXT: entry:
	// CHECK4-NEXT: [[AA_ADDR:%.]] = alloca i16, align 8			// CHECK4-NEXT: [[AA_ADDR:%.]] = alloca i16, align 8
	// CHECK4-NEXT: [[CAPTURED_VARS_ADDRS:%.]] = alloca [1 x i8], align 8			// CHECK4-NEXT: [[CAPTURED_VARS_ADDRS:%.]] = alloca [1 x i8], align 8
	// CHECK4-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 8			// CHECK4-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 8
	// CHECK4-NEXT: [[TMP0:%.]] = load i16, i16** [[AA_ADDR]], align 8			// CHECK4-NEXT: [[TMP0:%.]] = load i16, i16** [[AA_ADDR]], align 8
	// CHECK4-NEXT: [[TMP1:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1:[0-9]+]], i8 2, i1 false, i1 true)			// CHECK4-NEXT: [[TMP1:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l30_kernel_info, i1 true)
	// CHECK4-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1			// CHECK4-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
	// CHECK4-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]			// CHECK4-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
	// CHECK4: user_code.entry:			// CHECK4: user_code.entry:
	// CHECK4-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB2:[0-9]+]])			// CHECK4-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB2:[0-9]+]])
	// CHECK4-NEXT: [[TMP3:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 0			// CHECK4-NEXT: [[TMP3:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
	// CHECK4-NEXT: [[TMP4:%.]] = bitcast i16 [[TMP0]] to i8*			// CHECK4-NEXT: [[TMP4:%.]] = bitcast i16 [[TMP0]] to i8*
	// CHECK4-NEXT: store i8* [[TMP4]], i8** [[TMP3]], align 8			// CHECK4-NEXT: store i8* [[TMP4]], i8** [[TMP3]], align 8
	// CHECK4-NEXT: [[TMP5:%.]] = bitcast [1 x i8]* [[CAPTURED_VARS_ADDRS]] to i8**			// CHECK4-NEXT: [[TMP5:%.]] = bitcast [1 x i8]* [[CAPTURED_VARS_ADDRS]] to i8**
	// CHECK4-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32, i32, i16) @__omp_outlined__ to i8), i8 null, i8** [[TMP5]], i64 1)			// CHECK4-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32, i32, i16) @__omp_outlined__ to i8), i8 null, i8** [[TMP5]], i64 1)
	// CHECK4-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 true)			// CHECK4-NEXT: call void @__kmpc_target_deinit(i1 true)
	// CHECK4-NEXT: ret void			// CHECK4-NEXT: ret void
	// CHECK4: worker.exit:			// CHECK4: worker.exit:
	// CHECK4-NEXT: ret void			// CHECK4-NEXT: ret void
	//			//
	//			//
	// CHECK4-LABEL: define {{[^@]+}}@__omp_outlined__			// CHECK4-LABEL: define {{[^@]+}}@__omp_outlined__
	// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i16 nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1:[0-9]+]] {			// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i16 nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1:[0-9]+]] {
	// CHECK4-NEXT: entry:			// CHECK4-NEXT: entry:
	Show All 20 Lines
	// CHECK4-NEXT: [[B_ADDR:%.]] = alloca [10 x i32], align 8			// CHECK4-NEXT: [[B_ADDR:%.]] = alloca [10 x i32], align 8
	// CHECK4-NEXT: [[CAPTURED_VARS_ADDRS:%.]] = alloca [3 x i8], align 8			// CHECK4-NEXT: [[CAPTURED_VARS_ADDRS:%.]] = alloca [3 x i8], align 8
	// CHECK4-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8			// CHECK4-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
	// CHECK4-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 8			// CHECK4-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 8
	// CHECK4-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8			// CHECK4-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
	// CHECK4-NEXT: [[TMP0:%.]] = load i32, i32** [[A_ADDR]], align 8			// CHECK4-NEXT: [[TMP0:%.]] = load i32, i32** [[A_ADDR]], align 8
	// CHECK4-NEXT: [[TMP1:%.]] = load i16, i16** [[AA_ADDR]], align 8			// CHECK4-NEXT: [[TMP1:%.]] = load i16, i16** [[AA_ADDR]], align 8
	// CHECK4-NEXT: [[TMP2:%.]] = load [10 x i32], [10 x i32]** [[B_ADDR]], align 8			// CHECK4-NEXT: [[TMP2:%.]] = load [10 x i32], [10 x i32]** [[B_ADDR]], align 8
	// CHECK4-NEXT: [[TMP3:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 2, i1 false, i1 true)			// CHECK4-NEXT: [[TMP3:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l35_kernel_info, i1 true)
	// CHECK4-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP3]], -1			// CHECK4-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP3]], -1
	// CHECK4-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]			// CHECK4-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
	// CHECK4: user_code.entry:			// CHECK4: user_code.entry:
	// CHECK4-NEXT: [[TMP4:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB2]])			// CHECK4-NEXT: [[TMP4:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB2]])
	// CHECK4-NEXT: [[TMP5:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 0			// CHECK4-NEXT: [[TMP5:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
	// CHECK4-NEXT: [[TMP6:%.]] = bitcast i32 [[TMP0]] to i8*			// CHECK4-NEXT: [[TMP6:%.]] = bitcast i32 [[TMP0]] to i8*
	// CHECK4-NEXT: store i8* [[TMP6]], i8** [[TMP5]], align 8			// CHECK4-NEXT: store i8* [[TMP6]], i8** [[TMP5]], align 8
	// CHECK4-NEXT: [[TMP7:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 1			// CHECK4-NEXT: [[TMP7:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
	// CHECK4-NEXT: [[TMP8:%.]] = bitcast i16 [[TMP1]] to i8*			// CHECK4-NEXT: [[TMP8:%.]] = bitcast i16 [[TMP1]] to i8*
	// CHECK4-NEXT: store i8* [[TMP8]], i8** [[TMP7]], align 8			// CHECK4-NEXT: store i8* [[TMP8]], i8** [[TMP7]], align 8
	// CHECK4-NEXT: [[TMP9:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 2			// CHECK4-NEXT: [[TMP9:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 2
	// CHECK4-NEXT: [[TMP10:%.]] = bitcast [10 x i32] [[TMP2]] to i8*			// CHECK4-NEXT: [[TMP10:%.]] = bitcast [10 x i32] [[TMP2]] to i8*
	// CHECK4-NEXT: store i8* [[TMP10]], i8** [[TMP9]], align 8			// CHECK4-NEXT: store i8* [[TMP10]], i8** [[TMP9]], align 8
	// CHECK4-NEXT: [[TMP11:%.]] = bitcast [3 x i8]* [[CAPTURED_VARS_ADDRS]] to i8**			// CHECK4-NEXT: [[TMP11:%.]] = bitcast [3 x i8]* [[CAPTURED_VARS_ADDRS]] to i8**
	// CHECK4-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32, i32, i32, i16, [10 x i32]) @__omp_outlined__1 to i8), i8 null, i8** [[TMP11]], i64 3)			// CHECK4-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32, i32, i32, i16, [10 x i32]) @__omp_outlined__1 to i8), i8 null, i8** [[TMP11]], i64 3)
	// CHECK4-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 true)			// CHECK4-NEXT: call void @__kmpc_target_deinit(i1 true)
	// CHECK4-NEXT: ret void			// CHECK4-NEXT: ret void
	// CHECK4: worker.exit:			// CHECK4: worker.exit:
	// CHECK4-NEXT: ret void			// CHECK4-NEXT: ret void
	//			//
	//			//
	// CHECK4-LABEL: define {{[^@]+}}@__omp_outlined__1			// CHECK4-LABEL: define {{[^@]+}}@__omp_outlined__1
	// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i32 nonnull align 4 dereferenceable(4) [[A:%.]], i16 nonnull align 2 dereferenceable(2) [[AA:%.]], [10 x i32] nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {			// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i32 nonnull align 4 dereferenceable(4) [[A:%.]], i16 nonnull align 2 dereferenceable(2) [[AA:%.]], [10 x i32] nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {
	// CHECK4-NEXT: entry:			// CHECK4-NEXT: entry:
	Show All 27 Lines
	//			//
	// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l30			// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l30
	// CHECK5-SAME: (i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0:[0-9]+]] {			// CHECK5-SAME: (i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0:[0-9]+]] {
	// CHECK5-NEXT: entry:			// CHECK5-NEXT: entry:
	// CHECK5-NEXT: [[AA_ADDR:%.]] = alloca i16, align 4			// CHECK5-NEXT: [[AA_ADDR:%.]] = alloca i16, align 4
	// CHECK5-NEXT: [[CAPTURED_VARS_ADDRS:%.]] = alloca [1 x i8], align 4			// CHECK5-NEXT: [[CAPTURED_VARS_ADDRS:%.]] = alloca [1 x i8], align 4
	// CHECK5-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 4			// CHECK5-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 4
	// CHECK5-NEXT: [[TMP0:%.]] = load i16, i16** [[AA_ADDR]], align 4			// CHECK5-NEXT: [[TMP0:%.]] = load i16, i16** [[AA_ADDR]], align 4
	// CHECK5-NEXT: [[TMP1:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1:[0-9]+]], i8 2, i1 false, i1 true)			// CHECK5-NEXT: [[TMP1:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l30_kernel_info, i1 true)
	// CHECK5-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1			// CHECK5-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
	// CHECK5-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]			// CHECK5-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
	// CHECK5: user_code.entry:			// CHECK5: user_code.entry:
	// CHECK5-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB2:[0-9]+]])			// CHECK5-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB2:[0-9]+]])
	// CHECK5-NEXT: [[TMP3:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[CAPTURED_VARS_ADDRS]], i32 0, i32 0			// CHECK5-NEXT: [[TMP3:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
	// CHECK5-NEXT: [[TMP4:%.]] = bitcast i16 [[TMP0]] to i8*			// CHECK5-NEXT: [[TMP4:%.]] = bitcast i16 [[TMP0]] to i8*
	// CHECK5-NEXT: store i8* [[TMP4]], i8** [[TMP3]], align 4			// CHECK5-NEXT: store i8* [[TMP4]], i8** [[TMP3]], align 4
	// CHECK5-NEXT: [[TMP5:%.]] = bitcast [1 x i8]* [[CAPTURED_VARS_ADDRS]] to i8**			// CHECK5-NEXT: [[TMP5:%.]] = bitcast [1 x i8]* [[CAPTURED_VARS_ADDRS]] to i8**
	// CHECK5-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32, i32, i16) @__omp_outlined__ to i8), i8 null, i8** [[TMP5]], i32 1)			// CHECK5-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32, i32, i16) @__omp_outlined__ to i8), i8 null, i8** [[TMP5]], i32 1)
	// CHECK5-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 true)			// CHECK5-NEXT: call void @__kmpc_target_deinit(i1 true)
	// CHECK5-NEXT: ret void			// CHECK5-NEXT: ret void
	// CHECK5: worker.exit:			// CHECK5: worker.exit:
	// CHECK5-NEXT: ret void			// CHECK5-NEXT: ret void
	//			//
	//			//
	// CHECK5-LABEL: define {{[^@]+}}@__omp_outlined__			// CHECK5-LABEL: define {{[^@]+}}@__omp_outlined__
	// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i16 nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1:[0-9]+]] {			// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i16 nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1:[0-9]+]] {
	// CHECK5-NEXT: entry:			// CHECK5-NEXT: entry:
	Show All 20 Lines
	// CHECK5-NEXT: [[B_ADDR:%.]] = alloca [10 x i32], align 4			// CHECK5-NEXT: [[B_ADDR:%.]] = alloca [10 x i32], align 4
	// CHECK5-NEXT: [[CAPTURED_VARS_ADDRS:%.]] = alloca [3 x i8], align 4			// CHECK5-NEXT: [[CAPTURED_VARS_ADDRS:%.]] = alloca [3 x i8], align 4
	// CHECK5-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4			// CHECK5-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4
	// CHECK5-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 4			// CHECK5-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 4
	// CHECK5-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4			// CHECK5-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
	// CHECK5-NEXT: [[TMP0:%.]] = load i32, i32** [[A_ADDR]], align 4			// CHECK5-NEXT: [[TMP0:%.]] = load i32, i32** [[A_ADDR]], align 4
	// CHECK5-NEXT: [[TMP1:%.]] = load i16, i16** [[AA_ADDR]], align 4			// CHECK5-NEXT: [[TMP1:%.]] = load i16, i16** [[AA_ADDR]], align 4
	// CHECK5-NEXT: [[TMP2:%.]] = load [10 x i32], [10 x i32]** [[B_ADDR]], align 4			// CHECK5-NEXT: [[TMP2:%.]] = load [10 x i32], [10 x i32]** [[B_ADDR]], align 4
	// CHECK5-NEXT: [[TMP3:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 2, i1 false, i1 true)			// CHECK5-NEXT: [[TMP3:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l35_kernel_info, i1 true)
	// CHECK5-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP3]], -1			// CHECK5-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP3]], -1
	// CHECK5-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]			// CHECK5-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
	// CHECK5: user_code.entry:			// CHECK5: user_code.entry:
	// CHECK5-NEXT: [[TMP4:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB2]])			// CHECK5-NEXT: [[TMP4:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB2]])
	// CHECK5-NEXT: [[TMP5:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[CAPTURED_VARS_ADDRS]], i32 0, i32 0			// CHECK5-NEXT: [[TMP5:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
	// CHECK5-NEXT: [[TMP6:%.]] = bitcast i32 [[TMP0]] to i8*			// CHECK5-NEXT: [[TMP6:%.]] = bitcast i32 [[TMP0]] to i8*
	// CHECK5-NEXT: store i8* [[TMP6]], i8** [[TMP5]], align 4			// CHECK5-NEXT: store i8* [[TMP6]], i8** [[TMP5]], align 4
	// CHECK5-NEXT: [[TMP7:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[CAPTURED_VARS_ADDRS]], i32 0, i32 1			// CHECK5-NEXT: [[TMP7:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[CAPTURED_VARS_ADDRS]], i32 0, i32 1
	// CHECK5-NEXT: [[TMP8:%.]] = bitcast i16 [[TMP1]] to i8*			// CHECK5-NEXT: [[TMP8:%.]] = bitcast i16 [[TMP1]] to i8*
	// CHECK5-NEXT: store i8* [[TMP8]], i8** [[TMP7]], align 4			// CHECK5-NEXT: store i8* [[TMP8]], i8** [[TMP7]], align 4
	// CHECK5-NEXT: [[TMP9:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[CAPTURED_VARS_ADDRS]], i32 0, i32 2			// CHECK5-NEXT: [[TMP9:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[CAPTURED_VARS_ADDRS]], i32 0, i32 2
	// CHECK5-NEXT: [[TMP10:%.]] = bitcast [10 x i32] [[TMP2]] to i8*			// CHECK5-NEXT: [[TMP10:%.]] = bitcast [10 x i32] [[TMP2]] to i8*
	// CHECK5-NEXT: store i8* [[TMP10]], i8** [[TMP9]], align 4			// CHECK5-NEXT: store i8* [[TMP10]], i8** [[TMP9]], align 4
	// CHECK5-NEXT: [[TMP11:%.]] = bitcast [3 x i8]* [[CAPTURED_VARS_ADDRS]] to i8**			// CHECK5-NEXT: [[TMP11:%.]] = bitcast [3 x i8]* [[CAPTURED_VARS_ADDRS]] to i8**
	// CHECK5-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32, i32, i32, i16, [10 x i32]) @__omp_outlined__1 to i8), i8 null, i8** [[TMP11]], i32 3)			// CHECK5-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32, i32, i32, i16, [10 x i32]) @__omp_outlined__1 to i8), i8 null, i8** [[TMP11]], i32 3)
	// CHECK5-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 true)			// CHECK5-NEXT: call void @__kmpc_target_deinit(i1 true)
	// CHECK5-NEXT: ret void			// CHECK5-NEXT: ret void
	// CHECK5: worker.exit:			// CHECK5: worker.exit:
	// CHECK5-NEXT: ret void			// CHECK5-NEXT: ret void
	//			//
	//			//
	// CHECK5-LABEL: define {{[^@]+}}@__omp_outlined__1			// CHECK5-LABEL: define {{[^@]+}}@__omp_outlined__1
	// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i32 nonnull align 4 dereferenceable(4) [[A:%.]], i16 nonnull align 2 dereferenceable(2) [[AA:%.]], [10 x i32] nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {			// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i32 nonnull align 4 dereferenceable(4) [[A:%.]], i16 nonnull align 2 dereferenceable(2) [[AA:%.]], [10 x i32] nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {
	// CHECK5-NEXT: entry:			// CHECK5-NEXT: entry:
	Show All 27 Lines
	//			//
	// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l30			// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l30
	// CHECK6-SAME: (i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0:[0-9]+]] {			// CHECK6-SAME: (i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0:[0-9]+]] {
	// CHECK6-NEXT: entry:			// CHECK6-NEXT: entry:
	// CHECK6-NEXT: [[AA_ADDR:%.]] = alloca i16, align 4			// CHECK6-NEXT: [[AA_ADDR:%.]] = alloca i16, align 4
	// CHECK6-NEXT: [[CAPTURED_VARS_ADDRS:%.]] = alloca [1 x i8], align 4			// CHECK6-NEXT: [[CAPTURED_VARS_ADDRS:%.]] = alloca [1 x i8], align 4
	// CHECK6-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 4			// CHECK6-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 4
	// CHECK6-NEXT: [[TMP0:%.]] = load i16, i16** [[AA_ADDR]], align 4			// CHECK6-NEXT: [[TMP0:%.]] = load i16, i16** [[AA_ADDR]], align 4
	// CHECK6-NEXT: [[TMP1:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1:[0-9]+]], i8 2, i1 false, i1 true)			// CHECK6-NEXT: [[TMP1:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l30_kernel_info, i1 true)
	// CHECK6-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1			// CHECK6-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
	// CHECK6-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]			// CHECK6-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
	// CHECK6: user_code.entry:			// CHECK6: user_code.entry:
	// CHECK6-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB2:[0-9]+]])			// CHECK6-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB2:[0-9]+]])
	// CHECK6-NEXT: [[TMP3:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[CAPTURED_VARS_ADDRS]], i32 0, i32 0			// CHECK6-NEXT: [[TMP3:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
	// CHECK6-NEXT: [[TMP4:%.]] = bitcast i16 [[TMP0]] to i8*			// CHECK6-NEXT: [[TMP4:%.]] = bitcast i16 [[TMP0]] to i8*
	// CHECK6-NEXT: store i8* [[TMP4]], i8** [[TMP3]], align 4			// CHECK6-NEXT: store i8* [[TMP4]], i8** [[TMP3]], align 4
	// CHECK6-NEXT: [[TMP5:%.]] = bitcast [1 x i8]* [[CAPTURED_VARS_ADDRS]] to i8**			// CHECK6-NEXT: [[TMP5:%.]] = bitcast [1 x i8]* [[CAPTURED_VARS_ADDRS]] to i8**
	// CHECK6-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32, i32, i16) @__omp_outlined__ to i8), i8 null, i8** [[TMP5]], i32 1)			// CHECK6-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32, i32, i16) @__omp_outlined__ to i8), i8 null, i8** [[TMP5]], i32 1)
	// CHECK6-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 true)			// CHECK6-NEXT: call void @__kmpc_target_deinit(i1 true)
	// CHECK6-NEXT: ret void			// CHECK6-NEXT: ret void
	// CHECK6: worker.exit:			// CHECK6: worker.exit:
	// CHECK6-NEXT: ret void			// CHECK6-NEXT: ret void
	//			//
	//			//
	// CHECK6-LABEL: define {{[^@]+}}@__omp_outlined__			// CHECK6-LABEL: define {{[^@]+}}@__omp_outlined__
	// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i16 nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1:[0-9]+]] {			// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i16 nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1:[0-9]+]] {
	// CHECK6-NEXT: entry:			// CHECK6-NEXT: entry:
	Show All 20 Lines
	// CHECK6-NEXT: [[B_ADDR:%.]] = alloca [10 x i32], align 4			// CHECK6-NEXT: [[B_ADDR:%.]] = alloca [10 x i32], align 4
	// CHECK6-NEXT: [[CAPTURED_VARS_ADDRS:%.]] = alloca [3 x i8], align 4			// CHECK6-NEXT: [[CAPTURED_VARS_ADDRS:%.]] = alloca [3 x i8], align 4
	// CHECK6-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4			// CHECK6-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4
	// CHECK6-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 4			// CHECK6-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 4
	// CHECK6-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4			// CHECK6-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
	// CHECK6-NEXT: [[TMP0:%.]] = load i32, i32** [[A_ADDR]], align 4			// CHECK6-NEXT: [[TMP0:%.]] = load i32, i32** [[A_ADDR]], align 4
	// CHECK6-NEXT: [[TMP1:%.]] = load i16, i16** [[AA_ADDR]], align 4			// CHECK6-NEXT: [[TMP1:%.]] = load i16, i16** [[AA_ADDR]], align 4
	// CHECK6-NEXT: [[TMP2:%.]] = load [10 x i32], [10 x i32]** [[B_ADDR]], align 4			// CHECK6-NEXT: [[TMP2:%.]] = load [10 x i32], [10 x i32]** [[B_ADDR]], align 4
	// CHECK6-NEXT: [[TMP3:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 2, i1 false, i1 true)			// CHECK6-NEXT: [[TMP3:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l35_kernel_info, i1 true)
	// CHECK6-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP3]], -1			// CHECK6-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP3]], -1
	// CHECK6-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]			// CHECK6-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
	// CHECK6: user_code.entry:			// CHECK6: user_code.entry:
	// CHECK6-NEXT: [[TMP4:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB2]])			// CHECK6-NEXT: [[TMP4:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB2]])
	// CHECK6-NEXT: [[TMP5:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[CAPTURED_VARS_ADDRS]], i32 0, i32 0			// CHECK6-NEXT: [[TMP5:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
	// CHECK6-NEXT: [[TMP6:%.]] = bitcast i32 [[TMP0]] to i8*			// CHECK6-NEXT: [[TMP6:%.]] = bitcast i32 [[TMP0]] to i8*
	// CHECK6-NEXT: store i8* [[TMP6]], i8** [[TMP5]], align 4			// CHECK6-NEXT: store i8* [[TMP6]], i8** [[TMP5]], align 4
	// CHECK6-NEXT: [[TMP7:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[CAPTURED_VARS_ADDRS]], i32 0, i32 1			// CHECK6-NEXT: [[TMP7:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[CAPTURED_VARS_ADDRS]], i32 0, i32 1
	// CHECK6-NEXT: [[TMP8:%.]] = bitcast i16 [[TMP1]] to i8*			// CHECK6-NEXT: [[TMP8:%.]] = bitcast i16 [[TMP1]] to i8*
	// CHECK6-NEXT: store i8* [[TMP8]], i8** [[TMP7]], align 4			// CHECK6-NEXT: store i8* [[TMP8]], i8** [[TMP7]], align 4
	// CHECK6-NEXT: [[TMP9:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[CAPTURED_VARS_ADDRS]], i32 0, i32 2			// CHECK6-NEXT: [[TMP9:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[CAPTURED_VARS_ADDRS]], i32 0, i32 2
	// CHECK6-NEXT: [[TMP10:%.]] = bitcast [10 x i32] [[TMP2]] to i8*			// CHECK6-NEXT: [[TMP10:%.]] = bitcast [10 x i32] [[TMP2]] to i8*
	// CHECK6-NEXT: store i8* [[TMP10]], i8** [[TMP9]], align 4			// CHECK6-NEXT: store i8* [[TMP10]], i8** [[TMP9]], align 4
	// CHECK6-NEXT: [[TMP11:%.]] = bitcast [3 x i8]* [[CAPTURED_VARS_ADDRS]] to i8**			// CHECK6-NEXT: [[TMP11:%.]] = bitcast [3 x i8]* [[CAPTURED_VARS_ADDRS]] to i8**
	// CHECK6-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32, i32, i32, i16, [10 x i32]) @__omp_outlined__1 to i8), i8 null, i8** [[TMP11]], i32 3)			// CHECK6-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32, i32, i32, i16, [10 x i32]) @__omp_outlined__1 to i8), i8 null, i8** [[TMP11]], i32 3)
	// CHECK6-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 true)			// CHECK6-NEXT: call void @__kmpc_target_deinit(i1 true)
	// CHECK6-NEXT: ret void			// CHECK6-NEXT: ret void
	// CHECK6: worker.exit:			// CHECK6: worker.exit:
	// CHECK6-NEXT: ret void			// CHECK6-NEXT: ret void
	//			//
	//			//
	// CHECK6-LABEL: define {{[^@]+}}@__omp_outlined__1			// CHECK6-LABEL: define {{[^@]+}}@__omp_outlined__1
	// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i32 nonnull align 4 dereferenceable(4) [[A:%.]], i16 nonnull align 2 dereferenceable(2) [[AA:%.]], [10 x i32] nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {			// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i32 nonnull align 4 dereferenceable(4) [[A:%.]], i16 nonnull align 2 dereferenceable(2) [[AA:%.]], [10 x i32] nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {
	// CHECK6-NEXT: entry:			// CHECK6-NEXT: entry:
	Show All 27 Lines

clang/test/OpenMP/nvptx_target_parallel_num_threads_codegen.cpp

	Show First 20 Lines • Show All 47 Lines • ▼ Show 20 Lines
	#endif			#endif
	// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l25			// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l25
	// CHECK1-SAME: (i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0:[0-9]+]] {			// CHECK1-SAME: (i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0:[0-9]+]] {
	// CHECK1-NEXT: entry:			// CHECK1-NEXT: entry:
	// CHECK1-NEXT: [[AA_ADDR:%.]] = alloca i16, align 8			// CHECK1-NEXT: [[AA_ADDR:%.]] = alloca i16, align 8
	// CHECK1-NEXT: [[CAPTURED_VARS_ADDRS:%.]] = alloca [1 x i8], align 8			// CHECK1-NEXT: [[CAPTURED_VARS_ADDRS:%.]] = alloca [1 x i8], align 8
	// CHECK1-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 8			// CHECK1-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 8
	// CHECK1-NEXT: [[TMP0:%.]] = load i16, i16** [[AA_ADDR]], align 8			// CHECK1-NEXT: [[TMP0:%.]] = load i16, i16** [[AA_ADDR]], align 8
	// CHECK1-NEXT: [[TMP1:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1:[0-9]+]], i8 2, i1 false, i1 true)			// CHECK1-NEXT: [[TMP1:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l25_kernel_info, i1 true)
	// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1			// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
	// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]			// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
	// CHECK1: user_code.entry:			// CHECK1: user_code.entry:
	// CHECK1-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB2:[0-9]+]])			// CHECK1-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB2:[0-9]+]])
	// CHECK1-NEXT: [[TMP3:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 0			// CHECK1-NEXT: [[TMP3:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
	// CHECK1-NEXT: [[TMP4:%.]] = bitcast i16 [[TMP0]] to i8*			// CHECK1-NEXT: [[TMP4:%.]] = bitcast i16 [[TMP0]] to i8*
	// CHECK1-NEXT: store i8* [[TMP4]], i8** [[TMP3]], align 8			// CHECK1-NEXT: store i8* [[TMP4]], i8** [[TMP3]], align 8
	// CHECK1-NEXT: [[TMP5:%.]] = bitcast [1 x i8]* [[CAPTURED_VARS_ADDRS]] to i8**			// CHECK1-NEXT: [[TMP5:%.]] = bitcast [1 x i8]* [[CAPTURED_VARS_ADDRS]] to i8**
	// CHECK1-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32 1, i32 1024, i32 -1, i8* bitcast (void (i32, i32, i16) @__omp_outlined__ to i8), i8 null, i8** [[TMP5]], i64 1)			// CHECK1-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32 1, i32 1024, i32 -1, i8* bitcast (void (i32, i32, i16) @__omp_outlined__ to i8), i8 null, i8** [[TMP5]], i64 1)
	// CHECK1-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 true)			// CHECK1-NEXT: call void @__kmpc_target_deinit(i1 true)
	// CHECK1-NEXT: ret void			// CHECK1-NEXT: ret void
	// CHECK1: worker.exit:			// CHECK1: worker.exit:
	// CHECK1-NEXT: ret void			// CHECK1-NEXT: ret void
	//			//
	//			//
	// CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__			// CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__
	// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i16 nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1:[0-9]+]] {			// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i16 nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1:[0-9]+]] {
	// CHECK1-NEXT: entry:			// CHECK1-NEXT: entry:
	Show All 23 Lines
	// CHECK1-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8			// CHECK1-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
	// CHECK1-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 8			// CHECK1-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 8
	// CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8			// CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
	// CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8			// CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
	// CHECK1-NEXT: [[TMP0:%.]] = load i32, i32** [[A_ADDR]], align 8			// CHECK1-NEXT: [[TMP0:%.]] = load i32, i32** [[A_ADDR]], align 8
	// CHECK1-NEXT: [[TMP1:%.]] = load i16, i16** [[AA_ADDR]], align 8			// CHECK1-NEXT: [[TMP1:%.]] = load i16, i16** [[AA_ADDR]], align 8
	// CHECK1-NEXT: [[TMP2:%.]] = load [10 x i32], [10 x i32]** [[B_ADDR]], align 8			// CHECK1-NEXT: [[TMP2:%.]] = load [10 x i32], [10 x i32]** [[B_ADDR]], align 8
	// CHECK1-NEXT: [[CONV:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__ADDR]] to i32*			// CHECK1-NEXT: [[CONV:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__ADDR]] to i32*
	// CHECK1-NEXT: [[TMP3:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 2, i1 false, i1 true)			// CHECK1-NEXT: [[TMP3:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l30_kernel_info, i1 true)
	// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP3]], -1			// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP3]], -1
	// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]			// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
	// CHECK1: user_code.entry:			// CHECK1: user_code.entry:
	// CHECK1-NEXT: [[TMP4:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB2]])			// CHECK1-NEXT: [[TMP4:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB2]])
	// CHECK1-NEXT: [[TMP5:%.]] = load i32, i32 [[CONV]], align 4			// CHECK1-NEXT: [[TMP5:%.]] = load i32, i32 [[CONV]], align 4
	// CHECK1-NEXT: [[TMP6:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 0			// CHECK1-NEXT: [[TMP6:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
	// CHECK1-NEXT: [[TMP7:%.]] = bitcast i32 [[TMP0]] to i8*			// CHECK1-NEXT: [[TMP7:%.]] = bitcast i32 [[TMP0]] to i8*
	// CHECK1-NEXT: store i8* [[TMP7]], i8** [[TMP6]], align 8			// CHECK1-NEXT: store i8* [[TMP7]], i8** [[TMP6]], align 8
	// CHECK1-NEXT: [[TMP8:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 1			// CHECK1-NEXT: [[TMP8:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
	// CHECK1-NEXT: [[TMP9:%.]] = bitcast i16 [[TMP1]] to i8*			// CHECK1-NEXT: [[TMP9:%.]] = bitcast i16 [[TMP1]] to i8*
	// CHECK1-NEXT: store i8* [[TMP9]], i8** [[TMP8]], align 8			// CHECK1-NEXT: store i8* [[TMP9]], i8** [[TMP8]], align 8
	// CHECK1-NEXT: [[TMP10:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 2			// CHECK1-NEXT: [[TMP10:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 2
	// CHECK1-NEXT: [[TMP11:%.]] = bitcast [10 x i32] [[TMP2]] to i8*			// CHECK1-NEXT: [[TMP11:%.]] = bitcast [10 x i32] [[TMP2]] to i8*
	// CHECK1-NEXT: store i8* [[TMP11]], i8** [[TMP10]], align 8			// CHECK1-NEXT: store i8* [[TMP11]], i8** [[TMP10]], align 8
	// CHECK1-NEXT: [[TMP12:%.]] = bitcast [3 x i8]* [[CAPTURED_VARS_ADDRS]] to i8**			// CHECK1-NEXT: [[TMP12:%.]] = bitcast [3 x i8]* [[CAPTURED_VARS_ADDRS]] to i8**
	// CHECK1-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 1, i32 [[TMP5]], i32 -1, i8* bitcast (void (i32, i32, i32, i16, [10 x i32]) @__omp_outlined__1 to i8), i8 null, i8** [[TMP12]], i64 3)			// CHECK1-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 1, i32 [[TMP5]], i32 -1, i8* bitcast (void (i32, i32, i32, i16, [10 x i32]) @__omp_outlined__1 to i8), i8 null, i8** [[TMP12]], i64 3)
	// CHECK1-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 true)			// CHECK1-NEXT: call void @__kmpc_target_deinit(i1 true)
	// CHECK1-NEXT: ret void			// CHECK1-NEXT: ret void
	// CHECK1: worker.exit:			// CHECK1: worker.exit:
	// CHECK1-NEXT: ret void			// CHECK1-NEXT: ret void
	//			//
	//			//
	// CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__1			// CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__1
	// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i32 nonnull align 4 dereferenceable(4) [[A:%.]], i16 nonnull align 2 dereferenceable(2) [[AA:%.]], [10 x i32] nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {			// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i32 nonnull align 4 dereferenceable(4) [[A:%.]], i16 nonnull align 2 dereferenceable(2) [[AA:%.]], [10 x i32] nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {
	// CHECK1-NEXT: entry:			// CHECK1-NEXT: entry:
	Show All 27 Lines
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l25			// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l25
	// CHECK2-SAME: (i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0:[0-9]+]] {			// CHECK2-SAME: (i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0:[0-9]+]] {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	// CHECK2-NEXT: [[AA_ADDR:%.]] = alloca i16, align 4			// CHECK2-NEXT: [[AA_ADDR:%.]] = alloca i16, align 4
	// CHECK2-NEXT: [[CAPTURED_VARS_ADDRS:%.]] = alloca [1 x i8], align 4			// CHECK2-NEXT: [[CAPTURED_VARS_ADDRS:%.]] = alloca [1 x i8], align 4
	// CHECK2-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 4			// CHECK2-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 4
	// CHECK2-NEXT: [[TMP0:%.]] = load i16, i16** [[AA_ADDR]], align 4			// CHECK2-NEXT: [[TMP0:%.]] = load i16, i16** [[AA_ADDR]], align 4
	// CHECK2-NEXT: [[TMP1:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1:[0-9]+]], i8 2, i1 false, i1 true)			// CHECK2-NEXT: [[TMP1:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l25_kernel_info, i1 true)
	// CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1			// CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
	// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]			// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
	// CHECK2: user_code.entry:			// CHECK2: user_code.entry:
	// CHECK2-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB2:[0-9]+]])			// CHECK2-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB2:[0-9]+]])
	// CHECK2-NEXT: [[TMP3:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[CAPTURED_VARS_ADDRS]], i32 0, i32 0			// CHECK2-NEXT: [[TMP3:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
	// CHECK2-NEXT: [[TMP4:%.]] = bitcast i16 [[TMP0]] to i8*			// CHECK2-NEXT: [[TMP4:%.]] = bitcast i16 [[TMP0]] to i8*
	// CHECK2-NEXT: store i8* [[TMP4]], i8** [[TMP3]], align 4			// CHECK2-NEXT: store i8* [[TMP4]], i8** [[TMP3]], align 4
	// CHECK2-NEXT: [[TMP5:%.]] = bitcast [1 x i8]* [[CAPTURED_VARS_ADDRS]] to i8**			// CHECK2-NEXT: [[TMP5:%.]] = bitcast [1 x i8]* [[CAPTURED_VARS_ADDRS]] to i8**
	// CHECK2-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32 1, i32 1024, i32 -1, i8* bitcast (void (i32, i32, i16) @__omp_outlined__ to i8), i8 null, i8** [[TMP5]], i32 1)			// CHECK2-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32 1, i32 1024, i32 -1, i8* bitcast (void (i32, i32, i16) @__omp_outlined__ to i8), i8 null, i8** [[TMP5]], i32 1)
	// CHECK2-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 true)			// CHECK2-NEXT: call void @__kmpc_target_deinit(i1 true)
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	// CHECK2: worker.exit:			// CHECK2: worker.exit:
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__			// CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__
	// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i16 nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1:[0-9]+]] {			// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i16 nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1:[0-9]+]] {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	Show All 22 Lines
	// CHECK2-NEXT: [[CAPTURED_VARS_ADDRS:%.]] = alloca [3 x i8], align 4			// CHECK2-NEXT: [[CAPTURED_VARS_ADDRS:%.]] = alloca [3 x i8], align 4
	// CHECK2-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4			// CHECK2-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4
	// CHECK2-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 4			// CHECK2-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 4
	// CHECK2-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4			// CHECK2-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
	// CHECK2-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4			// CHECK2-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
	// CHECK2-NEXT: [[TMP0:%.]] = load i32, i32** [[A_ADDR]], align 4			// CHECK2-NEXT: [[TMP0:%.]] = load i32, i32** [[A_ADDR]], align 4
	// CHECK2-NEXT: [[TMP1:%.]] = load i16, i16** [[AA_ADDR]], align 4			// CHECK2-NEXT: [[TMP1:%.]] = load i16, i16** [[AA_ADDR]], align 4
	// CHECK2-NEXT: [[TMP2:%.]] = load [10 x i32], [10 x i32]** [[B_ADDR]], align 4			// CHECK2-NEXT: [[TMP2:%.]] = load [10 x i32], [10 x i32]** [[B_ADDR]], align 4
	// CHECK2-NEXT: [[TMP3:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 2, i1 false, i1 true)			// CHECK2-NEXT: [[TMP3:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l30_kernel_info, i1 true)
	// CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP3]], -1			// CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP3]], -1
	// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]			// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
	// CHECK2: user_code.entry:			// CHECK2: user_code.entry:
	// CHECK2-NEXT: [[TMP4:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB2]])			// CHECK2-NEXT: [[TMP4:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB2]])
	// CHECK2-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTCAPTURE_EXPR__ADDR]], align 4			// CHECK2-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTCAPTURE_EXPR__ADDR]], align 4
	// CHECK2-NEXT: [[TMP6:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[CAPTURED_VARS_ADDRS]], i32 0, i32 0			// CHECK2-NEXT: [[TMP6:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
	// CHECK2-NEXT: [[TMP7:%.]] = bitcast i32 [[TMP0]] to i8*			// CHECK2-NEXT: [[TMP7:%.]] = bitcast i32 [[TMP0]] to i8*
	// CHECK2-NEXT: store i8* [[TMP7]], i8** [[TMP6]], align 4			// CHECK2-NEXT: store i8* [[TMP7]], i8** [[TMP6]], align 4
	// CHECK2-NEXT: [[TMP8:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[CAPTURED_VARS_ADDRS]], i32 0, i32 1			// CHECK2-NEXT: [[TMP8:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[CAPTURED_VARS_ADDRS]], i32 0, i32 1
	// CHECK2-NEXT: [[TMP9:%.]] = bitcast i16 [[TMP1]] to i8*			// CHECK2-NEXT: [[TMP9:%.]] = bitcast i16 [[TMP1]] to i8*
	// CHECK2-NEXT: store i8* [[TMP9]], i8** [[TMP8]], align 4			// CHECK2-NEXT: store i8* [[TMP9]], i8** [[TMP8]], align 4
	// CHECK2-NEXT: [[TMP10:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[CAPTURED_VARS_ADDRS]], i32 0, i32 2			// CHECK2-NEXT: [[TMP10:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[CAPTURED_VARS_ADDRS]], i32 0, i32 2
	// CHECK2-NEXT: [[TMP11:%.]] = bitcast [10 x i32] [[TMP2]] to i8*			// CHECK2-NEXT: [[TMP11:%.]] = bitcast [10 x i32] [[TMP2]] to i8*
	// CHECK2-NEXT: store i8* [[TMP11]], i8** [[TMP10]], align 4			// CHECK2-NEXT: store i8* [[TMP11]], i8** [[TMP10]], align 4
	// CHECK2-NEXT: [[TMP12:%.]] = bitcast [3 x i8]* [[CAPTURED_VARS_ADDRS]] to i8**			// CHECK2-NEXT: [[TMP12:%.]] = bitcast [3 x i8]* [[CAPTURED_VARS_ADDRS]] to i8**
	// CHECK2-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 1, i32 [[TMP5]], i32 -1, i8* bitcast (void (i32, i32, i32, i16, [10 x i32]) @__omp_outlined__1 to i8), i8 null, i8** [[TMP12]], i32 3)			// CHECK2-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 1, i32 [[TMP5]], i32 -1, i8* bitcast (void (i32, i32, i32, i16, [10 x i32]) @__omp_outlined__1 to i8), i8 null, i8** [[TMP12]], i32 3)
	// CHECK2-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 true)			// CHECK2-NEXT: call void @__kmpc_target_deinit(i1 true)
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	// CHECK2: worker.exit:			// CHECK2: worker.exit:
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__1			// CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__1
	// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i32 nonnull align 4 dereferenceable(4) [[A:%.]], i16 nonnull align 2 dereferenceable(2) [[AA:%.]], [10 x i32] nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {			// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i32 nonnull align 4 dereferenceable(4) [[A:%.]], i16 nonnull align 2 dereferenceable(2) [[AA:%.]], [10 x i32] nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	Show All 27 Lines
	//			//
	// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l25			// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l25
	// CHECK3-SAME: (i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0:[0-9]+]] {			// CHECK3-SAME: (i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0:[0-9]+]] {
	// CHECK3-NEXT: entry:			// CHECK3-NEXT: entry:
	// CHECK3-NEXT: [[AA_ADDR:%.]] = alloca i16, align 4			// CHECK3-NEXT: [[AA_ADDR:%.]] = alloca i16, align 4
	// CHECK3-NEXT: [[CAPTURED_VARS_ADDRS:%.]] = alloca [1 x i8], align 4			// CHECK3-NEXT: [[CAPTURED_VARS_ADDRS:%.]] = alloca [1 x i8], align 4
	// CHECK3-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 4			// CHECK3-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 4
	// CHECK3-NEXT: [[TMP0:%.]] = load i16, i16** [[AA_ADDR]], align 4			// CHECK3-NEXT: [[TMP0:%.]] = load i16, i16** [[AA_ADDR]], align 4
	// CHECK3-NEXT: [[TMP1:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1:[0-9]+]], i8 2, i1 false, i1 true)			// CHECK3-NEXT: [[TMP1:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l25_kernel_info, i1 true)
	// CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1			// CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
	// CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]			// CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
	// CHECK3: user_code.entry:			// CHECK3: user_code.entry:
	// CHECK3-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB2:[0-9]+]])			// CHECK3-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB2:[0-9]+]])
	// CHECK3-NEXT: [[TMP3:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[CAPTURED_VARS_ADDRS]], i32 0, i32 0			// CHECK3-NEXT: [[TMP3:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
	// CHECK3-NEXT: [[TMP4:%.]] = bitcast i16 [[TMP0]] to i8*			// CHECK3-NEXT: [[TMP4:%.]] = bitcast i16 [[TMP0]] to i8*
	// CHECK3-NEXT: store i8* [[TMP4]], i8** [[TMP3]], align 4			// CHECK3-NEXT: store i8* [[TMP4]], i8** [[TMP3]], align 4
	// CHECK3-NEXT: [[TMP5:%.]] = bitcast [1 x i8]* [[CAPTURED_VARS_ADDRS]] to i8**			// CHECK3-NEXT: [[TMP5:%.]] = bitcast [1 x i8]* [[CAPTURED_VARS_ADDRS]] to i8**
	// CHECK3-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32 1, i32 1024, i32 -1, i8* bitcast (void (i32, i32, i16) @__omp_outlined__ to i8), i8 null, i8** [[TMP5]], i32 1)			// CHECK3-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32 1, i32 1024, i32 -1, i8* bitcast (void (i32, i32, i16) @__omp_outlined__ to i8), i8 null, i8** [[TMP5]], i32 1)
	// CHECK3-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 true)			// CHECK3-NEXT: call void @__kmpc_target_deinit(i1 true)
	// CHECK3-NEXT: ret void			// CHECK3-NEXT: ret void
	// CHECK3: worker.exit:			// CHECK3: worker.exit:
	// CHECK3-NEXT: ret void			// CHECK3-NEXT: ret void
	//			//
	//			//
	// CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__			// CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__
	// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i16 nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1:[0-9]+]] {			// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i16 nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1:[0-9]+]] {
	// CHECK3-NEXT: entry:			// CHECK3-NEXT: entry:
	Show All 22 Lines
	// CHECK3-NEXT: [[CAPTURED_VARS_ADDRS:%.]] = alloca [3 x i8], align 4			// CHECK3-NEXT: [[CAPTURED_VARS_ADDRS:%.]] = alloca [3 x i8], align 4
	// CHECK3-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4			// CHECK3-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4
	// CHECK3-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 4			// CHECK3-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 4
	// CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4			// CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
	// CHECK3-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4			// CHECK3-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
	// CHECK3-NEXT: [[TMP0:%.]] = load i32, i32** [[A_ADDR]], align 4			// CHECK3-NEXT: [[TMP0:%.]] = load i32, i32** [[A_ADDR]], align 4
	// CHECK3-NEXT: [[TMP1:%.]] = load i16, i16** [[AA_ADDR]], align 4			// CHECK3-NEXT: [[TMP1:%.]] = load i16, i16** [[AA_ADDR]], align 4
	// CHECK3-NEXT: [[TMP2:%.]] = load [10 x i32], [10 x i32]** [[B_ADDR]], align 4			// CHECK3-NEXT: [[TMP2:%.]] = load [10 x i32], [10 x i32]** [[B_ADDR]], align 4
	// CHECK3-NEXT: [[TMP3:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 2, i1 false, i1 true)			// CHECK3-NEXT: [[TMP3:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l30_kernel_info, i1 true)
	// CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP3]], -1			// CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP3]], -1
	// CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]			// CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
	// CHECK3: user_code.entry:			// CHECK3: user_code.entry:
	// CHECK3-NEXT: [[TMP4:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB2]])			// CHECK3-NEXT: [[TMP4:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB2]])
	// CHECK3-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTCAPTURE_EXPR__ADDR]], align 4			// CHECK3-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTCAPTURE_EXPR__ADDR]], align 4
	// CHECK3-NEXT: [[TMP6:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[CAPTURED_VARS_ADDRS]], i32 0, i32 0			// CHECK3-NEXT: [[TMP6:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
	// CHECK3-NEXT: [[TMP7:%.]] = bitcast i32 [[TMP0]] to i8*			// CHECK3-NEXT: [[TMP7:%.]] = bitcast i32 [[TMP0]] to i8*
	// CHECK3-NEXT: store i8* [[TMP7]], i8** [[TMP6]], align 4			// CHECK3-NEXT: store i8* [[TMP7]], i8** [[TMP6]], align 4
	// CHECK3-NEXT: [[TMP8:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[CAPTURED_VARS_ADDRS]], i32 0, i32 1			// CHECK3-NEXT: [[TMP8:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[CAPTURED_VARS_ADDRS]], i32 0, i32 1
	// CHECK3-NEXT: [[TMP9:%.]] = bitcast i16 [[TMP1]] to i8*			// CHECK3-NEXT: [[TMP9:%.]] = bitcast i16 [[TMP1]] to i8*
	// CHECK3-NEXT: store i8* [[TMP9]], i8** [[TMP8]], align 4			// CHECK3-NEXT: store i8* [[TMP9]], i8** [[TMP8]], align 4
	// CHECK3-NEXT: [[TMP10:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[CAPTURED_VARS_ADDRS]], i32 0, i32 2			// CHECK3-NEXT: [[TMP10:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[CAPTURED_VARS_ADDRS]], i32 0, i32 2
	// CHECK3-NEXT: [[TMP11:%.]] = bitcast [10 x i32] [[TMP2]] to i8*			// CHECK3-NEXT: [[TMP11:%.]] = bitcast [10 x i32] [[TMP2]] to i8*
	// CHECK3-NEXT: store i8* [[TMP11]], i8** [[TMP10]], align 4			// CHECK3-NEXT: store i8* [[TMP11]], i8** [[TMP10]], align 4
	// CHECK3-NEXT: [[TMP12:%.]] = bitcast [3 x i8]* [[CAPTURED_VARS_ADDRS]] to i8**			// CHECK3-NEXT: [[TMP12:%.]] = bitcast [3 x i8]* [[CAPTURED_VARS_ADDRS]] to i8**
	// CHECK3-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 1, i32 [[TMP5]], i32 -1, i8* bitcast (void (i32, i32, i32, i16, [10 x i32]) @__omp_outlined__1 to i8), i8 null, i8** [[TMP12]], i32 3)			// CHECK3-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 1, i32 [[TMP5]], i32 -1, i8* bitcast (void (i32, i32, i32, i16, [10 x i32]) @__omp_outlined__1 to i8), i8 null, i8** [[TMP12]], i32 3)
	// CHECK3-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 true)			// CHECK3-NEXT: call void @__kmpc_target_deinit(i1 true)
	// CHECK3-NEXT: ret void			// CHECK3-NEXT: ret void
	// CHECK3: worker.exit:			// CHECK3: worker.exit:
	// CHECK3-NEXT: ret void			// CHECK3-NEXT: ret void
	//			//
	//			//
	// CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__1			// CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__1
	// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i32 nonnull align 4 dereferenceable(4) [[A:%.]], i16 nonnull align 2 dereferenceable(2) [[AA:%.]], [10 x i32] nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {			// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i32 nonnull align 4 dereferenceable(4) [[A:%.]], i16 nonnull align 2 dereferenceable(2) [[AA:%.]], [10 x i32] nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {
	// CHECK3-NEXT: entry:			// CHECK3-NEXT: entry:
	Show All 27 Lines
	//			//
	// CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l25			// CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l25
	// CHECK4-SAME: (i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0:[0-9]+]] {			// CHECK4-SAME: (i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0:[0-9]+]] {
	// CHECK4-NEXT: entry:			// CHECK4-NEXT: entry:
	// CHECK4-NEXT: [[AA_ADDR:%.]] = alloca i16, align 8			// CHECK4-NEXT: [[AA_ADDR:%.]] = alloca i16, align 8
	// CHECK4-NEXT: [[CAPTURED_VARS_ADDRS:%.]] = alloca [1 x i8], align 8			// CHECK4-NEXT: [[CAPTURED_VARS_ADDRS:%.]] = alloca [1 x i8], align 8
	// CHECK4-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 8			// CHECK4-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 8
	// CHECK4-NEXT: [[TMP0:%.]] = load i16, i16** [[AA_ADDR]], align 8			// CHECK4-NEXT: [[TMP0:%.]] = load i16, i16** [[AA_ADDR]], align 8
	// CHECK4-NEXT: [[TMP1:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1:[0-9]+]], i8 2, i1 false, i1 true)			// CHECK4-NEXT: [[TMP1:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l25_kernel_info, i1 true)
	// CHECK4-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1			// CHECK4-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
	// CHECK4-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]			// CHECK4-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
	// CHECK4: user_code.entry:			// CHECK4: user_code.entry:
	// CHECK4-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB2:[0-9]+]])			// CHECK4-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB2:[0-9]+]])
	// CHECK4-NEXT: [[TMP3:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 0			// CHECK4-NEXT: [[TMP3:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
	// CHECK4-NEXT: [[TMP4:%.]] = bitcast i16 [[TMP0]] to i8*			// CHECK4-NEXT: [[TMP4:%.]] = bitcast i16 [[TMP0]] to i8*
	// CHECK4-NEXT: store i8* [[TMP4]], i8** [[TMP3]], align 8			// CHECK4-NEXT: store i8* [[TMP4]], i8** [[TMP3]], align 8
	// CHECK4-NEXT: [[TMP5:%.]] = bitcast [1 x i8]* [[CAPTURED_VARS_ADDRS]] to i8**			// CHECK4-NEXT: [[TMP5:%.]] = bitcast [1 x i8]* [[CAPTURED_VARS_ADDRS]] to i8**
	// CHECK4-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32 1, i32 1024, i32 -1, i8* bitcast (void (i32, i32, i16) @__omp_outlined__ to i8), i8 null, i8** [[TMP5]], i64 1)			// CHECK4-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32 1, i32 1024, i32 -1, i8* bitcast (void (i32, i32, i16) @__omp_outlined__ to i8), i8 null, i8** [[TMP5]], i64 1)
	// CHECK4-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 true)			// CHECK4-NEXT: call void @__kmpc_target_deinit(i1 true)
	// CHECK4-NEXT: ret void			// CHECK4-NEXT: ret void
	// CHECK4: worker.exit:			// CHECK4: worker.exit:
	// CHECK4-NEXT: ret void			// CHECK4-NEXT: ret void
	//			//
	//			//
	// CHECK4-LABEL: define {{[^@]+}}@__omp_outlined__			// CHECK4-LABEL: define {{[^@]+}}@__omp_outlined__
	// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i16 nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1:[0-9]+]] {			// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i16 nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1:[0-9]+]] {
	// CHECK4-NEXT: entry:			// CHECK4-NEXT: entry:
	Show All 23 Lines
	// CHECK4-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8			// CHECK4-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
	// CHECK4-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 8			// CHECK4-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 8
	// CHECK4-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8			// CHECK4-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
	// CHECK4-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8			// CHECK4-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
	// CHECK4-NEXT: [[TMP0:%.]] = load i32, i32** [[A_ADDR]], align 8			// CHECK4-NEXT: [[TMP0:%.]] = load i32, i32** [[A_ADDR]], align 8
	// CHECK4-NEXT: [[TMP1:%.]] = load i16, i16** [[AA_ADDR]], align 8			// CHECK4-NEXT: [[TMP1:%.]] = load i16, i16** [[AA_ADDR]], align 8
	// CHECK4-NEXT: [[TMP2:%.]] = load [10 x i32], [10 x i32]** [[B_ADDR]], align 8			// CHECK4-NEXT: [[TMP2:%.]] = load [10 x i32], [10 x i32]** [[B_ADDR]], align 8
	// CHECK4-NEXT: [[CONV:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__ADDR]] to i32*			// CHECK4-NEXT: [[CONV:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__ADDR]] to i32*
	// CHECK4-NEXT: [[TMP3:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 2, i1 false, i1 true)			// CHECK4-NEXT: [[TMP3:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l30_kernel_info, i1 true)
	// CHECK4-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP3]], -1			// CHECK4-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP3]], -1
	// CHECK4-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]			// CHECK4-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
	// CHECK4: user_code.entry:			// CHECK4: user_code.entry:
	// CHECK4-NEXT: [[TMP4:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB2]])			// CHECK4-NEXT: [[TMP4:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB2]])
	// CHECK4-NEXT: [[TMP5:%.]] = load i32, i32 [[CONV]], align 4			// CHECK4-NEXT: [[TMP5:%.]] = load i32, i32 [[CONV]], align 4
	// CHECK4-NEXT: [[TMP6:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 0			// CHECK4-NEXT: [[TMP6:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
	// CHECK4-NEXT: [[TMP7:%.]] = bitcast i32 [[TMP0]] to i8*			// CHECK4-NEXT: [[TMP7:%.]] = bitcast i32 [[TMP0]] to i8*
	// CHECK4-NEXT: store i8* [[TMP7]], i8** [[TMP6]], align 8			// CHECK4-NEXT: store i8* [[TMP7]], i8** [[TMP6]], align 8
	// CHECK4-NEXT: [[TMP8:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 1			// CHECK4-NEXT: [[TMP8:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
	// CHECK4-NEXT: [[TMP9:%.]] = bitcast i16 [[TMP1]] to i8*			// CHECK4-NEXT: [[TMP9:%.]] = bitcast i16 [[TMP1]] to i8*
	// CHECK4-NEXT: store i8* [[TMP9]], i8** [[TMP8]], align 8			// CHECK4-NEXT: store i8* [[TMP9]], i8** [[TMP8]], align 8
	// CHECK4-NEXT: [[TMP10:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 2			// CHECK4-NEXT: [[TMP10:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 2
	// CHECK4-NEXT: [[TMP11:%.]] = bitcast [10 x i32] [[TMP2]] to i8*			// CHECK4-NEXT: [[TMP11:%.]] = bitcast [10 x i32] [[TMP2]] to i8*
	// CHECK4-NEXT: store i8* [[TMP11]], i8** [[TMP10]], align 8			// CHECK4-NEXT: store i8* [[TMP11]], i8** [[TMP10]], align 8
	// CHECK4-NEXT: [[TMP12:%.]] = bitcast [3 x i8]* [[CAPTURED_VARS_ADDRS]] to i8**			// CHECK4-NEXT: [[TMP12:%.]] = bitcast [3 x i8]* [[CAPTURED_VARS_ADDRS]] to i8**
	// CHECK4-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 1, i32 [[TMP5]], i32 -1, i8* bitcast (void (i32, i32, i32, i16, [10 x i32]) @__omp_outlined__1 to i8), i8 null, i8** [[TMP12]], i64 3)			// CHECK4-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 1, i32 [[TMP5]], i32 -1, i8* bitcast (void (i32, i32, i32, i16, [10 x i32]) @__omp_outlined__1 to i8), i8 null, i8** [[TMP12]], i64 3)
	// CHECK4-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 true)			// CHECK4-NEXT: call void @__kmpc_target_deinit(i1 true)
	// CHECK4-NEXT: ret void			// CHECK4-NEXT: ret void
	// CHECK4: worker.exit:			// CHECK4: worker.exit:
	// CHECK4-NEXT: ret void			// CHECK4-NEXT: ret void
	//			//
	//			//
	// CHECK4-LABEL: define {{[^@]+}}@__omp_outlined__1			// CHECK4-LABEL: define {{[^@]+}}@__omp_outlined__1
	// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i32 nonnull align 4 dereferenceable(4) [[A:%.]], i16 nonnull align 2 dereferenceable(2) [[AA:%.]], [10 x i32] nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {			// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i32 nonnull align 4 dereferenceable(4) [[A:%.]], i16 nonnull align 2 dereferenceable(2) [[AA:%.]], [10 x i32] nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {
	// CHECK4-NEXT: entry:			// CHECK4-NEXT: entry:
	Show All 27 Lines
	//			//
	// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l25			// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l25
	// CHECK5-SAME: (i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0:[0-9]+]] {			// CHECK5-SAME: (i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0:[0-9]+]] {
	// CHECK5-NEXT: entry:			// CHECK5-NEXT: entry:
	// CHECK5-NEXT: [[AA_ADDR:%.]] = alloca i16, align 4			// CHECK5-NEXT: [[AA_ADDR:%.]] = alloca i16, align 4
	// CHECK5-NEXT: [[CAPTURED_VARS_ADDRS:%.]] = alloca [1 x i8], align 4			// CHECK5-NEXT: [[CAPTURED_VARS_ADDRS:%.]] = alloca [1 x i8], align 4
	// CHECK5-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 4			// CHECK5-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 4
	// CHECK5-NEXT: [[TMP0:%.]] = load i16, i16** [[AA_ADDR]], align 4			// CHECK5-NEXT: [[TMP0:%.]] = load i16, i16** [[AA_ADDR]], align 4
	// CHECK5-NEXT: [[TMP1:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1:[0-9]+]], i8 2, i1 false, i1 true)			// CHECK5-NEXT: [[TMP1:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l25_kernel_info, i1 true)
	// CHECK5-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1			// CHECK5-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
	// CHECK5-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]			// CHECK5-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
	// CHECK5: user_code.entry:			// CHECK5: user_code.entry:
	// CHECK5-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB2:[0-9]+]])			// CHECK5-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB2:[0-9]+]])
	// CHECK5-NEXT: [[TMP3:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[CAPTURED_VARS_ADDRS]], i32 0, i32 0			// CHECK5-NEXT: [[TMP3:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
	// CHECK5-NEXT: [[TMP4:%.]] = bitcast i16 [[TMP0]] to i8*			// CHECK5-NEXT: [[TMP4:%.]] = bitcast i16 [[TMP0]] to i8*
	// CHECK5-NEXT: store i8* [[TMP4]], i8** [[TMP3]], align 4			// CHECK5-NEXT: store i8* [[TMP4]], i8** [[TMP3]], align 4
	// CHECK5-NEXT: [[TMP5:%.]] = bitcast [1 x i8]* [[CAPTURED_VARS_ADDRS]] to i8**			// CHECK5-NEXT: [[TMP5:%.]] = bitcast [1 x i8]* [[CAPTURED_VARS_ADDRS]] to i8**
	// CHECK5-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32 1, i32 1024, i32 -1, i8* bitcast (void (i32, i32, i16) @__omp_outlined__ to i8), i8 null, i8** [[TMP5]], i32 1)			// CHECK5-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32 1, i32 1024, i32 -1, i8* bitcast (void (i32, i32, i16) @__omp_outlined__ to i8), i8 null, i8** [[TMP5]], i32 1)
	// CHECK5-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 true)			// CHECK5-NEXT: call void @__kmpc_target_deinit(i1 true)
	// CHECK5-NEXT: ret void			// CHECK5-NEXT: ret void
	// CHECK5: worker.exit:			// CHECK5: worker.exit:
	// CHECK5-NEXT: ret void			// CHECK5-NEXT: ret void
	//			//
	//			//
	// CHECK5-LABEL: define {{[^@]+}}@__omp_outlined__			// CHECK5-LABEL: define {{[^@]+}}@__omp_outlined__
	// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i16 nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1:[0-9]+]] {			// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i16 nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1:[0-9]+]] {
	// CHECK5-NEXT: entry:			// CHECK5-NEXT: entry:
	Show All 22 Lines
	// CHECK5-NEXT: [[CAPTURED_VARS_ADDRS:%.]] = alloca [3 x i8], align 4			// CHECK5-NEXT: [[CAPTURED_VARS_ADDRS:%.]] = alloca [3 x i8], align 4
	// CHECK5-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4			// CHECK5-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4
	// CHECK5-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 4			// CHECK5-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 4
	// CHECK5-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4			// CHECK5-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
	// CHECK5-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4			// CHECK5-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
	// CHECK5-NEXT: [[TMP0:%.]] = load i32, i32** [[A_ADDR]], align 4			// CHECK5-NEXT: [[TMP0:%.]] = load i32, i32** [[A_ADDR]], align 4
	// CHECK5-NEXT: [[TMP1:%.]] = load i16, i16** [[AA_ADDR]], align 4			// CHECK5-NEXT: [[TMP1:%.]] = load i16, i16** [[AA_ADDR]], align 4
	// CHECK5-NEXT: [[TMP2:%.]] = load [10 x i32], [10 x i32]** [[B_ADDR]], align 4			// CHECK5-NEXT: [[TMP2:%.]] = load [10 x i32], [10 x i32]** [[B_ADDR]], align 4
	// CHECK5-NEXT: [[TMP3:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 2, i1 false, i1 true)			// CHECK5-NEXT: [[TMP3:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l30_kernel_info, i1 true)
	// CHECK5-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP3]], -1			// CHECK5-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP3]], -1
	// CHECK5-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]			// CHECK5-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
	// CHECK5: user_code.entry:			// CHECK5: user_code.entry:
	// CHECK5-NEXT: [[TMP4:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB2]])			// CHECK5-NEXT: [[TMP4:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB2]])
	// CHECK5-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTCAPTURE_EXPR__ADDR]], align 4			// CHECK5-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTCAPTURE_EXPR__ADDR]], align 4
	// CHECK5-NEXT: [[TMP6:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[CAPTURED_VARS_ADDRS]], i32 0, i32 0			// CHECK5-NEXT: [[TMP6:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
	// CHECK5-NEXT: [[TMP7:%.]] = bitcast i32 [[TMP0]] to i8*			// CHECK5-NEXT: [[TMP7:%.]] = bitcast i32 [[TMP0]] to i8*
	// CHECK5-NEXT: store i8* [[TMP7]], i8** [[TMP6]], align 4			// CHECK5-NEXT: store i8* [[TMP7]], i8** [[TMP6]], align 4
	// CHECK5-NEXT: [[TMP8:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[CAPTURED_VARS_ADDRS]], i32 0, i32 1			// CHECK5-NEXT: [[TMP8:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[CAPTURED_VARS_ADDRS]], i32 0, i32 1
	// CHECK5-NEXT: [[TMP9:%.]] = bitcast i16 [[TMP1]] to i8*			// CHECK5-NEXT: [[TMP9:%.]] = bitcast i16 [[TMP1]] to i8*
	// CHECK5-NEXT: store i8* [[TMP9]], i8** [[TMP8]], align 4			// CHECK5-NEXT: store i8* [[TMP9]], i8** [[TMP8]], align 4
	// CHECK5-NEXT: [[TMP10:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[CAPTURED_VARS_ADDRS]], i32 0, i32 2			// CHECK5-NEXT: [[TMP10:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[CAPTURED_VARS_ADDRS]], i32 0, i32 2
	// CHECK5-NEXT: [[TMP11:%.]] = bitcast [10 x i32] [[TMP2]] to i8*			// CHECK5-NEXT: [[TMP11:%.]] = bitcast [10 x i32] [[TMP2]] to i8*
	// CHECK5-NEXT: store i8* [[TMP11]], i8** [[TMP10]], align 4			// CHECK5-NEXT: store i8* [[TMP11]], i8** [[TMP10]], align 4
	// CHECK5-NEXT: [[TMP12:%.]] = bitcast [3 x i8]* [[CAPTURED_VARS_ADDRS]] to i8**			// CHECK5-NEXT: [[TMP12:%.]] = bitcast [3 x i8]* [[CAPTURED_VARS_ADDRS]] to i8**
	// CHECK5-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 1, i32 [[TMP5]], i32 -1, i8* bitcast (void (i32, i32, i32, i16, [10 x i32]) @__omp_outlined__1 to i8), i8 null, i8** [[TMP12]], i32 3)			// CHECK5-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 1, i32 [[TMP5]], i32 -1, i8* bitcast (void (i32, i32, i32, i16, [10 x i32]) @__omp_outlined__1 to i8), i8 null, i8** [[TMP12]], i32 3)
	// CHECK5-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 true)			// CHECK5-NEXT: call void @__kmpc_target_deinit(i1 true)
	// CHECK5-NEXT: ret void			// CHECK5-NEXT: ret void
	// CHECK5: worker.exit:			// CHECK5: worker.exit:
	// CHECK5-NEXT: ret void			// CHECK5-NEXT: ret void
	//			//
	//			//
	// CHECK5-LABEL: define {{[^@]+}}@__omp_outlined__1			// CHECK5-LABEL: define {{[^@]+}}@__omp_outlined__1
	// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i32 nonnull align 4 dereferenceable(4) [[A:%.]], i16 nonnull align 2 dereferenceable(2) [[AA:%.]], [10 x i32] nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {			// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i32 nonnull align 4 dereferenceable(4) [[A:%.]], i16 nonnull align 2 dereferenceable(2) [[AA:%.]], [10 x i32] nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {
	// CHECK5-NEXT: entry:			// CHECK5-NEXT: entry:
	Show All 27 Lines
	//			//
	// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l25			// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l25
	// CHECK6-SAME: (i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0:[0-9]+]] {			// CHECK6-SAME: (i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0:[0-9]+]] {
	// CHECK6-NEXT: entry:			// CHECK6-NEXT: entry:
	// CHECK6-NEXT: [[AA_ADDR:%.]] = alloca i16, align 4			// CHECK6-NEXT: [[AA_ADDR:%.]] = alloca i16, align 4
	// CHECK6-NEXT: [[CAPTURED_VARS_ADDRS:%.]] = alloca [1 x i8], align 4			// CHECK6-NEXT: [[CAPTURED_VARS_ADDRS:%.]] = alloca [1 x i8], align 4
	// CHECK6-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 4			// CHECK6-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 4
	// CHECK6-NEXT: [[TMP0:%.]] = load i16, i16** [[AA_ADDR]], align 4			// CHECK6-NEXT: [[TMP0:%.]] = load i16, i16** [[AA_ADDR]], align 4
	// CHECK6-NEXT: [[TMP1:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1:[0-9]+]], i8 2, i1 false, i1 true)			// CHECK6-NEXT: [[TMP1:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l25_kernel_info, i1 true)
	// CHECK6-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1			// CHECK6-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
	// CHECK6-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]			// CHECK6-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
	// CHECK6: user_code.entry:			// CHECK6: user_code.entry:
	// CHECK6-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB2:[0-9]+]])			// CHECK6-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB2:[0-9]+]])
	// CHECK6-NEXT: [[TMP3:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[CAPTURED_VARS_ADDRS]], i32 0, i32 0			// CHECK6-NEXT: [[TMP3:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
	// CHECK6-NEXT: [[TMP4:%.]] = bitcast i16 [[TMP0]] to i8*			// CHECK6-NEXT: [[TMP4:%.]] = bitcast i16 [[TMP0]] to i8*
	// CHECK6-NEXT: store i8* [[TMP4]], i8** [[TMP3]], align 4			// CHECK6-NEXT: store i8* [[TMP4]], i8** [[TMP3]], align 4
	// CHECK6-NEXT: [[TMP5:%.]] = bitcast [1 x i8]* [[CAPTURED_VARS_ADDRS]] to i8**			// CHECK6-NEXT: [[TMP5:%.]] = bitcast [1 x i8]* [[CAPTURED_VARS_ADDRS]] to i8**
	// CHECK6-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32 1, i32 1024, i32 -1, i8* bitcast (void (i32, i32, i16) @__omp_outlined__ to i8), i8 null, i8** [[TMP5]], i32 1)			// CHECK6-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32 1, i32 1024, i32 -1, i8* bitcast (void (i32, i32, i16) @__omp_outlined__ to i8), i8 null, i8** [[TMP5]], i32 1)
	// CHECK6-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 true)			// CHECK6-NEXT: call void @__kmpc_target_deinit(i1 true)
	// CHECK6-NEXT: ret void			// CHECK6-NEXT: ret void
	// CHECK6: worker.exit:			// CHECK6: worker.exit:
	// CHECK6-NEXT: ret void			// CHECK6-NEXT: ret void
	//			//
	//			//
	// CHECK6-LABEL: define {{[^@]+}}@__omp_outlined__			// CHECK6-LABEL: define {{[^@]+}}@__omp_outlined__
	// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i16 nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1:[0-9]+]] {			// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i16 nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1:[0-9]+]] {
	// CHECK6-NEXT: entry:			// CHECK6-NEXT: entry:
	Show All 22 Lines
	// CHECK6-NEXT: [[CAPTURED_VARS_ADDRS:%.]] = alloca [3 x i8], align 4			// CHECK6-NEXT: [[CAPTURED_VARS_ADDRS:%.]] = alloca [3 x i8], align 4
	// CHECK6-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4			// CHECK6-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4
	// CHECK6-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 4			// CHECK6-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 4
	// CHECK6-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4			// CHECK6-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
	// CHECK6-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4			// CHECK6-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
	// CHECK6-NEXT: [[TMP0:%.]] = load i32, i32** [[A_ADDR]], align 4			// CHECK6-NEXT: [[TMP0:%.]] = load i32, i32** [[A_ADDR]], align 4
	// CHECK6-NEXT: [[TMP1:%.]] = load i16, i16** [[AA_ADDR]], align 4			// CHECK6-NEXT: [[TMP1:%.]] = load i16, i16** [[AA_ADDR]], align 4
	// CHECK6-NEXT: [[TMP2:%.]] = load [10 x i32], [10 x i32]** [[B_ADDR]], align 4			// CHECK6-NEXT: [[TMP2:%.]] = load [10 x i32], [10 x i32]** [[B_ADDR]], align 4
	// CHECK6-NEXT: [[TMP3:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 2, i1 false, i1 true)			// CHECK6-NEXT: [[TMP3:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l30_kernel_info, i1 true)
	// CHECK6-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP3]], -1			// CHECK6-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP3]], -1
	// CHECK6-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]			// CHECK6-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
	// CHECK6: user_code.entry:			// CHECK6: user_code.entry:
	// CHECK6-NEXT: [[TMP4:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB2]])			// CHECK6-NEXT: [[TMP4:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB2]])
	// CHECK6-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTCAPTURE_EXPR__ADDR]], align 4			// CHECK6-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTCAPTURE_EXPR__ADDR]], align 4
	// CHECK6-NEXT: [[TMP6:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[CAPTURED_VARS_ADDRS]], i32 0, i32 0			// CHECK6-NEXT: [[TMP6:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
	// CHECK6-NEXT: [[TMP7:%.]] = bitcast i32 [[TMP0]] to i8*			// CHECK6-NEXT: [[TMP7:%.]] = bitcast i32 [[TMP0]] to i8*
	// CHECK6-NEXT: store i8* [[TMP7]], i8** [[TMP6]], align 4			// CHECK6-NEXT: store i8* [[TMP7]], i8** [[TMP6]], align 4
	// CHECK6-NEXT: [[TMP8:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[CAPTURED_VARS_ADDRS]], i32 0, i32 1			// CHECK6-NEXT: [[TMP8:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[CAPTURED_VARS_ADDRS]], i32 0, i32 1
	// CHECK6-NEXT: [[TMP9:%.]] = bitcast i16 [[TMP1]] to i8*			// CHECK6-NEXT: [[TMP9:%.]] = bitcast i16 [[TMP1]] to i8*
	// CHECK6-NEXT: store i8* [[TMP9]], i8** [[TMP8]], align 4			// CHECK6-NEXT: store i8* [[TMP9]], i8** [[TMP8]], align 4
	// CHECK6-NEXT: [[TMP10:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[CAPTURED_VARS_ADDRS]], i32 0, i32 2			// CHECK6-NEXT: [[TMP10:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[CAPTURED_VARS_ADDRS]], i32 0, i32 2
	// CHECK6-NEXT: [[TMP11:%.]] = bitcast [10 x i32] [[TMP2]] to i8*			// CHECK6-NEXT: [[TMP11:%.]] = bitcast [10 x i32] [[TMP2]] to i8*
	// CHECK6-NEXT: store i8* [[TMP11]], i8** [[TMP10]], align 4			// CHECK6-NEXT: store i8* [[TMP11]], i8** [[TMP10]], align 4
	// CHECK6-NEXT: [[TMP12:%.]] = bitcast [3 x i8]* [[CAPTURED_VARS_ADDRS]] to i8**			// CHECK6-NEXT: [[TMP12:%.]] = bitcast [3 x i8]* [[CAPTURED_VARS_ADDRS]] to i8**
	// CHECK6-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 1, i32 [[TMP5]], i32 -1, i8* bitcast (void (i32, i32, i32, i16, [10 x i32]) @__omp_outlined__1 to i8), i8 null, i8** [[TMP12]], i32 3)			// CHECK6-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 1, i32 [[TMP5]], i32 -1, i8* bitcast (void (i32, i32, i32, i16, [10 x i32]) @__omp_outlined__1 to i8), i8 null, i8** [[TMP12]], i32 3)
	// CHECK6-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 true)			// CHECK6-NEXT: call void @__kmpc_target_deinit(i1 true)
	// CHECK6-NEXT: ret void			// CHECK6-NEXT: ret void
	// CHECK6: worker.exit:			// CHECK6: worker.exit:
	// CHECK6-NEXT: ret void			// CHECK6-NEXT: ret void
	//			//
	//			//
	// CHECK6-LABEL: define {{[^@]+}}@__omp_outlined__1			// CHECK6-LABEL: define {{[^@]+}}@__omp_outlined__1
	// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i32 nonnull align 4 dereferenceable(4) [[A:%.]], i16 nonnull align 2 dereferenceable(2) [[AA:%.]], [10 x i32] nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {			// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i32 nonnull align 4 dereferenceable(4) [[A:%.]], i16 nonnull align 2 dereferenceable(2) [[AA:%.]], [10 x i32] nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {
	// CHECK6-NEXT: entry:			// CHECK6-NEXT: entry:
	Show All 27 Lines

clang/test/OpenMP/nvptx_target_parallel_reduction_codegen.cpp

Show First 20 Lines • Show All 48 Lines • ▼ Show 20 Lines	int bar(int n){

a += ftemplate<char>(n);		a += ftemplate<char>(n);

return a;		return a;
}		}

// CHECK: define {{.*}}void {{@__omp_offloading_.+template.+l27}}(		// CHECK: define {{.*}}void {{@__omp_offloading_.+template.+l27}}(
//		//
// CHECK: call i32 @__kmpc_target_init({{.*}}, i8 2, i1 false, i1 true)		// CHECK: call i32 @__kmpc_target_init({{.*}}, i1 true)
// CHECK: call void @__kmpc_target_deinit({{.*}}, i8 2, i1 true)		// CHECK: call void @__kmpc_target_deinit(i1 true)
//		//
//		//
// define internal void [[PFN]](		// define internal void [[PFN]](
// CHECK: store double {{[0\.e\+]+}}, double* [[E:%.+]], align		// CHECK: store double {{[0\.e\+]+}}, double* [[E:%.+]], align
// CHECK: [[EV:%.+]] = load double, double* [[E]], align		// CHECK: [[EV:%.+]] = load double, double* [[E]], align
// CHECK: [[ADD:%.+]] = fadd double [[EV]], 5		// CHECK: [[ADD:%.+]] = fadd double [[EV]], 5
// CHECK: store double [[ADD]], double* [[E]], align		// CHECK: store double [[ADD]], double* [[E]], align
// CHECK: [[PTR1:%.+]] = getelementptr inbounds [[RLT:.+]], [1 x i8] [[RL:%.+]], i{{32\|64}} 0, i{{32\|64}} 0		// CHECK: [[PTR1:%.+]] = getelementptr inbounds [[RLT:.+]], [1 x i8] [[RL:%.+]], i{{32\|64}} 0, i{{32\|64}} 0
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// CHECK: [[READ_CONT]]		// CHECK: [[READ_CONT]]
// CHECK: [[NEXT:%.+]] = add nsw i32 [[CNT]], 1		// CHECK: [[NEXT:%.+]] = add nsw i32 [[CNT]], 1
// CHECK: store i32 [[NEXT]], i32* [[CNT_ADDR]],		// CHECK: store i32 [[NEXT]], i32* [[CNT_ADDR]],
// CHECK: br label		// CHECK: br label
// CHECK: ret		// CHECK: ret

// CHECK: define {{.*}}void {{@__omp_offloading_.+template.+l32}}(		// CHECK: define {{.*}}void {{@__omp_offloading_.+template.+l32}}(
//		//
// CHECK: call i32 @__kmpc_target_init({{.*}}, i8 2, i1 false, i1 true)		// CHECK: call i32 @__kmpc_target_init({{.*}}, i1 true)
// CHECK: call void @__kmpc_target_deinit({{.*}}, i8 2, i1 true)		// CHECK: call void @__kmpc_target_deinit(i1 true)
//		//
//		//
// define internal void [[PFN1]](		// define internal void [[PFN1]](
// CHECK: store float {{1\.[0e\+]+}}, float* [[D:%.+]], align		// CHECK: store float {{1\.[0e\+]+}}, float* [[D:%.+]], align
// CHECK: [[C_VAL:%.+]] = load i8, i8* [[C:%.+]], align		// CHECK: [[C_VAL:%.+]] = load i8, i8* [[C:%.+]], align
// CHECK: [[CONV:%.+]] = sext i8 [[C_VAL]] to i32		// CHECK: [[CONV:%.+]] = sext i8 [[C_VAL]] to i32
// CHECK: [[XOR:%.+]] = xor i32 [[CONV]], 2		// CHECK: [[XOR:%.+]] = xor i32 [[CONV]], 2
// CHECK: [[TRUNC:%.+]] = trunc i32 [[XOR]] to i8		// CHECK: [[TRUNC:%.+]] = trunc i32 [[XOR]] to i8
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// CHECK: [[READ_ELSE]]		// CHECK: [[READ_ELSE]]
// CHECK: br label {{%?}}[[READ_CONT]]		// CHECK: br label {{%?}}[[READ_CONT]]
//		//
// CHECK: [[READ_CONT]]		// CHECK: [[READ_CONT]]
// CHECK: ret		// CHECK: ret

// CHECK: define {{.*}}void {{@__omp_offloading_.+template.+l38}}(		// CHECK: define {{.*}}void {{@__omp_offloading_.+template.+l38}}(
//		//
// CHECK: call i32 @__kmpc_target_init({{.*}}, i8 2, i1 false, i1 true)		// CHECK: call i32 @__kmpc_target_init({{.*}}, i1 true)
// CHECK: call void @__kmpc_target_deinit({{.*}}, i8 2, i1 true)		// CHECK: call void @__kmpc_target_deinit(i1 true)
//		//
//		//
// define internal void [[PFN2]](		// define internal void [[PFN2]](
// CHECK: store i32 0, i32* [[A:%.+]], align		// CHECK: store i32 0, i32* [[A:%.+]], align
// CHECK: store i16 -32768, i16* [[B:%.+]], align		// CHECK: store i16 -32768, i16* [[B:%.+]], align
// CHECK: [[A_VAL:%.+]] = load i32, i32* [[A:%.+]], align		// CHECK: [[A_VAL:%.+]] = load i32, i32* [[A:%.+]], align
// CHECK: [[OR:%.+]] = or i32 [[A_VAL]], 1		// CHECK: [[OR:%.+]] = or i32 [[A_VAL]], 1
// CHECK: store i32 [[OR]], i32* [[A]], align		// CHECK: store i32 [[OR]], i32* [[A]], align
▲ Show 20 Lines • Show All 290 Lines • Show Last 20 Lines

clang/test/OpenMP/nvptx_target_parallel_reduction_codegen_tbaa_PR46146.cpp

This file is larger than 256 KB, so syntax highlighting is disabled by default.

Show All 29 Lines	void test() {
complex_reduction<double>();		complex_reduction<double>();
}		}
#endif		#endif
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z17complex_reductionIfEvv_l16		// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z17complex_reductionIfEvv_l16
// CHECK1-SAME: () #[[ATTR0:[0-9]+]] {		// CHECK1-SAME: () #[[ATTR0:[0-9]+]] {
// CHECK1-NEXT: entry:		// CHECK1-NEXT: entry:
// CHECK1-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4		// CHECK1-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
// CHECK1-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4		// CHECK1-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
// CHECK1-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1:[0-9]+]], i8 1, i1 true, i1 true)		// CHECK1-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z17complex_reductionIfEvv_l16_kernel_info, i1 true)
// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1		// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]		// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
// CHECK1: user_code.entry:		// CHECK1: user_code.entry:
// CHECK1-NEXT: [[TMP1:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB1]])		// CHECK1-NEXT: [[TMP1:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB1:[0-9]+]])
// CHECK1-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4		// CHECK1-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
// CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTTHREADID_TEMP_]], align 4, !tbaa [[TBAA8:![0-9]+]]		// CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTTHREADID_TEMP_]], align 4, !tbaa [[TBAA8:![0-9]+]]
// CHECK1-NEXT: call void @__omp_outlined__(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]]) #[[ATTR5:[0-9]+]]		// CHECK1-NEXT: call void @__omp_outlined__(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]]) #[[ATTR5:[0-9]+]]
// CHECK1-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true)		// CHECK1-NEXT: call void @__kmpc_target_deinit(i1 true)
// CHECK1-NEXT: ret void		// CHECK1-NEXT: ret void
// CHECK1: worker.exit:		// CHECK1: worker.exit:
// CHECK1-NEXT: ret void		// CHECK1-NEXT: ret void
//		//
//		//
// CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__		// CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__
// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {		// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
// CHECK1-NEXT: entry:		// CHECK1-NEXT: entry:
// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8		// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8
// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8		// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8
// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4		// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4		// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4		// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4		// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
// CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4		// CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
// CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4		// CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
// CHECK1-NEXT: [[IB:%.*]] = alloca i32, align 4		// CHECK1-NEXT: [[IB:%.*]] = alloca i32, align 4
// CHECK1-NEXT: [[REF_TMP:%.*]] = alloca float, align 4		// CHECK1-NEXT: [[REF_TMP:%.*]] = alloca float, align 4
// CHECK1-NEXT: [[REF_TMP2:%.*]] = alloca float, align 4		// CHECK1-NEXT: [[REF_TMP2:%.*]] = alloca float, align 4
// CHECK1-NEXT: [[CAPTURED_VARS_ADDRS:%.]] = alloca [3 x i8], align 8		// CHECK1-NEXT: [[CAPTURED_VARS_ADDRS:%.]] = alloca [3 x i8], align 8
// CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8, !tbaa [[TBAA12:![0-9]+]]		// CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8, !tbaa [[TBAA12:![0-9]+]]
// CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8, !tbaa [[TBAA12]]		// CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8, !tbaa [[TBAA12]]
// CHECK1-NEXT: [[ISTART:%.]] = call align 16 i8 @__kmpc_alloc_shared(i64 4)		// CHECK1-NEXT: [[ISTART:%.]] = call i8 @__kmpc_alloc_shared(i64 4)
// CHECK1-NEXT: [[ISTART_ON_STACK:%.]] = bitcast i8 [[ISTART]] to i32*		// CHECK1-NEXT: [[ISTART_ON_STACK:%.]] = bitcast i8 [[ISTART]] to i32*
// CHECK1-NEXT: [[IEND:%.]] = call align 16 i8 @__kmpc_alloc_shared(i64 4)		// CHECK1-NEXT: [[IEND:%.]] = call i8 @__kmpc_alloc_shared(i64 4)
// CHECK1-NEXT: [[IEND_ON_STACK:%.]] = bitcast i8 [[IEND]] to i32*		// CHECK1-NEXT: [[IEND_ON_STACK:%.]] = bitcast i8 [[IEND]] to i32*
// CHECK1-NEXT: [[PARTIAL_SUM:%.]] = call align 16 i8 @__kmpc_alloc_shared(i64 8)		// CHECK1-NEXT: [[PARTIAL_SUM:%.]] = call i8 @__kmpc_alloc_shared(i64 8)
// CHECK1-NEXT: [[PARTIAL_SUM_ON_STACK:%.]] = bitcast i8 [[PARTIAL_SUM]] to %"class.std::complex"*		// CHECK1-NEXT: [[PARTIAL_SUM_ON_STACK:%.]] = bitcast i8 [[PARTIAL_SUM]] to %"class.std::complex"*
// CHECK1-NEXT: [[TMP0:%.]] = bitcast i32 [[DOTOMP_IV]] to i8*		// CHECK1-NEXT: [[TMP0:%.]] = bitcast i32 [[DOTOMP_IV]] to i8*
// CHECK1-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP0]]) #[[ATTR5]]		// CHECK1-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP0]]) #[[ATTR5]]
// CHECK1-NEXT: [[TMP1:%.]] = bitcast i32 [[DOTOMP_LB]] to i8*		// CHECK1-NEXT: [[TMP1:%.]] = bitcast i32 [[DOTOMP_LB]] to i8*
// CHECK1-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP1]]) #[[ATTR5]]		// CHECK1-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP1]]) #[[ATTR5]]
// CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4, !tbaa [[TBAA8]]		// CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4, !tbaa [[TBAA8]]
// CHECK1-NEXT: [[TMP2:%.]] = bitcast i32 [[DOTOMP_UB]] to i8*		// CHECK1-NEXT: [[TMP2:%.]] = bitcast i32 [[DOTOMP_UB]] to i8*
// CHECK1-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP2]]) #[[ATTR5]]		// CHECK1-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP2]]) #[[ATTR5]]
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// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]		// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK1-NEXT: store i32 [[ADD]], i32* [[IB]], align 4, !tbaa [[TBAA8]]		// CHECK1-NEXT: store i32 [[ADD]], i32* [[IB]], align 4, !tbaa [[TBAA8]]
// CHECK1-NEXT: [[TMP14:%.]] = bitcast float [[REF_TMP]] to i8*		// CHECK1-NEXT: [[TMP14:%.]] = bitcast float [[REF_TMP]] to i8*
// CHECK1-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP14]]) #[[ATTR5]]		// CHECK1-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP14]]) #[[ATTR5]]
// CHECK1-NEXT: store float 0.000000e+00, float* [[REF_TMP]], align 4, !tbaa [[TBAA14:![0-9]+]]		// CHECK1-NEXT: store float 0.000000e+00, float* [[REF_TMP]], align 4, !tbaa [[TBAA14:![0-9]+]]
// CHECK1-NEXT: [[TMP15:%.]] = bitcast float [[REF_TMP2]] to i8*		// CHECK1-NEXT: [[TMP15:%.]] = bitcast float [[REF_TMP2]] to i8*
// CHECK1-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP15]]) #[[ATTR5]]		// CHECK1-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP15]]) #[[ATTR5]]
// CHECK1-NEXT: store float 0.000000e+00, float* [[REF_TMP2]], align 4, !tbaa [[TBAA14]]		// CHECK1-NEXT: store float 0.000000e+00, float* [[REF_TMP2]], align 4, !tbaa [[TBAA14]]
// CHECK1-NEXT: call void @_ZNSt7complexIfEC1ERKfS2_(%"class.std::complex"* nonnull align 4 dereferenceable(8) [[PARTIAL_SUM_ON_STACK]], float* nonnull align 4 dereferenceable(4) [[REF_TMP]], float* nonnull align 4 dereferenceable(4) [[REF_TMP2]]) #[[ATTR10:[0-9]+]]		// CHECK1-NEXT: call void @_ZNSt7complexIfEC1ERKfS2_(%"class.std::complex"* nonnull align 4 dereferenceable(8) [[PARTIAL_SUM_ON_STACK]], float* nonnull align 4 dereferenceable(4) [[REF_TMP]], float* nonnull align 4 dereferenceable(4) [[REF_TMP2]]) #[[ATTR12:[0-9]+]]
// CHECK1-NEXT: [[TMP16:%.]] = bitcast float [[REF_TMP2]] to i8*		// CHECK1-NEXT: [[TMP16:%.]] = bitcast float [[REF_TMP2]] to i8*
// CHECK1-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP16]]) #[[ATTR5]]		// CHECK1-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP16]]) #[[ATTR5]]
// CHECK1-NEXT: [[TMP17:%.]] = bitcast float [[REF_TMP]] to i8*		// CHECK1-NEXT: [[TMP17:%.]] = bitcast float [[REF_TMP]] to i8*
// CHECK1-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP17]]) #[[ATTR5]]		// CHECK1-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP17]]) #[[ATTR5]]
// CHECK1-NEXT: [[TMP18:%.]] = load i32, i32 [[IB]], align 4, !tbaa [[TBAA8]]		// CHECK1-NEXT: [[TMP18:%.]] = load i32, i32 [[IB]], align 4, !tbaa [[TBAA8]]
// CHECK1-NEXT: [[MUL3:%.*]] = mul nsw i32 [[TMP18]], 4		// CHECK1-NEXT: [[MUL3:%.*]] = mul nsw i32 [[TMP18]], 4
// CHECK1-NEXT: store i32 [[MUL3]], i32* [[ISTART_ON_STACK]], align 4, !tbaa [[TBAA8]]		// CHECK1-NEXT: store i32 [[MUL3]], i32* [[ISTART_ON_STACK]], align 4, !tbaa [[TBAA8]]
// CHECK1-NEXT: [[TMP19:%.]] = load i32, i32 [[IB]], align 4, !tbaa [[TBAA8]]		// CHECK1-NEXT: [[TMP19:%.]] = load i32, i32 [[IB]], align 4, !tbaa [[TBAA8]]
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// CHECK1-NEXT: [[__RE_ADDR:%.]] = alloca float, align 8		// CHECK1-NEXT: [[__RE_ADDR:%.]] = alloca float, align 8
// CHECK1-NEXT: [[__IM_ADDR:%.]] = alloca float, align 8		// CHECK1-NEXT: [[__IM_ADDR:%.]] = alloca float, align 8
// CHECK1-NEXT: store %"class.std::complex"* [[THIS]], %"class.std::complex"** [[THIS_ADDR]], align 8, !tbaa [[TBAA12]]		// CHECK1-NEXT: store %"class.std::complex"* [[THIS]], %"class.std::complex"** [[THIS_ADDR]], align 8, !tbaa [[TBAA12]]
// CHECK1-NEXT: store float* [[__RE]], float** [[__RE_ADDR]], align 8, !tbaa [[TBAA12]]		// CHECK1-NEXT: store float* [[__RE]], float** [[__RE_ADDR]], align 8, !tbaa [[TBAA12]]
// CHECK1-NEXT: store float* [[__IM]], float** [[__IM_ADDR]], align 8, !tbaa [[TBAA12]]		// CHECK1-NEXT: store float* [[__IM]], float** [[__IM_ADDR]], align 8, !tbaa [[TBAA12]]
// CHECK1-NEXT: [[THIS1:%.]] = load %"class.std::complex", %"class.std::complex"** [[THIS_ADDR]], align 8		// CHECK1-NEXT: [[THIS1:%.]] = load %"class.std::complex", %"class.std::complex"** [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[TMP0:%.]] = load float, float** [[__RE_ADDR]], align 8		// CHECK1-NEXT: [[TMP0:%.]] = load float, float** [[__RE_ADDR]], align 8
// CHECK1-NEXT: [[TMP1:%.]] = load float, float** [[__IM_ADDR]], align 8		// CHECK1-NEXT: [[TMP1:%.]] = load float, float** [[__IM_ADDR]], align 8
// CHECK1-NEXT: call void @_ZNSt7complexIfEC2ERKfS2_(%"class.std::complex"* nonnull align 4 dereferenceable(8) [[THIS1]], float* nonnull align 4 dereferenceable(4) [[TMP0]], float* nonnull align 4 dereferenceable(4) [[TMP1]]) #[[ATTR10]]		// CHECK1-NEXT: call void @_ZNSt7complexIfEC2ERKfS2_(%"class.std::complex"* nonnull align 4 dereferenceable(8) [[THIS1]], float* nonnull align 4 dereferenceable(4) [[TMP0]], float* nonnull align 4 dereferenceable(4) [[TMP1]]) #[[ATTR12]]
// CHECK1-NEXT: ret void		// CHECK1-NEXT: ret void
//		//
//		//
// CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__1		// CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__1
// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i32 nonnull align 4 dereferenceable(4) [[ISTART:%.]], i32 nonnull align 4 dereferenceable(4) [[IEND:%.]], %"class.std::complex" nonnull align 4 dereferenceable(8) [[PARTIAL_SUM:%.*]]) #[[ATTR0]] {		// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i32 nonnull align 4 dereferenceable(4) [[ISTART:%.]], i32 nonnull align 4 dereferenceable(4) [[IEND:%.]], %"class.std::complex" nonnull align 4 dereferenceable(8) [[PARTIAL_SUM:%.*]]) #[[ATTR0]] {
// CHECK1-NEXT: entry:		// CHECK1-NEXT: entry:
// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8		// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8
// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8		// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8
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// CHECK1-NEXT: [[TMP21:%.]] = bitcast %"class.std::complex" [[PARTIAL_SUM5]] to i8*		// CHECK1-NEXT: [[TMP21:%.]] = bitcast %"class.std::complex" [[PARTIAL_SUM5]] to i8*
// CHECK1-NEXT: call void @llvm.lifetime.start.p0i8(i64 8, i8* [[TMP21]]) #[[ATTR5]]		// CHECK1-NEXT: call void @llvm.lifetime.start.p0i8(i64 8, i8* [[TMP21]]) #[[ATTR5]]
// CHECK1-NEXT: [[TMP22:%.]] = bitcast float [[REF_TMP]] to i8*		// CHECK1-NEXT: [[TMP22:%.]] = bitcast float [[REF_TMP]] to i8*
// CHECK1-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP22]]) #[[ATTR5]]		// CHECK1-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP22]]) #[[ATTR5]]
// CHECK1-NEXT: store float 0.000000e+00, float* [[REF_TMP]], align 4, !tbaa [[TBAA14]]		// CHECK1-NEXT: store float 0.000000e+00, float* [[REF_TMP]], align 4, !tbaa [[TBAA14]]
// CHECK1-NEXT: [[TMP23:%.]] = bitcast float [[REF_TMP6]] to i8*		// CHECK1-NEXT: [[TMP23:%.]] = bitcast float [[REF_TMP6]] to i8*
// CHECK1-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP23]]) #[[ATTR5]]		// CHECK1-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP23]]) #[[ATTR5]]
// CHECK1-NEXT: store float 0.000000e+00, float* [[REF_TMP6]], align 4, !tbaa [[TBAA14]]		// CHECK1-NEXT: store float 0.000000e+00, float* [[REF_TMP6]], align 4, !tbaa [[TBAA14]]
// CHECK1-NEXT: call void @_ZNSt7complexIfEC1ERKfS2_(%"class.std::complex"* nonnull align 4 dereferenceable(8) [[PARTIAL_SUM5]], float* nonnull align 4 dereferenceable(4) [[REF_TMP]], float* nonnull align 4 dereferenceable(4) [[REF_TMP6]]) #[[ATTR10]]		// CHECK1-NEXT: call void @_ZNSt7complexIfEC1ERKfS2_(%"class.std::complex"* nonnull align 4 dereferenceable(8) [[PARTIAL_SUM5]], float* nonnull align 4 dereferenceable(4) [[REF_TMP]], float* nonnull align 4 dereferenceable(4) [[REF_TMP6]]) #[[ATTR12]]
// CHECK1-NEXT: [[TMP24:%.]] = bitcast float [[REF_TMP6]] to i8*		// CHECK1-NEXT: [[TMP24:%.]] = bitcast float [[REF_TMP6]] to i8*
// CHECK1-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP24]]) #[[ATTR5]]		// CHECK1-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP24]]) #[[ATTR5]]
// CHECK1-NEXT: [[TMP25:%.]] = bitcast float [[REF_TMP]] to i8*		// CHECK1-NEXT: [[TMP25:%.]] = bitcast float [[REF_TMP]] to i8*
// CHECK1-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP25]]) #[[ATTR5]]		// CHECK1-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP25]]) #[[ATTR5]]
// CHECK1-NEXT: [[TMP26:%.]] = bitcast i32 [[I7]] to i8*		// CHECK1-NEXT: [[TMP26:%.]] = bitcast i32 [[I7]] to i8*
// CHECK1-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP26]]) #[[ATTR5]]		// CHECK1-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP26]]) #[[ATTR5]]
// CHECK1-NEXT: [[TMP27:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8		// CHECK1-NEXT: [[TMP27:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK1-NEXT: [[TMP28:%.]] = load i32, i32 [[TMP27]], align 4, !tbaa [[TBAA8]]		// CHECK1-NEXT: [[TMP28:%.]] = load i32, i32 [[TMP27]], align 4, !tbaa [[TBAA8]]
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// CHECK1-NEXT: [[TMP42:%.]] = load i32, i32 [[I7]], align 4, !tbaa [[TBAA8]]		// CHECK1-NEXT: [[TMP42:%.]] = load i32, i32 [[I7]], align 4, !tbaa [[TBAA8]]
// CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP42]] to float		// CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP42]] to float
// CHECK1-NEXT: store float [[CONV]], float* [[REF_TMP15]], align 4, !tbaa [[TBAA14]]		// CHECK1-NEXT: store float [[CONV]], float* [[REF_TMP15]], align 4, !tbaa [[TBAA14]]
// CHECK1-NEXT: [[TMP43:%.]] = bitcast float [[REF_TMP16]] to i8*		// CHECK1-NEXT: [[TMP43:%.]] = bitcast float [[REF_TMP16]] to i8*
// CHECK1-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP43]]) #[[ATTR5]]		// CHECK1-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP43]]) #[[ATTR5]]
// CHECK1-NEXT: [[TMP44:%.]] = load i32, i32 [[I7]], align 4, !tbaa [[TBAA8]]		// CHECK1-NEXT: [[TMP44:%.]] = load i32, i32 [[I7]], align 4, !tbaa [[TBAA8]]
// CHECK1-NEXT: [[CONV17:%.*]] = sitofp i32 [[TMP44]] to float		// CHECK1-NEXT: [[CONV17:%.*]] = sitofp i32 [[TMP44]] to float
// CHECK1-NEXT: store float [[CONV17]], float* [[REF_TMP16]], align 4, !tbaa [[TBAA14]]		// CHECK1-NEXT: store float [[CONV17]], float* [[REF_TMP16]], align 4, !tbaa [[TBAA14]]
// CHECK1-NEXT: call void @_ZNSt7complexIfEC1ERKfS2_(%"class.std::complex"* nonnull align 4 dereferenceable(8) [[REF_TMP14]], float* nonnull align 4 dereferenceable(4) [[REF_TMP15]], float* nonnull align 4 dereferenceable(4) [[REF_TMP16]]) #[[ATTR10]]		// CHECK1-NEXT: call void @_ZNSt7complexIfEC1ERKfS2_(%"class.std::complex"* nonnull align 4 dereferenceable(8) [[REF_TMP14]], float* nonnull align 4 dereferenceable(4) [[REF_TMP15]], float* nonnull align 4 dereferenceable(4) [[REF_TMP16]]) #[[ATTR12]]
// CHECK1-NEXT: [[CALL:%.]] = call nonnull align 4 dereferenceable(8) %"class.std::complex" @_ZNSt7complexIfEpLIfEERS0_RKS_IT_E(%"class.std::complex"* nonnull align 4 dereferenceable(8) [[PARTIAL_SUM5]], %"class.std::complex"* nonnull align 4 dereferenceable(8) [[REF_TMP14]]) #[[ATTR10]]		// CHECK1-NEXT: [[CALL:%.]] = call nonnull align 4 dereferenceable(8) %"class.std::complex" @_ZNSt7complexIfEpLIfEERS0_RKS_IT_E(%"class.std::complex"* nonnull align 4 dereferenceable(8) [[PARTIAL_SUM5]], %"class.std::complex"* nonnull align 4 dereferenceable(8) [[REF_TMP14]]) #[[ATTR12]]
// CHECK1-NEXT: [[TMP45:%.]] = bitcast float [[REF_TMP16]] to i8*		// CHECK1-NEXT: [[TMP45:%.]] = bitcast float [[REF_TMP16]] to i8*
// CHECK1-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP45]]) #[[ATTR5]]		// CHECK1-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP45]]) #[[ATTR5]]
// CHECK1-NEXT: [[TMP46:%.]] = bitcast float [[REF_TMP15]] to i8*		// CHECK1-NEXT: [[TMP46:%.]] = bitcast float [[REF_TMP15]] to i8*
// CHECK1-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP46]]) #[[ATTR5]]		// CHECK1-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP46]]) #[[ATTR5]]
// CHECK1-NEXT: [[TMP47:%.]] = bitcast %"class.std::complex" [[REF_TMP14]] to i8*		// CHECK1-NEXT: [[TMP47:%.]] = bitcast %"class.std::complex" [[REF_TMP14]] to i8*
// CHECK1-NEXT: call void @llvm.lifetime.end.p0i8(i64 8, i8* [[TMP47]]) #[[ATTR5]]		// CHECK1-NEXT: call void @llvm.lifetime.end.p0i8(i64 8, i8* [[TMP47]]) #[[ATTR5]]
// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]		// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK1: omp.body.continue:		// CHECK1: omp.body.continue:
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// CHECK1-NEXT: [[TMP57:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0		// CHECK1-NEXT: [[TMP57:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0
// CHECK1-NEXT: [[TMP58:%.]] = bitcast %"class.std::complex" [[PARTIAL_SUM5]] to i8*		// CHECK1-NEXT: [[TMP58:%.]] = bitcast %"class.std::complex" [[PARTIAL_SUM5]] to i8*
// CHECK1-NEXT: store i8* [[TMP58]], i8** [[TMP57]], align 8		// CHECK1-NEXT: store i8* [[TMP58]], i8** [[TMP57]], align 8
// CHECK1-NEXT: [[TMP59:%.]] = bitcast [1 x i8]* [[DOTOMP_REDUCTION_RED_LIST]] to i8*		// CHECK1-NEXT: [[TMP59:%.]] = bitcast [1 x i8]* [[DOTOMP_REDUCTION_RED_LIST]] to i8*
// CHECK1-NEXT: [[TMP60:%.]] = call i32 @__kmpc_nvptx_parallel_reduce_nowait_v2(%struct.ident_t @[[GLOB1]], i32 [[TMP56]], i32 1, i64 8, i8* [[TMP59]], void (i8, i16, i16, i16) @_omp_reduction_shuffle_and_reduce_func, void (i8, i32) @_omp_reduction_inter_warp_copy_func)		// CHECK1-NEXT: [[TMP60:%.]] = call i32 @__kmpc_nvptx_parallel_reduce_nowait_v2(%struct.ident_t @[[GLOB1]], i32 [[TMP56]], i32 1, i64 8, i8* [[TMP59]], void (i8, i16, i16, i16) @_omp_reduction_shuffle_and_reduce_func, void (i8, i32) @_omp_reduction_inter_warp_copy_func)
// CHECK1-NEXT: [[TMP61:%.*]] = icmp eq i32 [[TMP60]], 1		// CHECK1-NEXT: [[TMP61:%.*]] = icmp eq i32 [[TMP60]], 1
// CHECK1-NEXT: br i1 [[TMP61]], label [[DOTOMP_REDUCTION_THEN:%.]], label [[DOTOMP_REDUCTION_DONE:%.]]		// CHECK1-NEXT: br i1 [[TMP61]], label [[DOTOMP_REDUCTION_THEN:%.]], label [[DOTOMP_REDUCTION_DONE:%.]]
// CHECK1: .omp.reduction.then:		// CHECK1: .omp.reduction.then:
// CHECK1-NEXT: [[CALL21:%.]] = call nonnull align 4 dereferenceable(8) %"class.std::complex" @_ZNSt7complexIfEpLIfEERS0_RKS_IT_E(%"class.std::complex"* nonnull align 4 dereferenceable(8) [[TMP2]], %"class.std::complex"* nonnull align 4 dereferenceable(8) [[PARTIAL_SUM5]]) #[[ATTR10]]		// CHECK1-NEXT: [[CALL21:%.]] = call nonnull align 4 dereferenceable(8) %"class.std::complex" @_ZNSt7complexIfEpLIfEERS0_RKS_IT_E(%"class.std::complex"* nonnull align 4 dereferenceable(8) [[TMP2]], %"class.std::complex"* nonnull align 4 dereferenceable(8) [[PARTIAL_SUM5]]) #[[ATTR12]]
// CHECK1-NEXT: call void @__kmpc_nvptx_end_reduce_nowait(i32 [[TMP56]])		// CHECK1-NEXT: call void @__kmpc_nvptx_end_reduce_nowait(i32 [[TMP56]])
// CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DONE]]		// CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DONE]]
// CHECK1: .omp.reduction.done:		// CHECK1: .omp.reduction.done:
// CHECK1-NEXT: [[TMP62:%.]] = bitcast i32 [[I7]] to i8*		// CHECK1-NEXT: [[TMP62:%.]] = bitcast i32 [[I7]] to i8*
// CHECK1-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP62]]) #[[ATTR5]]		// CHECK1-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP62]]) #[[ATTR5]]
// CHECK1-NEXT: [[TMP63:%.]] = bitcast %"class.std::complex" [[PARTIAL_SUM5]] to i8*		// CHECK1-NEXT: [[TMP63:%.]] = bitcast %"class.std::complex" [[PARTIAL_SUM5]] to i8*
// CHECK1-NEXT: call void @llvm.lifetime.end.p0i8(i64 8, i8* [[TMP63]]) #[[ATTR5]]		// CHECK1-NEXT: call void @llvm.lifetime.end.p0i8(i64 8, i8* [[TMP63]]) #[[ATTR5]]
// CHECK1-NEXT: [[TMP64:%.]] = bitcast i32 [[DOTOMP_IS_LAST]] to i8*		// CHECK1-NEXT: [[TMP64:%.]] = bitcast i32 [[DOTOMP_IS_LAST]] to i8*
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// CHECK1-SAME: (%"class.std::complex"* nonnull align 4 dereferenceable(8) [[THIS:%.]], %"class.std::complex" nonnull align 4 dereferenceable(8) [[__C:%.*]]) #[[ATTR4:[0-9]+]] comdat align 2 {		// CHECK1-SAME: (%"class.std::complex"* nonnull align 4 dereferenceable(8) [[THIS:%.]], %"class.std::complex" nonnull align 4 dereferenceable(8) [[__C:%.*]]) #[[ATTR4:[0-9]+]] comdat align 2 {
// CHECK1-NEXT: entry:		// CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.]] = alloca %"class.std::complex", align 8		// CHECK1-NEXT: [[THIS_ADDR:%.]] = alloca %"class.std::complex", align 8
// CHECK1-NEXT: [[__C_ADDR:%.]] = alloca %"class.std::complex", align 8		// CHECK1-NEXT: [[__C_ADDR:%.]] = alloca %"class.std::complex", align 8
// CHECK1-NEXT: store %"class.std::complex"* [[THIS]], %"class.std::complex"** [[THIS_ADDR]], align 8, !tbaa [[TBAA12]]		// CHECK1-NEXT: store %"class.std::complex"* [[THIS]], %"class.std::complex"** [[THIS_ADDR]], align 8, !tbaa [[TBAA12]]
// CHECK1-NEXT: store %"class.std::complex"* [[__C]], %"class.std::complex"** [[__C_ADDR]], align 8, !tbaa [[TBAA12]]		// CHECK1-NEXT: store %"class.std::complex"* [[__C]], %"class.std::complex"** [[__C_ADDR]], align 8, !tbaa [[TBAA12]]
// CHECK1-NEXT: [[THIS1:%.]] = load %"class.std::complex", %"class.std::complex"** [[THIS_ADDR]], align 8		// CHECK1-NEXT: [[THIS1:%.]] = load %"class.std::complex", %"class.std::complex"** [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[TMP0:%.]] = load %"class.std::complex", %"class.std::complex"** [[__C_ADDR]], align 8, !tbaa [[TBAA12]]		// CHECK1-NEXT: [[TMP0:%.]] = load %"class.std::complex", %"class.std::complex"** [[__C_ADDR]], align 8, !tbaa [[TBAA12]]
// CHECK1-NEXT: [[CALL:%.]] = call float @_ZNKSt7complexIfE4realEv(%"class.std::complex" nonnull align 4 dereferenceable(8) [[TMP0]]) #[[ATTR10]]		// CHECK1-NEXT: [[CALL:%.]] = call float @_ZNKSt7complexIfE4realEv(%"class.std::complex" nonnull align 4 dereferenceable(8) [[TMP0]]) #[[ATTR12]]
// CHECK1-NEXT: [[__RE_:%.]] = getelementptr inbounds %"class.std::complex", %"class.std::complex" [[THIS1]], i32 0, i32 0		// CHECK1-NEXT: [[__RE_:%.]] = getelementptr inbounds %"class.std::complex", %"class.std::complex" [[THIS1]], i32 0, i32 0
// CHECK1-NEXT: [[TMP1:%.]] = load float, float [[__RE_]], align 4, !tbaa [[TBAA16:![0-9]+]]		// CHECK1-NEXT: [[TMP1:%.]] = load float, float [[__RE_]], align 4, !tbaa [[TBAA16:![0-9]+]]
// CHECK1-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CALL]]		// CHECK1-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CALL]]
// CHECK1-NEXT: store float [[ADD]], float* [[__RE_]], align 4, !tbaa [[TBAA16]]		// CHECK1-NEXT: store float [[ADD]], float* [[__RE_]], align 4, !tbaa [[TBAA16]]
// CHECK1-NEXT: [[TMP2:%.]] = load %"class.std::complex", %"class.std::complex"** [[__C_ADDR]], align 8, !tbaa [[TBAA12]]		// CHECK1-NEXT: [[TMP2:%.]] = load %"class.std::complex", %"class.std::complex"** [[__C_ADDR]], align 8, !tbaa [[TBAA12]]
// CHECK1-NEXT: [[CALL2:%.]] = call float @_ZNKSt7complexIfE4imagEv(%"class.std::complex" nonnull align 4 dereferenceable(8) [[TMP2]]) #[[ATTR10]]		// CHECK1-NEXT: [[CALL2:%.]] = call float @_ZNKSt7complexIfE4imagEv(%"class.std::complex" nonnull align 4 dereferenceable(8) [[TMP2]]) #[[ATTR12]]
// CHECK1-NEXT: [[__IM_:%.]] = getelementptr inbounds %"class.std::complex", %"class.std::complex" [[THIS1]], i32 0, i32 1		// CHECK1-NEXT: [[__IM_:%.]] = getelementptr inbounds %"class.std::complex", %"class.std::complex" [[THIS1]], i32 0, i32 1
// CHECK1-NEXT: [[TMP3:%.]] = load float, float [[__IM_]], align 4, !tbaa [[TBAA18:![0-9]+]]		// CHECK1-NEXT: [[TMP3:%.]] = load float, float [[__IM_]], align 4, !tbaa [[TBAA18:![0-9]+]]
// CHECK1-NEXT: [[ADD3:%.*]] = fadd float [[TMP3]], [[CALL2]]		// CHECK1-NEXT: [[ADD3:%.*]] = fadd float [[TMP3]], [[CALL2]]
// CHECK1-NEXT: store float [[ADD3]], float* [[__IM_]], align 4, !tbaa [[TBAA18]]		// CHECK1-NEXT: store float [[ADD3]], float* [[__IM_]], align 4, !tbaa [[TBAA18]]
// CHECK1-NEXT: ret %"class.std::complex"* [[THIS1]]		// CHECK1-NEXT: ret %"class.std::complex"* [[THIS1]]
//		//
//		//
// CHECK1-LABEL: define {{[^@]+}}@_omp_reduction_shuffle_and_reduce_func		// CHECK1-LABEL: define {{[^@]+}}@_omp_reduction_shuffle_and_reduce_func
Show All 18 Lines
// CHECK1-NEXT: [[TMP10:%.]] = load i8, i8** [[TMP9]], align 8		// CHECK1-NEXT: [[TMP10:%.]] = load i8, i8** [[TMP9]], align 8
// CHECK1-NEXT: [[TMP11:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST]], i64 0, i64 0		// CHECK1-NEXT: [[TMP11:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST]], i64 0, i64 0
// CHECK1-NEXT: [[TMP12:%.]] = bitcast i8 [[TMP10]] to %"class.std::complex"*		// CHECK1-NEXT: [[TMP12:%.]] = bitcast i8 [[TMP10]] to %"class.std::complex"*
// CHECK1-NEXT: [[TMP13:%.]] = getelementptr %"class.std::complex", %"class.std::complex" [[TMP12]], i64 1		// CHECK1-NEXT: [[TMP13:%.]] = getelementptr %"class.std::complex", %"class.std::complex" [[TMP12]], i64 1
// CHECK1-NEXT: [[TMP14:%.]] = bitcast %"class.std::complex" [[TMP13]] to i8*		// CHECK1-NEXT: [[TMP14:%.]] = bitcast %"class.std::complex" [[TMP13]] to i8*
// CHECK1-NEXT: [[TMP15:%.]] = bitcast %"class.std::complex" [[TMP12]] to i64*		// CHECK1-NEXT: [[TMP15:%.]] = bitcast %"class.std::complex" [[TMP12]] to i64*
// CHECK1-NEXT: [[TMP16:%.]] = bitcast %"class.std::complex" [[DOTOMP_REDUCTION_ELEMENT]] to i64*		// CHECK1-NEXT: [[TMP16:%.]] = bitcast %"class.std::complex" [[DOTOMP_REDUCTION_ELEMENT]] to i64*
// CHECK1-NEXT: [[TMP17:%.]] = load i64, i64 [[TMP15]], align 4		// CHECK1-NEXT: [[TMP17:%.]] = load i64, i64 [[TMP15]], align 4
// CHECK1-NEXT: [[TMP18:%.*]] = call i32 @__kmpc_get_warp_size()		// CHECK1-NEXT: [[NVPTX_WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size()
// CHECK1-NEXT: [[TMP19:%.*]] = trunc i32 [[TMP18]] to i16		// CHECK1-NEXT: [[TMP18:%.*]] = trunc i32 [[NVPTX_WARP_SIZE]] to i16
// CHECK1-NEXT: [[TMP20:%.*]] = call i64 @__kmpc_shuffle_int64(i64 [[TMP17]], i16 [[TMP7]], i16 [[TMP19]])		// CHECK1-NEXT: [[TMP19:%.*]] = call i64 @__kmpc_shuffle_int64(i64 [[TMP17]], i16 [[TMP7]], i16 [[TMP18]])
// CHECK1-NEXT: store i64 [[TMP20]], i64* [[TMP16]], align 4		// CHECK1-NEXT: store i64 [[TMP19]], i64* [[TMP16]], align 4
// CHECK1-NEXT: [[TMP21:%.]] = getelementptr i64, i64 [[TMP15]], i64 1		// CHECK1-NEXT: [[TMP20:%.]] = getelementptr i64, i64 [[TMP15]], i64 1
// CHECK1-NEXT: [[TMP22:%.]] = getelementptr i64, i64 [[TMP16]], i64 1		// CHECK1-NEXT: [[TMP21:%.]] = getelementptr i64, i64 [[TMP16]], i64 1
// CHECK1-NEXT: [[TMP23:%.]] = bitcast %"class.std::complex" [[DOTOMP_REDUCTION_ELEMENT]] to i8*		// CHECK1-NEXT: [[TMP22:%.]] = bitcast %"class.std::complex" [[DOTOMP_REDUCTION_ELEMENT]] to i8*
// CHECK1-NEXT: store i8* [[TMP23]], i8** [[TMP11]], align 8, !tbaa [[TBAA12]]		// CHECK1-NEXT: store i8* [[TMP22]], i8** [[TMP11]], align 8, !tbaa [[TBAA12]]
// CHECK1-NEXT: [[TMP24:%.*]] = icmp eq i16 [[TMP8]], 0		// CHECK1-NEXT: [[TMP23:%.*]] = icmp eq i16 [[TMP8]], 0
// CHECK1-NEXT: [[TMP25:%.*]] = icmp eq i16 [[TMP8]], 1		// CHECK1-NEXT: [[TMP24:%.*]] = icmp eq i16 [[TMP8]], 1
// CHECK1-NEXT: [[TMP26:%.*]] = icmp ult i16 [[TMP6]], [[TMP7]]		// CHECK1-NEXT: [[TMP25:%.*]] = icmp ult i16 [[TMP6]], [[TMP7]]
// CHECK1-NEXT: [[TMP27:%.*]] = and i1 [[TMP25]], [[TMP26]]		// CHECK1-NEXT: [[TMP26:%.*]] = and i1 [[TMP24]], [[TMP25]]
// CHECK1-NEXT: [[TMP28:%.*]] = icmp eq i16 [[TMP8]], 2		// CHECK1-NEXT: [[TMP27:%.*]] = icmp eq i16 [[TMP8]], 2
// CHECK1-NEXT: [[TMP29:%.*]] = and i16 [[TMP6]], 1		// CHECK1-NEXT: [[TMP28:%.*]] = and i16 [[TMP6]], 1
// CHECK1-NEXT: [[TMP30:%.*]] = icmp eq i16 [[TMP29]], 0		// CHECK1-NEXT: [[TMP29:%.*]] = icmp eq i16 [[TMP28]], 0
// CHECK1-NEXT: [[TMP31:%.*]] = and i1 [[TMP28]], [[TMP30]]		// CHECK1-NEXT: [[TMP30:%.*]] = and i1 [[TMP27]], [[TMP29]]
// CHECK1-NEXT: [[TMP32:%.*]] = icmp sgt i16 [[TMP7]], 0		// CHECK1-NEXT: [[TMP31:%.*]] = icmp sgt i16 [[TMP7]], 0
// CHECK1-NEXT: [[TMP33:%.*]] = and i1 [[TMP31]], [[TMP32]]		// CHECK1-NEXT: [[TMP32:%.*]] = and i1 [[TMP30]], [[TMP31]]
// CHECK1-NEXT: [[TMP34:%.*]] = or i1 [[TMP24]], [[TMP27]]		// CHECK1-NEXT: [[TMP33:%.*]] = or i1 [[TMP23]], [[TMP26]]
// CHECK1-NEXT: [[TMP35:%.*]] = or i1 [[TMP34]], [[TMP33]]		// CHECK1-NEXT: [[TMP34:%.*]] = or i1 [[TMP33]], [[TMP32]]
// CHECK1-NEXT: br i1 [[TMP35]], label [[THEN:%.]], label [[ELSE:%.]]		// CHECK1-NEXT: br i1 [[TMP34]], label [[THEN:%.]], label [[ELSE:%.]]
// CHECK1: then:		// CHECK1: then:
// CHECK1-NEXT: [[TMP36:%.]] = bitcast [1 x i8]* [[TMP5]] to i8*		// CHECK1-NEXT: [[TMP35:%.]] = bitcast [1 x i8]* [[TMP5]] to i8*
// CHECK1-NEXT: [[TMP37:%.]] = bitcast [1 x i8]* [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST]] to i8*		// CHECK1-NEXT: [[TMP36:%.]] = bitcast [1 x i8]* [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST]] to i8*
// CHECK1-NEXT: call void @"_omp$reduction$reduction_func"(i8* [[TMP36]], i8* [[TMP37]]) #[[ATTR5]]		// CHECK1-NEXT: call void @"_omp$reduction$reduction_func"(i8* [[TMP35]], i8* [[TMP36]]) #[[ATTR5]]
// CHECK1-NEXT: br label [[IFCONT:%.*]]		// CHECK1-NEXT: br label [[IFCONT:%.*]]
// CHECK1: else:		// CHECK1: else:
// CHECK1-NEXT: br label [[IFCONT]]		// CHECK1-NEXT: br label [[IFCONT]]
// CHECK1: ifcont:		// CHECK1: ifcont:
// CHECK1-NEXT: [[TMP38:%.*]] = icmp eq i16 [[TMP8]], 1		// CHECK1-NEXT: [[TMP37:%.*]] = icmp eq i16 [[TMP8]], 1
// CHECK1-NEXT: [[TMP39:%.*]] = icmp uge i16 [[TMP6]], [[TMP7]]		// CHECK1-NEXT: [[TMP38:%.*]] = icmp uge i16 [[TMP6]], [[TMP7]]
// CHECK1-NEXT: [[TMP40:%.*]] = and i1 [[TMP38]], [[TMP39]]		// CHECK1-NEXT: [[TMP39:%.*]] = and i1 [[TMP37]], [[TMP38]]
// CHECK1-NEXT: br i1 [[TMP40]], label [[THEN4:%.]], label [[ELSE5:%.]]		// CHECK1-NEXT: br i1 [[TMP39]], label [[THEN4:%.]], label [[ELSE5:%.]]
// CHECK1: then4:		// CHECK1: then4:
// CHECK1-NEXT: [[TMP41:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST]], i64 0, i64 0		// CHECK1-NEXT: [[TMP40:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST]], i64 0, i64 0
// CHECK1-NEXT: [[TMP42:%.]] = load i8, i8** [[TMP41]], align 8		// CHECK1-NEXT: [[TMP41:%.]] = load i8, i8** [[TMP40]], align 8
// CHECK1-NEXT: [[TMP43:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[TMP5]], i64 0, i64 0		// CHECK1-NEXT: [[TMP42:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[TMP5]], i64 0, i64 0
// CHECK1-NEXT: [[TMP44:%.]] = load i8, i8** [[TMP43]], align 8		// CHECK1-NEXT: [[TMP43:%.]] = load i8, i8** [[TMP42]], align 8
// CHECK1-NEXT: [[TMP45:%.]] = bitcast i8 [[TMP42]] to %"class.std::complex"*		// CHECK1-NEXT: [[TMP44:%.]] = bitcast i8 [[TMP41]] to %"class.std::complex"*
// CHECK1-NEXT: [[TMP46:%.]] = bitcast i8 [[TMP44]] to %"class.std::complex"*		// CHECK1-NEXT: [[TMP45:%.]] = bitcast i8 [[TMP43]] to %"class.std::complex"*
// CHECK1-NEXT: [[TMP47:%.]] = bitcast %"class.std::complex" [[TMP46]] to i8*		// CHECK1-NEXT: [[TMP46:%.]] = bitcast %"class.std::complex" [[TMP45]] to i8*
// CHECK1-NEXT: [[TMP48:%.]] = bitcast %"class.std::complex" [[TMP45]] to i8*		// CHECK1-NEXT: [[TMP47:%.]] = bitcast %"class.std::complex" [[TMP44]] to i8*
// CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP47]], i8* align 4 [[TMP48]], i64 8, i1 false), !tbaa.struct !21		// CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP46]], i8* align 4 [[TMP47]], i64 8, i1 false), !tbaa.struct !21
// CHECK1-NEXT: br label [[IFCONT6:%.*]]		// CHECK1-NEXT: br label [[IFCONT6:%.*]]
// CHECK1: else5:		// CHECK1: else5:
// CHECK1-NEXT: br label [[IFCONT6]]		// CHECK1-NEXT: br label [[IFCONT6]]
// CHECK1: ifcont6:		// CHECK1: ifcont6:
// CHECK1-NEXT: ret void		// CHECK1-NEXT: ret void
//		//
//		//
// CHECK1-LABEL: define {{[^@]+}}@_omp_reduction_inter_warp_copy_func		// CHECK1-LABEL: define {{[^@]+}}@_omp_reduction_inter_warp_copy_func
// CHECK1-SAME: (i8* [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR6]] {		// CHECK1-SAME: (i8* [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR6]] {
// CHECK1-NEXT: entry:		// CHECK1-NEXT: entry:
// CHECK1-NEXT: [[DOTADDR:%.]] = alloca i8, align 8		// CHECK1-NEXT: [[DOTADDR:%.]] = alloca i8, align 8
// CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4		// CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
// CHECK1-NEXT: [[DOTCNT_ADDR:%.*]] = alloca i32, align 4		// CHECK1-NEXT: [[DOTCNT_ADDR:%.*]] = alloca i32, align 4
// CHECK1-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB1]])		// CHECK1-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB1]])
// CHECK1-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8, !tbaa [[TBAA12]]		// CHECK1-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8, !tbaa [[TBAA12]]
// CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTADDR1]], align 4, !tbaa [[TBAA8]]		// CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTADDR1]], align 4, !tbaa [[TBAA8]]
// CHECK1-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block()		// CHECK1-NEXT: [[NVPTX_TID:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block()
// CHECK1-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block()		// CHECK1-NEXT: [[NVPTX_TID2:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block()
// CHECK1-NEXT: [[NVPTX_LANE_ID:%.*]] = and i32 [[TMP4]], 31		// CHECK1-NEXT: [[NVPTX_LANE_ID:%.*]] = and i32 [[NVPTX_TID2]], 31
// CHECK1-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block()		// CHECK1-NEXT: [[NVPTX_TID3:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block()
// CHECK1-NEXT: [[NVPTX_WARP_ID:%.*]] = ashr i32 [[TMP5]], 5		// CHECK1-NEXT: [[NVPTX_WARP_ID:%.*]] = ashr i32 [[NVPTX_TID3]], 5
// CHECK1-NEXT: [[TMP6:%.]] = load i8, i8** [[DOTADDR]], align 8		// CHECK1-NEXT: [[TMP3:%.]] = load i8, i8** [[DOTADDR]], align 8
// CHECK1-NEXT: [[TMP7:%.]] = bitcast i8 [[TMP6]] to [1 x i8]		// CHECK1-NEXT: [[TMP4:%.]] = bitcast i8 [[TMP3]] to [1 x i8]
// CHECK1-NEXT: store i32 0, i32* [[DOTCNT_ADDR]], align 4, !tbaa [[TBAA8]]		// CHECK1-NEXT: store i32 0, i32* [[DOTCNT_ADDR]], align 4, !tbaa [[TBAA8]]
// CHECK1-NEXT: br label [[PRECOND:%.*]]		// CHECK1-NEXT: br label [[PRECOND:%.*]]
// CHECK1: precond:		// CHECK1: precond:
// CHECK1-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTCNT_ADDR]], align 4, !tbaa [[TBAA8]]		// CHECK1-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTCNT_ADDR]], align 4, !tbaa [[TBAA8]]
// CHECK1-NEXT: [[TMP9:%.*]] = icmp ult i32 [[TMP8]], 2		// CHECK1-NEXT: [[TMP6:%.*]] = icmp ult i32 [[TMP5]], 2
// CHECK1-NEXT: br i1 [[TMP9]], label [[BODY:%.]], label [[EXIT:%.]]		// CHECK1-NEXT: br i1 [[TMP6]], label [[BODY:%.]], label [[EXIT:%.]]
// CHECK1: body:		// CHECK1: body:
// CHECK1-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB4:[0-9]+]], i32 [[TMP2]])		// CHECK1-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB4:[0-9]+]], i32 [[TMP2]])
// CHECK1-NEXT: [[WARP_MASTER:%.*]] = icmp eq i32 [[NVPTX_LANE_ID]], 0		// CHECK1-NEXT: [[WARP_MASTER:%.*]] = icmp eq i32 [[NVPTX_LANE_ID]], 0
// CHECK1-NEXT: br i1 [[WARP_MASTER]], label [[THEN:%.]], label [[ELSE:%.]]		// CHECK1-NEXT: br i1 [[WARP_MASTER]], label [[THEN:%.]], label [[ELSE:%.]]
// CHECK1: then:		// CHECK1: then:
// CHECK1-NEXT: [[TMP10:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[TMP7]], i64 0, i64 0		// CHECK1-NEXT: [[TMP7:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[TMP4]], i64 0, i64 0
// CHECK1-NEXT: [[TMP11:%.]] = load i8, i8** [[TMP10]], align 8, !tbaa [[TBAA12]]		// CHECK1-NEXT: [[TMP8:%.]] = load i8, i8** [[TMP7]], align 8, !tbaa [[TBAA12]]
// CHECK1-NEXT: [[TMP12:%.]] = bitcast i8 [[TMP11]] to i32*		// CHECK1-NEXT: [[TMP9:%.]] = bitcast i8 [[TMP8]] to i32*
// CHECK1-NEXT: [[TMP13:%.]] = getelementptr i32, i32 [[TMP12]], i32 [[TMP8]]		// CHECK1-NEXT: [[TMP10:%.]] = getelementptr i32, i32 [[TMP9]], i32 [[TMP5]]
// CHECK1-NEXT: [[TMP14:%.]] = getelementptr inbounds [32 x i32], [32 x i32] addrspace(3) @__openmp_nvptx_data_transfer_temporary_storage, i64 0, i32 [[NVPTX_WARP_ID]]		// CHECK1-NEXT: [[TMP11:%.]] = getelementptr inbounds [32 x i32], [32 x i32] addrspace(3) @__openmp_nvptx_data_transfer_temporary_storage, i64 0, i32 [[NVPTX_WARP_ID]]
// CHECK1-NEXT: [[TMP15:%.]] = load i32, i32 [[TMP13]], align 4		// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32 [[TMP10]], align 4
// CHECK1-NEXT: store volatile i32 [[TMP15]], i32 addrspace(3)* [[TMP14]], align 4		// CHECK1-NEXT: store volatile i32 [[TMP12]], i32 addrspace(3)* [[TMP11]], align 4
// CHECK1-NEXT: br label [[IFCONT:%.*]]		// CHECK1-NEXT: br label [[IFCONT:%.*]]
// CHECK1: else:		// CHECK1: else:
// CHECK1-NEXT: br label [[IFCONT]]		// CHECK1-NEXT: br label [[IFCONT]]
// CHECK1: ifcont:		// CHECK1: ifcont:
// CHECK1-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB4]], i32 [[TMP2]])		// CHECK1-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB4]], i32 [[TMP2]])
// CHECK1-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTADDR1]], align 4, !tbaa [[TBAA8]]		// CHECK1-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTADDR1]], align 4, !tbaa [[TBAA8]]
// CHECK1-NEXT: [[IS_ACTIVE_THREAD:%.*]] = icmp ult i32 [[TMP3]], [[TMP16]]		// CHECK1-NEXT: [[IS_ACTIVE_THREAD:%.*]] = icmp ult i32 [[NVPTX_TID]], [[TMP13]]
// CHECK1-NEXT: br i1 [[IS_ACTIVE_THREAD]], label [[THEN2:%.]], label [[ELSE3:%.]]		// CHECK1-NEXT: br i1 [[IS_ACTIVE_THREAD]], label [[THEN4:%.]], label [[ELSE5:%.]]
// CHECK1: then2:		// CHECK1: then2:
// CHECK1-NEXT: [[TMP17:%.]] = getelementptr inbounds [32 x i32], [32 x i32] addrspace(3) @__openmp_nvptx_data_transfer_temporary_storage, i64 0, i32 [[TMP3]]		// CHECK1-NEXT: [[TMP14:%.]] = getelementptr inbounds [32 x i32], [32 x i32] addrspace(3) @__openmp_nvptx_data_transfer_temporary_storage, i64 0, i32 [[NVPTX_TID]]
// CHECK1-NEXT: [[TMP18:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[TMP7]], i64 0, i64 0		// CHECK1-NEXT: [[TMP15:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[TMP4]], i64 0, i64 0
// CHECK1-NEXT: [[TMP19:%.]] = load i8, i8** [[TMP18]], align 8, !tbaa [[TBAA12]]		// CHECK1-NEXT: [[TMP16:%.]] = load i8, i8** [[TMP15]], align 8, !tbaa [[TBAA12]]
// CHECK1-NEXT: [[TMP20:%.]] = bitcast i8 [[TMP19]] to i32*		// CHECK1-NEXT: [[TMP17:%.]] = bitcast i8 [[TMP16]] to i32*
// CHECK1-NEXT: [[TMP21:%.]] = getelementptr i32, i32 [[TMP20]], i32 [[TMP8]]		// CHECK1-NEXT: [[TMP18:%.]] = getelementptr i32, i32 [[TMP17]], i32 [[TMP5]]
// CHECK1-NEXT: [[TMP22:%.]] = load volatile i32, i32 addrspace(3) [[TMP17]], align 4, !tbaa [[TBAA8]]		// CHECK1-NEXT: [[TMP19:%.]] = load volatile i32, i32 addrspace(3) [[TMP14]], align 4, !tbaa [[TBAA8]]
// CHECK1-NEXT: store i32 [[TMP22]], i32* [[TMP21]], align 4, !tbaa [[TBAA8]]		// CHECK1-NEXT: store i32 [[TMP19]], i32* [[TMP18]], align 4, !tbaa [[TBAA8]]
// CHECK1-NEXT: br label [[IFCONT4:%.*]]		// CHECK1-NEXT: br label [[IFCONT6:%.*]]
// CHECK1: else3:		// CHECK1: else3:
// CHECK1-NEXT: br label [[IFCONT4]]		// CHECK1-NEXT: br label [[IFCONT6]]
// CHECK1: ifcont4:		// CHECK1: ifcont4:
// CHECK1-NEXT: [[TMP23:%.*]] = add nsw i32 [[TMP8]], 1		// CHECK1-NEXT: [[TMP20:%.*]] = add nsw i32 [[TMP5]], 1
// CHECK1-NEXT: store i32 [[TMP23]], i32* [[DOTCNT_ADDR]], align 4, !tbaa [[TBAA8]]		// CHECK1-NEXT: store i32 [[TMP20]], i32* [[DOTCNT_ADDR]], align 4, !tbaa [[TBAA8]]
// CHECK1-NEXT: br label [[PRECOND]]		// CHECK1-NEXT: br label [[PRECOND]]
// CHECK1: exit:		// CHECK1: exit:
// CHECK1-NEXT: ret void		// CHECK1-NEXT: ret void
//		//
//		//
// CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__1_wrapper		// CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__1_wrapper
// CHECK1-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR6]] {		// CHECK1-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR6]] {
// CHECK1-NEXT: entry:		// CHECK1-NEXT: entry:
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// CHECK1-NEXT: ret void		// CHECK1-NEXT: ret void
//		//
//		//
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z17complex_reductionIdEvv_l16		// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z17complex_reductionIdEvv_l16
// CHECK1-SAME: () #[[ATTR0]] {		// CHECK1-SAME: () #[[ATTR0]] {
// CHECK1-NEXT: entry:		// CHECK1-NEXT: entry:
// CHECK1-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4		// CHECK1-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
// CHECK1-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4		// CHECK1-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
// CHECK1-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 1, i1 true, i1 true)		// CHECK1-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z17complex_reductionIdEvv_l16_kernel_info, i1 true)
// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1		// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]		// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
// CHECK1: user_code.entry:		// CHECK1: user_code.entry:
// CHECK1-NEXT: [[TMP1:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB1]])		// CHECK1-NEXT: [[TMP1:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB1]])
// CHECK1-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4		// CHECK1-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
// CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTTHREADID_TEMP_]], align 4, !tbaa [[TBAA8]]		// CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTTHREADID_TEMP_]], align 4, !tbaa [[TBAA8]]
// CHECK1-NEXT: call void @__omp_outlined__2(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]]) #[[ATTR5]]		// CHECK1-NEXT: call void @__omp_outlined__2(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]]) #[[ATTR5]]
// CHECK1-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true)		// CHECK1-NEXT: call void @__kmpc_target_deinit(i1 true)
// CHECK1-NEXT: ret void		// CHECK1-NEXT: ret void
// CHECK1: worker.exit:		// CHECK1: worker.exit:
// CHECK1-NEXT: ret void		// CHECK1-NEXT: ret void
//		//
//		//
// CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__2		// CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__2
// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {		// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
// CHECK1-NEXT: entry:		// CHECK1-NEXT: entry:
// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8		// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8
// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8		// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8
// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4		// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4		// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4		// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4		// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
// CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4		// CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
// CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4		// CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
// CHECK1-NEXT: [[IB:%.*]] = alloca i32, align 4		// CHECK1-NEXT: [[IB:%.*]] = alloca i32, align 4
// CHECK1-NEXT: [[REF_TMP:%.*]] = alloca double, align 8		// CHECK1-NEXT: [[REF_TMP:%.*]] = alloca double, align 8
// CHECK1-NEXT: [[REF_TMP2:%.*]] = alloca double, align 8		// CHECK1-NEXT: [[REF_TMP2:%.*]] = alloca double, align 8
// CHECK1-NEXT: [[CAPTURED_VARS_ADDRS:%.]] = alloca [3 x i8], align 8		// CHECK1-NEXT: [[CAPTURED_VARS_ADDRS:%.]] = alloca [3 x i8], align 8
// CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8, !tbaa [[TBAA12]]		// CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8, !tbaa [[TBAA12]]
// CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8, !tbaa [[TBAA12]]		// CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8, !tbaa [[TBAA12]]
// CHECK1-NEXT: [[ISTART:%.]] = call align 16 i8 @__kmpc_alloc_shared(i64 4)		// CHECK1-NEXT: [[ISTART:%.]] = call i8 @__kmpc_alloc_shared(i64 4)
// CHECK1-NEXT: [[ISTART_ON_STACK:%.]] = bitcast i8 [[ISTART]] to i32*		// CHECK1-NEXT: [[ISTART_ON_STACK:%.]] = bitcast i8 [[ISTART]] to i32*
// CHECK1-NEXT: [[IEND:%.]] = call align 16 i8 @__kmpc_alloc_shared(i64 4)		// CHECK1-NEXT: [[IEND:%.]] = call i8 @__kmpc_alloc_shared(i64 4)
// CHECK1-NEXT: [[IEND_ON_STACK:%.]] = bitcast i8 [[IEND]] to i32*		// CHECK1-NEXT: [[IEND_ON_STACK:%.]] = bitcast i8 [[IEND]] to i32*
// CHECK1-NEXT: [[PARTIAL_SUM:%.]] = call align 16 i8 @__kmpc_alloc_shared(i64 16)		// CHECK1-NEXT: [[PARTIAL_SUM:%.]] = call i8 @__kmpc_alloc_shared(i64 16)
// CHECK1-NEXT: [[PARTIAL_SUM_ON_STACK:%.]] = bitcast i8 [[PARTIAL_SUM]] to %"class.std::complex.0"*		// CHECK1-NEXT: [[PARTIAL_SUM_ON_STACK:%.]] = bitcast i8 [[PARTIAL_SUM]] to %"class.std::complex.0"*
// CHECK1-NEXT: [[TMP0:%.]] = bitcast i32 [[DOTOMP_IV]] to i8*		// CHECK1-NEXT: [[TMP0:%.]] = bitcast i32 [[DOTOMP_IV]] to i8*
// CHECK1-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP0]]) #[[ATTR5]]		// CHECK1-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP0]]) #[[ATTR5]]
// CHECK1-NEXT: [[TMP1:%.]] = bitcast i32 [[DOTOMP_LB]] to i8*		// CHECK1-NEXT: [[TMP1:%.]] = bitcast i32 [[DOTOMP_LB]] to i8*
// CHECK1-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP1]]) #[[ATTR5]]		// CHECK1-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP1]]) #[[ATTR5]]
// CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4, !tbaa [[TBAA8]]		// CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4, !tbaa [[TBAA8]]
// CHECK1-NEXT: [[TMP2:%.]] = bitcast i32 [[DOTOMP_UB]] to i8*		// CHECK1-NEXT: [[TMP2:%.]] = bitcast i32 [[DOTOMP_UB]] to i8*
// CHECK1-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP2]]) #[[ATTR5]]		// CHECK1-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP2]]) #[[ATTR5]]
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// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]		// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK1-NEXT: store i32 [[ADD]], i32* [[IB]], align 4, !tbaa [[TBAA8]]		// CHECK1-NEXT: store i32 [[ADD]], i32* [[IB]], align 4, !tbaa [[TBAA8]]
// CHECK1-NEXT: [[TMP14:%.]] = bitcast double [[REF_TMP]] to i8*		// CHECK1-NEXT: [[TMP14:%.]] = bitcast double [[REF_TMP]] to i8*
// CHECK1-NEXT: call void @llvm.lifetime.start.p0i8(i64 8, i8* [[TMP14]]) #[[ATTR5]]		// CHECK1-NEXT: call void @llvm.lifetime.start.p0i8(i64 8, i8* [[TMP14]]) #[[ATTR5]]
// CHECK1-NEXT: store double 0.000000e+00, double* [[REF_TMP]], align 8, !tbaa [[TBAA22:![0-9]+]]		// CHECK1-NEXT: store double 0.000000e+00, double* [[REF_TMP]], align 8, !tbaa [[TBAA22:![0-9]+]]
// CHECK1-NEXT: [[TMP15:%.]] = bitcast double [[REF_TMP2]] to i8*		// CHECK1-NEXT: [[TMP15:%.]] = bitcast double [[REF_TMP2]] to i8*
// CHECK1-NEXT: call void @llvm.lifetime.start.p0i8(i64 8, i8* [[TMP15]]) #[[ATTR5]]		// CHECK1-NEXT: call void @llvm.lifetime.start.p0i8(i64 8, i8* [[TMP15]]) #[[ATTR5]]
// CHECK1-NEXT: store double 0.000000e+00, double* [[REF_TMP2]], align 8, !tbaa [[TBAA22]]		// CHECK1-NEXT: store double 0.000000e+00, double* [[REF_TMP2]], align 8, !tbaa [[TBAA22]]
// CHECK1-NEXT: call void @_ZNSt7complexIdEC1ERKdS2_(%"class.std::complex.0"* nonnull align 8 dereferenceable(16) [[PARTIAL_SUM_ON_STACK]], double* nonnull align 8 dereferenceable(8) [[REF_TMP]], double* nonnull align 8 dereferenceable(8) [[REF_TMP2]]) #[[ATTR10]]		// CHECK1-NEXT: call void @_ZNSt7complexIdEC1ERKdS2_(%"class.std::complex.0"* nonnull align 8 dereferenceable(16) [[PARTIAL_SUM_ON_STACK]], double* nonnull align 8 dereferenceable(8) [[REF_TMP]], double* nonnull align 8 dereferenceable(8) [[REF_TMP2]]) #[[ATTR12]]
// CHECK1-NEXT: [[TMP16:%.]] = bitcast double [[REF_TMP2]] to i8*		// CHECK1-NEXT: [[TMP16:%.]] = bitcast double [[REF_TMP2]] to i8*
// CHECK1-NEXT: call void @llvm.lifetime.end.p0i8(i64 8, i8* [[TMP16]]) #[[ATTR5]]		// CHECK1-NEXT: call void @llvm.lifetime.end.p0i8(i64 8, i8* [[TMP16]]) #[[ATTR5]]
// CHECK1-NEXT: [[TMP17:%.]] = bitcast double [[REF_TMP]] to i8*		// CHECK1-NEXT: [[TMP17:%.]] = bitcast double [[REF_TMP]] to i8*
// CHECK1-NEXT: call void @llvm.lifetime.end.p0i8(i64 8, i8* [[TMP17]]) #[[ATTR5]]		// CHECK1-NEXT: call void @llvm.lifetime.end.p0i8(i64 8, i8* [[TMP17]]) #[[ATTR5]]
// CHECK1-NEXT: [[TMP18:%.]] = load i32, i32 [[IB]], align 4, !tbaa [[TBAA8]]		// CHECK1-NEXT: [[TMP18:%.]] = load i32, i32 [[IB]], align 4, !tbaa [[TBAA8]]
// CHECK1-NEXT: [[MUL3:%.*]] = mul nsw i32 [[TMP18]], 4		// CHECK1-NEXT: [[MUL3:%.*]] = mul nsw i32 [[TMP18]], 4
// CHECK1-NEXT: store i32 [[MUL3]], i32* [[ISTART_ON_STACK]], align 4, !tbaa [[TBAA8]]		// CHECK1-NEXT: store i32 [[MUL3]], i32* [[ISTART_ON_STACK]], align 4, !tbaa [[TBAA8]]
// CHECK1-NEXT: [[TMP19:%.]] = load i32, i32 [[IB]], align 4, !tbaa [[TBAA8]]		// CHECK1-NEXT: [[TMP19:%.]] = load i32, i32 [[IB]], align 4, !tbaa [[TBAA8]]
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// CHECK1-NEXT: [[__RE_ADDR:%.]] = alloca double, align 8		// CHECK1-NEXT: [[__RE_ADDR:%.]] = alloca double, align 8
// CHECK1-NEXT: [[__IM_ADDR:%.]] = alloca double, align 8		// CHECK1-NEXT: [[__IM_ADDR:%.]] = alloca double, align 8
// CHECK1-NEXT: store %"class.std::complex.0"* [[THIS]], %"class.std::complex.0"** [[THIS_ADDR]], align 8, !tbaa [[TBAA12]]		// CHECK1-NEXT: store %"class.std::complex.0"* [[THIS]], %"class.std::complex.0"** [[THIS_ADDR]], align 8, !tbaa [[TBAA12]]
// CHECK1-NEXT: store double* [[__RE]], double** [[__RE_ADDR]], align 8, !tbaa [[TBAA12]]		// CHECK1-NEXT: store double* [[__RE]], double** [[__RE_ADDR]], align 8, !tbaa [[TBAA12]]
// CHECK1-NEXT: store double* [[__IM]], double** [[__IM_ADDR]], align 8, !tbaa [[TBAA12]]		// CHECK1-NEXT: store double* [[__IM]], double** [[__IM_ADDR]], align 8, !tbaa [[TBAA12]]
// CHECK1-NEXT: [[THIS1:%.]] = load %"class.std::complex.0", %"class.std::complex.0"** [[THIS_ADDR]], align 8		// CHECK1-NEXT: [[THIS1:%.]] = load %"class.std::complex.0", %"class.std::complex.0"** [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[TMP0:%.]] = load double, double** [[__RE_ADDR]], align 8		// CHECK1-NEXT: [[TMP0:%.]] = load double, double** [[__RE_ADDR]], align 8
// CHECK1-NEXT: [[TMP1:%.]] = load double, double** [[__IM_ADDR]], align 8		// CHECK1-NEXT: [[TMP1:%.]] = load double, double** [[__IM_ADDR]], align 8
// CHECK1-NEXT: call void @_ZNSt7complexIdEC2ERKdS2_(%"class.std::complex.0"* nonnull align 8 dereferenceable(16) [[THIS1]], double* nonnull align 8 dereferenceable(8) [[TMP0]], double* nonnull align 8 dereferenceable(8) [[TMP1]]) #[[ATTR10]]		// CHECK1-NEXT: call void @_ZNSt7complexIdEC2ERKdS2_(%"class.std::complex.0"* nonnull align 8 dereferenceable(16) [[THIS1]], double* nonnull align 8 dereferenceable(8) [[TMP0]], double* nonnull align 8 dereferenceable(8) [[TMP1]]) #[[ATTR12]]
// CHECK1-NEXT: ret void		// CHECK1-NEXT: ret void
//		//
//		//
// CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__3		// CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__3
// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i32 nonnull align 4 dereferenceable(4) [[ISTART:%.]], i32 nonnull align 4 dereferenceable(4) [[IEND:%.]], %"class.std::complex.0" nonnull align 8 dereferenceable(16) [[PARTIAL_SUM:%.*]]) #[[ATTR0]] {		// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i32 nonnull align 4 dereferenceable(4) [[ISTART:%.]], i32 nonnull align 4 dereferenceable(4) [[IEND:%.]], %"class.std::complex.0" nonnull align 8 dereferenceable(16) [[PARTIAL_SUM:%.*]]) #[[ATTR0]] {
// CHECK1-NEXT: entry:		// CHECK1-NEXT: entry:
// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8		// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8
// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8		// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8
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// CHECK1-NEXT: [[TMP21:%.]] = bitcast %"class.std::complex.0" [[PARTIAL_SUM5]] to i8*		// CHECK1-NEXT: [[TMP21:%.]] = bitcast %"class.std::complex.0" [[PARTIAL_SUM5]] to i8*
// CHECK1-NEXT: call void @llvm.lifetime.start.p0i8(i64 16, i8* [[TMP21]]) #[[ATTR5]]		// CHECK1-NEXT: call void @llvm.lifetime.start.p0i8(i64 16, i8* [[TMP21]]) #[[ATTR5]]
// CHECK1-NEXT: [[TMP22:%.]] = bitcast double [[REF_TMP]] to i8*		// CHECK1-NEXT: [[TMP22:%.]] = bitcast double [[REF_TMP]] to i8*
// CHECK1-NEXT: call void @llvm.lifetime.start.p0i8(i64 8, i8* [[TMP22]]) #[[ATTR5]]		// CHECK1-NEXT: call void @llvm.lifetime.start.p0i8(i64 8, i8* [[TMP22]]) #[[ATTR5]]
// CHECK1-NEXT: store double 0.000000e+00, double* [[REF_TMP]], align 8, !tbaa [[TBAA22]]		// CHECK1-NEXT: store double 0.000000e+00, double* [[REF_TMP]], align 8, !tbaa [[TBAA22]]
// CHECK1-NEXT: [[TMP23:%.]] = bitcast double [[REF_TMP6]] to i8*		// CHECK1-NEXT: [[TMP23:%.]] = bitcast double [[REF_TMP6]] to i8*
// CHECK1-NEXT: call void @llvm.lifetime.start.p0i8(i64 8, i8* [[TMP23]]) #[[ATTR5]]		// CHECK1-NEXT: call void @llvm.lifetime.start.p0i8(i64 8, i8* [[TMP23]]) #[[ATTR5]]
// CHECK1-NEXT: store double 0.000000e+00, double* [[REF_TMP6]], align 8, !tbaa [[TBAA22]]		// CHECK1-NEXT: store double 0.000000e+00, double* [[REF_TMP6]], align 8, !tbaa [[TBAA22]]
// CHECK1-NEXT: call void @_ZNSt7complexIdEC1ERKdS2_(%"class.std::complex.0"* nonnull align 8 dereferenceable(16) [[PARTIAL_SUM5]], double* nonnull align 8 dereferenceable(8) [[REF_TMP]], double* nonnull align 8 dereferenceable(8) [[REF_TMP6]]) #[[ATTR10]]		// CHECK1-NEXT: call void @_ZNSt7complexIdEC1ERKdS2_(%"class.std::complex.0"* nonnull align 8 dereferenceable(16) [[PARTIAL_SUM5]], double* nonnull align 8 dereferenceable(8) [[REF_TMP]], double* nonnull align 8 dereferenceable(8) [[REF_TMP6]]) #[[ATTR12]]
// CHECK1-NEXT: [[TMP24:%.]] = bitcast double [[REF_TMP6]] to i8*		// CHECK1-NEXT: [[TMP24:%.]] = bitcast double [[REF_TMP6]] to i8*
// CHECK1-NEXT: call void @llvm.lifetime.end.p0i8(i64 8, i8* [[TMP24]]) #[[ATTR5]]		// CHECK1-NEXT: call void @llvm.lifetime.end.p0i8(i64 8, i8* [[TMP24]]) #[[ATTR5]]
// CHECK1-NEXT: [[TMP25:%.]] = bitcast double [[REF_TMP]] to i8*		// CHECK1-NEXT: [[TMP25:%.]] = bitcast double [[REF_TMP]] to i8*
// CHECK1-NEXT: call void @llvm.lifetime.end.p0i8(i64 8, i8* [[TMP25]]) #[[ATTR5]]		// CHECK1-NEXT: call void @llvm.lifetime.end.p0i8(i64 8, i8* [[TMP25]]) #[[ATTR5]]
// CHECK1-NEXT: [[TMP26:%.]] = bitcast i32 [[I7]] to i8*		// CHECK1-NEXT: [[TMP26:%.]] = bitcast i32 [[I7]] to i8*
// CHECK1-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP26]]) #[[ATTR5]]		// CHECK1-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP26]]) #[[ATTR5]]
// CHECK1-NEXT: [[TMP27:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8		// CHECK1-NEXT: [[TMP27:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK1-NEXT: [[TMP28:%.]] = load i32, i32 [[TMP27]], align 4, !tbaa [[TBAA8]]		// CHECK1-NEXT: [[TMP28:%.]] = load i32, i32 [[TMP27]], align 4, !tbaa [[TBAA8]]
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// CHECK1-NEXT: [[TMP42:%.]] = load i32, i32 [[I7]], align 4, !tbaa [[TBAA8]]		// CHECK1-NEXT: [[TMP42:%.]] = load i32, i32 [[I7]], align 4, !tbaa [[TBAA8]]
// CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP42]] to double		// CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP42]] to double
// CHECK1-NEXT: store double [[CONV]], double* [[REF_TMP15]], align 8, !tbaa [[TBAA22]]		// CHECK1-NEXT: store double [[CONV]], double* [[REF_TMP15]], align 8, !tbaa [[TBAA22]]
// CHECK1-NEXT: [[TMP43:%.]] = bitcast double [[REF_TMP16]] to i8*		// CHECK1-NEXT: [[TMP43:%.]] = bitcast double [[REF_TMP16]] to i8*
// CHECK1-NEXT: call void @llvm.lifetime.start.p0i8(i64 8, i8* [[TMP43]]) #[[ATTR5]]		// CHECK1-NEXT: call void @llvm.lifetime.start.p0i8(i64 8, i8* [[TMP43]]) #[[ATTR5]]
// CHECK1-NEXT: [[TMP44:%.]] = load i32, i32 [[I7]], align 4, !tbaa [[TBAA8]]		// CHECK1-NEXT: [[TMP44:%.]] = load i32, i32 [[I7]], align 4, !tbaa [[TBAA8]]
// CHECK1-NEXT: [[CONV17:%.*]] = sitofp i32 [[TMP44]] to double		// CHECK1-NEXT: [[CONV17:%.*]] = sitofp i32 [[TMP44]] to double
// CHECK1-NEXT: store double [[CONV17]], double* [[REF_TMP16]], align 8, !tbaa [[TBAA22]]		// CHECK1-NEXT: store double [[CONV17]], double* [[REF_TMP16]], align 8, !tbaa [[TBAA22]]
// CHECK1-NEXT: call void @_ZNSt7complexIdEC1ERKdS2_(%"class.std::complex.0"* nonnull align 8 dereferenceable(16) [[REF_TMP14]], double* nonnull align 8 dereferenceable(8) [[REF_TMP15]], double* nonnull align 8 dereferenceable(8) [[REF_TMP16]]) #[[ATTR10]]		// CHECK1-NEXT: call void @_ZNSt7complexIdEC1ERKdS2_(%"class.std::complex.0"* nonnull align 8 dereferenceable(16) [[REF_TMP14]], double* nonnull align 8 dereferenceable(8) [[REF_TMP15]], double* nonnull align 8 dereferenceable(8) [[REF_TMP16]]) #[[ATTR12]]
// CHECK1-NEXT: [[CALL:%.]] = call nonnull align 8 dereferenceable(16) %"class.std::complex.0" @_ZNSt7complexIdEpLIdEERS0_RKS_IT_E(%"class.std::complex.0"* nonnull align 8 dereferenceable(16) [[PARTIAL_SUM5]], %"class.std::complex.0"* nonnull align 8 dereferenceable(16) [[REF_TMP14]]) #[[ATTR10]]		// CHECK1-NEXT: [[CALL:%.]] = call nonnull align 8 dereferenceable(16) %"class.std::complex.0" @_ZNSt7complexIdEpLIdEERS0_RKS_IT_E(%"class.std::complex.0"* nonnull align 8 dereferenceable(16) [[PARTIAL_SUM5]], %"class.std::complex.0"* nonnull align 8 dereferenceable(16) [[REF_TMP14]]) #[[ATTR12]]
// CHECK1-NEXT: [[TMP45:%.]] = bitcast double [[REF_TMP16]] to i8*		// CHECK1-NEXT: [[TMP45:%.]] = bitcast double [[REF_TMP16]] to i8*
// CHECK1-NEXT: call void @llvm.lifetime.end.p0i8(i64 8, i8* [[TMP45]]) #[[ATTR5]]		// CHECK1-NEXT: call void @llvm.lifetime.end.p0i8(i64 8, i8* [[TMP45]]) #[[ATTR5]]
// CHECK1-NEXT: [[TMP46:%.]] = bitcast double [[REF_TMP15]] to i8*		// CHECK1-NEXT: [[TMP46:%.]] = bitcast double [[REF_TMP15]] to i8*
// CHECK1-NEXT: call void @llvm.lifetime.end.p0i8(i64 8, i8* [[TMP46]]) #[[ATTR5]]		// CHECK1-NEXT: call void @llvm.lifetime.end.p0i8(i64 8, i8* [[TMP46]]) #[[ATTR5]]
// CHECK1-NEXT: [[TMP47:%.]] = bitcast %"class.std::complex.0" [[REF_TMP14]] to i8*		// CHECK1-NEXT: [[TMP47:%.]] = bitcast %"class.std::complex.0" [[REF_TMP14]] to i8*
// CHECK1-NEXT: call void @llvm.lifetime.end.p0i8(i64 16, i8* [[TMP47]]) #[[ATTR5]]		// CHECK1-NEXT: call void @llvm.lifetime.end.p0i8(i64 16, i8* [[TMP47]]) #[[ATTR5]]
// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]		// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK1: omp.body.continue:		// CHECK1: omp.body.continue:
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// CHECK1-NEXT: [[TMP57:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0		// CHECK1-NEXT: [[TMP57:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0
// CHECK1-NEXT: [[TMP58:%.]] = bitcast %"class.std::complex.0" [[PARTIAL_SUM5]] to i8*		// CHECK1-NEXT: [[TMP58:%.]] = bitcast %"class.std::complex.0" [[PARTIAL_SUM5]] to i8*
// CHECK1-NEXT: store i8* [[TMP58]], i8** [[TMP57]], align 8		// CHECK1-NEXT: store i8* [[TMP58]], i8** [[TMP57]], align 8
// CHECK1-NEXT: [[TMP59:%.]] = bitcast [1 x i8]* [[DOTOMP_REDUCTION_RED_LIST]] to i8*		// CHECK1-NEXT: [[TMP59:%.]] = bitcast [1 x i8]* [[DOTOMP_REDUCTION_RED_LIST]] to i8*
// CHECK1-NEXT: [[TMP60:%.]] = call i32 @__kmpc_nvptx_parallel_reduce_nowait_v2(%struct.ident_t @[[GLOB1]], i32 [[TMP56]], i32 1, i64 8, i8* [[TMP59]], void (i8, i16, i16, i16) @_omp_reduction_shuffle_and_reduce_func5, void (i8, i32) @_omp_reduction_inter_warp_copy_func6)		// CHECK1-NEXT: [[TMP60:%.]] = call i32 @__kmpc_nvptx_parallel_reduce_nowait_v2(%struct.ident_t @[[GLOB1]], i32 [[TMP56]], i32 1, i64 8, i8* [[TMP59]], void (i8, i16, i16, i16) @_omp_reduction_shuffle_and_reduce_func5, void (i8, i32) @_omp_reduction_inter_warp_copy_func6)
// CHECK1-NEXT: [[TMP61:%.*]] = icmp eq i32 [[TMP60]], 1		// CHECK1-NEXT: [[TMP61:%.*]] = icmp eq i32 [[TMP60]], 1
// CHECK1-NEXT: br i1 [[TMP61]], label [[DOTOMP_REDUCTION_THEN:%.]], label [[DOTOMP_REDUCTION_DONE:%.]]		// CHECK1-NEXT: br i1 [[TMP61]], label [[DOTOMP_REDUCTION_THEN:%.]], label [[DOTOMP_REDUCTION_DONE:%.]]
// CHECK1: .omp.reduction.then:		// CHECK1: .omp.reduction.then:
// CHECK1-NEXT: [[CALL21:%.]] = call nonnull align 8 dereferenceable(16) %"class.std::complex.0" @_ZNSt7complexIdEpLIdEERS0_RKS_IT_E(%"class.std::complex.0"* nonnull align 8 dereferenceable(16) [[TMP2]], %"class.std::complex.0"* nonnull align 8 dereferenceable(16) [[PARTIAL_SUM5]]) #[[ATTR10]]		// CHECK1-NEXT: [[CALL21:%.]] = call nonnull align 8 dereferenceable(16) %"class.std::complex.0" @_ZNSt7complexIdEpLIdEERS0_RKS_IT_E(%"class.std::complex.0"* nonnull align 8 dereferenceable(16) [[TMP2]], %"class.std::complex.0"* nonnull align 8 dereferenceable(16) [[PARTIAL_SUM5]]) #[[ATTR12]]
// CHECK1-NEXT: call void @__kmpc_nvptx_end_reduce_nowait(i32 [[TMP56]])		// CHECK1-NEXT: call void @__kmpc_nvptx_end_reduce_nowait(i32 [[TMP56]])
// CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DONE]]		// CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DONE]]
// CHECK1: .omp.reduction.done:		// CHECK1: .omp.reduction.done:
// CHECK1-NEXT: [[TMP62:%.]] = bitcast i32 [[I7]] to i8*		// CHECK1-NEXT: [[TMP62:%.]] = bitcast i32 [[I7]] to i8*
// CHECK1-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP62]]) #[[ATTR5]]		// CHECK1-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP62]]) #[[ATTR5]]
// CHECK1-NEXT: [[TMP63:%.]] = bitcast %"class.std::complex.0" [[PARTIAL_SUM5]] to i8*		// CHECK1-NEXT: [[TMP63:%.]] = bitcast %"class.std::complex.0" [[PARTIAL_SUM5]] to i8*
// CHECK1-NEXT: call void @llvm.lifetime.end.p0i8(i64 16, i8* [[TMP63]]) #[[ATTR5]]		// CHECK1-NEXT: call void @llvm.lifetime.end.p0i8(i64 16, i8* [[TMP63]]) #[[ATTR5]]
// CHECK1-NEXT: [[TMP64:%.]] = bitcast i32 [[DOTOMP_IS_LAST]] to i8*		// CHECK1-NEXT: [[TMP64:%.]] = bitcast i32 [[DOTOMP_IS_LAST]] to i8*
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// CHECK1-SAME: (%"class.std::complex.0"* nonnull align 8 dereferenceable(16) [[THIS:%.]], %"class.std::complex.0" nonnull align 8 dereferenceable(16) [[__C:%.*]]) #[[ATTR4]] comdat align 2 {		// CHECK1-SAME: (%"class.std::complex.0"* nonnull align 8 dereferenceable(16) [[THIS:%.]], %"class.std::complex.0" nonnull align 8 dereferenceable(16) [[__C:%.*]]) #[[ATTR4]] comdat align 2 {
// CHECK1-NEXT: entry:		// CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.]] = alloca %"class.std::complex.0", align 8		// CHECK1-NEXT: [[THIS_ADDR:%.]] = alloca %"class.std::complex.0", align 8
// CHECK1-NEXT: [[__C_ADDR:%.]] = alloca %"class.std::complex.0", align 8		// CHECK1-NEXT: [[__C_ADDR:%.]] = alloca %"class.std::complex.0", align 8
// CHECK1-NEXT: store %"class.std::complex.0"* [[THIS]], %"class.std::complex.0"** [[THIS_ADDR]], align 8, !tbaa [[TBAA12]]		// CHECK1-NEXT: store %"class.std::complex.0"* [[THIS]], %"class.std::complex.0"** [[THIS_ADDR]], align 8, !tbaa [[TBAA12]]
// CHECK1-NEXT: store %"class.std::complex.0"* [[__C]], %"class.std::complex.0"** [[__C_ADDR]], align 8, !tbaa [[TBAA12]]		// CHECK1-NEXT: store %"class.std::complex.0"* [[__C]], %"class.std::complex.0"** [[__C_ADDR]], align 8, !tbaa [[TBAA12]]
// CHECK1-NEXT: [[THIS1:%.]] = load %"class.std::complex.0", %"class.std::complex.0"** [[THIS_ADDR]], align 8		// CHECK1-NEXT: [[THIS1:%.]] = load %"class.std::complex.0", %"class.std::complex.0"** [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[TMP0:%.]] = load %"class.std::complex.0", %"class.std::complex.0"** [[__C_ADDR]], align 8, !tbaa [[TBAA12]]		// CHECK1-NEXT: [[TMP0:%.]] = load %"class.std::complex.0", %"class.std::complex.0"** [[__C_ADDR]], align 8, !tbaa [[TBAA12]]
// CHECK1-NEXT: [[CALL:%.]] = call double @_ZNKSt7complexIdE4realEv(%"class.std::complex.0" nonnull align 8 dereferenceable(16) [[TMP0]]) #[[ATTR10]]		// CHECK1-NEXT: [[CALL:%.]] = call double @_ZNKSt7complexIdE4realEv(%"class.std::complex.0" nonnull align 8 dereferenceable(16) [[TMP0]]) #[[ATTR12]]
// CHECK1-NEXT: [[__RE_:%.]] = getelementptr inbounds %"class.std::complex.0", %"class.std::complex.0" [[THIS1]], i32 0, i32 0		// CHECK1-NEXT: [[__RE_:%.]] = getelementptr inbounds %"class.std::complex.0", %"class.std::complex.0" [[THIS1]], i32 0, i32 0
// CHECK1-NEXT: [[TMP1:%.]] = load double, double [[__RE_]], align 8, !tbaa [[TBAA24:![0-9]+]]		// CHECK1-NEXT: [[TMP1:%.]] = load double, double [[__RE_]], align 8, !tbaa [[TBAA24:![0-9]+]]
// CHECK1-NEXT: [[ADD:%.*]] = fadd double [[TMP1]], [[CALL]]		// CHECK1-NEXT: [[ADD:%.*]] = fadd double [[TMP1]], [[CALL]]
// CHECK1-NEXT: store double [[ADD]], double* [[__RE_]], align 8, !tbaa [[TBAA24]]		// CHECK1-NEXT: store double [[ADD]], double* [[__RE_]], align 8, !tbaa [[TBAA24]]
// CHECK1-NEXT: [[TMP2:%.]] = load %"class.std::complex.0", %"class.std::complex.0"** [[__C_ADDR]], align 8, !tbaa [[TBAA12]]		// CHECK1-NEXT: [[TMP2:%.]] = load %"class.std::complex.0", %"class.std::complex.0"** [[__C_ADDR]], align 8, !tbaa [[TBAA12]]
// CHECK1-NEXT: [[CALL2:%.]] = call double @_ZNKSt7complexIdE4imagEv(%"class.std::complex.0" nonnull align 8 dereferenceable(16) [[TMP2]]) #[[ATTR10]]		// CHECK1-NEXT: [[CALL2:%.]] = call double @_ZNKSt7complexIdE4imagEv(%"class.std::complex.0" nonnull align 8 dereferenceable(16) [[TMP2]]) #[[ATTR12]]
// CHECK1-NEXT: [[__IM_:%.]] = getelementptr inbounds %"class.std::complex.0", %"class.std::complex.0" [[THIS1]], i32 0, i32 1		// CHECK1-NEXT: [[__IM_:%.]] = getelementptr inbounds %"class.std::complex.0", %"class.std::complex.0" [[THIS1]], i32 0, i32 1
// CHECK1-NEXT: [[TMP3:%.]] = load double, double [[__IM_]], align 8, !tbaa [[TBAA26:![0-9]+]]		// CHECK1-NEXT: [[TMP3:%.]] = load double, double [[__IM_]], align 8, !tbaa [[TBAA26:![0-9]+]]
// CHECK1-NEXT: [[ADD3:%.*]] = fadd double [[TMP3]], [[CALL2]]		// CHECK1-NEXT: [[ADD3:%.*]] = fadd double [[TMP3]], [[CALL2]]
// CHECK1-NEXT: store double [[ADD3]], double* [[__IM_]], align 8, !tbaa [[TBAA26]]		// CHECK1-NEXT: store double [[ADD3]], double* [[__IM_]], align 8, !tbaa [[TBAA26]]
// CHECK1-NEXT: ret %"class.std::complex.0"* [[THIS1]]		// CHECK1-NEXT: ret %"class.std::complex.0"* [[THIS1]]
//		//
//		//
// CHECK1-LABEL: define {{[^@]+}}@_omp_reduction_shuffle_and_reduce_func5		// CHECK1-LABEL: define {{[^@]+}}@_omp_reduction_shuffle_and_reduce_func5
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// CHECK1-NEXT: [[TMP11:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST]], i64 0, i64 0		// CHECK1-NEXT: [[TMP11:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST]], i64 0, i64 0
// CHECK1-NEXT: [[TMP12:%.]] = bitcast i8 [[TMP10]] to %"class.std::complex.0"*		// CHECK1-NEXT: [[TMP12:%.]] = bitcast i8 [[TMP10]] to %"class.std::complex.0"*
// CHECK1-NEXT: [[TMP13:%.]] = getelementptr %"class.std::complex.0", %"class.std::complex.0" [[TMP12]], i64 1		// CHECK1-NEXT: [[TMP13:%.]] = getelementptr %"class.std::complex.0", %"class.std::complex.0" [[TMP12]], i64 1
// CHECK1-NEXT: [[TMP14:%.]] = bitcast %"class.std::complex.0" [[TMP13]] to i8*		// CHECK1-NEXT: [[TMP14:%.]] = bitcast %"class.std::complex.0" [[TMP13]] to i8*
// CHECK1-NEXT: [[TMP15:%.]] = bitcast %"class.std::complex.0" [[TMP12]] to i64*		// CHECK1-NEXT: [[TMP15:%.]] = bitcast %"class.std::complex.0" [[TMP12]] to i64*
// CHECK1-NEXT: [[TMP16:%.]] = bitcast %"class.std::complex.0" [[DOTOMP_REDUCTION_ELEMENT]] to i64*		// CHECK1-NEXT: [[TMP16:%.]] = bitcast %"class.std::complex.0" [[DOTOMP_REDUCTION_ELEMENT]] to i64*
// CHECK1-NEXT: br label [[DOTSHUFFLE_PRE_COND:%.*]]		// CHECK1-NEXT: br label [[DOTSHUFFLE_PRE_COND:%.*]]
// CHECK1: .shuffle.pre_cond:		// CHECK1: .shuffle.pre_cond:
// CHECK1-NEXT: [[TMP17:%.]] = phi i64 [ [[TMP15]], [[ENTRY:%.]] ], [ [[TMP29:%.]], [[DOTSHUFFLE_THEN:%.*]] ]		// CHECK1-NEXT: [[TMP17:%.]] = phi i64 [ [[TMP15]], [[ENTRY:%.]] ], [ [[TMP28:%.]], [[DOTSHUFFLE_THEN:%.*]] ]
// CHECK1-NEXT: [[TMP18:%.]] = phi i64 [ [[TMP16]], [[ENTRY]] ], [ [[TMP30:%.*]], [[DOTSHUFFLE_THEN]] ]		// CHECK1-NEXT: [[TMP18:%.]] = phi i64 [ [[TMP16]], [[ENTRY]] ], [ [[TMP29:%.*]], [[DOTSHUFFLE_THEN]] ]
// CHECK1-NEXT: [[TMP19:%.]] = bitcast i64 [[TMP17]] to i8*		// CHECK1-NEXT: [[TMP19:%.]] = bitcast i64 [[TMP17]] to i8*
// CHECK1-NEXT: [[TMP20:%.]] = ptrtoint i8 [[TMP14]] to i64		// CHECK1-NEXT: [[TMP20:%.]] = ptrtoint i8 [[TMP14]] to i64
// CHECK1-NEXT: [[TMP21:%.]] = ptrtoint i8 [[TMP19]] to i64		// CHECK1-NEXT: [[TMP21:%.]] = ptrtoint i8 [[TMP19]] to i64
// CHECK1-NEXT: [[TMP22:%.*]] = sub i64 [[TMP20]], [[TMP21]]		// CHECK1-NEXT: [[TMP22:%.*]] = sub i64 [[TMP20]], [[TMP21]]
// CHECK1-NEXT: [[TMP23:%.]] = sdiv exact i64 [[TMP22]], ptrtoint (i8 getelementptr (i8, i8* null, i32 1) to i64)		// CHECK1-NEXT: [[TMP23:%.]] = sdiv exact i64 [[TMP22]], ptrtoint (i8 getelementptr (i8, i8* null, i32 1) to i64)
// CHECK1-NEXT: [[TMP24:%.*]] = icmp sgt i64 [[TMP23]], 7		// CHECK1-NEXT: [[TMP24:%.*]] = icmp sgt i64 [[TMP23]], 7
// CHECK1-NEXT: br i1 [[TMP24]], label [[DOTSHUFFLE_THEN]], label [[DOTSHUFFLE_EXIT:%.*]]		// CHECK1-NEXT: br i1 [[TMP24]], label [[DOTSHUFFLE_THEN]], label [[DOTSHUFFLE_EXIT:%.*]]
// CHECK1: .shuffle.then:		// CHECK1: .shuffle.then:
// CHECK1-NEXT: [[TMP25:%.]] = load i64, i64 [[TMP17]], align 8		// CHECK1-NEXT: [[TMP25:%.]] = load i64, i64 [[TMP17]], align 8
// CHECK1-NEXT: [[TMP26:%.*]] = call i32 @__kmpc_get_warp_size()		// CHECK1-NEXT: [[NVPTX_WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size()
// CHECK1-NEXT: [[TMP27:%.*]] = trunc i32 [[TMP26]] to i16		// CHECK1-NEXT: [[TMP26:%.*]] = trunc i32 [[NVPTX_WARP_SIZE]] to i16
// CHECK1-NEXT: [[TMP28:%.*]] = call i64 @__kmpc_shuffle_int64(i64 [[TMP25]], i16 [[TMP7]], i16 [[TMP27]])		// CHECK1-NEXT: [[TMP27:%.*]] = call i64 @__kmpc_shuffle_int64(i64 [[TMP25]], i16 [[TMP7]], i16 [[TMP26]])
// CHECK1-NEXT: store i64 [[TMP28]], i64* [[TMP18]], align 8		// CHECK1-NEXT: store i64 [[TMP27]], i64* [[TMP18]], align 8
// CHECK1-NEXT: [[TMP29]] = getelementptr i64, i64* [[TMP17]], i64 1		// CHECK1-NEXT: [[TMP28]] = getelementptr i64, i64* [[TMP17]], i64 1
// CHECK1-NEXT: [[TMP30]] = getelementptr i64, i64* [[TMP18]], i64 1		// CHECK1-NEXT: [[TMP29]] = getelementptr i64, i64* [[TMP18]], i64 1
// CHECK1-NEXT: br label [[DOTSHUFFLE_PRE_COND]]		// CHECK1-NEXT: br label [[DOTSHUFFLE_PRE_COND]]
// CHECK1: .shuffle.exit:		// CHECK1: .shuffle.exit:
// CHECK1-NEXT: [[TMP31:%.]] = bitcast %"class.std::complex.0" [[DOTOMP_REDUCTION_ELEMENT]] to i8*		// CHECK1-NEXT: [[TMP30:%.]] = bitcast %"class.std::complex.0" [[DOTOMP_REDUCTION_ELEMENT]] to i8*
// CHECK1-NEXT: store i8* [[TMP31]], i8** [[TMP11]], align 8, !tbaa [[TBAA12]]		// CHECK1-NEXT: store i8* [[TMP30]], i8** [[TMP11]], align 8, !tbaa [[TBAA12]]
// CHECK1-NEXT: [[TMP32:%.*]] = icmp eq i16 [[TMP8]], 0		// CHECK1-NEXT: [[TMP31:%.*]] = icmp eq i16 [[TMP8]], 0
// CHECK1-NEXT: [[TMP33:%.*]] = icmp eq i16 [[TMP8]], 1		// CHECK1-NEXT: [[TMP32:%.*]] = icmp eq i16 [[TMP8]], 1
// CHECK1-NEXT: [[TMP34:%.*]] = icmp ult i16 [[TMP6]], [[TMP7]]		// CHECK1-NEXT: [[TMP33:%.*]] = icmp ult i16 [[TMP6]], [[TMP7]]
// CHECK1-NEXT: [[TMP35:%.*]] = and i1 [[TMP33]], [[TMP34]]		// CHECK1-NEXT: [[TMP34:%.*]] = and i1 [[TMP32]], [[TMP33]]
// CHECK1-NEXT: [[TMP36:%.*]] = icmp eq i16 [[TMP8]], 2		// CHECK1-NEXT: [[TMP35:%.*]] = icmp eq i16 [[TMP8]], 2
// CHECK1-NEXT: [[TMP37:%.*]] = and i16 [[TMP6]], 1		// CHECK1-NEXT: [[TMP36:%.*]] = and i16 [[TMP6]], 1
// CHECK1-NEXT: [[TMP38:%.*]] = icmp eq i16 [[TMP37]], 0		// CHECK1-NEXT: [[TMP37:%.*]] = icmp eq i16 [[TMP36]], 0
// CHECK1-NEXT: [[TMP39:%.*]] = and i1 [[TMP36]], [[TMP38]]		// CHECK1-NEXT: [[TMP38:%.*]] = and i1 [[TMP35]], [[TMP37]]
// CHECK1-NEXT: [[TMP40:%.*]] = icmp sgt i16 [[TMP7]], 0		// CHECK1-NEXT: [[TMP39:%.*]] = icmp sgt i16 [[TMP7]], 0
// CHECK1-NEXT: [[TMP41:%.*]] = and i1 [[TMP39]], [[TMP40]]		// CHECK1-NEXT: [[TMP40:%.*]] = and i1 [[TMP38]], [[TMP39]]
// CHECK1-NEXT: [[TMP42:%.*]] = or i1 [[TMP32]], [[TMP35]]		// CHECK1-NEXT: [[TMP41:%.*]] = or i1 [[TMP31]], [[TMP34]]
// CHECK1-NEXT: [[TMP43:%.*]] = or i1 [[TMP42]], [[TMP41]]		// CHECK1-NEXT: [[TMP42:%.*]] = or i1 [[TMP41]], [[TMP40]]
// CHECK1-NEXT: br i1 [[TMP43]], label [[THEN:%.]], label [[ELSE:%.]]		// CHECK1-NEXT: br i1 [[TMP42]], label [[THEN:%.]], label [[ELSE:%.]]
// CHECK1: then:		// CHECK1: then:
// CHECK1-NEXT: [[TMP44:%.]] = bitcast [1 x i8]* [[TMP5]] to i8*		// CHECK1-NEXT: [[TMP43:%.]] = bitcast [1 x i8]* [[TMP5]] to i8*
// CHECK1-NEXT: [[TMP45:%.]] = bitcast [1 x i8]* [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST]] to i8*		// CHECK1-NEXT: [[TMP44:%.]] = bitcast [1 x i8]* [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST]] to i8*
// CHECK1-NEXT: call void @"_omp$reduction$reduction_func4"(i8* [[TMP44]], i8* [[TMP45]]) #[[ATTR5]]		// CHECK1-NEXT: call void @"_omp$reduction$reduction_func4"(i8* [[TMP43]], i8* [[TMP44]]) #[[ATTR5]]
// CHECK1-NEXT: br label [[IFCONT:%.*]]		// CHECK1-NEXT: br label [[IFCONT:%.*]]
// CHECK1: else:		// CHECK1: else:
// CHECK1-NEXT: br label [[IFCONT]]		// CHECK1-NEXT: br label [[IFCONT]]
// CHECK1: ifcont:		// CHECK1: ifcont:
// CHECK1-NEXT: [[TMP46:%.*]] = icmp eq i16 [[TMP8]], 1		// CHECK1-NEXT: [[TMP45:%.*]] = icmp eq i16 [[TMP8]], 1
// CHECK1-NEXT: [[TMP47:%.*]] = icmp uge i16 [[TMP6]], [[TMP7]]		// CHECK1-NEXT: [[TMP46:%.*]] = icmp uge i16 [[TMP6]], [[TMP7]]
// CHECK1-NEXT: [[TMP48:%.*]] = and i1 [[TMP46]], [[TMP47]]		// CHECK1-NEXT: [[TMP47:%.*]] = and i1 [[TMP45]], [[TMP46]]
// CHECK1-NEXT: br i1 [[TMP48]], label [[THEN4:%.]], label [[ELSE5:%.]]		// CHECK1-NEXT: br i1 [[TMP47]], label [[THEN4:%.]], label [[ELSE5:%.]]
// CHECK1: then4:		// CHECK1: then4:
// CHECK1-NEXT: [[TMP49:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST]], i64 0, i64 0		// CHECK1-NEXT: [[TMP48:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST]], i64 0, i64 0
// CHECK1-NEXT: [[TMP50:%.]] = load i8, i8** [[TMP49]], align 8		// CHECK1-NEXT: [[TMP49:%.]] = load i8, i8** [[TMP48]], align 8
// CHECK1-NEXT: [[TMP51:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[TMP5]], i64 0, i64 0		// CHECK1-NEXT: [[TMP50:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[TMP5]], i64 0, i64 0
// CHECK1-NEXT: [[TMP52:%.]] = load i8, i8** [[TMP51]], align 8		// CHECK1-NEXT: [[TMP51:%.]] = load i8, i8** [[TMP50]], align 8
// CHECK1-NEXT: [[TMP53:%.]] = bitcast i8 [[TMP50]] to %"class.std::complex.0"*		// CHECK1-NEXT: [[TMP52:%.]] = bitcast i8 [[TMP49]] to %"class.std::complex.0"*
// CHECK1-NEXT: [[TMP54:%.]] = bitcast i8 [[TMP52]] to %"class.std::complex.0"*		// CHECK1-NEXT: [[TMP53:%.]] = bitcast i8 [[TMP51]] to %"class.std::complex.0"*
// CHECK1-NEXT: [[TMP55:%.]] = bitcast %"class.std::complex.0" [[TMP54]] to i8*		// CHECK1-NEXT: [[TMP54:%.]] = bitcast %"class.std::complex.0" [[TMP53]] to i8*
// CHECK1-NEXT: [[TMP56:%.]] = bitcast %"class.std::complex.0" [[TMP53]] to i8*		// CHECK1-NEXT: [[TMP55:%.]] = bitcast %"class.std::complex.0" [[TMP52]] to i8*
// CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP55]], i8* align 8 [[TMP56]], i64 16, i1 false), !tbaa.struct !27		// CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP54]], i8* align 8 [[TMP55]], i64 16, i1 false), !tbaa.struct !27
// CHECK1-NEXT: br label [[IFCONT6:%.*]]		// CHECK1-NEXT: br label [[IFCONT6:%.*]]
// CHECK1: else5:		// CHECK1: else5:
// CHECK1-NEXT: br label [[IFCONT6]]		// CHECK1-NEXT: br label [[IFCONT6]]
// CHECK1: ifcont6:		// CHECK1: ifcont6:
// CHECK1-NEXT: ret void		// CHECK1-NEXT: ret void
//		//
//		//
// CHECK1-LABEL: define {{[^@]+}}@_omp_reduction_inter_warp_copy_func6		// CHECK1-LABEL: define {{[^@]+}}@_omp_reduction_inter_warp_copy_func6
// CHECK1-SAME: (i8* [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR6]] {		// CHECK1-SAME: (i8* [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR6]] {
// CHECK1-NEXT: entry:		// CHECK1-NEXT: entry:
// CHECK1-NEXT: [[DOTADDR:%.]] = alloca i8, align 8		// CHECK1-NEXT: [[DOTADDR:%.]] = alloca i8, align 8
// CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4		// CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
// CHECK1-NEXT: [[DOTCNT_ADDR:%.*]] = alloca i32, align 4		// CHECK1-NEXT: [[DOTCNT_ADDR:%.*]] = alloca i32, align 4
// CHECK1-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB1]])		// CHECK1-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB1]])
// CHECK1-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8, !tbaa [[TBAA12]]		// CHECK1-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8, !tbaa [[TBAA12]]
// CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTADDR1]], align 4, !tbaa [[TBAA8]]		// CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTADDR1]], align 4, !tbaa [[TBAA8]]
// CHECK1-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block()		// CHECK1-NEXT: [[NVPTX_TID:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block()
// CHECK1-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block()		// CHECK1-NEXT: [[NVPTX_TID2:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block()
// CHECK1-NEXT: [[NVPTX_LANE_ID:%.*]] = and i32 [[TMP4]], 31		// CHECK1-NEXT: [[NVPTX_LANE_ID:%.*]] = and i32 [[NVPTX_TID2]], 31
// CHECK1-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block()		// CHECK1-NEXT: [[NVPTX_TID3:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block()
// CHECK1-NEXT: [[NVPTX_WARP_ID:%.*]] = ashr i32 [[TMP5]], 5		// CHECK1-NEXT: [[NVPTX_WARP_ID:%.*]] = ashr i32 [[NVPTX_TID3]], 5
// CHECK1-NEXT: [[TMP6:%.]] = load i8, i8** [[DOTADDR]], align 8		// CHECK1-NEXT: [[TMP3:%.]] = load i8, i8** [[DOTADDR]], align 8
// CHECK1-NEXT: [[TMP7:%.]] = bitcast i8 [[TMP6]] to [1 x i8]		// CHECK1-NEXT: [[TMP4:%.]] = bitcast i8 [[TMP3]] to [1 x i8]
// CHECK1-NEXT: store i32 0, i32* [[DOTCNT_ADDR]], align 4, !tbaa [[TBAA8]]		// CHECK1-NEXT: store i32 0, i32* [[DOTCNT_ADDR]], align 4, !tbaa [[TBAA8]]
// CHECK1-NEXT: br label [[PRECOND:%.*]]		// CHECK1-NEXT: br label [[PRECOND:%.*]]
// CHECK1: precond:		// CHECK1: precond:
// CHECK1-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTCNT_ADDR]], align 4, !tbaa [[TBAA8]]		// CHECK1-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTCNT_ADDR]], align 4, !tbaa [[TBAA8]]
// CHECK1-NEXT: [[TMP9:%.*]] = icmp ult i32 [[TMP8]], 4		// CHECK1-NEXT: [[TMP6:%.*]] = icmp ult i32 [[TMP5]], 4
// CHECK1-NEXT: br i1 [[TMP9]], label [[BODY:%.]], label [[EXIT:%.]]		// CHECK1-NEXT: br i1 [[TMP6]], label [[BODY:%.]], label [[EXIT:%.]]
// CHECK1: body:		// CHECK1: body:
// CHECK1-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB4]], i32 [[TMP2]])		// CHECK1-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB4]], i32 [[TMP2]])
// CHECK1-NEXT: [[WARP_MASTER:%.*]] = icmp eq i32 [[NVPTX_LANE_ID]], 0		// CHECK1-NEXT: [[WARP_MASTER:%.*]] = icmp eq i32 [[NVPTX_LANE_ID]], 0
// CHECK1-NEXT: br i1 [[WARP_MASTER]], label [[THEN:%.]], label [[ELSE:%.]]		// CHECK1-NEXT: br i1 [[WARP_MASTER]], label [[THEN:%.]], label [[ELSE:%.]]
// CHECK1: then:		// CHECK1: then:
// CHECK1-NEXT: [[TMP10:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[TMP7]], i64 0, i64 0		// CHECK1-NEXT: [[TMP7:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[TMP4]], i64 0, i64 0
// CHECK1-NEXT: [[TMP11:%.]] = load i8, i8** [[TMP10]], align 8, !tbaa [[TBAA12]]		// CHECK1-NEXT: [[TMP8:%.]] = load i8, i8** [[TMP7]], align 8, !tbaa [[TBAA12]]
// CHECK1-NEXT: [[TMP12:%.]] = bitcast i8 [[TMP11]] to i32*		// CHECK1-NEXT: [[TMP9:%.]] = bitcast i8 [[TMP8]] to i32*
// CHECK1-NEXT: [[TMP13:%.]] = getelementptr i32, i32 [[TMP12]], i32 [[TMP8]]		// CHECK1-NEXT: [[TMP10:%.]] = getelementptr i32, i32 [[TMP9]], i32 [[TMP5]]
// CHECK1-NEXT: [[TMP14:%.]] = getelementptr inbounds [32 x i32], [32 x i32] addrspace(3) @__openmp_nvptx_data_transfer_temporary_storage, i64 0, i32 [[NVPTX_WARP_ID]]		// CHECK1-NEXT: [[TMP11:%.]] = getelementptr inbounds [32 x i32], [32 x i32] addrspace(3) @__openmp_nvptx_data_transfer_temporary_storage, i64 0, i32 [[NVPTX_WARP_ID]]
// CHECK1-NEXT: [[TMP15:%.]] = load i32, i32 [[TMP13]], align 4		// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32 [[TMP10]], align 4
// CHECK1-NEXT: store volatile i32 [[TMP15]], i32 addrspace(3)* [[TMP14]], align 4		// CHECK1-NEXT: store volatile i32 [[TMP12]], i32 addrspace(3)* [[TMP11]], align 4
// CHECK1-NEXT: br label [[IFCONT:%.*]]		// CHECK1-NEXT: br label [[IFCONT:%.*]]
// CHECK1: else:		// CHECK1: else:
// CHECK1-NEXT: br label [[IFCONT]]		// CHECK1-NEXT: br label [[IFCONT]]
// CHECK1: ifcont:		// CHECK1: ifcont:
// CHECK1-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB4]], i32 [[TMP2]])		// CHECK1-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB4]], i32 [[TMP2]])
// CHECK1-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTADDR1]], align 4, !tbaa [[TBAA8]]		// CHECK1-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTADDR1]], align 4, !tbaa [[TBAA8]]
// CHECK1-NEXT: [[IS_ACTIVE_THREAD:%.*]] = icmp ult i32 [[TMP3]], [[TMP16]]		// CHECK1-NEXT: [[IS_ACTIVE_THREAD:%.*]] = icmp ult i32 [[NVPTX_TID]], [[TMP13]]
// CHECK1-NEXT: br i1 [[IS_ACTIVE_THREAD]], label [[THEN2:%.]], label [[ELSE3:%.]]		// CHECK1-NEXT: br i1 [[IS_ACTIVE_THREAD]], label [[THEN4:%.]], label [[ELSE5:%.]]
// CHECK1: then2:		// CHECK1: then2:
// CHECK1-NEXT: [[TMP17:%.]] = getelementptr inbounds [32 x i32], [32 x i32] addrspace(3) @__openmp_nvptx_data_transfer_temporary_storage, i64 0, i32 [[TMP3]]		// CHECK1-NEXT: [[TMP14:%.]] = getelementptr inbounds [32 x i32], [32 x i32] addrspace(3) @__openmp_nvptx_data_transfer_temporary_storage, i64 0, i32 [[NVPTX_TID]]
// CHECK1-NEXT: [[TMP18:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[TMP7]], i64 0, i64 0		// CHECK1-NEXT: [[TMP15:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[TMP4]], i64 0, i64 0
// CHECK1-NEXT: [[TMP19:%.]] = load i8, i8** [[TMP18]], align 8, !tbaa [[TBAA12]]		// CHECK1-NEXT: [[TMP16:%.]] = load i8, i8** [[TMP15]], align 8, !tbaa [[TBAA12]]
// CHECK1-NEXT: [[TMP20:%.]] = bitcast i8 [[TMP19]] to i32*		// CHECK1-NEXT: [[TMP17:%.]] = bitcast i8 [[TMP16]] to i32*
// CHECK1-NEXT: [[TMP21:%.]] = getelementptr i32, i32 [[TMP20]], i32 [[TMP8]]		// CHECK1-NEXT: [[TMP18:%.]] = getelementptr i32, i32 [[TMP17]], i32 [[TMP5]]
// CHECK1-NEXT: [[TMP22:%.]] = load volatile i32, i32 addrspace(3) [[TMP17]], align 4, !tbaa [[TBAA8]]		// CHECK1-NEXT: [[TMP19:%.]] = load volatile i32, i32 addrspace(3) [[TMP14]], align 4, !tbaa [[TBAA8]]
// CHECK1-NEXT: store i32 [[TMP22]], i32* [[TMP21]], align 4, !tbaa [[TBAA8]]		// CHECK1-NEXT: store i32 [[TMP19]], i32* [[TMP18]], align 4, !tbaa [[TBAA8]]
// CHECK1-NEXT: br label [[IFCONT4:%.*]]		// CHECK1-NEXT: br label [[IFCONT6:%.*]]
// CHECK1: else3:		// CHECK1: else3:
// CHECK1-NEXT: br label [[IFCONT4]]		// CHECK1-NEXT: br label [[IFCONT6]]
// CHECK1: ifcont4:		// CHECK1: ifcont4:
// CHECK1-NEXT: [[TMP23:%.*]] = add nsw i32 [[TMP8]], 1		// CHECK1-NEXT: [[TMP20:%.*]] = add nsw i32 [[TMP5]], 1
// CHECK1-NEXT: store i32 [[TMP23]], i32* [[DOTCNT_ADDR]], align 4, !tbaa [[TBAA8]]		// CHECK1-NEXT: store i32 [[TMP20]], i32* [[DOTCNT_ADDR]], align 4, !tbaa [[TBAA8]]
// CHECK1-NEXT: br label [[PRECOND]]		// CHECK1-NEXT: br label [[PRECOND]]
// CHECK1: exit:		// CHECK1: exit:
// CHECK1-NEXT: ret void		// CHECK1-NEXT: ret void
//		//
//		//
// CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__3_wrapper		// CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__3_wrapper
// CHECK1-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR6]] {		// CHECK1-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR6]] {
// CHECK1-NEXT: entry:		// CHECK1-NEXT: entry:
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// CHECK1-NEXT: ret double [[TMP0]]		// CHECK1-NEXT: ret double [[TMP0]]
//		//
//		//
// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z17complex_reductionIfEvv_l16		// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z17complex_reductionIfEvv_l16
// CHECK2-SAME: () #[[ATTR0:[0-9]+]] {		// CHECK2-SAME: () #[[ATTR0:[0-9]+]] {
// CHECK2-NEXT: entry:		// CHECK2-NEXT: entry:
// CHECK2-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4		// CHECK2-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
// CHECK2-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4		// CHECK2-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
// CHECK2-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1:[0-9]+]], i8 1, i1 true, i1 true)		// CHECK2-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z17complex_reductionIfEvv_l16_kernel_info, i1 true)
// CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1		// CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]		// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
// CHECK2: user_code.entry:		// CHECK2: user_code.entry:
// CHECK2-NEXT: [[TMP1:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB1]])		// CHECK2-NEXT: [[TMP1:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB1:[0-9]+]])
// CHECK2-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4		// CHECK2-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
// CHECK2-NEXT: store i32 [[TMP1]], i32* [[DOTTHREADID_TEMP_]], align 4, !tbaa [[TBAA8:![0-9]+]]		// CHECK2-NEXT: store i32 [[TMP1]], i32* [[DOTTHREADID_TEMP_]], align 4, !tbaa [[TBAA8:![0-9]+]]
// CHECK2-NEXT: call void @__omp_outlined__(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]]) #[[ATTR5:[0-9]+]]		// CHECK2-NEXT: call void @__omp_outlined__(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]]) #[[ATTR5:[0-9]+]]
// CHECK2-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true)		// CHECK2-NEXT: call void @__kmpc_target_deinit(i1 true)
// CHECK2-NEXT: ret void		// CHECK2-NEXT: ret void
// CHECK2: worker.exit:		// CHECK2: worker.exit:
// CHECK2-NEXT: ret void		// CHECK2-NEXT: ret void
//		//
//		//
// CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__		// CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__
// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {		// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
// CHECK2-NEXT: entry:		// CHECK2-NEXT: entry:
// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8		// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8
// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8		// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8
// CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4		// CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
// CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4		// CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4
// CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4		// CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
// CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4		// CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
// CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4		// CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
// CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4		// CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
// CHECK2-NEXT: [[IB:%.*]] = alloca i32, align 4		// CHECK2-NEXT: [[IB:%.*]] = alloca i32, align 4
// CHECK2-NEXT: [[REF_TMP:%.*]] = alloca float, align 4		// CHECK2-NEXT: [[REF_TMP:%.*]] = alloca float, align 4
// CHECK2-NEXT: [[REF_TMP2:%.*]] = alloca float, align 4		// CHECK2-NEXT: [[REF_TMP2:%.*]] = alloca float, align 4
// CHECK2-NEXT: [[CAPTURED_VARS_ADDRS:%.]] = alloca [3 x i8], align 8		// CHECK2-NEXT: [[CAPTURED_VARS_ADDRS:%.]] = alloca [3 x i8], align 8
// CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8, !tbaa [[TBAA12:![0-9]+]]		// CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8, !tbaa [[TBAA12:![0-9]+]]
// CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8, !tbaa [[TBAA12]]		// CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8, !tbaa [[TBAA12]]
// CHECK2-NEXT: [[ISTART:%.]] = call align 16 i8 @__kmpc_alloc_shared(i64 4)		// CHECK2-NEXT: [[ISTART:%.]] = call i8 @__kmpc_alloc_shared(i64 4)
// CHECK2-NEXT: [[ISTART_ON_STACK:%.]] = bitcast i8 [[ISTART]] to i32*		// CHECK2-NEXT: [[ISTART_ON_STACK:%.]] = bitcast i8 [[ISTART]] to i32*
// CHECK2-NEXT: [[IEND:%.]] = call align 16 i8 @__kmpc_alloc_shared(i64 4)		// CHECK2-NEXT: [[IEND:%.]] = call i8 @__kmpc_alloc_shared(i64 4)
// CHECK2-NEXT: [[IEND_ON_STACK:%.]] = bitcast i8 [[IEND]] to i32*		// CHECK2-NEXT: [[IEND_ON_STACK:%.]] = bitcast i8 [[IEND]] to i32*
// CHECK2-NEXT: [[PARTIAL_SUM:%.]] = call align 16 i8 @__kmpc_alloc_shared(i64 8)		// CHECK2-NEXT: [[PARTIAL_SUM:%.]] = call i8 @__kmpc_alloc_shared(i64 8)
// CHECK2-NEXT: [[PARTIAL_SUM_ON_STACK:%.]] = bitcast i8 [[PARTIAL_SUM]] to %"class.std::complex"*		// CHECK2-NEXT: [[PARTIAL_SUM_ON_STACK:%.]] = bitcast i8 [[PARTIAL_SUM]] to %"class.std::complex"*
// CHECK2-NEXT: [[TMP0:%.]] = bitcast i32 [[DOTOMP_IV]] to i8*		// CHECK2-NEXT: [[TMP0:%.]] = bitcast i32 [[DOTOMP_IV]] to i8*
// CHECK2-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP0]]) #[[ATTR5]]		// CHECK2-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP0]]) #[[ATTR5]]
// CHECK2-NEXT: [[TMP1:%.]] = bitcast i32 [[DOTOMP_LB]] to i8*		// CHECK2-NEXT: [[TMP1:%.]] = bitcast i32 [[DOTOMP_LB]] to i8*
// CHECK2-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP1]]) #[[ATTR5]]		// CHECK2-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP1]]) #[[ATTR5]]
// CHECK2-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4, !tbaa [[TBAA8]]		// CHECK2-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4, !tbaa [[TBAA8]]
// CHECK2-NEXT: [[TMP2:%.]] = bitcast i32 [[DOTOMP_UB]] to i8*		// CHECK2-NEXT: [[TMP2:%.]] = bitcast i32 [[DOTOMP_UB]] to i8*
// CHECK2-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP2]]) #[[ATTR5]]		// CHECK2-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP2]]) #[[ATTR5]]
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// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]		// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK2-NEXT: store i32 [[ADD]], i32* [[IB]], align 4, !tbaa [[TBAA8]]		// CHECK2-NEXT: store i32 [[ADD]], i32* [[IB]], align 4, !tbaa [[TBAA8]]
// CHECK2-NEXT: [[TMP14:%.]] = bitcast float [[REF_TMP]] to i8*		// CHECK2-NEXT: [[TMP14:%.]] = bitcast float [[REF_TMP]] to i8*
// CHECK2-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP14]]) #[[ATTR5]]		// CHECK2-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP14]]) #[[ATTR5]]
// CHECK2-NEXT: store float 0.000000e+00, float* [[REF_TMP]], align 4, !tbaa [[TBAA14:![0-9]+]]		// CHECK2-NEXT: store float 0.000000e+00, float* [[REF_TMP]], align 4, !tbaa [[TBAA14:![0-9]+]]
// CHECK2-NEXT: [[TMP15:%.]] = bitcast float [[REF_TMP2]] to i8*		// CHECK2-NEXT: [[TMP15:%.]] = bitcast float [[REF_TMP2]] to i8*
// CHECK2-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP15]]) #[[ATTR5]]		// CHECK2-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP15]]) #[[ATTR5]]
// CHECK2-NEXT: store float 0.000000e+00, float* [[REF_TMP2]], align 4, !tbaa [[TBAA14]]		// CHECK2-NEXT: store float 0.000000e+00, float* [[REF_TMP2]], align 4, !tbaa [[TBAA14]]
// CHECK2-NEXT: call void @_ZNSt7complexIfEC1ERKfS2_(%"class.std::complex"* nonnull align 4 dereferenceable(8) [[PARTIAL_SUM_ON_STACK]], float* nonnull align 4 dereferenceable(4) [[REF_TMP]], float* nonnull align 4 dereferenceable(4) [[REF_TMP2]]) #[[ATTR10:[0-9]+]]		// CHECK2-NEXT: call void @_ZNSt7complexIfEC1ERKfS2_(%"class.std::complex"* nonnull align 4 dereferenceable(8) [[PARTIAL_SUM_ON_STACK]], float* nonnull align 4 dereferenceable(4) [[REF_TMP]], float* nonnull align 4 dereferenceable(4) [[REF_TMP2]]) #[[ATTR12:[0-9]+]]
// CHECK2-NEXT: [[TMP16:%.]] = bitcast float [[REF_TMP2]] to i8*		// CHECK2-NEXT: [[TMP16:%.]] = bitcast float [[REF_TMP2]] to i8*
// CHECK2-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP16]]) #[[ATTR5]]		// CHECK2-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP16]]) #[[ATTR5]]
// CHECK2-NEXT: [[TMP17:%.]] = bitcast float [[REF_TMP]] to i8*		// CHECK2-NEXT: [[TMP17:%.]] = bitcast float [[REF_TMP]] to i8*
// CHECK2-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP17]]) #[[ATTR5]]		// CHECK2-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP17]]) #[[ATTR5]]
// CHECK2-NEXT: [[TMP18:%.]] = load i32, i32 [[IB]], align 4, !tbaa [[TBAA8]]		// CHECK2-NEXT: [[TMP18:%.]] = load i32, i32 [[IB]], align 4, !tbaa [[TBAA8]]
// CHECK2-NEXT: [[MUL3:%.*]] = mul nsw i32 [[TMP18]], 4		// CHECK2-NEXT: [[MUL3:%.*]] = mul nsw i32 [[TMP18]], 4
// CHECK2-NEXT: store i32 [[MUL3]], i32* [[ISTART_ON_STACK]], align 4, !tbaa [[TBAA8]]		// CHECK2-NEXT: store i32 [[MUL3]], i32* [[ISTART_ON_STACK]], align 4, !tbaa [[TBAA8]]
// CHECK2-NEXT: [[TMP19:%.]] = load i32, i32 [[IB]], align 4, !tbaa [[TBAA8]]		// CHECK2-NEXT: [[TMP19:%.]] = load i32, i32 [[IB]], align 4, !tbaa [[TBAA8]]
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// CHECK2-NEXT: [[__RE_ADDR:%.]] = alloca float, align 8		// CHECK2-NEXT: [[__RE_ADDR:%.]] = alloca float, align 8
// CHECK2-NEXT: [[__IM_ADDR:%.]] = alloca float, align 8		// CHECK2-NEXT: [[__IM_ADDR:%.]] = alloca float, align 8
// CHECK2-NEXT: store %"class.std::complex"* [[THIS]], %"class.std::complex"** [[THIS_ADDR]], align 8, !tbaa [[TBAA12]]		// CHECK2-NEXT: store %"class.std::complex"* [[THIS]], %"class.std::complex"** [[THIS_ADDR]], align 8, !tbaa [[TBAA12]]
// CHECK2-NEXT: store float* [[__RE]], float** [[__RE_ADDR]], align 8, !tbaa [[TBAA12]]		// CHECK2-NEXT: store float* [[__RE]], float** [[__RE_ADDR]], align 8, !tbaa [[TBAA12]]
// CHECK2-NEXT: store float* [[__IM]], float** [[__IM_ADDR]], align 8, !tbaa [[TBAA12]]		// CHECK2-NEXT: store float* [[__IM]], float** [[__IM_ADDR]], align 8, !tbaa [[TBAA12]]
// CHECK2-NEXT: [[THIS1:%.]] = load %"class.std::complex", %"class.std::complex"** [[THIS_ADDR]], align 8		// CHECK2-NEXT: [[THIS1:%.]] = load %"class.std::complex", %"class.std::complex"** [[THIS_ADDR]], align 8
// CHECK2-NEXT: [[TMP0:%.]] = load float, float** [[__RE_ADDR]], align 8		// CHECK2-NEXT: [[TMP0:%.]] = load float, float** [[__RE_ADDR]], align 8
// CHECK2-NEXT: [[TMP1:%.]] = load float, float** [[__IM_ADDR]], align 8		// CHECK2-NEXT: [[TMP1:%.]] = load float, float** [[__IM_ADDR]], align 8
// CHECK2-NEXT: call void @_ZNSt7complexIfEC2ERKfS2_(%"class.std::complex"* nonnull align 4 dereferenceable(8) [[THIS1]], float* nonnull align 4 dereferenceable(4) [[TMP0]], float* nonnull align 4 dereferenceable(4) [[TMP1]]) #[[ATTR10]]		// CHECK2-NEXT: call void @_ZNSt7complexIfEC2ERKfS2_(%"class.std::complex"* nonnull align 4 dereferenceable(8) [[THIS1]], float* nonnull align 4 dereferenceable(4) [[TMP0]], float* nonnull align 4 dereferenceable(4) [[TMP1]]) #[[ATTR12]]
// CHECK2-NEXT: ret void		// CHECK2-NEXT: ret void
//		//
//		//
// CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__1		// CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__1
// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i32 nonnull align 4 dereferenceable(4) [[ISTART:%.]], i32 nonnull align 4 dereferenceable(4) [[IEND:%.]], %"class.std::complex" nonnull align 4 dereferenceable(8) [[PARTIAL_SUM:%.*]]) #[[ATTR0]] {		// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i32 nonnull align 4 dereferenceable(4) [[ISTART:%.]], i32 nonnull align 4 dereferenceable(4) [[IEND:%.]], %"class.std::complex" nonnull align 4 dereferenceable(8) [[PARTIAL_SUM:%.*]]) #[[ATTR0]] {
// CHECK2-NEXT: entry:		// CHECK2-NEXT: entry:
// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8		// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8
// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8		// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8
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// CHECK2-NEXT: [[TMP21:%.]] = bitcast %"class.std::complex" [[PARTIAL_SUM5]] to i8*		// CHECK2-NEXT: [[TMP21:%.]] = bitcast %"class.std::complex" [[PARTIAL_SUM5]] to i8*
// CHECK2-NEXT: call void @llvm.lifetime.start.p0i8(i64 8, i8* [[TMP21]]) #[[ATTR5]]		// CHECK2-NEXT: call void @llvm.lifetime.start.p0i8(i64 8, i8* [[TMP21]]) #[[ATTR5]]
// CHECK2-NEXT: [[TMP22:%.]] = bitcast float [[REF_TMP]] to i8*		// CHECK2-NEXT: [[TMP22:%.]] = bitcast float [[REF_TMP]] to i8*
// CHECK2-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP22]]) #[[ATTR5]]		// CHECK2-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP22]]) #[[ATTR5]]
// CHECK2-NEXT: store float 0.000000e+00, float* [[REF_TMP]], align 4, !tbaa [[TBAA14]]		// CHECK2-NEXT: store float 0.000000e+00, float* [[REF_TMP]], align 4, !tbaa [[TBAA14]]
// CHECK2-NEXT: [[TMP23:%.]] = bitcast float [[REF_TMP6]] to i8*		// CHECK2-NEXT: [[TMP23:%.]] = bitcast float [[REF_TMP6]] to i8*
// CHECK2-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP23]]) #[[ATTR5]]		// CHECK2-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP23]]) #[[ATTR5]]
// CHECK2-NEXT: store float 0.000000e+00, float* [[REF_TMP6]], align 4, !tbaa [[TBAA14]]		// CHECK2-NEXT: store float 0.000000e+00, float* [[REF_TMP6]], align 4, !tbaa [[TBAA14]]
// CHECK2-NEXT: call void @_ZNSt7complexIfEC1ERKfS2_(%"class.std::complex"* nonnull align 4 dereferenceable(8) [[PARTIAL_SUM5]], float* nonnull align 4 dereferenceable(4) [[REF_TMP]], float* nonnull align 4 dereferenceable(4) [[REF_TMP6]]) #[[ATTR10]]		// CHECK2-NEXT: call void @_ZNSt7complexIfEC1ERKfS2_(%"class.std::complex"* nonnull align 4 dereferenceable(8) [[PARTIAL_SUM5]], float* nonnull align 4 dereferenceable(4) [[REF_TMP]], float* nonnull align 4 dereferenceable(4) [[REF_TMP6]]) #[[ATTR12]]
// CHECK2-NEXT: [[TMP24:%.]] = bitcast float [[REF_TMP6]] to i8*		// CHECK2-NEXT: [[TMP24:%.]] = bitcast float [[REF_TMP6]] to i8*
// CHECK2-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP24]]) #[[ATTR5]]		// CHECK2-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP24]]) #[[ATTR5]]
// CHECK2-NEXT: [[TMP25:%.]] = bitcast float [[REF_TMP]] to i8*		// CHECK2-NEXT: [[TMP25:%.]] = bitcast float [[REF_TMP]] to i8*
// CHECK2-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP25]]) #[[ATTR5]]		// CHECK2-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP25]]) #[[ATTR5]]
// CHECK2-NEXT: [[TMP26:%.]] = bitcast i32 [[I7]] to i8*		// CHECK2-NEXT: [[TMP26:%.]] = bitcast i32 [[I7]] to i8*
// CHECK2-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP26]]) #[[ATTR5]]		// CHECK2-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP26]]) #[[ATTR5]]
// CHECK2-NEXT: [[TMP27:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8		// CHECK2-NEXT: [[TMP27:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK2-NEXT: [[TMP28:%.]] = load i32, i32 [[TMP27]], align 4, !tbaa [[TBAA8]]		// CHECK2-NEXT: [[TMP28:%.]] = load i32, i32 [[TMP27]], align 4, !tbaa [[TBAA8]]
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// CHECK2-NEXT: [[TMP42:%.]] = load i32, i32 [[I7]], align 4, !tbaa [[TBAA8]]		// CHECK2-NEXT: [[TMP42:%.]] = load i32, i32 [[I7]], align 4, !tbaa [[TBAA8]]
// CHECK2-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP42]] to float		// CHECK2-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP42]] to float
// CHECK2-NEXT: store float [[CONV]], float* [[REF_TMP15]], align 4, !tbaa [[TBAA14]]		// CHECK2-NEXT: store float [[CONV]], float* [[REF_TMP15]], align 4, !tbaa [[TBAA14]]
// CHECK2-NEXT: [[TMP43:%.]] = bitcast float [[REF_TMP16]] to i8*		// CHECK2-NEXT: [[TMP43:%.]] = bitcast float [[REF_TMP16]] to i8*
// CHECK2-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP43]]) #[[ATTR5]]		// CHECK2-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP43]]) #[[ATTR5]]
// CHECK2-NEXT: [[TMP44:%.]] = load i32, i32 [[I7]], align 4, !tbaa [[TBAA8]]		// CHECK2-NEXT: [[TMP44:%.]] = load i32, i32 [[I7]], align 4, !tbaa [[TBAA8]]
// CHECK2-NEXT: [[CONV17:%.*]] = sitofp i32 [[TMP44]] to float		// CHECK2-NEXT: [[CONV17:%.*]] = sitofp i32 [[TMP44]] to float
// CHECK2-NEXT: store float [[CONV17]], float* [[REF_TMP16]], align 4, !tbaa [[TBAA14]]		// CHECK2-NEXT: store float [[CONV17]], float* [[REF_TMP16]], align 4, !tbaa [[TBAA14]]
// CHECK2-NEXT: call void @_ZNSt7complexIfEC1ERKfS2_(%"class.std::complex"* nonnull align 4 dereferenceable(8) [[REF_TMP14]], float* nonnull align 4 dereferenceable(4) [[REF_TMP15]], float* nonnull align 4 dereferenceable(4) [[REF_TMP16]]) #[[ATTR10]]		// CHECK2-NEXT: call void @_ZNSt7complexIfEC1ERKfS2_(%"class.std::complex"* nonnull align 4 dereferenceable(8) [[REF_TMP14]], float* nonnull align 4 dereferenceable(4) [[REF_TMP15]], float* nonnull align 4 dereferenceable(4) [[REF_TMP16]]) #[[ATTR12]]
// CHECK2-NEXT: [[CALL:%.]] = call nonnull align 4 dereferenceable(8) %"class.std::complex" @_ZNSt7complexIfEpLIfEERS0_RKS_IT_E(%"class.std::complex"* nonnull align 4 dereferenceable(8) [[PARTIAL_SUM5]], %"class.std::complex"* nonnull align 4 dereferenceable(8) [[REF_TMP14]]) #[[ATTR10]]		// CHECK2-NEXT: [[CALL:%.]] = call nonnull align 4 dereferenceable(8) %"class.std::complex" @_ZNSt7complexIfEpLIfEERS0_RKS_IT_E(%"class.std::complex"* nonnull align 4 dereferenceable(8) [[PARTIAL_SUM5]], %"class.std::complex"* nonnull align 4 dereferenceable(8) [[REF_TMP14]]) #[[ATTR12]]
// CHECK2-NEXT: [[TMP45:%.]] = bitcast float [[REF_TMP16]] to i8*		// CHECK2-NEXT: [[TMP45:%.]] = bitcast float [[REF_TMP16]] to i8*
// CHECK2-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP45]]) #[[ATTR5]]		// CHECK2-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP45]]) #[[ATTR5]]
// CHECK2-NEXT: [[TMP46:%.]] = bitcast float [[REF_TMP15]] to i8*		// CHECK2-NEXT: [[TMP46:%.]] = bitcast float [[REF_TMP15]] to i8*
// CHECK2-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP46]]) #[[ATTR5]]		// CHECK2-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP46]]) #[[ATTR5]]
// CHECK2-NEXT: [[TMP47:%.]] = bitcast %"class.std::complex" [[REF_TMP14]] to i8*		// CHECK2-NEXT: [[TMP47:%.]] = bitcast %"class.std::complex" [[REF_TMP14]] to i8*
// CHECK2-NEXT: call void @llvm.lifetime.end.p0i8(i64 8, i8* [[TMP47]]) #[[ATTR5]]		// CHECK2-NEXT: call void @llvm.lifetime.end.p0i8(i64 8, i8* [[TMP47]]) #[[ATTR5]]
// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]		// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK2: omp.body.continue:		// CHECK2: omp.body.continue:
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// CHECK2-NEXT: [[TMP57:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0		// CHECK2-NEXT: [[TMP57:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0
// CHECK2-NEXT: [[TMP58:%.]] = bitcast %"class.std::complex" [[PARTIAL_SUM5]] to i8*		// CHECK2-NEXT: [[TMP58:%.]] = bitcast %"class.std::complex" [[PARTIAL_SUM5]] to i8*
// CHECK2-NEXT: store i8* [[TMP58]], i8** [[TMP57]], align 8		// CHECK2-NEXT: store i8* [[TMP58]], i8** [[TMP57]], align 8
// CHECK2-NEXT: [[TMP59:%.]] = bitcast [1 x i8]* [[DOTOMP_REDUCTION_RED_LIST]] to i8*		// CHECK2-NEXT: [[TMP59:%.]] = bitcast [1 x i8]* [[DOTOMP_REDUCTION_RED_LIST]] to i8*
// CHECK2-NEXT: [[TMP60:%.]] = call i32 @__kmpc_nvptx_parallel_reduce_nowait_v2(%struct.ident_t @[[GLOB1]], i32 [[TMP56]], i32 1, i64 8, i8* [[TMP59]], void (i8, i16, i16, i16) @_omp_reduction_shuffle_and_reduce_func, void (i8, i32) @_omp_reduction_inter_warp_copy_func)		// CHECK2-NEXT: [[TMP60:%.]] = call i32 @__kmpc_nvptx_parallel_reduce_nowait_v2(%struct.ident_t @[[GLOB1]], i32 [[TMP56]], i32 1, i64 8, i8* [[TMP59]], void (i8, i16, i16, i16) @_omp_reduction_shuffle_and_reduce_func, void (i8, i32) @_omp_reduction_inter_warp_copy_func)
// CHECK2-NEXT: [[TMP61:%.*]] = icmp eq i32 [[TMP60]], 1		// CHECK2-NEXT: [[TMP61:%.*]] = icmp eq i32 [[TMP60]], 1
// CHECK2-NEXT: br i1 [[TMP61]], label [[DOTOMP_REDUCTION_THEN:%.]], label [[DOTOMP_REDUCTION_DONE:%.]]		// CHECK2-NEXT: br i1 [[TMP61]], label [[DOTOMP_REDUCTION_THEN:%.]], label [[DOTOMP_REDUCTION_DONE:%.]]
// CHECK2: .omp.reduction.then:		// CHECK2: .omp.reduction.then:
// CHECK2-NEXT: [[CALL21:%.]] = call nonnull align 4 dereferenceable(8) %"class.std::complex" @_ZNSt7complexIfEpLIfEERS0_RKS_IT_E(%"class.std::complex"* nonnull align 4 dereferenceable(8) [[TMP2]], %"class.std::complex"* nonnull align 4 dereferenceable(8) [[PARTIAL_SUM5]]) #[[ATTR10]]		// CHECK2-NEXT: [[CALL21:%.]] = call nonnull align 4 dereferenceable(8) %"class.std::complex" @_ZNSt7complexIfEpLIfEERS0_RKS_IT_E(%"class.std::complex"* nonnull align 4 dereferenceable(8) [[TMP2]], %"class.std::complex"* nonnull align 4 dereferenceable(8) [[PARTIAL_SUM5]]) #[[ATTR12]]
// CHECK2-NEXT: call void @__kmpc_nvptx_end_reduce_nowait(i32 [[TMP56]])		// CHECK2-NEXT: call void @__kmpc_nvptx_end_reduce_nowait(i32 [[TMP56]])
// CHECK2-NEXT: br label [[DOTOMP_REDUCTION_DONE]]		// CHECK2-NEXT: br label [[DOTOMP_REDUCTION_DONE]]
// CHECK2: .omp.reduction.done:		// CHECK2: .omp.reduction.done:
// CHECK2-NEXT: [[TMP62:%.]] = bitcast i32 [[I7]] to i8*		// CHECK2-NEXT: [[TMP62:%.]] = bitcast i32 [[I7]] to i8*
// CHECK2-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP62]]) #[[ATTR5]]		// CHECK2-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP62]]) #[[ATTR5]]
// CHECK2-NEXT: [[TMP63:%.]] = bitcast %"class.std::complex" [[PARTIAL_SUM5]] to i8*		// CHECK2-NEXT: [[TMP63:%.]] = bitcast %"class.std::complex" [[PARTIAL_SUM5]] to i8*
// CHECK2-NEXT: call void @llvm.lifetime.end.p0i8(i64 8, i8* [[TMP63]]) #[[ATTR5]]		// CHECK2-NEXT: call void @llvm.lifetime.end.p0i8(i64 8, i8* [[TMP63]]) #[[ATTR5]]
// CHECK2-NEXT: [[TMP64:%.]] = bitcast i32 [[DOTOMP_IS_LAST]] to i8*		// CHECK2-NEXT: [[TMP64:%.]] = bitcast i32 [[DOTOMP_IS_LAST]] to i8*
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// CHECK2-SAME: (%"class.std::complex"* nonnull align 4 dereferenceable(8) [[THIS:%.]], %"class.std::complex" nonnull align 4 dereferenceable(8) [[__C:%.*]]) #[[ATTR4:[0-9]+]] comdat align 2 {		// CHECK2-SAME: (%"class.std::complex"* nonnull align 4 dereferenceable(8) [[THIS:%.]], %"class.std::complex" nonnull align 4 dereferenceable(8) [[__C:%.*]]) #[[ATTR4:[0-9]+]] comdat align 2 {
// CHECK2-NEXT: entry:		// CHECK2-NEXT: entry:
// CHECK2-NEXT: [[THIS_ADDR:%.]] = alloca %"class.std::complex", align 8		// CHECK2-NEXT: [[THIS_ADDR:%.]] = alloca %"class.std::complex", align 8
// CHECK2-NEXT: [[__C_ADDR:%.]] = alloca %"class.std::complex", align 8		// CHECK2-NEXT: [[__C_ADDR:%.]] = alloca %"class.std::complex", align 8
// CHECK2-NEXT: store %"class.std::complex"* [[THIS]], %"class.std::complex"** [[THIS_ADDR]], align 8, !tbaa [[TBAA12]]		// CHECK2-NEXT: store %"class.std::complex"* [[THIS]], %"class.std::complex"** [[THIS_ADDR]], align 8, !tbaa [[TBAA12]]
// CHECK2-NEXT: store %"class.std::complex"* [[__C]], %"class.std::complex"** [[__C_ADDR]], align 8, !tbaa [[TBAA12]]		// CHECK2-NEXT: store %"class.std::complex"* [[__C]], %"class.std::complex"** [[__C_ADDR]], align 8, !tbaa [[TBAA12]]
// CHECK2-NEXT: [[THIS1:%.]] = load %"class.std::complex", %"class.std::complex"** [[THIS_ADDR]], align 8		// CHECK2-NEXT: [[THIS1:%.]] = load %"class.std::complex", %"class.std::complex"** [[THIS_ADDR]], align 8
// CHECK2-NEXT: [[TMP0:%.]] = load %"class.std::complex", %"class.std::complex"** [[__C_ADDR]], align 8, !tbaa [[TBAA12]]		// CHECK2-NEXT: [[TMP0:%.]] = load %"class.std::complex", %"class.std::complex"** [[__C_ADDR]], align 8, !tbaa [[TBAA12]]
// CHECK2-NEXT: [[CALL:%.]] = call float @_ZNKSt7complexIfE4realEv(%"class.std::complex" nonnull align 4 dereferenceable(8) [[TMP0]]) #[[ATTR10]]		// CHECK2-NEXT: [[CALL:%.]] = call float @_ZNKSt7complexIfE4realEv(%"class.std::complex" nonnull align 4 dereferenceable(8) [[TMP0]]) #[[ATTR12]]
// CHECK2-NEXT: [[__RE_:%.]] = getelementptr inbounds %"class.std::complex", %"class.std::complex" [[THIS1]], i32 0, i32 0		// CHECK2-NEXT: [[__RE_:%.]] = getelementptr inbounds %"class.std::complex", %"class.std::complex" [[THIS1]], i32 0, i32 0
// CHECK2-NEXT: [[TMP1:%.]] = load float, float [[__RE_]], align 4, !tbaa [[TBAA16:![0-9]+]]		// CHECK2-NEXT: [[TMP1:%.]] = load float, float [[__RE_]], align 4, !tbaa [[TBAA16:![0-9]+]]
// CHECK2-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CALL]]		// CHECK2-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CALL]]
// CHECK2-NEXT: store float [[ADD]], float* [[__RE_]], align 4, !tbaa [[TBAA16]]		// CHECK2-NEXT: store float [[ADD]], float* [[__RE_]], align 4, !tbaa [[TBAA16]]
// CHECK2-NEXT: [[TMP2:%.]] = load %"class.std::complex", %"class.std::complex"** [[__C_ADDR]], align 8, !tbaa [[TBAA12]]		// CHECK2-NEXT: [[TMP2:%.]] = load %"class.std::complex", %"class.std::complex"** [[__C_ADDR]], align 8, !tbaa [[TBAA12]]
// CHECK2-NEXT: [[CALL2:%.]] = call float @_ZNKSt7complexIfE4imagEv(%"class.std::complex" nonnull align 4 dereferenceable(8) [[TMP2]]) #[[ATTR10]]		// CHECK2-NEXT: [[CALL2:%.]] = call float @_ZNKSt7complexIfE4imagEv(%"class.std::complex" nonnull align 4 dereferenceable(8) [[TMP2]]) #[[ATTR12]]
// CHECK2-NEXT: [[__IM_:%.]] = getelementptr inbounds %"class.std::complex", %"class.std::complex" [[THIS1]], i32 0, i32 1		// CHECK2-NEXT: [[__IM_:%.]] = getelementptr inbounds %"class.std::complex", %"class.std::complex" [[THIS1]], i32 0, i32 1
// CHECK2-NEXT: [[TMP3:%.]] = load float, float [[__IM_]], align 4, !tbaa [[TBAA18:![0-9]+]]		// CHECK2-NEXT: [[TMP3:%.]] = load float, float [[__IM_]], align 4, !tbaa [[TBAA18:![0-9]+]]
// CHECK2-NEXT: [[ADD3:%.*]] = fadd float [[TMP3]], [[CALL2]]		// CHECK2-NEXT: [[ADD3:%.*]] = fadd float [[TMP3]], [[CALL2]]
// CHECK2-NEXT: store float [[ADD3]], float* [[__IM_]], align 4, !tbaa [[TBAA18]]		// CHECK2-NEXT: store float [[ADD3]], float* [[__IM_]], align 4, !tbaa [[TBAA18]]
// CHECK2-NEXT: ret %"class.std::complex"* [[THIS1]]		// CHECK2-NEXT: ret %"class.std::complex"* [[THIS1]]
//		//
//		//
// CHECK2-LABEL: define {{[^@]+}}@_omp_reduction_shuffle_and_reduce_func		// CHECK2-LABEL: define {{[^@]+}}@_omp_reduction_shuffle_and_reduce_func
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// CHECK2-NEXT: [[TMP10:%.]] = load i8, i8** [[TMP9]], align 8		// CHECK2-NEXT: [[TMP10:%.]] = load i8, i8** [[TMP9]], align 8
// CHECK2-NEXT: [[TMP11:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST]], i64 0, i64 0		// CHECK2-NEXT: [[TMP11:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST]], i64 0, i64 0
// CHECK2-NEXT: [[TMP12:%.]] = bitcast i8 [[TMP10]] to %"class.std::complex"*		// CHECK2-NEXT: [[TMP12:%.]] = bitcast i8 [[TMP10]] to %"class.std::complex"*
// CHECK2-NEXT: [[TMP13:%.]] = getelementptr %"class.std::complex", %"class.std::complex" [[TMP12]], i64 1		// CHECK2-NEXT: [[TMP13:%.]] = getelementptr %"class.std::complex", %"class.std::complex" [[TMP12]], i64 1
// CHECK2-NEXT: [[TMP14:%.]] = bitcast %"class.std::complex" [[TMP13]] to i8*		// CHECK2-NEXT: [[TMP14:%.]] = bitcast %"class.std::complex" [[TMP13]] to i8*
// CHECK2-NEXT: [[TMP15:%.]] = bitcast %"class.std::complex" [[TMP12]] to i64*		// CHECK2-NEXT: [[TMP15:%.]] = bitcast %"class.std::complex" [[TMP12]] to i64*
// CHECK2-NEXT: [[TMP16:%.]] = bitcast %"class.std::complex" [[DOTOMP_REDUCTION_ELEMENT]] to i64*		// CHECK2-NEXT: [[TMP16:%.]] = bitcast %"class.std::complex" [[DOTOMP_REDUCTION_ELEMENT]] to i64*
// CHECK2-NEXT: [[TMP17:%.]] = load i64, i64 [[TMP15]], align 4		// CHECK2-NEXT: [[TMP17:%.]] = load i64, i64 [[TMP15]], align 4
// CHECK2-NEXT: [[TMP18:%.*]] = call i32 @__kmpc_get_warp_size()		// CHECK2-NEXT: [[NVPTX_WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size()
// CHECK2-NEXT: [[TMP19:%.*]] = trunc i32 [[TMP18]] to i16		// CHECK2-NEXT: [[TMP18:%.*]] = trunc i32 [[NVPTX_WARP_SIZE]] to i16
// CHECK2-NEXT: [[TMP20:%.*]] = call i64 @__kmpc_shuffle_int64(i64 [[TMP17]], i16 [[TMP7]], i16 [[TMP19]])		// CHECK2-NEXT: [[TMP19:%.*]] = call i64 @__kmpc_shuffle_int64(i64 [[TMP17]], i16 [[TMP7]], i16 [[TMP18]])
// CHECK2-NEXT: store i64 [[TMP20]], i64* [[TMP16]], align 4		// CHECK2-NEXT: store i64 [[TMP19]], i64* [[TMP16]], align 4
// CHECK2-NEXT: [[TMP21:%.]] = getelementptr i64, i64 [[TMP15]], i64 1		// CHECK2-NEXT: [[TMP20:%.]] = getelementptr i64, i64 [[TMP15]], i64 1
// CHECK2-NEXT: [[TMP22:%.]] = getelementptr i64, i64 [[TMP16]], i64 1		// CHECK2-NEXT: [[TMP21:%.]] = getelementptr i64, i64 [[TMP16]], i64 1
// CHECK2-NEXT: [[TMP23:%.]] = bitcast %"class.std::complex" [[DOTOMP_REDUCTION_ELEMENT]] to i8*		// CHECK2-NEXT: [[TMP22:%.]] = bitcast %"class.std::complex" [[DOTOMP_REDUCTION_ELEMENT]] to i8*
// CHECK2-NEXT: store i8* [[TMP23]], i8** [[TMP11]], align 8, !tbaa [[TBAA12]]		// CHECK2-NEXT: store i8* [[TMP22]], i8** [[TMP11]], align 8, !tbaa [[TBAA12]]
// CHECK2-NEXT: [[TMP24:%.*]] = icmp eq i16 [[TMP8]], 0		// CHECK2-NEXT: [[TMP23:%.*]] = icmp eq i16 [[TMP8]], 0
// CHECK2-NEXT: [[TMP25:%.*]] = icmp eq i16 [[TMP8]], 1		// CHECK2-NEXT: [[TMP24:%.*]] = icmp eq i16 [[TMP8]], 1
// CHECK2-NEXT: [[TMP26:%.*]] = icmp ult i16 [[TMP6]], [[TMP7]]		// CHECK2-NEXT: [[TMP25:%.*]] = icmp ult i16 [[TMP6]], [[TMP7]]
// CHECK2-NEXT: [[TMP27:%.*]] = and i1 [[TMP25]], [[TMP26]]		// CHECK2-NEXT: [[TMP26:%.*]] = and i1 [[TMP24]], [[TMP25]]
// CHECK2-NEXT: [[TMP28:%.*]] = icmp eq i16 [[TMP8]], 2		// CHECK2-NEXT: [[TMP27:%.*]] = icmp eq i16 [[TMP8]], 2
// CHECK2-NEXT: [[TMP29:%.*]] = and i16 [[TMP6]], 1		// CHECK2-NEXT: [[TMP28:%.*]] = and i16 [[TMP6]], 1
// CHECK2-NEXT: [[TMP30:%.*]] = icmp eq i16 [[TMP29]], 0		// CHECK2-NEXT: [[TMP29:%.*]] = icmp eq i16 [[TMP28]], 0
// CHECK2-NEXT: [[TMP31:%.*]] = and i1 [[TMP28]], [[TMP30]]		// CHECK2-NEXT: [[TMP30:%.*]] = and i1 [[TMP27]], [[TMP29]]
// CHECK2-NEXT: [[TMP32:%.*]] = icmp sgt i16 [[TMP7]], 0		// CHECK2-NEXT: [[TMP31:%.*]] = icmp sgt i16 [[TMP7]], 0
// CHECK2-NEXT: [[TMP33:%.*]] = and i1 [[TMP31]], [[TMP32]]		// CHECK2-NEXT: [[TMP32:%.*]] = and i1 [[TMP30]], [[TMP31]]
// CHECK2-NEXT: [[TMP34:%.*]] = or i1 [[TMP24]], [[TMP27]]		// CHECK2-NEXT: [[TMP33:%.*]] = or i1 [[TMP23]], [[TMP26]]
// CHECK2-NEXT: [[TMP35:%.*]] = or i1 [[TMP34]], [[TMP33]]		// CHECK2-NEXT: [[TMP34:%.*]] = or i1 [[TMP33]], [[TMP32]]
// CHECK2-NEXT: br i1 [[TMP35]], label [[THEN:%.]], label [[ELSE:%.]]		// CHECK2-NEXT: br i1 [[TMP34]], label [[THEN:%.]], label [[ELSE:%.]]
// CHECK2: then:		// CHECK2: then:
// CHECK2-NEXT: [[TMP36:%.]] = bitcast [1 x i8]* [[TMP5]] to i8*		// CHECK2-NEXT: [[TMP35:%.]] = bitcast [1 x i8]* [[TMP5]] to i8*
// CHECK2-NEXT: [[TMP37:%.]] = bitcast [1 x i8]* [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST]] to i8*		// CHECK2-NEXT: [[TMP36:%.]] = bitcast [1 x i8]* [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST]] to i8*
// CHECK2-NEXT: call void @"_omp$reduction$reduction_func"(i8* [[TMP36]], i8* [[TMP37]]) #[[ATTR5]]		// CHECK2-NEXT: call void @"_omp$reduction$reduction_func"(i8* [[TMP35]], i8* [[TMP36]]) #[[ATTR5]]
// CHECK2-NEXT: br label [[IFCONT:%.*]]		// CHECK2-NEXT: br label [[IFCONT:%.*]]
// CHECK2: else:		// CHECK2: else:
// CHECK2-NEXT: br label [[IFCONT]]		// CHECK2-NEXT: br label [[IFCONT]]
// CHECK2: ifcont:		// CHECK2: ifcont:
// CHECK2-NEXT: [[TMP38:%.*]] = icmp eq i16 [[TMP8]], 1		// CHECK2-NEXT: [[TMP37:%.*]] = icmp eq i16 [[TMP8]], 1
// CHECK2-NEXT: [[TMP39:%.*]] = icmp uge i16 [[TMP6]], [[TMP7]]		// CHECK2-NEXT: [[TMP38:%.*]] = icmp uge i16 [[TMP6]], [[TMP7]]
// CHECK2-NEXT: [[TMP40:%.*]] = and i1 [[TMP38]], [[TMP39]]		// CHECK2-NEXT: [[TMP39:%.*]] = and i1 [[TMP37]], [[TMP38]]
// CHECK2-NEXT: br i1 [[TMP40]], label [[THEN4:%.]], label [[ELSE5:%.]]		// CHECK2-NEXT: br i1 [[TMP39]], label [[THEN4:%.]], label [[ELSE5:%.]]
// CHECK2: then4:		// CHECK2: then4:
// CHECK2-NEXT: [[TMP41:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST]], i64 0, i64 0		// CHECK2-NEXT: [[TMP40:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST]], i64 0, i64 0
// CHECK2-NEXT: [[TMP42:%.]] = load i8, i8** [[TMP41]], align 8		// CHECK2-NEXT: [[TMP41:%.]] = load i8, i8** [[TMP40]], align 8
// CHECK2-NEXT: [[TMP43:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[TMP5]], i64 0, i64 0		// CHECK2-NEXT: [[TMP42:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[TMP5]], i64 0, i64 0
// CHECK2-NEXT: [[TMP44:%.]] = load i8, i8** [[TMP43]], align 8		// CHECK2-NEXT: [[TMP43:%.]] = load i8, i8** [[TMP42]], align 8
// CHECK2-NEXT: [[TMP45:%.]] = bitcast i8 [[TMP42]] to %"class.std::complex"*		// CHECK2-NEXT: [[TMP44:%.]] = bitcast i8 [[TMP41]] to %"class.std::complex"*
// CHECK2-NEXT: [[TMP46:%.]] = bitcast i8 [[TMP44]] to %"class.std::complex"*		// CHECK2-NEXT: [[TMP45:%.]] = bitcast i8 [[TMP43]] to %"class.std::complex"*
// CHECK2-NEXT: [[TMP47:%.]] = bitcast %"class.std::complex" [[TMP46]] to i8*		// CHECK2-NEXT: [[TMP46:%.]] = bitcast %"class.std::complex" [[TMP45]] to i8*
// CHECK2-NEXT: [[TMP48:%.]] = bitcast %"class.std::complex" [[TMP45]] to i8*		// CHECK2-NEXT: [[TMP47:%.]] = bitcast %"class.std::complex" [[TMP44]] to i8*
// CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP47]], i8* align 4 [[TMP48]], i64 8, i1 false), !tbaa.struct !21		// CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP46]], i8* align 4 [[TMP47]], i64 8, i1 false), !tbaa.struct !21
// CHECK2-NEXT: br label [[IFCONT6:%.*]]		// CHECK2-NEXT: br label [[IFCONT6:%.*]]
// CHECK2: else5:		// CHECK2: else5:
// CHECK2-NEXT: br label [[IFCONT6]]		// CHECK2-NEXT: br label [[IFCONT6]]
// CHECK2: ifcont6:		// CHECK2: ifcont6:
// CHECK2-NEXT: ret void		// CHECK2-NEXT: ret void
//		//
//		//
// CHECK2-LABEL: define {{[^@]+}}@_omp_reduction_inter_warp_copy_func		// CHECK2-LABEL: define {{[^@]+}}@_omp_reduction_inter_warp_copy_func
// CHECK2-SAME: (i8* [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR6]] {		// CHECK2-SAME: (i8* [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR6]] {
// CHECK2-NEXT: entry:		// CHECK2-NEXT: entry:
// CHECK2-NEXT: [[DOTADDR:%.]] = alloca i8, align 8		// CHECK2-NEXT: [[DOTADDR:%.]] = alloca i8, align 8
// CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4		// CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
// CHECK2-NEXT: [[DOTCNT_ADDR:%.*]] = alloca i32, align 4		// CHECK2-NEXT: [[DOTCNT_ADDR:%.*]] = alloca i32, align 4
// CHECK2-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB1]])		// CHECK2-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB1]])
// CHECK2-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8, !tbaa [[TBAA12]]		// CHECK2-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8, !tbaa [[TBAA12]]
// CHECK2-NEXT: store i32 [[TMP1]], i32* [[DOTADDR1]], align 4, !tbaa [[TBAA8]]		// CHECK2-NEXT: store i32 [[TMP1]], i32* [[DOTADDR1]], align 4, !tbaa [[TBAA8]]
// CHECK2-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block()		// CHECK2-NEXT: [[NVPTX_TID:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block()
// CHECK2-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block()		// CHECK2-NEXT: [[NVPTX_TID2:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block()
// CHECK2-NEXT: [[NVPTX_LANE_ID:%.*]] = and i32 [[TMP4]], 31		// CHECK2-NEXT: [[NVPTX_LANE_ID:%.*]] = and i32 [[NVPTX_TID2]], 31
// CHECK2-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block()		// CHECK2-NEXT: [[NVPTX_TID3:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block()
// CHECK2-NEXT: [[NVPTX_WARP_ID:%.*]] = ashr i32 [[TMP5]], 5		// CHECK2-NEXT: [[NVPTX_WARP_ID:%.*]] = ashr i32 [[NVPTX_TID3]], 5
// CHECK2-NEXT: [[TMP6:%.]] = load i8, i8** [[DOTADDR]], align 8		// CHECK2-NEXT: [[TMP3:%.]] = load i8, i8** [[DOTADDR]], align 8
// CHECK2-NEXT: [[TMP7:%.]] = bitcast i8 [[TMP6]] to [1 x i8]		// CHECK2-NEXT: [[TMP4:%.]] = bitcast i8 [[TMP3]] to [1 x i8]
// CHECK2-NEXT: store i32 0, i32* [[DOTCNT_ADDR]], align 4, !tbaa [[TBAA8]]		// CHECK2-NEXT: store i32 0, i32* [[DOTCNT_ADDR]], align 4, !tbaa [[TBAA8]]
// CHECK2-NEXT: br label [[PRECOND:%.*]]		// CHECK2-NEXT: br label [[PRECOND:%.*]]
// CHECK2: precond:		// CHECK2: precond:
// CHECK2-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTCNT_ADDR]], align 4, !tbaa [[TBAA8]]		// CHECK2-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTCNT_ADDR]], align 4, !tbaa [[TBAA8]]
// CHECK2-NEXT: [[TMP9:%.*]] = icmp ult i32 [[TMP8]], 2		// CHECK2-NEXT: [[TMP6:%.*]] = icmp ult i32 [[TMP5]], 2
// CHECK2-NEXT: br i1 [[TMP9]], label [[BODY:%.]], label [[EXIT:%.]]		// CHECK2-NEXT: br i1 [[TMP6]], label [[BODY:%.]], label [[EXIT:%.]]
// CHECK2: body:		// CHECK2: body:
// CHECK2-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB4:[0-9]+]], i32 [[TMP2]])		// CHECK2-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB4:[0-9]+]], i32 [[TMP2]])
// CHECK2-NEXT: [[WARP_MASTER:%.*]] = icmp eq i32 [[NVPTX_LANE_ID]], 0		// CHECK2-NEXT: [[WARP_MASTER:%.*]] = icmp eq i32 [[NVPTX_LANE_ID]], 0
// CHECK2-NEXT: br i1 [[WARP_MASTER]], label [[THEN:%.]], label [[ELSE:%.]]		// CHECK2-NEXT: br i1 [[WARP_MASTER]], label [[THEN:%.]], label [[ELSE:%.]]
// CHECK2: then:		// CHECK2: then:
// CHECK2-NEXT: [[TMP10:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[TMP7]], i64 0, i64 0		// CHECK2-NEXT: [[TMP7:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[TMP4]], i64 0, i64 0
// CHECK2-NEXT: [[TMP11:%.]] = load i8, i8** [[TMP10]], align 8, !tbaa [[TBAA12]]		// CHECK2-NEXT: [[TMP8:%.]] = load i8, i8** [[TMP7]], align 8, !tbaa [[TBAA12]]
// CHECK2-NEXT: [[TMP12:%.]] = bitcast i8 [[TMP11]] to i32*		// CHECK2-NEXT: [[TMP9:%.]] = bitcast i8 [[TMP8]] to i32*
// CHECK2-NEXT: [[TMP13:%.]] = getelementptr i32, i32 [[TMP12]], i32 [[TMP8]]		// CHECK2-NEXT: [[TMP10:%.]] = getelementptr i32, i32 [[TMP9]], i32 [[TMP5]]
// CHECK2-NEXT: [[TMP14:%.]] = getelementptr inbounds [32 x i32], [32 x i32] addrspace(3) @__openmp_nvptx_data_transfer_temporary_storage, i64 0, i32 [[NVPTX_WARP_ID]]		// CHECK2-NEXT: [[TMP11:%.]] = getelementptr inbounds [32 x i32], [32 x i32] addrspace(3) @__openmp_nvptx_data_transfer_temporary_storage, i64 0, i32 [[NVPTX_WARP_ID]]
// CHECK2-NEXT: [[TMP15:%.]] = load i32, i32 [[TMP13]], align 4		// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32 [[TMP10]], align 4
// CHECK2-NEXT: store volatile i32 [[TMP15]], i32 addrspace(3)* [[TMP14]], align 4		// CHECK2-NEXT: store volatile i32 [[TMP12]], i32 addrspace(3)* [[TMP11]], align 4
// CHECK2-NEXT: br label [[IFCONT:%.*]]		// CHECK2-NEXT: br label [[IFCONT:%.*]]
// CHECK2: else:		// CHECK2: else:
// CHECK2-NEXT: br label [[IFCONT]]		// CHECK2-NEXT: br label [[IFCONT]]
// CHECK2: ifcont:		// CHECK2: ifcont:
// CHECK2-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB4]], i32 [[TMP2]])		// CHECK2-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB4]], i32 [[TMP2]])
// CHECK2-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTADDR1]], align 4, !tbaa [[TBAA8]]		// CHECK2-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTADDR1]], align 4, !tbaa [[TBAA8]]
// CHECK2-NEXT: [[IS_ACTIVE_THREAD:%.*]] = icmp ult i32 [[TMP3]], [[TMP16]]		// CHECK2-NEXT: [[IS_ACTIVE_THREAD:%.*]] = icmp ult i32 [[NVPTX_TID]], [[TMP13]]
// CHECK2-NEXT: br i1 [[IS_ACTIVE_THREAD]], label [[THEN2:%.]], label [[ELSE3:%.]]		// CHECK2-NEXT: br i1 [[IS_ACTIVE_THREAD]], label [[THEN4:%.]], label [[ELSE5:%.]]
// CHECK2: then2:		// CHECK2: then2:
// CHECK2-NEXT: [[TMP17:%.]] = getelementptr inbounds [32 x i32], [32 x i32] addrspace(3) @__openmp_nvptx_data_transfer_temporary_storage, i64 0, i32 [[TMP3]]		// CHECK2-NEXT: [[TMP14:%.]] = getelementptr inbounds [32 x i32], [32 x i32] addrspace(3) @__openmp_nvptx_data_transfer_temporary_storage, i64 0, i32 [[NVPTX_TID]]
// CHECK2-NEXT: [[TMP18:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[TMP7]], i64 0, i64 0		// CHECK2-NEXT: [[TMP15:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[TMP4]], i64 0, i64 0
// CHECK2-NEXT: [[TMP19:%.]] = load i8, i8** [[TMP18]], align 8, !tbaa [[TBAA12]]		// CHECK2-NEXT: [[TMP16:%.]] = load i8, i8** [[TMP15]], align 8, !tbaa [[TBAA12]]
// CHECK2-NEXT: [[TMP20:%.]] = bitcast i8 [[TMP19]] to i32*		// CHECK2-NEXT: [[TMP17:%.]] = bitcast i8 [[TMP16]] to i32*
// CHECK2-NEXT: [[TMP21:%.]] = getelementptr i32, i32 [[TMP20]], i32 [[TMP8]]		// CHECK2-NEXT: [[TMP18:%.]] = getelementptr i32, i32 [[TMP17]], i32 [[TMP5]]
// CHECK2-NEXT: [[TMP22:%.]] = load volatile i32, i32 addrspace(3) [[TMP17]], align 4, !tbaa [[TBAA8]]		// CHECK2-NEXT: [[TMP19:%.]] = load volatile i32, i32 addrspace(3) [[TMP14]], align 4, !tbaa [[TBAA8]]
// CHECK2-NEXT: store i32 [[TMP22]], i32* [[TMP21]], align 4, !tbaa [[TBAA8]]		// CHECK2-NEXT: store i32 [[TMP19]], i32* [[TMP18]], align 4, !tbaa [[TBAA8]]
// CHECK2-NEXT: br label [[IFCONT4:%.*]]		// CHECK2-NEXT: br label [[IFCONT6:%.*]]
// CHECK2: else3:		// CHECK2: else3:
// CHECK2-NEXT: br label [[IFCONT4]]		// CHECK2-NEXT: br label [[IFCONT6]]
// CHECK2: ifcont4:		// CHECK2: ifcont4:
// CHECK2-NEXT: [[TMP23:%.*]] = add nsw i32 [[TMP8]], 1		// CHECK2-NEXT: [[TMP20:%.*]] = add nsw i32 [[TMP5]], 1
// CHECK2-NEXT: store i32 [[TMP23]], i32* [[DOTCNT_ADDR]], align 4, !tbaa [[TBAA8]]		// CHECK2-NEXT: store i32 [[TMP20]], i32* [[DOTCNT_ADDR]], align 4, !tbaa [[TBAA8]]
// CHECK2-NEXT: br label [[PRECOND]]		// CHECK2-NEXT: br label [[PRECOND]]
// CHECK2: exit:		// CHECK2: exit:
// CHECK2-NEXT: ret void		// CHECK2-NEXT: ret void
//		//
//		//
// CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__1_wrapper		// CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__1_wrapper
// CHECK2-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR6]] {		// CHECK2-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR6]] {
// CHECK2-NEXT: entry:		// CHECK2-NEXT: entry:
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// CHECK2-NEXT: ret void		// CHECK2-NEXT: ret void
//		//
//		//
// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z17complex_reductionIdEvv_l16		// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z17complex_reductionIdEvv_l16
// CHECK2-SAME: () #[[ATTR0]] {		// CHECK2-SAME: () #[[ATTR0]] {
// CHECK2-NEXT: entry:		// CHECK2-NEXT: entry:
// CHECK2-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4		// CHECK2-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
// CHECK2-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4		// CHECK2-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
// CHECK2-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 1, i1 true, i1 true)		// CHECK2-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z17complex_reductionIdEvv_l16_kernel_info, i1 true)
// CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1		// CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]		// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
// CHECK2: user_code.entry:		// CHECK2: user_code.entry:
// CHECK2-NEXT: [[TMP1:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB1]])		// CHECK2-NEXT: [[TMP1:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB1]])
// CHECK2-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4		// CHECK2-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
// CHECK2-NEXT: store i32 [[TMP1]], i32* [[DOTTHREADID_TEMP_]], align 4, !tbaa [[TBAA8]]		// CHECK2-NEXT: store i32 [[TMP1]], i32* [[DOTTHREADID_TEMP_]], align 4, !tbaa [[TBAA8]]
// CHECK2-NEXT: call void @__omp_outlined__2(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]]) #[[ATTR5]]		// CHECK2-NEXT: call void @__omp_outlined__2(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]]) #[[ATTR5]]
// CHECK2-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true)		// CHECK2-NEXT: call void @__kmpc_target_deinit(i1 true)
// CHECK2-NEXT: ret void		// CHECK2-NEXT: ret void
// CHECK2: worker.exit:		// CHECK2: worker.exit:
// CHECK2-NEXT: ret void		// CHECK2-NEXT: ret void
//		//
//		//
// CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__2		// CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__2
// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {		// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
// CHECK2-NEXT: entry:		// CHECK2-NEXT: entry:
// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8		// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8
// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8		// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8
// CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4		// CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
// CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4		// CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4
// CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4		// CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
// CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4		// CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
// CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4		// CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
// CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4		// CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
// CHECK2-NEXT: [[IB:%.*]] = alloca i32, align 4		// CHECK2-NEXT: [[IB:%.*]] = alloca i32, align 4
// CHECK2-NEXT: [[REF_TMP:%.*]] = alloca double, align 8		// CHECK2-NEXT: [[REF_TMP:%.*]] = alloca double, align 8
// CHECK2-NEXT: [[REF_TMP2:%.*]] = alloca double, align 8		// CHECK2-NEXT: [[REF_TMP2:%.*]] = alloca double, align 8
// CHECK2-NEXT: [[CAPTURED_VARS_ADDRS:%.]] = alloca [3 x i8], align 8		// CHECK2-NEXT: [[CAPTURED_VARS_ADDRS:%.]] = alloca [3 x i8], align 8
// CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8, !tbaa [[TBAA12]]		// CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8, !tbaa [[TBAA12]]
// CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8, !tbaa [[TBAA12]]		// CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8, !tbaa [[TBAA12]]
// CHECK2-NEXT: [[ISTART:%.]] = call align 16 i8 @__kmpc_alloc_shared(i64 4)		// CHECK2-NEXT: [[ISTART:%.]] = call i8 @__kmpc_alloc_shared(i64 4)
// CHECK2-NEXT: [[ISTART_ON_STACK:%.]] = bitcast i8 [[ISTART]] to i32*		// CHECK2-NEXT: [[ISTART_ON_STACK:%.]] = bitcast i8 [[ISTART]] to i32*
// CHECK2-NEXT: [[IEND:%.]] = call align 16 i8 @__kmpc_alloc_shared(i64 4)		// CHECK2-NEXT: [[IEND:%.]] = call i8 @__kmpc_alloc_shared(i64 4)
// CHECK2-NEXT: [[IEND_ON_STACK:%.]] = bitcast i8 [[IEND]] to i32*		// CHECK2-NEXT: [[IEND_ON_STACK:%.]] = bitcast i8 [[IEND]] to i32*
// CHECK2-NEXT: [[PARTIAL_SUM:%.]] = call align 16 i8 @__kmpc_alloc_shared(i64 16)		// CHECK2-NEXT: [[PARTIAL_SUM:%.]] = call i8 @__kmpc_alloc_shared(i64 16)
// CHECK2-NEXT: [[PARTIAL_SUM_ON_STACK:%.]] = bitcast i8 [[PARTIAL_SUM]] to %"class.std::complex.0"*		// CHECK2-NEXT: [[PARTIAL_SUM_ON_STACK:%.]] = bitcast i8 [[PARTIAL_SUM]] to %"class.std::complex.0"*
// CHECK2-NEXT: [[TMP0:%.]] = bitcast i32 [[DOTOMP_IV]] to i8*		// CHECK2-NEXT: [[TMP0:%.]] = bitcast i32 [[DOTOMP_IV]] to i8*
// CHECK2-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP0]]) #[[ATTR5]]		// CHECK2-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP0]]) #[[ATTR5]]
// CHECK2-NEXT: [[TMP1:%.]] = bitcast i32 [[DOTOMP_LB]] to i8*		// CHECK2-NEXT: [[TMP1:%.]] = bitcast i32 [[DOTOMP_LB]] to i8*
// CHECK2-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP1]]) #[[ATTR5]]		// CHECK2-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP1]]) #[[ATTR5]]
// CHECK2-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4, !tbaa [[TBAA8]]		// CHECK2-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4, !tbaa [[TBAA8]]
// CHECK2-NEXT: [[TMP2:%.]] = bitcast i32 [[DOTOMP_UB]] to i8*		// CHECK2-NEXT: [[TMP2:%.]] = bitcast i32 [[DOTOMP_UB]] to i8*
// CHECK2-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP2]]) #[[ATTR5]]		// CHECK2-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP2]]) #[[ATTR5]]
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// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]		// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK2-NEXT: store i32 [[ADD]], i32* [[IB]], align 4, !tbaa [[TBAA8]]		// CHECK2-NEXT: store i32 [[ADD]], i32* [[IB]], align 4, !tbaa [[TBAA8]]
// CHECK2-NEXT: [[TMP14:%.]] = bitcast double [[REF_TMP]] to i8*		// CHECK2-NEXT: [[TMP14:%.]] = bitcast double [[REF_TMP]] to i8*
// CHECK2-NEXT: call void @llvm.lifetime.start.p0i8(i64 8, i8* [[TMP14]]) #[[ATTR5]]		// CHECK2-NEXT: call void @llvm.lifetime.start.p0i8(i64 8, i8* [[TMP14]]) #[[ATTR5]]
// CHECK2-NEXT: store double 0.000000e+00, double* [[REF_TMP]], align 8, !tbaa [[TBAA22:![0-9]+]]		// CHECK2-NEXT: store double 0.000000e+00, double* [[REF_TMP]], align 8, !tbaa [[TBAA22:![0-9]+]]
// CHECK2-NEXT: [[TMP15:%.]] = bitcast double [[REF_TMP2]] to i8*		// CHECK2-NEXT: [[TMP15:%.]] = bitcast double [[REF_TMP2]] to i8*
// CHECK2-NEXT: call void @llvm.lifetime.start.p0i8(i64 8, i8* [[TMP15]]) #[[ATTR5]]		// CHECK2-NEXT: call void @llvm.lifetime.start.p0i8(i64 8, i8* [[TMP15]]) #[[ATTR5]]
// CHECK2-NEXT: store double 0.000000e+00, double* [[REF_TMP2]], align 8, !tbaa [[TBAA22]]		// CHECK2-NEXT: store double 0.000000e+00, double* [[REF_TMP2]], align 8, !tbaa [[TBAA22]]
// CHECK2-NEXT: call void @_ZNSt7complexIdEC1ERKdS2_(%"class.std::complex.0"* nonnull align 8 dereferenceable(16) [[PARTIAL_SUM_ON_STACK]], double* nonnull align 8 dereferenceable(8) [[REF_TMP]], double* nonnull align 8 dereferenceable(8) [[REF_TMP2]]) #[[ATTR10]]		// CHECK2-NEXT: call void @_ZNSt7complexIdEC1ERKdS2_(%"class.std::complex.0"* nonnull align 8 dereferenceable(16) [[PARTIAL_SUM_ON_STACK]], double* nonnull align 8 dereferenceable(8) [[REF_TMP]], double* nonnull align 8 dereferenceable(8) [[REF_TMP2]]) #[[ATTR12]]
// CHECK2-NEXT: [[TMP16:%.]] = bitcast double [[REF_TMP2]] to i8*		// CHECK2-NEXT: [[TMP16:%.]] = bitcast double [[REF_TMP2]] to i8*
// CHECK2-NEXT: call void @llvm.lifetime.end.p0i8(i64 8, i8* [[TMP16]]) #[[ATTR5]]		// CHECK2-NEXT: call void @llvm.lifetime.end.p0i8(i64 8, i8* [[TMP16]]) #[[ATTR5]]
// CHECK2-NEXT: [[TMP17:%.]] = bitcast double [[REF_TMP]] to i8*		// CHECK2-NEXT: [[TMP17:%.]] = bitcast double [[REF_TMP]] to i8*
// CHECK2-NEXT: call void @llvm.lifetime.end.p0i8(i64 8, i8* [[TMP17]]) #[[ATTR5]]		// CHECK2-NEXT: call void @llvm.lifetime.end.p0i8(i64 8, i8* [[TMP17]]) #[[ATTR5]]
// CHECK2-NEXT: [[TMP18:%.]] = load i32, i32 [[IB]], align 4, !tbaa [[TBAA8]]		// CHECK2-NEXT: [[TMP18:%.]] = load i32, i32 [[IB]], align 4, !tbaa [[TBAA8]]
// CHECK2-NEXT: [[MUL3:%.*]] = mul nsw i32 [[TMP18]], 4		// CHECK2-NEXT: [[MUL3:%.*]] = mul nsw i32 [[TMP18]], 4
// CHECK2-NEXT: store i32 [[MUL3]], i32* [[ISTART_ON_STACK]], align 4, !tbaa [[TBAA8]]		// CHECK2-NEXT: store i32 [[MUL3]], i32* [[ISTART_ON_STACK]], align 4, !tbaa [[TBAA8]]
// CHECK2-NEXT: [[TMP19:%.]] = load i32, i32 [[IB]], align 4, !tbaa [[TBAA8]]		// CHECK2-NEXT: [[TMP19:%.]] = load i32, i32 [[IB]], align 4, !tbaa [[TBAA8]]
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// CHECK2-NEXT: [[__RE_ADDR:%.]] = alloca double, align 8		// CHECK2-NEXT: [[__RE_ADDR:%.]] = alloca double, align 8
// CHECK2-NEXT: [[__IM_ADDR:%.]] = alloca double, align 8		// CHECK2-NEXT: [[__IM_ADDR:%.]] = alloca double, align 8
// CHECK2-NEXT: store %"class.std::complex.0"* [[THIS]], %"class.std::complex.0"** [[THIS_ADDR]], align 8, !tbaa [[TBAA12]]		// CHECK2-NEXT: store %"class.std::complex.0"* [[THIS]], %"class.std::complex.0"** [[THIS_ADDR]], align 8, !tbaa [[TBAA12]]
// CHECK2-NEXT: store double* [[__RE]], double** [[__RE_ADDR]], align 8, !tbaa [[TBAA12]]		// CHECK2-NEXT: store double* [[__RE]], double** [[__RE_ADDR]], align 8, !tbaa [[TBAA12]]
// CHECK2-NEXT: store double* [[__IM]], double** [[__IM_ADDR]], align 8, !tbaa [[TBAA12]]		// CHECK2-NEXT: store double* [[__IM]], double** [[__IM_ADDR]], align 8, !tbaa [[TBAA12]]
// CHECK2-NEXT: [[THIS1:%.]] = load %"class.std::complex.0", %"class.std::complex.0"** [[THIS_ADDR]], align 8		// CHECK2-NEXT: [[THIS1:%.]] = load %"class.std::complex.0", %"class.std::complex.0"** [[THIS_ADDR]], align 8
// CHECK2-NEXT: [[TMP0:%.]] = load double, double** [[__RE_ADDR]], align 8		// CHECK2-NEXT: [[TMP0:%.]] = load double, double** [[__RE_ADDR]], align 8
// CHECK2-NEXT: [[TMP1:%.]] = load double, double** [[__IM_ADDR]], align 8		// CHECK2-NEXT: [[TMP1:%.]] = load double, double** [[__IM_ADDR]], align 8
// CHECK2-NEXT: call void @_ZNSt7complexIdEC2ERKdS2_(%"class.std::complex.0"* nonnull align 8 dereferenceable(16) [[THIS1]], double* nonnull align 8 dereferenceable(8) [[TMP0]], double* nonnull align 8 dereferenceable(8) [[TMP1]]) #[[ATTR10]]		// CHECK2-NEXT: call void @_ZNSt7complexIdEC2ERKdS2_(%"class.std::complex.0"* nonnull align 8 dereferenceable(16) [[THIS1]], double* nonnull align 8 dereferenceable(8) [[TMP0]], double* nonnull align 8 dereferenceable(8) [[TMP1]]) #[[ATTR12]]
// CHECK2-NEXT: ret void		// CHECK2-NEXT: ret void
//		//
//		//
// CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__3		// CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__3
// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i32 nonnull align 4 dereferenceable(4) [[ISTART:%.]], i32 nonnull align 4 dereferenceable(4) [[IEND:%.]], %"class.std::complex.0" nonnull align 8 dereferenceable(16) [[PARTIAL_SUM:%.*]]) #[[ATTR0]] {		// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i32 nonnull align 4 dereferenceable(4) [[ISTART:%.]], i32 nonnull align 4 dereferenceable(4) [[IEND:%.]], %"class.std::complex.0" nonnull align 8 dereferenceable(16) [[PARTIAL_SUM:%.*]]) #[[ATTR0]] {
// CHECK2-NEXT: entry:		// CHECK2-NEXT: entry:
// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8		// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8
// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8		// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8
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// CHECK2-NEXT: [[TMP21:%.]] = bitcast %"class.std::complex.0" [[PARTIAL_SUM5]] to i8*		// CHECK2-NEXT: [[TMP21:%.]] = bitcast %"class.std::complex.0" [[PARTIAL_SUM5]] to i8*
// CHECK2-NEXT: call void @llvm.lifetime.start.p0i8(i64 16, i8* [[TMP21]]) #[[ATTR5]]		// CHECK2-NEXT: call void @llvm.lifetime.start.p0i8(i64 16, i8* [[TMP21]]) #[[ATTR5]]
// CHECK2-NEXT: [[TMP22:%.]] = bitcast double [[REF_TMP]] to i8*		// CHECK2-NEXT: [[TMP22:%.]] = bitcast double [[REF_TMP]] to i8*
// CHECK2-NEXT: call void @llvm.lifetime.start.p0i8(i64 8, i8* [[TMP22]]) #[[ATTR5]]		// CHECK2-NEXT: call void @llvm.lifetime.start.p0i8(i64 8, i8* [[TMP22]]) #[[ATTR5]]
// CHECK2-NEXT: store double 0.000000e+00, double* [[REF_TMP]], align 8, !tbaa [[TBAA22]]		// CHECK2-NEXT: store double 0.000000e+00, double* [[REF_TMP]], align 8, !tbaa [[TBAA22]]
// CHECK2-NEXT: [[TMP23:%.]] = bitcast double [[REF_TMP6]] to i8*		// CHECK2-NEXT: [[TMP23:%.]] = bitcast double [[REF_TMP6]] to i8*
// CHECK2-NEXT: call void @llvm.lifetime.start.p0i8(i64 8, i8* [[TMP23]]) #[[ATTR5]]		// CHECK2-NEXT: call void @llvm.lifetime.start.p0i8(i64 8, i8* [[TMP23]]) #[[ATTR5]]
// CHECK2-NEXT: store double 0.000000e+00, double* [[REF_TMP6]], align 8, !tbaa [[TBAA22]]		// CHECK2-NEXT: store double 0.000000e+00, double* [[REF_TMP6]], align 8, !tbaa [[TBAA22]]
// CHECK2-NEXT: call void @_ZNSt7complexIdEC1ERKdS2_(%"class.std::complex.0"* nonnull align 8 dereferenceable(16) [[PARTIAL_SUM5]], double* nonnull align 8 dereferenceable(8) [[REF_TMP]], double* nonnull align 8 dereferenceable(8) [[REF_TMP6]]) #[[ATTR10]]		// CHECK2-NEXT: call void @_ZNSt7complexIdEC1ERKdS2_(%"class.std::complex.0"* nonnull align 8 dereferenceable(16) [[PARTIAL_SUM5]], double* nonnull align 8 dereferenceable(8) [[REF_TMP]], double* nonnull align 8 dereferenceable(8) [[REF_TMP6]]) #[[ATTR12]]
// CHECK2-NEXT: [[TMP24:%.]] = bitcast double [[REF_TMP6]] to i8*		// CHECK2-NEXT: [[TMP24:%.]] = bitcast double [[REF_TMP6]] to i8*
// CHECK2-NEXT: call void @llvm.lifetime.end.p0i8(i64 8, i8* [[TMP24]]) #[[ATTR5]]		// CHECK2-NEXT: call void @llvm.lifetime.end.p0i8(i64 8, i8* [[TMP24]]) #[[ATTR5]]
// CHECK2-NEXT: [[TMP25:%.]] = bitcast double [[REF_TMP]] to i8*		// CHECK2-NEXT: [[TMP25:%.]] = bitcast double [[REF_TMP]] to i8*
// CHECK2-NEXT: call void @llvm.lifetime.end.p0i8(i64 8, i8* [[TMP25]]) #[[ATTR5]]		// CHECK2-NEXT: call void @llvm.lifetime.end.p0i8(i64 8, i8* [[TMP25]]) #[[ATTR5]]
// CHECK2-NEXT: [[TMP26:%.]] = bitcast i32 [[I7]] to i8*		// CHECK2-NEXT: [[TMP26:%.]] = bitcast i32 [[I7]] to i8*
// CHECK2-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP26]]) #[[ATTR5]]		// CHECK2-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP26]]) #[[ATTR5]]
// CHECK2-NEXT: [[TMP27:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8		// CHECK2-NEXT: [[TMP27:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK2-NEXT: [[TMP28:%.]] = load i32, i32 [[TMP27]], align 4, !tbaa [[TBAA8]]		// CHECK2-NEXT: [[TMP28:%.]] = load i32, i32 [[TMP27]], align 4, !tbaa [[TBAA8]]
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// CHECK2-NEXT: [[TMP42:%.]] = load i32, i32 [[I7]], align 4, !tbaa [[TBAA8]]		// CHECK2-NEXT: [[TMP42:%.]] = load i32, i32 [[I7]], align 4, !tbaa [[TBAA8]]
// CHECK2-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP42]] to double		// CHECK2-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP42]] to double
// CHECK2-NEXT: store double [[CONV]], double* [[REF_TMP15]], align 8, !tbaa [[TBAA22]]		// CHECK2-NEXT: store double [[CONV]], double* [[REF_TMP15]], align 8, !tbaa [[TBAA22]]
// CHECK2-NEXT: [[TMP43:%.]] = bitcast double [[REF_TMP16]] to i8*		// CHECK2-NEXT: [[TMP43:%.]] = bitcast double [[REF_TMP16]] to i8*
// CHECK2-NEXT: call void @llvm.lifetime.start.p0i8(i64 8, i8* [[TMP43]]) #[[ATTR5]]		// CHECK2-NEXT: call void @llvm.lifetime.start.p0i8(i64 8, i8* [[TMP43]]) #[[ATTR5]]
// CHECK2-NEXT: [[TMP44:%.]] = load i32, i32 [[I7]], align 4, !tbaa [[TBAA8]]		// CHECK2-NEXT: [[TMP44:%.]] = load i32, i32 [[I7]], align 4, !tbaa [[TBAA8]]
// CHECK2-NEXT: [[CONV17:%.*]] = sitofp i32 [[TMP44]] to double		// CHECK2-NEXT: [[CONV17:%.*]] = sitofp i32 [[TMP44]] to double
// CHECK2-NEXT: store double [[CONV17]], double* [[REF_TMP16]], align 8, !tbaa [[TBAA22]]		// CHECK2-NEXT: store double [[CONV17]], double* [[REF_TMP16]], align 8, !tbaa [[TBAA22]]
// CHECK2-NEXT: call void @_ZNSt7complexIdEC1ERKdS2_(%"class.std::complex.0"* nonnull align 8 dereferenceable(16) [[REF_TMP14]], double* nonnull align 8 dereferenceable(8) [[REF_TMP15]], double* nonnull align 8 dereferenceable(8) [[REF_TMP16]]) #[[ATTR10]]		// CHECK2-NEXT: call void @_ZNSt7complexIdEC1ERKdS2_(%"class.std::complex.0"* nonnull align 8 dereferenceable(16) [[REF_TMP14]], double* nonnull align 8 dereferenceable(8) [[REF_TMP15]], double* nonnull align 8 dereferenceable(8) [[REF_TMP16]]) #[[ATTR12]]
// CHECK2-NEXT: [[CALL:%.]] = call nonnull align 8 dereferenceable(16) %"class.std::complex.0" @_ZNSt7complexIdEpLIdEERS0_RKS_IT_E(%"class.std::complex.0"* nonnull align 8 dereferenceable(16) [[PARTIAL_SUM5]], %"class.std::complex.0"* nonnull align 8 dereferenceable(16) [[REF_TMP14]]) #[[ATTR10]]		// CHECK2-NEXT: [[CALL:%.]] = call nonnull align 8 dereferenceable(16) %"class.std::complex.0" @_ZNSt7complexIdEpLIdEERS0_RKS_IT_E(%"class.std::complex.0"* nonnull align 8 dereferenceable(16) [[PARTIAL_SUM5]], %"class.std::complex.0"* nonnull align 8 dereferenceable(16) [[REF_TMP14]]) #[[ATTR12]]
// CHECK2-NEXT: [[TMP45:%.]] = bitcast double [[REF_TMP16]] to i8*		// CHECK2-NEXT: [[TMP45:%.]] = bitcast double [[REF_TMP16]] to i8*
// CHECK2-NEXT: call void @llvm.lifetime.end.p0i8(i64 8, i8* [[TMP45]]) #[[ATTR5]]		// CHECK2-NEXT: call void @llvm.lifetime.end.p0i8(i64 8, i8* [[TMP45]]) #[[ATTR5]]
// CHECK2-NEXT: [[TMP46:%.]] = bitcast double [[REF_TMP15]] to i8*		// CHECK2-NEXT: [[TMP46:%.]] = bitcast double [[REF_TMP15]] to i8*
// CHECK2-NEXT: call void @llvm.lifetime.end.p0i8(i64 8, i8* [[TMP46]]) #[[ATTR5]]		// CHECK2-NEXT: call void @llvm.lifetime.end.p0i8(i64 8, i8* [[TMP46]]) #[[ATTR5]]
// CHECK2-NEXT: [[TMP47:%.]] = bitcast %"class.std::complex.0" [[REF_TMP14]] to i8*		// CHECK2-NEXT: [[TMP47:%.]] = bitcast %"class.std::complex.0" [[REF_TMP14]] to i8*
// CHECK2-NEXT: call void @llvm.lifetime.end.p0i8(i64 16, i8* [[TMP47]]) #[[ATTR5]]		// CHECK2-NEXT: call void @llvm.lifetime.end.p0i8(i64 16, i8* [[TMP47]]) #[[ATTR5]]
// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]		// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK2: omp.body.continue:		// CHECK2: omp.body.continue:
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// CHECK2-NEXT: [[TMP57:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0		// CHECK2-NEXT: [[TMP57:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0
// CHECK2-NEXT: [[TMP58:%.]] = bitcast %"class.std::complex.0" [[PARTIAL_SUM5]] to i8*		// CHECK2-NEXT: [[TMP58:%.]] = bitcast %"class.std::complex.0" [[PARTIAL_SUM5]] to i8*
// CHECK2-NEXT: store i8* [[TMP58]], i8** [[TMP57]], align 8		// CHECK2-NEXT: store i8* [[TMP58]], i8** [[TMP57]], align 8
// CHECK2-NEXT: [[TMP59:%.]] = bitcast [1 x i8]* [[DOTOMP_REDUCTION_RED_LIST]] to i8*		// CHECK2-NEXT: [[TMP59:%.]] = bitcast [1 x i8]* [[DOTOMP_REDUCTION_RED_LIST]] to i8*
// CHECK2-NEXT: [[TMP60:%.]] = call i32 @__kmpc_nvptx_parallel_reduce_nowait_v2(%struct.ident_t @[[GLOB1]], i32 [[TMP56]], i32 1, i64 8, i8* [[TMP59]], void (i8, i16, i16, i16) @_omp_reduction_shuffle_and_reduce_func5, void (i8, i32) @_omp_reduction_inter_warp_copy_func6)		// CHECK2-NEXT: [[TMP60:%.]] = call i32 @__kmpc_nvptx_parallel_reduce_nowait_v2(%struct.ident_t @[[GLOB1]], i32 [[TMP56]], i32 1, i64 8, i8* [[TMP59]], void (i8, i16, i16, i16) @_omp_reduction_shuffle_and_reduce_func5, void (i8, i32) @_omp_reduction_inter_warp_copy_func6)
// CHECK2-NEXT: [[TMP61:%.*]] = icmp eq i32 [[TMP60]], 1		// CHECK2-NEXT: [[TMP61:%.*]] = icmp eq i32 [[TMP60]], 1
// CHECK2-NEXT: br i1 [[TMP61]], label [[DOTOMP_REDUCTION_THEN:%.]], label [[DOTOMP_REDUCTION_DONE:%.]]		// CHECK2-NEXT: br i1 [[TMP61]], label [[DOTOMP_REDUCTION_THEN:%.]], label [[DOTOMP_REDUCTION_DONE:%.]]
// CHECK2: .omp.reduction.then:		// CHECK2: .omp.reduction.then:
// CHECK2-NEXT: [[CALL21:%.]] = call nonnull align 8 dereferenceable(16) %"class.std::complex.0" @_ZNSt7complexIdEpLIdEERS0_RKS_IT_E(%"class.std::complex.0"* nonnull align 8 dereferenceable(16) [[TMP2]], %"class.std::complex.0"* nonnull align 8 dereferenceable(16) [[PARTIAL_SUM5]]) #[[ATTR10]]		// CHECK2-NEXT: [[CALL21:%.]] = call nonnull align 8 dereferenceable(16) %"class.std::complex.0" @_ZNSt7complexIdEpLIdEERS0_RKS_IT_E(%"class.std::complex.0"* nonnull align 8 dereferenceable(16) [[TMP2]], %"class.std::complex.0"* nonnull align 8 dereferenceable(16) [[PARTIAL_SUM5]]) #[[ATTR12]]
// CHECK2-NEXT: call void @__kmpc_nvptx_end_reduce_nowait(i32 [[TMP56]])		// CHECK2-NEXT: call void @__kmpc_nvptx_end_reduce_nowait(i32 [[TMP56]])
// CHECK2-NEXT: br label [[DOTOMP_REDUCTION_DONE]]		// CHECK2-NEXT: br label [[DOTOMP_REDUCTION_DONE]]
// CHECK2: .omp.reduction.done:		// CHECK2: .omp.reduction.done:
// CHECK2-NEXT: [[TMP62:%.]] = bitcast i32 [[I7]] to i8*		// CHECK2-NEXT: [[TMP62:%.]] = bitcast i32 [[I7]] to i8*
// CHECK2-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP62]]) #[[ATTR5]]		// CHECK2-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP62]]) #[[ATTR5]]
// CHECK2-NEXT: [[TMP63:%.]] = bitcast %"class.std::complex.0" [[PARTIAL_SUM5]] to i8*		// CHECK2-NEXT: [[TMP63:%.]] = bitcast %"class.std::complex.0" [[PARTIAL_SUM5]] to i8*
// CHECK2-NEXT: call void @llvm.lifetime.end.p0i8(i64 16, i8* [[TMP63]]) #[[ATTR5]]		// CHECK2-NEXT: call void @llvm.lifetime.end.p0i8(i64 16, i8* [[TMP63]]) #[[ATTR5]]
// CHECK2-NEXT: [[TMP64:%.]] = bitcast i32 [[DOTOMP_IS_LAST]] to i8*		// CHECK2-NEXT: [[TMP64:%.]] = bitcast i32 [[DOTOMP_IS_LAST]] to i8*
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// CHECK2-SAME: (%"class.std::complex.0"* nonnull align 8 dereferenceable(16) [[THIS:%.]], %"class.std::complex.0" nonnull align 8 dereferenceable(16) [[__C:%.*]]) #[[ATTR4]] comdat align 2 {		// CHECK2-SAME: (%"class.std::complex.0"* nonnull align 8 dereferenceable(16) [[THIS:%.]], %"class.std::complex.0" nonnull align 8 dereferenceable(16) [[__C:%.*]]) #[[ATTR4]] comdat align 2 {
// CHECK2-NEXT: entry:		// CHECK2-NEXT: entry:
// CHECK2-NEXT: [[THIS_ADDR:%.]] = alloca %"class.std::complex.0", align 8		// CHECK2-NEXT: [[THIS_ADDR:%.]] = alloca %"class.std::complex.0", align 8
// CHECK2-NEXT: [[__C_ADDR:%.]] = alloca %"class.std::complex.0", align 8		// CHECK2-NEXT: [[__C_ADDR:%.]] = alloca %"class.std::complex.0", align 8
// CHECK2-NEXT: store %"class.std::complex.0"* [[THIS]], %"class.std::complex.0"** [[THIS_ADDR]], align 8, !tbaa [[TBAA12]]		// CHECK2-NEXT: store %"class.std::complex.0"* [[THIS]], %"class.std::complex.0"** [[THIS_ADDR]], align 8, !tbaa [[TBAA12]]
// CHECK2-NEXT: store %"class.std::complex.0"* [[__C]], %"class.std::complex.0"** [[__C_ADDR]], align 8, !tbaa [[TBAA12]]		// CHECK2-NEXT: store %"class.std::complex.0"* [[__C]], %"class.std::complex.0"** [[__C_ADDR]], align 8, !tbaa [[TBAA12]]
// CHECK2-NEXT: [[THIS1:%.]] = load %"class.std::complex.0", %"class.std::complex.0"** [[THIS_ADDR]], align 8		// CHECK2-NEXT: [[THIS1:%.]] = load %"class.std::complex.0", %"class.std::complex.0"** [[THIS_ADDR]], align 8
// CHECK2-NEXT: [[TMP0:%.]] = load %"class.std::complex.0", %"class.std::complex.0"** [[__C_ADDR]], align 8, !tbaa [[TBAA12]]		// CHECK2-NEXT: [[TMP0:%.]] = load %"class.std::complex.0", %"class.std::complex.0"** [[__C_ADDR]], align 8, !tbaa [[TBAA12]]
// CHECK2-NEXT: [[CALL:%.]] = call double @_ZNKSt7complexIdE4realEv(%"class.std::complex.0" nonnull align 8 dereferenceable(16) [[TMP0]]) #[[ATTR10]]		// CHECK2-NEXT: [[CALL:%.]] = call double @_ZNKSt7complexIdE4realEv(%"class.std::complex.0" nonnull align 8 dereferenceable(16) [[TMP0]]) #[[ATTR12]]
// CHECK2-NEXT: [[__RE_:%.]] = getelementptr inbounds %"class.std::complex.0", %"class.std::complex.0" [[THIS1]], i32 0, i32 0		// CHECK2-NEXT: [[__RE_:%.]] = getelementptr inbounds %"class.std::complex.0", %"class.std::complex.0" [[THIS1]], i32 0, i32 0
// CHECK2-NEXT: [[TMP1:%.]] = load double, double [[__RE_]], align 8, !tbaa [[TBAA24:![0-9]+]]		// CHECK2-NEXT: [[TMP1:%.]] = load double, double [[__RE_]], align 8, !tbaa [[TBAA24:![0-9]+]]
// CHECK2-NEXT: [[ADD:%.*]] = fadd double [[TMP1]], [[CALL]]		// CHECK2-NEXT: [[ADD:%.*]] = fadd double [[TMP1]], [[CALL]]
// CHECK2-NEXT: store double [[ADD]], double* [[__RE_]], align 8, !tbaa [[TBAA24]]		// CHECK2-NEXT: store double [[ADD]], double* [[__RE_]], align 8, !tbaa [[TBAA24]]
// CHECK2-NEXT: [[TMP2:%.]] = load %"class.std::complex.0", %"class.std::complex.0"** [[__C_ADDR]], align 8, !tbaa [[TBAA12]]		// CHECK2-NEXT: [[TMP2:%.]] = load %"class.std::complex.0", %"class.std::complex.0"** [[__C_ADDR]], align 8, !tbaa [[TBAA12]]
// CHECK2-NEXT: [[CALL2:%.]] = call double @_ZNKSt7complexIdE4imagEv(%"class.std::complex.0" nonnull align 8 dereferenceable(16) [[TMP2]]) #[[ATTR10]]		// CHECK2-NEXT: [[CALL2:%.]] = call double @_ZNKSt7complexIdE4imagEv(%"class.std::complex.0" nonnull align 8 dereferenceable(16) [[TMP2]]) #[[ATTR12]]
// CHECK2-NEXT: [[__IM_:%.]] = getelementptr inbounds %"class.std::complex.0", %"class.std::complex.0" [[THIS1]], i32 0, i32 1		// CHECK2-NEXT: [[__IM_:%.]] = getelementptr inbounds %"class.std::complex.0", %"class.std::complex.0" [[THIS1]], i32 0, i32 1
// CHECK2-NEXT: [[TMP3:%.]] = load double, double [[__IM_]], align 8, !tbaa [[TBAA26:![0-9]+]]		// CHECK2-NEXT: [[TMP3:%.]] = load double, double [[__IM_]], align 8, !tbaa [[TBAA26:![0-9]+]]
// CHECK2-NEXT: [[ADD3:%.*]] = fadd double [[TMP3]], [[CALL2]]		// CHECK2-NEXT: [[ADD3:%.*]] = fadd double [[TMP3]], [[CALL2]]
// CHECK2-NEXT: store double [[ADD3]], double* [[__IM_]], align 8, !tbaa [[TBAA26]]		// CHECK2-NEXT: store double [[ADD3]], double* [[__IM_]], align 8, !tbaa [[TBAA26]]
// CHECK2-NEXT: ret %"class.std::complex.0"* [[THIS1]]		// CHECK2-NEXT: ret %"class.std::complex.0"* [[THIS1]]
//		//
//		//
// CHECK2-LABEL: define {{[^@]+}}@_omp_reduction_shuffle_and_reduce_func5		// CHECK2-LABEL: define {{[^@]+}}@_omp_reduction_shuffle_and_reduce_func5
Show All 19 Lines
// CHECK2-NEXT: [[TMP11:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST]], i64 0, i64 0		// CHECK2-NEXT: [[TMP11:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST]], i64 0, i64 0
// CHECK2-NEXT: [[TMP12:%.]] = bitcast i8 [[TMP10]] to %"class.std::complex.0"*		// CHECK2-NEXT: [[TMP12:%.]] = bitcast i8 [[TMP10]] to %"class.std::complex.0"*
// CHECK2-NEXT: [[TMP13:%.]] = getelementptr %"class.std::complex.0", %"class.std::complex.0" [[TMP12]], i64 1		// CHECK2-NEXT: [[TMP13:%.]] = getelementptr %"class.std::complex.0", %"class.std::complex.0" [[TMP12]], i64 1
// CHECK2-NEXT: [[TMP14:%.]] = bitcast %"class.std::complex.0" [[TMP13]] to i8*		// CHECK2-NEXT: [[TMP14:%.]] = bitcast %"class.std::complex.0" [[TMP13]] to i8*
// CHECK2-NEXT: [[TMP15:%.]] = bitcast %"class.std::complex.0" [[TMP12]] to i64*		// CHECK2-NEXT: [[TMP15:%.]] = bitcast %"class.std::complex.0" [[TMP12]] to i64*
// CHECK2-NEXT: [[TMP16:%.]] = bitcast %"class.std::complex.0" [[DOTOMP_REDUCTION_ELEMENT]] to i64*		// CHECK2-NEXT: [[TMP16:%.]] = bitcast %"class.std::complex.0" [[DOTOMP_REDUCTION_ELEMENT]] to i64*
// CHECK2-NEXT: br label [[DOTSHUFFLE_PRE_COND:%.*]]		// CHECK2-NEXT: br label [[DOTSHUFFLE_PRE_COND:%.*]]
// CHECK2: .shuffle.pre_cond:		// CHECK2: .shuffle.pre_cond:
// CHECK2-NEXT: [[TMP17:%.]] = phi i64 [ [[TMP15]], [[ENTRY:%.]] ], [ [[TMP29:%.]], [[DOTSHUFFLE_THEN:%.*]] ]		// CHECK2-NEXT: [[TMP17:%.]] = phi i64 [ [[TMP15]], [[ENTRY:%.]] ], [ [[TMP28:%.]], [[DOTSHUFFLE_THEN:%.*]] ]
// CHECK2-NEXT: [[TMP18:%.]] = phi i64 [ [[TMP16]], [[ENTRY]] ], [ [[TMP30:%.*]], [[DOTSHUFFLE_THEN]] ]		// CHECK2-NEXT: [[TMP18:%.]] = phi i64 [ [[TMP16]], [[ENTRY]] ], [ [[TMP29:%.*]], [[DOTSHUFFLE_THEN]] ]
// CHECK2-NEXT: [[TMP19:%.]] = bitcast i64 [[TMP17]] to i8*		// CHECK2-NEXT: [[TMP19:%.]] = bitcast i64 [[TMP17]] to i8*
// CHECK2-NEXT: [[TMP20:%.]] = ptrtoint i8 [[TMP14]] to i64		// CHECK2-NEXT: [[TMP20:%.]] = ptrtoint i8 [[TMP14]] to i64
// CHECK2-NEXT: [[TMP21:%.]] = ptrtoint i8 [[TMP19]] to i64		// CHECK2-NEXT: [[TMP21:%.]] = ptrtoint i8 [[TMP19]] to i64
// CHECK2-NEXT: [[TMP22:%.*]] = sub i64 [[TMP20]], [[TMP21]]		// CHECK2-NEXT: [[TMP22:%.*]] = sub i64 [[TMP20]], [[TMP21]]
// CHECK2-NEXT: [[TMP23:%.]] = sdiv exact i64 [[TMP22]], ptrtoint (i8 getelementptr (i8, i8* null, i32 1) to i64)		// CHECK2-NEXT: [[TMP23:%.]] = sdiv exact i64 [[TMP22]], ptrtoint (i8 getelementptr (i8, i8* null, i32 1) to i64)
// CHECK2-NEXT: [[TMP24:%.*]] = icmp sgt i64 [[TMP23]], 7		// CHECK2-NEXT: [[TMP24:%.*]] = icmp sgt i64 [[TMP23]], 7
// CHECK2-NEXT: br i1 [[TMP24]], label [[DOTSHUFFLE_THEN]], label [[DOTSHUFFLE_EXIT:%.*]]		// CHECK2-NEXT: br i1 [[TMP24]], label [[DOTSHUFFLE_THEN]], label [[DOTSHUFFLE_EXIT:%.*]]
// CHECK2: .shuffle.then:		// CHECK2: .shuffle.then:
// CHECK2-NEXT: [[TMP25:%.]] = load i64, i64 [[TMP17]], align 8		// CHECK2-NEXT: [[TMP25:%.]] = load i64, i64 [[TMP17]], align 8
// CHECK2-NEXT: [[TMP26:%.*]] = call i32 @__kmpc_get_warp_size()		// CHECK2-NEXT: [[NVPTX_WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size()
// CHECK2-NEXT: [[TMP27:%.*]] = trunc i32 [[TMP26]] to i16		// CHECK2-NEXT: [[TMP26:%.*]] = trunc i32 [[NVPTX_WARP_SIZE]] to i16
// CHECK2-NEXT: [[TMP28:%.*]] = call i64 @__kmpc_shuffle_int64(i64 [[TMP25]], i16 [[TMP7]], i16 [[TMP27]])		// CHECK2-NEXT: [[TMP27:%.*]] = call i64 @__kmpc_shuffle_int64(i64 [[TMP25]], i16 [[TMP7]], i16 [[TMP26]])
// CHECK2-NEXT: store i64 [[TMP28]], i64* [[TMP18]], align 8		// CHECK2-NEXT: store i64 [[TMP27]], i64* [[TMP18]], align 8
// CHECK2-NEXT: [[TMP29]] = getelementptr i64, i64* [[TMP17]], i64 1		// CHECK2-NEXT: [[TMP28]] = getelementptr i64, i64* [[TMP17]], i64 1
// CHECK2-NEXT: [[TMP30]] = getelementptr i64, i64* [[TMP18]], i64 1		// CHECK2-NEXT: [[TMP29]] = getelementptr i64, i64* [[TMP18]], i64 1
// CHECK2-NEXT: br label [[DOTSHUFFLE_PRE_COND]]		// CHECK2-NEXT: br label [[DOTSHUFFLE_PRE_COND]]
// CHECK2: .shuffle.exit:		// CHECK2: .shuffle.exit:
// CHECK2-NEXT: [[TMP31:%.]] = bitcast %"class.std::complex.0" [[DOTOMP_REDUCTION_ELEMENT]] to i8*		// CHECK2-NEXT: [[TMP30:%.]] = bitcast %"class.std::complex.0" [[DOTOMP_REDUCTION_ELEMENT]] to i8*
// CHECK2-NEXT: store i8* [[TMP31]], i8** [[TMP11]], align 8, !tbaa [[TBAA12]]		// CHECK2-NEXT: store i8* [[TMP30]], i8** [[TMP11]], align 8, !tbaa [[TBAA12]]
// CHECK2-NEXT: [[TMP32:%.*]] = icmp eq i16 [[TMP8]], 0		// CHECK2-NEXT: [[TMP31:%.*]] = icmp eq i16 [[TMP8]], 0
// CHECK2-NEXT: [[TMP33:%.*]] = icmp eq i16 [[TMP8]], 1		// CHECK2-NEXT: [[TMP32:%.*]] = icmp eq i16 [[TMP8]], 1
// CHECK2-NEXT: [[TMP34:%.*]] = icmp ult i16 [[TMP6]], [[TMP7]]		// CHECK2-NEXT: [[TMP33:%.*]] = icmp ult i16 [[TMP6]], [[TMP7]]
// CHECK2-NEXT: [[TMP35:%.*]] = and i1 [[TMP33]], [[TMP34]]		// CHECK2-NEXT: [[TMP34:%.*]] = and i1 [[TMP32]], [[TMP33]]
// CHECK2-NEXT: [[TMP36:%.*]] = icmp eq i16 [[TMP8]], 2		// CHECK2-NEXT: [[TMP35:%.*]] = icmp eq i16 [[TMP8]], 2
// CHECK2-NEXT: [[TMP37:%.*]] = and i16 [[TMP6]], 1		// CHECK2-NEXT: [[TMP36:%.*]] = and i16 [[TMP6]], 1
// CHECK2-NEXT: [[TMP38:%.*]] = icmp eq i16 [[TMP37]], 0		// CHECK2-NEXT: [[TMP37:%.*]] = icmp eq i16 [[TMP36]], 0
// CHECK2-NEXT: [[TMP39:%.*]] = and i1 [[TMP36]], [[TMP38]]		// CHECK2-NEXT: [[TMP38:%.*]] = and i1 [[TMP35]], [[TMP37]]
// CHECK2-NEXT: [[TMP40:%.*]] = icmp sgt i16 [[TMP7]], 0		// CHECK2-NEXT: [[TMP39:%.*]] = icmp sgt i16 [[TMP7]], 0
// CHECK2-NEXT: [[TMP41:%.*]] = and i1 [[TMP39]], [[TMP40]]		// CHECK2-NEXT: [[TMP40:%.*]] = and i1 [[TMP38]], [[TMP39]]
// CHECK2-NEXT: [[TMP42:%.*]] = or i1 [[TMP32]], [[TMP35]]		// CHECK2-NEXT: [[TMP41:%.*]] = or i1 [[TMP31]], [[TMP34]]
// CHECK2-NEXT: [[TMP43:%.*]] = or i1 [[TMP42]], [[TMP41]]		// CHECK2-NEXT: [[TMP42:%.*]] = or i1 [[TMP41]], [[TMP40]]
// CHECK2-NEXT: br i1 [[TMP43]], label [[THEN:%.]], label [[ELSE:%.]]		// CHECK2-NEXT: br i1 [[TMP42]], label [[THEN:%.]], label [[ELSE:%.]]
// CHECK2: then:		// CHECK2: then:
// CHECK2-NEXT: [[TMP44:%.]] = bitcast [1 x i8]* [[TMP5]] to i8*		// CHECK2-NEXT: [[TMP43:%.]] = bitcast [1 x i8]* [[TMP5]] to i8*
// CHECK2-NEXT: [[TMP45:%.]] = bitcast [1 x i8]* [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST]] to i8*		// CHECK2-NEXT: [[TMP44:%.]] = bitcast [1 x i8]* [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST]] to i8*
// CHECK2-NEXT: call void @"_omp$reduction$reduction_func4"(i8* [[TMP44]], i8* [[TMP45]]) #[[ATTR5]]		// CHECK2-NEXT: call void @"_omp$reduction$reduction_func4"(i8* [[TMP43]], i8* [[TMP44]]) #[[ATTR5]]
// CHECK2-NEXT: br label [[IFCONT:%.*]]		// CHECK2-NEXT: br label [[IFCONT:%.*]]
// CHECK2: else:		// CHECK2: else:
// CHECK2-NEXT: br label [[IFCONT]]		// CHECK2-NEXT: br label [[IFCONT]]
// CHECK2: ifcont:		// CHECK2: ifcont:
// CHECK2-NEXT: [[TMP46:%.*]] = icmp eq i16 [[TMP8]], 1		// CHECK2-NEXT: [[TMP45:%.*]] = icmp eq i16 [[TMP8]], 1
// CHECK2-NEXT: [[TMP47:%.*]] = icmp uge i16 [[TMP6]], [[TMP7]]		// CHECK2-NEXT: [[TMP46:%.*]] = icmp uge i16 [[TMP6]], [[TMP7]]
// CHECK2-NEXT: [[TMP48:%.*]] = and i1 [[TMP46]], [[TMP47]]		// CHECK2-NEXT: [[TMP47:%.*]] = and i1 [[TMP45]], [[TMP46]]
// CHECK2-NEXT: br i1 [[TMP48]], label [[THEN4:%.]], label [[ELSE5:%.]]		// CHECK2-NEXT: br i1 [[TMP47]], label [[THEN4:%.]], label [[ELSE5:%.]]
// CHECK2: then4:		// CHECK2: then4:
// CHECK2-NEXT: [[TMP49:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST]], i64 0, i64 0		// CHECK2-NEXT: [[TMP48:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST]], i64 0, i64 0
// CHECK2-NEXT: [[TMP50:%.]] = load i8, i8** [[TMP49]], align 8		// CHECK2-NEXT: [[TMP49:%.]] = load i8, i8** [[TMP48]], align 8
// CHECK2-NEXT: [[TMP51:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[TMP5]], i64 0, i64 0		// CHECK2-NEXT: [[TMP50:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[TMP5]], i64 0, i64 0
// CHECK2-NEXT: [[TMP52:%.]] = load i8, i8** [[TMP51]], align 8		// CHECK2-NEXT: [[TMP51:%.]] = load i8, i8** [[TMP50]], align 8
// CHECK2-NEXT: [[TMP53:%.]] = bitcast i8 [[TMP50]] to %"class.std::complex.0"*		// CHECK2-NEXT: [[TMP52:%.]] = bitcast i8 [[TMP49]] to %"class.std::complex.0"*
// CHECK2-NEXT: [[TMP54:%.]] = bitcast i8 [[TMP52]] to %"class.std::complex.0"*		// CHECK2-NEXT: [[TMP53:%.]] = bitcast i8 [[TMP51]] to %"class.std::complex.0"*
// CHECK2-NEXT: [[TMP55:%.]] = bitcast %"class.std::complex.0" [[TMP54]] to i8*		// CHECK2-NEXT: [[TMP54:%.]] = bitcast %"class.std::complex.0" [[TMP53]] to i8*
// CHECK2-NEXT: [[TMP56:%.]] = bitcast %"class.std::complex.0" [[TMP53]] to i8*		// CHECK2-NEXT: [[TMP55:%.]] = bitcast %"class.std::complex.0" [[TMP52]] to i8*
// CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP55]], i8* align 8 [[TMP56]], i64 16, i1 false), !tbaa.struct !27		// CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP54]], i8* align 8 [[TMP55]], i64 16, i1 false), !tbaa.struct !27
// CHECK2-NEXT: br label [[IFCONT6:%.*]]		// CHECK2-NEXT: br label [[IFCONT6:%.*]]
// CHECK2: else5:		// CHECK2: else5:
// CHECK2-NEXT: br label [[IFCONT6]]		// CHECK2-NEXT: br label [[IFCONT6]]
// CHECK2: ifcont6:		// CHECK2: ifcont6:
// CHECK2-NEXT: ret void		// CHECK2-NEXT: ret void
//		//
//		//
// CHECK2-LABEL: define {{[^@]+}}@_omp_reduction_inter_warp_copy_func6		// CHECK2-LABEL: define {{[^@]+}}@_omp_reduction_inter_warp_copy_func6
// CHECK2-SAME: (i8* [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR6]] {		// CHECK2-SAME: (i8* [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR6]] {
// CHECK2-NEXT: entry:		// CHECK2-NEXT: entry:
// CHECK2-NEXT: [[DOTADDR:%.]] = alloca i8, align 8		// CHECK2-NEXT: [[DOTADDR:%.]] = alloca i8, align 8
// CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4		// CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
// CHECK2-NEXT: [[DOTCNT_ADDR:%.*]] = alloca i32, align 4		// CHECK2-NEXT: [[DOTCNT_ADDR:%.*]] = alloca i32, align 4
// CHECK2-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB1]])		// CHECK2-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB1]])
// CHECK2-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8, !tbaa [[TBAA12]]		// CHECK2-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8, !tbaa [[TBAA12]]
// CHECK2-NEXT: store i32 [[TMP1]], i32* [[DOTADDR1]], align 4, !tbaa [[TBAA8]]		// CHECK2-NEXT: store i32 [[TMP1]], i32* [[DOTADDR1]], align 4, !tbaa [[TBAA8]]
// CHECK2-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block()		// CHECK2-NEXT: [[NVPTX_TID:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block()
// CHECK2-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block()		// CHECK2-NEXT: [[NVPTX_TID2:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block()
// CHECK2-NEXT: [[NVPTX_LANE_ID:%.*]] = and i32 [[TMP4]], 31		// CHECK2-NEXT: [[NVPTX_LANE_ID:%.*]] = and i32 [[NVPTX_TID2]], 31
// CHECK2-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block()		// CHECK2-NEXT: [[NVPTX_TID3:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block()
// CHECK2-NEXT: [[NVPTX_WARP_ID:%.*]] = ashr i32 [[TMP5]], 5		// CHECK2-NEXT: [[NVPTX_WARP_ID:%.*]] = ashr i32 [[NVPTX_TID3]], 5
// CHECK2-NEXT: [[TMP6:%.]] = load i8, i8** [[DOTADDR]], align 8		// CHECK2-NEXT: [[TMP3:%.]] = load i8, i8** [[DOTADDR]], align 8
// CHECK2-NEXT: [[TMP7:%.]] = bitcast i8 [[TMP6]] to [1 x i8]		// CHECK2-NEXT: [[TMP4:%.]] = bitcast i8 [[TMP3]] to [1 x i8]
// CHECK2-NEXT: store i32 0, i32* [[DOTCNT_ADDR]], align 4, !tbaa [[TBAA8]]		// CHECK2-NEXT: store i32 0, i32* [[DOTCNT_ADDR]], align 4, !tbaa [[TBAA8]]
// CHECK2-NEXT: br label [[PRECOND:%.*]]		// CHECK2-NEXT: br label [[PRECOND:%.*]]
// CHECK2: precond:		// CHECK2: precond:
// CHECK2-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTCNT_ADDR]], align 4, !tbaa [[TBAA8]]		// CHECK2-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTCNT_ADDR]], align 4, !tbaa [[TBAA8]]
// CHECK2-NEXT: [[TMP9:%.*]] = icmp ult i32 [[TMP8]], 4		// CHECK2-NEXT: [[TMP6:%.*]] = icmp ult i32 [[TMP5]], 4
// CHECK2-NEXT: br i1 [[TMP9]], label [[BODY:%.]], label [[EXIT:%.]]		// CHECK2-NEXT: br i1 [[TMP6]], label [[BODY:%.]], label [[EXIT:%.]]
// CHECK2: body:		// CHECK2: body:
// CHECK2-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB4]], i32 [[TMP2]])		// CHECK2-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB4]], i32 [[TMP2]])
// CHECK2-NEXT: [[WARP_MASTER:%.*]] = icmp eq i32 [[NVPTX_LANE_ID]], 0		// CHECK2-NEXT: [[WARP_MASTER:%.*]] = icmp eq i32 [[NVPTX_LANE_ID]], 0
// CHECK2-NEXT: br i1 [[WARP_MASTER]], label [[THEN:%.]], label [[ELSE:%.]]		// CHECK2-NEXT: br i1 [[WARP_MASTER]], label [[THEN:%.]], label [[ELSE:%.]]
// CHECK2: then:		// CHECK2: then:
// CHECK2-NEXT: [[TMP10:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[TMP7]], i64 0, i64 0		// CHECK2-NEXT: [[TMP7:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[TMP4]], i64 0, i64 0
// CHECK2-NEXT: [[TMP11:%.]] = load i8, i8** [[TMP10]], align 8, !tbaa [[TBAA12]]		// CHECK2-NEXT: [[TMP8:%.]] = load i8, i8** [[TMP7]], align 8, !tbaa [[TBAA12]]
// CHECK2-NEXT: [[TMP12:%.]] = bitcast i8 [[TMP11]] to i32*		// CHECK2-NEXT: [[TMP9:%.]] = bitcast i8 [[TMP8]] to i32*
// CHECK2-NEXT: [[TMP13:%.]] = getelementptr i32, i32 [[TMP12]], i32 [[TMP8]]		// CHECK2-NEXT: [[TMP10:%.]] = getelementptr i32, i32 [[TMP9]], i32 [[TMP5]]
// CHECK2-NEXT: [[TMP14:%.]] = getelementptr inbounds [32 x i32], [32 x i32] addrspace(3) @__openmp_nvptx_data_transfer_temporary_storage, i64 0, i32 [[NVPTX_WARP_ID]]		// CHECK2-NEXT: [[TMP11:%.]] = getelementptr inbounds [32 x i32], [32 x i32] addrspace(3) @__openmp_nvptx_data_transfer_temporary_storage, i64 0, i32 [[NVPTX_WARP_ID]]
// CHECK2-NEXT: [[TMP15:%.]] = load i32, i32 [[TMP13]], align 4		// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32 [[TMP10]], align 4
// CHECK2-NEXT: store volatile i32 [[TMP15]], i32 addrspace(3)* [[TMP14]], align 4		// CHECK2-NEXT: store volatile i32 [[TMP12]], i32 addrspace(3)* [[TMP11]], align 4
// CHECK2-NEXT: br label [[IFCONT:%.*]]		// CHECK2-NEXT: br label [[IFCONT:%.*]]
// CHECK2: else:		// CHECK2: else:
// CHECK2-NEXT: br label [[IFCONT]]		// CHECK2-NEXT: br label [[IFCONT]]
// CHECK2: ifcont:		// CHECK2: ifcont:
// CHECK2-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB4]], i32 [[TMP2]])		// CHECK2-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB4]], i32 [[TMP2]])
// CHECK2-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTADDR1]], align 4, !tbaa [[TBAA8]]		// CHECK2-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTADDR1]], align 4, !tbaa [[TBAA8]]
// CHECK2-NEXT: [[IS_ACTIVE_THREAD:%.*]] = icmp ult i32 [[TMP3]], [[TMP16]]		// CHECK2-NEXT: [[IS_ACTIVE_THREAD:%.*]] = icmp ult i32 [[NVPTX_TID]], [[TMP13]]
// CHECK2-NEXT: br i1 [[IS_ACTIVE_THREAD]], label [[THEN2:%.]], label [[ELSE3:%.]]		// CHECK2-NEXT: br i1 [[IS_ACTIVE_THREAD]], label [[THEN4:%.]], label [[ELSE5:%.]]
// CHECK2: then2:		// CHECK2: then2:
// CHECK2-NEXT: [[TMP17:%.]] = getelementptr inbounds [32 x i32], [32 x i32] addrspace(3) @__openmp_nvptx_data_transfer_temporary_storage, i64 0, i32 [[TMP3]]		// CHECK2-NEXT: [[TMP14:%.]] = getelementptr inbounds [32 x i32], [32 x i32] addrspace(3) @__openmp_nvptx_data_transfer_temporary_storage, i64 0, i32 [[NVPTX_TID]]
// CHECK2-NEXT: [[TMP18:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[TMP7]], i64 0, i64 0		// CHECK2-NEXT: [[TMP15:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[TMP4]], i64 0, i64 0
// CHECK2-NEXT: [[TMP19:%.]] = load i8, i8** [[TMP18]], align 8, !tbaa [[TBAA12]]		// CHECK2-NEXT: [[TMP16:%.]] = load i8, i8** [[TMP15]], align 8, !tbaa [[TBAA12]]
// CHECK2-NEXT: [[TMP20:%.]] = bitcast i8 [[TMP19]] to i32*		// CHECK2-NEXT: [[TMP17:%.]] = bitcast i8 [[TMP16]] to i32*
// CHECK2-NEXT: [[TMP21:%.]] = getelementptr i32, i32 [[TMP20]], i32 [[TMP8]]		// CHECK2-NEXT: [[TMP18:%.]] = getelementptr i32, i32 [[TMP17]], i32 [[TMP5]]
// CHECK2-NEXT: [[TMP22:%.]] = load volatile i32, i32 addrspace(3) [[TMP17]], align 4, !tbaa [[TBAA8]]		// CHECK2-NEXT: [[TMP19:%.]] = load volatile i32, i32 addrspace(3) [[TMP14]], align 4, !tbaa [[TBAA8]]
// CHECK2-NEXT: store i32 [[TMP22]], i32* [[TMP21]], align 4, !tbaa [[TBAA8]]		// CHECK2-NEXT: store i32 [[TMP19]], i32* [[TMP18]], align 4, !tbaa [[TBAA8]]
// CHECK2-NEXT: br label [[IFCONT4:%.*]]		// CHECK2-NEXT: br label [[IFCONT6:%.*]]
// CHECK2: else3:		// CHECK2: else3:
// CHECK2-NEXT: br label [[IFCONT4]]		// CHECK2-NEXT: br label [[IFCONT6]]
// CHECK2: ifcont4:		// CHECK2: ifcont4:
// CHECK2-NEXT: [[TMP23:%.*]] = add nsw i32 [[TMP8]], 1		// CHECK2-NEXT: [[TMP20:%.*]] = add nsw i32 [[TMP5]], 1
// CHECK2-NEXT: store i32 [[TMP23]], i32* [[DOTCNT_ADDR]], align 4, !tbaa [[TBAA8]]		// CHECK2-NEXT: store i32 [[TMP20]], i32* [[DOTCNT_ADDR]], align 4, !tbaa [[TBAA8]]
// CHECK2-NEXT: br label [[PRECOND]]		// CHECK2-NEXT: br label [[PRECOND]]
// CHECK2: exit:		// CHECK2: exit:
// CHECK2-NEXT: ret void		// CHECK2-NEXT: ret void
//		//
//		//
// CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__3_wrapper		// CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__3_wrapper
// CHECK2-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR6]] {		// CHECK2-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR6]] {
// CHECK2-NEXT: entry:		// CHECK2-NEXT: entry:
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// CHECK2-NEXT: ret double [[TMP0]]		// CHECK2-NEXT: ret double [[TMP0]]
//		//
//		//
// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z17complex_reductionIfEvv_l16		// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z17complex_reductionIfEvv_l16
// CHECK3-SAME: () #[[ATTR0:[0-9]+]] {		// CHECK3-SAME: () #[[ATTR0:[0-9]+]] {
// CHECK3-NEXT: entry:		// CHECK3-NEXT: entry:
// CHECK3-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4		// CHECK3-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
// CHECK3-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4		// CHECK3-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
// CHECK3-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1:[0-9]+]], i8 1, i1 true, i1 true)		// CHECK3-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z17complex_reductionIfEvv_l16_kernel_info, i1 true)
// CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1		// CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
// CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]		// CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
// CHECK3: user_code.entry:		// CHECK3: user_code.entry:
// CHECK3-NEXT: [[TMP1:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB1]])		// CHECK3-NEXT: [[TMP1:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB1:[0-9]+]])
// CHECK3-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4		// CHECK3-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
// CHECK3-NEXT: store i32 [[TMP1]], i32* [[DOTTHREADID_TEMP_]], align 4, !tbaa [[TBAA8:![0-9]+]]		// CHECK3-NEXT: store i32 [[TMP1]], i32* [[DOTTHREADID_TEMP_]], align 4, !tbaa [[TBAA8:![0-9]+]]
// CHECK3-NEXT: call void @__omp_outlined__(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]]) #[[ATTR5:[0-9]+]]		// CHECK3-NEXT: call void @__omp_outlined__(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]]) #[[ATTR5:[0-9]+]]
// CHECK3-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true)		// CHECK3-NEXT: call void @__kmpc_target_deinit(i1 true)
// CHECK3-NEXT: ret void		// CHECK3-NEXT: ret void
// CHECK3: worker.exit:		// CHECK3: worker.exit:
// CHECK3-NEXT: ret void		// CHECK3-NEXT: ret void
//		//
//		//
// CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__		// CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__
// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {		// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
// CHECK3-NEXT: entry:		// CHECK3-NEXT: entry:
// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8		// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8
// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8		// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8
// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4		// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4		// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4
// CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4		// CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
// CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4		// CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4		// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4		// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
// CHECK3-NEXT: [[IB:%.*]] = alloca i32, align 4		// CHECK3-NEXT: [[IB:%.*]] = alloca i32, align 4
// CHECK3-NEXT: [[REF_TMP:%.*]] = alloca float, align 4		// CHECK3-NEXT: [[REF_TMP:%.*]] = alloca float, align 4
// CHECK3-NEXT: [[REF_TMP2:%.*]] = alloca float, align 4		// CHECK3-NEXT: [[REF_TMP2:%.*]] = alloca float, align 4
// CHECK3-NEXT: [[CAPTURED_VARS_ADDRS:%.]] = alloca [3 x i8], align 8		// CHECK3-NEXT: [[CAPTURED_VARS_ADDRS:%.]] = alloca [3 x i8], align 8
// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8, !tbaa [[TBAA12:![0-9]+]]		// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8, !tbaa [[TBAA12:![0-9]+]]
// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8, !tbaa [[TBAA12]]		// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8, !tbaa [[TBAA12]]
// CHECK3-NEXT: [[ISTART:%.]] = call align 16 i8 @__kmpc_alloc_shared(i64 4)		// CHECK3-NEXT: [[ISTART:%.]] = call i8 @__kmpc_alloc_shared(i64 4)
// CHECK3-NEXT: [[ISTART_ON_STACK:%.]] = bitcast i8 [[ISTART]] to i32*		// CHECK3-NEXT: [[ISTART_ON_STACK:%.]] = bitcast i8 [[ISTART]] to i32*
// CHECK3-NEXT: [[IEND:%.]] = call align 16 i8 @__kmpc_alloc_shared(i64 4)		// CHECK3-NEXT: [[IEND:%.]] = call i8 @__kmpc_alloc_shared(i64 4)
// CHECK3-NEXT: [[IEND_ON_STACK:%.]] = bitcast i8 [[IEND]] to i32*		// CHECK3-NEXT: [[IEND_ON_STACK:%.]] = bitcast i8 [[IEND]] to i32*
// CHECK3-NEXT: [[PARTIAL_SUM:%.]] = call align 16 i8 @__kmpc_alloc_shared(i64 8)		// CHECK3-NEXT: [[PARTIAL_SUM:%.]] = call i8 @__kmpc_alloc_shared(i64 8)
// CHECK3-NEXT: [[PARTIAL_SUM_ON_STACK:%.]] = bitcast i8 [[PARTIAL_SUM]] to %"class.std::complex"*		// CHECK3-NEXT: [[PARTIAL_SUM_ON_STACK:%.]] = bitcast i8 [[PARTIAL_SUM]] to %"class.std::complex"*
// CHECK3-NEXT: [[TMP0:%.]] = bitcast i32 [[DOTOMP_IV]] to i8*		// CHECK3-NEXT: [[TMP0:%.]] = bitcast i32 [[DOTOMP_IV]] to i8*
// CHECK3-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP0]]) #[[ATTR5]]		// CHECK3-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP0]]) #[[ATTR5]]
// CHECK3-NEXT: [[TMP1:%.]] = bitcast i32 [[DOTOMP_LB]] to i8*		// CHECK3-NEXT: [[TMP1:%.]] = bitcast i32 [[DOTOMP_LB]] to i8*
// CHECK3-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP1]]) #[[ATTR5]]		// CHECK3-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP1]]) #[[ATTR5]]
// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4, !tbaa [[TBAA8]]		// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4, !tbaa [[TBAA8]]
// CHECK3-NEXT: [[TMP2:%.]] = bitcast i32 [[DOTOMP_UB]] to i8*		// CHECK3-NEXT: [[TMP2:%.]] = bitcast i32 [[DOTOMP_UB]] to i8*
// CHECK3-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP2]]) #[[ATTR5]]		// CHECK3-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP2]]) #[[ATTR5]]
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// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]		// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK3-NEXT: store i32 [[ADD]], i32* [[IB]], align 4, !tbaa [[TBAA8]]		// CHECK3-NEXT: store i32 [[ADD]], i32* [[IB]], align 4, !tbaa [[TBAA8]]
// CHECK3-NEXT: [[TMP14:%.]] = bitcast float [[REF_TMP]] to i8*		// CHECK3-NEXT: [[TMP14:%.]] = bitcast float [[REF_TMP]] to i8*
// CHECK3-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP14]]) #[[ATTR5]]		// CHECK3-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP14]]) #[[ATTR5]]
// CHECK3-NEXT: store float 0.000000e+00, float* [[REF_TMP]], align 4, !tbaa [[TBAA14:![0-9]+]]		// CHECK3-NEXT: store float 0.000000e+00, float* [[REF_TMP]], align 4, !tbaa [[TBAA14:![0-9]+]]
// CHECK3-NEXT: [[TMP15:%.]] = bitcast float [[REF_TMP2]] to i8*		// CHECK3-NEXT: [[TMP15:%.]] = bitcast float [[REF_TMP2]] to i8*
// CHECK3-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP15]]) #[[ATTR5]]		// CHECK3-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP15]]) #[[ATTR5]]
// CHECK3-NEXT: store float 0.000000e+00, float* [[REF_TMP2]], align 4, !tbaa [[TBAA14]]		// CHECK3-NEXT: store float 0.000000e+00, float* [[REF_TMP2]], align 4, !tbaa [[TBAA14]]
// CHECK3-NEXT: call void @_ZNSt7complexIfEC1ERKfS2_(%"class.std::complex"* nonnull align 4 dereferenceable(8) [[PARTIAL_SUM_ON_STACK]], float* nonnull align 4 dereferenceable(4) [[REF_TMP]], float* nonnull align 4 dereferenceable(4) [[REF_TMP2]]) #[[ATTR10:[0-9]+]]		// CHECK3-NEXT: call void @_ZNSt7complexIfEC1ERKfS2_(%"class.std::complex"* nonnull align 4 dereferenceable(8) [[PARTIAL_SUM_ON_STACK]], float* nonnull align 4 dereferenceable(4) [[REF_TMP]], float* nonnull align 4 dereferenceable(4) [[REF_TMP2]]) #[[ATTR12:[0-9]+]]
// CHECK3-NEXT: [[TMP16:%.]] = bitcast float [[REF_TMP2]] to i8*		// CHECK3-NEXT: [[TMP16:%.]] = bitcast float [[REF_TMP2]] to i8*
// CHECK3-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP16]]) #[[ATTR5]]		// CHECK3-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP16]]) #[[ATTR5]]
// CHECK3-NEXT: [[TMP17:%.]] = bitcast float [[REF_TMP]] to i8*		// CHECK3-NEXT: [[TMP17:%.]] = bitcast float [[REF_TMP]] to i8*
// CHECK3-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP17]]) #[[ATTR5]]		// CHECK3-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP17]]) #[[ATTR5]]
// CHECK3-NEXT: [[TMP18:%.]] = load i32, i32 [[IB]], align 4, !tbaa [[TBAA8]]		// CHECK3-NEXT: [[TMP18:%.]] = load i32, i32 [[IB]], align 4, !tbaa [[TBAA8]]
// CHECK3-NEXT: [[MUL3:%.*]] = mul nsw i32 [[TMP18]], 4		// CHECK3-NEXT: [[MUL3:%.*]] = mul nsw i32 [[TMP18]], 4
// CHECK3-NEXT: store i32 [[MUL3]], i32* [[ISTART_ON_STACK]], align 4, !tbaa [[TBAA8]]		// CHECK3-NEXT: store i32 [[MUL3]], i32* [[ISTART_ON_STACK]], align 4, !tbaa [[TBAA8]]
// CHECK3-NEXT: [[TMP19:%.]] = load i32, i32 [[IB]], align 4, !tbaa [[TBAA8]]		// CHECK3-NEXT: [[TMP19:%.]] = load i32, i32 [[IB]], align 4, !tbaa [[TBAA8]]
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// CHECK3-NEXT: [[__RE_ADDR:%.]] = alloca float, align 8		// CHECK3-NEXT: [[__RE_ADDR:%.]] = alloca float, align 8
// CHECK3-NEXT: [[__IM_ADDR:%.]] = alloca float, align 8		// CHECK3-NEXT: [[__IM_ADDR:%.]] = alloca float, align 8
// CHECK3-NEXT: store %"class.std::complex"* [[THIS]], %"class.std::complex"** [[THIS_ADDR]], align 8, !tbaa [[TBAA12]]		// CHECK3-NEXT: store %"class.std::complex"* [[THIS]], %"class.std::complex"** [[THIS_ADDR]], align 8, !tbaa [[TBAA12]]
// CHECK3-NEXT: store float* [[__RE]], float** [[__RE_ADDR]], align 8, !tbaa [[TBAA12]]		// CHECK3-NEXT: store float* [[__RE]], float** [[__RE_ADDR]], align 8, !tbaa [[TBAA12]]
// CHECK3-NEXT: store float* [[__IM]], float** [[__IM_ADDR]], align 8, !tbaa [[TBAA12]]		// CHECK3-NEXT: store float* [[__IM]], float** [[__IM_ADDR]], align 8, !tbaa [[TBAA12]]
// CHECK3-NEXT: [[THIS1:%.]] = load %"class.std::complex", %"class.std::complex"** [[THIS_ADDR]], align 8		// CHECK3-NEXT: [[THIS1:%.]] = load %"class.std::complex", %"class.std::complex"** [[THIS_ADDR]], align 8
// CHECK3-NEXT: [[TMP0:%.]] = load float, float** [[__RE_ADDR]], align 8		// CHECK3-NEXT: [[TMP0:%.]] = load float, float** [[__RE_ADDR]], align 8
// CHECK3-NEXT: [[TMP1:%.]] = load float, float** [[__IM_ADDR]], align 8		// CHECK3-NEXT: [[TMP1:%.]] = load float, float** [[__IM_ADDR]], align 8
// CHECK3-NEXT: call void @_ZNSt7complexIfEC2ERKfS2_(%"class.std::complex"* nonnull align 4 dereferenceable(8) [[THIS1]], float* nonnull align 4 dereferenceable(4) [[TMP0]], float* nonnull align 4 dereferenceable(4) [[TMP1]]) #[[ATTR10]]		// CHECK3-NEXT: call void @_ZNSt7complexIfEC2ERKfS2_(%"class.std::complex"* nonnull align 4 dereferenceable(8) [[THIS1]], float* nonnull align 4 dereferenceable(4) [[TMP0]], float* nonnull align 4 dereferenceable(4) [[TMP1]]) #[[ATTR12]]
// CHECK3-NEXT: ret void		// CHECK3-NEXT: ret void
//		//
//		//
// CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__1		// CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__1
// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i32 nonnull align 4 dereferenceable(4) [[ISTART:%.]], i32 nonnull align 4 dereferenceable(4) [[IEND:%.]], %"class.std::complex" nonnull align 4 dereferenceable(8) [[PARTIAL_SUM:%.*]]) #[[ATTR0]] {		// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i32 nonnull align 4 dereferenceable(4) [[ISTART:%.]], i32 nonnull align 4 dereferenceable(4) [[IEND:%.]], %"class.std::complex" nonnull align 4 dereferenceable(8) [[PARTIAL_SUM:%.*]]) #[[ATTR0]] {
// CHECK3-NEXT: entry:		// CHECK3-NEXT: entry:
// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8		// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8
// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8		// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8
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// CHECK3-NEXT: [[TMP21:%.]] = bitcast %"class.std::complex" [[PARTIAL_SUM5]] to i8*		// CHECK3-NEXT: [[TMP21:%.]] = bitcast %"class.std::complex" [[PARTIAL_SUM5]] to i8*
// CHECK3-NEXT: call void @llvm.lifetime.start.p0i8(i64 8, i8* [[TMP21]]) #[[ATTR5]]		// CHECK3-NEXT: call void @llvm.lifetime.start.p0i8(i64 8, i8* [[TMP21]]) #[[ATTR5]]
// CHECK3-NEXT: [[TMP22:%.]] = bitcast float [[REF_TMP]] to i8*		// CHECK3-NEXT: [[TMP22:%.]] = bitcast float [[REF_TMP]] to i8*
// CHECK3-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP22]]) #[[ATTR5]]		// CHECK3-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP22]]) #[[ATTR5]]
// CHECK3-NEXT: store float 0.000000e+00, float* [[REF_TMP]], align 4, !tbaa [[TBAA14]]		// CHECK3-NEXT: store float 0.000000e+00, float* [[REF_TMP]], align 4, !tbaa [[TBAA14]]
// CHECK3-NEXT: [[TMP23:%.]] = bitcast float [[REF_TMP6]] to i8*		// CHECK3-NEXT: [[TMP23:%.]] = bitcast float [[REF_TMP6]] to i8*
// CHECK3-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP23]]) #[[ATTR5]]		// CHECK3-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP23]]) #[[ATTR5]]
// CHECK3-NEXT: store float 0.000000e+00, float* [[REF_TMP6]], align 4, !tbaa [[TBAA14]]		// CHECK3-NEXT: store float 0.000000e+00, float* [[REF_TMP6]], align 4, !tbaa [[TBAA14]]
// CHECK3-NEXT: call void @_ZNSt7complexIfEC1ERKfS2_(%"class.std::complex"* nonnull align 4 dereferenceable(8) [[PARTIAL_SUM5]], float* nonnull align 4 dereferenceable(4) [[REF_TMP]], float* nonnull align 4 dereferenceable(4) [[REF_TMP6]]) #[[ATTR10]]		// CHECK3-NEXT: call void @_ZNSt7complexIfEC1ERKfS2_(%"class.std::complex"* nonnull align 4 dereferenceable(8) [[PARTIAL_SUM5]], float* nonnull align 4 dereferenceable(4) [[REF_TMP]], float* nonnull align 4 dereferenceable(4) [[REF_TMP6]]) #[[ATTR12]]
// CHECK3-NEXT: [[TMP24:%.]] = bitcast float [[REF_TMP6]] to i8*		// CHECK3-NEXT: [[TMP24:%.]] = bitcast float [[REF_TMP6]] to i8*
// CHECK3-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP24]]) #[[ATTR5]]		// CHECK3-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP24]]) #[[ATTR5]]
// CHECK3-NEXT: [[TMP25:%.]] = bitcast float [[REF_TMP]] to i8*		// CHECK3-NEXT: [[TMP25:%.]] = bitcast float [[REF_TMP]] to i8*
// CHECK3-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP25]]) #[[ATTR5]]		// CHECK3-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP25]]) #[[ATTR5]]
// CHECK3-NEXT: [[TMP26:%.]] = bitcast i32 [[I7]] to i8*		// CHECK3-NEXT: [[TMP26:%.]] = bitcast i32 [[I7]] to i8*
// CHECK3-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP26]]) #[[ATTR5]]		// CHECK3-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP26]]) #[[ATTR5]]
// CHECK3-NEXT: [[TMP27:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8		// CHECK3-NEXT: [[TMP27:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK3-NEXT: [[TMP28:%.]] = load i32, i32 [[TMP27]], align 4, !tbaa [[TBAA8]]		// CHECK3-NEXT: [[TMP28:%.]] = load i32, i32 [[TMP27]], align 4, !tbaa [[TBAA8]]
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// CHECK3-NEXT: [[TMP42:%.]] = load i32, i32 [[I7]], align 4, !tbaa [[TBAA8]]		// CHECK3-NEXT: [[TMP42:%.]] = load i32, i32 [[I7]], align 4, !tbaa [[TBAA8]]
// CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP42]] to float		// CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP42]] to float
// CHECK3-NEXT: store float [[CONV]], float* [[REF_TMP15]], align 4, !tbaa [[TBAA14]]		// CHECK3-NEXT: store float [[CONV]], float* [[REF_TMP15]], align 4, !tbaa [[TBAA14]]
// CHECK3-NEXT: [[TMP43:%.]] = bitcast float [[REF_TMP16]] to i8*		// CHECK3-NEXT: [[TMP43:%.]] = bitcast float [[REF_TMP16]] to i8*
// CHECK3-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP43]]) #[[ATTR5]]		// CHECK3-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP43]]) #[[ATTR5]]
// CHECK3-NEXT: [[TMP44:%.]] = load i32, i32 [[I7]], align 4, !tbaa [[TBAA8]]		// CHECK3-NEXT: [[TMP44:%.]] = load i32, i32 [[I7]], align 4, !tbaa [[TBAA8]]
// CHECK3-NEXT: [[CONV17:%.*]] = sitofp i32 [[TMP44]] to float		// CHECK3-NEXT: [[CONV17:%.*]] = sitofp i32 [[TMP44]] to float
// CHECK3-NEXT: store float [[CONV17]], float* [[REF_TMP16]], align 4, !tbaa [[TBAA14]]		// CHECK3-NEXT: store float [[CONV17]], float* [[REF_TMP16]], align 4, !tbaa [[TBAA14]]
// CHECK3-NEXT: call void @_ZNSt7complexIfEC1ERKfS2_(%"class.std::complex"* nonnull align 4 dereferenceable(8) [[REF_TMP14]], float* nonnull align 4 dereferenceable(4) [[REF_TMP15]], float* nonnull align 4 dereferenceable(4) [[REF_TMP16]]) #[[ATTR10]]		// CHECK3-NEXT: call void @_ZNSt7complexIfEC1ERKfS2_(%"class.std::complex"* nonnull align 4 dereferenceable(8) [[REF_TMP14]], float* nonnull align 4 dereferenceable(4) [[REF_TMP15]], float* nonnull align 4 dereferenceable(4) [[REF_TMP16]]) #[[ATTR12]]
// CHECK3-NEXT: [[CALL:%.]] = call nonnull align 4 dereferenceable(8) %"class.std::complex" @_ZNSt7complexIfEpLIfEERS0_RKS_IT_E(%"class.std::complex"* nonnull align 4 dereferenceable(8) [[PARTIAL_SUM5]], %"class.std::complex"* nonnull align 4 dereferenceable(8) [[REF_TMP14]]) #[[ATTR10]]		// CHECK3-NEXT: [[CALL:%.]] = call nonnull align 4 dereferenceable(8) %"class.std::complex" @_ZNSt7complexIfEpLIfEERS0_RKS_IT_E(%"class.std::complex"* nonnull align 4 dereferenceable(8) [[PARTIAL_SUM5]], %"class.std::complex"* nonnull align 4 dereferenceable(8) [[REF_TMP14]]) #[[ATTR12]]
// CHECK3-NEXT: [[TMP45:%.]] = bitcast float [[REF_TMP16]] to i8*		// CHECK3-NEXT: [[TMP45:%.]] = bitcast float [[REF_TMP16]] to i8*
// CHECK3-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP45]]) #[[ATTR5]]		// CHECK3-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP45]]) #[[ATTR5]]
// CHECK3-NEXT: [[TMP46:%.]] = bitcast float [[REF_TMP15]] to i8*		// CHECK3-NEXT: [[TMP46:%.]] = bitcast float [[REF_TMP15]] to i8*
// CHECK3-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP46]]) #[[ATTR5]]		// CHECK3-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP46]]) #[[ATTR5]]
// CHECK3-NEXT: [[TMP47:%.]] = bitcast %"class.std::complex" [[REF_TMP14]] to i8*		// CHECK3-NEXT: [[TMP47:%.]] = bitcast %"class.std::complex" [[REF_TMP14]] to i8*
// CHECK3-NEXT: call void @llvm.lifetime.end.p0i8(i64 8, i8* [[TMP47]]) #[[ATTR5]]		// CHECK3-NEXT: call void @llvm.lifetime.end.p0i8(i64 8, i8* [[TMP47]]) #[[ATTR5]]
// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]		// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK3: omp.body.continue:		// CHECK3: omp.body.continue:
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// CHECK3-NEXT: [[TMP57:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0		// CHECK3-NEXT: [[TMP57:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0
// CHECK3-NEXT: [[TMP58:%.]] = bitcast %"class.std::complex" [[PARTIAL_SUM5]] to i8*		// CHECK3-NEXT: [[TMP58:%.]] = bitcast %"class.std::complex" [[PARTIAL_SUM5]] to i8*
// CHECK3-NEXT: store i8* [[TMP58]], i8** [[TMP57]], align 8		// CHECK3-NEXT: store i8* [[TMP58]], i8** [[TMP57]], align 8
// CHECK3-NEXT: [[TMP59:%.]] = bitcast [1 x i8]* [[DOTOMP_REDUCTION_RED_LIST]] to i8*		// CHECK3-NEXT: [[TMP59:%.]] = bitcast [1 x i8]* [[DOTOMP_REDUCTION_RED_LIST]] to i8*
// CHECK3-NEXT: [[TMP60:%.]] = call i32 @__kmpc_nvptx_parallel_reduce_nowait_v2(%struct.ident_t @[[GLOB1]], i32 [[TMP56]], i32 1, i64 8, i8* [[TMP59]], void (i8, i16, i16, i16) @_omp_reduction_shuffle_and_reduce_func, void (i8, i32) @_omp_reduction_inter_warp_copy_func)		// CHECK3-NEXT: [[TMP60:%.]] = call i32 @__kmpc_nvptx_parallel_reduce_nowait_v2(%struct.ident_t @[[GLOB1]], i32 [[TMP56]], i32 1, i64 8, i8* [[TMP59]], void (i8, i16, i16, i16) @_omp_reduction_shuffle_and_reduce_func, void (i8, i32) @_omp_reduction_inter_warp_copy_func)
// CHECK3-NEXT: [[TMP61:%.*]] = icmp eq i32 [[TMP60]], 1		// CHECK3-NEXT: [[TMP61:%.*]] = icmp eq i32 [[TMP60]], 1
// CHECK3-NEXT: br i1 [[TMP61]], label [[DOTOMP_REDUCTION_THEN:%.]], label [[DOTOMP_REDUCTION_DONE:%.]]		// CHECK3-NEXT: br i1 [[TMP61]], label [[DOTOMP_REDUCTION_THEN:%.]], label [[DOTOMP_REDUCTION_DONE:%.]]
// CHECK3: .omp.reduction.then:		// CHECK3: .omp.reduction.then:
// CHECK3-NEXT: [[CALL21:%.]] = call nonnull align 4 dereferenceable(8) %"class.std::complex" @_ZNSt7complexIfEpLIfEERS0_RKS_IT_E(%"class.std::complex"* nonnull align 4 dereferenceable(8) [[TMP2]], %"class.std::complex"* nonnull align 4 dereferenceable(8) [[PARTIAL_SUM5]]) #[[ATTR10]]		// CHECK3-NEXT: [[CALL21:%.]] = call nonnull align 4 dereferenceable(8) %"class.std::complex" @_ZNSt7complexIfEpLIfEERS0_RKS_IT_E(%"class.std::complex"* nonnull align 4 dereferenceable(8) [[TMP2]], %"class.std::complex"* nonnull align 4 dereferenceable(8) [[PARTIAL_SUM5]]) #[[ATTR12]]
// CHECK3-NEXT: call void @__kmpc_nvptx_end_reduce_nowait(i32 [[TMP56]])		// CHECK3-NEXT: call void @__kmpc_nvptx_end_reduce_nowait(i32 [[TMP56]])
// CHECK3-NEXT: br label [[DOTOMP_REDUCTION_DONE]]		// CHECK3-NEXT: br label [[DOTOMP_REDUCTION_DONE]]
// CHECK3: .omp.reduction.done:		// CHECK3: .omp.reduction.done:
// CHECK3-NEXT: [[TMP62:%.]] = bitcast i32 [[I7]] to i8*		// CHECK3-NEXT: [[TMP62:%.]] = bitcast i32 [[I7]] to i8*
// CHECK3-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP62]]) #[[ATTR5]]		// CHECK3-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP62]]) #[[ATTR5]]
// CHECK3-NEXT: [[TMP63:%.]] = bitcast %"class.std::complex" [[PARTIAL_SUM5]] to i8*		// CHECK3-NEXT: [[TMP63:%.]] = bitcast %"class.std::complex" [[PARTIAL_SUM5]] to i8*
// CHECK3-NEXT: call void @llvm.lifetime.end.p0i8(i64 8, i8* [[TMP63]]) #[[ATTR5]]		// CHECK3-NEXT: call void @llvm.lifetime.end.p0i8(i64 8, i8* [[TMP63]]) #[[ATTR5]]
// CHECK3-NEXT: [[TMP64:%.]] = bitcast i32 [[DOTOMP_IS_LAST]] to i8*		// CHECK3-NEXT: [[TMP64:%.]] = bitcast i32 [[DOTOMP_IS_LAST]] to i8*
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// CHECK3-SAME: (%"class.std::complex"* nonnull align 4 dereferenceable(8) [[THIS:%.]], %"class.std::complex" nonnull align 4 dereferenceable(8) [[__C:%.*]]) #[[ATTR4:[0-9]+]] comdat align 2 {		// CHECK3-SAME: (%"class.std::complex"* nonnull align 4 dereferenceable(8) [[THIS:%.]], %"class.std::complex" nonnull align 4 dereferenceable(8) [[__C:%.*]]) #[[ATTR4:[0-9]+]] comdat align 2 {
// CHECK3-NEXT: entry:		// CHECK3-NEXT: entry:
// CHECK3-NEXT: [[THIS_ADDR:%.]] = alloca %"class.std::complex", align 8		// CHECK3-NEXT: [[THIS_ADDR:%.]] = alloca %"class.std::complex", align 8
// CHECK3-NEXT: [[__C_ADDR:%.]] = alloca %"class.std::complex", align 8		// CHECK3-NEXT: [[__C_ADDR:%.]] = alloca %"class.std::complex", align 8
// CHECK3-NEXT: store %"class.std::complex"* [[THIS]], %"class.std::complex"** [[THIS_ADDR]], align 8, !tbaa [[TBAA12]]		// CHECK3-NEXT: store %"class.std::complex"* [[THIS]], %"class.std::complex"** [[THIS_ADDR]], align 8, !tbaa [[TBAA12]]
// CHECK3-NEXT: store %"class.std::complex"* [[__C]], %"class.std::complex"** [[__C_ADDR]], align 8, !tbaa [[TBAA12]]		// CHECK3-NEXT: store %"class.std::complex"* [[__C]], %"class.std::complex"** [[__C_ADDR]], align 8, !tbaa [[TBAA12]]
// CHECK3-NEXT: [[THIS1:%.]] = load %"class.std::complex", %"class.std::complex"** [[THIS_ADDR]], align 8		// CHECK3-NEXT: [[THIS1:%.]] = load %"class.std::complex", %"class.std::complex"** [[THIS_ADDR]], align 8
// CHECK3-NEXT: [[TMP0:%.]] = load %"class.std::complex", %"class.std::complex"** [[__C_ADDR]], align 8, !tbaa [[TBAA12]]		// CHECK3-NEXT: [[TMP0:%.]] = load %"class.std::complex", %"class.std::complex"** [[__C_ADDR]], align 8, !tbaa [[TBAA12]]
// CHECK3-NEXT: [[CALL:%.]] = call float @_ZNKSt7complexIfE4realEv(%"class.std::complex" nonnull align 4 dereferenceable(8) [[TMP0]]) #[[ATTR10]]		// CHECK3-NEXT: [[CALL:%.]] = call float @_ZNKSt7complexIfE4realEv(%"class.std::complex" nonnull align 4 dereferenceable(8) [[TMP0]]) #[[ATTR12]]
// CHECK3-NEXT: [[__RE_:%.]] = getelementptr inbounds %"class.std::complex", %"class.std::complex" [[THIS1]], i32 0, i32 0		// CHECK3-NEXT: [[__RE_:%.]] = getelementptr inbounds %"class.std::complex", %"class.std::complex" [[THIS1]], i32 0, i32 0
// CHECK3-NEXT: [[TMP1:%.]] = load float, float [[__RE_]], align 4, !tbaa [[TBAA16:![0-9]+]]		// CHECK3-NEXT: [[TMP1:%.]] = load float, float [[__RE_]], align 4, !tbaa [[TBAA16:![0-9]+]]
// CHECK3-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CALL]]		// CHECK3-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CALL]]
// CHECK3-NEXT: store float [[ADD]], float* [[__RE_]], align 4, !tbaa [[TBAA16]]		// CHECK3-NEXT: store float [[ADD]], float* [[__RE_]], align 4, !tbaa [[TBAA16]]
// CHECK3-NEXT: [[TMP2:%.]] = load %"class.std::complex", %"class.std::complex"** [[__C_ADDR]], align 8, !tbaa [[TBAA12]]		// CHECK3-NEXT: [[TMP2:%.]] = load %"class.std::complex", %"class.std::complex"** [[__C_ADDR]], align 8, !tbaa [[TBAA12]]
// CHECK3-NEXT: [[CALL2:%.]] = call float @_ZNKSt7complexIfE4imagEv(%"class.std::complex" nonnull align 4 dereferenceable(8) [[TMP2]]) #[[ATTR10]]		// CHECK3-NEXT: [[CALL2:%.]] = call float @_ZNKSt7complexIfE4imagEv(%"class.std::complex" nonnull align 4 dereferenceable(8) [[TMP2]]) #[[ATTR12]]
// CHECK3-NEXT: [[__IM_:%.]] = getelementptr inbounds %"class.std::complex", %"class.std::complex" [[THIS1]], i32 0, i32 1		// CHECK3-NEXT: [[__IM_:%.]] = getelementptr inbounds %"class.std::complex", %"class.std::complex" [[THIS1]], i32 0, i32 1
// CHECK3-NEXT: [[TMP3:%.]] = load float, float [[__IM_]], align 4, !tbaa [[TBAA18:![0-9]+]]		// CHECK3-NEXT: [[TMP3:%.]] = load float, float [[__IM_]], align 4, !tbaa [[TBAA18:![0-9]+]]
// CHECK3-NEXT: [[ADD3:%.*]] = fadd float [[TMP3]], [[CALL2]]		// CHECK3-NEXT: [[ADD3:%.*]] = fadd float [[TMP3]], [[CALL2]]
// CHECK3-NEXT: store float [[ADD3]], float* [[__IM_]], align 4, !tbaa [[TBAA18]]		// CHECK3-NEXT: store float [[ADD3]], float* [[__IM_]], align 4, !tbaa [[TBAA18]]
// CHECK3-NEXT: ret %"class.std::complex"* [[THIS1]]		// CHECK3-NEXT: ret %"class.std::complex"* [[THIS1]]
//		//
//		//
// CHECK3-LABEL: define {{[^@]+}}@_omp_reduction_shuffle_and_reduce_func		// CHECK3-LABEL: define {{[^@]+}}@_omp_reduction_shuffle_and_reduce_func
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// CHECK3-NEXT: [[TMP10:%.]] = load i8, i8** [[TMP9]], align 8		// CHECK3-NEXT: [[TMP10:%.]] = load i8, i8** [[TMP9]], align 8
// CHECK3-NEXT: [[TMP11:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST]], i64 0, i64 0		// CHECK3-NEXT: [[TMP11:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST]], i64 0, i64 0
// CHECK3-NEXT: [[TMP12:%.]] = bitcast i8 [[TMP10]] to %"class.std::complex"*		// CHECK3-NEXT: [[TMP12:%.]] = bitcast i8 [[TMP10]] to %"class.std::complex"*
// CHECK3-NEXT: [[TMP13:%.]] = getelementptr %"class.std::complex", %"class.std::complex" [[TMP12]], i64 1		// CHECK3-NEXT: [[TMP13:%.]] = getelementptr %"class.std::complex", %"class.std::complex" [[TMP12]], i64 1
// CHECK3-NEXT: [[TMP14:%.]] = bitcast %"class.std::complex" [[TMP13]] to i8*		// CHECK3-NEXT: [[TMP14:%.]] = bitcast %"class.std::complex" [[TMP13]] to i8*
// CHECK3-NEXT: [[TMP15:%.]] = bitcast %"class.std::complex" [[TMP12]] to i64*		// CHECK3-NEXT: [[TMP15:%.]] = bitcast %"class.std::complex" [[TMP12]] to i64*
// CHECK3-NEXT: [[TMP16:%.]] = bitcast %"class.std::complex" [[DOTOMP_REDUCTION_ELEMENT]] to i64*		// CHECK3-NEXT: [[TMP16:%.]] = bitcast %"class.std::complex" [[DOTOMP_REDUCTION_ELEMENT]] to i64*
// CHECK3-NEXT: [[TMP17:%.]] = load i64, i64 [[TMP15]], align 4		// CHECK3-NEXT: [[TMP17:%.]] = load i64, i64 [[TMP15]], align 4
// CHECK3-NEXT: [[TMP18:%.*]] = call i32 @__kmpc_get_warp_size()		// CHECK3-NEXT: [[NVPTX_WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size()
// CHECK3-NEXT: [[TMP19:%.*]] = trunc i32 [[TMP18]] to i16		// CHECK3-NEXT: [[TMP18:%.*]] = trunc i32 [[NVPTX_WARP_SIZE]] to i16
// CHECK3-NEXT: [[TMP20:%.*]] = call i64 @__kmpc_shuffle_int64(i64 [[TMP17]], i16 [[TMP7]], i16 [[TMP19]])		// CHECK3-NEXT: [[TMP19:%.*]] = call i64 @__kmpc_shuffle_int64(i64 [[TMP17]], i16 [[TMP7]], i16 [[TMP18]])
// CHECK3-NEXT: store i64 [[TMP20]], i64* [[TMP16]], align 4		// CHECK3-NEXT: store i64 [[TMP19]], i64* [[TMP16]], align 4
// CHECK3-NEXT: [[TMP21:%.]] = getelementptr i64, i64 [[TMP15]], i64 1		// CHECK3-NEXT: [[TMP20:%.]] = getelementptr i64, i64 [[TMP15]], i64 1
// CHECK3-NEXT: [[TMP22:%.]] = getelementptr i64, i64 [[TMP16]], i64 1		// CHECK3-NEXT: [[TMP21:%.]] = getelementptr i64, i64 [[TMP16]], i64 1
// CHECK3-NEXT: [[TMP23:%.]] = bitcast %"class.std::complex" [[DOTOMP_REDUCTION_ELEMENT]] to i8*		// CHECK3-NEXT: [[TMP22:%.]] = bitcast %"class.std::complex" [[DOTOMP_REDUCTION_ELEMENT]] to i8*
// CHECK3-NEXT: store i8* [[TMP23]], i8** [[TMP11]], align 8, !tbaa [[TBAA12]]		// CHECK3-NEXT: store i8* [[TMP22]], i8** [[TMP11]], align 8, !tbaa [[TBAA12]]
// CHECK3-NEXT: [[TMP24:%.*]] = icmp eq i16 [[TMP8]], 0		// CHECK3-NEXT: [[TMP23:%.*]] = icmp eq i16 [[TMP8]], 0
// CHECK3-NEXT: [[TMP25:%.*]] = icmp eq i16 [[TMP8]], 1		// CHECK3-NEXT: [[TMP24:%.*]] = icmp eq i16 [[TMP8]], 1
// CHECK3-NEXT: [[TMP26:%.*]] = icmp ult i16 [[TMP6]], [[TMP7]]		// CHECK3-NEXT: [[TMP25:%.*]] = icmp ult i16 [[TMP6]], [[TMP7]]
// CHECK3-NEXT: [[TMP27:%.*]] = and i1 [[TMP25]], [[TMP26]]		// CHECK3-NEXT: [[TMP26:%.*]] = and i1 [[TMP24]], [[TMP25]]
// CHECK3-NEXT: [[TMP28:%.*]] = icmp eq i16 [[TMP8]], 2		// CHECK3-NEXT: [[TMP27:%.*]] = icmp eq i16 [[TMP8]], 2
// CHECK3-NEXT: [[TMP29:%.*]] = and i16 [[TMP6]], 1		// CHECK3-NEXT: [[TMP28:%.*]] = and i16 [[TMP6]], 1
// CHECK3-NEXT: [[TMP30:%.*]] = icmp eq i16 [[TMP29]], 0		// CHECK3-NEXT: [[TMP29:%.*]] = icmp eq i16 [[TMP28]], 0
// CHECK3-NEXT: [[TMP31:%.*]] = and i1 [[TMP28]], [[TMP30]]		// CHECK3-NEXT: [[TMP30:%.*]] = and i1 [[TMP27]], [[TMP29]]
// CHECK3-NEXT: [[TMP32:%.*]] = icmp sgt i16 [[TMP7]], 0		// CHECK3-NEXT: [[TMP31:%.*]] = icmp sgt i16 [[TMP7]], 0
// CHECK3-NEXT: [[TMP33:%.*]] = and i1 [[TMP31]], [[TMP32]]		// CHECK3-NEXT: [[TMP32:%.*]] = and i1 [[TMP30]], [[TMP31]]
// CHECK3-NEXT: [[TMP34:%.*]] = or i1 [[TMP24]], [[TMP27]]		// CHECK3-NEXT: [[TMP33:%.*]] = or i1 [[TMP23]], [[TMP26]]
// CHECK3-NEXT: [[TMP35:%.*]] = or i1 [[TMP34]], [[TMP33]]		// CHECK3-NEXT: [[TMP34:%.*]] = or i1 [[TMP33]], [[TMP32]]
// CHECK3-NEXT: br i1 [[TMP35]], label [[THEN:%.]], label [[ELSE:%.]]		// CHECK3-NEXT: br i1 [[TMP34]], label [[THEN:%.]], label [[ELSE:%.]]
// CHECK3: then:		// CHECK3: then:
// CHECK3-NEXT: [[TMP36:%.]] = bitcast [1 x i8]* [[TMP5]] to i8*		// CHECK3-NEXT: [[TMP35:%.]] = bitcast [1 x i8]* [[TMP5]] to i8*
// CHECK3-NEXT: [[TMP37:%.]] = bitcast [1 x i8]* [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST]] to i8*		// CHECK3-NEXT: [[TMP36:%.]] = bitcast [1 x i8]* [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST]] to i8*
// CHECK3-NEXT: call void @"_omp$reduction$reduction_func"(i8* [[TMP36]], i8* [[TMP37]]) #[[ATTR5]]		// CHECK3-NEXT: call void @"_omp$reduction$reduction_func"(i8* [[TMP35]], i8* [[TMP36]]) #[[ATTR5]]
// CHECK3-NEXT: br label [[IFCONT:%.*]]		// CHECK3-NEXT: br label [[IFCONT:%.*]]
// CHECK3: else:		// CHECK3: else:
// CHECK3-NEXT: br label [[IFCONT]]		// CHECK3-NEXT: br label [[IFCONT]]
// CHECK3: ifcont:		// CHECK3: ifcont:
// CHECK3-NEXT: [[TMP38:%.*]] = icmp eq i16 [[TMP8]], 1		// CHECK3-NEXT: [[TMP37:%.*]] = icmp eq i16 [[TMP8]], 1
// CHECK3-NEXT: [[TMP39:%.*]] = icmp uge i16 [[TMP6]], [[TMP7]]		// CHECK3-NEXT: [[TMP38:%.*]] = icmp uge i16 [[TMP6]], [[TMP7]]
// CHECK3-NEXT: [[TMP40:%.*]] = and i1 [[TMP38]], [[TMP39]]		// CHECK3-NEXT: [[TMP39:%.*]] = and i1 [[TMP37]], [[TMP38]]
// CHECK3-NEXT: br i1 [[TMP40]], label [[THEN4:%.]], label [[ELSE5:%.]]		// CHECK3-NEXT: br i1 [[TMP39]], label [[THEN4:%.]], label [[ELSE5:%.]]
// CHECK3: then4:		// CHECK3: then4:
// CHECK3-NEXT: [[TMP41:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST]], i64 0, i64 0		// CHECK3-NEXT: [[TMP40:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST]], i64 0, i64 0
// CHECK3-NEXT: [[TMP42:%.]] = load i8, i8** [[TMP41]], align 8		// CHECK3-NEXT: [[TMP41:%.]] = load i8, i8** [[TMP40]], align 8
// CHECK3-NEXT: [[TMP43:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[TMP5]], i64 0, i64 0		// CHECK3-NEXT: [[TMP42:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[TMP5]], i64 0, i64 0
// CHECK3-NEXT: [[TMP44:%.]] = load i8, i8** [[TMP43]], align 8		// CHECK3-NEXT: [[TMP43:%.]] = load i8, i8** [[TMP42]], align 8
// CHECK3-NEXT: [[TMP45:%.]] = bitcast i8 [[TMP42]] to %"class.std::complex"*		// CHECK3-NEXT: [[TMP44:%.]] = bitcast i8 [[TMP41]] to %"class.std::complex"*
// CHECK3-NEXT: [[TMP46:%.]] = bitcast i8 [[TMP44]] to %"class.std::complex"*		// CHECK3-NEXT: [[TMP45:%.]] = bitcast i8 [[TMP43]] to %"class.std::complex"*
// CHECK3-NEXT: [[TMP47:%.]] = bitcast %"class.std::complex" [[TMP46]] to i8*		// CHECK3-NEXT: [[TMP46:%.]] = bitcast %"class.std::complex" [[TMP45]] to i8*
// CHECK3-NEXT: [[TMP48:%.]] = bitcast %"class.std::complex" [[TMP45]] to i8*		// CHECK3-NEXT: [[TMP47:%.]] = bitcast %"class.std::complex" [[TMP44]] to i8*
// CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP47]], i8* align 4 [[TMP48]], i64 8, i1 false), !tbaa.struct !21		// CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP46]], i8* align 4 [[TMP47]], i64 8, i1 false), !tbaa.struct !21
// CHECK3-NEXT: br label [[IFCONT6:%.*]]		// CHECK3-NEXT: br label [[IFCONT6:%.*]]
// CHECK3: else5:		// CHECK3: else5:
// CHECK3-NEXT: br label [[IFCONT6]]		// CHECK3-NEXT: br label [[IFCONT6]]
// CHECK3: ifcont6:		// CHECK3: ifcont6:
// CHECK3-NEXT: ret void		// CHECK3-NEXT: ret void
//		//
//		//
// CHECK3-LABEL: define {{[^@]+}}@_omp_reduction_inter_warp_copy_func		// CHECK3-LABEL: define {{[^@]+}}@_omp_reduction_inter_warp_copy_func
// CHECK3-SAME: (i8* [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR6]] {		// CHECK3-SAME: (i8* [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR6]] {
// CHECK3-NEXT: entry:		// CHECK3-NEXT: entry:
// CHECK3-NEXT: [[DOTADDR:%.]] = alloca i8, align 8		// CHECK3-NEXT: [[DOTADDR:%.]] = alloca i8, align 8
// CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4		// CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
// CHECK3-NEXT: [[DOTCNT_ADDR:%.*]] = alloca i32, align 4		// CHECK3-NEXT: [[DOTCNT_ADDR:%.*]] = alloca i32, align 4
// CHECK3-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB1]])		// CHECK3-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB1]])
// CHECK3-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8, !tbaa [[TBAA12]]		// CHECK3-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8, !tbaa [[TBAA12]]
// CHECK3-NEXT: store i32 [[TMP1]], i32* [[DOTADDR1]], align 4, !tbaa [[TBAA8]]		// CHECK3-NEXT: store i32 [[TMP1]], i32* [[DOTADDR1]], align 4, !tbaa [[TBAA8]]
// CHECK3-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block()		// CHECK3-NEXT: [[NVPTX_TID:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block()
// CHECK3-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block()		// CHECK3-NEXT: [[NVPTX_TID2:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block()
// CHECK3-NEXT: [[NVPTX_LANE_ID:%.*]] = and i32 [[TMP4]], 31		// CHECK3-NEXT: [[NVPTX_LANE_ID:%.*]] = and i32 [[NVPTX_TID2]], 31
// CHECK3-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block()		// CHECK3-NEXT: [[NVPTX_TID3:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block()
// CHECK3-NEXT: [[NVPTX_WARP_ID:%.*]] = ashr i32 [[TMP5]], 5		// CHECK3-NEXT: [[NVPTX_WARP_ID:%.*]] = ashr i32 [[NVPTX_TID3]], 5
// CHECK3-NEXT: [[TMP6:%.]] = load i8, i8** [[DOTADDR]], align 8		// CHECK3-NEXT: [[TMP3:%.]] = load i8, i8** [[DOTADDR]], align 8
// CHECK3-NEXT: [[TMP7:%.]] = bitcast i8 [[TMP6]] to [1 x i8]		// CHECK3-NEXT: [[TMP4:%.]] = bitcast i8 [[TMP3]] to [1 x i8]
// CHECK3-NEXT: store i32 0, i32* [[DOTCNT_ADDR]], align 4, !tbaa [[TBAA8]]		// CHECK3-NEXT: store i32 0, i32* [[DOTCNT_ADDR]], align 4, !tbaa [[TBAA8]]
// CHECK3-NEXT: br label [[PRECOND:%.*]]		// CHECK3-NEXT: br label [[PRECOND:%.*]]
// CHECK3: precond:		// CHECK3: precond:
// CHECK3-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTCNT_ADDR]], align 4, !tbaa [[TBAA8]]		// CHECK3-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTCNT_ADDR]], align 4, !tbaa [[TBAA8]]
// CHECK3-NEXT: [[TMP9:%.*]] = icmp ult i32 [[TMP8]], 2		// CHECK3-NEXT: [[TMP6:%.*]] = icmp ult i32 [[TMP5]], 2
// CHECK3-NEXT: br i1 [[TMP9]], label [[BODY:%.]], label [[EXIT:%.]]		// CHECK3-NEXT: br i1 [[TMP6]], label [[BODY:%.]], label [[EXIT:%.]]
// CHECK3: body:		// CHECK3: body:
// CHECK3-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB4:[0-9]+]], i32 [[TMP2]])		// CHECK3-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB4:[0-9]+]], i32 [[TMP2]])
// CHECK3-NEXT: [[WARP_MASTER:%.*]] = icmp eq i32 [[NVPTX_LANE_ID]], 0		// CHECK3-NEXT: [[WARP_MASTER:%.*]] = icmp eq i32 [[NVPTX_LANE_ID]], 0
// CHECK3-NEXT: br i1 [[WARP_MASTER]], label [[THEN:%.]], label [[ELSE:%.]]		// CHECK3-NEXT: br i1 [[WARP_MASTER]], label [[THEN:%.]], label [[ELSE:%.]]
// CHECK3: then:		// CHECK3: then:
// CHECK3-NEXT: [[TMP10:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[TMP7]], i64 0, i64 0		// CHECK3-NEXT: [[TMP7:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[TMP4]], i64 0, i64 0
// CHECK3-NEXT: [[TMP11:%.]] = load i8, i8** [[TMP10]], align 8, !tbaa [[TBAA12]]		// CHECK3-NEXT: [[TMP8:%.]] = load i8, i8** [[TMP7]], align 8, !tbaa [[TBAA12]]
// CHECK3-NEXT: [[TMP12:%.]] = bitcast i8 [[TMP11]] to i32*		// CHECK3-NEXT: [[TMP9:%.]] = bitcast i8 [[TMP8]] to i32*
// CHECK3-NEXT: [[TMP13:%.]] = getelementptr i32, i32 [[TMP12]], i32 [[TMP8]]		// CHECK3-NEXT: [[TMP10:%.]] = getelementptr i32, i32 [[TMP9]], i32 [[TMP5]]
// CHECK3-NEXT: [[TMP14:%.]] = getelementptr inbounds [32 x i32], [32 x i32] addrspace(3) @__openmp_nvptx_data_transfer_temporary_storage, i64 0, i32 [[NVPTX_WARP_ID]]		// CHECK3-NEXT: [[TMP11:%.]] = getelementptr inbounds [32 x i32], [32 x i32] addrspace(3) @__openmp_nvptx_data_transfer_temporary_storage, i64 0, i32 [[NVPTX_WARP_ID]]
// CHECK3-NEXT: [[TMP15:%.]] = load i32, i32 [[TMP13]], align 4		// CHECK3-NEXT: [[TMP12:%.]] = load i32, i32 [[TMP10]], align 4
// CHECK3-NEXT: store volatile i32 [[TMP15]], i32 addrspace(3)* [[TMP14]], align 4		// CHECK3-NEXT: store volatile i32 [[TMP12]], i32 addrspace(3)* [[TMP11]], align 4
// CHECK3-NEXT: br label [[IFCONT:%.*]]		// CHECK3-NEXT: br label [[IFCONT:%.*]]
// CHECK3: else:		// CHECK3: else:
// CHECK3-NEXT: br label [[IFCONT]]		// CHECK3-NEXT: br label [[IFCONT]]
// CHECK3: ifcont:		// CHECK3: ifcont:
// CHECK3-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB4]], i32 [[TMP2]])		// CHECK3-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB4]], i32 [[TMP2]])
// CHECK3-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTADDR1]], align 4, !tbaa [[TBAA8]]		// CHECK3-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTADDR1]], align 4, !tbaa [[TBAA8]]
// CHECK3-NEXT: [[IS_ACTIVE_THREAD:%.*]] = icmp ult i32 [[TMP3]], [[TMP16]]		// CHECK3-NEXT: [[IS_ACTIVE_THREAD:%.*]] = icmp ult i32 [[NVPTX_TID]], [[TMP13]]
// CHECK3-NEXT: br i1 [[IS_ACTIVE_THREAD]], label [[THEN2:%.]], label [[ELSE3:%.]]		// CHECK3-NEXT: br i1 [[IS_ACTIVE_THREAD]], label [[THEN4:%.]], label [[ELSE5:%.]]
// CHECK3: then2:		// CHECK3: then2:
// CHECK3-NEXT: [[TMP17:%.]] = getelementptr inbounds [32 x i32], [32 x i32] addrspace(3) @__openmp_nvptx_data_transfer_temporary_storage, i64 0, i32 [[TMP3]]		// CHECK3-NEXT: [[TMP14:%.]] = getelementptr inbounds [32 x i32], [32 x i32] addrspace(3) @__openmp_nvptx_data_transfer_temporary_storage, i64 0, i32 [[NVPTX_TID]]
// CHECK3-NEXT: [[TMP18:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[TMP7]], i64 0, i64 0		// CHECK3-NEXT: [[TMP15:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[TMP4]], i64 0, i64 0
// CHECK3-NEXT: [[TMP19:%.]] = load i8, i8** [[TMP18]], align 8, !tbaa [[TBAA12]]		// CHECK3-NEXT: [[TMP16:%.]] = load i8, i8** [[TMP15]], align 8, !tbaa [[TBAA12]]
// CHECK3-NEXT: [[TMP20:%.]] = bitcast i8 [[TMP19]] to i32*		// CHECK3-NEXT: [[TMP17:%.]] = bitcast i8 [[TMP16]] to i32*
// CHECK3-NEXT: [[TMP21:%.]] = getelementptr i32, i32 [[TMP20]], i32 [[TMP8]]		// CHECK3-NEXT: [[TMP18:%.]] = getelementptr i32, i32 [[TMP17]], i32 [[TMP5]]
// CHECK3-NEXT: [[TMP22:%.]] = load volatile i32, i32 addrspace(3) [[TMP17]], align 4, !tbaa [[TBAA8]]		// CHECK3-NEXT: [[TMP19:%.]] = load volatile i32, i32 addrspace(3) [[TMP14]], align 4, !tbaa [[TBAA8]]
// CHECK3-NEXT: store i32 [[TMP22]], i32* [[TMP21]], align 4, !tbaa [[TBAA8]]		// CHECK3-NEXT: store i32 [[TMP19]], i32* [[TMP18]], align 4, !tbaa [[TBAA8]]
// CHECK3-NEXT: br label [[IFCONT4:%.*]]		// CHECK3-NEXT: br label [[IFCONT6:%.*]]
// CHECK3: else3:		// CHECK3: else3:
// CHECK3-NEXT: br label [[IFCONT4]]		// CHECK3-NEXT: br label [[IFCONT6]]
// CHECK3: ifcont4:		// CHECK3: ifcont4:
// CHECK3-NEXT: [[TMP23:%.*]] = add nsw i32 [[TMP8]], 1		// CHECK3-NEXT: [[TMP20:%.*]] = add nsw i32 [[TMP5]], 1
// CHECK3-NEXT: store i32 [[TMP23]], i32* [[DOTCNT_ADDR]], align 4, !tbaa [[TBAA8]]		// CHECK3-NEXT: store i32 [[TMP20]], i32* [[DOTCNT_ADDR]], align 4, !tbaa [[TBAA8]]
// CHECK3-NEXT: br label [[PRECOND]]		// CHECK3-NEXT: br label [[PRECOND]]
// CHECK3: exit:		// CHECK3: exit:
// CHECK3-NEXT: ret void		// CHECK3-NEXT: ret void
//		//
//		//
// CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__1_wrapper		// CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__1_wrapper
// CHECK3-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR6]] {		// CHECK3-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR6]] {
// CHECK3-NEXT: entry:		// CHECK3-NEXT: entry:
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// CHECK3-NEXT: ret void		// CHECK3-NEXT: ret void
//		//
//		//
// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z17complex_reductionIdEvv_l16		// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z17complex_reductionIdEvv_l16
// CHECK3-SAME: () #[[ATTR0]] {		// CHECK3-SAME: () #[[ATTR0]] {
// CHECK3-NEXT: entry:		// CHECK3-NEXT: entry:
// CHECK3-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4		// CHECK3-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
// CHECK3-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4		// CHECK3-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
// CHECK3-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 1, i1 true, i1 true)		// CHECK3-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z17complex_reductionIdEvv_l16_kernel_info, i1 true)
// CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1		// CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
// CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]		// CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
// CHECK3: user_code.entry:		// CHECK3: user_code.entry:
// CHECK3-NEXT: [[TMP1:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB1]])		// CHECK3-NEXT: [[TMP1:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB1]])
// CHECK3-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4		// CHECK3-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
// CHECK3-NEXT: store i32 [[TMP1]], i32* [[DOTTHREADID_TEMP_]], align 4, !tbaa [[TBAA8]]		// CHECK3-NEXT: store i32 [[TMP1]], i32* [[DOTTHREADID_TEMP_]], align 4, !tbaa [[TBAA8]]
// CHECK3-NEXT: call void @__omp_outlined__2(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]]) #[[ATTR5]]		// CHECK3-NEXT: call void @__omp_outlined__2(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]]) #[[ATTR5]]
// CHECK3-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true)		// CHECK3-NEXT: call void @__kmpc_target_deinit(i1 true)
// CHECK3-NEXT: ret void		// CHECK3-NEXT: ret void
// CHECK3: worker.exit:		// CHECK3: worker.exit:
// CHECK3-NEXT: ret void		// CHECK3-NEXT: ret void
//		//
//		//
// CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__2		// CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__2
// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {		// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
// CHECK3-NEXT: entry:		// CHECK3-NEXT: entry:
// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8		// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8
// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8		// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8
// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4		// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4		// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4
// CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4		// CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
// CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4		// CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4		// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4		// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
// CHECK3-NEXT: [[IB:%.*]] = alloca i32, align 4		// CHECK3-NEXT: [[IB:%.*]] = alloca i32, align 4
// CHECK3-NEXT: [[REF_TMP:%.*]] = alloca double, align 8		// CHECK3-NEXT: [[REF_TMP:%.*]] = alloca double, align 8
// CHECK3-NEXT: [[REF_TMP2:%.*]] = alloca double, align 8		// CHECK3-NEXT: [[REF_TMP2:%.*]] = alloca double, align 8
// CHECK3-NEXT: [[CAPTURED_VARS_ADDRS:%.]] = alloca [3 x i8], align 8		// CHECK3-NEXT: [[CAPTURED_VARS_ADDRS:%.]] = alloca [3 x i8], align 8
// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8, !tbaa [[TBAA12]]		// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8, !tbaa [[TBAA12]]
// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8, !tbaa [[TBAA12]]		// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8, !tbaa [[TBAA12]]
// CHECK3-NEXT: [[ISTART:%.]] = call align 16 i8 @__kmpc_alloc_shared(i64 4)		// CHECK3-NEXT: [[ISTART:%.]] = call i8 @__kmpc_alloc_shared(i64 4)
// CHECK3-NEXT: [[ISTART_ON_STACK:%.]] = bitcast i8 [[ISTART]] to i32*		// CHECK3-NEXT: [[ISTART_ON_STACK:%.]] = bitcast i8 [[ISTART]] to i32*
// CHECK3-NEXT: [[IEND:%.]] = call align 16 i8 @__kmpc_alloc_shared(i64 4)		// CHECK3-NEXT: [[IEND:%.]] = call i8 @__kmpc_alloc_shared(i64 4)
// CHECK3-NEXT: [[IEND_ON_STACK:%.]] = bitcast i8 [[IEND]] to i32*		// CHECK3-NEXT: [[IEND_ON_STACK:%.]] = bitcast i8 [[IEND]] to i32*
// CHECK3-NEXT: [[PARTIAL_SUM:%.]] = call align 16 i8 @__kmpc_alloc_shared(i64 16)		// CHECK3-NEXT: [[PARTIAL_SUM:%.]] = call i8 @__kmpc_alloc_shared(i64 16)
// CHECK3-NEXT: [[PARTIAL_SUM_ON_STACK:%.]] = bitcast i8 [[PARTIAL_SUM]] to %"class.std::complex.0"*		// CHECK3-NEXT: [[PARTIAL_SUM_ON_STACK:%.]] = bitcast i8 [[PARTIAL_SUM]] to %"class.std::complex.0"*
// CHECK3-NEXT: [[TMP0:%.]] = bitcast i32 [[DOTOMP_IV]] to i8*		// CHECK3-NEXT: [[TMP0:%.]] = bitcast i32 [[DOTOMP_IV]] to i8*
// CHECK3-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP0]]) #[[ATTR5]]		// CHECK3-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP0]]) #[[ATTR5]]
// CHECK3-NEXT: [[TMP1:%.]] = bitcast i32 [[DOTOMP_LB]] to i8*		// CHECK3-NEXT: [[TMP1:%.]] = bitcast i32 [[DOTOMP_LB]] to i8*
// CHECK3-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP1]]) #[[ATTR5]]		// CHECK3-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP1]]) #[[ATTR5]]
// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4, !tbaa [[TBAA8]]		// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4, !tbaa [[TBAA8]]
// CHECK3-NEXT: [[TMP2:%.]] = bitcast i32 [[DOTOMP_UB]] to i8*		// CHECK3-NEXT: [[TMP2:%.]] = bitcast i32 [[DOTOMP_UB]] to i8*
// CHECK3-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP2]]) #[[ATTR5]]		// CHECK3-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP2]]) #[[ATTR5]]
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// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]		// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK3-NEXT: store i32 [[ADD]], i32* [[IB]], align 4, !tbaa [[TBAA8]]		// CHECK3-NEXT: store i32 [[ADD]], i32* [[IB]], align 4, !tbaa [[TBAA8]]
// CHECK3-NEXT: [[TMP14:%.]] = bitcast double [[REF_TMP]] to i8*		// CHECK3-NEXT: [[TMP14:%.]] = bitcast double [[REF_TMP]] to i8*
// CHECK3-NEXT: call void @llvm.lifetime.start.p0i8(i64 8, i8* [[TMP14]]) #[[ATTR5]]		// CHECK3-NEXT: call void @llvm.lifetime.start.p0i8(i64 8, i8* [[TMP14]]) #[[ATTR5]]
// CHECK3-NEXT: store double 0.000000e+00, double* [[REF_TMP]], align 8, !tbaa [[TBAA22:![0-9]+]]		// CHECK3-NEXT: store double 0.000000e+00, double* [[REF_TMP]], align 8, !tbaa [[TBAA22:![0-9]+]]
// CHECK3-NEXT: [[TMP15:%.]] = bitcast double [[REF_TMP2]] to i8*		// CHECK3-NEXT: [[TMP15:%.]] = bitcast double [[REF_TMP2]] to i8*
// CHECK3-NEXT: call void @llvm.lifetime.start.p0i8(i64 8, i8* [[TMP15]]) #[[ATTR5]]		// CHECK3-NEXT: call void @llvm.lifetime.start.p0i8(i64 8, i8* [[TMP15]]) #[[ATTR5]]
// CHECK3-NEXT: store double 0.000000e+00, double* [[REF_TMP2]], align 8, !tbaa [[TBAA22]]		// CHECK3-NEXT: store double 0.000000e+00, double* [[REF_TMP2]], align 8, !tbaa [[TBAA22]]
// CHECK3-NEXT: call void @_ZNSt7complexIdEC1ERKdS2_(%"class.std::complex.0"* nonnull align 8 dereferenceable(16) [[PARTIAL_SUM_ON_STACK]], double* nonnull align 8 dereferenceable(8) [[REF_TMP]], double* nonnull align 8 dereferenceable(8) [[REF_TMP2]]) #[[ATTR10]]		// CHECK3-NEXT: call void @_ZNSt7complexIdEC1ERKdS2_(%"class.std::complex.0"* nonnull align 8 dereferenceable(16) [[PARTIAL_SUM_ON_STACK]], double* nonnull align 8 dereferenceable(8) [[REF_TMP]], double* nonnull align 8 dereferenceable(8) [[REF_TMP2]]) #[[ATTR12]]
// CHECK3-NEXT: [[TMP16:%.]] = bitcast double [[REF_TMP2]] to i8*		// CHECK3-NEXT: [[TMP16:%.]] = bitcast double [[REF_TMP2]] to i8*
// CHECK3-NEXT: call void @llvm.lifetime.end.p0i8(i64 8, i8* [[TMP16]]) #[[ATTR5]]		// CHECK3-NEXT: call void @llvm.lifetime.end.p0i8(i64 8, i8* [[TMP16]]) #[[ATTR5]]
// CHECK3-NEXT: [[TMP17:%.]] = bitcast double [[REF_TMP]] to i8*		// CHECK3-NEXT: [[TMP17:%.]] = bitcast double [[REF_TMP]] to i8*
// CHECK3-NEXT: call void @llvm.lifetime.end.p0i8(i64 8, i8* [[TMP17]]) #[[ATTR5]]		// CHECK3-NEXT: call void @llvm.lifetime.end.p0i8(i64 8, i8* [[TMP17]]) #[[ATTR5]]
// CHECK3-NEXT: [[TMP18:%.]] = load i32, i32 [[IB]], align 4, !tbaa [[TBAA8]]		// CHECK3-NEXT: [[TMP18:%.]] = load i32, i32 [[IB]], align 4, !tbaa [[TBAA8]]
// CHECK3-NEXT: [[MUL3:%.*]] = mul nsw i32 [[TMP18]], 4		// CHECK3-NEXT: [[MUL3:%.*]] = mul nsw i32 [[TMP18]], 4
// CHECK3-NEXT: store i32 [[MUL3]], i32* [[ISTART_ON_STACK]], align 4, !tbaa [[TBAA8]]		// CHECK3-NEXT: store i32 [[MUL3]], i32* [[ISTART_ON_STACK]], align 4, !tbaa [[TBAA8]]
// CHECK3-NEXT: [[TMP19:%.]] = load i32, i32 [[IB]], align 4, !tbaa [[TBAA8]]		// CHECK3-NEXT: [[TMP19:%.]] = load i32, i32 [[IB]], align 4, !tbaa [[TBAA8]]
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// CHECK3-NEXT: [[__RE_ADDR:%.]] = alloca double, align 8		// CHECK3-NEXT: [[__RE_ADDR:%.]] = alloca double, align 8
// CHECK3-NEXT: [[__IM_ADDR:%.]] = alloca double, align 8		// CHECK3-NEXT: [[__IM_ADDR:%.]] = alloca double, align 8
// CHECK3-NEXT: store %"class.std::complex.0"* [[THIS]], %"class.std::complex.0"** [[THIS_ADDR]], align 8, !tbaa [[TBAA12]]		// CHECK3-NEXT: store %"class.std::complex.0"* [[THIS]], %"class.std::complex.0"** [[THIS_ADDR]], align 8, !tbaa [[TBAA12]]
// CHECK3-NEXT: store double* [[__RE]], double** [[__RE_ADDR]], align 8, !tbaa [[TBAA12]]		// CHECK3-NEXT: store double* [[__RE]], double** [[__RE_ADDR]], align 8, !tbaa [[TBAA12]]
// CHECK3-NEXT: store double* [[__IM]], double** [[__IM_ADDR]], align 8, !tbaa [[TBAA12]]		// CHECK3-NEXT: store double* [[__IM]], double** [[__IM_ADDR]], align 8, !tbaa [[TBAA12]]
// CHECK3-NEXT: [[THIS1:%.]] = load %"class.std::complex.0", %"class.std::complex.0"** [[THIS_ADDR]], align 8		// CHECK3-NEXT: [[THIS1:%.]] = load %"class.std::complex.0", %"class.std::complex.0"** [[THIS_ADDR]], align 8
// CHECK3-NEXT: [[TMP0:%.]] = load double, double** [[__RE_ADDR]], align 8		// CHECK3-NEXT: [[TMP0:%.]] = load double, double** [[__RE_ADDR]], align 8
// CHECK3-NEXT: [[TMP1:%.]] = load double, double** [[__IM_ADDR]], align 8		// CHECK3-NEXT: [[TMP1:%.]] = load double, double** [[__IM_ADDR]], align 8
// CHECK3-NEXT: call void @_ZNSt7complexIdEC2ERKdS2_(%"class.std::complex.0"* nonnull align 8 dereferenceable(16) [[THIS1]], double* nonnull align 8 dereferenceable(8) [[TMP0]], double* nonnull align 8 dereferenceable(8) [[TMP1]]) #[[ATTR10]]		// CHECK3-NEXT: call void @_ZNSt7complexIdEC2ERKdS2_(%"class.std::complex.0"* nonnull align 8 dereferenceable(16) [[THIS1]], double* nonnull align 8 dereferenceable(8) [[TMP0]], double* nonnull align 8 dereferenceable(8) [[TMP1]]) #[[ATTR12]]
// CHECK3-NEXT: ret void		// CHECK3-NEXT: ret void
//		//
//		//
// CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__3		// CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__3
// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i32 nonnull align 4 dereferenceable(4) [[ISTART:%.]], i32 nonnull align 4 dereferenceable(4) [[IEND:%.]], %"class.std::complex.0" nonnull align 8 dereferenceable(16) [[PARTIAL_SUM:%.*]]) #[[ATTR0]] {		// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i32 nonnull align 4 dereferenceable(4) [[ISTART:%.]], i32 nonnull align 4 dereferenceable(4) [[IEND:%.]], %"class.std::complex.0" nonnull align 8 dereferenceable(16) [[PARTIAL_SUM:%.*]]) #[[ATTR0]] {
// CHECK3-NEXT: entry:		// CHECK3-NEXT: entry:
// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8		// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8
// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8		// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8
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// CHECK3-NEXT: [[TMP21:%.]] = bitcast %"class.std::complex.0" [[PARTIAL_SUM5]] to i8*		// CHECK3-NEXT: [[TMP21:%.]] = bitcast %"class.std::complex.0" [[PARTIAL_SUM5]] to i8*
// CHECK3-NEXT: call void @llvm.lifetime.start.p0i8(i64 16, i8* [[TMP21]]) #[[ATTR5]]		// CHECK3-NEXT: call void @llvm.lifetime.start.p0i8(i64 16, i8* [[TMP21]]) #[[ATTR5]]
// CHECK3-NEXT: [[TMP22:%.]] = bitcast double [[REF_TMP]] to i8*		// CHECK3-NEXT: [[TMP22:%.]] = bitcast double [[REF_TMP]] to i8*
// CHECK3-NEXT: call void @llvm.lifetime.start.p0i8(i64 8, i8* [[TMP22]]) #[[ATTR5]]		// CHECK3-NEXT: call void @llvm.lifetime.start.p0i8(i64 8, i8* [[TMP22]]) #[[ATTR5]]
// CHECK3-NEXT: store double 0.000000e+00, double* [[REF_TMP]], align 8, !tbaa [[TBAA22]]		// CHECK3-NEXT: store double 0.000000e+00, double* [[REF_TMP]], align 8, !tbaa [[TBAA22]]
// CHECK3-NEXT: [[TMP23:%.]] = bitcast double [[REF_TMP6]] to i8*		// CHECK3-NEXT: [[TMP23:%.]] = bitcast double [[REF_TMP6]] to i8*
// CHECK3-NEXT: call void @llvm.lifetime.start.p0i8(i64 8, i8* [[TMP23]]) #[[ATTR5]]		// CHECK3-NEXT: call void @llvm.lifetime.start.p0i8(i64 8, i8* [[TMP23]]) #[[ATTR5]]
// CHECK3-NEXT: store double 0.000000e+00, double* [[REF_TMP6]], align 8, !tbaa [[TBAA22]]		// CHECK3-NEXT: store double 0.000000e+00, double* [[REF_TMP6]], align 8, !tbaa [[TBAA22]]
// CHECK3-NEXT: call void @_ZNSt7complexIdEC1ERKdS2_(%"class.std::complex.0"* nonnull align 8 dereferenceable(16) [[PARTIAL_SUM5]], double* nonnull align 8 dereferenceable(8) [[REF_TMP]], double* nonnull align 8 dereferenceable(8) [[REF_TMP6]]) #[[ATTR10]]		// CHECK3-NEXT: call void @_ZNSt7complexIdEC1ERKdS2_(%"class.std::complex.0"* nonnull align 8 dereferenceable(16) [[PARTIAL_SUM5]], double* nonnull align 8 dereferenceable(8) [[REF_TMP]], double* nonnull align 8 dereferenceable(8) [[REF_TMP6]]) #[[ATTR12]]
// CHECK3-NEXT: [[TMP24:%.]] = bitcast double [[REF_TMP6]] to i8*		// CHECK3-NEXT: [[TMP24:%.]] = bitcast double [[REF_TMP6]] to i8*
// CHECK3-NEXT: call void @llvm.lifetime.end.p0i8(i64 8, i8* [[TMP24]]) #[[ATTR5]]		// CHECK3-NEXT: call void @llvm.lifetime.end.p0i8(i64 8, i8* [[TMP24]]) #[[ATTR5]]
// CHECK3-NEXT: [[TMP25:%.]] = bitcast double [[REF_TMP]] to i8*		// CHECK3-NEXT: [[TMP25:%.]] = bitcast double [[REF_TMP]] to i8*
// CHECK3-NEXT: call void @llvm.lifetime.end.p0i8(i64 8, i8* [[TMP25]]) #[[ATTR5]]		// CHECK3-NEXT: call void @llvm.lifetime.end.p0i8(i64 8, i8* [[TMP25]]) #[[ATTR5]]
// CHECK3-NEXT: [[TMP26:%.]] = bitcast i32 [[I7]] to i8*		// CHECK3-NEXT: [[TMP26:%.]] = bitcast i32 [[I7]] to i8*
// CHECK3-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP26]]) #[[ATTR5]]		// CHECK3-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP26]]) #[[ATTR5]]
// CHECK3-NEXT: [[TMP27:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8		// CHECK3-NEXT: [[TMP27:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK3-NEXT: [[TMP28:%.]] = load i32, i32 [[TMP27]], align 4, !tbaa [[TBAA8]]		// CHECK3-NEXT: [[TMP28:%.]] = load i32, i32 [[TMP27]], align 4, !tbaa [[TBAA8]]
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// CHECK3-NEXT: [[TMP42:%.]] = load i32, i32 [[I7]], align 4, !tbaa [[TBAA8]]		// CHECK3-NEXT: [[TMP42:%.]] = load i32, i32 [[I7]], align 4, !tbaa [[TBAA8]]
// CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP42]] to double		// CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP42]] to double
// CHECK3-NEXT: store double [[CONV]], double* [[REF_TMP15]], align 8, !tbaa [[TBAA22]]		// CHECK3-NEXT: store double [[CONV]], double* [[REF_TMP15]], align 8, !tbaa [[TBAA22]]
// CHECK3-NEXT: [[TMP43:%.]] = bitcast double [[REF_TMP16]] to i8*		// CHECK3-NEXT: [[TMP43:%.]] = bitcast double [[REF_TMP16]] to i8*
// CHECK3-NEXT: call void @llvm.lifetime.start.p0i8(i64 8, i8* [[TMP43]]) #[[ATTR5]]		// CHECK3-NEXT: call void @llvm.lifetime.start.p0i8(i64 8, i8* [[TMP43]]) #[[ATTR5]]
// CHECK3-NEXT: [[TMP44:%.]] = load i32, i32 [[I7]], align 4, !tbaa [[TBAA8]]		// CHECK3-NEXT: [[TMP44:%.]] = load i32, i32 [[I7]], align 4, !tbaa [[TBAA8]]
// CHECK3-NEXT: [[CONV17:%.*]] = sitofp i32 [[TMP44]] to double		// CHECK3-NEXT: [[CONV17:%.*]] = sitofp i32 [[TMP44]] to double
// CHECK3-NEXT: store double [[CONV17]], double* [[REF_TMP16]], align 8, !tbaa [[TBAA22]]		// CHECK3-NEXT: store double [[CONV17]], double* [[REF_TMP16]], align 8, !tbaa [[TBAA22]]
// CHECK3-NEXT: call void @_ZNSt7complexIdEC1ERKdS2_(%"class.std::complex.0"* nonnull align 8 dereferenceable(16) [[REF_TMP14]], double* nonnull align 8 dereferenceable(8) [[REF_TMP15]], double* nonnull align 8 dereferenceable(8) [[REF_TMP16]]) #[[ATTR10]]		// CHECK3-NEXT: call void @_ZNSt7complexIdEC1ERKdS2_(%"class.std::complex.0"* nonnull align 8 dereferenceable(16) [[REF_TMP14]], double* nonnull align 8 dereferenceable(8) [[REF_TMP15]], double* nonnull align 8 dereferenceable(8) [[REF_TMP16]]) #[[ATTR12]]
// CHECK3-NEXT: [[CALL:%.]] = call nonnull align 8 dereferenceable(16) %"class.std::complex.0" @_ZNSt7complexIdEpLIdEERS0_RKS_IT_E(%"class.std::complex.0"* nonnull align 8 dereferenceable(16) [[PARTIAL_SUM5]], %"class.std::complex.0"* nonnull align 8 dereferenceable(16) [[REF_TMP14]]) #[[ATTR10]]		// CHECK3-NEXT: [[CALL:%.]] = call nonnull align 8 dereferenceable(16) %"class.std::complex.0" @_ZNSt7complexIdEpLIdEERS0_RKS_IT_E(%"class.std::complex.0"* nonnull align 8 dereferenceable(16) [[PARTIAL_SUM5]], %"class.std::complex.0"* nonnull align 8 dereferenceable(16) [[REF_TMP14]]) #[[ATTR12]]
// CHECK3-NEXT: [[TMP45:%.]] = bitcast double [[REF_TMP16]] to i8*		// CHECK3-NEXT: [[TMP45:%.]] = bitcast double [[REF_TMP16]] to i8*
// CHECK3-NEXT: call void @llvm.lifetime.end.p0i8(i64 8, i8* [[TMP45]]) #[[ATTR5]]		// CHECK3-NEXT: call void @llvm.lifetime.end.p0i8(i64 8, i8* [[TMP45]]) #[[ATTR5]]
// CHECK3-NEXT: [[TMP46:%.]] = bitcast double [[REF_TMP15]] to i8*		// CHECK3-NEXT: [[TMP46:%.]] = bitcast double [[REF_TMP15]] to i8*
// CHECK3-NEXT: call void @llvm.lifetime.end.p0i8(i64 8, i8* [[TMP46]]) #[[ATTR5]]		// CHECK3-NEXT: call void @llvm.lifetime.end.p0i8(i64 8, i8* [[TMP46]]) #[[ATTR5]]
// CHECK3-NEXT: [[TMP47:%.]] = bitcast %"class.std::complex.0" [[REF_TMP14]] to i8*		// CHECK3-NEXT: [[TMP47:%.]] = bitcast %"class.std::complex.0" [[REF_TMP14]] to i8*
// CHECK3-NEXT: call void @llvm.lifetime.end.p0i8(i64 16, i8* [[TMP47]]) #[[ATTR5]]		// CHECK3-NEXT: call void @llvm.lifetime.end.p0i8(i64 16, i8* [[TMP47]]) #[[ATTR5]]
// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]		// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK3: omp.body.continue:		// CHECK3: omp.body.continue:
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// CHECK3-NEXT: [[TMP57:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0		// CHECK3-NEXT: [[TMP57:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0
// CHECK3-NEXT: [[TMP58:%.]] = bitcast %"class.std::complex.0" [[PARTIAL_SUM5]] to i8*		// CHECK3-NEXT: [[TMP58:%.]] = bitcast %"class.std::complex.0" [[PARTIAL_SUM5]] to i8*
// CHECK3-NEXT: store i8* [[TMP58]], i8** [[TMP57]], align 8		// CHECK3-NEXT: store i8* [[TMP58]], i8** [[TMP57]], align 8
// CHECK3-NEXT: [[TMP59:%.]] = bitcast [1 x i8]* [[DOTOMP_REDUCTION_RED_LIST]] to i8*		// CHECK3-NEXT: [[TMP59:%.]] = bitcast [1 x i8]* [[DOTOMP_REDUCTION_RED_LIST]] to i8*
// CHECK3-NEXT: [[TMP60:%.]] = call i32 @__kmpc_nvptx_parallel_reduce_nowait_v2(%struct.ident_t @[[GLOB1]], i32 [[TMP56]], i32 1, i64 8, i8* [[TMP59]], void (i8, i16, i16, i16) @_omp_reduction_shuffle_and_reduce_func5, void (i8, i32) @_omp_reduction_inter_warp_copy_func6)		// CHECK3-NEXT: [[TMP60:%.]] = call i32 @__kmpc_nvptx_parallel_reduce_nowait_v2(%struct.ident_t @[[GLOB1]], i32 [[TMP56]], i32 1, i64 8, i8* [[TMP59]], void (i8, i16, i16, i16) @_omp_reduction_shuffle_and_reduce_func5, void (i8, i32) @_omp_reduction_inter_warp_copy_func6)
// CHECK3-NEXT: [[TMP61:%.*]] = icmp eq i32 [[TMP60]], 1		// CHECK3-NEXT: [[TMP61:%.*]] = icmp eq i32 [[TMP60]], 1
// CHECK3-NEXT: br i1 [[TMP61]], label [[DOTOMP_REDUCTION_THEN:%.]], label [[DOTOMP_REDUCTION_DONE:%.]]		// CHECK3-NEXT: br i1 [[TMP61]], label [[DOTOMP_REDUCTION_THEN:%.]], label [[DOTOMP_REDUCTION_DONE:%.]]
// CHECK3: .omp.reduction.then:		// CHECK3: .omp.reduction.then:
// CHECK3-NEXT: [[CALL21:%.]] = call nonnull align 8 dereferenceable(16) %"class.std::complex.0" @_ZNSt7complexIdEpLIdEERS0_RKS_IT_E(%"class.std::complex.0"* nonnull align 8 dereferenceable(16) [[TMP2]], %"class.std::complex.0"* nonnull align 8 dereferenceable(16) [[PARTIAL_SUM5]]) #[[ATTR10]]		// CHECK3-NEXT: [[CALL21:%.]] = call nonnull align 8 dereferenceable(16) %"class.std::complex.0" @_ZNSt7complexIdEpLIdEERS0_RKS_IT_E(%"class.std::complex.0"* nonnull align 8 dereferenceable(16) [[TMP2]], %"class.std::complex.0"* nonnull align 8 dereferenceable(16) [[PARTIAL_SUM5]]) #[[ATTR12]]
// CHECK3-NEXT: call void @__kmpc_nvptx_end_reduce_nowait(i32 [[TMP56]])		// CHECK3-NEXT: call void @__kmpc_nvptx_end_reduce_nowait(i32 [[TMP56]])
// CHECK3-NEXT: br label [[DOTOMP_REDUCTION_DONE]]		// CHECK3-NEXT: br label [[DOTOMP_REDUCTION_DONE]]
// CHECK3: .omp.reduction.done:		// CHECK3: .omp.reduction.done:
// CHECK3-NEXT: [[TMP62:%.]] = bitcast i32 [[I7]] to i8*		// CHECK3-NEXT: [[TMP62:%.]] = bitcast i32 [[I7]] to i8*
// CHECK3-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP62]]) #[[ATTR5]]		// CHECK3-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP62]]) #[[ATTR5]]
// CHECK3-NEXT: [[TMP63:%.]] = bitcast %"class.std::complex.0" [[PARTIAL_SUM5]] to i8*		// CHECK3-NEXT: [[TMP63:%.]] = bitcast %"class.std::complex.0" [[PARTIAL_SUM5]] to i8*
// CHECK3-NEXT: call void @llvm.lifetime.end.p0i8(i64 16, i8* [[TMP63]]) #[[ATTR5]]		// CHECK3-NEXT: call void @llvm.lifetime.end.p0i8(i64 16, i8* [[TMP63]]) #[[ATTR5]]
// CHECK3-NEXT: [[TMP64:%.]] = bitcast i32 [[DOTOMP_IS_LAST]] to i8*		// CHECK3-NEXT: [[TMP64:%.]] = bitcast i32 [[DOTOMP_IS_LAST]] to i8*
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// CHECK3-SAME: (%"class.std::complex.0"* nonnull align 8 dereferenceable(16) [[THIS:%.]], %"class.std::complex.0" nonnull align 8 dereferenceable(16) [[__C:%.*]]) #[[ATTR4]] comdat align 2 {		// CHECK3-SAME: (%"class.std::complex.0"* nonnull align 8 dereferenceable(16) [[THIS:%.]], %"class.std::complex.0" nonnull align 8 dereferenceable(16) [[__C:%.*]]) #[[ATTR4]] comdat align 2 {
// CHECK3-NEXT: entry:		// CHECK3-NEXT: entry:
// CHECK3-NEXT: [[THIS_ADDR:%.]] = alloca %"class.std::complex.0", align 8		// CHECK3-NEXT: [[THIS_ADDR:%.]] = alloca %"class.std::complex.0", align 8
// CHECK3-NEXT: [[__C_ADDR:%.]] = alloca %"class.std::complex.0", align 8		// CHECK3-NEXT: [[__C_ADDR:%.]] = alloca %"class.std::complex.0", align 8
// CHECK3-NEXT: store %"class.std::complex.0"* [[THIS]], %"class.std::complex.0"** [[THIS_ADDR]], align 8, !tbaa [[TBAA12]]		// CHECK3-NEXT: store %"class.std::complex.0"* [[THIS]], %"class.std::complex.0"** [[THIS_ADDR]], align 8, !tbaa [[TBAA12]]
// CHECK3-NEXT: store %"class.std::complex.0"* [[__C]], %"class.std::complex.0"** [[__C_ADDR]], align 8, !tbaa [[TBAA12]]		// CHECK3-NEXT: store %"class.std::complex.0"* [[__C]], %"class.std::complex.0"** [[__C_ADDR]], align 8, !tbaa [[TBAA12]]
// CHECK3-NEXT: [[THIS1:%.]] = load %"class.std::complex.0", %"class.std::complex.0"** [[THIS_ADDR]], align 8		// CHECK3-NEXT: [[THIS1:%.]] = load %"class.std::complex.0", %"class.std::complex.0"** [[THIS_ADDR]], align 8
// CHECK3-NEXT: [[TMP0:%.]] = load %"class.std::complex.0", %"class.std::complex.0"** [[__C_ADDR]], align 8, !tbaa [[TBAA12]]		// CHECK3-NEXT: [[TMP0:%.]] = load %"class.std::complex.0", %"class.std::complex.0"** [[__C_ADDR]], align 8, !tbaa [[TBAA12]]
// CHECK3-NEXT: [[CALL:%.]] = call double @_ZNKSt7complexIdE4realEv(%"class.std::complex.0" nonnull align 8 dereferenceable(16) [[TMP0]]) #[[ATTR10]]		// CHECK3-NEXT: [[CALL:%.]] = call double @_ZNKSt7complexIdE4realEv(%"class.std::complex.0" nonnull align 8 dereferenceable(16) [[TMP0]]) #[[ATTR12]]
// CHECK3-NEXT: [[__RE_:%.]] = getelementptr inbounds %"class.std::complex.0", %"class.std::complex.0" [[THIS1]], i32 0, i32 0		// CHECK3-NEXT: [[__RE_:%.]] = getelementptr inbounds %"class.std::complex.0", %"class.std::complex.0" [[THIS1]], i32 0, i32 0
// CHECK3-NEXT: [[TMP1:%.]] = load double, double [[__RE_]], align 8, !tbaa [[TBAA24:![0-9]+]]		// CHECK3-NEXT: [[TMP1:%.]] = load double, double [[__RE_]], align 8, !tbaa [[TBAA24:![0-9]+]]
// CHECK3-NEXT: [[ADD:%.*]] = fadd double [[TMP1]], [[CALL]]		// CHECK3-NEXT: [[ADD:%.*]] = fadd double [[TMP1]], [[CALL]]
// CHECK3-NEXT: store double [[ADD]], double* [[__RE_]], align 8, !tbaa [[TBAA24]]		// CHECK3-NEXT: store double [[ADD]], double* [[__RE_]], align 8, !tbaa [[TBAA24]]
// CHECK3-NEXT: [[TMP2:%.]] = load %"class.std::complex.0", %"class.std::complex.0"** [[__C_ADDR]], align 8, !tbaa [[TBAA12]]		// CHECK3-NEXT: [[TMP2:%.]] = load %"class.std::complex.0", %"class.std::complex.0"** [[__C_ADDR]], align 8, !tbaa [[TBAA12]]
// CHECK3-NEXT: [[CALL2:%.]] = call double @_ZNKSt7complexIdE4imagEv(%"class.std::complex.0" nonnull align 8 dereferenceable(16) [[TMP2]]) #[[ATTR10]]		// CHECK3-NEXT: [[CALL2:%.]] = call double @_ZNKSt7complexIdE4imagEv(%"class.std::complex.0" nonnull align 8 dereferenceable(16) [[TMP2]]) #[[ATTR12]]
// CHECK3-NEXT: [[__IM_:%.]] = getelementptr inbounds %"class.std::complex.0", %"class.std::complex.0" [[THIS1]], i32 0, i32 1		// CHECK3-NEXT: [[__IM_:%.]] = getelementptr inbounds %"class.std::complex.0", %"class.std::complex.0" [[THIS1]], i32 0, i32 1
// CHECK3-NEXT: [[TMP3:%.]] = load double, double [[__IM_]], align 8, !tbaa [[TBAA26:![0-9]+]]		// CHECK3-NEXT: [[TMP3:%.]] = load double, double [[__IM_]], align 8, !tbaa [[TBAA26:![0-9]+]]
// CHECK3-NEXT: [[ADD3:%.*]] = fadd double [[TMP3]], [[CALL2]]		// CHECK3-NEXT: [[ADD3:%.*]] = fadd double [[TMP3]], [[CALL2]]
// CHECK3-NEXT: store double [[ADD3]], double* [[__IM_]], align 8, !tbaa [[TBAA26]]		// CHECK3-NEXT: store double [[ADD3]], double* [[__IM_]], align 8, !tbaa [[TBAA26]]
// CHECK3-NEXT: ret %"class.std::complex.0"* [[THIS1]]		// CHECK3-NEXT: ret %"class.std::complex.0"* [[THIS1]]
//		//
//		//
// CHECK3-LABEL: define {{[^@]+}}@_omp_reduction_shuffle_and_reduce_func5		// CHECK3-LABEL: define {{[^@]+}}@_omp_reduction_shuffle_and_reduce_func5
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// CHECK3-NEXT: [[TMP11:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST]], i64 0, i64 0		// CHECK3-NEXT: [[TMP11:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST]], i64 0, i64 0
// CHECK3-NEXT: [[TMP12:%.]] = bitcast i8 [[TMP10]] to %"class.std::complex.0"*		// CHECK3-NEXT: [[TMP12:%.]] = bitcast i8 [[TMP10]] to %"class.std::complex.0"*
// CHECK3-NEXT: [[TMP13:%.]] = getelementptr %"class.std::complex.0", %"class.std::complex.0" [[TMP12]], i64 1		// CHECK3-NEXT: [[TMP13:%.]] = getelementptr %"class.std::complex.0", %"class.std::complex.0" [[TMP12]], i64 1
// CHECK3-NEXT: [[TMP14:%.]] = bitcast %"class.std::complex.0" [[TMP13]] to i8*		// CHECK3-NEXT: [[TMP14:%.]] = bitcast %"class.std::complex.0" [[TMP13]] to i8*
// CHECK3-NEXT: [[TMP15:%.]] = bitcast %"class.std::complex.0" [[TMP12]] to i64*		// CHECK3-NEXT: [[TMP15:%.]] = bitcast %"class.std::complex.0" [[TMP12]] to i64*
// CHECK3-NEXT: [[TMP16:%.]] = bitcast %"class.std::complex.0" [[DOTOMP_REDUCTION_ELEMENT]] to i64*		// CHECK3-NEXT: [[TMP16:%.]] = bitcast %"class.std::complex.0" [[DOTOMP_REDUCTION_ELEMENT]] to i64*
// CHECK3-NEXT: br label [[DOTSHUFFLE_PRE_COND:%.*]]		// CHECK3-NEXT: br label [[DOTSHUFFLE_PRE_COND:%.*]]
// CHECK3: .shuffle.pre_cond:		// CHECK3: .shuffle.pre_cond:
// CHECK3-NEXT: [[TMP17:%.]] = phi i64 [ [[TMP15]], [[ENTRY:%.]] ], [ [[TMP29:%.]], [[DOTSHUFFLE_THEN:%.*]] ]		// CHECK3-NEXT: [[TMP17:%.]] = phi i64 [ [[TMP15]], [[ENTRY:%.]] ], [ [[TMP28:%.]], [[DOTSHUFFLE_THEN:%.*]] ]
// CHECK3-NEXT: [[TMP18:%.]] = phi i64 [ [[TMP16]], [[ENTRY]] ], [ [[TMP30:%.*]], [[DOTSHUFFLE_THEN]] ]		// CHECK3-NEXT: [[TMP18:%.]] = phi i64 [ [[TMP16]], [[ENTRY]] ], [ [[TMP29:%.*]], [[DOTSHUFFLE_THEN]] ]
// CHECK3-NEXT: [[TMP19:%.]] = bitcast i64 [[TMP17]] to i8*		// CHECK3-NEXT: [[TMP19:%.]] = bitcast i64 [[TMP17]] to i8*
// CHECK3-NEXT: [[TMP20:%.]] = ptrtoint i8 [[TMP14]] to i64		// CHECK3-NEXT: [[TMP20:%.]] = ptrtoint i8 [[TMP14]] to i64
// CHECK3-NEXT: [[TMP21:%.]] = ptrtoint i8 [[TMP19]] to i64		// CHECK3-NEXT: [[TMP21:%.]] = ptrtoint i8 [[TMP19]] to i64
// CHECK3-NEXT: [[TMP22:%.*]] = sub i64 [[TMP20]], [[TMP21]]		// CHECK3-NEXT: [[TMP22:%.*]] = sub i64 [[TMP20]], [[TMP21]]
// CHECK3-NEXT: [[TMP23:%.]] = sdiv exact i64 [[TMP22]], ptrtoint (i8 getelementptr (i8, i8* null, i32 1) to i64)		// CHECK3-NEXT: [[TMP23:%.]] = sdiv exact i64 [[TMP22]], ptrtoint (i8 getelementptr (i8, i8* null, i32 1) to i64)
// CHECK3-NEXT: [[TMP24:%.*]] = icmp sgt i64 [[TMP23]], 7		// CHECK3-NEXT: [[TMP24:%.*]] = icmp sgt i64 [[TMP23]], 7
// CHECK3-NEXT: br i1 [[TMP24]], label [[DOTSHUFFLE_THEN]], label [[DOTSHUFFLE_EXIT:%.*]]		// CHECK3-NEXT: br i1 [[TMP24]], label [[DOTSHUFFLE_THEN]], label [[DOTSHUFFLE_EXIT:%.*]]
// CHECK3: .shuffle.then:		// CHECK3: .shuffle.then:
// CHECK3-NEXT: [[TMP25:%.]] = load i64, i64 [[TMP17]], align 8		// CHECK3-NEXT: [[TMP25:%.]] = load i64, i64 [[TMP17]], align 8
// CHECK3-NEXT: [[TMP26:%.*]] = call i32 @__kmpc_get_warp_size()		// CHECK3-NEXT: [[NVPTX_WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size()
// CHECK3-NEXT: [[TMP27:%.*]] = trunc i32 [[TMP26]] to i16		// CHECK3-NEXT: [[TMP26:%.*]] = trunc i32 [[NVPTX_WARP_SIZE]] to i16
// CHECK3-NEXT: [[TMP28:%.*]] = call i64 @__kmpc_shuffle_int64(i64 [[TMP25]], i16 [[TMP7]], i16 [[TMP27]])		// CHECK3-NEXT: [[TMP27:%.*]] = call i64 @__kmpc_shuffle_int64(i64 [[TMP25]], i16 [[TMP7]], i16 [[TMP26]])
// CHECK3-NEXT: store i64 [[TMP28]], i64* [[TMP18]], align 8		// CHECK3-NEXT: store i64 [[TMP27]], i64* [[TMP18]], align 8
// CHECK3-NEXT: [[TMP29]] = getelementptr i64, i64* [[TMP17]], i64 1		// CHECK3-NEXT: [[TMP28]] = getelementptr i64, i64* [[TMP17]], i64 1
// CHECK3-NEXT: [[TMP30]] = getelementptr i64, i64* [[TMP18]], i64 1		// CHECK3-NEXT: [[TMP29]] = getelementptr i64, i64* [[TMP18]], i64 1
// CHECK3-NEXT: br label [[DOTSHUFFLE_PRE_COND]]		// CHECK3-NEXT: br label [[DOTSHUFFLE_PRE_COND]]
// CHECK3: .shuffle.exit:		// CHECK3: .shuffle.exit:
// CHECK3-NEXT: [[TMP31:%.]] = bitcast %"class.std::complex.0" [[DOTOMP_REDUCTION_ELEMENT]] to i8*		// CHECK3-NEXT: [[TMP30:%.]] = bitcast %"class.std::complex.0" [[DOTOMP_REDUCTION_ELEMENT]] to i8*
// CHECK3-NEXT: store i8* [[TMP31]], i8** [[TMP11]], align 8, !tbaa [[TBAA12]]		// CHECK3-NEXT: store i8* [[TMP30]], i8** [[TMP11]], align 8, !tbaa [[TBAA12]]
// CHECK3-NEXT: [[TMP32:%.*]] = icmp eq i16 [[TMP8]], 0		// CHECK3-NEXT: [[TMP31:%.*]] = icmp eq i16 [[TMP8]], 0
// CHECK3-NEXT: [[TMP33:%.*]] = icmp eq i16 [[TMP8]], 1		// CHECK3-NEXT: [[TMP32:%.*]] = icmp eq i16 [[TMP8]], 1
// CHECK3-NEXT: [[TMP34:%.*]] = icmp ult i16 [[TMP6]], [[TMP7]]		// CHECK3-NEXT: [[TMP33:%.*]] = icmp ult i16 [[TMP6]], [[TMP7]]
// CHECK3-NEXT: [[TMP35:%.*]] = and i1 [[TMP33]], [[TMP34]]		// CHECK3-NEXT: [[TMP34:%.*]] = and i1 [[TMP32]], [[TMP33]]
// CHECK3-NEXT: [[TMP36:%.*]] = icmp eq i16 [[TMP8]], 2		// CHECK3-NEXT: [[TMP35:%.*]] = icmp eq i16 [[TMP8]], 2
// CHECK3-NEXT: [[TMP37:%.*]] = and i16 [[TMP6]], 1		// CHECK3-NEXT: [[TMP36:%.*]] = and i16 [[TMP6]], 1
// CHECK3-NEXT: [[TMP38:%.*]] = icmp eq i16 [[TMP37]], 0		// CHECK3-NEXT: [[TMP37:%.*]] = icmp eq i16 [[TMP36]], 0
// CHECK3-NEXT: [[TMP39:%.*]] = and i1 [[TMP36]], [[TMP38]]		// CHECK3-NEXT: [[TMP38:%.*]] = and i1 [[TMP35]], [[TMP37]]
// CHECK3-NEXT: [[TMP40:%.*]] = icmp sgt i16 [[TMP7]], 0		// CHECK3-NEXT: [[TMP39:%.*]] = icmp sgt i16 [[TMP7]], 0
// CHECK3-NEXT: [[TMP41:%.*]] = and i1 [[TMP39]], [[TMP40]]		// CHECK3-NEXT: [[TMP40:%.*]] = and i1 [[TMP38]], [[TMP39]]
// CHECK3-NEXT: [[TMP42:%.*]] = or i1 [[TMP32]], [[TMP35]]		// CHECK3-NEXT: [[TMP41:%.*]] = or i1 [[TMP31]], [[TMP34]]
// CHECK3-NEXT: [[TMP43:%.*]] = or i1 [[TMP42]], [[TMP41]]		// CHECK3-NEXT: [[TMP42:%.*]] = or i1 [[TMP41]], [[TMP40]]
// CHECK3-NEXT: br i1 [[TMP43]], label [[THEN:%.]], label [[ELSE:%.]]		// CHECK3-NEXT: br i1 [[TMP42]], label [[THEN:%.]], label [[ELSE:%.]]
// CHECK3: then:		// CHECK3: then:
// CHECK3-NEXT: [[TMP44:%.]] = bitcast [1 x i8]* [[TMP5]] to i8*		// CHECK3-NEXT: [[TMP43:%.]] = bitcast [1 x i8]* [[TMP5]] to i8*
// CHECK3-NEXT: [[TMP45:%.]] = bitcast [1 x i8]* [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST]] to i8*		// CHECK3-NEXT: [[TMP44:%.]] = bitcast [1 x i8]* [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST]] to i8*
// CHECK3-NEXT: call void @"_omp$reduction$reduction_func4"(i8* [[TMP44]], i8* [[TMP45]]) #[[ATTR5]]		// CHECK3-NEXT: call void @"_omp$reduction$reduction_func4"(i8* [[TMP43]], i8* [[TMP44]]) #[[ATTR5]]
// CHECK3-NEXT: br label [[IFCONT:%.*]]		// CHECK3-NEXT: br label [[IFCONT:%.*]]
// CHECK3: else:		// CHECK3: else:
// CHECK3-NEXT: br label [[IFCONT]]		// CHECK3-NEXT: br label [[IFCONT]]
// CHECK3: ifcont:		// CHECK3: ifcont:
// CHECK3-NEXT: [[TMP46:%.*]] = icmp eq i16 [[TMP8]], 1		// CHECK3-NEXT: [[TMP45:%.*]] = icmp eq i16 [[TMP8]], 1
// CHECK3-NEXT: [[TMP47:%.*]] = icmp uge i16 [[TMP6]], [[TMP7]]		// CHECK3-NEXT: [[TMP46:%.*]] = icmp uge i16 [[TMP6]], [[TMP7]]
// CHECK3-NEXT: [[TMP48:%.*]] = and i1 [[TMP46]], [[TMP47]]		// CHECK3-NEXT: [[TMP47:%.*]] = and i1 [[TMP45]], [[TMP46]]
// CHECK3-NEXT: br i1 [[TMP48]], label [[THEN4:%.]], label [[ELSE5:%.]]		// CHECK3-NEXT: br i1 [[TMP47]], label [[THEN4:%.]], label [[ELSE5:%.]]
// CHECK3: then4:		// CHECK3: then4:
// CHECK3-NEXT: [[TMP49:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST]], i64 0, i64 0		// CHECK3-NEXT: [[TMP48:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST]], i64 0, i64 0
// CHECK3-NEXT: [[TMP50:%.]] = load i8, i8** [[TMP49]], align 8		// CHECK3-NEXT: [[TMP49:%.]] = load i8, i8** [[TMP48]], align 8
// CHECK3-NEXT: [[TMP51:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[TMP5]], i64 0, i64 0		// CHECK3-NEXT: [[TMP50:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[TMP5]], i64 0, i64 0
// CHECK3-NEXT: [[TMP52:%.]] = load i8, i8** [[TMP51]], align 8		// CHECK3-NEXT: [[TMP51:%.]] = load i8, i8** [[TMP50]], align 8
// CHECK3-NEXT: [[TMP53:%.]] = bitcast i8 [[TMP50]] to %"class.std::complex.0"*		// CHECK3-NEXT: [[TMP52:%.]] = bitcast i8 [[TMP49]] to %"class.std::complex.0"*
// CHECK3-NEXT: [[TMP54:%.]] = bitcast i8 [[TMP52]] to %"class.std::complex.0"*		// CHECK3-NEXT: [[TMP53:%.]] = bitcast i8 [[TMP51]] to %"class.std::complex.0"*
// CHECK3-NEXT: [[TMP55:%.]] = bitcast %"class.std::complex.0" [[TMP54]] to i8*		// CHECK3-NEXT: [[TMP54:%.]] = bitcast %"class.std::complex.0" [[TMP53]] to i8*
// CHECK3-NEXT: [[TMP56:%.]] = bitcast %"class.std::complex.0" [[TMP53]] to i8*		// CHECK3-NEXT: [[TMP55:%.]] = bitcast %"class.std::complex.0" [[TMP52]] to i8*
// CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP55]], i8* align 8 [[TMP56]], i64 16, i1 false), !tbaa.struct !27		// CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP54]], i8* align 8 [[TMP55]], i64 16, i1 false), !tbaa.struct !27
// CHECK3-NEXT: br label [[IFCONT6:%.*]]		// CHECK3-NEXT: br label [[IFCONT6:%.*]]
// CHECK3: else5:		// CHECK3: else5:
// CHECK3-NEXT: br label [[IFCONT6]]		// CHECK3-NEXT: br label [[IFCONT6]]
// CHECK3: ifcont6:		// CHECK3: ifcont6:
// CHECK3-NEXT: ret void		// CHECK3-NEXT: ret void
//		//
//		//
// CHECK3-LABEL: define {{[^@]+}}@_omp_reduction_inter_warp_copy_func6		// CHECK3-LABEL: define {{[^@]+}}@_omp_reduction_inter_warp_copy_func6
// CHECK3-SAME: (i8* [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR6]] {		// CHECK3-SAME: (i8* [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR6]] {
// CHECK3-NEXT: entry:		// CHECK3-NEXT: entry:
// CHECK3-NEXT: [[DOTADDR:%.]] = alloca i8, align 8		// CHECK3-NEXT: [[DOTADDR:%.]] = alloca i8, align 8
// CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4		// CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
// CHECK3-NEXT: [[DOTCNT_ADDR:%.*]] = alloca i32, align 4		// CHECK3-NEXT: [[DOTCNT_ADDR:%.*]] = alloca i32, align 4
// CHECK3-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB1]])		// CHECK3-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB1]])
// CHECK3-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8, !tbaa [[TBAA12]]		// CHECK3-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8, !tbaa [[TBAA12]]
// CHECK3-NEXT: store i32 [[TMP1]], i32* [[DOTADDR1]], align 4, !tbaa [[TBAA8]]		// CHECK3-NEXT: store i32 [[TMP1]], i32* [[DOTADDR1]], align 4, !tbaa [[TBAA8]]
// CHECK3-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block()		// CHECK3-NEXT: [[NVPTX_TID:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block()
// CHECK3-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block()		// CHECK3-NEXT: [[NVPTX_TID2:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block()
// CHECK3-NEXT: [[NVPTX_LANE_ID:%.*]] = and i32 [[TMP4]], 31		// CHECK3-NEXT: [[NVPTX_LANE_ID:%.*]] = and i32 [[NVPTX_TID2]], 31
// CHECK3-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block()		// CHECK3-NEXT: [[NVPTX_TID3:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block()
// CHECK3-NEXT: [[NVPTX_WARP_ID:%.*]] = ashr i32 [[TMP5]], 5		// CHECK3-NEXT: [[NVPTX_WARP_ID:%.*]] = ashr i32 [[NVPTX_TID3]], 5
// CHECK3-NEXT: [[TMP6:%.]] = load i8, i8** [[DOTADDR]], align 8		// CHECK3-NEXT: [[TMP3:%.]] = load i8, i8** [[DOTADDR]], align 8
// CHECK3-NEXT: [[TMP7:%.]] = bitcast i8 [[TMP6]] to [1 x i8]		// CHECK3-NEXT: [[TMP4:%.]] = bitcast i8 [[TMP3]] to [1 x i8]
// CHECK3-NEXT: store i32 0, i32* [[DOTCNT_ADDR]], align 4, !tbaa [[TBAA8]]		// CHECK3-NEXT: store i32 0, i32* [[DOTCNT_ADDR]], align 4, !tbaa [[TBAA8]]
// CHECK3-NEXT: br label [[PRECOND:%.*]]		// CHECK3-NEXT: br label [[PRECOND:%.*]]
// CHECK3: precond:		// CHECK3: precond:
// CHECK3-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTCNT_ADDR]], align 4, !tbaa [[TBAA8]]		// CHECK3-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTCNT_ADDR]], align 4, !tbaa [[TBAA8]]
// CHECK3-NEXT: [[TMP9:%.*]] = icmp ult i32 [[TMP8]], 4		// CHECK3-NEXT: [[TMP6:%.*]] = icmp ult i32 [[TMP5]], 4
// CHECK3-NEXT: br i1 [[TMP9]], label [[BODY:%.]], label [[EXIT:%.]]		// CHECK3-NEXT: br i1 [[TMP6]], label [[BODY:%.]], label [[EXIT:%.]]
// CHECK3: body:		// CHECK3: body:
// CHECK3-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB4]], i32 [[TMP2]])		// CHECK3-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB4]], i32 [[TMP2]])
// CHECK3-NEXT: [[WARP_MASTER:%.*]] = icmp eq i32 [[NVPTX_LANE_ID]], 0		// CHECK3-NEXT: [[WARP_MASTER:%.*]] = icmp eq i32 [[NVPTX_LANE_ID]], 0
// CHECK3-NEXT: br i1 [[WARP_MASTER]], label [[THEN:%.]], label [[ELSE:%.]]		// CHECK3-NEXT: br i1 [[WARP_MASTER]], label [[THEN:%.]], label [[ELSE:%.]]
// CHECK3: then:		// CHECK3: then:
// CHECK3-NEXT: [[TMP10:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[TMP7]], i64 0, i64 0		// CHECK3-NEXT: [[TMP7:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[TMP4]], i64 0, i64 0
// CHECK3-NEXT: [[TMP11:%.]] = load i8, i8** [[TMP10]], align 8, !tbaa [[TBAA12]]		// CHECK3-NEXT: [[TMP8:%.]] = load i8, i8** [[TMP7]], align 8, !tbaa [[TBAA12]]
// CHECK3-NEXT: [[TMP12:%.]] = bitcast i8 [[TMP11]] to i32*		// CHECK3-NEXT: [[TMP9:%.]] = bitcast i8 [[TMP8]] to i32*
// CHECK3-NEXT: [[TMP13:%.]] = getelementptr i32, i32 [[TMP12]], i32 [[TMP8]]		// CHECK3-NEXT: [[TMP10:%.]] = getelementptr i32, i32 [[TMP9]], i32 [[TMP5]]
// CHECK3-NEXT: [[TMP14:%.]] = getelementptr inbounds [32 x i32], [32 x i32] addrspace(3) @__openmp_nvptx_data_transfer_temporary_storage, i64 0, i32 [[NVPTX_WARP_ID]]		// CHECK3-NEXT: [[TMP11:%.]] = getelementptr inbounds [32 x i32], [32 x i32] addrspace(3) @__openmp_nvptx_data_transfer_temporary_storage, i64 0, i32 [[NVPTX_WARP_ID]]
// CHECK3-NEXT: [[TMP15:%.]] = load i32, i32 [[TMP13]], align 4		// CHECK3-NEXT: [[TMP12:%.]] = load i32, i32 [[TMP10]], align 4
// CHECK3-NEXT: store volatile i32 [[TMP15]], i32 addrspace(3)* [[TMP14]], align 4		// CHECK3-NEXT: store volatile i32 [[TMP12]], i32 addrspace(3)* [[TMP11]], align 4
// CHECK3-NEXT: br label [[IFCONT:%.*]]		// CHECK3-NEXT: br label [[IFCONT:%.*]]
// CHECK3: else:		// CHECK3: else:
// CHECK3-NEXT: br label [[IFCONT]]		// CHECK3-NEXT: br label [[IFCONT]]
// CHECK3: ifcont:		// CHECK3: ifcont:
// CHECK3-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB4]], i32 [[TMP2]])		// CHECK3-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB4]], i32 [[TMP2]])
// CHECK3-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTADDR1]], align 4, !tbaa [[TBAA8]]		// CHECK3-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTADDR1]], align 4, !tbaa [[TBAA8]]
// CHECK3-NEXT: [[IS_ACTIVE_THREAD:%.*]] = icmp ult i32 [[TMP3]], [[TMP16]]		// CHECK3-NEXT: [[IS_ACTIVE_THREAD:%.*]] = icmp ult i32 [[NVPTX_TID]], [[TMP13]]
// CHECK3-NEXT: br i1 [[IS_ACTIVE_THREAD]], label [[THEN2:%.]], label [[ELSE3:%.]]		// CHECK3-NEXT: br i1 [[IS_ACTIVE_THREAD]], label [[THEN4:%.]], label [[ELSE5:%.]]
// CHECK3: then2:		// CHECK3: then2:
// CHECK3-NEXT: [[TMP17:%.]] = getelementptr inbounds [32 x i32], [32 x i32] addrspace(3) @__openmp_nvptx_data_transfer_temporary_storage, i64 0, i32 [[TMP3]]		// CHECK3-NEXT: [[TMP14:%.]] = getelementptr inbounds [32 x i32], [32 x i32] addrspace(3) @__openmp_nvptx_data_transfer_temporary_storage, i64 0, i32 [[NVPTX_TID]]
// CHECK3-NEXT: [[TMP18:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[TMP7]], i64 0, i64 0		// CHECK3-NEXT: [[TMP15:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[TMP4]], i64 0, i64 0
// CHECK3-NEXT: [[TMP19:%.]] = load i8, i8** [[TMP18]], align 8, !tbaa [[TBAA12]]		// CHECK3-NEXT: [[TMP16:%.]] = load i8, i8** [[TMP15]], align 8, !tbaa [[TBAA12]]
// CHECK3-NEXT: [[TMP20:%.]] = bitcast i8 [[TMP19]] to i32*		// CHECK3-NEXT: [[TMP17:%.]] = bitcast i8 [[TMP16]] to i32*
// CHECK3-NEXT: [[TMP21:%.]] = getelementptr i32, i32 [[TMP20]], i32 [[TMP8]]		// CHECK3-NEXT: [[TMP18:%.]] = getelementptr i32, i32 [[TMP17]], i32 [[TMP5]]
// CHECK3-NEXT: [[TMP22:%.]] = load volatile i32, i32 addrspace(3) [[TMP17]], align 4, !tbaa [[TBAA8]]		// CHECK3-NEXT: [[TMP19:%.]] = load volatile i32, i32 addrspace(3) [[TMP14]], align 4, !tbaa [[TBAA8]]
// CHECK3-NEXT: store i32 [[TMP22]], i32* [[TMP21]], align 4, !tbaa [[TBAA8]]		// CHECK3-NEXT: store i32 [[TMP19]], i32* [[TMP18]], align 4, !tbaa [[TBAA8]]
// CHECK3-NEXT: br label [[IFCONT4:%.*]]		// CHECK3-NEXT: br label [[IFCONT6:%.*]]
// CHECK3: else3:		// CHECK3: else3:
// CHECK3-NEXT: br label [[IFCONT4]]		// CHECK3-NEXT: br label [[IFCONT6]]
// CHECK3: ifcont4:		// CHECK3: ifcont4:
// CHECK3-NEXT: [[TMP23:%.*]] = add nsw i32 [[TMP8]], 1		// CHECK3-NEXT: [[TMP20:%.*]] = add nsw i32 [[TMP5]], 1
// CHECK3-NEXT: store i32 [[TMP23]], i32* [[DOTCNT_ADDR]], align 4, !tbaa [[TBAA8]]		// CHECK3-NEXT: store i32 [[TMP20]], i32* [[DOTCNT_ADDR]], align 4, !tbaa [[TBAA8]]
// CHECK3-NEXT: br label [[PRECOND]]		// CHECK3-NEXT: br label [[PRECOND]]
// CHECK3: exit:		// CHECK3: exit:
// CHECK3-NEXT: ret void		// CHECK3-NEXT: ret void
//		//
//		//
// CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__3_wrapper		// CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__3_wrapper
// CHECK3-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR6]] {		// CHECK3-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR6]] {
// CHECK3-NEXT: entry:		// CHECK3-NEXT: entry:
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clang/test/OpenMP/nvptx_target_printf_codegen.c

	Show First 20 Lines • Show All 42 Lines • ▼ Show 20 Lines
	//			//
	//			//
	//			//
	// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_CheckSimple_l13			// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_CheckSimple_l13
	// CHECK-64-SAME: () #[[ATTR0:[0-9]+]] {			// CHECK-64-SAME: () #[[ATTR0:[0-9]+]] {
	// CHECK-64-NEXT: entry:			// CHECK-64-NEXT: entry:
	// CHECK-64-NEXT: [[FMT:%.]] = alloca i8, align 8			// CHECK-64-NEXT: [[FMT:%.]] = alloca i8, align 8
	// CHECK-64-NEXT: [[TMP:%.]] = alloca [[PRINTF_ARGS:%.]], align 8			// CHECK-64-NEXT: [[TMP:%.]] = alloca [[PRINTF_ARGS:%.]], align 8
	// CHECK-64-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1:[0-9]+]], i8 1, i1 true, i1 true)			// CHECK-64-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_CheckSimple_l13_kernel_info, i1 true)
	// CHECK-64-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1			// CHECK-64-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
	// CHECK-64-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]			// CHECK-64-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
	// CHECK-64: user_code.entry:			// CHECK-64: user_code.entry:
	// CHECK-64-NEXT: store i8* getelementptr inbounds ([11 x i8], [11 x i8]* @.str, i64 0, i64 0), i8** [[FMT]], align 8			// CHECK-64-NEXT: store i8* getelementptr inbounds ([11 x i8], [11 x i8]* @.str, i64 0, i64 0), i8** [[FMT]], align 8
	// CHECK-64-NEXT: [[TMP1:%.]] = load i8, i8** [[FMT]], align 8			// CHECK-64-NEXT: [[TMP1:%.]] = load i8, i8** [[FMT]], align 8
	// CHECK-64-NEXT: [[TMP2:%.]] = getelementptr inbounds [[PRINTF_ARGS]], %printf_args [[TMP]], i32 0, i32 0			// CHECK-64-NEXT: [[TMP2:%.]] = getelementptr inbounds [[PRINTF_ARGS]], %printf_args [[TMP]], i32 0, i32 0
	// CHECK-64-NEXT: store i32 1, i32* [[TMP2]], align 4			// CHECK-64-NEXT: store i32 1, i32* [[TMP2]], align 4
	// CHECK-64-NEXT: [[TMP3:%.]] = getelementptr inbounds [[PRINTF_ARGS]], %printf_args [[TMP]], i32 0, i32 1			// CHECK-64-NEXT: [[TMP3:%.]] = getelementptr inbounds [[PRINTF_ARGS]], %printf_args [[TMP]], i32 0, i32 1
	// CHECK-64-NEXT: store i64 2, i64* [[TMP3]], align 8			// CHECK-64-NEXT: store i64 2, i64* [[TMP3]], align 8
	// CHECK-64-NEXT: [[TMP4:%.]] = getelementptr inbounds [[PRINTF_ARGS]], %printf_args [[TMP]], i32 0, i32 2			// CHECK-64-NEXT: [[TMP4:%.]] = getelementptr inbounds [[PRINTF_ARGS]], %printf_args [[TMP]], i32 0, i32 2
	// CHECK-64-NEXT: store double 3.000000e+00, double* [[TMP4]], align 8			// CHECK-64-NEXT: store double 3.000000e+00, double* [[TMP4]], align 8
	// CHECK-64-NEXT: [[TMP5:%.]] = bitcast %printf_args [[TMP]] to i8*			// CHECK-64-NEXT: [[TMP5:%.]] = bitcast %printf_args [[TMP]] to i8*
	// CHECK-64-NEXT: [[TMP6:%.]] = call i32 @__llvm_omp_vprintf(i8 [[TMP1]], i8* [[TMP5]], i32 24)			// CHECK-64-NEXT: [[TMP6:%.]] = call i32 @__llvm_omp_vprintf(i8 [[TMP1]], i8* [[TMP5]], i32 24)
	// CHECK-64-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true)			// CHECK-64-NEXT: call void @__kmpc_target_deinit(i1 true)
	// CHECK-64-NEXT: ret void			// CHECK-64-NEXT: ret void
	// CHECK-64: worker.exit:			// CHECK-64: worker.exit:
	// CHECK-64-NEXT: ret void			// CHECK-64-NEXT: ret void
	//			//
	//			//
	// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_CheckNoArgs_l25			// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_CheckNoArgs_l25
	// CHECK-64-SAME: () #[[ATTR0]] {			// CHECK-64-SAME: () #[[ATTR0]] {
	// CHECK-64-NEXT: entry:			// CHECK-64-NEXT: entry:
	// CHECK-64-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 1, i1 true, i1 true)			// CHECK-64-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_CheckNoArgs_l25_kernel_info, i1 true)
	// CHECK-64-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1			// CHECK-64-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
	// CHECK-64-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]			// CHECK-64-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
	// CHECK-64: user_code.entry:			// CHECK-64: user_code.entry:
	// CHECK-64-NEXT: [[TMP1:%.]] = call i32 @__llvm_omp_vprintf(i8 getelementptr inbounds ([14 x i8], [14 x i8]* @.str1, i64 0, i64 0), i8* null, i32 0)			// CHECK-64-NEXT: [[TMP1:%.]] = call i32 @__llvm_omp_vprintf(i8 getelementptr inbounds ([14 x i8], [14 x i8]* @.str1, i64 0, i64 0), i8* null, i32 0)
	// CHECK-64-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true)			// CHECK-64-NEXT: call void @__kmpc_target_deinit(i1 true)
	// CHECK-64-NEXT: ret void			// CHECK-64-NEXT: ret void
	// CHECK-64: worker.exit:			// CHECK-64: worker.exit:
	// CHECK-64-NEXT: ret void			// CHECK-64-NEXT: ret void
	//			//
	//			//
	// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_CheckAllocaIsInEntryBlock_l36			// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_CheckAllocaIsInEntryBlock_l36
	// CHECK-64-SAME: (i64 [[FOO:%.*]]) #[[ATTR0]] {			// CHECK-64-SAME: (i64 [[FOO:%.*]]) #[[ATTR0]] {
	// CHECK-64-NEXT: entry:			// CHECK-64-NEXT: entry:
	// CHECK-64-NEXT: [[FOO_ADDR:%.*]] = alloca i64, align 8			// CHECK-64-NEXT: [[FOO_ADDR:%.*]] = alloca i64, align 8
	// CHECK-64-NEXT: [[TMP:%.]] = alloca [[PRINTF_ARGS_0:%.]], align 8			// CHECK-64-NEXT: [[TMP:%.]] = alloca [[PRINTF_ARGS_0:%.]], align 8
	// CHECK-64-NEXT: store i64 [[FOO]], i64* [[FOO_ADDR]], align 8			// CHECK-64-NEXT: store i64 [[FOO]], i64* [[FOO_ADDR]], align 8
	// CHECK-64-NEXT: [[CONV:%.]] = bitcast i64 [[FOO_ADDR]] to i32*			// CHECK-64-NEXT: [[CONV:%.]] = bitcast i64 [[FOO_ADDR]] to i32*
	// CHECK-64-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 1, i1 true, i1 true)			// CHECK-64-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_CheckAllocaIsInEntryBlock_l36_kernel_info, i1 true)
	// CHECK-64-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1			// CHECK-64-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
	// CHECK-64-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]			// CHECK-64-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
	// CHECK-64: user_code.entry:			// CHECK-64: user_code.entry:
	// CHECK-64-NEXT: [[TMP1:%.]] = load i32, i32 [[CONV]], align 4			// CHECK-64-NEXT: [[TMP1:%.]] = load i32, i32 [[CONV]], align 4
	// CHECK-64-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0			// CHECK-64-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0
	// CHECK-64-NEXT: br i1 [[TOBOOL]], label [[IF_THEN:%.]], label [[IF_END:%.]]			// CHECK-64-NEXT: br i1 [[TOBOOL]], label [[IF_THEN:%.]], label [[IF_END:%.]]
	// CHECK-64: if.then:			// CHECK-64: if.then:
	// CHECK-64-NEXT: [[TMP2:%.]] = getelementptr inbounds [[PRINTF_ARGS_0]], %printf_args.0 [[TMP]], i32 0, i32 0			// CHECK-64-NEXT: [[TMP2:%.]] = getelementptr inbounds [[PRINTF_ARGS_0]], %printf_args.0 [[TMP]], i32 0, i32 0
	// CHECK-64-NEXT: store i32 42, i32* [[TMP2]], align 4			// CHECK-64-NEXT: store i32 42, i32* [[TMP2]], align 4
	// CHECK-64-NEXT: [[TMP3:%.]] = bitcast %printf_args.0 [[TMP]] to i8*			// CHECK-64-NEXT: [[TMP3:%.]] = bitcast %printf_args.0 [[TMP]] to i8*
	// CHECK-64-NEXT: [[TMP4:%.]] = call i32 @__llvm_omp_vprintf(i8 getelementptr inbounds ([3 x i8], [3 x i8]* @.str2, i64 0, i64 0), i8* [[TMP3]], i32 4)			// CHECK-64-NEXT: [[TMP4:%.]] = call i32 @__llvm_omp_vprintf(i8 getelementptr inbounds ([3 x i8], [3 x i8]* @.str2, i64 0, i64 0), i8* [[TMP3]], i32 4)
	// CHECK-64-NEXT: br label [[IF_END]]			// CHECK-64-NEXT: br label [[IF_END]]
	// CHECK-64: worker.exit:			// CHECK-64: worker.exit:
	// CHECK-64-NEXT: ret void			// CHECK-64-NEXT: ret void
	// CHECK-64: if.end:			// CHECK-64: if.end:
	// CHECK-64-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true)			// CHECK-64-NEXT: call void @__kmpc_target_deinit(i1 true)
	// CHECK-64-NEXT: ret void			// CHECK-64-NEXT: ret void
	//			//
	//			//
	//			//
	//			//
	//			//
	// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_CheckSimple_l13			// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_CheckSimple_l13
	// CHECK-32-SAME: () #[[ATTR0:[0-9]+]] {			// CHECK-32-SAME: () #[[ATTR0:[0-9]+]] {
	// CHECK-32-NEXT: entry:			// CHECK-32-NEXT: entry:
	// CHECK-32-NEXT: [[FMT:%.]] = alloca i8, align 4			// CHECK-32-NEXT: [[FMT:%.]] = alloca i8, align 4
	// CHECK-32-NEXT: [[TMP:%.]] = alloca [[PRINTF_ARGS:%.]], align 8			// CHECK-32-NEXT: [[TMP:%.]] = alloca [[PRINTF_ARGS:%.]], align 8
	// CHECK-32-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1:[0-9]+]], i8 1, i1 true, i1 true)			// CHECK-32-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_CheckSimple_l13_kernel_info, i1 true)
	// CHECK-32-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1			// CHECK-32-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
	// CHECK-32-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]			// CHECK-32-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
	// CHECK-32: user_code.entry:			// CHECK-32: user_code.entry:
	// CHECK-32-NEXT: store i8* getelementptr inbounds ([11 x i8], [11 x i8]* @.str, i32 0, i32 0), i8** [[FMT]], align 4			// CHECK-32-NEXT: store i8* getelementptr inbounds ([11 x i8], [11 x i8]* @.str, i32 0, i32 0), i8** [[FMT]], align 4
	// CHECK-32-NEXT: [[TMP1:%.]] = load i8, i8** [[FMT]], align 4			// CHECK-32-NEXT: [[TMP1:%.]] = load i8, i8** [[FMT]], align 4
	// CHECK-32-NEXT: [[TMP2:%.]] = getelementptr inbounds [[PRINTF_ARGS]], %printf_args [[TMP]], i32 0, i32 0			// CHECK-32-NEXT: [[TMP2:%.]] = getelementptr inbounds [[PRINTF_ARGS]], %printf_args [[TMP]], i32 0, i32 0
	// CHECK-32-NEXT: store i32 1, i32* [[TMP2]], align 4			// CHECK-32-NEXT: store i32 1, i32* [[TMP2]], align 4
	// CHECK-32-NEXT: [[TMP3:%.]] = getelementptr inbounds [[PRINTF_ARGS]], %printf_args [[TMP]], i32 0, i32 1			// CHECK-32-NEXT: [[TMP3:%.]] = getelementptr inbounds [[PRINTF_ARGS]], %printf_args [[TMP]], i32 0, i32 1
	// CHECK-32-NEXT: store i64 2, i64* [[TMP3]], align 8			// CHECK-32-NEXT: store i64 2, i64* [[TMP3]], align 8
	// CHECK-32-NEXT: [[TMP4:%.]] = getelementptr inbounds [[PRINTF_ARGS]], %printf_args [[TMP]], i32 0, i32 2			// CHECK-32-NEXT: [[TMP4:%.]] = getelementptr inbounds [[PRINTF_ARGS]], %printf_args [[TMP]], i32 0, i32 2
	// CHECK-32-NEXT: store double 3.000000e+00, double* [[TMP4]], align 8			// CHECK-32-NEXT: store double 3.000000e+00, double* [[TMP4]], align 8
	// CHECK-32-NEXT: [[TMP5:%.]] = bitcast %printf_args [[TMP]] to i8*			// CHECK-32-NEXT: [[TMP5:%.]] = bitcast %printf_args [[TMP]] to i8*
	// CHECK-32-NEXT: [[TMP6:%.]] = call i32 @__llvm_omp_vprintf(i8 [[TMP1]], i8* [[TMP5]], i32 24)			// CHECK-32-NEXT: [[TMP6:%.]] = call i32 @__llvm_omp_vprintf(i8 [[TMP1]], i8* [[TMP5]], i32 24)
	// CHECK-32-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true)			// CHECK-32-NEXT: call void @__kmpc_target_deinit(i1 true)
	// CHECK-32-NEXT: ret void			// CHECK-32-NEXT: ret void
	// CHECK-32: worker.exit:			// CHECK-32: worker.exit:
	// CHECK-32-NEXT: ret void			// CHECK-32-NEXT: ret void
	//			//
	//			//
	// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_CheckNoArgs_l25			// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_CheckNoArgs_l25
	// CHECK-32-SAME: () #[[ATTR0]] {			// CHECK-32-SAME: () #[[ATTR0]] {
	// CHECK-32-NEXT: entry:			// CHECK-32-NEXT: entry:
	// CHECK-32-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 1, i1 true, i1 true)			// CHECK-32-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_CheckNoArgs_l25_kernel_info, i1 true)
	// CHECK-32-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1			// CHECK-32-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
	// CHECK-32-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]			// CHECK-32-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
	// CHECK-32: user_code.entry:			// CHECK-32: user_code.entry:
	// CHECK-32-NEXT: [[TMP1:%.]] = call i32 @__llvm_omp_vprintf(i8 getelementptr inbounds ([14 x i8], [14 x i8]* @.str1, i32 0, i32 0), i8* null, i32 0)			// CHECK-32-NEXT: [[TMP1:%.]] = call i32 @__llvm_omp_vprintf(i8 getelementptr inbounds ([14 x i8], [14 x i8]* @.str1, i32 0, i32 0), i8* null, i32 0)
	// CHECK-32-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true)			// CHECK-32-NEXT: call void @__kmpc_target_deinit(i1 true)
	// CHECK-32-NEXT: ret void			// CHECK-32-NEXT: ret void
	// CHECK-32: worker.exit:			// CHECK-32: worker.exit:
	// CHECK-32-NEXT: ret void			// CHECK-32-NEXT: ret void
	//			//
	//			//
	// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_CheckAllocaIsInEntryBlock_l36			// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_CheckAllocaIsInEntryBlock_l36
	// CHECK-32-SAME: (i32 [[FOO:%.*]]) #[[ATTR0]] {			// CHECK-32-SAME: (i32 [[FOO:%.*]]) #[[ATTR0]] {
	// CHECK-32-NEXT: entry:			// CHECK-32-NEXT: entry:
	// CHECK-32-NEXT: [[FOO_ADDR:%.*]] = alloca i32, align 4			// CHECK-32-NEXT: [[FOO_ADDR:%.*]] = alloca i32, align 4
	// CHECK-32-NEXT: [[TMP:%.]] = alloca [[PRINTF_ARGS_0:%.]], align 8			// CHECK-32-NEXT: [[TMP:%.]] = alloca [[PRINTF_ARGS_0:%.]], align 8
	// CHECK-32-NEXT: store i32 [[FOO]], i32* [[FOO_ADDR]], align 4			// CHECK-32-NEXT: store i32 [[FOO]], i32* [[FOO_ADDR]], align 4
	// CHECK-32-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 1, i1 true, i1 true)			// CHECK-32-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_CheckAllocaIsInEntryBlock_l36_kernel_info, i1 true)
	// CHECK-32-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1			// CHECK-32-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
	// CHECK-32-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]			// CHECK-32-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
	// CHECK-32: user_code.entry:			// CHECK-32: user_code.entry:
	// CHECK-32-NEXT: [[TMP1:%.]] = load i32, i32 [[FOO_ADDR]], align 4			// CHECK-32-NEXT: [[TMP1:%.]] = load i32, i32 [[FOO_ADDR]], align 4
	// CHECK-32-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0			// CHECK-32-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0
	// CHECK-32-NEXT: br i1 [[TOBOOL]], label [[IF_THEN:%.]], label [[IF_END:%.]]			// CHECK-32-NEXT: br i1 [[TOBOOL]], label [[IF_THEN:%.]], label [[IF_END:%.]]
	// CHECK-32: if.then:			// CHECK-32: if.then:
	// CHECK-32-NEXT: [[TMP2:%.]] = getelementptr inbounds [[PRINTF_ARGS_0]], %printf_args.0 [[TMP]], i32 0, i32 0			// CHECK-32-NEXT: [[TMP2:%.]] = getelementptr inbounds [[PRINTF_ARGS_0]], %printf_args.0 [[TMP]], i32 0, i32 0
	// CHECK-32-NEXT: store i32 42, i32* [[TMP2]], align 4			// CHECK-32-NEXT: store i32 42, i32* [[TMP2]], align 4
	// CHECK-32-NEXT: [[TMP3:%.]] = bitcast %printf_args.0 [[TMP]] to i8*			// CHECK-32-NEXT: [[TMP3:%.]] = bitcast %printf_args.0 [[TMP]] to i8*
	// CHECK-32-NEXT: [[TMP4:%.]] = call i32 @__llvm_omp_vprintf(i8 getelementptr inbounds ([3 x i8], [3 x i8]* @.str2, i32 0, i32 0), i8* [[TMP3]], i32 4)			// CHECK-32-NEXT: [[TMP4:%.]] = call i32 @__llvm_omp_vprintf(i8 getelementptr inbounds ([3 x i8], [3 x i8]* @.str2, i32 0, i32 0), i8* [[TMP3]], i32 4)
	// CHECK-32-NEXT: br label [[IF_END]]			// CHECK-32-NEXT: br label [[IF_END]]
	// CHECK-32: worker.exit:			// CHECK-32: worker.exit:
	// CHECK-32-NEXT: ret void			// CHECK-32-NEXT: ret void
	// CHECK-32: if.end:			// CHECK-32: if.end:
	// CHECK-32-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true)			// CHECK-32-NEXT: call void @__kmpc_target_deinit(i1 true)
	// CHECK-32-NEXT: ret void			// CHECK-32-NEXT: ret void
	//			//

clang/test/OpenMP/nvptx_target_simd_codegen.cpp

Show First 20 Lines • Show All 55 Lines • ▼ Show 20 Lines	int bar(int n){
int a = 0;		int a = 0;

a += ftemplate<int>(n);		a += ftemplate<int>(n);

return a;		return a;
}		}

// CHECK-LABEL: define {{.*}}void {{@__omp_offloading_.+l32}}(		// CHECK-LABEL: define {{.*}}void {{@__omp_offloading_.+l32}}(
// CHECK: call i32 @__kmpc_target_init({{.*}}, i8 2, i1 false, i1 false)		// CHECK: call i32 @__kmpc_target_init({{.*}}, i1 false)
// CHECK-NOT: call void @__kmpc_for_static_init		// CHECK-NOT: call void @__kmpc_for_static_init
// CHECK-NOT: call void @__kmpc_for_static_fini		// CHECK-NOT: call void @__kmpc_for_static_fini
// CHECK: call void @__kmpc_target_deinit({{.*}}, i8 2, i1 false)		// CHECK: call void @__kmpc_target_deinit(i1 false)
// CHECK: ret void		// CHECK: ret void

// CHECK-LABEL: define {{.*}}void {{@__omp_offloading_.+l37}}(		// CHECK-LABEL: define {{.*}}void {{@__omp_offloading_.+l37}}(
// CHECK: call i32 @__kmpc_target_init({{.*}}, i8 2, i1 false, i1 false)		// CHECK: call i32 @__kmpc_target_init({{.*}}, i1 false)
// CHECK-NOT: call void @__kmpc_for_static_init		// CHECK-NOT: call void @__kmpc_for_static_init
// CHECK-NOT: call void @__kmpc_for_static_fini		// CHECK-NOT: call void @__kmpc_for_static_fini
// CHECK: call void @__kmpc_target_deinit({{.*}}, i8 2, i1 false)		// CHECK: call void @__kmpc_target_deinit(i1 false)
// CHECK: ret void		// CHECK: ret void

// CHECK-LABEL: define {{.*}}void {{@__omp_offloading_.+l42}}(		// CHECK-LABEL: define {{.*}}void {{@__omp_offloading_.+l42}}(
// CHECK: call i32 @__kmpc_target_init({{.*}}, i8 2, i1 false, i1 false)		// CHECK: call i32 @__kmpc_target_init({{.*}}, i1 false)
// CHECK-NOT: call void @__kmpc_for_static_init		// CHECK-NOT: call void @__kmpc_for_static_init
// CHECK-NOT: call void @__kmpc_for_static_fini		// CHECK-NOT: call void @__kmpc_for_static_fini
// CHECK: call void @__kmpc_target_deinit({{.*}}, i8 2, i1 false)		// CHECK: call void @__kmpc_target_deinit(i1 false)
// CHECK: ret void		// CHECK: ret void

// CHECK-LABEL: define {{.*}}void {{@__omp_offloading_.+l47}}(		// CHECK-LABEL: define {{.*}}void {{@__omp_offloading_.+l47}}(
// CHECK: call i32 @__kmpc_target_init({{.*}}, i8 2, i1 false, i1 false)		// CHECK: call i32 @__kmpc_target_init({{.*}}, i1 false)
// CHECK-NOT: call void @__kmpc_for_static_init		// CHECK-NOT: call void @__kmpc_for_static_init
// CHECK-NOT: call void @__kmpc_for_static_fini		// CHECK-NOT: call void @__kmpc_for_static_fini
// CHECK-NOT: call void @__kmpc_nvptx_end_reduce_nowait(		// CHECK-NOT: call void @__kmpc_nvptx_end_reduce_nowait(
// CHECK: call void @__kmpc_target_deinit({{.*}}, i8 2, i1 false)		// CHECK: call void @__kmpc_target_deinit(i1 false)
// CHECK: ret void		// CHECK: ret void

#endif		#endif

clang/test/OpenMP/nvptx_target_teams_codegen.cpp

	Show First 20 Lines • Show All 52 Lines • ▼ Show 20 Lines
	// CHECK1-SAME: (i64 [[A:%.*]]) #[[ATTR0:[0-9]+]] {			// CHECK1-SAME: (i64 [[A:%.*]]) #[[ATTR0:[0-9]+]] {
	// CHECK1-NEXT: entry:			// CHECK1-NEXT: entry:
	// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8			// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
	// CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8			// CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
	// CHECK1-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			// CHECK1-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	// CHECK1-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4			// CHECK1-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
	// CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8			// CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
	// CHECK1-NEXT: [[CONV:%.]] = bitcast i64 [[A_ADDR]] to i8*			// CHECK1-NEXT: [[CONV:%.]] = bitcast i64 [[A_ADDR]] to i8*
	// CHECK1-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1:[0-9]+]], i8 1, i1 true, i1 true)			// CHECK1-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIcET_i_l23_kernel_info, i1 true)
	// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1			// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
	// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]			// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
	// CHECK1: user_code.entry:			// CHECK1: user_code.entry:
	// CHECK1-NEXT: [[TMP1:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB1]])			// CHECK1-NEXT: [[TMP1:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB1:[0-9]+]])
	// CHECK1-NEXT: [[TMP2:%.]] = load i8, i8 [[CONV]], align 1			// CHECK1-NEXT: [[TMP2:%.]] = load i8, i8 [[CONV]], align 8
	// CHECK1-NEXT: [[CONV1:%.]] = bitcast i64 [[A_CASTED]] to i8*			// CHECK1-NEXT: [[CONV1:%.]] = bitcast i64 [[A_CASTED]] to i8*
	// CHECK1-NEXT: store i8 [[TMP2]], i8* [[CONV1]], align 1			// CHECK1-NEXT: store i8 [[TMP2]], i8* [[CONV1]], align 1
	// CHECK1-NEXT: [[TMP3:%.]] = load i64, i64 [[A_CASTED]], align 8			// CHECK1-NEXT: [[TMP3:%.]] = load i64, i64 [[A_CASTED]], align 8
	// CHECK1-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4			// CHECK1-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	// CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTTHREADID_TEMP_]], align 4			// CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTTHREADID_TEMP_]], align 4
	// CHECK1-NEXT: call void @__omp_outlined__(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i64 [[TMP3]]) #[[ATTR1:[0-9]+]]			// CHECK1-NEXT: call void @__omp_outlined__(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i64 [[TMP3]]) #[[ATTR1:[0-9]+]]
	// CHECK1-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true)			// CHECK1-NEXT: call void @__kmpc_target_deinit(i1 true)
	// CHECK1-NEXT: ret void			// CHECK1-NEXT: ret void
	// CHECK1: worker.exit:			// CHECK1: worker.exit:
	// CHECK1-NEXT: ret void			// CHECK1-NEXT: ret void
	//			//
	//			//
	// CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__			// CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__
	// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i64 [[A:%.]]) #[[ATTR0]] {			// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i64 [[A:%.]]) #[[ATTR0]] {
	// CHECK1-NEXT: entry:			// CHECK1-NEXT: entry:
	// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8			// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8
	// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8			// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8
	// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8			// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
	// CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8			// CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
	// CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8			// CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
	// CHECK1-NEXT: [[CONV:%.]] = bitcast i64 [[A_ADDR]] to i8*			// CHECK1-NEXT: [[CONV:%.]] = bitcast i64 [[A_ADDR]] to i8*
	// CHECK1-NEXT: store i8 49, i8* [[CONV]], align 1			// CHECK1-NEXT: store i8 49, i8* [[CONV]], align 8
	// CHECK1-NEXT: ret void			// CHECK1-NEXT: ret void
	//			//
	//			//
	// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIcET_i_l28			// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIcET_i_l28
	// CHECK1-SAME: (i64 [[AA:%.*]]) #[[ATTR0]] {			// CHECK1-SAME: (i64 [[AA:%.*]]) #[[ATTR0]] {
	// CHECK1-NEXT: entry:			// CHECK1-NEXT: entry:
	// CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8			// CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
	// CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8			// CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
	// CHECK1-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			// CHECK1-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	// CHECK1-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4			// CHECK1-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
	// CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8			// CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
	// CHECK1-NEXT: [[CONV:%.]] = bitcast i64 [[AA_ADDR]] to i16*			// CHECK1-NEXT: [[CONV:%.]] = bitcast i64 [[AA_ADDR]] to i16*
	// CHECK1-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 1, i1 true, i1 true)			// CHECK1-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIcET_i_l28_kernel_info, i1 true)
	// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1			// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
	// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]			// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
	// CHECK1: user_code.entry:			// CHECK1: user_code.entry:
	// CHECK1-NEXT: [[TMP1:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB1]])			// CHECK1-NEXT: [[TMP1:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB1]])
	// CHECK1-NEXT: [[TMP2:%.]] = load i16, i16 [[CONV]], align 2			// CHECK1-NEXT: [[TMP2:%.]] = load i16, i16 [[CONV]], align 8
	// CHECK1-NEXT: [[CONV1:%.]] = bitcast i64 [[AA_CASTED]] to i16*			// CHECK1-NEXT: [[CONV1:%.]] = bitcast i64 [[AA_CASTED]] to i16*
	// CHECK1-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2			// CHECK1-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
	// CHECK1-NEXT: [[TMP3:%.]] = load i64, i64 [[AA_CASTED]], align 8			// CHECK1-NEXT: [[TMP3:%.]] = load i64, i64 [[AA_CASTED]], align 8
	// CHECK1-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4			// CHECK1-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	// CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTTHREADID_TEMP_]], align 4			// CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTTHREADID_TEMP_]], align 4
	// CHECK1-NEXT: call void @__omp_outlined__1(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i64 [[TMP3]]) #[[ATTR1]]			// CHECK1-NEXT: call void @__omp_outlined__1(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i64 [[TMP3]]) #[[ATTR1]]
	// CHECK1-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true)			// CHECK1-NEXT: call void @__kmpc_target_deinit(i1 true)
	// CHECK1-NEXT: ret void			// CHECK1-NEXT: ret void
	// CHECK1: worker.exit:			// CHECK1: worker.exit:
	// CHECK1-NEXT: ret void			// CHECK1-NEXT: ret void
	//			//
	//			//
	// CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__1			// CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__1
	// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i64 [[AA:%.]]) #[[ATTR0]] {			// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i64 [[AA:%.]]) #[[ATTR0]] {
	// CHECK1-NEXT: entry:			// CHECK1-NEXT: entry:
	// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8			// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8
	// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8			// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8
	// CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8			// CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
	// CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8			// CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
	// CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8			// CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
	// CHECK1-NEXT: [[CONV:%.]] = bitcast i64 [[AA_ADDR]] to i16*			// CHECK1-NEXT: [[CONV:%.]] = bitcast i64 [[AA_ADDR]] to i16*
	// CHECK1-NEXT: store i16 1, i16* [[CONV]], align 2			// CHECK1-NEXT: store i16 1, i16* [[CONV]], align 8
	// CHECK1-NEXT: ret void			// CHECK1-NEXT: ret void
	//			//
	//			//
	// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIcET_i_l33			// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIcET_i_l33
	// CHECK1-SAME: (i64 [[AA:%.*]]) #[[ATTR0]] {			// CHECK1-SAME: (i64 [[AA:%.*]]) #[[ATTR0]] {
	// CHECK1-NEXT: entry:			// CHECK1-NEXT: entry:
	// CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8			// CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
	// CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8			// CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
	// CHECK1-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			// CHECK1-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	// CHECK1-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4			// CHECK1-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
	// CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8			// CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
	// CHECK1-NEXT: [[CONV:%.]] = bitcast i64 [[AA_ADDR]] to i16*			// CHECK1-NEXT: [[CONV:%.]] = bitcast i64 [[AA_ADDR]] to i16*
	// CHECK1-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 2, i1 false, i1 true)			// CHECK1-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIcET_i_l33_kernel_info, i1 true)
	// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1			// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
	// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]			// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
	// CHECK1: user_code.entry:			// CHECK1: user_code.entry:
	// CHECK1-NEXT: [[TMP1:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB2:[0-9]+]])			// CHECK1-NEXT: [[TMP1:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB2:[0-9]+]])
	// CHECK1-NEXT: [[TMP2:%.]] = load i16, i16 [[CONV]], align 2			// CHECK1-NEXT: [[TMP2:%.]] = load i16, i16 [[CONV]], align 8
	// CHECK1-NEXT: [[CONV1:%.]] = bitcast i64 [[AA_CASTED]] to i16*			// CHECK1-NEXT: [[CONV1:%.]] = bitcast i64 [[AA_CASTED]] to i16*
	// CHECK1-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2			// CHECK1-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
	// CHECK1-NEXT: [[TMP3:%.]] = load i64, i64 [[AA_CASTED]], align 8			// CHECK1-NEXT: [[TMP3:%.]] = load i64, i64 [[AA_CASTED]], align 8
	// CHECK1-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4			// CHECK1-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	// CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTTHREADID_TEMP_]], align 4			// CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTTHREADID_TEMP_]], align 4
	// CHECK1-NEXT: call void @__omp_outlined__2(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i64 [[TMP3]]) #[[ATTR1]]			// CHECK1-NEXT: call void @__omp_outlined__2(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i64 [[TMP3]]) #[[ATTR1]]
	// CHECK1-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 true)			// CHECK1-NEXT: call void @__kmpc_target_deinit(i1 true)
	// CHECK1-NEXT: ret void			// CHECK1-NEXT: ret void
	// CHECK1: worker.exit:			// CHECK1: worker.exit:
	// CHECK1-NEXT: ret void			// CHECK1-NEXT: ret void
	//			//
	//			//
	// CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__2			// CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__2
	// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i64 [[AA:%.]]) #[[ATTR0]] {			// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i64 [[AA:%.]]) #[[ATTR0]] {
	// CHECK1-NEXT: entry:			// CHECK1-NEXT: entry:
	▲ Show 20 Lines • Show All 54 Lines • ▼ Show 20 Lines
	// CHECK2-SAME: (i32 [[A:%.*]]) #[[ATTR0:[0-9]+]] {			// CHECK2-SAME: (i32 [[A:%.*]]) #[[ATTR0:[0-9]+]] {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	// CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4			// CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
	// CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4			// CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
	// CHECK2-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			// CHECK2-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	// CHECK2-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4			// CHECK2-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
	// CHECK2-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4			// CHECK2-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
	// CHECK2-NEXT: [[CONV:%.]] = bitcast i32 [[A_ADDR]] to i8*			// CHECK2-NEXT: [[CONV:%.]] = bitcast i32 [[A_ADDR]] to i8*
	// CHECK2-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1:[0-9]+]], i8 1, i1 true, i1 true)			// CHECK2-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIcET_i_l23_kernel_info, i1 true)
	// CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1			// CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
	// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]			// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
	// CHECK2: user_code.entry:			// CHECK2: user_code.entry:
	// CHECK2-NEXT: [[TMP1:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB1]])			// CHECK2-NEXT: [[TMP1:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB1:[0-9]+]])
	// CHECK2-NEXT: [[TMP2:%.]] = load i8, i8 [[CONV]], align 1			// CHECK2-NEXT: [[TMP2:%.]] = load i8, i8 [[CONV]], align 4
	// CHECK2-NEXT: [[CONV1:%.]] = bitcast i32 [[A_CASTED]] to i8*			// CHECK2-NEXT: [[CONV1:%.]] = bitcast i32 [[A_CASTED]] to i8*
	// CHECK2-NEXT: store i8 [[TMP2]], i8* [[CONV1]], align 1			// CHECK2-NEXT: store i8 [[TMP2]], i8* [[CONV1]], align 1
	// CHECK2-NEXT: [[TMP3:%.]] = load i32, i32 [[A_CASTED]], align 4			// CHECK2-NEXT: [[TMP3:%.]] = load i32, i32 [[A_CASTED]], align 4
	// CHECK2-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4			// CHECK2-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	// CHECK2-NEXT: store i32 [[TMP1]], i32* [[DOTTHREADID_TEMP_]], align 4			// CHECK2-NEXT: store i32 [[TMP1]], i32* [[DOTTHREADID_TEMP_]], align 4
	// CHECK2-NEXT: call void @__omp_outlined__(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i32 [[TMP3]]) #[[ATTR1:[0-9]+]]			// CHECK2-NEXT: call void @__omp_outlined__(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i32 [[TMP3]]) #[[ATTR1:[0-9]+]]
	// CHECK2-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true)			// CHECK2-NEXT: call void @__kmpc_target_deinit(i1 true)
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	// CHECK2: worker.exit:			// CHECK2: worker.exit:
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__			// CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__
	// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i32 [[A:%.]]) #[[ATTR0]] {			// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i32 [[A:%.]]) #[[ATTR0]] {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 4			// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 4
	// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 4			// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 4
	// CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4			// CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
	// CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4			// CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
	// CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4			// CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
	// CHECK2-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4			// CHECK2-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
	// CHECK2-NEXT: [[CONV:%.]] = bitcast i32 [[A_ADDR]] to i8*			// CHECK2-NEXT: [[CONV:%.]] = bitcast i32 [[A_ADDR]] to i8*
	// CHECK2-NEXT: store i8 49, i8* [[CONV]], align 1			// CHECK2-NEXT: store i8 49, i8* [[CONV]], align 4
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIcET_i_l28			// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIcET_i_l28
	// CHECK2-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] {			// CHECK2-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	// CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4			// CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
	// CHECK2-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4			// CHECK2-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
	// CHECK2-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			// CHECK2-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	// CHECK2-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4			// CHECK2-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
	// CHECK2-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4			// CHECK2-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
	// CHECK2-NEXT: [[CONV:%.]] = bitcast i32 [[AA_ADDR]] to i16*			// CHECK2-NEXT: [[CONV:%.]] = bitcast i32 [[AA_ADDR]] to i16*
	// CHECK2-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 1, i1 true, i1 true)			// CHECK2-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIcET_i_l28_kernel_info, i1 true)
	// CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1			// CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
	// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]			// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
	// CHECK2: user_code.entry:			// CHECK2: user_code.entry:
	// CHECK2-NEXT: [[TMP1:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB1]])			// CHECK2-NEXT: [[TMP1:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB1]])
	// CHECK2-NEXT: [[TMP2:%.]] = load i16, i16 [[CONV]], align 2			// CHECK2-NEXT: [[TMP2:%.]] = load i16, i16 [[CONV]], align 4
	// CHECK2-NEXT: [[CONV1:%.]] = bitcast i32 [[AA_CASTED]] to i16*			// CHECK2-NEXT: [[CONV1:%.]] = bitcast i32 [[AA_CASTED]] to i16*
	// CHECK2-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2			// CHECK2-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
	// CHECK2-NEXT: [[TMP3:%.]] = load i32, i32 [[AA_CASTED]], align 4			// CHECK2-NEXT: [[TMP3:%.]] = load i32, i32 [[AA_CASTED]], align 4
	// CHECK2-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4			// CHECK2-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	// CHECK2-NEXT: store i32 [[TMP1]], i32* [[DOTTHREADID_TEMP_]], align 4			// CHECK2-NEXT: store i32 [[TMP1]], i32* [[DOTTHREADID_TEMP_]], align 4
	// CHECK2-NEXT: call void @__omp_outlined__1(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i32 [[TMP3]]) #[[ATTR1]]			// CHECK2-NEXT: call void @__omp_outlined__1(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i32 [[TMP3]]) #[[ATTR1]]
	// CHECK2-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true)			// CHECK2-NEXT: call void @__kmpc_target_deinit(i1 true)
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	// CHECK2: worker.exit:			// CHECK2: worker.exit:
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__1			// CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__1
	// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i32 [[AA:%.]]) #[[ATTR0]] {			// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i32 [[AA:%.]]) #[[ATTR0]] {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 4			// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 4
	// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 4			// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 4
	// CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4			// CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
	// CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4			// CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
	// CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4			// CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
	// CHECK2-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4			// CHECK2-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
	// CHECK2-NEXT: [[CONV:%.]] = bitcast i32 [[AA_ADDR]] to i16*			// CHECK2-NEXT: [[CONV:%.]] = bitcast i32 [[AA_ADDR]] to i16*
	// CHECK2-NEXT: store i16 1, i16* [[CONV]], align 2			// CHECK2-NEXT: store i16 1, i16* [[CONV]], align 4
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIcET_i_l33			// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIcET_i_l33
	// CHECK2-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] {			// CHECK2-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	// CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4			// CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
	// CHECK2-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4			// CHECK2-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
	// CHECK2-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			// CHECK2-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	// CHECK2-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4			// CHECK2-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
	// CHECK2-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4			// CHECK2-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
	// CHECK2-NEXT: [[CONV:%.]] = bitcast i32 [[AA_ADDR]] to i16*			// CHECK2-NEXT: [[CONV:%.]] = bitcast i32 [[AA_ADDR]] to i16*
	// CHECK2-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 2, i1 false, i1 true)			// CHECK2-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIcET_i_l33_kernel_info, i1 true)
	// CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1			// CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
	// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]			// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
	// CHECK2: user_code.entry:			// CHECK2: user_code.entry:
	// CHECK2-NEXT: [[TMP1:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB2:[0-9]+]])			// CHECK2-NEXT: [[TMP1:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB2:[0-9]+]])
	// CHECK2-NEXT: [[TMP2:%.]] = load i16, i16 [[CONV]], align 2			// CHECK2-NEXT: [[TMP2:%.]] = load i16, i16 [[CONV]], align 4
	// CHECK2-NEXT: [[CONV1:%.]] = bitcast i32 [[AA_CASTED]] to i16*			// CHECK2-NEXT: [[CONV1:%.]] = bitcast i32 [[AA_CASTED]] to i16*
	// CHECK2-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2			// CHECK2-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
	// CHECK2-NEXT: [[TMP3:%.]] = load i32, i32 [[AA_CASTED]], align 4			// CHECK2-NEXT: [[TMP3:%.]] = load i32, i32 [[AA_CASTED]], align 4
	// CHECK2-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4			// CHECK2-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	// CHECK2-NEXT: store i32 [[TMP1]], i32* [[DOTTHREADID_TEMP_]], align 4			// CHECK2-NEXT: store i32 [[TMP1]], i32* [[DOTTHREADID_TEMP_]], align 4
	// CHECK2-NEXT: call void @__omp_outlined__2(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i32 [[TMP3]]) #[[ATTR1]]			// CHECK2-NEXT: call void @__omp_outlined__2(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i32 [[TMP3]]) #[[ATTR1]]
	// CHECK2-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 true)			// CHECK2-NEXT: call void @__kmpc_target_deinit(i1 true)
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	// CHECK2: worker.exit:			// CHECK2: worker.exit:
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__2			// CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__2
	// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i32 [[AA:%.]]) #[[ATTR0]] {			// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i32 [[AA:%.]]) #[[ATTR0]] {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
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	// CHECK3-SAME: (i32 [[A:%.*]]) #[[ATTR0:[0-9]+]] {			// CHECK3-SAME: (i32 [[A:%.*]]) #[[ATTR0:[0-9]+]] {
	// CHECK3-NEXT: entry:			// CHECK3-NEXT: entry:
	// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4			// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
	// CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4			// CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
	// CHECK3-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			// CHECK3-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	// CHECK3-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4			// CHECK3-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
	// CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4			// CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
	// CHECK3-NEXT: [[CONV:%.]] = bitcast i32 [[A_ADDR]] to i8*			// CHECK3-NEXT: [[CONV:%.]] = bitcast i32 [[A_ADDR]] to i8*
	// CHECK3-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1:[0-9]+]], i8 1, i1 true, i1 true)			// CHECK3-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIcET_i_l23_kernel_info, i1 true)
	// CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1			// CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
	// CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]			// CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
	// CHECK3: user_code.entry:			// CHECK3: user_code.entry:
	// CHECK3-NEXT: [[TMP1:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB1]])			// CHECK3-NEXT: [[TMP1:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB1:[0-9]+]])
	// CHECK3-NEXT: [[TMP2:%.]] = load i8, i8 [[CONV]], align 1			// CHECK3-NEXT: [[TMP2:%.]] = load i8, i8 [[CONV]], align 4
	// CHECK3-NEXT: [[CONV1:%.]] = bitcast i32 [[A_CASTED]] to i8*			// CHECK3-NEXT: [[CONV1:%.]] = bitcast i32 [[A_CASTED]] to i8*
	// CHECK3-NEXT: store i8 [[TMP2]], i8* [[CONV1]], align 1			// CHECK3-NEXT: store i8 [[TMP2]], i8* [[CONV1]], align 1
	// CHECK3-NEXT: [[TMP3:%.]] = load i32, i32 [[A_CASTED]], align 4			// CHECK3-NEXT: [[TMP3:%.]] = load i32, i32 [[A_CASTED]], align 4
	// CHECK3-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4			// CHECK3-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	// CHECK3-NEXT: store i32 [[TMP1]], i32* [[DOTTHREADID_TEMP_]], align 4			// CHECK3-NEXT: store i32 [[TMP1]], i32* [[DOTTHREADID_TEMP_]], align 4
	// CHECK3-NEXT: call void @__omp_outlined__(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i32 [[TMP3]]) #[[ATTR1:[0-9]+]]			// CHECK3-NEXT: call void @__omp_outlined__(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i32 [[TMP3]]) #[[ATTR1:[0-9]+]]
	// CHECK3-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true)			// CHECK3-NEXT: call void @__kmpc_target_deinit(i1 true)
	// CHECK3-NEXT: ret void			// CHECK3-NEXT: ret void
	// CHECK3: worker.exit:			// CHECK3: worker.exit:
	// CHECK3-NEXT: ret void			// CHECK3-NEXT: ret void
	//			//
	//			//
	// CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__			// CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__
	// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i32 [[A:%.]]) #[[ATTR0]] {			// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i32 [[A:%.]]) #[[ATTR0]] {
	// CHECK3-NEXT: entry:			// CHECK3-NEXT: entry:
	// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 4			// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 4
	// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 4			// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 4
	// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4			// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
	// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4			// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
	// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4			// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
	// CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4			// CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
	// CHECK3-NEXT: [[CONV:%.]] = bitcast i32 [[A_ADDR]] to i8*			// CHECK3-NEXT: [[CONV:%.]] = bitcast i32 [[A_ADDR]] to i8*
	// CHECK3-NEXT: store i8 49, i8* [[CONV]], align 1			// CHECK3-NEXT: store i8 49, i8* [[CONV]], align 4
	// CHECK3-NEXT: ret void			// CHECK3-NEXT: ret void
	//			//
	//			//
	// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIcET_i_l28			// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIcET_i_l28
	// CHECK3-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] {			// CHECK3-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] {
	// CHECK3-NEXT: entry:			// CHECK3-NEXT: entry:
	// CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4			// CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
	// CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4			// CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
	// CHECK3-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			// CHECK3-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	// CHECK3-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4			// CHECK3-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
	// CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4			// CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
	// CHECK3-NEXT: [[CONV:%.]] = bitcast i32 [[AA_ADDR]] to i16*			// CHECK3-NEXT: [[CONV:%.]] = bitcast i32 [[AA_ADDR]] to i16*
	// CHECK3-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 1, i1 true, i1 true)			// CHECK3-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIcET_i_l28_kernel_info, i1 true)
	// CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1			// CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
	// CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]			// CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
	// CHECK3: user_code.entry:			// CHECK3: user_code.entry:
	// CHECK3-NEXT: [[TMP1:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB1]])			// CHECK3-NEXT: [[TMP1:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB1]])
	// CHECK3-NEXT: [[TMP2:%.]] = load i16, i16 [[CONV]], align 2			// CHECK3-NEXT: [[TMP2:%.]] = load i16, i16 [[CONV]], align 4
	// CHECK3-NEXT: [[CONV1:%.]] = bitcast i32 [[AA_CASTED]] to i16*			// CHECK3-NEXT: [[CONV1:%.]] = bitcast i32 [[AA_CASTED]] to i16*
	// CHECK3-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2			// CHECK3-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
	// CHECK3-NEXT: [[TMP3:%.]] = load i32, i32 [[AA_CASTED]], align 4			// CHECK3-NEXT: [[TMP3:%.]] = load i32, i32 [[AA_CASTED]], align 4
	// CHECK3-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4			// CHECK3-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	// CHECK3-NEXT: store i32 [[TMP1]], i32* [[DOTTHREADID_TEMP_]], align 4			// CHECK3-NEXT: store i32 [[TMP1]], i32* [[DOTTHREADID_TEMP_]], align 4
	// CHECK3-NEXT: call void @__omp_outlined__1(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i32 [[TMP3]]) #[[ATTR1]]			// CHECK3-NEXT: call void @__omp_outlined__1(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i32 [[TMP3]]) #[[ATTR1]]
	// CHECK3-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true)			// CHECK3-NEXT: call void @__kmpc_target_deinit(i1 true)
	// CHECK3-NEXT: ret void			// CHECK3-NEXT: ret void
	// CHECK3: worker.exit:			// CHECK3: worker.exit:
	// CHECK3-NEXT: ret void			// CHECK3-NEXT: ret void
	//			//
	//			//
	// CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__1			// CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__1
	// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i32 [[AA:%.]]) #[[ATTR0]] {			// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i32 [[AA:%.]]) #[[ATTR0]] {
	// CHECK3-NEXT: entry:			// CHECK3-NEXT: entry:
	// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 4			// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 4
	// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 4			// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 4
	// CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4			// CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
	// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4			// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
	// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4			// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
	// CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4			// CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
	// CHECK3-NEXT: [[CONV:%.]] = bitcast i32 [[AA_ADDR]] to i16*			// CHECK3-NEXT: [[CONV:%.]] = bitcast i32 [[AA_ADDR]] to i16*
	// CHECK3-NEXT: store i16 1, i16* [[CONV]], align 2			// CHECK3-NEXT: store i16 1, i16* [[CONV]], align 4
	// CHECK3-NEXT: ret void			// CHECK3-NEXT: ret void
	//			//
	//			//
	// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIcET_i_l33			// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIcET_i_l33
	// CHECK3-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] {			// CHECK3-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] {
	// CHECK3-NEXT: entry:			// CHECK3-NEXT: entry:
	// CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4			// CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
	// CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4			// CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
	// CHECK3-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			// CHECK3-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	// CHECK3-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4			// CHECK3-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
	// CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4			// CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
	// CHECK3-NEXT: [[CONV:%.]] = bitcast i32 [[AA_ADDR]] to i16*			// CHECK3-NEXT: [[CONV:%.]] = bitcast i32 [[AA_ADDR]] to i16*
	// CHECK3-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 2, i1 false, i1 true)			// CHECK3-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIcET_i_l33_kernel_info, i1 true)
	// CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1			// CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
	// CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]			// CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
	// CHECK3: user_code.entry:			// CHECK3: user_code.entry:
	// CHECK3-NEXT: [[TMP1:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB2:[0-9]+]])			// CHECK3-NEXT: [[TMP1:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB2:[0-9]+]])
	// CHECK3-NEXT: [[TMP2:%.]] = load i16, i16 [[CONV]], align 2			// CHECK3-NEXT: [[TMP2:%.]] = load i16, i16 [[CONV]], align 4
	// CHECK3-NEXT: [[CONV1:%.]] = bitcast i32 [[AA_CASTED]] to i16*			// CHECK3-NEXT: [[CONV1:%.]] = bitcast i32 [[AA_CASTED]] to i16*
	// CHECK3-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2			// CHECK3-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
	// CHECK3-NEXT: [[TMP3:%.]] = load i32, i32 [[AA_CASTED]], align 4			// CHECK3-NEXT: [[TMP3:%.]] = load i32, i32 [[AA_CASTED]], align 4
	// CHECK3-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4			// CHECK3-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	// CHECK3-NEXT: store i32 [[TMP1]], i32* [[DOTTHREADID_TEMP_]], align 4			// CHECK3-NEXT: store i32 [[TMP1]], i32* [[DOTTHREADID_TEMP_]], align 4
	// CHECK3-NEXT: call void @__omp_outlined__2(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i32 [[TMP3]]) #[[ATTR1]]			// CHECK3-NEXT: call void @__omp_outlined__2(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i32 [[TMP3]]) #[[ATTR1]]
	// CHECK3-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 true)			// CHECK3-NEXT: call void @__kmpc_target_deinit(i1 true)
	// CHECK3-NEXT: ret void			// CHECK3-NEXT: ret void
	// CHECK3: worker.exit:			// CHECK3: worker.exit:
	// CHECK3-NEXT: ret void			// CHECK3-NEXT: ret void
	//			//
	//			//
	// CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__2			// CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__2
	// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i32 [[AA:%.]]) #[[ATTR0]] {			// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i32 [[AA:%.]]) #[[ATTR0]] {
	// CHECK3-NEXT: entry:			// CHECK3-NEXT: entry:
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clang/test/OpenMP/nvptx_target_teams_distribute_codegen.cpp

	Show First 20 Lines • Show All 573 Lines • ▼ Show 20 Lines
	// CHECK6-NEXT: [[TMP5:%.]] = load i32, i32** [[TMP4]], align 4			// CHECK6-NEXT: [[TMP5:%.]] = load i32, i32** [[TMP4]], align 4
	// CHECK6-NEXT: call void @__omp_outlined__1(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]], i32* [[TMP5]]) #[[ATTR3]]			// CHECK6-NEXT: call void @__omp_outlined__1(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]], i32* [[TMP5]]) #[[ATTR3]]
	// CHECK6-NEXT: ret void			// CHECK6-NEXT: ret void
	// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIcET_i_l16			// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIcET_i_l16
	// CHECK1-SAME: () #[[ATTR0:[0-9]+]] {			// CHECK1-SAME: () #[[ATTR0:[0-9]+]] {
	// CHECK1-NEXT: entry:			// CHECK1-NEXT: entry:
	// CHECK1-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			// CHECK1-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	// CHECK1-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4			// CHECK1-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
	// CHECK1-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1:[0-9]+]], i8 1, i1 true, i1 true)			// CHECK1-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIcET_i_l16_kernel_info, i1 true)
	// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1			// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
	// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]			// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
	// CHECK1: user_code.entry:			// CHECK1: user_code.entry:
	// CHECK1-NEXT: [[TMP1:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB1]])			// CHECK1-NEXT: [[TMP1:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB1:[0-9]+]])
	// CHECK1-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4			// CHECK1-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	// CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTTHREADID_TEMP_]], align 4			// CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTTHREADID_TEMP_]], align 4
	// CHECK1-NEXT: call void @__omp_outlined__(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]]) #[[ATTR4:[0-9]+]]			// CHECK1-NEXT: call void @__omp_outlined__(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]]) #[[ATTR4:[0-9]+]]
	// CHECK1-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true)			// CHECK1-NEXT: call void @__kmpc_target_deinit(i1 true)
	// CHECK1-NEXT: ret void			// CHECK1-NEXT: ret void
	// CHECK1: worker.exit:			// CHECK1: worker.exit:
	// CHECK1-NEXT: ret void			// CHECK1-NEXT: ret void
	//			//
	//			//
	// CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__			// CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__
	// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {			// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
	// CHECK1-NEXT: entry:			// CHECK1-NEXT: entry:
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	// CHECK1-NEXT: ret void			// CHECK1-NEXT: ret void
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIcET_i_l16			// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIcET_i_l16
	// CHECK2-SAME: () #[[ATTR0:[0-9]+]] {			// CHECK2-SAME: () #[[ATTR0:[0-9]+]] {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	// CHECK2-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			// CHECK2-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	// CHECK2-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4			// CHECK2-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
	// CHECK2-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1:[0-9]+]], i8 1, i1 true, i1 true)			// CHECK2-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIcET_i_l16_kernel_info, i1 true)
	// CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1			// CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
	// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]			// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
	// CHECK2: user_code.entry:			// CHECK2: user_code.entry:
	// CHECK2-NEXT: [[TMP1:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB1]])			// CHECK2-NEXT: [[TMP1:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB1:[0-9]+]])
	// CHECK2-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4			// CHECK2-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	// CHECK2-NEXT: store i32 [[TMP1]], i32* [[DOTTHREADID_TEMP_]], align 4			// CHECK2-NEXT: store i32 [[TMP1]], i32* [[DOTTHREADID_TEMP_]], align 4
	// CHECK2-NEXT: call void @__omp_outlined__(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]]) #[[ATTR4:[0-9]+]]			// CHECK2-NEXT: call void @__omp_outlined__(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]]) #[[ATTR4:[0-9]+]]
	// CHECK2-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true)			// CHECK2-NEXT: call void @__kmpc_target_deinit(i1 true)
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	// CHECK2: worker.exit:			// CHECK2: worker.exit:
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__			// CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__
	// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {			// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
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	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	//			//
	//			//
	// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIcET_i_l16			// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIcET_i_l16
	// CHECK3-SAME: () #[[ATTR0:[0-9]+]] {			// CHECK3-SAME: () #[[ATTR0:[0-9]+]] {
	// CHECK3-NEXT: entry:			// CHECK3-NEXT: entry:
	// CHECK3-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			// CHECK3-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	// CHECK3-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4			// CHECK3-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
	// CHECK3-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1:[0-9]+]], i8 1, i1 true, i1 true)			// CHECK3-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIcET_i_l16_kernel_info, i1 true)
	// CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1			// CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
	// CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]			// CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
	// CHECK3: user_code.entry:			// CHECK3: user_code.entry:
	// CHECK3-NEXT: [[TMP1:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB1]])			// CHECK3-NEXT: [[TMP1:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB1:[0-9]+]])
	// CHECK3-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4			// CHECK3-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	// CHECK3-NEXT: store i32 [[TMP1]], i32* [[DOTTHREADID_TEMP_]], align 4			// CHECK3-NEXT: store i32 [[TMP1]], i32* [[DOTTHREADID_TEMP_]], align 4
	// CHECK3-NEXT: call void @__omp_outlined__(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]]) #[[ATTR4:[0-9]+]]			// CHECK3-NEXT: call void @__omp_outlined__(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]]) #[[ATTR4:[0-9]+]]
	// CHECK3-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true)			// CHECK3-NEXT: call void @__kmpc_target_deinit(i1 true)
	// CHECK3-NEXT: ret void			// CHECK3-NEXT: ret void
	// CHECK3: worker.exit:			// CHECK3: worker.exit:
	// CHECK3-NEXT: ret void			// CHECK3-NEXT: ret void
	//			//
	//			//
	// CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__			// CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__
	// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {			// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
	// CHECK3-NEXT: entry:			// CHECK3-NEXT: entry:
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clang/test/OpenMP/nvptx_target_teams_distribute_parallel_for_codegen.cpp

This file is larger than 256 KB, so syntax highlighting is disabled by default.

	Show First 20 Lines • Show All 18,477 Lines • ▼ Show 20 Lines
	// CHECK1-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			// CHECK1-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	// CHECK1-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4			// CHECK1-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
	// CHECK1-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8			// CHECK1-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
	// CHECK1-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8			// CHECK1-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8
	// CHECK1-NEXT: store i64 [[L]], i64* [[L_ADDR]], align 8			// CHECK1-NEXT: store i64 [[L]], i64* [[L_ADDR]], align 8
	// CHECK1-NEXT: [[CONV:%.]] = bitcast i64 [[N_ADDR]] to i32*			// CHECK1-NEXT: [[CONV:%.]] = bitcast i64 [[N_ADDR]] to i32*
	// CHECK1-NEXT: [[TMP0:%.]] = load [1000 x i32], [1000 x i32]** [[A_ADDR]], align 8			// CHECK1-NEXT: [[TMP0:%.]] = load [1000 x i32], [1000 x i32]** [[A_ADDR]], align 8
	// CHECK1-NEXT: [[CONV1:%.]] = bitcast i64 [[L_ADDR]] to i32*			// CHECK1-NEXT: [[CONV1:%.]] = bitcast i64 [[L_ADDR]] to i32*
	// CHECK1-NEXT: [[TMP1:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1:[0-9]+]], i8 2, i1 false, i1 false)			// CHECK1-NEXT: [[TMP1:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l28_kernel_info, i1 false)
	// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1			// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
	// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]			// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
	// CHECK1: user_code.entry:			// CHECK1: user_code.entry:
	// CHECK1-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB4:[0-9]+]])			// CHECK1-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB4:[0-9]+]])
	// CHECK1-NEXT: [[TMP3:%.]] = load i32, i32 [[CONV]], align 4			// CHECK1-NEXT: [[TMP3:%.]] = load i32, i32 [[CONV]], align 4
	// CHECK1-NEXT: [[CONV2:%.]] = bitcast i64 [[N_CASTED]] to i32*			// CHECK1-NEXT: [[CONV2:%.]] = bitcast i64 [[N_CASTED]] to i32*
	// CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4			// CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
	// CHECK1-NEXT: [[TMP4:%.]] = load i64, i64 [[N_CASTED]], align 8			// CHECK1-NEXT: [[TMP4:%.]] = load i64, i64 [[N_CASTED]], align 8
	// CHECK1-NEXT: [[TMP5:%.]] = load i32, i32 [[CONV1]], align 4			// CHECK1-NEXT: [[TMP5:%.]] = load i32, i32 [[CONV1]], align 4
	// CHECK1-NEXT: [[CONV3:%.]] = bitcast i64 [[L_CASTED]] to i32*			// CHECK1-NEXT: [[CONV3:%.]] = bitcast i64 [[L_CASTED]] to i32*
	// CHECK1-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4			// CHECK1-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4
	// CHECK1-NEXT: [[TMP6:%.]] = load i64, i64 [[L_CASTED]], align 8			// CHECK1-NEXT: [[TMP6:%.]] = load i64, i64 [[L_CASTED]], align 8
	// CHECK1-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4			// CHECK1-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4			// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4
	// CHECK1-NEXT: call void @__omp_outlined__(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i64 [[TMP4]], [1000 x i32]* [[TMP0]], i64 [[TMP6]]) #[[ATTR2:[0-9]+]]			// CHECK1-NEXT: call void @__omp_outlined__(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i64 [[TMP4]], [1000 x i32]* [[TMP0]], i64 [[TMP6]]) #[[ATTR2:[0-9]+]]
	// CHECK1-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 false)			// CHECK1-NEXT: call void @__kmpc_target_deinit(i1 false)
	// CHECK1-NEXT: ret void			// CHECK1-NEXT: ret void
	// CHECK1: worker.exit:			// CHECK1: worker.exit:
	// CHECK1-NEXT: ret void			// CHECK1-NEXT: ret void
	//			//
	//			//
	// CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__			// CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__
	// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i64 [[N:%.]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.]], i64 [[L:%.]]) #[[ATTR0]] {			// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i64 [[N:%.]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.]], i64 [[L:%.]]) #[[ATTR0]] {
	// CHECK1-NEXT: entry:			// CHECK1-NEXT: entry:
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	// CHECK1-NEXT: [[AA_ADDR:%.]] = alloca [1000 x i16], align 8			// CHECK1-NEXT: [[AA_ADDR:%.]] = alloca [1000 x i16], align 8
	// CHECK1-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8			// CHECK1-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8
	// CHECK1-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			// CHECK1-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	// CHECK1-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4			// CHECK1-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
	// CHECK1-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8			// CHECK1-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
	// CHECK1-NEXT: store [1000 x i16]* [[AA]], [1000 x i16]** [[AA_ADDR]], align 8			// CHECK1-NEXT: store [1000 x i16]* [[AA]], [1000 x i16]** [[AA_ADDR]], align 8
	// CHECK1-NEXT: [[CONV:%.]] = bitcast i64 [[N_ADDR]] to i32*			// CHECK1-NEXT: [[CONV:%.]] = bitcast i64 [[N_ADDR]] to i32*
	// CHECK1-NEXT: [[TMP0:%.]] = load [1000 x i16], [1000 x i16]** [[AA_ADDR]], align 8			// CHECK1-NEXT: [[TMP0:%.]] = load [1000 x i16], [1000 x i16]** [[AA_ADDR]], align 8
	// CHECK1-NEXT: [[TMP1:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 2, i1 false, i1 false)			// CHECK1-NEXT: [[TMP1:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l34_kernel_info, i1 false)
	// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1			// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
	// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]			// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
	// CHECK1: user_code.entry:			// CHECK1: user_code.entry:
	// CHECK1-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB4]])			// CHECK1-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB4]])
	// CHECK1-NEXT: [[TMP3:%.]] = load i32, i32 [[CONV]], align 4			// CHECK1-NEXT: [[TMP3:%.]] = load i32, i32 [[CONV]], align 4
	// CHECK1-NEXT: [[CONV1:%.]] = bitcast i64 [[N_CASTED]] to i32*			// CHECK1-NEXT: [[CONV1:%.]] = bitcast i64 [[N_CASTED]] to i32*
	// CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4			// CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4
	// CHECK1-NEXT: [[TMP4:%.]] = load i64, i64 [[N_CASTED]], align 8			// CHECK1-NEXT: [[TMP4:%.]] = load i64, i64 [[N_CASTED]], align 8
	// CHECK1-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4			// CHECK1-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4			// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4
	// CHECK1-NEXT: call void @__omp_outlined__2(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i64 [[TMP4]], [1000 x i16]* [[TMP0]]) #[[ATTR2]]			// CHECK1-NEXT: call void @__omp_outlined__2(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i64 [[TMP4]], [1000 x i16]* [[TMP0]]) #[[ATTR2]]
	// CHECK1-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 false)			// CHECK1-NEXT: call void @__kmpc_target_deinit(i1 false)
	// CHECK1-NEXT: ret void			// CHECK1-NEXT: ret void
	// CHECK1: worker.exit:			// CHECK1: worker.exit:
	// CHECK1-NEXT: ret void			// CHECK1-NEXT: ret void
	//			//
	//			//
	// CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__2			// CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__2
	// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i64 [[N:%.]], [1000 x i16]* nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR0]] {			// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i64 [[N:%.]], [1000 x i16]* nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR0]] {
	// CHECK1-NEXT: entry:			// CHECK1-NEXT: entry:
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	// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l39			// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l39
	// CHECK1-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {			// CHECK1-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
	// CHECK1-NEXT: entry:			// CHECK1-NEXT: entry:
	// CHECK1-NEXT: [[B_ADDR:%.]] = alloca [10 x i32], align 8			// CHECK1-NEXT: [[B_ADDR:%.]] = alloca [10 x i32], align 8
	// CHECK1-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			// CHECK1-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	// CHECK1-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4			// CHECK1-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
	// CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8			// CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
	// CHECK1-NEXT: [[TMP0:%.]] = load [10 x i32], [10 x i32]** [[B_ADDR]], align 8			// CHECK1-NEXT: [[TMP0:%.]] = load [10 x i32], [10 x i32]** [[B_ADDR]], align 8
	// CHECK1-NEXT: [[TMP1:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 2, i1 false, i1 false)			// CHECK1-NEXT: [[TMP1:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l39_kernel_info, i1 false)
	// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1			// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
	// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]			// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
	// CHECK1: user_code.entry:			// CHECK1: user_code.entry:
	// CHECK1-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB4]])			// CHECK1-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB4]])
	// CHECK1-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4			// CHECK1-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4			// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4
	// CHECK1-NEXT: call void @__omp_outlined__4(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], [10 x i32]* [[TMP0]]) #[[ATTR2]]			// CHECK1-NEXT: call void @__omp_outlined__4(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], [10 x i32]* [[TMP0]]) #[[ATTR2]]
	// CHECK1-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 false)			// CHECK1-NEXT: call void @__kmpc_target_deinit(i1 false)
	// CHECK1-NEXT: ret void			// CHECK1-NEXT: ret void
	// CHECK1: worker.exit:			// CHECK1: worker.exit:
	// CHECK1-NEXT: ret void			// CHECK1-NEXT: ret void
	//			//
	//			//
	// CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__4			// CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__4
	// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], [10 x i32] nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {			// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], [10 x i32] nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
	// CHECK1-NEXT: entry:			// CHECK1-NEXT: entry:
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	// CHECK1-NEXT: [[F_ADDR:%.*]] = alloca i64, align 8			// CHECK1-NEXT: [[F_ADDR:%.*]] = alloca i64, align 8
	// CHECK1-NEXT: [[F_CASTED:%.*]] = alloca i64, align 8			// CHECK1-NEXT: [[F_CASTED:%.*]] = alloca i64, align 8
	// CHECK1-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			// CHECK1-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	// CHECK1-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4			// CHECK1-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
	// CHECK1-NEXT: store [10 x [10 x i32]]* [[C]], [10 x [10 x i32]]** [[C_ADDR]], align 8			// CHECK1-NEXT: store [10 x [10 x i32]]* [[C]], [10 x [10 x i32]]** [[C_ADDR]], align 8
	// CHECK1-NEXT: store i64 [[F]], i64* [[F_ADDR]], align 8			// CHECK1-NEXT: store i64 [[F]], i64* [[F_ADDR]], align 8
	// CHECK1-NEXT: [[TMP0:%.]] = load [10 x [10 x i32]], [10 x [10 x i32]]** [[C_ADDR]], align 8			// CHECK1-NEXT: [[TMP0:%.]] = load [10 x [10 x i32]], [10 x [10 x i32]]** [[C_ADDR]], align 8
	// CHECK1-NEXT: [[CONV:%.]] = bitcast i64 [[F_ADDR]] to i32*			// CHECK1-NEXT: [[CONV:%.]] = bitcast i64 [[F_ADDR]] to i32*
	// CHECK1-NEXT: [[TMP1:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 2, i1 false, i1 false)			// CHECK1-NEXT: [[TMP1:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l44_kernel_info, i1 false)
	// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1			// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
	// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]			// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
	// CHECK1: user_code.entry:			// CHECK1: user_code.entry:
	// CHECK1-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB4]])			// CHECK1-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB4]])
	// CHECK1-NEXT: [[TMP3:%.]] = load i32, i32 [[CONV]], align 4			// CHECK1-NEXT: [[TMP3:%.]] = load i32, i32 [[CONV]], align 4
	// CHECK1-NEXT: [[CONV1:%.]] = bitcast i64 [[F_CASTED]] to i32*			// CHECK1-NEXT: [[CONV1:%.]] = bitcast i64 [[F_CASTED]] to i32*
	// CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4			// CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4
	// CHECK1-NEXT: [[TMP4:%.]] = load i64, i64 [[F_CASTED]], align 8			// CHECK1-NEXT: [[TMP4:%.]] = load i64, i64 [[F_CASTED]], align 8
	// CHECK1-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4			// CHECK1-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4			// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4
	// CHECK1-NEXT: call void @__omp_outlined__6(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], [10 x [10 x i32]]* [[TMP0]], i64 [[TMP4]]) #[[ATTR2]]			// CHECK1-NEXT: call void @__omp_outlined__6(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], [10 x [10 x i32]]* [[TMP0]], i64 [[TMP4]]) #[[ATTR2]]
	// CHECK1-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 false)			// CHECK1-NEXT: call void @__kmpc_target_deinit(i1 false)
	// CHECK1-NEXT: ret void			// CHECK1-NEXT: ret void
	// CHECK1: worker.exit:			// CHECK1: worker.exit:
	// CHECK1-NEXT: ret void			// CHECK1-NEXT: ret void
	//			//
	//			//
	// CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__6			// CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__6
	// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], [10 x [10 x i32]] nonnull align 4 dereferenceable(400) [[C:%.]], i64 [[F:%.]]) #[[ATTR0]] {			// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], [10 x [10 x i32]] nonnull align 4 dereferenceable(400) [[C:%.]], i64 [[F:%.]]) #[[ATTR0]] {
	// CHECK1-NEXT: entry:			// CHECK1-NEXT: entry:
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	// CHECK1-NEXT: [[C_ADDR:%.]] = alloca [10 x [10 x i32]], align 8			// CHECK1-NEXT: [[C_ADDR:%.]] = alloca [10 x [10 x i32]], align 8
	// CHECK1-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8			// CHECK1-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8
	// CHECK1-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			// CHECK1-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	// CHECK1-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4			// CHECK1-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
	// CHECK1-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8			// CHECK1-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
	// CHECK1-NEXT: store [10 x [10 x i32]]* [[C]], [10 x [10 x i32]]** [[C_ADDR]], align 8			// CHECK1-NEXT: store [10 x [10 x i32]]* [[C]], [10 x [10 x i32]]** [[C_ADDR]], align 8
	// CHECK1-NEXT: [[CONV:%.]] = bitcast i64 [[N_ADDR]] to i32*			// CHECK1-NEXT: [[CONV:%.]] = bitcast i64 [[N_ADDR]] to i32*
	// CHECK1-NEXT: [[TMP0:%.]] = load [10 x [10 x i32]], [10 x [10 x i32]]** [[C_ADDR]], align 8			// CHECK1-NEXT: [[TMP0:%.]] = load [10 x [10 x i32]], [10 x [10 x i32]]** [[C_ADDR]], align 8
	// CHECK1-NEXT: [[TMP1:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 2, i1 false, i1 false)			// CHECK1-NEXT: [[TMP1:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l52_kernel_info, i1 false)
	// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1			// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
	// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]			// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
	// CHECK1: user_code.entry:			// CHECK1: user_code.entry:
	// CHECK1-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB4]])			// CHECK1-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB4]])
	// CHECK1-NEXT: [[TMP3:%.]] = load i32, i32 [[CONV]], align 4			// CHECK1-NEXT: [[TMP3:%.]] = load i32, i32 [[CONV]], align 4
	// CHECK1-NEXT: [[CONV1:%.]] = bitcast i64 [[N_CASTED]] to i32*			// CHECK1-NEXT: [[CONV1:%.]] = bitcast i64 [[N_CASTED]] to i32*
	// CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4			// CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4
	// CHECK1-NEXT: [[TMP4:%.]] = load i64, i64 [[N_CASTED]], align 8			// CHECK1-NEXT: [[TMP4:%.]] = load i64, i64 [[N_CASTED]], align 8
	// CHECK1-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4			// CHECK1-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4			// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4
	// CHECK1-NEXT: call void @__omp_outlined__8(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i64 [[TMP4]], [10 x [10 x i32]]* [[TMP0]]) #[[ATTR2]]			// CHECK1-NEXT: call void @__omp_outlined__8(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i64 [[TMP4]], [10 x [10 x i32]]* [[TMP0]]) #[[ATTR2]]
	// CHECK1-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 false)			// CHECK1-NEXT: call void @__kmpc_target_deinit(i1 false)
	// CHECK1-NEXT: ret void			// CHECK1-NEXT: ret void
	// CHECK1: worker.exit:			// CHECK1: worker.exit:
	// CHECK1-NEXT: ret void			// CHECK1-NEXT: ret void
	//			//
	//			//
	// CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__8			// CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__8
	// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i64 [[N:%.]], [10 x [10 x i32]]* nonnull align 4 dereferenceable(400) [[C:%.*]]) #[[ATTR0]] {			// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i64 [[N:%.]], [10 x [10 x i32]]* nonnull align 4 dereferenceable(400) [[C:%.*]]) #[[ATTR0]] {
	// CHECK1-NEXT: entry:			// CHECK1-NEXT: entry:
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	// CHECK1-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8			// CHECK1-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8
	// CHECK1-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			// CHECK1-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	// CHECK1-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4			// CHECK1-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
	// CHECK1-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8			// CHECK1-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
	// CHECK1-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8			// CHECK1-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8
	// CHECK1-NEXT: store i32* [[V]], i32** [[V_ADDR]], align 8			// CHECK1-NEXT: store i32* [[V]], i32** [[V_ADDR]], align 8
	// CHECK1-NEXT: [[CONV:%.]] = bitcast i64 [[N_ADDR]] to i32*			// CHECK1-NEXT: [[CONV:%.]] = bitcast i64 [[N_ADDR]] to i32*
	// CHECK1-NEXT: [[TMP0:%.]] = load [1000 x i32], [1000 x i32]** [[A_ADDR]], align 8			// CHECK1-NEXT: [[TMP0:%.]] = load [1000 x i32], [1000 x i32]** [[A_ADDR]], align 8
	// CHECK1-NEXT: [[TMP1:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 2, i1 false, i1 false)			// CHECK1-NEXT: [[TMP1:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l59_kernel_info, i1 false)
	// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1			// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
	// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]			// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
	// CHECK1: user_code.entry:			// CHECK1: user_code.entry:
	// CHECK1-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB4]])			// CHECK1-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB4]])
	// CHECK1-NEXT: [[TMP3:%.]] = load i32, i32 [[CONV]], align 4			// CHECK1-NEXT: [[TMP3:%.]] = load i32, i32 [[CONV]], align 4
	// CHECK1-NEXT: [[CONV1:%.]] = bitcast i64 [[N_CASTED]] to i32*			// CHECK1-NEXT: [[CONV1:%.]] = bitcast i64 [[N_CASTED]] to i32*
	// CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4			// CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4
	// CHECK1-NEXT: [[TMP4:%.]] = load i64, i64 [[N_CASTED]], align 8			// CHECK1-NEXT: [[TMP4:%.]] = load i64, i64 [[N_CASTED]], align 8
	// CHECK1-NEXT: [[TMP5:%.]] = load i32, i32** [[V_ADDR]], align 8			// CHECK1-NEXT: [[TMP5:%.]] = load i32, i32** [[V_ADDR]], align 8
	// CHECK1-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4			// CHECK1-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4			// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4
	// CHECK1-NEXT: call void @__omp_outlined__10(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i64 [[TMP4]], [1000 x i32]* [[TMP0]], i32* [[TMP5]]) #[[ATTR2]]			// CHECK1-NEXT: call void @__omp_outlined__10(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i64 [[TMP4]], [1000 x i32]* [[TMP0]], i32* [[TMP5]]) #[[ATTR2]]
	// CHECK1-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 false)			// CHECK1-NEXT: call void @__kmpc_target_deinit(i1 false)
	// CHECK1-NEXT: ret void			// CHECK1-NEXT: ret void
	// CHECK1: worker.exit:			// CHECK1: worker.exit:
	// CHECK1-NEXT: ret void			// CHECK1-NEXT: ret void
	//			//
	//			//
	// CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__10			// CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__10
	// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i64 [[N:%.]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.]], i32 [[V:%.*]]) #[[ATTR0]] {			// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i64 [[N:%.]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.]], i32 [[V:%.*]]) #[[ATTR0]] {
	// CHECK1-NEXT: entry:			// CHECK1-NEXT: entry:
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	// CHECK2-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			// CHECK2-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	// CHECK2-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4			// CHECK2-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
	// CHECK2-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8			// CHECK2-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
	// CHECK2-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8			// CHECK2-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8
	// CHECK2-NEXT: store i64 [[L]], i64* [[L_ADDR]], align 8			// CHECK2-NEXT: store i64 [[L]], i64* [[L_ADDR]], align 8
	// CHECK2-NEXT: [[CONV:%.]] = bitcast i64 [[N_ADDR]] to i32*			// CHECK2-NEXT: [[CONV:%.]] = bitcast i64 [[N_ADDR]] to i32*
	// CHECK2-NEXT: [[TMP0:%.]] = load [1000 x i32], [1000 x i32]** [[A_ADDR]], align 8			// CHECK2-NEXT: [[TMP0:%.]] = load [1000 x i32], [1000 x i32]** [[A_ADDR]], align 8
	// CHECK2-NEXT: [[CONV1:%.]] = bitcast i64 [[L_ADDR]] to i32*			// CHECK2-NEXT: [[CONV1:%.]] = bitcast i64 [[L_ADDR]] to i32*
	// CHECK2-NEXT: [[TMP1:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1:[0-9]+]], i8 2, i1 false, i1 false)			// CHECK2-NEXT: [[TMP1:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l28_kernel_info, i1 false)
	// CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1			// CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
	// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]			// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
	// CHECK2: user_code.entry:			// CHECK2: user_code.entry:
	// CHECK2-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB4:[0-9]+]])			// CHECK2-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB4:[0-9]+]])
	// CHECK2-NEXT: [[TMP3:%.]] = load i32, i32 [[CONV]], align 4			// CHECK2-NEXT: [[TMP3:%.]] = load i32, i32 [[CONV]], align 4
	// CHECK2-NEXT: [[CONV2:%.]] = bitcast i64 [[N_CASTED]] to i32*			// CHECK2-NEXT: [[CONV2:%.]] = bitcast i64 [[N_CASTED]] to i32*
	// CHECK2-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4			// CHECK2-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
	// CHECK2-NEXT: [[TMP4:%.]] = load i64, i64 [[N_CASTED]], align 8			// CHECK2-NEXT: [[TMP4:%.]] = load i64, i64 [[N_CASTED]], align 8
	// CHECK2-NEXT: [[TMP5:%.]] = load i32, i32 [[CONV1]], align 4			// CHECK2-NEXT: [[TMP5:%.]] = load i32, i32 [[CONV1]], align 4
	// CHECK2-NEXT: [[CONV3:%.]] = bitcast i64 [[L_CASTED]] to i32*			// CHECK2-NEXT: [[CONV3:%.]] = bitcast i64 [[L_CASTED]] to i32*
	// CHECK2-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4			// CHECK2-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4
	// CHECK2-NEXT: [[TMP6:%.]] = load i64, i64 [[L_CASTED]], align 8			// CHECK2-NEXT: [[TMP6:%.]] = load i64, i64 [[L_CASTED]], align 8
	// CHECK2-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4			// CHECK2-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4			// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4
	// CHECK2-NEXT: call void @__omp_outlined__(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i64 [[TMP4]], [1000 x i32]* [[TMP0]], i64 [[TMP6]]) #[[ATTR2:[0-9]+]]			// CHECK2-NEXT: call void @__omp_outlined__(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i64 [[TMP4]], [1000 x i32]* [[TMP0]], i64 [[TMP6]]) #[[ATTR2:[0-9]+]]
	// CHECK2-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 false)			// CHECK2-NEXT: call void @__kmpc_target_deinit(i1 false)
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	// CHECK2: worker.exit:			// CHECK2: worker.exit:
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__			// CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__
	// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i64 [[N:%.]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.]], i64 [[L:%.]]) #[[ATTR0]] {			// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i64 [[N:%.]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.]], i64 [[L:%.]]) #[[ATTR0]] {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	▲ Show 20 Lines • Show All 290 Lines • ▼ Show 20 Lines
	// CHECK2-NEXT: [[AA_ADDR:%.]] = alloca [1000 x i16], align 8			// CHECK2-NEXT: [[AA_ADDR:%.]] = alloca [1000 x i16], align 8
	// CHECK2-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8			// CHECK2-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8
	// CHECK2-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			// CHECK2-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	// CHECK2-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4			// CHECK2-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
	// CHECK2-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8			// CHECK2-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
	// CHECK2-NEXT: store [1000 x i16]* [[AA]], [1000 x i16]** [[AA_ADDR]], align 8			// CHECK2-NEXT: store [1000 x i16]* [[AA]], [1000 x i16]** [[AA_ADDR]], align 8
	// CHECK2-NEXT: [[CONV:%.]] = bitcast i64 [[N_ADDR]] to i32*			// CHECK2-NEXT: [[CONV:%.]] = bitcast i64 [[N_ADDR]] to i32*
	// CHECK2-NEXT: [[TMP0:%.]] = load [1000 x i16], [1000 x i16]** [[AA_ADDR]], align 8			// CHECK2-NEXT: [[TMP0:%.]] = load [1000 x i16], [1000 x i16]** [[AA_ADDR]], align 8
	// CHECK2-NEXT: [[TMP1:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 2, i1 false, i1 false)			// CHECK2-NEXT: [[TMP1:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l34_kernel_info, i1 false)
	// CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1			// CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
	// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]			// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
	// CHECK2: user_code.entry:			// CHECK2: user_code.entry:
	// CHECK2-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB4]])			// CHECK2-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB4]])
	// CHECK2-NEXT: [[TMP3:%.]] = load i32, i32 [[CONV]], align 4			// CHECK2-NEXT: [[TMP3:%.]] = load i32, i32 [[CONV]], align 4
	// CHECK2-NEXT: [[CONV1:%.]] = bitcast i64 [[N_CASTED]] to i32*			// CHECK2-NEXT: [[CONV1:%.]] = bitcast i64 [[N_CASTED]] to i32*
	// CHECK2-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4			// CHECK2-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4
	// CHECK2-NEXT: [[TMP4:%.]] = load i64, i64 [[N_CASTED]], align 8			// CHECK2-NEXT: [[TMP4:%.]] = load i64, i64 [[N_CASTED]], align 8
	// CHECK2-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4			// CHECK2-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4			// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4
	// CHECK2-NEXT: call void @__omp_outlined__2(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i64 [[TMP4]], [1000 x i16]* [[TMP0]]) #[[ATTR2]]			// CHECK2-NEXT: call void @__omp_outlined__2(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i64 [[TMP4]], [1000 x i16]* [[TMP0]]) #[[ATTR2]]
	// CHECK2-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 false)			// CHECK2-NEXT: call void @__kmpc_target_deinit(i1 false)
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	// CHECK2: worker.exit:			// CHECK2: worker.exit:
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__2			// CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__2
	// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i64 [[N:%.]], [1000 x i16]* nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR0]] {			// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i64 [[N:%.]], [1000 x i16]* nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR0]] {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	▲ Show 20 Lines • Show All 226 Lines • ▼ Show 20 Lines
	// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l39			// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l39
	// CHECK2-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {			// CHECK2-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	// CHECK2-NEXT: [[B_ADDR:%.]] = alloca [10 x i32], align 8			// CHECK2-NEXT: [[B_ADDR:%.]] = alloca [10 x i32], align 8
	// CHECK2-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			// CHECK2-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	// CHECK2-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4			// CHECK2-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
	// CHECK2-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8			// CHECK2-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
	// CHECK2-NEXT: [[TMP0:%.]] = load [10 x i32], [10 x i32]** [[B_ADDR]], align 8			// CHECK2-NEXT: [[TMP0:%.]] = load [10 x i32], [10 x i32]** [[B_ADDR]], align 8
	// CHECK2-NEXT: [[TMP1:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 2, i1 false, i1 false)			// CHECK2-NEXT: [[TMP1:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l39_kernel_info, i1 false)
	// CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1			// CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
	// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]			// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
	// CHECK2: user_code.entry:			// CHECK2: user_code.entry:
	// CHECK2-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB4]])			// CHECK2-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB4]])
	// CHECK2-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4			// CHECK2-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4			// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4
	// CHECK2-NEXT: call void @__omp_outlined__4(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], [10 x i32]* [[TMP0]]) #[[ATTR2]]			// CHECK2-NEXT: call void @__omp_outlined__4(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], [10 x i32]* [[TMP0]]) #[[ATTR2]]
	// CHECK2-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 false)			// CHECK2-NEXT: call void @__kmpc_target_deinit(i1 false)
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	// CHECK2: worker.exit:			// CHECK2: worker.exit:
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__4			// CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__4
	// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], [10 x i32] nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {			// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], [10 x i32] nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	▲ Show 20 Lines • Show All 166 Lines • ▼ Show 20 Lines
	// CHECK2-NEXT: [[F_ADDR:%.*]] = alloca i64, align 8			// CHECK2-NEXT: [[F_ADDR:%.*]] = alloca i64, align 8
	// CHECK2-NEXT: [[F_CASTED:%.*]] = alloca i64, align 8			// CHECK2-NEXT: [[F_CASTED:%.*]] = alloca i64, align 8
	// CHECK2-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			// CHECK2-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	// CHECK2-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4			// CHECK2-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
	// CHECK2-NEXT: store [10 x [10 x i32]]* [[C]], [10 x [10 x i32]]** [[C_ADDR]], align 8			// CHECK2-NEXT: store [10 x [10 x i32]]* [[C]], [10 x [10 x i32]]** [[C_ADDR]], align 8
	// CHECK2-NEXT: store i64 [[F]], i64* [[F_ADDR]], align 8			// CHECK2-NEXT: store i64 [[F]], i64* [[F_ADDR]], align 8
	// CHECK2-NEXT: [[TMP0:%.]] = load [10 x [10 x i32]], [10 x [10 x i32]]** [[C_ADDR]], align 8			// CHECK2-NEXT: [[TMP0:%.]] = load [10 x [10 x i32]], [10 x [10 x i32]]** [[C_ADDR]], align 8
	// CHECK2-NEXT: [[CONV:%.]] = bitcast i64 [[F_ADDR]] to i32*			// CHECK2-NEXT: [[CONV:%.]] = bitcast i64 [[F_ADDR]] to i32*
	// CHECK2-NEXT: [[TMP1:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 2, i1 false, i1 false)			// CHECK2-NEXT: [[TMP1:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l44_kernel_info, i1 false)
	// CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1			// CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
	// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]			// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
	// CHECK2: user_code.entry:			// CHECK2: user_code.entry:
	// CHECK2-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB4]])			// CHECK2-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB4]])
	// CHECK2-NEXT: [[TMP3:%.]] = load i32, i32 [[CONV]], align 4			// CHECK2-NEXT: [[TMP3:%.]] = load i32, i32 [[CONV]], align 4
	// CHECK2-NEXT: [[CONV1:%.]] = bitcast i64 [[F_CASTED]] to i32*			// CHECK2-NEXT: [[CONV1:%.]] = bitcast i64 [[F_CASTED]] to i32*
	// CHECK2-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4			// CHECK2-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4
	// CHECK2-NEXT: [[TMP4:%.]] = load i64, i64 [[F_CASTED]], align 8			// CHECK2-NEXT: [[TMP4:%.]] = load i64, i64 [[F_CASTED]], align 8
	// CHECK2-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4			// CHECK2-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4			// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4
	// CHECK2-NEXT: call void @__omp_outlined__6(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], [10 x [10 x i32]]* [[TMP0]], i64 [[TMP4]]) #[[ATTR2]]			// CHECK2-NEXT: call void @__omp_outlined__6(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], [10 x [10 x i32]]* [[TMP0]], i64 [[TMP4]]) #[[ATTR2]]
	// CHECK2-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 false)			// CHECK2-NEXT: call void @__kmpc_target_deinit(i1 false)
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	// CHECK2: worker.exit:			// CHECK2: worker.exit:
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__6			// CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__6
	// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], [10 x [10 x i32]] nonnull align 4 dereferenceable(400) [[C:%.]], i64 [[F:%.]]) #[[ATTR0]] {			// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], [10 x [10 x i32]] nonnull align 4 dereferenceable(400) [[C:%.]], i64 [[F:%.]]) #[[ATTR0]] {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	▲ Show 20 Lines • Show All 204 Lines • ▼ Show 20 Lines
	// CHECK2-NEXT: [[C_ADDR:%.]] = alloca [10 x [10 x i32]], align 8			// CHECK2-NEXT: [[C_ADDR:%.]] = alloca [10 x [10 x i32]], align 8
	// CHECK2-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8			// CHECK2-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8
	// CHECK2-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			// CHECK2-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	// CHECK2-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4			// CHECK2-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
	// CHECK2-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8			// CHECK2-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
	// CHECK2-NEXT: store [10 x [10 x i32]]* [[C]], [10 x [10 x i32]]** [[C_ADDR]], align 8			// CHECK2-NEXT: store [10 x [10 x i32]]* [[C]], [10 x [10 x i32]]** [[C_ADDR]], align 8
	// CHECK2-NEXT: [[CONV:%.]] = bitcast i64 [[N_ADDR]] to i32*			// CHECK2-NEXT: [[CONV:%.]] = bitcast i64 [[N_ADDR]] to i32*
	// CHECK2-NEXT: [[TMP0:%.]] = load [10 x [10 x i32]], [10 x [10 x i32]]** [[C_ADDR]], align 8			// CHECK2-NEXT: [[TMP0:%.]] = load [10 x [10 x i32]], [10 x [10 x i32]]** [[C_ADDR]], align 8
	// CHECK2-NEXT: [[TMP1:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 2, i1 false, i1 false)			// CHECK2-NEXT: [[TMP1:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l52_kernel_info, i1 false)
	// CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1			// CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
	// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]			// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
	// CHECK2: user_code.entry:			// CHECK2: user_code.entry:
	// CHECK2-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB4]])			// CHECK2-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB4]])
	// CHECK2-NEXT: [[TMP3:%.]] = load i32, i32 [[CONV]], align 4			// CHECK2-NEXT: [[TMP3:%.]] = load i32, i32 [[CONV]], align 4
	// CHECK2-NEXT: [[CONV1:%.]] = bitcast i64 [[N_CASTED]] to i32*			// CHECK2-NEXT: [[CONV1:%.]] = bitcast i64 [[N_CASTED]] to i32*
	// CHECK2-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4			// CHECK2-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4
	// CHECK2-NEXT: [[TMP4:%.]] = load i64, i64 [[N_CASTED]], align 8			// CHECK2-NEXT: [[TMP4:%.]] = load i64, i64 [[N_CASTED]], align 8
	// CHECK2-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4			// CHECK2-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4			// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4
	// CHECK2-NEXT: call void @__omp_outlined__8(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i64 [[TMP4]], [10 x [10 x i32]]* [[TMP0]]) #[[ATTR2]]			// CHECK2-NEXT: call void @__omp_outlined__8(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i64 [[TMP4]], [10 x [10 x i32]]* [[TMP0]]) #[[ATTR2]]
	// CHECK2-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 false)			// CHECK2-NEXT: call void @__kmpc_target_deinit(i1 false)
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	// CHECK2: worker.exit:			// CHECK2: worker.exit:
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__8			// CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__8
	// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i64 [[N:%.]], [10 x [10 x i32]]* nonnull align 4 dereferenceable(400) [[C:%.*]]) #[[ATTR0]] {			// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i64 [[N:%.]], [10 x [10 x i32]]* nonnull align 4 dereferenceable(400) [[C:%.*]]) #[[ATTR0]] {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
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	// CHECK2-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8			// CHECK2-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8
	// CHECK2-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			// CHECK2-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	// CHECK2-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4			// CHECK2-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
	// CHECK2-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8			// CHECK2-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
	// CHECK2-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8			// CHECK2-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8
	// CHECK2-NEXT: store i32* [[V]], i32** [[V_ADDR]], align 8			// CHECK2-NEXT: store i32* [[V]], i32** [[V_ADDR]], align 8
	// CHECK2-NEXT: [[CONV:%.]] = bitcast i64 [[N_ADDR]] to i32*			// CHECK2-NEXT: [[CONV:%.]] = bitcast i64 [[N_ADDR]] to i32*
	// CHECK2-NEXT: [[TMP0:%.]] = load [1000 x i32], [1000 x i32]** [[A_ADDR]], align 8			// CHECK2-NEXT: [[TMP0:%.]] = load [1000 x i32], [1000 x i32]** [[A_ADDR]], align 8
	// CHECK2-NEXT: [[TMP1:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 2, i1 false, i1 false)			// CHECK2-NEXT: [[TMP1:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l59_kernel_info, i1 false)
	// CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1			// CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
	// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]			// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
	// CHECK2: user_code.entry:			// CHECK2: user_code.entry:
	// CHECK2-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB4]])			// CHECK2-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB4]])
	// CHECK2-NEXT: [[TMP3:%.]] = load i32, i32 [[CONV]], align 4			// CHECK2-NEXT: [[TMP3:%.]] = load i32, i32 [[CONV]], align 4
	// CHECK2-NEXT: [[CONV1:%.]] = bitcast i64 [[N_CASTED]] to i32*			// CHECK2-NEXT: [[CONV1:%.]] = bitcast i64 [[N_CASTED]] to i32*
	// CHECK2-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4			// CHECK2-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4
	// CHECK2-NEXT: [[TMP4:%.]] = load i64, i64 [[N_CASTED]], align 8			// CHECK2-NEXT: [[TMP4:%.]] = load i64, i64 [[N_CASTED]], align 8
	// CHECK2-NEXT: [[TMP5:%.]] = load i32, i32** [[V_ADDR]], align 8			// CHECK2-NEXT: [[TMP5:%.]] = load i32, i32** [[V_ADDR]], align 8
	// CHECK2-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4			// CHECK2-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4			// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4
	// CHECK2-NEXT: call void @__omp_outlined__10(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i64 [[TMP4]], [1000 x i32]* [[TMP0]], i32* [[TMP5]]) #[[ATTR2]]			// CHECK2-NEXT: call void @__omp_outlined__10(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i64 [[TMP4]], [1000 x i32]* [[TMP0]], i32* [[TMP5]]) #[[ATTR2]]
	// CHECK2-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 false)			// CHECK2-NEXT: call void @__kmpc_target_deinit(i1 false)
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	// CHECK2: worker.exit:			// CHECK2: worker.exit:
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__10			// CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__10
	// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i64 [[N:%.]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.]], i32 [[V:%.*]]) #[[ATTR0]] {			// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i64 [[N:%.]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.]], i32 [[V:%.*]]) #[[ATTR0]] {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
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	// CHECK3-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4			// CHECK3-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4
	// CHECK3-NEXT: [[L_CASTED:%.*]] = alloca i32, align 4			// CHECK3-NEXT: [[L_CASTED:%.*]] = alloca i32, align 4
	// CHECK3-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			// CHECK3-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	// CHECK3-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4			// CHECK3-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
	// CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4			// CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
	// CHECK3-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 4			// CHECK3-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 4
	// CHECK3-NEXT: store i32 [[L]], i32* [[L_ADDR]], align 4			// CHECK3-NEXT: store i32 [[L]], i32* [[L_ADDR]], align 4
	// CHECK3-NEXT: [[TMP0:%.]] = load [1000 x i32], [1000 x i32]** [[A_ADDR]], align 4			// CHECK3-NEXT: [[TMP0:%.]] = load [1000 x i32], [1000 x i32]** [[A_ADDR]], align 4
	// CHECK3-NEXT: [[TMP1:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1:[0-9]+]], i8 2, i1 false, i1 false)			// CHECK3-NEXT: [[TMP1:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l28_kernel_info, i1 false)
	// CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1			// CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
	// CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]			// CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
	// CHECK3: user_code.entry:			// CHECK3: user_code.entry:
	// CHECK3-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB4:[0-9]+]])			// CHECK3-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB4:[0-9]+]])
	// CHECK3-NEXT: [[TMP3:%.]] = load i32, i32 [[N_ADDR]], align 4			// CHECK3-NEXT: [[TMP3:%.]] = load i32, i32 [[N_ADDR]], align 4
	// CHECK3-NEXT: store i32 [[TMP3]], i32* [[N_CASTED]], align 4			// CHECK3-NEXT: store i32 [[TMP3]], i32* [[N_CASTED]], align 4
	// CHECK3-NEXT: [[TMP4:%.]] = load i32, i32 [[N_CASTED]], align 4			// CHECK3-NEXT: [[TMP4:%.]] = load i32, i32 [[N_CASTED]], align 4
	// CHECK3-NEXT: [[TMP5:%.]] = load i32, i32 [[L_ADDR]], align 4			// CHECK3-NEXT: [[TMP5:%.]] = load i32, i32 [[L_ADDR]], align 4
	// CHECK3-NEXT: store i32 [[TMP5]], i32* [[L_CASTED]], align 4			// CHECK3-NEXT: store i32 [[TMP5]], i32* [[L_CASTED]], align 4
	// CHECK3-NEXT: [[TMP6:%.]] = load i32, i32 [[L_CASTED]], align 4			// CHECK3-NEXT: [[TMP6:%.]] = load i32, i32 [[L_CASTED]], align 4
	// CHECK3-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4			// CHECK3-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	// CHECK3-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4			// CHECK3-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4
	// CHECK3-NEXT: call void @__omp_outlined__(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i32 [[TMP4]], [1000 x i32]* [[TMP0]], i32 [[TMP6]]) #[[ATTR2:[0-9]+]]			// CHECK3-NEXT: call void @__omp_outlined__(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i32 [[TMP4]], [1000 x i32]* [[TMP0]], i32 [[TMP6]]) #[[ATTR2:[0-9]+]]
	// CHECK3-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 false)			// CHECK3-NEXT: call void @__kmpc_target_deinit(i1 false)
	// CHECK3-NEXT: ret void			// CHECK3-NEXT: ret void
	// CHECK3: worker.exit:			// CHECK3: worker.exit:
	// CHECK3-NEXT: ret void			// CHECK3-NEXT: ret void
	//			//
	//			//
	// CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__			// CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__
	// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i32 [[N:%.]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.]], i32 [[L:%.]]) #[[ATTR0]] {			// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i32 [[N:%.]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.]], i32 [[L:%.]]) #[[ATTR0]] {
	// CHECK3-NEXT: entry:			// CHECK3-NEXT: entry:
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	// CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4			// CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
	// CHECK3-NEXT: [[AA_ADDR:%.]] = alloca [1000 x i16], align 4			// CHECK3-NEXT: [[AA_ADDR:%.]] = alloca [1000 x i16], align 4
	// CHECK3-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4			// CHECK3-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4
	// CHECK3-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			// CHECK3-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	// CHECK3-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4			// CHECK3-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
	// CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4			// CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
	// CHECK3-NEXT: store [1000 x i16]* [[AA]], [1000 x i16]** [[AA_ADDR]], align 4			// CHECK3-NEXT: store [1000 x i16]* [[AA]], [1000 x i16]** [[AA_ADDR]], align 4
	// CHECK3-NEXT: [[TMP0:%.]] = load [1000 x i16], [1000 x i16]** [[AA_ADDR]], align 4			// CHECK3-NEXT: [[TMP0:%.]] = load [1000 x i16], [1000 x i16]** [[AA_ADDR]], align 4
	// CHECK3-NEXT: [[TMP1:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 2, i1 false, i1 false)			// CHECK3-NEXT: [[TMP1:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l34_kernel_info, i1 false)
	// CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1			// CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
	// CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]			// CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
	// CHECK3: user_code.entry:			// CHECK3: user_code.entry:
	// CHECK3-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB4]])			// CHECK3-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB4]])
	// CHECK3-NEXT: [[TMP3:%.]] = load i32, i32 [[N_ADDR]], align 4			// CHECK3-NEXT: [[TMP3:%.]] = load i32, i32 [[N_ADDR]], align 4
	// CHECK3-NEXT: store i32 [[TMP3]], i32* [[N_CASTED]], align 4			// CHECK3-NEXT: store i32 [[TMP3]], i32* [[N_CASTED]], align 4
	// CHECK3-NEXT: [[TMP4:%.]] = load i32, i32 [[N_CASTED]], align 4			// CHECK3-NEXT: [[TMP4:%.]] = load i32, i32 [[N_CASTED]], align 4
	// CHECK3-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4			// CHECK3-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	// CHECK3-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4			// CHECK3-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4
	// CHECK3-NEXT: call void @__omp_outlined__2(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i32 [[TMP4]], [1000 x i16]* [[TMP0]]) #[[ATTR2]]			// CHECK3-NEXT: call void @__omp_outlined__2(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i32 [[TMP4]], [1000 x i16]* [[TMP0]]) #[[ATTR2]]
	// CHECK3-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 false)			// CHECK3-NEXT: call void @__kmpc_target_deinit(i1 false)
	// CHECK3-NEXT: ret void			// CHECK3-NEXT: ret void
	// CHECK3: worker.exit:			// CHECK3: worker.exit:
	// CHECK3-NEXT: ret void			// CHECK3-NEXT: ret void
	//			//
	//			//
	// CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__2			// CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__2
	// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i32 [[N:%.]], [1000 x i16]* nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR0]] {			// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i32 [[N:%.]], [1000 x i16]* nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR0]] {
	// CHECK3-NEXT: entry:			// CHECK3-NEXT: entry:
	▲ Show 20 Lines • Show All 217 Lines • ▼ Show 20 Lines
	// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l39			// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l39
	// CHECK3-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {			// CHECK3-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
	// CHECK3-NEXT: entry:			// CHECK3-NEXT: entry:
	// CHECK3-NEXT: [[B_ADDR:%.]] = alloca [10 x i32], align 4			// CHECK3-NEXT: [[B_ADDR:%.]] = alloca [10 x i32], align 4
	// CHECK3-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			// CHECK3-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	// CHECK3-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4			// CHECK3-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
	// CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4			// CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
	// CHECK3-NEXT: [[TMP0:%.]] = load [10 x i32], [10 x i32]** [[B_ADDR]], align 4			// CHECK3-NEXT: [[TMP0:%.]] = load [10 x i32], [10 x i32]** [[B_ADDR]], align 4
	// CHECK3-NEXT: [[TMP1:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 2, i1 false, i1 false)			// CHECK3-NEXT: [[TMP1:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l39_kernel_info, i1 false)
	// CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1			// CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
	// CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]			// CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
	// CHECK3: user_code.entry:			// CHECK3: user_code.entry:
	// CHECK3-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB4]])			// CHECK3-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB4]])
	// CHECK3-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4			// CHECK3-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	// CHECK3-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4			// CHECK3-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4
	// CHECK3-NEXT: call void @__omp_outlined__4(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], [10 x i32]* [[TMP0]]) #[[ATTR2]]			// CHECK3-NEXT: call void @__omp_outlined__4(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], [10 x i32]* [[TMP0]]) #[[ATTR2]]
	// CHECK3-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 false)			// CHECK3-NEXT: call void @__kmpc_target_deinit(i1 false)
	// CHECK3-NEXT: ret void			// CHECK3-NEXT: ret void
	// CHECK3: worker.exit:			// CHECK3: worker.exit:
	// CHECK3-NEXT: ret void			// CHECK3-NEXT: ret void
	//			//
	//			//
	// CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__4			// CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__4
	// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], [10 x i32] nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {			// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], [10 x i32] nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
	// CHECK3-NEXT: entry:			// CHECK3-NEXT: entry:
	▲ Show 20 Lines • Show All 159 Lines • ▼ Show 20 Lines
	// CHECK3-NEXT: [[C_ADDR:%.]] = alloca [10 x [10 x i32]], align 4			// CHECK3-NEXT: [[C_ADDR:%.]] = alloca [10 x [10 x i32]], align 4
	// CHECK3-NEXT: [[F_ADDR:%.*]] = alloca i32, align 4			// CHECK3-NEXT: [[F_ADDR:%.*]] = alloca i32, align 4
	// CHECK3-NEXT: [[F_CASTED:%.*]] = alloca i32, align 4			// CHECK3-NEXT: [[F_CASTED:%.*]] = alloca i32, align 4
	// CHECK3-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			// CHECK3-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	// CHECK3-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4			// CHECK3-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
	// CHECK3-NEXT: store [10 x [10 x i32]]* [[C]], [10 x [10 x i32]]** [[C_ADDR]], align 4			// CHECK3-NEXT: store [10 x [10 x i32]]* [[C]], [10 x [10 x i32]]** [[C_ADDR]], align 4
	// CHECK3-NEXT: store i32 [[F]], i32* [[F_ADDR]], align 4			// CHECK3-NEXT: store i32 [[F]], i32* [[F_ADDR]], align 4
	// CHECK3-NEXT: [[TMP0:%.]] = load [10 x [10 x i32]], [10 x [10 x i32]]** [[C_ADDR]], align 4			// CHECK3-NEXT: [[TMP0:%.]] = load [10 x [10 x i32]], [10 x [10 x i32]]** [[C_ADDR]], align 4
	// CHECK3-NEXT: [[TMP1:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 2, i1 false, i1 false)			// CHECK3-NEXT: [[TMP1:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l44_kernel_info, i1 false)
	// CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1			// CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
	// CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]			// CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
	// CHECK3: user_code.entry:			// CHECK3: user_code.entry:
	// CHECK3-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB4]])			// CHECK3-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB4]])
	// CHECK3-NEXT: [[TMP3:%.]] = load i32, i32 [[F_ADDR]], align 4			// CHECK3-NEXT: [[TMP3:%.]] = load i32, i32 [[F_ADDR]], align 4
	// CHECK3-NEXT: store i32 [[TMP3]], i32* [[F_CASTED]], align 4			// CHECK3-NEXT: store i32 [[TMP3]], i32* [[F_CASTED]], align 4
	// CHECK3-NEXT: [[TMP4:%.]] = load i32, i32 [[F_CASTED]], align 4			// CHECK3-NEXT: [[TMP4:%.]] = load i32, i32 [[F_CASTED]], align 4
	// CHECK3-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4			// CHECK3-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	// CHECK3-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4			// CHECK3-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4
	// CHECK3-NEXT: call void @__omp_outlined__6(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], [10 x [10 x i32]]* [[TMP0]], i32 [[TMP4]]) #[[ATTR2]]			// CHECK3-NEXT: call void @__omp_outlined__6(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], [10 x [10 x i32]]* [[TMP0]], i32 [[TMP4]]) #[[ATTR2]]
	// CHECK3-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 false)			// CHECK3-NEXT: call void @__kmpc_target_deinit(i1 false)
	// CHECK3-NEXT: ret void			// CHECK3-NEXT: ret void
	// CHECK3: worker.exit:			// CHECK3: worker.exit:
	// CHECK3-NEXT: ret void			// CHECK3-NEXT: ret void
	//			//
	//			//
	// CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__6			// CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__6
	// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], [10 x [10 x i32]] nonnull align 4 dereferenceable(400) [[C:%.]], i32 [[F:%.]]) #[[ATTR0]] {			// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], [10 x [10 x i32]] nonnull align 4 dereferenceable(400) [[C:%.]], i32 [[F:%.]]) #[[ATTR0]] {
	// CHECK3-NEXT: entry:			// CHECK3-NEXT: entry:
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	// CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4			// CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
	// CHECK3-NEXT: [[C_ADDR:%.]] = alloca [10 x [10 x i32]], align 4			// CHECK3-NEXT: [[C_ADDR:%.]] = alloca [10 x [10 x i32]], align 4
	// CHECK3-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4			// CHECK3-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4
	// CHECK3-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			// CHECK3-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	// CHECK3-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4			// CHECK3-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
	// CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4			// CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
	// CHECK3-NEXT: store [10 x [10 x i32]]* [[C]], [10 x [10 x i32]]** [[C_ADDR]], align 4			// CHECK3-NEXT: store [10 x [10 x i32]]* [[C]], [10 x [10 x i32]]** [[C_ADDR]], align 4
	// CHECK3-NEXT: [[TMP0:%.]] = load [10 x [10 x i32]], [10 x [10 x i32]]** [[C_ADDR]], align 4			// CHECK3-NEXT: [[TMP0:%.]] = load [10 x [10 x i32]], [10 x [10 x i32]]** [[C_ADDR]], align 4
	// CHECK3-NEXT: [[TMP1:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 2, i1 false, i1 false)			// CHECK3-NEXT: [[TMP1:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l52_kernel_info, i1 false)
	// CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1			// CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
	// CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]			// CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
	// CHECK3: user_code.entry:			// CHECK3: user_code.entry:
	// CHECK3-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB4]])			// CHECK3-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB4]])
	// CHECK3-NEXT: [[TMP3:%.]] = load i32, i32 [[N_ADDR]], align 4			// CHECK3-NEXT: [[TMP3:%.]] = load i32, i32 [[N_ADDR]], align 4
	// CHECK3-NEXT: store i32 [[TMP3]], i32* [[N_CASTED]], align 4			// CHECK3-NEXT: store i32 [[TMP3]], i32* [[N_CASTED]], align 4
	// CHECK3-NEXT: [[TMP4:%.]] = load i32, i32 [[N_CASTED]], align 4			// CHECK3-NEXT: [[TMP4:%.]] = load i32, i32 [[N_CASTED]], align 4
	// CHECK3-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4			// CHECK3-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	// CHECK3-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4			// CHECK3-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4
	// CHECK3-NEXT: call void @__omp_outlined__8(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i32 [[TMP4]], [10 x [10 x i32]]* [[TMP0]]) #[[ATTR2]]			// CHECK3-NEXT: call void @__omp_outlined__8(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i32 [[TMP4]], [10 x [10 x i32]]* [[TMP0]]) #[[ATTR2]]
	// CHECK3-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 false)			// CHECK3-NEXT: call void @__kmpc_target_deinit(i1 false)
	// CHECK3-NEXT: ret void			// CHECK3-NEXT: ret void
	// CHECK3: worker.exit:			// CHECK3: worker.exit:
	// CHECK3-NEXT: ret void			// CHECK3-NEXT: ret void
	//			//
	//			//
	// CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__8			// CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__8
	// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i32 [[N:%.]], [10 x [10 x i32]]* nonnull align 4 dereferenceable(400) [[C:%.*]]) #[[ATTR0]] {			// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i32 [[N:%.]], [10 x [10 x i32]]* nonnull align 4 dereferenceable(400) [[C:%.*]]) #[[ATTR0]] {
	// CHECK3-NEXT: entry:			// CHECK3-NEXT: entry:
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	// CHECK3-NEXT: [[V_ADDR:%.]] = alloca i32, align 4			// CHECK3-NEXT: [[V_ADDR:%.]] = alloca i32, align 4
	// CHECK3-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4			// CHECK3-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4
	// CHECK3-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			// CHECK3-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	// CHECK3-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4			// CHECK3-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
	// CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4			// CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
	// CHECK3-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 4			// CHECK3-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 4
	// CHECK3-NEXT: store i32* [[V]], i32** [[V_ADDR]], align 4			// CHECK3-NEXT: store i32* [[V]], i32** [[V_ADDR]], align 4
	// CHECK3-NEXT: [[TMP0:%.]] = load [1000 x i32], [1000 x i32]** [[A_ADDR]], align 4			// CHECK3-NEXT: [[TMP0:%.]] = load [1000 x i32], [1000 x i32]** [[A_ADDR]], align 4
	// CHECK3-NEXT: [[TMP1:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 2, i1 false, i1 false)			// CHECK3-NEXT: [[TMP1:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l59_kernel_info, i1 false)
	// CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1			// CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
	// CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]			// CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
	// CHECK3: user_code.entry:			// CHECK3: user_code.entry:
	// CHECK3-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB4]])			// CHECK3-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB4]])
	// CHECK3-NEXT: [[TMP3:%.]] = load i32, i32 [[N_ADDR]], align 4			// CHECK3-NEXT: [[TMP3:%.]] = load i32, i32 [[N_ADDR]], align 4
	// CHECK3-NEXT: store i32 [[TMP3]], i32* [[N_CASTED]], align 4			// CHECK3-NEXT: store i32 [[TMP3]], i32* [[N_CASTED]], align 4
	// CHECK3-NEXT: [[TMP4:%.]] = load i32, i32 [[N_CASTED]], align 4			// CHECK3-NEXT: [[TMP4:%.]] = load i32, i32 [[N_CASTED]], align 4
	// CHECK3-NEXT: [[TMP5:%.]] = load i32, i32** [[V_ADDR]], align 4			// CHECK3-NEXT: [[TMP5:%.]] = load i32, i32** [[V_ADDR]], align 4
	// CHECK3-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4			// CHECK3-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	// CHECK3-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4			// CHECK3-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4
	// CHECK3-NEXT: call void @__omp_outlined__10(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i32 [[TMP4]], [1000 x i32]* [[TMP0]], i32* [[TMP5]]) #[[ATTR2]]			// CHECK3-NEXT: call void @__omp_outlined__10(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i32 [[TMP4]], [1000 x i32]* [[TMP0]], i32* [[TMP5]]) #[[ATTR2]]
	// CHECK3-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 false)			// CHECK3-NEXT: call void @__kmpc_target_deinit(i1 false)
	// CHECK3-NEXT: ret void			// CHECK3-NEXT: ret void
	// CHECK3: worker.exit:			// CHECK3: worker.exit:
	// CHECK3-NEXT: ret void			// CHECK3-NEXT: ret void
	//			//
	//			//
	// CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__10			// CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__10
	// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i32 [[N:%.]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.]], i32 [[V:%.*]]) #[[ATTR0]] {			// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i32 [[N:%.]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.]], i32 [[V:%.*]]) #[[ATTR0]] {
	// CHECK3-NEXT: entry:			// CHECK3-NEXT: entry:
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	// CHECK4-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4			// CHECK4-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4
	// CHECK4-NEXT: [[L_CASTED:%.*]] = alloca i32, align 4			// CHECK4-NEXT: [[L_CASTED:%.*]] = alloca i32, align 4
	// CHECK4-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			// CHECK4-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	// CHECK4-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4			// CHECK4-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
	// CHECK4-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4			// CHECK4-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
	// CHECK4-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 4			// CHECK4-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 4
	// CHECK4-NEXT: store i32 [[L]], i32* [[L_ADDR]], align 4			// CHECK4-NEXT: store i32 [[L]], i32* [[L_ADDR]], align 4
	// CHECK4-NEXT: [[TMP0:%.]] = load [1000 x i32], [1000 x i32]** [[A_ADDR]], align 4			// CHECK4-NEXT: [[TMP0:%.]] = load [1000 x i32], [1000 x i32]** [[A_ADDR]], align 4
	// CHECK4-NEXT: [[TMP1:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1:[0-9]+]], i8 2, i1 false, i1 false)			// CHECK4-NEXT: [[TMP1:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l28_kernel_info, i1 false)
	// CHECK4-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1			// CHECK4-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
	// CHECK4-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]			// CHECK4-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
	// CHECK4: user_code.entry:			// CHECK4: user_code.entry:
	// CHECK4-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB4:[0-9]+]])			// CHECK4-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB4:[0-9]+]])
	// CHECK4-NEXT: [[TMP3:%.]] = load i32, i32 [[N_ADDR]], align 4			// CHECK4-NEXT: [[TMP3:%.]] = load i32, i32 [[N_ADDR]], align 4
	// CHECK4-NEXT: store i32 [[TMP3]], i32* [[N_CASTED]], align 4			// CHECK4-NEXT: store i32 [[TMP3]], i32* [[N_CASTED]], align 4
	// CHECK4-NEXT: [[TMP4:%.]] = load i32, i32 [[N_CASTED]], align 4			// CHECK4-NEXT: [[TMP4:%.]] = load i32, i32 [[N_CASTED]], align 4
	// CHECK4-NEXT: [[TMP5:%.]] = load i32, i32 [[L_ADDR]], align 4			// CHECK4-NEXT: [[TMP5:%.]] = load i32, i32 [[L_ADDR]], align 4
	// CHECK4-NEXT: store i32 [[TMP5]], i32* [[L_CASTED]], align 4			// CHECK4-NEXT: store i32 [[TMP5]], i32* [[L_CASTED]], align 4
	// CHECK4-NEXT: [[TMP6:%.]] = load i32, i32 [[L_CASTED]], align 4			// CHECK4-NEXT: [[TMP6:%.]] = load i32, i32 [[L_CASTED]], align 4
	// CHECK4-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4			// CHECK4-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	// CHECK4-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4			// CHECK4-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4
	// CHECK4-NEXT: call void @__omp_outlined__(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i32 [[TMP4]], [1000 x i32]* [[TMP0]], i32 [[TMP6]]) #[[ATTR2:[0-9]+]]			// CHECK4-NEXT: call void @__omp_outlined__(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i32 [[TMP4]], [1000 x i32]* [[TMP0]], i32 [[TMP6]]) #[[ATTR2:[0-9]+]]
	// CHECK4-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 false)			// CHECK4-NEXT: call void @__kmpc_target_deinit(i1 false)
	// CHECK4-NEXT: ret void			// CHECK4-NEXT: ret void
	// CHECK4: worker.exit:			// CHECK4: worker.exit:
	// CHECK4-NEXT: ret void			// CHECK4-NEXT: ret void
	//			//
	//			//
	// CHECK4-LABEL: define {{[^@]+}}@__omp_outlined__			// CHECK4-LABEL: define {{[^@]+}}@__omp_outlined__
	// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i32 [[N:%.]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.]], i32 [[L:%.]]) #[[ATTR0]] {			// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i32 [[N:%.]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.]], i32 [[L:%.]]) #[[ATTR0]] {
	// CHECK4-NEXT: entry:			// CHECK4-NEXT: entry:
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	// CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4			// CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
	// CHECK4-NEXT: [[AA_ADDR:%.]] = alloca [1000 x i16], align 4			// CHECK4-NEXT: [[AA_ADDR:%.]] = alloca [1000 x i16], align 4
	// CHECK4-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4			// CHECK4-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4
	// CHECK4-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			// CHECK4-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	// CHECK4-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4			// CHECK4-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
	// CHECK4-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4			// CHECK4-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
	// CHECK4-NEXT: store [1000 x i16]* [[AA]], [1000 x i16]** [[AA_ADDR]], align 4			// CHECK4-NEXT: store [1000 x i16]* [[AA]], [1000 x i16]** [[AA_ADDR]], align 4
	// CHECK4-NEXT: [[TMP0:%.]] = load [1000 x i16], [1000 x i16]** [[AA_ADDR]], align 4			// CHECK4-NEXT: [[TMP0:%.]] = load [1000 x i16], [1000 x i16]** [[AA_ADDR]], align 4
	// CHECK4-NEXT: [[TMP1:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 2, i1 false, i1 false)			// CHECK4-NEXT: [[TMP1:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l34_kernel_info, i1 false)
	// CHECK4-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1			// CHECK4-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
	// CHECK4-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]			// CHECK4-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
	// CHECK4: user_code.entry:			// CHECK4: user_code.entry:
	// CHECK4-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB4]])			// CHECK4-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB4]])
	// CHECK4-NEXT: [[TMP3:%.]] = load i32, i32 [[N_ADDR]], align 4			// CHECK4-NEXT: [[TMP3:%.]] = load i32, i32 [[N_ADDR]], align 4
	// CHECK4-NEXT: store i32 [[TMP3]], i32* [[N_CASTED]], align 4			// CHECK4-NEXT: store i32 [[TMP3]], i32* [[N_CASTED]], align 4
	// CHECK4-NEXT: [[TMP4:%.]] = load i32, i32 [[N_CASTED]], align 4			// CHECK4-NEXT: [[TMP4:%.]] = load i32, i32 [[N_CASTED]], align 4
	// CHECK4-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4			// CHECK4-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	// CHECK4-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4			// CHECK4-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4
	// CHECK4-NEXT: call void @__omp_outlined__2(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i32 [[TMP4]], [1000 x i16]* [[TMP0]]) #[[ATTR2]]			// CHECK4-NEXT: call void @__omp_outlined__2(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i32 [[TMP4]], [1000 x i16]* [[TMP0]]) #[[ATTR2]]
	// CHECK4-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 false)			// CHECK4-NEXT: call void @__kmpc_target_deinit(i1 false)
	// CHECK4-NEXT: ret void			// CHECK4-NEXT: ret void
	// CHECK4: worker.exit:			// CHECK4: worker.exit:
	// CHECK4-NEXT: ret void			// CHECK4-NEXT: ret void
	//			//
	//			//
	// CHECK4-LABEL: define {{[^@]+}}@__omp_outlined__2			// CHECK4-LABEL: define {{[^@]+}}@__omp_outlined__2
	// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i32 [[N:%.]], [1000 x i16]* nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR0]] {			// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i32 [[N:%.]], [1000 x i16]* nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR0]] {
	// CHECK4-NEXT: entry:			// CHECK4-NEXT: entry:
	▲ Show 20 Lines • Show All 217 Lines • ▼ Show 20 Lines
	// CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l39			// CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l39
	// CHECK4-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {			// CHECK4-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
	// CHECK4-NEXT: entry:			// CHECK4-NEXT: entry:
	// CHECK4-NEXT: [[B_ADDR:%.]] = alloca [10 x i32], align 4			// CHECK4-NEXT: [[B_ADDR:%.]] = alloca [10 x i32], align 4
	// CHECK4-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			// CHECK4-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	// CHECK4-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4			// CHECK4-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
	// CHECK4-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4			// CHECK4-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
	// CHECK4-NEXT: [[TMP0:%.]] = load [10 x i32], [10 x i32]** [[B_ADDR]], align 4			// CHECK4-NEXT: [[TMP0:%.]] = load [10 x i32], [10 x i32]** [[B_ADDR]], align 4
	// CHECK4-NEXT: [[TMP1:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 2, i1 false, i1 false)			// CHECK4-NEXT: [[TMP1:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l39_kernel_info, i1 false)
	// CHECK4-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1			// CHECK4-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
	// CHECK4-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]			// CHECK4-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
	// CHECK4: user_code.entry:			// CHECK4: user_code.entry:
	// CHECK4-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB4]])			// CHECK4-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB4]])
	// CHECK4-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4			// CHECK4-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	// CHECK4-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4			// CHECK4-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4
	// CHECK4-NEXT: call void @__omp_outlined__4(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], [10 x i32]* [[TMP0]]) #[[ATTR2]]			// CHECK4-NEXT: call void @__omp_outlined__4(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], [10 x i32]* [[TMP0]]) #[[ATTR2]]
	// CHECK4-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 false)			// CHECK4-NEXT: call void @__kmpc_target_deinit(i1 false)
	// CHECK4-NEXT: ret void			// CHECK4-NEXT: ret void
	// CHECK4: worker.exit:			// CHECK4: worker.exit:
	// CHECK4-NEXT: ret void			// CHECK4-NEXT: ret void
	//			//
	//			//
	// CHECK4-LABEL: define {{[^@]+}}@__omp_outlined__4			// CHECK4-LABEL: define {{[^@]+}}@__omp_outlined__4
	// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], [10 x i32] nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {			// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], [10 x i32] nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
	// CHECK4-NEXT: entry:			// CHECK4-NEXT: entry:
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	// CHECK4-NEXT: [[C_ADDR:%.]] = alloca [10 x [10 x i32]], align 4			// CHECK4-NEXT: [[C_ADDR:%.]] = alloca [10 x [10 x i32]], align 4
	// CHECK4-NEXT: [[F_ADDR:%.*]] = alloca i32, align 4			// CHECK4-NEXT: [[F_ADDR:%.*]] = alloca i32, align 4
	// CHECK4-NEXT: [[F_CASTED:%.*]] = alloca i32, align 4			// CHECK4-NEXT: [[F_CASTED:%.*]] = alloca i32, align 4
	// CHECK4-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			// CHECK4-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	// CHECK4-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4			// CHECK4-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
	// CHECK4-NEXT: store [10 x [10 x i32]]* [[C]], [10 x [10 x i32]]** [[C_ADDR]], align 4			// CHECK4-NEXT: store [10 x [10 x i32]]* [[C]], [10 x [10 x i32]]** [[C_ADDR]], align 4
	// CHECK4-NEXT: store i32 [[F]], i32* [[F_ADDR]], align 4			// CHECK4-NEXT: store i32 [[F]], i32* [[F_ADDR]], align 4
	// CHECK4-NEXT: [[TMP0:%.]] = load [10 x [10 x i32]], [10 x [10 x i32]]** [[C_ADDR]], align 4			// CHECK4-NEXT: [[TMP0:%.]] = load [10 x [10 x i32]], [10 x [10 x i32]]** [[C_ADDR]], align 4
	// CHECK4-NEXT: [[TMP1:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 2, i1 false, i1 false)			// CHECK4-NEXT: [[TMP1:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l44_kernel_info, i1 false)
	// CHECK4-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1			// CHECK4-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
	// CHECK4-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]			// CHECK4-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
	// CHECK4: user_code.entry:			// CHECK4: user_code.entry:
	// CHECK4-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB4]])			// CHECK4-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB4]])
	// CHECK4-NEXT: [[TMP3:%.]] = load i32, i32 [[F_ADDR]], align 4			// CHECK4-NEXT: [[TMP3:%.]] = load i32, i32 [[F_ADDR]], align 4
	// CHECK4-NEXT: store i32 [[TMP3]], i32* [[F_CASTED]], align 4			// CHECK4-NEXT: store i32 [[TMP3]], i32* [[F_CASTED]], align 4
	// CHECK4-NEXT: [[TMP4:%.]] = load i32, i32 [[F_CASTED]], align 4			// CHECK4-NEXT: [[TMP4:%.]] = load i32, i32 [[F_CASTED]], align 4
	// CHECK4-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4			// CHECK4-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	// CHECK4-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4			// CHECK4-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4
	// CHECK4-NEXT: call void @__omp_outlined__6(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], [10 x [10 x i32]]* [[TMP0]], i32 [[TMP4]]) #[[ATTR2]]			// CHECK4-NEXT: call void @__omp_outlined__6(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], [10 x [10 x i32]]* [[TMP0]], i32 [[TMP4]]) #[[ATTR2]]
	// CHECK4-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 false)			// CHECK4-NEXT: call void @__kmpc_target_deinit(i1 false)
	// CHECK4-NEXT: ret void			// CHECK4-NEXT: ret void
	// CHECK4: worker.exit:			// CHECK4: worker.exit:
	// CHECK4-NEXT: ret void			// CHECK4-NEXT: ret void
	//			//
	//			//
	// CHECK4-LABEL: define {{[^@]+}}@__omp_outlined__6			// CHECK4-LABEL: define {{[^@]+}}@__omp_outlined__6
	// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], [10 x [10 x i32]] nonnull align 4 dereferenceable(400) [[C:%.]], i32 [[F:%.]]) #[[ATTR0]] {			// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], [10 x [10 x i32]] nonnull align 4 dereferenceable(400) [[C:%.]], i32 [[F:%.]]) #[[ATTR0]] {
	// CHECK4-NEXT: entry:			// CHECK4-NEXT: entry:
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	// CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4			// CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
	// CHECK4-NEXT: [[C_ADDR:%.]] = alloca [10 x [10 x i32]], align 4			// CHECK4-NEXT: [[C_ADDR:%.]] = alloca [10 x [10 x i32]], align 4
	// CHECK4-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4			// CHECK4-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4
	// CHECK4-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			// CHECK4-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	// CHECK4-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4			// CHECK4-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
	// CHECK4-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4			// CHECK4-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
	// CHECK4-NEXT: store [10 x [10 x i32]]* [[C]], [10 x [10 x i32]]** [[C_ADDR]], align 4			// CHECK4-NEXT: store [10 x [10 x i32]]* [[C]], [10 x [10 x i32]]** [[C_ADDR]], align 4
	// CHECK4-NEXT: [[TMP0:%.]] = load [10 x [10 x i32]], [10 x [10 x i32]]** [[C_ADDR]], align 4			// CHECK4-NEXT: [[TMP0:%.]] = load [10 x [10 x i32]], [10 x [10 x i32]]** [[C_ADDR]], align 4
	// CHECK4-NEXT: [[TMP1:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 2, i1 false, i1 false)			// CHECK4-NEXT: [[TMP1:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l52_kernel_info, i1 false)
	// CHECK4-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1			// CHECK4-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
	// CHECK4-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]			// CHECK4-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
	// CHECK4: user_code.entry:			// CHECK4: user_code.entry:
	// CHECK4-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB4]])			// CHECK4-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB4]])
	// CHECK4-NEXT: [[TMP3:%.]] = load i32, i32 [[N_ADDR]], align 4			// CHECK4-NEXT: [[TMP3:%.]] = load i32, i32 [[N_ADDR]], align 4
	// CHECK4-NEXT: store i32 [[TMP3]], i32* [[N_CASTED]], align 4			// CHECK4-NEXT: store i32 [[TMP3]], i32* [[N_CASTED]], align 4
	// CHECK4-NEXT: [[TMP4:%.]] = load i32, i32 [[N_CASTED]], align 4			// CHECK4-NEXT: [[TMP4:%.]] = load i32, i32 [[N_CASTED]], align 4
	// CHECK4-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4			// CHECK4-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	// CHECK4-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4			// CHECK4-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4
	// CHECK4-NEXT: call void @__omp_outlined__8(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i32 [[TMP4]], [10 x [10 x i32]]* [[TMP0]]) #[[ATTR2]]			// CHECK4-NEXT: call void @__omp_outlined__8(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i32 [[TMP4]], [10 x [10 x i32]]* [[TMP0]]) #[[ATTR2]]
	// CHECK4-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 false)			// CHECK4-NEXT: call void @__kmpc_target_deinit(i1 false)
	// CHECK4-NEXT: ret void			// CHECK4-NEXT: ret void
	// CHECK4: worker.exit:			// CHECK4: worker.exit:
	// CHECK4-NEXT: ret void			// CHECK4-NEXT: ret void
	//			//
	//			//
	// CHECK4-LABEL: define {{[^@]+}}@__omp_outlined__8			// CHECK4-LABEL: define {{[^@]+}}@__omp_outlined__8
	// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i32 [[N:%.]], [10 x [10 x i32]]* nonnull align 4 dereferenceable(400) [[C:%.*]]) #[[ATTR0]] {			// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i32 [[N:%.]], [10 x [10 x i32]]* nonnull align 4 dereferenceable(400) [[C:%.*]]) #[[ATTR0]] {
	// CHECK4-NEXT: entry:			// CHECK4-NEXT: entry:
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	// CHECK4-NEXT: [[V_ADDR:%.]] = alloca i32, align 4			// CHECK4-NEXT: [[V_ADDR:%.]] = alloca i32, align 4
	// CHECK4-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4			// CHECK4-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4
	// CHECK4-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			// CHECK4-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	// CHECK4-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4			// CHECK4-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
	// CHECK4-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4			// CHECK4-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
	// CHECK4-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 4			// CHECK4-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 4
	// CHECK4-NEXT: store i32* [[V]], i32** [[V_ADDR]], align 4			// CHECK4-NEXT: store i32* [[V]], i32** [[V_ADDR]], align 4
	// CHECK4-NEXT: [[TMP0:%.]] = load [1000 x i32], [1000 x i32]** [[A_ADDR]], align 4			// CHECK4-NEXT: [[TMP0:%.]] = load [1000 x i32], [1000 x i32]** [[A_ADDR]], align 4
	// CHECK4-NEXT: [[TMP1:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 2, i1 false, i1 false)			// CHECK4-NEXT: [[TMP1:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l59_kernel_info, i1 false)
	// CHECK4-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1			// CHECK4-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
	// CHECK4-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]			// CHECK4-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
	// CHECK4: user_code.entry:			// CHECK4: user_code.entry:
	// CHECK4-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB4]])			// CHECK4-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB4]])
	// CHECK4-NEXT: [[TMP3:%.]] = load i32, i32 [[N_ADDR]], align 4			// CHECK4-NEXT: [[TMP3:%.]] = load i32, i32 [[N_ADDR]], align 4
	// CHECK4-NEXT: store i32 [[TMP3]], i32* [[N_CASTED]], align 4			// CHECK4-NEXT: store i32 [[TMP3]], i32* [[N_CASTED]], align 4
	// CHECK4-NEXT: [[TMP4:%.]] = load i32, i32 [[N_CASTED]], align 4			// CHECK4-NEXT: [[TMP4:%.]] = load i32, i32 [[N_CASTED]], align 4
	// CHECK4-NEXT: [[TMP5:%.]] = load i32, i32** [[V_ADDR]], align 4			// CHECK4-NEXT: [[TMP5:%.]] = load i32, i32** [[V_ADDR]], align 4
	// CHECK4-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4			// CHECK4-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	// CHECK4-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4			// CHECK4-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4
	// CHECK4-NEXT: call void @__omp_outlined__10(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i32 [[TMP4]], [1000 x i32]* [[TMP0]], i32* [[TMP5]]) #[[ATTR2]]			// CHECK4-NEXT: call void @__omp_outlined__10(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i32 [[TMP4]], [1000 x i32]* [[TMP0]], i32* [[TMP5]]) #[[ATTR2]]
	// CHECK4-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 false)			// CHECK4-NEXT: call void @__kmpc_target_deinit(i1 false)
	// CHECK4-NEXT: ret void			// CHECK4-NEXT: ret void
	// CHECK4: worker.exit:			// CHECK4: worker.exit:
	// CHECK4-NEXT: ret void			// CHECK4-NEXT: ret void
	//			//
	//			//
	// CHECK4-LABEL: define {{[^@]+}}@__omp_outlined__10			// CHECK4-LABEL: define {{[^@]+}}@__omp_outlined__10
	// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i32 [[N:%.]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.]], i32 [[V:%.*]]) #[[ATTR0]] {			// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i32 [[N:%.]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.]], i32 [[V:%.*]]) #[[ATTR0]] {
	// CHECK4-NEXT: entry:			// CHECK4-NEXT: entry:
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clang/test/OpenMP/nvptx_target_teams_distribute_parallel_for_generic_mode_codegen.cpp

	Show All 39 Lines
	// CHECK1-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			// CHECK1-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	// CHECK1-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4			// CHECK1-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
	// CHECK1-NEXT: store i64 [[ARGC]], i64* [[ARGC_ADDR]], align 8			// CHECK1-NEXT: store i64 [[ARGC]], i64* [[ARGC_ADDR]], align 8
	// CHECK1-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8			// CHECK1-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
	// CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8			// CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
	// CHECK1-NEXT: [[CONV:%.]] = bitcast i64 [[ARGC_ADDR]] to i32*			// CHECK1-NEXT: [[CONV:%.]] = bitcast i64 [[ARGC_ADDR]] to i32*
	// CHECK1-NEXT: [[TMP0:%.]] = load i32, i32** [[A_ADDR]], align 8			// CHECK1-NEXT: [[TMP0:%.]] = load i32, i32** [[A_ADDR]], align 8
	// CHECK1-NEXT: [[CONV1:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__ADDR]] to i32*			// CHECK1-NEXT: [[CONV1:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__ADDR]] to i32*
	// CHECK1-NEXT: [[TMP1:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1:[0-9]+]], i8 2, i1 false, i1 false)			// CHECK1-NEXT: [[TMP1:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l24_kernel_info, i1 false)
	// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1			// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
	// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]			// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
	// CHECK1: user_code.entry:			// CHECK1: user_code.entry:
	// CHECK1-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB4:[0-9]+]])			// CHECK1-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB4:[0-9]+]])
	// CHECK1-NEXT: [[TMP3:%.]] = load i32, i32 [[CONV]], align 4			// CHECK1-NEXT: [[TMP3:%.]] = load i32, i32 [[CONV]], align 4
	// CHECK1-NEXT: [[CONV2:%.]] = bitcast i64 [[ARGC_CASTED]] to i32*			// CHECK1-NEXT: [[CONV2:%.]] = bitcast i64 [[ARGC_CASTED]] to i32*
	// CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4			// CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
	// CHECK1-NEXT: [[TMP4:%.]] = load i64, i64 [[ARGC_CASTED]], align 8			// CHECK1-NEXT: [[TMP4:%.]] = load i64, i64 [[ARGC_CASTED]], align 8
	// CHECK1-NEXT: [[TMP5:%.]] = load i32, i32 [[CONV1]], align 4			// CHECK1-NEXT: [[TMP5:%.]] = load i32, i32 [[CONV1]], align 4
	// CHECK1-NEXT: [[CONV3:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED]] to i32*			// CHECK1-NEXT: [[CONV3:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED]] to i32*
	// CHECK1-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4			// CHECK1-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4
	// CHECK1-NEXT: [[TMP6:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED]], align 8			// CHECK1-NEXT: [[TMP6:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED]], align 8
	// CHECK1-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4			// CHECK1-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4			// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4
	// CHECK1-NEXT: call void @__omp_outlined__(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i64 [[TMP4]], i32* [[TMP0]], i64 [[TMP6]]) #[[ATTR2:[0-9]+]]			// CHECK1-NEXT: call void @__omp_outlined__(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i64 [[TMP4]], i32* [[TMP0]], i64 [[TMP6]]) #[[ATTR2:[0-9]+]]
	// CHECK1-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 false)			// CHECK1-NEXT: call void @__kmpc_target_deinit(i1 false)
	// CHECK1-NEXT: ret void			// CHECK1-NEXT: ret void
	// CHECK1: worker.exit:			// CHECK1: worker.exit:
	// CHECK1-NEXT: ret void			// CHECK1-NEXT: ret void
	//			//
	//			//
	// CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__			// CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__
	// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i64 [[ARGC:%.]], i32* nonnull align 4 dereferenceable(4) [[A:%.]], i64 [[DOTCAPTURE_EXPR_:%.]]) #[[ATTR0]] {			// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i64 [[ARGC:%.]], i32* nonnull align 4 dereferenceable(4) [[A:%.]], i64 [[DOTCAPTURE_EXPR_:%.]]) #[[ATTR0]] {
	// CHECK1-NEXT: entry:			// CHECK1-NEXT: entry:
	▲ Show 20 Lines • Show All 275 Lines • ▼ Show 20 Lines
	// CHECK2-NEXT: [[ARGC_CASTED:%.*]] = alloca i32, align 4			// CHECK2-NEXT: [[ARGC_CASTED:%.*]] = alloca i32, align 4
	// CHECK2-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4			// CHECK2-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
	// CHECK2-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			// CHECK2-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	// CHECK2-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4			// CHECK2-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
	// CHECK2-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4			// CHECK2-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4
	// CHECK2-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4			// CHECK2-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4
	// CHECK2-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4			// CHECK2-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
	// CHECK2-NEXT: [[TMP0:%.]] = load i32, i32** [[A_ADDR]], align 4			// CHECK2-NEXT: [[TMP0:%.]] = load i32, i32** [[A_ADDR]], align 4
	// CHECK2-NEXT: [[TMP1:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1:[0-9]+]], i8 2, i1 false, i1 false)			// CHECK2-NEXT: [[TMP1:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l24_kernel_info, i1 false)
	// CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1			// CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
	// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]			// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
	// CHECK2: user_code.entry:			// CHECK2: user_code.entry:
	// CHECK2-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB4:[0-9]+]])			// CHECK2-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB4:[0-9]+]])
	// CHECK2-NEXT: [[TMP3:%.]] = load i32, i32 [[ARGC_ADDR]], align 4			// CHECK2-NEXT: [[TMP3:%.]] = load i32, i32 [[ARGC_ADDR]], align 4
	// CHECK2-NEXT: store i32 [[TMP3]], i32* [[ARGC_CASTED]], align 4			// CHECK2-NEXT: store i32 [[TMP3]], i32* [[ARGC_CASTED]], align 4
	// CHECK2-NEXT: [[TMP4:%.]] = load i32, i32 [[ARGC_CASTED]], align 4			// CHECK2-NEXT: [[TMP4:%.]] = load i32, i32 [[ARGC_CASTED]], align 4
	// CHECK2-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTCAPTURE_EXPR__ADDR]], align 4			// CHECK2-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTCAPTURE_EXPR__ADDR]], align 4
	// CHECK2-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4			// CHECK2-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
	// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTCAPTURE_EXPR__CASTED]], align 4			// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTCAPTURE_EXPR__CASTED]], align 4
	// CHECK2-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4			// CHECK2-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4			// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4
	// CHECK2-NEXT: call void @__omp_outlined__(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i32 [[TMP4]], i32* [[TMP0]], i32 [[TMP6]]) #[[ATTR2:[0-9]+]]			// CHECK2-NEXT: call void @__omp_outlined__(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i32 [[TMP4]], i32* [[TMP0]], i32 [[TMP6]]) #[[ATTR2:[0-9]+]]
	// CHECK2-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 false)			// CHECK2-NEXT: call void @__kmpc_target_deinit(i1 false)
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	// CHECK2: worker.exit:			// CHECK2: worker.exit:
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__			// CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__
	// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i32 [[ARGC:%.]], i32* nonnull align 4 dereferenceable(4) [[A:%.]], i32 [[DOTCAPTURE_EXPR_:%.]]) #[[ATTR0]] {			// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i32 [[ARGC:%.]], i32* nonnull align 4 dereferenceable(4) [[A:%.]], i32 [[DOTCAPTURE_EXPR_:%.]]) #[[ATTR0]] {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	▲ Show 20 Lines • Show All 263 Lines • ▼ Show 20 Lines
	// CHECK3-NEXT: [[ARGC_CASTED:%.*]] = alloca i32, align 4			// CHECK3-NEXT: [[ARGC_CASTED:%.*]] = alloca i32, align 4
	// CHECK3-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4			// CHECK3-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
	// CHECK3-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			// CHECK3-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	// CHECK3-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4			// CHECK3-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
	// CHECK3-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4			// CHECK3-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4
	// CHECK3-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4			// CHECK3-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4
	// CHECK3-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4			// CHECK3-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
	// CHECK3-NEXT: [[TMP0:%.]] = load i32, i32** [[A_ADDR]], align 4			// CHECK3-NEXT: [[TMP0:%.]] = load i32, i32** [[A_ADDR]], align 4
	// CHECK3-NEXT: [[TMP1:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1:[0-9]+]], i8 2, i1 false, i1 false)			// CHECK3-NEXT: [[TMP1:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l24_kernel_info, i1 false)
	// CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1			// CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
	// CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]			// CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
	// CHECK3: user_code.entry:			// CHECK3: user_code.entry:
	// CHECK3-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB4:[0-9]+]])			// CHECK3-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB4:[0-9]+]])
	// CHECK3-NEXT: [[TMP3:%.]] = load i32, i32 [[ARGC_ADDR]], align 4			// CHECK3-NEXT: [[TMP3:%.]] = load i32, i32 [[ARGC_ADDR]], align 4
	// CHECK3-NEXT: store i32 [[TMP3]], i32* [[ARGC_CASTED]], align 4			// CHECK3-NEXT: store i32 [[TMP3]], i32* [[ARGC_CASTED]], align 4
	// CHECK3-NEXT: [[TMP4:%.]] = load i32, i32 [[ARGC_CASTED]], align 4			// CHECK3-NEXT: [[TMP4:%.]] = load i32, i32 [[ARGC_CASTED]], align 4
	// CHECK3-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTCAPTURE_EXPR__ADDR]], align 4			// CHECK3-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTCAPTURE_EXPR__ADDR]], align 4
	// CHECK3-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4			// CHECK3-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
	// CHECK3-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTCAPTURE_EXPR__CASTED]], align 4			// CHECK3-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTCAPTURE_EXPR__CASTED]], align 4
	// CHECK3-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4			// CHECK3-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	// CHECK3-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4			// CHECK3-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4
	// CHECK3-NEXT: call void @__omp_outlined__(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i32 [[TMP4]], i32* [[TMP0]], i32 [[TMP6]]) #[[ATTR2:[0-9]+]]			// CHECK3-NEXT: call void @__omp_outlined__(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i32 [[TMP4]], i32* [[TMP0]], i32 [[TMP6]]) #[[ATTR2:[0-9]+]]
	// CHECK3-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 false)			// CHECK3-NEXT: call void @__kmpc_target_deinit(i1 false)
	// CHECK3-NEXT: ret void			// CHECK3-NEXT: ret void
	// CHECK3: worker.exit:			// CHECK3: worker.exit:
	// CHECK3-NEXT: ret void			// CHECK3-NEXT: ret void
	//			//
	//			//
	// CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__			// CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__
	// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i32 [[ARGC:%.]], i32* nonnull align 4 dereferenceable(4) [[A:%.]], i32 [[DOTCAPTURE_EXPR_:%.]]) #[[ATTR0]] {			// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i32 [[ARGC:%.]], i32* nonnull align 4 dereferenceable(4) [[A:%.]], i32 [[DOTCAPTURE_EXPR_:%.]]) #[[ATTR0]] {
	// CHECK3-NEXT: entry:			// CHECK3-NEXT: entry:
	▲ Show 20 Lines • Show All 265 Lines • ▼ Show 20 Lines
	// CHECK4-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			// CHECK4-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	// CHECK4-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4			// CHECK4-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
	// CHECK4-NEXT: store i64 [[ARGC]], i64* [[ARGC_ADDR]], align 8			// CHECK4-NEXT: store i64 [[ARGC]], i64* [[ARGC_ADDR]], align 8
	// CHECK4-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8			// CHECK4-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
	// CHECK4-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8			// CHECK4-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
	// CHECK4-NEXT: [[CONV:%.]] = bitcast i64 [[ARGC_ADDR]] to i32*			// CHECK4-NEXT: [[CONV:%.]] = bitcast i64 [[ARGC_ADDR]] to i32*
	// CHECK4-NEXT: [[TMP0:%.]] = load i32, i32** [[A_ADDR]], align 8			// CHECK4-NEXT: [[TMP0:%.]] = load i32, i32** [[A_ADDR]], align 8
	// CHECK4-NEXT: [[CONV1:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__ADDR]] to i32*			// CHECK4-NEXT: [[CONV1:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__ADDR]] to i32*
	// CHECK4-NEXT: [[TMP1:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1:[0-9]+]], i8 2, i1 false, i1 false)			// CHECK4-NEXT: [[TMP1:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l24_kernel_info, i1 false)
	// CHECK4-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1			// CHECK4-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
	// CHECK4-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]			// CHECK4-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
	// CHECK4: user_code.entry:			// CHECK4: user_code.entry:
	// CHECK4-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB4:[0-9]+]])			// CHECK4-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB4:[0-9]+]])
	// CHECK4-NEXT: [[TMP3:%.]] = load i32, i32 [[CONV]], align 4			// CHECK4-NEXT: [[TMP3:%.]] = load i32, i32 [[CONV]], align 4
	// CHECK4-NEXT: [[CONV2:%.]] = bitcast i64 [[ARGC_CASTED]] to i32*			// CHECK4-NEXT: [[CONV2:%.]] = bitcast i64 [[ARGC_CASTED]] to i32*
	// CHECK4-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4			// CHECK4-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
	// CHECK4-NEXT: [[TMP4:%.]] = load i64, i64 [[ARGC_CASTED]], align 8			// CHECK4-NEXT: [[TMP4:%.]] = load i64, i64 [[ARGC_CASTED]], align 8
	// CHECK4-NEXT: [[TMP5:%.]] = load i32, i32 [[CONV1]], align 4			// CHECK4-NEXT: [[TMP5:%.]] = load i32, i32 [[CONV1]], align 4
	// CHECK4-NEXT: [[CONV3:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED]] to i32*			// CHECK4-NEXT: [[CONV3:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED]] to i32*
	// CHECK4-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4			// CHECK4-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4
	// CHECK4-NEXT: [[TMP6:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED]], align 8			// CHECK4-NEXT: [[TMP6:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED]], align 8
	// CHECK4-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4			// CHECK4-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	// CHECK4-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4			// CHECK4-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4
	// CHECK4-NEXT: call void @__omp_outlined__(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i64 [[TMP4]], i32* [[TMP0]], i64 [[TMP6]]) #[[ATTR2:[0-9]+]]			// CHECK4-NEXT: call void @__omp_outlined__(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i64 [[TMP4]], i32* [[TMP0]], i64 [[TMP6]]) #[[ATTR2:[0-9]+]]
	// CHECK4-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 false)			// CHECK4-NEXT: call void @__kmpc_target_deinit(i1 false)
	// CHECK4-NEXT: ret void			// CHECK4-NEXT: ret void
	// CHECK4: worker.exit:			// CHECK4: worker.exit:
	// CHECK4-NEXT: ret void			// CHECK4-NEXT: ret void
	//			//
	//			//
	// CHECK4-LABEL: define {{[^@]+}}@__omp_outlined__			// CHECK4-LABEL: define {{[^@]+}}@__omp_outlined__
	// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i64 [[ARGC:%.]], i32* nonnull align 4 dereferenceable(4) [[A:%.]], i64 [[DOTCAPTURE_EXPR_:%.]]) #[[ATTR0]] {			// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i64 [[ARGC:%.]], i32* nonnull align 4 dereferenceable(4) [[A:%.]], i64 [[DOTCAPTURE_EXPR_:%.]]) #[[ATTR0]] {
	// CHECK4-NEXT: entry:			// CHECK4-NEXT: entry:
	▲ Show 20 Lines • Show All 275 Lines • ▼ Show 20 Lines
	// CHECK5-NEXT: [[ARGC_CASTED:%.*]] = alloca i32, align 4			// CHECK5-NEXT: [[ARGC_CASTED:%.*]] = alloca i32, align 4
	// CHECK5-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4			// CHECK5-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
	// CHECK5-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			// CHECK5-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	// CHECK5-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4			// CHECK5-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
	// CHECK5-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4			// CHECK5-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4
	// CHECK5-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4			// CHECK5-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4
	// CHECK5-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4			// CHECK5-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
	// CHECK5-NEXT: [[TMP0:%.]] = load i32, i32** [[A_ADDR]], align 4			// CHECK5-NEXT: [[TMP0:%.]] = load i32, i32** [[A_ADDR]], align 4
	// CHECK5-NEXT: [[TMP1:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1:[0-9]+]], i8 2, i1 false, i1 false)			// CHECK5-NEXT: [[TMP1:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l24_kernel_info, i1 false)
	// CHECK5-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1			// CHECK5-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
	// CHECK5-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]			// CHECK5-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
	// CHECK5: user_code.entry:			// CHECK5: user_code.entry:
	// CHECK5-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB4:[0-9]+]])			// CHECK5-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB4:[0-9]+]])
	// CHECK5-NEXT: [[TMP3:%.]] = load i32, i32 [[ARGC_ADDR]], align 4			// CHECK5-NEXT: [[TMP3:%.]] = load i32, i32 [[ARGC_ADDR]], align 4
	// CHECK5-NEXT: store i32 [[TMP3]], i32* [[ARGC_CASTED]], align 4			// CHECK5-NEXT: store i32 [[TMP3]], i32* [[ARGC_CASTED]], align 4
	// CHECK5-NEXT: [[TMP4:%.]] = load i32, i32 [[ARGC_CASTED]], align 4			// CHECK5-NEXT: [[TMP4:%.]] = load i32, i32 [[ARGC_CASTED]], align 4
	// CHECK5-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTCAPTURE_EXPR__ADDR]], align 4			// CHECK5-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTCAPTURE_EXPR__ADDR]], align 4
	// CHECK5-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4			// CHECK5-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
	// CHECK5-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTCAPTURE_EXPR__CASTED]], align 4			// CHECK5-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTCAPTURE_EXPR__CASTED]], align 4
	// CHECK5-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4			// CHECK5-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	// CHECK5-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4			// CHECK5-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4
	// CHECK5-NEXT: call void @__omp_outlined__(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i32 [[TMP4]], i32* [[TMP0]], i32 [[TMP6]]) #[[ATTR2:[0-9]+]]			// CHECK5-NEXT: call void @__omp_outlined__(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i32 [[TMP4]], i32* [[TMP0]], i32 [[TMP6]]) #[[ATTR2:[0-9]+]]
	// CHECK5-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 false)			// CHECK5-NEXT: call void @__kmpc_target_deinit(i1 false)
	// CHECK5-NEXT: ret void			// CHECK5-NEXT: ret void
	// CHECK5: worker.exit:			// CHECK5: worker.exit:
	// CHECK5-NEXT: ret void			// CHECK5-NEXT: ret void
	//			//
	//			//
	// CHECK5-LABEL: define {{[^@]+}}@__omp_outlined__			// CHECK5-LABEL: define {{[^@]+}}@__omp_outlined__
	// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i32 [[ARGC:%.]], i32* nonnull align 4 dereferenceable(4) [[A:%.]], i32 [[DOTCAPTURE_EXPR_:%.]]) #[[ATTR0]] {			// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i32 [[ARGC:%.]], i32* nonnull align 4 dereferenceable(4) [[A:%.]], i32 [[DOTCAPTURE_EXPR_:%.]]) #[[ATTR0]] {
	// CHECK5-NEXT: entry:			// CHECK5-NEXT: entry:
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	// CHECK6-NEXT: [[ARGC_CASTED:%.*]] = alloca i32, align 4			// CHECK6-NEXT: [[ARGC_CASTED:%.*]] = alloca i32, align 4
	// CHECK6-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4			// CHECK6-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
	// CHECK6-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			// CHECK6-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	// CHECK6-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4			// CHECK6-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
	// CHECK6-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4			// CHECK6-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4
	// CHECK6-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4			// CHECK6-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4
	// CHECK6-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4			// CHECK6-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
	// CHECK6-NEXT: [[TMP0:%.]] = load i32, i32** [[A_ADDR]], align 4			// CHECK6-NEXT: [[TMP0:%.]] = load i32, i32** [[A_ADDR]], align 4
	// CHECK6-NEXT: [[TMP1:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1:[0-9]+]], i8 2, i1 false, i1 false)			// CHECK6-NEXT: [[TMP1:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l24_kernel_info, i1 false)
	// CHECK6-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1			// CHECK6-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
	// CHECK6-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]			// CHECK6-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
	// CHECK6: user_code.entry:			// CHECK6: user_code.entry:
	// CHECK6-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB4:[0-9]+]])			// CHECK6-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB4:[0-9]+]])
	// CHECK6-NEXT: [[TMP3:%.]] = load i32, i32 [[ARGC_ADDR]], align 4			// CHECK6-NEXT: [[TMP3:%.]] = load i32, i32 [[ARGC_ADDR]], align 4
	// CHECK6-NEXT: store i32 [[TMP3]], i32* [[ARGC_CASTED]], align 4			// CHECK6-NEXT: store i32 [[TMP3]], i32* [[ARGC_CASTED]], align 4
	// CHECK6-NEXT: [[TMP4:%.]] = load i32, i32 [[ARGC_CASTED]], align 4			// CHECK6-NEXT: [[TMP4:%.]] = load i32, i32 [[ARGC_CASTED]], align 4
	// CHECK6-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTCAPTURE_EXPR__ADDR]], align 4			// CHECK6-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTCAPTURE_EXPR__ADDR]], align 4
	// CHECK6-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4			// CHECK6-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
	// CHECK6-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTCAPTURE_EXPR__CASTED]], align 4			// CHECK6-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTCAPTURE_EXPR__CASTED]], align 4
	// CHECK6-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4			// CHECK6-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	// CHECK6-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4			// CHECK6-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4
	// CHECK6-NEXT: call void @__omp_outlined__(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i32 [[TMP4]], i32* [[TMP0]], i32 [[TMP6]]) #[[ATTR2:[0-9]+]]			// CHECK6-NEXT: call void @__omp_outlined__(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i32 [[TMP4]], i32* [[TMP0]], i32 [[TMP6]]) #[[ATTR2:[0-9]+]]
	// CHECK6-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 false)			// CHECK6-NEXT: call void @__kmpc_target_deinit(i1 false)
	// CHECK6-NEXT: ret void			// CHECK6-NEXT: ret void
	// CHECK6: worker.exit:			// CHECK6: worker.exit:
	// CHECK6-NEXT: ret void			// CHECK6-NEXT: ret void
	//			//
	//			//
	// CHECK6-LABEL: define {{[^@]+}}@__omp_outlined__			// CHECK6-LABEL: define {{[^@]+}}@__omp_outlined__
	// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i32 [[ARGC:%.]], i32* nonnull align 4 dereferenceable(4) [[A:%.]], i32 [[DOTCAPTURE_EXPR_:%.]]) #[[ATTR0]] {			// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i32 [[ARGC:%.]], i32* nonnull align 4 dereferenceable(4) [[A:%.]], i32 [[DOTCAPTURE_EXPR_:%.]]) #[[ATTR0]] {
	// CHECK6-NEXT: entry:			// CHECK6-NEXT: entry:
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clang/test/OpenMP/nvptx_target_teams_distribute_parallel_for_simd_codegen.cpp

This file is larger than 256 KB, so syntax highlighting is disabled by default.

	Show First 20 Lines • Show All 9,390 Lines • ▼ Show 20 Lines
	// CHECK1-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			// CHECK1-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	// CHECK1-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4			// CHECK1-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
	// CHECK1-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8			// CHECK1-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
	// CHECK1-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8			// CHECK1-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8
	// CHECK1-NEXT: store i64 [[L]], i64* [[L_ADDR]], align 8			// CHECK1-NEXT: store i64 [[L]], i64* [[L_ADDR]], align 8
	// CHECK1-NEXT: [[CONV:%.]] = bitcast i64 [[N_ADDR]] to i32*			// CHECK1-NEXT: [[CONV:%.]] = bitcast i64 [[N_ADDR]] to i32*
	// CHECK1-NEXT: [[TMP0:%.]] = load [1000 x i32], [1000 x i32]** [[A_ADDR]], align 8			// CHECK1-NEXT: [[TMP0:%.]] = load [1000 x i32], [1000 x i32]** [[A_ADDR]], align 8
	// CHECK1-NEXT: [[CONV1:%.]] = bitcast i64 [[L_ADDR]] to i32*			// CHECK1-NEXT: [[CONV1:%.]] = bitcast i64 [[L_ADDR]] to i32*
	// CHECK1-NEXT: [[TMP1:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1:[0-9]+]], i8 2, i1 false, i1 false)			// CHECK1-NEXT: [[TMP1:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l26_kernel_info, i1 false)
	// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1			// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
	// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]			// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
	// CHECK1: user_code.entry:			// CHECK1: user_code.entry:
	// CHECK1-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB4:[0-9]+]])			// CHECK1-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB4:[0-9]+]])
	// CHECK1-NEXT: [[TMP3:%.]] = load i32, i32 [[CONV]], align 4			// CHECK1-NEXT: [[TMP3:%.]] = load i32, i32 [[CONV]], align 4
	// CHECK1-NEXT: [[CONV2:%.]] = bitcast i64 [[N_CASTED]] to i32*			// CHECK1-NEXT: [[CONV2:%.]] = bitcast i64 [[N_CASTED]] to i32*
	// CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4			// CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
	// CHECK1-NEXT: [[TMP4:%.]] = load i64, i64 [[N_CASTED]], align 8			// CHECK1-NEXT: [[TMP4:%.]] = load i64, i64 [[N_CASTED]], align 8
	// CHECK1-NEXT: [[TMP5:%.]] = load i32, i32 [[CONV1]], align 4			// CHECK1-NEXT: [[TMP5:%.]] = load i32, i32 [[CONV1]], align 4
	// CHECK1-NEXT: [[CONV3:%.]] = bitcast i64 [[L_CASTED]] to i32*			// CHECK1-NEXT: [[CONV3:%.]] = bitcast i64 [[L_CASTED]] to i32*
	// CHECK1-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4			// CHECK1-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4
	// CHECK1-NEXT: [[TMP6:%.]] = load i64, i64 [[L_CASTED]], align 8			// CHECK1-NEXT: [[TMP6:%.]] = load i64, i64 [[L_CASTED]], align 8
	// CHECK1-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4			// CHECK1-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4			// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4
	// CHECK1-NEXT: call void @__omp_outlined__(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i64 [[TMP4]], [1000 x i32]* [[TMP0]], i64 [[TMP6]]) #[[ATTR2:[0-9]+]]			// CHECK1-NEXT: call void @__omp_outlined__(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i64 [[TMP4]], [1000 x i32]* [[TMP0]], i64 [[TMP6]]) #[[ATTR2:[0-9]+]]
	// CHECK1-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 false)			// CHECK1-NEXT: call void @__kmpc_target_deinit(i1 false)
	// CHECK1-NEXT: ret void			// CHECK1-NEXT: ret void
	// CHECK1: worker.exit:			// CHECK1: worker.exit:
	// CHECK1-NEXT: ret void			// CHECK1-NEXT: ret void
	//			//
	//			//
	// CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__			// CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__
	// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i64 [[N:%.]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.]], i64 [[L:%.]]) #[[ATTR0]] {			// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i64 [[N:%.]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.]], i64 [[L:%.]]) #[[ATTR0]] {
	// CHECK1-NEXT: entry:			// CHECK1-NEXT: entry:
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	// CHECK1-NEXT: [[AA_ADDR:%.]] = alloca [1000 x i16], align 8			// CHECK1-NEXT: [[AA_ADDR:%.]] = alloca [1000 x i16], align 8
	// CHECK1-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8			// CHECK1-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8
	// CHECK1-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			// CHECK1-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	// CHECK1-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4			// CHECK1-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
	// CHECK1-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8			// CHECK1-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
	// CHECK1-NEXT: store [1000 x i16]* [[AA]], [1000 x i16]** [[AA_ADDR]], align 8			// CHECK1-NEXT: store [1000 x i16]* [[AA]], [1000 x i16]** [[AA_ADDR]], align 8
	// CHECK1-NEXT: [[CONV:%.]] = bitcast i64 [[N_ADDR]] to i32*			// CHECK1-NEXT: [[CONV:%.]] = bitcast i64 [[N_ADDR]] to i32*
	// CHECK1-NEXT: [[TMP0:%.]] = load [1000 x i16], [1000 x i16]** [[AA_ADDR]], align 8			// CHECK1-NEXT: [[TMP0:%.]] = load [1000 x i16], [1000 x i16]** [[AA_ADDR]], align 8
	// CHECK1-NEXT: [[TMP1:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 2, i1 false, i1 false)			// CHECK1-NEXT: [[TMP1:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l32_kernel_info, i1 false)
	// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1			// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
	// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]			// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
	// CHECK1: user_code.entry:			// CHECK1: user_code.entry:
	// CHECK1-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB4]])			// CHECK1-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB4]])
	// CHECK1-NEXT: [[TMP3:%.]] = load i32, i32 [[CONV]], align 4			// CHECK1-NEXT: [[TMP3:%.]] = load i32, i32 [[CONV]], align 4
	// CHECK1-NEXT: [[CONV1:%.]] = bitcast i64 [[N_CASTED]] to i32*			// CHECK1-NEXT: [[CONV1:%.]] = bitcast i64 [[N_CASTED]] to i32*
	// CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4			// CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4
	// CHECK1-NEXT: [[TMP4:%.]] = load i64, i64 [[N_CASTED]], align 8			// CHECK1-NEXT: [[TMP4:%.]] = load i64, i64 [[N_CASTED]], align 8
	// CHECK1-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4			// CHECK1-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4			// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4
	// CHECK1-NEXT: call void @__omp_outlined__2(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i64 [[TMP4]], [1000 x i16]* [[TMP0]]) #[[ATTR2]]			// CHECK1-NEXT: call void @__omp_outlined__2(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i64 [[TMP4]], [1000 x i16]* [[TMP0]]) #[[ATTR2]]
	// CHECK1-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 false)			// CHECK1-NEXT: call void @__kmpc_target_deinit(i1 false)
	// CHECK1-NEXT: ret void			// CHECK1-NEXT: ret void
	// CHECK1: worker.exit:			// CHECK1: worker.exit:
	// CHECK1-NEXT: ret void			// CHECK1-NEXT: ret void
	//			//
	//			//
	// CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__2			// CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__2
	// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i64 [[N:%.]], [1000 x i16]* nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR0]] {			// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i64 [[N:%.]], [1000 x i16]* nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR0]] {
	// CHECK1-NEXT: entry:			// CHECK1-NEXT: entry:
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	// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l37			// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l37
	// CHECK1-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {			// CHECK1-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
	// CHECK1-NEXT: entry:			// CHECK1-NEXT: entry:
	// CHECK1-NEXT: [[B_ADDR:%.]] = alloca [10 x i32], align 8			// CHECK1-NEXT: [[B_ADDR:%.]] = alloca [10 x i32], align 8
	// CHECK1-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			// CHECK1-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	// CHECK1-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4			// CHECK1-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
	// CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8			// CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
	// CHECK1-NEXT: [[TMP0:%.]] = load [10 x i32], [10 x i32]** [[B_ADDR]], align 8			// CHECK1-NEXT: [[TMP0:%.]] = load [10 x i32], [10 x i32]** [[B_ADDR]], align 8
	// CHECK1-NEXT: [[TMP1:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 2, i1 false, i1 false)			// CHECK1-NEXT: [[TMP1:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l37_kernel_info, i1 false)
	// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1			// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
	// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]			// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
	// CHECK1: user_code.entry:			// CHECK1: user_code.entry:
	// CHECK1-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB4]])			// CHECK1-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB4]])
	// CHECK1-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4			// CHECK1-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4			// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4
	// CHECK1-NEXT: call void @__omp_outlined__4(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], [10 x i32]* [[TMP0]]) #[[ATTR2]]			// CHECK1-NEXT: call void @__omp_outlined__4(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], [10 x i32]* [[TMP0]]) #[[ATTR2]]
	// CHECK1-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 false)			// CHECK1-NEXT: call void @__kmpc_target_deinit(i1 false)
	// CHECK1-NEXT: ret void			// CHECK1-NEXT: ret void
	// CHECK1: worker.exit:			// CHECK1: worker.exit:
	// CHECK1-NEXT: ret void			// CHECK1-NEXT: ret void
	//			//
	//			//
	// CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__4			// CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__4
	// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], [10 x i32] nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {			// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], [10 x i32] nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
	// CHECK1-NEXT: entry:			// CHECK1-NEXT: entry:
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	// CHECK1-NEXT: [[F_ADDR:%.*]] = alloca i64, align 8			// CHECK1-NEXT: [[F_ADDR:%.*]] = alloca i64, align 8
	// CHECK1-NEXT: [[F_CASTED:%.*]] = alloca i64, align 8			// CHECK1-NEXT: [[F_CASTED:%.*]] = alloca i64, align 8
	// CHECK1-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			// CHECK1-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	// CHECK1-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4			// CHECK1-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
	// CHECK1-NEXT: store [10 x [10 x i32]]* [[C]], [10 x [10 x i32]]** [[C_ADDR]], align 8			// CHECK1-NEXT: store [10 x [10 x i32]]* [[C]], [10 x [10 x i32]]** [[C_ADDR]], align 8
	// CHECK1-NEXT: store i64 [[F]], i64* [[F_ADDR]], align 8			// CHECK1-NEXT: store i64 [[F]], i64* [[F_ADDR]], align 8
	// CHECK1-NEXT: [[TMP0:%.]] = load [10 x [10 x i32]], [10 x [10 x i32]]** [[C_ADDR]], align 8			// CHECK1-NEXT: [[TMP0:%.]] = load [10 x [10 x i32]], [10 x [10 x i32]]** [[C_ADDR]], align 8
	// CHECK1-NEXT: [[CONV:%.]] = bitcast i64 [[F_ADDR]] to i32*			// CHECK1-NEXT: [[CONV:%.]] = bitcast i64 [[F_ADDR]] to i32*
	// CHECK1-NEXT: [[TMP1:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 2, i1 false, i1 false)			// CHECK1-NEXT: [[TMP1:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l42_kernel_info, i1 false)
	// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1			// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
	// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]			// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
	// CHECK1: user_code.entry:			// CHECK1: user_code.entry:
	// CHECK1-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB4]])			// CHECK1-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB4]])
	// CHECK1-NEXT: [[TMP3:%.]] = load i32, i32 [[CONV]], align 4			// CHECK1-NEXT: [[TMP3:%.]] = load i32, i32 [[CONV]], align 4
	// CHECK1-NEXT: [[CONV1:%.]] = bitcast i64 [[F_CASTED]] to i32*			// CHECK1-NEXT: [[CONV1:%.]] = bitcast i64 [[F_CASTED]] to i32*
	// CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4			// CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4
	// CHECK1-NEXT: [[TMP4:%.]] = load i64, i64 [[F_CASTED]], align 8			// CHECK1-NEXT: [[TMP4:%.]] = load i64, i64 [[F_CASTED]], align 8
	// CHECK1-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4			// CHECK1-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4			// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4
	// CHECK1-NEXT: call void @__omp_outlined__6(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], [10 x [10 x i32]]* [[TMP0]], i64 [[TMP4]]) #[[ATTR2]]			// CHECK1-NEXT: call void @__omp_outlined__6(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], [10 x [10 x i32]]* [[TMP0]], i64 [[TMP4]]) #[[ATTR2]]
	// CHECK1-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 false)			// CHECK1-NEXT: call void @__kmpc_target_deinit(i1 false)
	// CHECK1-NEXT: ret void			// CHECK1-NEXT: ret void
	// CHECK1: worker.exit:			// CHECK1: worker.exit:
	// CHECK1-NEXT: ret void			// CHECK1-NEXT: ret void
	//			//
	//			//
	// CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__6			// CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__6
	// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], [10 x [10 x i32]] nonnull align 4 dereferenceable(400) [[C:%.]], i64 [[F:%.]]) #[[ATTR0]] {			// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], [10 x [10 x i32]] nonnull align 4 dereferenceable(400) [[C:%.]], i64 [[F:%.]]) #[[ATTR0]] {
	// CHECK1-NEXT: entry:			// CHECK1-NEXT: entry:
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	// CHECK2-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4			// CHECK2-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4
	// CHECK2-NEXT: [[L_CASTED:%.*]] = alloca i32, align 4			// CHECK2-NEXT: [[L_CASTED:%.*]] = alloca i32, align 4
	// CHECK2-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			// CHECK2-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	// CHECK2-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4			// CHECK2-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
	// CHECK2-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4			// CHECK2-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
	// CHECK2-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 4			// CHECK2-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 4
	// CHECK2-NEXT: store i32 [[L]], i32* [[L_ADDR]], align 4			// CHECK2-NEXT: store i32 [[L]], i32* [[L_ADDR]], align 4
	// CHECK2-NEXT: [[TMP0:%.]] = load [1000 x i32], [1000 x i32]** [[A_ADDR]], align 4			// CHECK2-NEXT: [[TMP0:%.]] = load [1000 x i32], [1000 x i32]** [[A_ADDR]], align 4
	// CHECK2-NEXT: [[TMP1:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1:[0-9]+]], i8 2, i1 false, i1 false)			// CHECK2-NEXT: [[TMP1:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l26_kernel_info, i1 false)
	// CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1			// CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
	// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]			// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
	// CHECK2: user_code.entry:			// CHECK2: user_code.entry:
	// CHECK2-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB4:[0-9]+]])			// CHECK2-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB4:[0-9]+]])
	// CHECK2-NEXT: [[TMP3:%.]] = load i32, i32 [[N_ADDR]], align 4			// CHECK2-NEXT: [[TMP3:%.]] = load i32, i32 [[N_ADDR]], align 4
	// CHECK2-NEXT: store i32 [[TMP3]], i32* [[N_CASTED]], align 4			// CHECK2-NEXT: store i32 [[TMP3]], i32* [[N_CASTED]], align 4
	// CHECK2-NEXT: [[TMP4:%.]] = load i32, i32 [[N_CASTED]], align 4			// CHECK2-NEXT: [[TMP4:%.]] = load i32, i32 [[N_CASTED]], align 4
	// CHECK2-NEXT: [[TMP5:%.]] = load i32, i32 [[L_ADDR]], align 4			// CHECK2-NEXT: [[TMP5:%.]] = load i32, i32 [[L_ADDR]], align 4
	// CHECK2-NEXT: store i32 [[TMP5]], i32* [[L_CASTED]], align 4			// CHECK2-NEXT: store i32 [[TMP5]], i32* [[L_CASTED]], align 4
	// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[L_CASTED]], align 4			// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[L_CASTED]], align 4
	// CHECK2-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4			// CHECK2-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4			// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4
	// CHECK2-NEXT: call void @__omp_outlined__(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i32 [[TMP4]], [1000 x i32]* [[TMP0]], i32 [[TMP6]]) #[[ATTR2:[0-9]+]]			// CHECK2-NEXT: call void @__omp_outlined__(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i32 [[TMP4]], [1000 x i32]* [[TMP0]], i32 [[TMP6]]) #[[ATTR2:[0-9]+]]
	// CHECK2-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 false)			// CHECK2-NEXT: call void @__kmpc_target_deinit(i1 false)
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	// CHECK2: worker.exit:			// CHECK2: worker.exit:
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__			// CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__
	// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i32 [[N:%.]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.]], i32 [[L:%.]]) #[[ATTR0]] {			// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i32 [[N:%.]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.]], i32 [[L:%.]]) #[[ATTR0]] {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
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	// CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4			// CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
	// CHECK2-NEXT: [[AA_ADDR:%.]] = alloca [1000 x i16], align 4			// CHECK2-NEXT: [[AA_ADDR:%.]] = alloca [1000 x i16], align 4
	// CHECK2-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4			// CHECK2-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4
	// CHECK2-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			// CHECK2-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	// CHECK2-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4			// CHECK2-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
	// CHECK2-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4			// CHECK2-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
	// CHECK2-NEXT: store [1000 x i16]* [[AA]], [1000 x i16]** [[AA_ADDR]], align 4			// CHECK2-NEXT: store [1000 x i16]* [[AA]], [1000 x i16]** [[AA_ADDR]], align 4
	// CHECK2-NEXT: [[TMP0:%.]] = load [1000 x i16], [1000 x i16]** [[AA_ADDR]], align 4			// CHECK2-NEXT: [[TMP0:%.]] = load [1000 x i16], [1000 x i16]** [[AA_ADDR]], align 4
	// CHECK2-NEXT: [[TMP1:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 2, i1 false, i1 false)			// CHECK2-NEXT: [[TMP1:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l32_kernel_info, i1 false)
	// CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1			// CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
	// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]			// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
	// CHECK2: user_code.entry:			// CHECK2: user_code.entry:
	// CHECK2-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB4]])			// CHECK2-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB4]])
	// CHECK2-NEXT: [[TMP3:%.]] = load i32, i32 [[N_ADDR]], align 4			// CHECK2-NEXT: [[TMP3:%.]] = load i32, i32 [[N_ADDR]], align 4
	// CHECK2-NEXT: store i32 [[TMP3]], i32* [[N_CASTED]], align 4			// CHECK2-NEXT: store i32 [[TMP3]], i32* [[N_CASTED]], align 4
	// CHECK2-NEXT: [[TMP4:%.]] = load i32, i32 [[N_CASTED]], align 4			// CHECK2-NEXT: [[TMP4:%.]] = load i32, i32 [[N_CASTED]], align 4
	// CHECK2-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4			// CHECK2-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4			// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4
	// CHECK2-NEXT: call void @__omp_outlined__2(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i32 [[TMP4]], [1000 x i16]* [[TMP0]]) #[[ATTR2]]			// CHECK2-NEXT: call void @__omp_outlined__2(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i32 [[TMP4]], [1000 x i16]* [[TMP0]]) #[[ATTR2]]
	// CHECK2-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 false)			// CHECK2-NEXT: call void @__kmpc_target_deinit(i1 false)
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	// CHECK2: worker.exit:			// CHECK2: worker.exit:
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__2			// CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__2
	// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i32 [[N:%.]], [1000 x i16]* nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR0]] {			// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i32 [[N:%.]], [1000 x i16]* nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR0]] {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	▲ Show 20 Lines • Show All 241 Lines • ▼ Show 20 Lines
	// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l37			// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l37
	// CHECK2-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {			// CHECK2-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	// CHECK2-NEXT: [[B_ADDR:%.]] = alloca [10 x i32], align 4			// CHECK2-NEXT: [[B_ADDR:%.]] = alloca [10 x i32], align 4
	// CHECK2-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			// CHECK2-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	// CHECK2-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4			// CHECK2-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
	// CHECK2-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4			// CHECK2-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
	// CHECK2-NEXT: [[TMP0:%.]] = load [10 x i32], [10 x i32]** [[B_ADDR]], align 4			// CHECK2-NEXT: [[TMP0:%.]] = load [10 x i32], [10 x i32]** [[B_ADDR]], align 4
	// CHECK2-NEXT: [[TMP1:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 2, i1 false, i1 false)			// CHECK2-NEXT: [[TMP1:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l37_kernel_info, i1 false)
	// CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1			// CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
	// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]			// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
	// CHECK2: user_code.entry:			// CHECK2: user_code.entry:
	// CHECK2-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB4]])			// CHECK2-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB4]])
	// CHECK2-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4			// CHECK2-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4			// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4
	// CHECK2-NEXT: call void @__omp_outlined__4(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], [10 x i32]* [[TMP0]]) #[[ATTR2]]			// CHECK2-NEXT: call void @__omp_outlined__4(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], [10 x i32]* [[TMP0]]) #[[ATTR2]]
	// CHECK2-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 false)			// CHECK2-NEXT: call void @__kmpc_target_deinit(i1 false)
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	// CHECK2: worker.exit:			// CHECK2: worker.exit:
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__4			// CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__4
	// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], [10 x i32] nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {			// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], [10 x i32] nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	▲ Show 20 Lines • Show All 173 Lines • ▼ Show 20 Lines
	// CHECK2-NEXT: [[C_ADDR:%.]] = alloca [10 x [10 x i32]], align 4			// CHECK2-NEXT: [[C_ADDR:%.]] = alloca [10 x [10 x i32]], align 4
	// CHECK2-NEXT: [[F_ADDR:%.*]] = alloca i32, align 4			// CHECK2-NEXT: [[F_ADDR:%.*]] = alloca i32, align 4
	// CHECK2-NEXT: [[F_CASTED:%.*]] = alloca i32, align 4			// CHECK2-NEXT: [[F_CASTED:%.*]] = alloca i32, align 4
	// CHECK2-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			// CHECK2-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	// CHECK2-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4			// CHECK2-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
	// CHECK2-NEXT: store [10 x [10 x i32]]* [[C]], [10 x [10 x i32]]** [[C_ADDR]], align 4			// CHECK2-NEXT: store [10 x [10 x i32]]* [[C]], [10 x [10 x i32]]** [[C_ADDR]], align 4
	// CHECK2-NEXT: store i32 [[F]], i32* [[F_ADDR]], align 4			// CHECK2-NEXT: store i32 [[F]], i32* [[F_ADDR]], align 4
	// CHECK2-NEXT: [[TMP0:%.]] = load [10 x [10 x i32]], [10 x [10 x i32]]** [[C_ADDR]], align 4			// CHECK2-NEXT: [[TMP0:%.]] = load [10 x [10 x i32]], [10 x [10 x i32]]** [[C_ADDR]], align 4
	// CHECK2-NEXT: [[TMP1:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 2, i1 false, i1 false)			// CHECK2-NEXT: [[TMP1:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l42_kernel_info, i1 false)
	// CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1			// CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
	// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]			// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
	// CHECK2: user_code.entry:			// CHECK2: user_code.entry:
	// CHECK2-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB4]])			// CHECK2-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB4]])
	// CHECK2-NEXT: [[TMP3:%.]] = load i32, i32 [[F_ADDR]], align 4			// CHECK2-NEXT: [[TMP3:%.]] = load i32, i32 [[F_ADDR]], align 4
	// CHECK2-NEXT: store i32 [[TMP3]], i32* [[F_CASTED]], align 4			// CHECK2-NEXT: store i32 [[TMP3]], i32* [[F_CASTED]], align 4
	// CHECK2-NEXT: [[TMP4:%.]] = load i32, i32 [[F_CASTED]], align 4			// CHECK2-NEXT: [[TMP4:%.]] = load i32, i32 [[F_CASTED]], align 4
	// CHECK2-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4			// CHECK2-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4			// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4
	// CHECK2-NEXT: call void @__omp_outlined__6(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], [10 x [10 x i32]]* [[TMP0]], i32 [[TMP4]]) #[[ATTR2]]			// CHECK2-NEXT: call void @__omp_outlined__6(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], [10 x [10 x i32]]* [[TMP0]], i32 [[TMP4]]) #[[ATTR2]]
	// CHECK2-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 false)			// CHECK2-NEXT: call void @__kmpc_target_deinit(i1 false)
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	// CHECK2: worker.exit:			// CHECK2: worker.exit:
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__6			// CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__6
	// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], [10 x [10 x i32]] nonnull align 4 dereferenceable(400) [[C:%.]], i32 [[F:%.]]) #[[ATTR0]] {			// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], [10 x [10 x i32]] nonnull align 4 dereferenceable(400) [[C:%.]], i32 [[F:%.]]) #[[ATTR0]] {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	▲ Show 20 Lines • Show All 212 Lines • ▼ Show 20 Lines
	// CHECK3-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4			// CHECK3-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4
	// CHECK3-NEXT: [[L_CASTED:%.*]] = alloca i32, align 4			// CHECK3-NEXT: [[L_CASTED:%.*]] = alloca i32, align 4
	// CHECK3-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			// CHECK3-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	// CHECK3-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4			// CHECK3-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
	// CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4			// CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
	// CHECK3-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 4			// CHECK3-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 4
	// CHECK3-NEXT: store i32 [[L]], i32* [[L_ADDR]], align 4			// CHECK3-NEXT: store i32 [[L]], i32* [[L_ADDR]], align 4
	// CHECK3-NEXT: [[TMP0:%.]] = load [1000 x i32], [1000 x i32]** [[A_ADDR]], align 4			// CHECK3-NEXT: [[TMP0:%.]] = load [1000 x i32], [1000 x i32]** [[A_ADDR]], align 4
	// CHECK3-NEXT: [[TMP1:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1:[0-9]+]], i8 2, i1 false, i1 false)			// CHECK3-NEXT: [[TMP1:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l26_kernel_info, i1 false)
	// CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1			// CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
	// CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]			// CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
	// CHECK3: user_code.entry:			// CHECK3: user_code.entry:
	// CHECK3-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB4:[0-9]+]])			// CHECK3-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB4:[0-9]+]])
	// CHECK3-NEXT: [[TMP3:%.]] = load i32, i32 [[N_ADDR]], align 4			// CHECK3-NEXT: [[TMP3:%.]] = load i32, i32 [[N_ADDR]], align 4
	// CHECK3-NEXT: store i32 [[TMP3]], i32* [[N_CASTED]], align 4			// CHECK3-NEXT: store i32 [[TMP3]], i32* [[N_CASTED]], align 4
	// CHECK3-NEXT: [[TMP4:%.]] = load i32, i32 [[N_CASTED]], align 4			// CHECK3-NEXT: [[TMP4:%.]] = load i32, i32 [[N_CASTED]], align 4
	// CHECK3-NEXT: [[TMP5:%.]] = load i32, i32 [[L_ADDR]], align 4			// CHECK3-NEXT: [[TMP5:%.]] = load i32, i32 [[L_ADDR]], align 4
	// CHECK3-NEXT: store i32 [[TMP5]], i32* [[L_CASTED]], align 4			// CHECK3-NEXT: store i32 [[TMP5]], i32* [[L_CASTED]], align 4
	// CHECK3-NEXT: [[TMP6:%.]] = load i32, i32 [[L_CASTED]], align 4			// CHECK3-NEXT: [[TMP6:%.]] = load i32, i32 [[L_CASTED]], align 4
	// CHECK3-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4			// CHECK3-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	// CHECK3-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4			// CHECK3-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4
	// CHECK3-NEXT: call void @__omp_outlined__(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i32 [[TMP4]], [1000 x i32]* [[TMP0]], i32 [[TMP6]]) #[[ATTR2:[0-9]+]]			// CHECK3-NEXT: call void @__omp_outlined__(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i32 [[TMP4]], [1000 x i32]* [[TMP0]], i32 [[TMP6]]) #[[ATTR2:[0-9]+]]
	// CHECK3-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 false)			// CHECK3-NEXT: call void @__kmpc_target_deinit(i1 false)
	// CHECK3-NEXT: ret void			// CHECK3-NEXT: ret void
	// CHECK3: worker.exit:			// CHECK3: worker.exit:
	// CHECK3-NEXT: ret void			// CHECK3-NEXT: ret void
	//			//
	//			//
	// CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__			// CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__
	// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i32 [[N:%.]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.]], i32 [[L:%.]]) #[[ATTR0]] {			// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i32 [[N:%.]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.]], i32 [[L:%.]]) #[[ATTR0]] {
	// CHECK3-NEXT: entry:			// CHECK3-NEXT: entry:
	▲ Show 20 Lines • Show All 300 Lines • ▼ Show 20 Lines
	// CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4			// CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
	// CHECK3-NEXT: [[AA_ADDR:%.]] = alloca [1000 x i16], align 4			// CHECK3-NEXT: [[AA_ADDR:%.]] = alloca [1000 x i16], align 4
	// CHECK3-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4			// CHECK3-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4
	// CHECK3-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			// CHECK3-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	// CHECK3-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4			// CHECK3-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
	// CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4			// CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
	// CHECK3-NEXT: store [1000 x i16]* [[AA]], [1000 x i16]** [[AA_ADDR]], align 4			// CHECK3-NEXT: store [1000 x i16]* [[AA]], [1000 x i16]** [[AA_ADDR]], align 4
	// CHECK3-NEXT: [[TMP0:%.]] = load [1000 x i16], [1000 x i16]** [[AA_ADDR]], align 4			// CHECK3-NEXT: [[TMP0:%.]] = load [1000 x i16], [1000 x i16]** [[AA_ADDR]], align 4
	// CHECK3-NEXT: [[TMP1:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 2, i1 false, i1 false)			// CHECK3-NEXT: [[TMP1:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l32_kernel_info, i1 false)
	// CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1			// CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
	// CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]			// CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
	// CHECK3: user_code.entry:			// CHECK3: user_code.entry:
	// CHECK3-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB4]])			// CHECK3-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB4]])
	// CHECK3-NEXT: [[TMP3:%.]] = load i32, i32 [[N_ADDR]], align 4			// CHECK3-NEXT: [[TMP3:%.]] = load i32, i32 [[N_ADDR]], align 4
	// CHECK3-NEXT: store i32 [[TMP3]], i32* [[N_CASTED]], align 4			// CHECK3-NEXT: store i32 [[TMP3]], i32* [[N_CASTED]], align 4
	// CHECK3-NEXT: [[TMP4:%.]] = load i32, i32 [[N_CASTED]], align 4			// CHECK3-NEXT: [[TMP4:%.]] = load i32, i32 [[N_CASTED]], align 4
	// CHECK3-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4			// CHECK3-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	// CHECK3-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4			// CHECK3-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4
	// CHECK3-NEXT: call void @__omp_outlined__2(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i32 [[TMP4]], [1000 x i16]* [[TMP0]]) #[[ATTR2]]			// CHECK3-NEXT: call void @__omp_outlined__2(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i32 [[TMP4]], [1000 x i16]* [[TMP0]]) #[[ATTR2]]
	// CHECK3-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 false)			// CHECK3-NEXT: call void @__kmpc_target_deinit(i1 false)
	// CHECK3-NEXT: ret void			// CHECK3-NEXT: ret void
	// CHECK3: worker.exit:			// CHECK3: worker.exit:
	// CHECK3-NEXT: ret void			// CHECK3-NEXT: ret void
	//			//
	//			//
	// CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__2			// CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__2
	// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i32 [[N:%.]], [1000 x i16]* nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR0]] {			// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i32 [[N:%.]], [1000 x i16]* nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR0]] {
	// CHECK3-NEXT: entry:			// CHECK3-NEXT: entry:
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	// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l37			// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l37
	// CHECK3-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {			// CHECK3-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
	// CHECK3-NEXT: entry:			// CHECK3-NEXT: entry:
	// CHECK3-NEXT: [[B_ADDR:%.]] = alloca [10 x i32], align 4			// CHECK3-NEXT: [[B_ADDR:%.]] = alloca [10 x i32], align 4
	// CHECK3-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			// CHECK3-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	// CHECK3-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4			// CHECK3-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
	// CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4			// CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
	// CHECK3-NEXT: [[TMP0:%.]] = load [10 x i32], [10 x i32]** [[B_ADDR]], align 4			// CHECK3-NEXT: [[TMP0:%.]] = load [10 x i32], [10 x i32]** [[B_ADDR]], align 4
	// CHECK3-NEXT: [[TMP1:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 2, i1 false, i1 false)			// CHECK3-NEXT: [[TMP1:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l37_kernel_info, i1 false)
	// CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1			// CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
	// CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]			// CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
	// CHECK3: user_code.entry:			// CHECK3: user_code.entry:
	// CHECK3-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB4]])			// CHECK3-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB4]])
	// CHECK3-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4			// CHECK3-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	// CHECK3-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4			// CHECK3-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4
	// CHECK3-NEXT: call void @__omp_outlined__4(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], [10 x i32]* [[TMP0]]) #[[ATTR2]]			// CHECK3-NEXT: call void @__omp_outlined__4(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], [10 x i32]* [[TMP0]]) #[[ATTR2]]
	// CHECK3-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 false)			// CHECK3-NEXT: call void @__kmpc_target_deinit(i1 false)
	// CHECK3-NEXT: ret void			// CHECK3-NEXT: ret void
	// CHECK3: worker.exit:			// CHECK3: worker.exit:
	// CHECK3-NEXT: ret void			// CHECK3-NEXT: ret void
	//			//
	//			//
	// CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__4			// CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__4
	// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], [10 x i32] nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {			// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], [10 x i32] nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
	// CHECK3-NEXT: entry:			// CHECK3-NEXT: entry:
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	// CHECK3-NEXT: [[C_ADDR:%.]] = alloca [10 x [10 x i32]], align 4			// CHECK3-NEXT: [[C_ADDR:%.]] = alloca [10 x [10 x i32]], align 4
	// CHECK3-NEXT: [[F_ADDR:%.*]] = alloca i32, align 4			// CHECK3-NEXT: [[F_ADDR:%.*]] = alloca i32, align 4
	// CHECK3-NEXT: [[F_CASTED:%.*]] = alloca i32, align 4			// CHECK3-NEXT: [[F_CASTED:%.*]] = alloca i32, align 4
	// CHECK3-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			// CHECK3-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	// CHECK3-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4			// CHECK3-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
	// CHECK3-NEXT: store [10 x [10 x i32]]* [[C]], [10 x [10 x i32]]** [[C_ADDR]], align 4			// CHECK3-NEXT: store [10 x [10 x i32]]* [[C]], [10 x [10 x i32]]** [[C_ADDR]], align 4
	// CHECK3-NEXT: store i32 [[F]], i32* [[F_ADDR]], align 4			// CHECK3-NEXT: store i32 [[F]], i32* [[F_ADDR]], align 4
	// CHECK3-NEXT: [[TMP0:%.]] = load [10 x [10 x i32]], [10 x [10 x i32]]** [[C_ADDR]], align 4			// CHECK3-NEXT: [[TMP0:%.]] = load [10 x [10 x i32]], [10 x [10 x i32]]** [[C_ADDR]], align 4
	// CHECK3-NEXT: [[TMP1:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 2, i1 false, i1 false)			// CHECK3-NEXT: [[TMP1:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l42_kernel_info, i1 false)
	// CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1			// CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
	// CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]			// CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
	// CHECK3: user_code.entry:			// CHECK3: user_code.entry:
	// CHECK3-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB4]])			// CHECK3-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB4]])
	// CHECK3-NEXT: [[TMP3:%.]] = load i32, i32 [[F_ADDR]], align 4			// CHECK3-NEXT: [[TMP3:%.]] = load i32, i32 [[F_ADDR]], align 4
	// CHECK3-NEXT: store i32 [[TMP3]], i32* [[F_CASTED]], align 4			// CHECK3-NEXT: store i32 [[TMP3]], i32* [[F_CASTED]], align 4
	// CHECK3-NEXT: [[TMP4:%.]] = load i32, i32 [[F_CASTED]], align 4			// CHECK3-NEXT: [[TMP4:%.]] = load i32, i32 [[F_CASTED]], align 4
	// CHECK3-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4			// CHECK3-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	// CHECK3-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4			// CHECK3-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4
	// CHECK3-NEXT: call void @__omp_outlined__6(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], [10 x [10 x i32]]* [[TMP0]], i32 [[TMP4]]) #[[ATTR2]]			// CHECK3-NEXT: call void @__omp_outlined__6(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], [10 x [10 x i32]]* [[TMP0]], i32 [[TMP4]]) #[[ATTR2]]
	// CHECK3-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 false)			// CHECK3-NEXT: call void @__kmpc_target_deinit(i1 false)
	// CHECK3-NEXT: ret void			// CHECK3-NEXT: ret void
	// CHECK3: worker.exit:			// CHECK3: worker.exit:
	// CHECK3-NEXT: ret void			// CHECK3-NEXT: ret void
	//			//
	//			//
	// CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__6			// CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__6
	// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], [10 x [10 x i32]] nonnull align 4 dereferenceable(400) [[C:%.]], i32 [[F:%.]]) #[[ATTR0]] {			// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], [10 x [10 x i32]] nonnull align 4 dereferenceable(400) [[C:%.]], i32 [[F:%.]]) #[[ATTR0]] {
	// CHECK3-NEXT: entry:			// CHECK3-NEXT: entry:
	▲ Show 20 Lines • Show All 205 Lines • Show Last 20 Lines

clang/test/OpenMP/nvptx_target_teams_distribute_simd_codegen.cpp

Show First 20 Lines • Show All 64 Lines • ▼ Show 20 Lines	int bar(int n){
int a = 0;		int a = 0;

a += ftemplate<int>(n);		a += ftemplate<int>(n);

return a;		return a;
}		}

// CHECK-LABEL: define {{.*}}void {{@__omp_offloading_.+}}_l37(		// CHECK-LABEL: define {{.*}}void {{@__omp_offloading_.+}}_l37(
// CHECK: call i32 @__kmpc_target_init({{.*}}, i8 2, i1 false, i1 false)		// CHECK: call i32 @__kmpc_target_init({{.*}}, i1 false)
// CHECK: call void @__kmpc_target_deinit({{.*}}, i8 2, i1 false)		// CHECK: call void @__kmpc_target_deinit(i1 false)

// CHECK: call void @__kmpc_distribute_static_init_4({{.+}}, {{.+}}, {{.+}} 91,		// CHECK: call void @__kmpc_distribute_static_init_4({{.+}}, {{.+}}, {{.+}} 91,
// CHECK: call void @__kmpc_distribute_static_fini(		// CHECK: call void @__kmpc_distribute_static_fini(
// CHECK: ret void		// CHECK: ret void

// CHECK-LABEL: define {{.*}}void {{@__omp_offloading_.+}}_l43(		// CHECK-LABEL: define {{.*}}void {{@__omp_offloading_.+}}_l43(
// CHECK: call i32 @__kmpc_target_init({{.*}}, i8 2, i1 false, i1 false)		// CHECK: call i32 @__kmpc_target_init({{.*}}, i1 false)
// CHECK: call void @__kmpc_target_deinit({{.*}}, i8 2, i1 false)		// CHECK: call void @__kmpc_target_deinit(i1 false)

// CHECK: call void @__kmpc_distribute_static_init_4({{.+}}, {{.+}}, {{.+}} 91,		// CHECK: call void @__kmpc_distribute_static_init_4({{.+}}, {{.+}}, {{.+}} 91,
// CHECK: call void @__kmpc_distribute_static_fini(		// CHECK: call void @__kmpc_distribute_static_fini(
// CHECK: ret void		// CHECK: ret void

// CHECK-LABEL: define {{.*}}void {{@__omp_offloading_.+}}_l48(		// CHECK-LABEL: define {{.*}}void {{@__omp_offloading_.+}}_l48(
// CHECK: call i32 @__kmpc_target_init({{.*}}, i8 2, i1 false, i1 false)		// CHECK: call i32 @__kmpc_target_init({{.*}}, i1 false)
// CHECK: call void @__kmpc_target_deinit({{.*}}, i8 2, i1 false)		// CHECK: call void @__kmpc_target_deinit(i1 false)

// CHECK: call void @__kmpc_distribute_static_init_4({{.+}}, {{.+}}, {{.+}} 91,		// CHECK: call void @__kmpc_distribute_static_init_4({{.+}}, {{.+}}, {{.+}} 91,
// CHECK: call void @__kmpc_distribute_static_fini(		// CHECK: call void @__kmpc_distribute_static_fini(
// CHECK: ret void		// CHECK: ret void

// CHECK: define {{.*}}void {{@__omp_offloading_.+}}_l53({{.+}}, i{{32\|64}} [[F_IN:%.+]])		// CHECK: define {{.*}}void {{@__omp_offloading_.+}}_l53({{.+}}, i{{32\|64}} [[F_IN:%.+]])
// CHECK: store {{.+}} [[F_IN]], {{.+}}* {{.+}},		// CHECK: store {{.+}} [[F_IN]], {{.+}}* {{.+}},
// CHECK: call i32 @__kmpc_target_init({{.*}}, i8 2, i1 false, i1 false)		// CHECK: call i32 @__kmpc_target_init({{.*}}, i1 false)
// CHECK: call void @__kmpc_target_deinit({{.*}}, i8 2, i1 false)		// CHECK: call void @__kmpc_target_deinit(i1 false)

// CHECK: store {{.+}} 99, {{.+}}* [[COMB_UB:%.+]], align		// CHECK: store {{.+}} 99, {{.+}}* [[COMB_UB:%.+]], align
// CHECK: call void @__kmpc_distribute_static_init_4({{.+}}, {{.+}}, {{.+}} 91, {{.+}}, {{.+}}, {{.+}}* [[COMB_UB]],		// CHECK: call void @__kmpc_distribute_static_init_4({{.+}}, {{.+}}, {{.+}} 91, {{.+}}, {{.+}}, {{.+}}* [[COMB_UB]],
// CHECK: call void @__kmpc_distribute_static_fini(		// CHECK: call void @__kmpc_distribute_static_fini(
// CHECK: ret void		// CHECK: ret void

#endif		#endif

clang/test/OpenMP/nvptx_teams_codegen.cpp

	Show First 20 Lines • Show All 892 Lines • ▼ Show 20 Lines
	// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l23			// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l23
	// CHECK1-SAME: (i64 [[ARGC:%.*]]) #[[ATTR0:[0-9]+]] {			// CHECK1-SAME: (i64 [[ARGC:%.*]]) #[[ATTR0:[0-9]+]] {
	// CHECK1-NEXT: entry:			// CHECK1-NEXT: entry:
	// CHECK1-NEXT: [[ARGC_ADDR:%.*]] = alloca i64, align 8			// CHECK1-NEXT: [[ARGC_ADDR:%.*]] = alloca i64, align 8
	// CHECK1-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			// CHECK1-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	// CHECK1-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4			// CHECK1-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
	// CHECK1-NEXT: store i64 [[ARGC]], i64* [[ARGC_ADDR]], align 8			// CHECK1-NEXT: store i64 [[ARGC]], i64* [[ARGC_ADDR]], align 8
	// CHECK1-NEXT: [[CONV:%.]] = bitcast i64 [[ARGC_ADDR]] to i32*			// CHECK1-NEXT: [[CONV:%.]] = bitcast i64 [[ARGC_ADDR]] to i32*
	// CHECK1-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1:[0-9]+]], i8 1, i1 true, i1 true)			// CHECK1-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l23_kernel_info, i1 true)
	// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1			// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
	// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]			// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
	// CHECK1: user_code.entry:			// CHECK1: user_code.entry:
	// CHECK1-NEXT: [[TMP1:%.]] = load i32, i32 [[CONV]], align 4			// CHECK1-NEXT: [[TMP1:%.]] = load i32, i32 [[CONV]], align 4
	// CHECK1-NEXT: [[ARGC1:%.]] = call align 8 i8 @__kmpc_alloc_shared(i64 4)			// CHECK1-NEXT: [[ARGC1:%.]] = call align 8 i8 @__kmpc_alloc_shared(i64 4)
	// CHECK1-NEXT: [[ARGC_ON_STACK:%.]] = bitcast i8 [[ARGC1]] to i32*			// CHECK1-NEXT: [[ARGC_ON_STACK:%.]] = bitcast i8 [[ARGC1]] to i32*
	// CHECK1-NEXT: store i32 [[TMP1]], i32* [[ARGC_ON_STACK]], align 4			// CHECK1-NEXT: store i32 [[TMP1]], i32* [[ARGC_ON_STACK]], align 4
	// CHECK1-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB1]])			// CHECK1-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB1:[0-9]+]])
	// CHECK1-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4			// CHECK1-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4			// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4
	// CHECK1-NEXT: call void @__omp_outlined__(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i32* [[ARGC_ON_STACK]]) #[[ATTR2:[0-9]+]]			// CHECK1-NEXT: call void @__omp_outlined__(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i32* [[ARGC_ON_STACK]]) #[[ATTR2:[0-9]+]]
	// CHECK1-NEXT: call void @__kmpc_free_shared(i8* [[ARGC1]], i64 4)			// CHECK1-NEXT: call void @__kmpc_free_shared(i8* [[ARGC1]], i64 4)
	// CHECK1-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true)			// CHECK1-NEXT: call void @__kmpc_target_deinit(i1 true)
	// CHECK1-NEXT: ret void			// CHECK1-NEXT: ret void
	// CHECK1: worker.exit:			// CHECK1: worker.exit:
	// CHECK1-NEXT: ret void			// CHECK1-NEXT: ret void
	//			//
	//			//
	// CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__			// CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__
	// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i32 nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR0]] {			// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i32 nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR0]] {
	// CHECK1-NEXT: entry:			// CHECK1-NEXT: entry:
	Show All 10 Lines
	//			//
	// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIPPcEiT__l15			// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIPPcEiT__l15
	// CHECK1-SAME: (i8** [[ARGC:%.*]]) #[[ATTR0]] {			// CHECK1-SAME: (i8** [[ARGC:%.*]]) #[[ATTR0]] {
	// CHECK1-NEXT: entry:			// CHECK1-NEXT: entry:
	// CHECK1-NEXT: [[ARGC_ADDR:%.]] = alloca i8*, align 8			// CHECK1-NEXT: [[ARGC_ADDR:%.]] = alloca i8*, align 8
	// CHECK1-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			// CHECK1-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	// CHECK1-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4			// CHECK1-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
	// CHECK1-NEXT: store i8 [[ARGC]], i8* [[ARGC_ADDR]], align 8			// CHECK1-NEXT: store i8 [[ARGC]], i8* [[ARGC_ADDR]], align 8
	// CHECK1-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 1, i1 true, i1 true)			// CHECK1-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIPPcEiT__l15_kernel_info, i1 true)
	// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1			// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
	// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]			// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
	// CHECK1: user_code.entry:			// CHECK1: user_code.entry:
	// CHECK1-NEXT: [[TMP1:%.]] = load i8, i8** [[ARGC_ADDR]], align 8			// CHECK1-NEXT: [[TMP1:%.]] = load i8, i8** [[ARGC_ADDR]], align 8
	// CHECK1-NEXT: [[ARGC1:%.]] = call align 8 i8 @__kmpc_alloc_shared(i64 8)			// CHECK1-NEXT: [[ARGC1:%.]] = call align 8 i8 @__kmpc_alloc_shared(i64 8)
	// CHECK1-NEXT: [[ARGC_ON_STACK:%.]] = bitcast i8 [[ARGC1]] to i8***			// CHECK1-NEXT: [[ARGC_ON_STACK:%.]] = bitcast i8 [[ARGC1]] to i8***
	// CHECK1-NEXT: store i8 [[TMP1]], i8* [[ARGC_ON_STACK]], align 8			// CHECK1-NEXT: store i8 [[TMP1]], i8* [[ARGC_ON_STACK]], align 8
	// CHECK1-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB1]])			// CHECK1-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB1]])
	// CHECK1-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4			// CHECK1-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4			// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4
	// CHECK1-NEXT: call void @__omp_outlined__1(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i8*** [[ARGC_ON_STACK]]) #[[ATTR2]]			// CHECK1-NEXT: call void @__omp_outlined__1(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i8*** [[ARGC_ON_STACK]]) #[[ATTR2]]
	// CHECK1-NEXT: call void @__kmpc_free_shared(i8* [[ARGC1]], i64 8)			// CHECK1-NEXT: call void @__kmpc_free_shared(i8* [[ARGC1]], i64 8)
	// CHECK1-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true)			// CHECK1-NEXT: call void @__kmpc_target_deinit(i1 true)
	// CHECK1-NEXT: ret void			// CHECK1-NEXT: ret void
	// CHECK1: worker.exit:			// CHECK1: worker.exit:
	// CHECK1-NEXT: ret void			// CHECK1-NEXT: ret void
	//			//
	//			//
	// CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__1			// CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__1
	// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i8** nonnull align 8 dereferenceable(8) [[ARGC:%.*]]) #[[ATTR0]] {			// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i8** nonnull align 8 dereferenceable(8) [[ARGC:%.*]]) #[[ATTR0]] {
	// CHECK1-NEXT: entry:			// CHECK1-NEXT: entry:
	Show All 10 Lines
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l23			// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l23
	// CHECK2-SAME: (i32 [[ARGC:%.*]]) #[[ATTR0:[0-9]+]] {			// CHECK2-SAME: (i32 [[ARGC:%.*]]) #[[ATTR0:[0-9]+]] {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	// CHECK2-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4			// CHECK2-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4
	// CHECK2-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			// CHECK2-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	// CHECK2-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4			// CHECK2-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
	// CHECK2-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4			// CHECK2-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4
	// CHECK2-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1:[0-9]+]], i8 1, i1 true, i1 true)			// CHECK2-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l23_kernel_info, i1 true)
	// CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1			// CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
	// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]			// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
	// CHECK2: user_code.entry:			// CHECK2: user_code.entry:
	// CHECK2-NEXT: [[TMP1:%.]] = load i32, i32 [[ARGC_ADDR]], align 4			// CHECK2-NEXT: [[TMP1:%.]] = load i32, i32 [[ARGC_ADDR]], align 4
	// CHECK2-NEXT: [[ARGC1:%.]] = call align 8 i8 @__kmpc_alloc_shared(i32 4)			// CHECK2-NEXT: [[ARGC1:%.]] = call align 8 i8 @__kmpc_alloc_shared(i32 4)
	// CHECK2-NEXT: [[ARGC_ON_STACK:%.]] = bitcast i8 [[ARGC1]] to i32*			// CHECK2-NEXT: [[ARGC_ON_STACK:%.]] = bitcast i8 [[ARGC1]] to i32*
	// CHECK2-NEXT: store i32 [[TMP1]], i32* [[ARGC_ON_STACK]], align 4			// CHECK2-NEXT: store i32 [[TMP1]], i32* [[ARGC_ON_STACK]], align 4
	// CHECK2-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB1]])			// CHECK2-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB1:[0-9]+]])
	// CHECK2-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4			// CHECK2-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4			// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4
	// CHECK2-NEXT: call void @__omp_outlined__(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i32* [[ARGC_ON_STACK]]) #[[ATTR2:[0-9]+]]			// CHECK2-NEXT: call void @__omp_outlined__(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i32* [[ARGC_ON_STACK]]) #[[ATTR2:[0-9]+]]
	// CHECK2-NEXT: call void @__kmpc_free_shared(i8* [[ARGC1]], i32 4)			// CHECK2-NEXT: call void @__kmpc_free_shared(i8* [[ARGC1]], i32 4)
	// CHECK2-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true)			// CHECK2-NEXT: call void @__kmpc_target_deinit(i1 true)
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	// CHECK2: worker.exit:			// CHECK2: worker.exit:
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__			// CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__
	// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i32 nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR0]] {			// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i32 nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR0]] {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	Show All 10 Lines
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIPPcEiT__l15			// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIPPcEiT__l15
	// CHECK2-SAME: (i8** [[ARGC:%.*]]) #[[ATTR0]] {			// CHECK2-SAME: (i8** [[ARGC:%.*]]) #[[ATTR0]] {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	// CHECK2-NEXT: [[ARGC_ADDR:%.]] = alloca i8*, align 4			// CHECK2-NEXT: [[ARGC_ADDR:%.]] = alloca i8*, align 4
	// CHECK2-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			// CHECK2-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	// CHECK2-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4			// CHECK2-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
	// CHECK2-NEXT: store i8 [[ARGC]], i8* [[ARGC_ADDR]], align 4			// CHECK2-NEXT: store i8 [[ARGC]], i8* [[ARGC_ADDR]], align 4
	// CHECK2-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 1, i1 true, i1 true)			// CHECK2-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIPPcEiT__l15_kernel_info, i1 true)
	// CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1			// CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
	// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]			// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
	// CHECK2: user_code.entry:			// CHECK2: user_code.entry:
	// CHECK2-NEXT: [[TMP1:%.]] = load i8, i8** [[ARGC_ADDR]], align 4			// CHECK2-NEXT: [[TMP1:%.]] = load i8, i8** [[ARGC_ADDR]], align 4
	// CHECK2-NEXT: [[ARGC1:%.]] = call align 8 i8 @__kmpc_alloc_shared(i32 4)			// CHECK2-NEXT: [[ARGC1:%.]] = call align 8 i8 @__kmpc_alloc_shared(i32 4)
	// CHECK2-NEXT: [[ARGC_ON_STACK:%.]] = bitcast i8 [[ARGC1]] to i8***			// CHECK2-NEXT: [[ARGC_ON_STACK:%.]] = bitcast i8 [[ARGC1]] to i8***
	// CHECK2-NEXT: store i8 [[TMP1]], i8* [[ARGC_ON_STACK]], align 4			// CHECK2-NEXT: store i8 [[TMP1]], i8* [[ARGC_ON_STACK]], align 4
	// CHECK2-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB1]])			// CHECK2-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB1]])
	// CHECK2-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4			// CHECK2-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4			// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4
	// CHECK2-NEXT: call void @__omp_outlined__1(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i8*** [[ARGC_ON_STACK]]) #[[ATTR2]]			// CHECK2-NEXT: call void @__omp_outlined__1(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i8*** [[ARGC_ON_STACK]]) #[[ATTR2]]
	// CHECK2-NEXT: call void @__kmpc_free_shared(i8* [[ARGC1]], i32 4)			// CHECK2-NEXT: call void @__kmpc_free_shared(i8* [[ARGC1]], i32 4)
	// CHECK2-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true)			// CHECK2-NEXT: call void @__kmpc_target_deinit(i1 true)
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	// CHECK2: worker.exit:			// CHECK2: worker.exit:
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__1			// CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__1
	// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i8** nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR0]] {			// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i8** nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR0]] {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	Show All 17 Lines
	// CHECK3-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			// CHECK3-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	// CHECK3-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4			// CHECK3-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
	// CHECK3-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8			// CHECK3-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
	// CHECK3-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8			// CHECK3-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
	// CHECK3-NEXT: store i64 [[ARGC]], i64* [[ARGC_ADDR]], align 8			// CHECK3-NEXT: store i64 [[ARGC]], i64* [[ARGC_ADDR]], align 8
	// CHECK3-NEXT: [[CONV:%.]] = bitcast i64 [[A_ADDR]] to i32*			// CHECK3-NEXT: [[CONV:%.]] = bitcast i64 [[A_ADDR]] to i32*
	// CHECK3-NEXT: [[CONV1:%.]] = bitcast i64 [[B_ADDR]] to i32*			// CHECK3-NEXT: [[CONV1:%.]] = bitcast i64 [[B_ADDR]] to i32*
	// CHECK3-NEXT: [[CONV2:%.]] = bitcast i64 [[ARGC_ADDR]] to i32*			// CHECK3-NEXT: [[CONV2:%.]] = bitcast i64 [[ARGC_ADDR]] to i32*
	// CHECK3-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1:[0-9]+]], i8 1, i1 true, i1 true)			// CHECK3-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l64_kernel_info, i1 true)
	// CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1			// CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
	// CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]			// CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
	// CHECK3: user_code.entry:			// CHECK3: user_code.entry:
	// CHECK3-NEXT: [[TMP1:%.]] = load i32, i32 [[CONV2]], align 4			// CHECK3-NEXT: [[TMP1:%.]] = load i32, i32 [[CONV2]], align 4
	// CHECK3-NEXT: [[ARGC3:%.]] = call align 8 i8 @__kmpc_alloc_shared(i64 4)			// CHECK3-NEXT: [[ARGC3:%.]] = call align 8 i8 @__kmpc_alloc_shared(i64 4)
	// CHECK3-NEXT: [[ARGC_ON_STACK:%.]] = bitcast i8 [[ARGC3]] to i32*			// CHECK3-NEXT: [[ARGC_ON_STACK:%.]] = bitcast i8 [[ARGC3]] to i32*
	// CHECK3-NEXT: store i32 [[TMP1]], i32* [[ARGC_ON_STACK]], align 4			// CHECK3-NEXT: store i32 [[TMP1]], i32* [[ARGC_ON_STACK]], align 4
	// CHECK3-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB1]])			// CHECK3-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB1:[0-9]+]])
	// CHECK3-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4			// CHECK3-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	// CHECK3-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4			// CHECK3-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4
	// CHECK3-NEXT: call void @__omp_outlined__(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i32* [[ARGC_ON_STACK]]) #[[ATTR2:[0-9]+]]			// CHECK3-NEXT: call void @__omp_outlined__(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i32* [[ARGC_ON_STACK]]) #[[ATTR2:[0-9]+]]
	// CHECK3-NEXT: call void @__kmpc_free_shared(i8* [[ARGC3]], i64 4)			// CHECK3-NEXT: call void @__kmpc_free_shared(i8* [[ARGC3]], i64 4)
	// CHECK3-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true)			// CHECK3-NEXT: call void @__kmpc_target_deinit(i1 true)
	// CHECK3-NEXT: ret void			// CHECK3-NEXT: ret void
	// CHECK3: worker.exit:			// CHECK3: worker.exit:
	// CHECK3-NEXT: ret void			// CHECK3-NEXT: ret void
	//			//
	//			//
	// CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__			// CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__
	// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i32 nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR0]] {			// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i32 nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR0]] {
	// CHECK3-NEXT: entry:			// CHECK3-NEXT: entry:
	Show All 16 Lines
	// CHECK3-NEXT: [[ARGC_ADDR:%.]] = alloca i8*, align 8			// CHECK3-NEXT: [[ARGC_ADDR:%.]] = alloca i8*, align 8
	// CHECK3-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			// CHECK3-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	// CHECK3-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4			// CHECK3-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
	// CHECK3-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8			// CHECK3-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
	// CHECK3-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8			// CHECK3-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
	// CHECK3-NEXT: store i8 [[ARGC]], i8* [[ARGC_ADDR]], align 8			// CHECK3-NEXT: store i8 [[ARGC]], i8* [[ARGC_ADDR]], align 8
	// CHECK3-NEXT: [[CONV:%.]] = bitcast i64 [[A_ADDR]] to i32*			// CHECK3-NEXT: [[CONV:%.]] = bitcast i64 [[A_ADDR]] to i32*
	// CHECK3-NEXT: [[CONV1:%.]] = bitcast i64 [[B_ADDR]] to i32*			// CHECK3-NEXT: [[CONV1:%.]] = bitcast i64 [[B_ADDR]] to i32*
	// CHECK3-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 1, i1 true, i1 true)			// CHECK3-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIPPcEiT__l53_kernel_info, i1 true)
	// CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1			// CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
	// CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]			// CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
	// CHECK3: user_code.entry:			// CHECK3: user_code.entry:
	// CHECK3-NEXT: [[TMP1:%.]] = load i8, i8** [[ARGC_ADDR]], align 8			// CHECK3-NEXT: [[TMP1:%.]] = load i8, i8** [[ARGC_ADDR]], align 8
	// CHECK3-NEXT: [[ARGC2:%.]] = call align 8 i8 @__kmpc_alloc_shared(i64 8)			// CHECK3-NEXT: [[ARGC2:%.]] = call align 8 i8 @__kmpc_alloc_shared(i64 8)
	// CHECK3-NEXT: [[ARGC_ON_STACK:%.]] = bitcast i8 [[ARGC2]] to i8***			// CHECK3-NEXT: [[ARGC_ON_STACK:%.]] = bitcast i8 [[ARGC2]] to i8***
	// CHECK3-NEXT: store i8 [[TMP1]], i8* [[ARGC_ON_STACK]], align 8			// CHECK3-NEXT: store i8 [[TMP1]], i8* [[ARGC_ON_STACK]], align 8
	// CHECK3-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB1]])			// CHECK3-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB1]])
	// CHECK3-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4			// CHECK3-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	// CHECK3-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4			// CHECK3-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4
	// CHECK3-NEXT: call void @__omp_outlined__1(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i8*** [[ARGC_ON_STACK]]) #[[ATTR2]]			// CHECK3-NEXT: call void @__omp_outlined__1(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i8*** [[ARGC_ON_STACK]]) #[[ATTR2]]
	// CHECK3-NEXT: call void @__kmpc_free_shared(i8* [[ARGC2]], i64 8)			// CHECK3-NEXT: call void @__kmpc_free_shared(i8* [[ARGC2]], i64 8)
	// CHECK3-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true)			// CHECK3-NEXT: call void @__kmpc_target_deinit(i1 true)
	// CHECK3-NEXT: ret void			// CHECK3-NEXT: ret void
	// CHECK3: worker.exit:			// CHECK3: worker.exit:
	// CHECK3-NEXT: ret void			// CHECK3-NEXT: ret void
	//			//
	//			//
	// CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__1			// CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__1
	// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i8** nonnull align 8 dereferenceable(8) [[ARGC:%.*]]) #[[ATTR0]] {			// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i8** nonnull align 8 dereferenceable(8) [[ARGC:%.*]]) #[[ATTR0]] {
	// CHECK3-NEXT: entry:			// CHECK3-NEXT: entry:
	Show All 14 Lines
	// CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4			// CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
	// CHECK4-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4			// CHECK4-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
	// CHECK4-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4			// CHECK4-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4
	// CHECK4-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			// CHECK4-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	// CHECK4-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4			// CHECK4-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
	// CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4			// CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
	// CHECK4-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4			// CHECK4-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
	// CHECK4-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4			// CHECK4-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4
	// CHECK4-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1:[0-9]+]], i8 1, i1 true, i1 true)			// CHECK4-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l64_kernel_info, i1 true)
	// CHECK4-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1			// CHECK4-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
	// CHECK4-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]			// CHECK4-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
	// CHECK4: user_code.entry:			// CHECK4: user_code.entry:
	// CHECK4-NEXT: [[TMP1:%.]] = load i32, i32 [[ARGC_ADDR]], align 4			// CHECK4-NEXT: [[TMP1:%.]] = load i32, i32 [[ARGC_ADDR]], align 4
	// CHECK4-NEXT: [[ARGC1:%.]] = call align 8 i8 @__kmpc_alloc_shared(i32 4)			// CHECK4-NEXT: [[ARGC1:%.]] = call align 8 i8 @__kmpc_alloc_shared(i32 4)
	// CHECK4-NEXT: [[ARGC_ON_STACK:%.]] = bitcast i8 [[ARGC1]] to i32*			// CHECK4-NEXT: [[ARGC_ON_STACK:%.]] = bitcast i8 [[ARGC1]] to i32*
	// CHECK4-NEXT: store i32 [[TMP1]], i32* [[ARGC_ON_STACK]], align 4			// CHECK4-NEXT: store i32 [[TMP1]], i32* [[ARGC_ON_STACK]], align 4
	// CHECK4-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB1]])			// CHECK4-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB1:[0-9]+]])
	// CHECK4-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4			// CHECK4-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	// CHECK4-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4			// CHECK4-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4
	// CHECK4-NEXT: call void @__omp_outlined__(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i32* [[ARGC_ON_STACK]]) #[[ATTR2:[0-9]+]]			// CHECK4-NEXT: call void @__omp_outlined__(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i32* [[ARGC_ON_STACK]]) #[[ATTR2:[0-9]+]]
	// CHECK4-NEXT: call void @__kmpc_free_shared(i8* [[ARGC1]], i32 4)			// CHECK4-NEXT: call void @__kmpc_free_shared(i8* [[ARGC1]], i32 4)
	// CHECK4-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true)			// CHECK4-NEXT: call void @__kmpc_target_deinit(i1 true)
	// CHECK4-NEXT: ret void			// CHECK4-NEXT: ret void
	// CHECK4: worker.exit:			// CHECK4: worker.exit:
	// CHECK4-NEXT: ret void			// CHECK4-NEXT: ret void
	//			//
	//			//
	// CHECK4-LABEL: define {{[^@]+}}@__omp_outlined__			// CHECK4-LABEL: define {{[^@]+}}@__omp_outlined__
	// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i32 nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR0]] {			// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i32 nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR0]] {
	// CHECK4-NEXT: entry:			// CHECK4-NEXT: entry:
	Show All 14 Lines
	// CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4			// CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
	// CHECK4-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4			// CHECK4-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
	// CHECK4-NEXT: [[ARGC_ADDR:%.]] = alloca i8*, align 4			// CHECK4-NEXT: [[ARGC_ADDR:%.]] = alloca i8*, align 4
	// CHECK4-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			// CHECK4-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	// CHECK4-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4			// CHECK4-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
	// CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4			// CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
	// CHECK4-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4			// CHECK4-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
	// CHECK4-NEXT: store i8 [[ARGC]], i8* [[ARGC_ADDR]], align 4			// CHECK4-NEXT: store i8 [[ARGC]], i8* [[ARGC_ADDR]], align 4
	// CHECK4-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 1, i1 true, i1 true)			// CHECK4-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIPPcEiT__l53_kernel_info, i1 true)
	// CHECK4-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1			// CHECK4-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
	// CHECK4-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]			// CHECK4-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]]
	// CHECK4: user_code.entry:			// CHECK4: user_code.entry:
	// CHECK4-NEXT: [[TMP1:%.]] = load i8, i8** [[ARGC_ADDR]], align 4			// CHECK4-NEXT: [[TMP1:%.]] = load i8, i8** [[ARGC_ADDR]], align 4
	// CHECK4-NEXT: [[ARGC1:%.]] = call align 8 i8 @__kmpc_alloc_shared(i32 4)			// CHECK4-NEXT: [[ARGC1:%.]] = call align 8 i8 @__kmpc_alloc_shared(i32 4)
	// CHECK4-NEXT: [[ARGC_ON_STACK:%.]] = bitcast i8 [[ARGC1]] to i8***			// CHECK4-NEXT: [[ARGC_ON_STACK:%.]] = bitcast i8 [[ARGC1]] to i8***
	// CHECK4-NEXT: store i8 [[TMP1]], i8* [[ARGC_ON_STACK]], align 4			// CHECK4-NEXT: store i8 [[TMP1]], i8* [[ARGC_ON_STACK]], align 4
	// CHECK4-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB1]])			// CHECK4-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB1]])
	// CHECK4-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4			// CHECK4-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	// CHECK4-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4			// CHECK4-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4
	// CHECK4-NEXT: call void @__omp_outlined__1(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i8*** [[ARGC_ON_STACK]]) #[[ATTR2]]			// CHECK4-NEXT: call void @__omp_outlined__1(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i8*** [[ARGC_ON_STACK]]) #[[ATTR2]]
	// CHECK4-NEXT: call void @__kmpc_free_shared(i8* [[ARGC1]], i32 4)			// CHECK4-NEXT: call void @__kmpc_free_shared(i8* [[ARGC1]], i32 4)
	// CHECK4-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true)			// CHECK4-NEXT: call void @__kmpc_target_deinit(i1 true)
	// CHECK4-NEXT: ret void			// CHECK4-NEXT: ret void
	// CHECK4: worker.exit:			// CHECK4: worker.exit:
	// CHECK4-NEXT: ret void			// CHECK4-NEXT: ret void
	//			//
	//			//
	// CHECK4-LABEL: define {{[^@]+}}@__omp_outlined__1			// CHECK4-LABEL: define {{[^@]+}}@__omp_outlined__1
	// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i8** nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR0]] {			// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i8** nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR0]] {
	// CHECK4-NEXT: entry:			// CHECK4-NEXT: entry:
	Show All 10 Lines

clang/test/OpenMP/openmp_win_codegen.cpp

	Show First 20 Lines • Show All 149 Lines • ▼ Show 20 Lines
	// CHECK1-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to i32*			// CHECK1-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to i32*
	// CHECK1-NEXT: [[TMP9:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[TMP5]], i64 0, i64 0			// CHECK1-NEXT: [[TMP9:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[TMP5]], i64 0, i64 0
	// CHECK1-NEXT: [[TMP10:%.]] = load i8, i8** [[TMP9]], align 8			// CHECK1-NEXT: [[TMP10:%.]] = load i8, i8** [[TMP9]], align 8
	// CHECK1-NEXT: [[TMP11:%.]] = bitcast i8 [[TMP10]] to i32*			// CHECK1-NEXT: [[TMP11:%.]] = bitcast i8 [[TMP10]] to i32*
	// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32 [[TMP11]], align 4			// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32 [[TMP11]], align 4
	// CHECK1-NEXT: store i32 [[TMP12]], i32* [[TMP8]], align 4			// CHECK1-NEXT: store i32 [[TMP12]], i32* [[TMP8]], align 4
	// CHECK1-NEXT: ret void			// CHECK1-NEXT: ret void
	//			//
	//
	No newline at end of file

clang/test/OpenMP/parallel_codegen.cpp

	Show First 20 Lines • Show All 305 Lines • ▼ Show 20 Lines
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	// CHECK2-NEXT: [[RETVAL:%.*]] = alloca i32, align 4			// CHECK2-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
	// CHECK2-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4			// CHECK2-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4
	// CHECK2-NEXT: [[ARGV_ADDR:%.]] = alloca i8*, align 8			// CHECK2-NEXT: [[ARGV_ADDR:%.]] = alloca i8*, align 8
	// CHECK2-NEXT: [[SAVED_STACK:%.]] = alloca i8, align 8			// CHECK2-NEXT: [[SAVED_STACK:%.]] = alloca i8, align 8
	// CHECK2-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8			// CHECK2-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8
	// CHECK2-NEXT: store i32 0, i32* [[RETVAL]], align 4			// CHECK2-NEXT: store i32 0, i32* [[RETVAL]], align 4
	// CHECK2-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4			// CHECK2-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4
	// CHECK2-NEXT: call void @llvm.dbg.declare(metadata i32* [[ARGC_ADDR]], metadata [[META17:![0-9]+]], metadata !DIExpression()), !dbg [[DBG18:![0-9]+]]			// CHECK2-NEXT: call void @llvm.dbg.declare(metadata i32* [[ARGC_ADDR]], metadata [[META18:![0-9]+]], metadata !DIExpression()), !dbg [[DBG19:![0-9]+]]
	// CHECK2-NEXT: store i8 [[ARGV]], i8* [[ARGV_ADDR]], align 8			// CHECK2-NEXT: store i8 [[ARGV]], i8* [[ARGV_ADDR]], align 8
	// CHECK2-NEXT: call void @llvm.dbg.declare(metadata i8*** [[ARGV_ADDR]], metadata [[META19:![0-9]+]], metadata !DIExpression()), !dbg [[DBG20:![0-9]+]]			// CHECK2-NEXT: call void @llvm.dbg.declare(metadata i8*** [[ARGV_ADDR]], metadata [[META20:![0-9]+]], metadata !DIExpression()), !dbg [[DBG21:![0-9]+]]
	// CHECK2-NEXT: [[TMP0:%.]] = load i32, i32 [[ARGC_ADDR]], align 4, !dbg [[DBG21:![0-9]+]]			// CHECK2-NEXT: [[TMP0:%.]] = load i32, i32 [[ARGC_ADDR]], align 4, !dbg [[DBG22:![0-9]+]]
	// CHECK2-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64, !dbg [[DBG22:![0-9]+]]			// CHECK2-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64, !dbg [[DBG23:![0-9]+]]
	// CHECK2-NEXT: [[TMP2:%.]] = call i8 @llvm.stacksave(), !dbg [[DBG22]]			// CHECK2-NEXT: [[TMP2:%.]] = call i8 @llvm.stacksave(), !dbg [[DBG23]]
	// CHECK2-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8, !dbg [[DBG22]]			// CHECK2-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8, !dbg [[DBG23]]
	// CHECK2-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 16, !dbg [[DBG22]]			// CHECK2-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 16, !dbg [[DBG23]]
	// CHECK2-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8, !dbg [[DBG22]]			// CHECK2-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8, !dbg [[DBG23]]
	// CHECK2-NEXT: call void @llvm.dbg.declare(metadata i64* [[__VLA_EXPR0]], metadata [[META23:![0-9]+]], metadata !DIExpression()), !dbg [[DBG25:![0-9]+]]			// CHECK2-NEXT: call void @llvm.dbg.declare(metadata i64* [[__VLA_EXPR0]], metadata [[META24:![0-9]+]], metadata !DIExpression()), !dbg [[DBG26:![0-9]+]]
	// CHECK2-NEXT: call void @llvm.dbg.declare(metadata i32* [[VLA]], metadata [[META26:![0-9]+]], metadata !DIExpression()), !dbg [[DBG30:![0-9]+]]			// CHECK2-NEXT: call void @llvm.dbg.declare(metadata i32* [[VLA]], metadata [[META27:![0-9]+]], metadata !DIExpression()), !dbg [[DBG31:![0-9]+]]
	// CHECK2-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i32) @.omp_outlined. to void (i32, i32, ...)), i64 [[TMP1]], i32 [[VLA]]), !dbg [[DBG31:![0-9]+]]			// CHECK2-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i32) @.omp_outlined. to void (i32, i32, ...)), i64 [[TMP1]], i32 [[VLA]]), !dbg [[DBG32:![0-9]+]]
	// CHECK2-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB5:[0-9]+]], i32 1, void (i32, i32, ...)* bitcast (void (i32, i32, i64)* @.omp_outlined..4 to void (i32, i32, ...)*), i64 [[TMP1]]), !dbg [[DBG32:![0-9]+]]			// CHECK2-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB5:[0-9]+]], i32 1, void (i32, i32, ...)* bitcast (void (i32, i32, i64)* @.omp_outlined..4 to void (i32, i32, ...)*), i64 [[TMP1]]), !dbg [[DBG33:![0-9]+]]
	// CHECK2-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB9:[0-9]+]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i32) @.omp_outlined..8 to void (i32, i32, ...)), i64 [[TMP1]], i32 [[VLA]]), !dbg [[DBG33:![0-9]+]]			// CHECK2-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB9:[0-9]+]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i32) @.omp_outlined..8 to void (i32, i32, ...)), i64 [[TMP1]], i32 [[VLA]]), !dbg [[DBG34:![0-9]+]]
	// CHECK2-NEXT: [[TMP3:%.]] = load i8, i8** [[ARGV_ADDR]], align 8, !dbg [[DBG34:![0-9]+]]			// CHECK2-NEXT: [[TMP3:%.]] = load i8, i8** [[ARGV_ADDR]], align 8, !dbg [[DBG35:![0-9]+]]
	// CHECK2-NEXT: [[CALL:%.]] = call i32 @_Z5tmainIPPcEiT_(i8* [[TMP3]]), !dbg [[DBG35:![0-9]+]]			// CHECK2-NEXT: [[CALL:%.]] = call i32 @_Z5tmainIPPcEiT_(i8* [[TMP3]]), !dbg [[DBG36:![0-9]+]]
	// CHECK2-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4, !dbg [[DBG36:![0-9]+]]			// CHECK2-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4, !dbg [[DBG37:![0-9]+]]
	// CHECK2-NEXT: [[TMP4:%.]] = load i8, i8** [[SAVED_STACK]], align 8, !dbg [[DBG37:![0-9]+]]			// CHECK2-NEXT: [[TMP4:%.]] = load i8, i8** [[SAVED_STACK]], align 8, !dbg [[DBG38:![0-9]+]]
	// CHECK2-NEXT: call void @llvm.stackrestore(i8* [[TMP4]]), !dbg [[DBG37]]			// CHECK2-NEXT: call void @llvm.stackrestore(i8* [[TMP4]]), !dbg [[DBG38]]
	// CHECK2-NEXT: [[TMP5:%.]] = load i32, i32 [[RETVAL]], align 4, !dbg [[DBG37]]			// CHECK2-NEXT: [[TMP5:%.]] = load i32, i32 [[RETVAL]], align 4, !dbg [[DBG38]]
	// CHECK2-NEXT: ret i32 [[TMP5]], !dbg [[DBG37]]			// CHECK2-NEXT: ret i32 [[TMP5]], !dbg [[DBG38]]
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined._debug__			// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined._debug__
	// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i64 [[VLA:%.]], i32* nonnull align 4 dereferenceable(4) [[A:%.]]) #[[ATTR3:[0-9]+]] personality i8 bitcast (i32 (...)* @__gxx_personality_v0 to i8*) !dbg [[DBG38:![0-9]+]] {			// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i64 [[VLA:%.]], i32* nonnull align 4 dereferenceable(4) [[A:%.]]) #[[ATTR3:[0-9]+]] personality i8 bitcast (i32 (...)* @__gxx_personality_v0 to i8*) !dbg [[DBG39:![0-9]+]] {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8			// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8
	// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8			// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8
	// CHECK2-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8			// CHECK2-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
	// CHECK2-NEXT: [[A_ADDR:%.]] = alloca i32, align 8			// CHECK2-NEXT: [[A_ADDR:%.]] = alloca i32, align 8
	// CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK2-NEXT: call void @llvm.dbg.declare(metadata i32** [[DOTGLOBAL_TID__ADDR]], metadata [[META46:![0-9]+]], metadata !DIExpression()), !dbg [[DBG47:![0-9]+]]			// CHECK2-NEXT: call void @llvm.dbg.declare(metadata i32** [[DOTGLOBAL_TID__ADDR]], metadata [[META47:![0-9]+]], metadata !DIExpression()), !dbg [[DBG48:![0-9]+]]
	// CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8			// CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
	// CHECK2-NEXT: call void @llvm.dbg.declare(metadata i32** [[DOTBOUND_TID__ADDR]], metadata [[META48:![0-9]+]], metadata !DIExpression()), !dbg [[DBG47]]			// CHECK2-NEXT: call void @llvm.dbg.declare(metadata i32** [[DOTBOUND_TID__ADDR]], metadata [[META49:![0-9]+]], metadata !DIExpression()), !dbg [[DBG48]]
	// CHECK2-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8			// CHECK2-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
	// CHECK2-NEXT: call void @llvm.dbg.declare(metadata i64* [[VLA_ADDR]], metadata [[META49:![0-9]+]], metadata !DIExpression()), !dbg [[DBG47]]			// CHECK2-NEXT: call void @llvm.dbg.declare(metadata i64* [[VLA_ADDR]], metadata [[META50:![0-9]+]], metadata !DIExpression()), !dbg [[DBG48]]
	// CHECK2-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8			// CHECK2-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
	// CHECK2-NEXT: call void @llvm.dbg.declare(metadata i32** [[A_ADDR]], metadata [[META50:![0-9]+]], metadata !DIExpression()), !dbg [[DBG51:![0-9]+]]			// CHECK2-NEXT: call void @llvm.dbg.declare(metadata i32** [[A_ADDR]], metadata [[META51:![0-9]+]], metadata !DIExpression()), !dbg [[DBG52:![0-9]+]]
	// CHECK2-NEXT: [[TMP0:%.]] = load i64, i64 [[VLA_ADDR]], align 8, !dbg [[DBG52:![0-9]+]]			// CHECK2-NEXT: [[TMP0:%.]] = load i64, i64 [[VLA_ADDR]], align 8, !dbg [[DBG53:![0-9]+]]
	// CHECK2-NEXT: [[TMP1:%.]] = load i32, i32** [[A_ADDR]], align 8, !dbg [[DBG52]]			// CHECK2-NEXT: [[TMP1:%.]] = load i32, i32** [[A_ADDR]], align 8, !dbg [[DBG53]]
	// CHECK2-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP1]], i64 1, !dbg [[DBG53:![0-9]+]]			// CHECK2-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP1]], i64 1, !dbg [[DBG54:![0-9]+]]
	// CHECK2-NEXT: [[TMP2:%.]] = load i32, i32 [[ARRAYIDX]], align 4, !dbg [[DBG53]]			// CHECK2-NEXT: [[TMP2:%.]] = load i32, i32 [[ARRAYIDX]], align 4, !dbg [[DBG54]]
	// CHECK2-NEXT: invoke void @_Z3fooIiEvT_(i32 [[TMP2]])			// CHECK2-NEXT: invoke void @_Z3fooIiEvT_(i32 [[TMP2]])
	// CHECK2-NEXT: to label [[INVOKE_CONT:%.]] unwind label [[TERMINATE_LPAD:%.]], !dbg [[DBG52]]			// CHECK2-NEXT: to label [[INVOKE_CONT:%.]] unwind label [[TERMINATE_LPAD:%.]], !dbg [[DBG53]]
	// CHECK2: invoke.cont:			// CHECK2: invoke.cont:
	// CHECK2-NEXT: [[TMP3:%.]] = load i32, i32 @global, align 4, !dbg [[DBG54:![0-9]+]]			// CHECK2-NEXT: [[TMP3:%.]] = load i32, i32 @global, align 4, !dbg [[DBG55:![0-9]+]]
	// CHECK2-NEXT: [[ARRAYIDX1:%.]] = getelementptr inbounds i32, i32 [[TMP1]], i64 1, !dbg [[DBG55:![0-9]+]]			// CHECK2-NEXT: [[ARRAYIDX1:%.]] = getelementptr inbounds i32, i32 [[TMP1]], i64 1, !dbg [[DBG56:![0-9]+]]
	// CHECK2-NEXT: store i32 [[TMP3]], i32* [[ARRAYIDX1]], align 4, !dbg [[DBG56:![0-9]+]]			// CHECK2-NEXT: store i32 [[TMP3]], i32* [[ARRAYIDX1]], align 4, !dbg [[DBG57:![0-9]+]]
	// CHECK2-NEXT: ret void, !dbg [[DBG54]]			// CHECK2-NEXT: ret void, !dbg [[DBG55]]
	// CHECK2: terminate.lpad:			// CHECK2: terminate.lpad:
	// CHECK2-NEXT: [[TMP4:%.]] = landingpad { i8, i32 }			// CHECK2-NEXT: [[TMP4:%.]] = landingpad { i8, i32 }
	// CHECK2-NEXT: catch i8* null, !dbg [[DBG52]]			// CHECK2-NEXT: catch i8* null, !dbg [[DBG53]]
	// CHECK2-NEXT: [[TMP5:%.]] = extractvalue { i8, i32 } [[TMP4]], 0, !dbg [[DBG52]]			// CHECK2-NEXT: [[TMP5:%.]] = extractvalue { i8, i32 } [[TMP4]], 0, !dbg [[DBG53]]
	// CHECK2-NEXT: call void @__clang_call_terminate(i8* [[TMP5]]) #[[ATTR7:[0-9]+]], !dbg [[DBG52]]			// CHECK2-NEXT: call void @__clang_call_terminate(i8* [[TMP5]]) #[[ATTR7:[0-9]+]], !dbg [[DBG53]]
	// CHECK2-NEXT: unreachable, !dbg [[DBG52]]			// CHECK2-NEXT: unreachable, !dbg [[DBG53]]
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@_Z3fooIiEvT_			// CHECK2-LABEL: define {{[^@]+}}@_Z3fooIiEvT_
	// CHECK2-SAME: (i32 [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat !dbg [[DBG57:![0-9]+]] {			// CHECK2-SAME: (i32 [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat !dbg [[DBG58:![0-9]+]] {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	// CHECK2-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4			// CHECK2-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4
	// CHECK2-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4			// CHECK2-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4
	// CHECK2-NEXT: call void @llvm.dbg.declare(metadata i32* [[ARGC_ADDR]], metadata [[META62:![0-9]+]], metadata !DIExpression()), !dbg [[DBG63:![0-9]+]]			// CHECK2-NEXT: call void @llvm.dbg.declare(metadata i32* [[ARGC_ADDR]], metadata [[META63:![0-9]+]], metadata !DIExpression()), !dbg [[DBG64:![0-9]+]]
	// CHECK2-NEXT: ret void, !dbg [[DBG64:![0-9]+]]			// CHECK2-NEXT: ret void, !dbg [[DBG65:![0-9]+]]
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@__clang_call_terminate			// CHECK2-LABEL: define {{[^@]+}}@__clang_call_terminate
	// CHECK2-SAME: (i8* [[TMP0:%.*]]) #[[ATTR5:[0-9]+]] comdat {			// CHECK2-SAME: (i8* [[TMP0:%.*]]) #[[ATTR5:[0-9]+]] comdat {
	// CHECK2-NEXT: [[TMP2:%.]] = call i8 @__cxa_begin_catch(i8* [[TMP0]]) #[[ATTR6:[0-9]+]]			// CHECK2-NEXT: [[TMP2:%.]] = call i8 @__cxa_begin_catch(i8* [[TMP0]]) #[[ATTR6:[0-9]+]]
	// CHECK2-NEXT: call void @_ZSt9terminatev() #[[ATTR7]]			// CHECK2-NEXT: call void @_ZSt9terminatev() #[[ATTR7]]
	// CHECK2-NEXT: unreachable			// CHECK2-NEXT: unreachable
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined.			// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined.
	// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i64 [[VLA:%.]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR3]] !dbg [[DBG65:![0-9]+]] {			// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i64 [[VLA:%.]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR3]] !dbg [[DBG66:![0-9]+]] {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8			// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8
	// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8			// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8
	// CHECK2-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8			// CHECK2-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
	// CHECK2-NEXT: [[A_ADDR:%.]] = alloca i32, align 8			// CHECK2-NEXT: [[A_ADDR:%.]] = alloca i32, align 8
	// CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK2-NEXT: call void @llvm.dbg.declare(metadata i32** [[DOTGLOBAL_TID__ADDR]], metadata [[META66:![0-9]+]], metadata !DIExpression()), !dbg [[DBG67:![0-9]+]]			// CHECK2-NEXT: call void @llvm.dbg.declare(metadata i32** [[DOTGLOBAL_TID__ADDR]], metadata [[META67:![0-9]+]], metadata !DIExpression()), !dbg [[DBG68:![0-9]+]]
	// CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8			// CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
	// CHECK2-NEXT: call void @llvm.dbg.declare(metadata i32** [[DOTBOUND_TID__ADDR]], metadata [[META68:![0-9]+]], metadata !DIExpression()), !dbg [[DBG67]]			// CHECK2-NEXT: call void @llvm.dbg.declare(metadata i32** [[DOTBOUND_TID__ADDR]], metadata [[META69:![0-9]+]], metadata !DIExpression()), !dbg [[DBG68]]
	// CHECK2-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8			// CHECK2-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
	// CHECK2-NEXT: call void @llvm.dbg.declare(metadata i64* [[VLA_ADDR]], metadata [[META69:![0-9]+]], metadata !DIExpression()), !dbg [[DBG67]]			// CHECK2-NEXT: call void @llvm.dbg.declare(metadata i64* [[VLA_ADDR]], metadata [[META70:![0-9]+]], metadata !DIExpression()), !dbg [[DBG68]]
	// CHECK2-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8			// CHECK2-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
	// CHECK2-NEXT: call void @llvm.dbg.declare(metadata i32** [[A_ADDR]], metadata [[META70:![0-9]+]], metadata !DIExpression()), !dbg [[DBG67]]			// CHECK2-NEXT: call void @llvm.dbg.declare(metadata i32** [[A_ADDR]], metadata [[META71:![0-9]+]], metadata !DIExpression()), !dbg [[DBG68]]
	// CHECK2-NEXT: [[TMP0:%.]] = load i64, i64 [[VLA_ADDR]], align 8, !dbg [[DBG71:![0-9]+]]			// CHECK2-NEXT: [[TMP0:%.]] = load i64, i64 [[VLA_ADDR]], align 8, !dbg [[DBG72:![0-9]+]]
	// CHECK2-NEXT: [[TMP1:%.]] = load i32, i32** [[A_ADDR]], align 8, !dbg [[DBG71]]			// CHECK2-NEXT: [[TMP1:%.]] = load i32, i32** [[A_ADDR]], align 8, !dbg [[DBG72]]
	// CHECK2-NEXT: [[TMP2:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG71]]			// CHECK2-NEXT: [[TMP2:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG72]]
	// CHECK2-NEXT: [[TMP3:%.]] = load i32, i32** [[DOTBOUND_TID__ADDR]], align 8, !dbg [[DBG71]]			// CHECK2-NEXT: [[TMP3:%.]] = load i32, i32** [[DOTBOUND_TID__ADDR]], align 8, !dbg [[DBG72]]
	// CHECK2-NEXT: [[TMP4:%.]] = load i32, i32** [[A_ADDR]], align 8, !dbg [[DBG71]]			// CHECK2-NEXT: [[TMP4:%.]] = load i32, i32** [[A_ADDR]], align 8, !dbg [[DBG72]]
	// CHECK2-NEXT: call void @.omp_outlined._debug__(i32* [[TMP2]], i32* [[TMP3]], i64 [[TMP0]], i32* [[TMP4]]) #[[ATTR6]], !dbg [[DBG71]]			// CHECK2-NEXT: call void @.omp_outlined._debug__(i32* [[TMP2]], i32* [[TMP3]], i64 [[TMP0]], i32* [[TMP4]]) #[[ATTR6]], !dbg [[DBG72]]
	// CHECK2-NEXT: ret void, !dbg [[DBG71]]			// CHECK2-NEXT: ret void, !dbg [[DBG72]]
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined._debug__.1			// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined._debug__.1
	// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i64 [[VLA:%.]]) #[[ATTR3]] !dbg [[DBG74:![0-9]+]] {			// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i64 [[VLA:%.]]) #[[ATTR3]] !dbg [[DBG75:![0-9]+]] {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8			// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8
	// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8			// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8
	// CHECK2-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8			// CHECK2-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
	// CHECK2-NEXT: [[GLOBAL:%.*]] = alloca i32, align 4			// CHECK2-NEXT: [[GLOBAL:%.*]] = alloca i32, align 4
	// CHECK2-NEXT: [[SAVED_STACK:%.]] = alloca i8, align 8			// CHECK2-NEXT: [[SAVED_STACK:%.]] = alloca i8, align 8
	// CHECK2-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8			// CHECK2-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8
	// CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK2-NEXT: call void @llvm.dbg.declare(metadata i32** [[DOTGLOBAL_TID__ADDR]], metadata [[META77:![0-9]+]], metadata !DIExpression()), !dbg [[DBG78:![0-9]+]]			// CHECK2-NEXT: call void @llvm.dbg.declare(metadata i32** [[DOTGLOBAL_TID__ADDR]], metadata [[META78:![0-9]+]], metadata !DIExpression()), !dbg [[DBG79:![0-9]+]]
	// CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8			// CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
	// CHECK2-NEXT: call void @llvm.dbg.declare(metadata i32** [[DOTBOUND_TID__ADDR]], metadata [[META79:![0-9]+]], metadata !DIExpression()), !dbg [[DBG78]]			// CHECK2-NEXT: call void @llvm.dbg.declare(metadata i32** [[DOTBOUND_TID__ADDR]], metadata [[META80:![0-9]+]], metadata !DIExpression()), !dbg [[DBG79]]
	// CHECK2-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8			// CHECK2-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
	// CHECK2-NEXT: call void @llvm.dbg.declare(metadata i64* [[VLA_ADDR]], metadata [[META80:![0-9]+]], metadata !DIExpression()), !dbg [[DBG78]]			// CHECK2-NEXT: call void @llvm.dbg.declare(metadata i64* [[VLA_ADDR]], metadata [[META81:![0-9]+]], metadata !DIExpression()), !dbg [[DBG79]]
	// CHECK2-NEXT: [[TMP0:%.]] = load i64, i64 [[VLA_ADDR]], align 8, !dbg [[DBG81:![0-9]+]]			// CHECK2-NEXT: [[TMP0:%.]] = load i64, i64 [[VLA_ADDR]], align 8, !dbg [[DBG82:![0-9]+]]
	// CHECK2-NEXT: call void @llvm.dbg.declare(metadata i32* [[GLOBAL]], metadata [[META82:![0-9]+]], metadata !DIExpression()), !dbg [[DBG78]]			// CHECK2-NEXT: call void @llvm.dbg.declare(metadata i32* [[GLOBAL]], metadata [[META83:![0-9]+]], metadata !DIExpression()), !dbg [[DBG79]]
	// CHECK2-NEXT: [[TMP1:%.]] = call i8 @llvm.stacksave(), !dbg [[DBG81]]			// CHECK2-NEXT: [[TMP1:%.]] = call i8 @llvm.stacksave(), !dbg [[DBG82]]
	// CHECK2-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 8, !dbg [[DBG81]]			// CHECK2-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 8, !dbg [[DBG82]]
	// CHECK2-NEXT: [[VLA1:%.*]] = alloca i32, i64 [[TMP0]], align 16, !dbg [[DBG81]]			// CHECK2-NEXT: [[VLA1:%.*]] = alloca i32, i64 [[TMP0]], align 16, !dbg [[DBG82]]
	// CHECK2-NEXT: store i64 [[TMP0]], i64* [[__VLA_EXPR0]], align 8, !dbg [[DBG81]]			// CHECK2-NEXT: store i64 [[TMP0]], i64* [[__VLA_EXPR0]], align 8, !dbg [[DBG82]]
	// CHECK2-NEXT: call void @llvm.dbg.declare(metadata i64* [[__VLA_EXPR0]], metadata [[META83:![0-9]+]], metadata !DIExpression()), !dbg [[DBG78]]			// CHECK2-NEXT: call void @llvm.dbg.declare(metadata i64* [[__VLA_EXPR0]], metadata [[META84:![0-9]+]], metadata !DIExpression()), !dbg [[DBG79]]
	// CHECK2-NEXT: call void @llvm.dbg.declare(metadata i32* [[VLA1]], metadata [[META84:![0-9]+]], metadata !DIExpression()), !dbg [[DBG78]]			// CHECK2-NEXT: call void @llvm.dbg.declare(metadata i32* [[VLA1]], metadata [[META85:![0-9]+]], metadata !DIExpression()), !dbg [[DBG79]]
	// CHECK2-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i32, i32)* @.omp_outlined..3 to void (i32, i32, ...)), i64 [[TMP0]], i32 [[VLA1]], i32* [[GLOBAL]]), !dbg [[DBG81]]			// CHECK2-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i32, i32)* @.omp_outlined..3 to void (i32, i32, ...)), i64 [[TMP0]], i32 [[VLA1]], i32* [[GLOBAL]]), !dbg [[DBG82]]
	// CHECK2-NEXT: [[TMP2:%.]] = load i8, i8** [[SAVED_STACK]], align 8, !dbg [[DBG85:![0-9]+]]			// CHECK2-NEXT: [[TMP2:%.]] = load i8, i8** [[SAVED_STACK]], align 8, !dbg [[DBG86:![0-9]+]]
	// CHECK2-NEXT: call void @llvm.stackrestore(i8* [[TMP2]]), !dbg [[DBG85]]			// CHECK2-NEXT: call void @llvm.stackrestore(i8* [[TMP2]]), !dbg [[DBG86]]
	// CHECK2-NEXT: ret void, !dbg [[DBG87:![0-9]+]]			// CHECK2-NEXT: ret void, !dbg [[DBG88:![0-9]+]]
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined._debug__.2			// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined._debug__.2
	// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i64 [[VLA:%.]], i32* nonnull align 4 dereferenceable(4) [[A:%.]], i32 nonnull align 4 dereferenceable(4) [[GLOBAL:%.]]) #[[ATTR3]] personality i8 bitcast (i32 (...)* @__gxx_personality_v0 to i8*) !dbg [[DBG88:![0-9]+]] {			// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i64 [[VLA:%.]], i32* nonnull align 4 dereferenceable(4) [[A:%.]], i32 nonnull align 4 dereferenceable(4) [[GLOBAL:%.]]) #[[ATTR3]] personality i8 bitcast (i32 (...)* @__gxx_personality_v0 to i8*) !dbg [[DBG89:![0-9]+]] {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8			// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8
	// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8			// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8
	// CHECK2-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8			// CHECK2-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
	// CHECK2-NEXT: [[A_ADDR:%.]] = alloca i32, align 8			// CHECK2-NEXT: [[A_ADDR:%.]] = alloca i32, align 8
	// CHECK2-NEXT: [[GLOBAL_ADDR:%.]] = alloca i32, align 8			// CHECK2-NEXT: [[GLOBAL_ADDR:%.]] = alloca i32, align 8
	// CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK2-NEXT: call void @llvm.dbg.declare(metadata i32** [[DOTGLOBAL_TID__ADDR]], metadata [[META91:![0-9]+]], metadata !DIExpression()), !dbg [[DBG92:![0-9]+]]			// CHECK2-NEXT: call void @llvm.dbg.declare(metadata i32** [[DOTGLOBAL_TID__ADDR]], metadata [[META92:![0-9]+]], metadata !DIExpression()), !dbg [[DBG93:![0-9]+]]
	// CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8			// CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
	// CHECK2-NEXT: call void @llvm.dbg.declare(metadata i32** [[DOTBOUND_TID__ADDR]], metadata [[META93:![0-9]+]], metadata !DIExpression()), !dbg [[DBG92]]			// CHECK2-NEXT: call void @llvm.dbg.declare(metadata i32** [[DOTBOUND_TID__ADDR]], metadata [[META94:![0-9]+]], metadata !DIExpression()), !dbg [[DBG93]]
	// CHECK2-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8			// CHECK2-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
	// CHECK2-NEXT: call void @llvm.dbg.declare(metadata i64* [[VLA_ADDR]], metadata [[META94:![0-9]+]], metadata !DIExpression()), !dbg [[DBG92]]			// CHECK2-NEXT: call void @llvm.dbg.declare(metadata i64* [[VLA_ADDR]], metadata [[META95:![0-9]+]], metadata !DIExpression()), !dbg [[DBG93]]
	// CHECK2-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8			// CHECK2-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
	// CHECK2-NEXT: call void @llvm.dbg.declare(metadata i32** [[A_ADDR]], metadata [[META95:![0-9]+]], metadata !DIExpression()), !dbg [[DBG96:![0-9]+]]			// CHECK2-NEXT: call void @llvm.dbg.declare(metadata i32** [[A_ADDR]], metadata [[META96:![0-9]+]], metadata !DIExpression()), !dbg [[DBG97:![0-9]+]]
	// CHECK2-NEXT: store i32* [[GLOBAL]], i32** [[GLOBAL_ADDR]], align 8			// CHECK2-NEXT: store i32* [[GLOBAL]], i32** [[GLOBAL_ADDR]], align 8
	// CHECK2-NEXT: call void @llvm.dbg.declare(metadata i32** [[GLOBAL_ADDR]], metadata [[META97:![0-9]+]], metadata !DIExpression()), !dbg [[DBG98:![0-9]+]]			// CHECK2-NEXT: call void @llvm.dbg.declare(metadata i32** [[GLOBAL_ADDR]], metadata [[META98:![0-9]+]], metadata !DIExpression()), !dbg [[DBG99:![0-9]+]]
	// CHECK2-NEXT: [[TMP0:%.]] = load i64, i64 [[VLA_ADDR]], align 8, !dbg [[DBG99:![0-9]+]]			// CHECK2-NEXT: [[TMP0:%.]] = load i64, i64 [[VLA_ADDR]], align 8, !dbg [[DBG100:![0-9]+]]
	// CHECK2-NEXT: [[TMP1:%.]] = load i32, i32** [[A_ADDR]], align 8, !dbg [[DBG99]]			// CHECK2-NEXT: [[TMP1:%.]] = load i32, i32** [[A_ADDR]], align 8, !dbg [[DBG100]]
	// CHECK2-NEXT: [[TMP2:%.]] = load i32, i32** [[GLOBAL_ADDR]], align 8, !dbg [[DBG99]]			// CHECK2-NEXT: [[TMP2:%.]] = load i32, i32** [[GLOBAL_ADDR]], align 8, !dbg [[DBG100]]
	// CHECK2-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP1]], i64 1, !dbg [[DBG100:![0-9]+]]			// CHECK2-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP1]], i64 1, !dbg [[DBG101:![0-9]+]]
	// CHECK2-NEXT: [[TMP3:%.]] = load i32, i32 [[ARRAYIDX]], align 4, !dbg [[DBG100]]			// CHECK2-NEXT: [[TMP3:%.]] = load i32, i32 [[ARRAYIDX]], align 4, !dbg [[DBG101]]
	// CHECK2-NEXT: invoke void @_Z3fooIiEvT_(i32 [[TMP3]])			// CHECK2-NEXT: invoke void @_Z3fooIiEvT_(i32 [[TMP3]])
	// CHECK2-NEXT: to label [[INVOKE_CONT:%.]] unwind label [[TERMINATE_LPAD:%.]], !dbg [[DBG99]]			// CHECK2-NEXT: to label [[INVOKE_CONT:%.]] unwind label [[TERMINATE_LPAD:%.]], !dbg [[DBG100]]
	// CHECK2: invoke.cont:			// CHECK2: invoke.cont:
	// CHECK2-NEXT: [[TMP4:%.]] = load i32, i32 [[TMP2]], align 4, !dbg [[DBG101:![0-9]+]]			// CHECK2-NEXT: [[TMP4:%.]] = load i32, i32 [[TMP2]], align 4, !dbg [[DBG102:![0-9]+]]
	// CHECK2-NEXT: [[ARRAYIDX1:%.]] = getelementptr inbounds i32, i32 [[TMP1]], i64 1, !dbg [[DBG102:![0-9]+]]			// CHECK2-NEXT: [[ARRAYIDX1:%.]] = getelementptr inbounds i32, i32 [[TMP1]], i64 1, !dbg [[DBG103:![0-9]+]]
	// CHECK2-NEXT: store i32 [[TMP4]], i32* [[ARRAYIDX1]], align 4, !dbg [[DBG103:![0-9]+]]			// CHECK2-NEXT: store i32 [[TMP4]], i32* [[ARRAYIDX1]], align 4, !dbg [[DBG104:![0-9]+]]
	// CHECK2-NEXT: ret void, !dbg [[DBG101]]			// CHECK2-NEXT: ret void, !dbg [[DBG102]]
	// CHECK2: terminate.lpad:			// CHECK2: terminate.lpad:
	// CHECK2-NEXT: [[TMP5:%.]] = landingpad { i8, i32 }			// CHECK2-NEXT: [[TMP5:%.]] = landingpad { i8, i32 }
	// CHECK2-NEXT: catch i8* null, !dbg [[DBG99]]			// CHECK2-NEXT: catch i8* null, !dbg [[DBG100]]
	// CHECK2-NEXT: [[TMP6:%.]] = extractvalue { i8, i32 } [[TMP5]], 0, !dbg [[DBG99]]			// CHECK2-NEXT: [[TMP6:%.]] = extractvalue { i8, i32 } [[TMP5]], 0, !dbg [[DBG100]]
	// CHECK2-NEXT: call void @__clang_call_terminate(i8* [[TMP6]]) #[[ATTR7]], !dbg [[DBG99]]			// CHECK2-NEXT: call void @__clang_call_terminate(i8* [[TMP6]]) #[[ATTR7]], !dbg [[DBG100]]
	// CHECK2-NEXT: unreachable, !dbg [[DBG99]]			// CHECK2-NEXT: unreachable, !dbg [[DBG100]]
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..3			// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..3
	// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i64 [[VLA:%.]], i32* nonnull align 4 dereferenceable(4) [[A:%.]], i32 nonnull align 4 dereferenceable(4) [[GLOBAL:%.*]]) #[[ATTR3]] !dbg [[DBG104:![0-9]+]] {			// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i64 [[VLA:%.]], i32* nonnull align 4 dereferenceable(4) [[A:%.]], i32 nonnull align 4 dereferenceable(4) [[GLOBAL:%.*]]) #[[ATTR3]] !dbg [[DBG105:![0-9]+]] {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8			// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8
	// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8			// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8
	// CHECK2-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8			// CHECK2-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
	// CHECK2-NEXT: [[A_ADDR:%.]] = alloca i32, align 8			// CHECK2-NEXT: [[A_ADDR:%.]] = alloca i32, align 8
	// CHECK2-NEXT: [[GLOBAL_ADDR:%.]] = alloca i32, align 8			// CHECK2-NEXT: [[GLOBAL_ADDR:%.]] = alloca i32, align 8
	// CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK2-NEXT: call void @llvm.dbg.declare(metadata i32** [[DOTGLOBAL_TID__ADDR]], metadata [[META105:![0-9]+]], metadata !DIExpression()), !dbg [[DBG106:![0-9]+]]			// CHECK2-NEXT: call void @llvm.dbg.declare(metadata i32** [[DOTGLOBAL_TID__ADDR]], metadata [[META106:![0-9]+]], metadata !DIExpression()), !dbg [[DBG107:![0-9]+]]
	// CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8			// CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
	// CHECK2-NEXT: call void @llvm.dbg.declare(metadata i32** [[DOTBOUND_TID__ADDR]], metadata [[META107:![0-9]+]], metadata !DIExpression()), !dbg [[DBG106]]			// CHECK2-NEXT: call void @llvm.dbg.declare(metadata i32** [[DOTBOUND_TID__ADDR]], metadata [[META108:![0-9]+]], metadata !DIExpression()), !dbg [[DBG107]]
	// CHECK2-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8			// CHECK2-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
	// CHECK2-NEXT: call void @llvm.dbg.declare(metadata i64* [[VLA_ADDR]], metadata [[META108:![0-9]+]], metadata !DIExpression()), !dbg [[DBG106]]			// CHECK2-NEXT: call void @llvm.dbg.declare(metadata i64* [[VLA_ADDR]], metadata [[META109:![0-9]+]], metadata !DIExpression()), !dbg [[DBG107]]
	// CHECK2-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8			// CHECK2-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
	// CHECK2-NEXT: call void @llvm.dbg.declare(metadata i32** [[A_ADDR]], metadata [[META109:![0-9]+]], metadata !DIExpression()), !dbg [[DBG106]]			// CHECK2-NEXT: call void @llvm.dbg.declare(metadata i32** [[A_ADDR]], metadata [[META110:![0-9]+]], metadata !DIExpression()), !dbg [[DBG107]]
	// CHECK2-NEXT: store i32* [[GLOBAL]], i32** [[GLOBAL_ADDR]], align 8			// CHECK2-NEXT: store i32* [[GLOBAL]], i32** [[GLOBAL_ADDR]], align 8
	// CHECK2-NEXT: call void @llvm.dbg.declare(metadata i32** [[GLOBAL_ADDR]], metadata [[META110:![0-9]+]], metadata !DIExpression()), !dbg [[DBG106]]			// CHECK2-NEXT: call void @llvm.dbg.declare(metadata i32** [[GLOBAL_ADDR]], metadata [[META111:![0-9]+]], metadata !DIExpression()), !dbg [[DBG107]]
	// CHECK2-NEXT: [[TMP0:%.]] = load i64, i64 [[VLA_ADDR]], align 8, !dbg [[DBG111:![0-9]+]]			// CHECK2-NEXT: [[TMP0:%.]] = load i64, i64 [[VLA_ADDR]], align 8, !dbg [[DBG112:![0-9]+]]
	// CHECK2-NEXT: [[TMP1:%.]] = load i32, i32** [[A_ADDR]], align 8, !dbg [[DBG111]]			// CHECK2-NEXT: [[TMP1:%.]] = load i32, i32** [[A_ADDR]], align 8, !dbg [[DBG112]]
	// CHECK2-NEXT: [[TMP2:%.]] = load i32, i32** [[GLOBAL_ADDR]], align 8, !dbg [[DBG111]]			// CHECK2-NEXT: [[TMP2:%.]] = load i32, i32** [[GLOBAL_ADDR]], align 8, !dbg [[DBG112]]
	// CHECK2-NEXT: [[TMP3:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG111]]			// CHECK2-NEXT: [[TMP3:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG112]]
	// CHECK2-NEXT: [[TMP4:%.]] = load i32, i32** [[DOTBOUND_TID__ADDR]], align 8, !dbg [[DBG111]]			// CHECK2-NEXT: [[TMP4:%.]] = load i32, i32** [[DOTBOUND_TID__ADDR]], align 8, !dbg [[DBG112]]
	// CHECK2-NEXT: [[TMP5:%.]] = load i32, i32** [[A_ADDR]], align 8, !dbg [[DBG111]]			// CHECK2-NEXT: [[TMP5:%.]] = load i32, i32** [[A_ADDR]], align 8, !dbg [[DBG112]]
	// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32** [[GLOBAL_ADDR]], align 8, !dbg [[DBG111]]			// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32** [[GLOBAL_ADDR]], align 8, !dbg [[DBG112]]
	// CHECK2-NEXT: call void @.omp_outlined._debug__.2(i32* [[TMP3]], i32* [[TMP4]], i64 [[TMP0]], i32* [[TMP5]], i32* [[TMP6]]) #[[ATTR6]], !dbg [[DBG111]]			// CHECK2-NEXT: call void @.omp_outlined._debug__.2(i32* [[TMP3]], i32* [[TMP4]], i64 [[TMP0]], i32* [[TMP5]], i32* [[TMP6]]) #[[ATTR6]], !dbg [[DBG112]]
	// CHECK2-NEXT: ret void, !dbg [[DBG111]]			// CHECK2-NEXT: ret void, !dbg [[DBG112]]
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..4			// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..4
	// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i64 [[VLA:%.]]) #[[ATTR3]] !dbg [[DBG112:![0-9]+]] {			// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i64 [[VLA:%.]]) #[[ATTR3]] !dbg [[DBG113:![0-9]+]] {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8			// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8
	// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8			// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8
	// CHECK2-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8			// CHECK2-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
	// CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK2-NEXT: call void @llvm.dbg.declare(metadata i32** [[DOTGLOBAL_TID__ADDR]], metadata [[META113:![0-9]+]], metadata !DIExpression()), !dbg [[DBG114:![0-9]+]]			// CHECK2-NEXT: call void @llvm.dbg.declare(metadata i32** [[DOTGLOBAL_TID__ADDR]], metadata [[META114:![0-9]+]], metadata !DIExpression()), !dbg [[DBG115:![0-9]+]]
	// CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8			// CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
	// CHECK2-NEXT: call void @llvm.dbg.declare(metadata i32** [[DOTBOUND_TID__ADDR]], metadata [[META115:![0-9]+]], metadata !DIExpression()), !dbg [[DBG114]]			// CHECK2-NEXT: call void @llvm.dbg.declare(metadata i32** [[DOTBOUND_TID__ADDR]], metadata [[META116:![0-9]+]], metadata !DIExpression()), !dbg [[DBG115]]
	// CHECK2-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8			// CHECK2-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
	// CHECK2-NEXT: call void @llvm.dbg.declare(metadata i64* [[VLA_ADDR]], metadata [[META116:![0-9]+]], metadata !DIExpression()), !dbg [[DBG114]]			// CHECK2-NEXT: call void @llvm.dbg.declare(metadata i64* [[VLA_ADDR]], metadata [[META117:![0-9]+]], metadata !DIExpression()), !dbg [[DBG115]]
	// CHECK2-NEXT: [[TMP0:%.]] = load i64, i64 [[VLA_ADDR]], align 8, !dbg [[DBG117:![0-9]+]]			// CHECK2-NEXT: [[TMP0:%.]] = load i64, i64 [[VLA_ADDR]], align 8, !dbg [[DBG118:![0-9]+]]
	// CHECK2-NEXT: [[TMP1:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG117]]			// CHECK2-NEXT: [[TMP1:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG118]]
	// CHECK2-NEXT: [[TMP2:%.]] = load i32, i32** [[DOTBOUND_TID__ADDR]], align 8, !dbg [[DBG117]]			// CHECK2-NEXT: [[TMP2:%.]] = load i32, i32** [[DOTBOUND_TID__ADDR]], align 8, !dbg [[DBG118]]
	// CHECK2-NEXT: call void @.omp_outlined._debug__.1(i32* [[TMP1]], i32* [[TMP2]], i64 [[TMP0]]) #[[ATTR6]], !dbg [[DBG117]]			// CHECK2-NEXT: call void @.omp_outlined._debug__.1(i32* [[TMP1]], i32* [[TMP2]], i64 [[TMP0]]) #[[ATTR6]], !dbg [[DBG118]]
	// CHECK2-NEXT: ret void, !dbg [[DBG117]]			// CHECK2-NEXT: ret void, !dbg [[DBG118]]
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined._debug__.5			// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined._debug__.5
	// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i64 [[VLA:%.]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR3]] !dbg [[DBG118:![0-9]+]] {			// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i64 [[VLA:%.]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR3]] !dbg [[DBG119:![0-9]+]] {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8			// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8
	// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8			// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8
	// CHECK2-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8			// CHECK2-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
	// CHECK2-NEXT: [[A_ADDR:%.]] = alloca i32, align 8			// CHECK2-NEXT: [[A_ADDR:%.]] = alloca i32, align 8
	// CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK2-NEXT: call void @llvm.dbg.declare(metadata i32** [[DOTGLOBAL_TID__ADDR]], metadata [[META119:![0-9]+]], metadata !DIExpression()), !dbg [[DBG120:![0-9]+]]			// CHECK2-NEXT: call void @llvm.dbg.declare(metadata i32** [[DOTGLOBAL_TID__ADDR]], metadata [[META120:![0-9]+]], metadata !DIExpression()), !dbg [[DBG121:![0-9]+]]
	// CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8			// CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
	// CHECK2-NEXT: call void @llvm.dbg.declare(metadata i32** [[DOTBOUND_TID__ADDR]], metadata [[META121:![0-9]+]], metadata !DIExpression()), !dbg [[DBG120]]			// CHECK2-NEXT: call void @llvm.dbg.declare(metadata i32** [[DOTBOUND_TID__ADDR]], metadata [[META122:![0-9]+]], metadata !DIExpression()), !dbg [[DBG121]]
	// CHECK2-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8			// CHECK2-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
	// CHECK2-NEXT: call void @llvm.dbg.declare(metadata i64* [[VLA_ADDR]], metadata [[META122:![0-9]+]], metadata !DIExpression()), !dbg [[DBG120]]			// CHECK2-NEXT: call void @llvm.dbg.declare(metadata i64* [[VLA_ADDR]], metadata [[META123:![0-9]+]], metadata !DIExpression()), !dbg [[DBG121]]
	// CHECK2-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8			// CHECK2-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
	// CHECK2-NEXT: call void @llvm.dbg.declare(metadata i32** [[A_ADDR]], metadata [[META123:![0-9]+]], metadata !DIExpression()), !dbg [[DBG124:![0-9]+]]			// CHECK2-NEXT: call void @llvm.dbg.declare(metadata i32** [[A_ADDR]], metadata [[META124:![0-9]+]], metadata !DIExpression()), !dbg [[DBG125:![0-9]+]]
	// CHECK2-NEXT: [[TMP0:%.]] = load i64, i64 [[VLA_ADDR]], align 8, !dbg [[DBG125:![0-9]+]]			// CHECK2-NEXT: [[TMP0:%.]] = load i64, i64 [[VLA_ADDR]], align 8, !dbg [[DBG126:![0-9]+]]
	// CHECK2-NEXT: [[TMP1:%.]] = load i32, i32** [[A_ADDR]], align 8, !dbg [[DBG125]]			// CHECK2-NEXT: [[TMP1:%.]] = load i32, i32** [[A_ADDR]], align 8, !dbg [[DBG126]]
	// CHECK2-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB7:[0-9]+]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i32) @.omp_outlined..7 to void (i32, i32, ...)), i64 [[TMP0]], i32 [[TMP1]]), !dbg [[DBG125]]			// CHECK2-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB7:[0-9]+]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i32) @.omp_outlined..7 to void (i32, i32, ...)), i64 [[TMP0]], i32 [[TMP1]]), !dbg [[DBG126]]
	// CHECK2-NEXT: ret void, !dbg [[DBG126:![0-9]+]]			// CHECK2-NEXT: ret void, !dbg [[DBG127:![0-9]+]]
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined._debug__.6			// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined._debug__.6
	// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i64 [[VLA:%.]], i32* nonnull align 4 dereferenceable(4) [[A:%.]]) #[[ATTR3]] personality i8 bitcast (i32 (...)* @__gxx_personality_v0 to i8*) !dbg [[DBG127:![0-9]+]] {			// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i64 [[VLA:%.]], i32* nonnull align 4 dereferenceable(4) [[A:%.]]) #[[ATTR3]] personality i8 bitcast (i32 (...)* @__gxx_personality_v0 to i8*) !dbg [[DBG128:![0-9]+]] {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8			// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8
	// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8			// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8
	// CHECK2-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8			// CHECK2-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
	// CHECK2-NEXT: [[A_ADDR:%.]] = alloca i32, align 8			// CHECK2-NEXT: [[A_ADDR:%.]] = alloca i32, align 8
	// CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK2-NEXT: call void @llvm.dbg.declare(metadata i32** [[DOTGLOBAL_TID__ADDR]], metadata [[META128:![0-9]+]], metadata !DIExpression()), !dbg [[DBG129:![0-9]+]]			// CHECK2-NEXT: call void @llvm.dbg.declare(metadata i32** [[DOTGLOBAL_TID__ADDR]], metadata [[META129:![0-9]+]], metadata !DIExpression()), !dbg [[DBG130:![0-9]+]]
	// CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8			// CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
	// CHECK2-NEXT: call void @llvm.dbg.declare(metadata i32** [[DOTBOUND_TID__ADDR]], metadata [[META130:![0-9]+]], metadata !DIExpression()), !dbg [[DBG129]]			// CHECK2-NEXT: call void @llvm.dbg.declare(metadata i32** [[DOTBOUND_TID__ADDR]], metadata [[META131:![0-9]+]], metadata !DIExpression()), !dbg [[DBG130]]
	// CHECK2-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8			// CHECK2-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
	// CHECK2-NEXT: call void @llvm.dbg.declare(metadata i64* [[VLA_ADDR]], metadata [[META131:![0-9]+]], metadata !DIExpression()), !dbg [[DBG129]]			// CHECK2-NEXT: call void @llvm.dbg.declare(metadata i64* [[VLA_ADDR]], metadata [[META132:![0-9]+]], metadata !DIExpression()), !dbg [[DBG130]]
	// CHECK2-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8			// CHECK2-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
	// CHECK2-NEXT: call void @llvm.dbg.declare(metadata i32** [[A_ADDR]], metadata [[META132:![0-9]+]], metadata !DIExpression()), !dbg [[DBG133:![0-9]+]]			// CHECK2-NEXT: call void @llvm.dbg.declare(metadata i32** [[A_ADDR]], metadata [[META133:![0-9]+]], metadata !DIExpression()), !dbg [[DBG134:![0-9]+]]
	// CHECK2-NEXT: [[TMP0:%.]] = load i64, i64 [[VLA_ADDR]], align 8, !dbg [[DBG134:![0-9]+]]			// CHECK2-NEXT: [[TMP0:%.]] = load i64, i64 [[VLA_ADDR]], align 8, !dbg [[DBG135:![0-9]+]]
	// CHECK2-NEXT: [[TMP1:%.]] = load i32, i32** [[A_ADDR]], align 8, !dbg [[DBG134]]			// CHECK2-NEXT: [[TMP1:%.]] = load i32, i32** [[A_ADDR]], align 8, !dbg [[DBG135]]
	// CHECK2-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP1]], i64 1, !dbg [[DBG135:![0-9]+]]			// CHECK2-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP1]], i64 1, !dbg [[DBG136:![0-9]+]]
	// CHECK2-NEXT: [[TMP2:%.]] = load i32, i32 [[ARRAYIDX]], align 4, !dbg [[DBG135]]			// CHECK2-NEXT: [[TMP2:%.]] = load i32, i32 [[ARRAYIDX]], align 4, !dbg [[DBG136]]
	// CHECK2-NEXT: invoke void @_Z3fooIiEvT_(i32 [[TMP2]])			// CHECK2-NEXT: invoke void @_Z3fooIiEvT_(i32 [[TMP2]])
	// CHECK2-NEXT: to label [[INVOKE_CONT:%.]] unwind label [[TERMINATE_LPAD:%.]], !dbg [[DBG134]]			// CHECK2-NEXT: to label [[INVOKE_CONT:%.]] unwind label [[TERMINATE_LPAD:%.]], !dbg [[DBG135]]
	// CHECK2: invoke.cont:			// CHECK2: invoke.cont:
	// CHECK2-NEXT: [[TMP3:%.]] = load i32, i32 @global, align 4, !dbg [[DBG136:![0-9]+]]			// CHECK2-NEXT: [[TMP3:%.]] = load i32, i32 @global, align 4, !dbg [[DBG137:![0-9]+]]
	// CHECK2-NEXT: [[ARRAYIDX1:%.]] = getelementptr inbounds i32, i32 [[TMP1]], i64 1, !dbg [[DBG137:![0-9]+]]			// CHECK2-NEXT: [[ARRAYIDX1:%.]] = getelementptr inbounds i32, i32 [[TMP1]], i64 1, !dbg [[DBG138:![0-9]+]]
	// CHECK2-NEXT: store i32 [[TMP3]], i32* [[ARRAYIDX1]], align 4, !dbg [[DBG138:![0-9]+]]			// CHECK2-NEXT: store i32 [[TMP3]], i32* [[ARRAYIDX1]], align 4, !dbg [[DBG139:![0-9]+]]
	// CHECK2-NEXT: ret void, !dbg [[DBG136]]			// CHECK2-NEXT: ret void, !dbg [[DBG137]]
	// CHECK2: terminate.lpad:			// CHECK2: terminate.lpad:
	// CHECK2-NEXT: [[TMP4:%.]] = landingpad { i8, i32 }			// CHECK2-NEXT: [[TMP4:%.]] = landingpad { i8, i32 }
	// CHECK2-NEXT: catch i8* null, !dbg [[DBG134]]			// CHECK2-NEXT: catch i8* null, !dbg [[DBG135]]
	// CHECK2-NEXT: [[TMP5:%.]] = extractvalue { i8, i32 } [[TMP4]], 0, !dbg [[DBG134]]			// CHECK2-NEXT: [[TMP5:%.]] = extractvalue { i8, i32 } [[TMP4]], 0, !dbg [[DBG135]]
	// CHECK2-NEXT: call void @__clang_call_terminate(i8* [[TMP5]]) #[[ATTR7]], !dbg [[DBG134]]			// CHECK2-NEXT: call void @__clang_call_terminate(i8* [[TMP5]]) #[[ATTR7]], !dbg [[DBG135]]
	// CHECK2-NEXT: unreachable, !dbg [[DBG134]]			// CHECK2-NEXT: unreachable, !dbg [[DBG135]]
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..7			// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..7
	// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i64 [[VLA:%.]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR3]] !dbg [[DBG139:![0-9]+]] {			// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i64 [[VLA:%.]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR3]] !dbg [[DBG140:![0-9]+]] {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8			// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8
	// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8			// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8
	// CHECK2-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8			// CHECK2-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
	// CHECK2-NEXT: [[A_ADDR:%.]] = alloca i32, align 8			// CHECK2-NEXT: [[A_ADDR:%.]] = alloca i32, align 8
	// CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK2-NEXT: call void @llvm.dbg.declare(metadata i32** [[DOTGLOBAL_TID__ADDR]], metadata [[META140:![0-9]+]], metadata !DIExpression()), !dbg [[DBG141:![0-9]+]]			// CHECK2-NEXT: call void @llvm.dbg.declare(metadata i32** [[DOTGLOBAL_TID__ADDR]], metadata [[META141:![0-9]+]], metadata !DIExpression()), !dbg [[DBG142:![0-9]+]]
	// CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8			// CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
	// CHECK2-NEXT: call void @llvm.dbg.declare(metadata i32** [[DOTBOUND_TID__ADDR]], metadata [[META142:![0-9]+]], metadata !DIExpression()), !dbg [[DBG141]]			// CHECK2-NEXT: call void @llvm.dbg.declare(metadata i32** [[DOTBOUND_TID__ADDR]], metadata [[META143:![0-9]+]], metadata !DIExpression()), !dbg [[DBG142]]
	// CHECK2-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8			// CHECK2-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
	// CHECK2-NEXT: call void @llvm.dbg.declare(metadata i64* [[VLA_ADDR]], metadata [[META143:![0-9]+]], metadata !DIExpression()), !dbg [[DBG141]]			// CHECK2-NEXT: call void @llvm.dbg.declare(metadata i64* [[VLA_ADDR]], metadata [[META144:![0-9]+]], metadata !DIExpression()), !dbg [[DBG142]]
	// CHECK2-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8			// CHECK2-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
	// CHECK2-NEXT: call void @llvm.dbg.declare(metadata i32** [[A_ADDR]], metadata [[META144:![0-9]+]], metadata !DIExpression()), !dbg [[DBG141]]			// CHECK2-NEXT: call void @llvm.dbg.declare(metadata i32** [[A_ADDR]], metadata [[META145:![0-9]+]], metadata !DIExpression()), !dbg [[DBG142]]
	// CHECK2-NEXT: [[TMP0:%.]] = load i64, i64 [[VLA_ADDR]], align 8, !dbg [[DBG145:![0-9]+]]			// CHECK2-NEXT: [[TMP0:%.]] = load i64, i64 [[VLA_ADDR]], align 8, !dbg [[DBG146:![0-9]+]]
	// CHECK2-NEXT: [[TMP1:%.]] = load i32, i32** [[A_ADDR]], align 8, !dbg [[DBG145]]			// CHECK2-NEXT: [[TMP1:%.]] = load i32, i32** [[A_ADDR]], align 8, !dbg [[DBG146]]
	// CHECK2-NEXT: [[TMP2:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG145]]			// CHECK2-NEXT: [[TMP2:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG146]]
	// CHECK2-NEXT: [[TMP3:%.]] = load i32, i32** [[DOTBOUND_TID__ADDR]], align 8, !dbg [[DBG145]]			// CHECK2-NEXT: [[TMP3:%.]] = load i32, i32** [[DOTBOUND_TID__ADDR]], align 8, !dbg [[DBG146]]
	// CHECK2-NEXT: [[TMP4:%.]] = load i32, i32** [[A_ADDR]], align 8, !dbg [[DBG145]]			// CHECK2-NEXT: [[TMP4:%.]] = load i32, i32** [[A_ADDR]], align 8, !dbg [[DBG146]]
	// CHECK2-NEXT: call void @.omp_outlined._debug__.6(i32* [[TMP2]], i32* [[TMP3]], i64 [[TMP0]], i32* [[TMP4]]) #[[ATTR6]], !dbg [[DBG145]]			// CHECK2-NEXT: call void @.omp_outlined._debug__.6(i32* [[TMP2]], i32* [[TMP3]], i64 [[TMP0]], i32* [[TMP4]]) #[[ATTR6]], !dbg [[DBG146]]
	// CHECK2-NEXT: ret void, !dbg [[DBG145]]			// CHECK2-NEXT: ret void, !dbg [[DBG146]]
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..8			// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..8
	// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i64 [[VLA:%.]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR3]] !dbg [[DBG146:![0-9]+]] {			// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i64 [[VLA:%.]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR3]] !dbg [[DBG147:![0-9]+]] {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8			// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8
	// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8			// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8
	// CHECK2-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8			// CHECK2-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
	// CHECK2-NEXT: [[A_ADDR:%.]] = alloca i32, align 8			// CHECK2-NEXT: [[A_ADDR:%.]] = alloca i32, align 8
	// CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK2-NEXT: call void @llvm.dbg.declare(metadata i32** [[DOTGLOBAL_TID__ADDR]], metadata [[META147:![0-9]+]], metadata !DIExpression()), !dbg [[DBG148:![0-9]+]]			// CHECK2-NEXT: call void @llvm.dbg.declare(metadata i32** [[DOTGLOBAL_TID__ADDR]], metadata [[META148:![0-9]+]], metadata !DIExpression()), !dbg [[DBG149:![0-9]+]]
	// CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8			// CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
	// CHECK2-NEXT: call void @llvm.dbg.declare(metadata i32** [[DOTBOUND_TID__ADDR]], metadata [[META149:![0-9]+]], metadata !DIExpression()), !dbg [[DBG148]]			// CHECK2-NEXT: call void @llvm.dbg.declare(metadata i32** [[DOTBOUND_TID__ADDR]], metadata [[META150:![0-9]+]], metadata !DIExpression()), !dbg [[DBG149]]
	// CHECK2-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8			// CHECK2-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
	// CHECK2-NEXT: call void @llvm.dbg.declare(metadata i64* [[VLA_ADDR]], metadata [[META150:![0-9]+]], metadata !DIExpression()), !dbg [[DBG148]]			// CHECK2-NEXT: call void @llvm.dbg.declare(metadata i64* [[VLA_ADDR]], metadata [[META151:![0-9]+]], metadata !DIExpression()), !dbg [[DBG149]]
	// CHECK2-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8			// CHECK2-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
	// CHECK2-NEXT: call void @llvm.dbg.declare(metadata i32** [[A_ADDR]], metadata [[META151:![0-9]+]], metadata !DIExpression()), !dbg [[DBG148]]			// CHECK2-NEXT: call void @llvm.dbg.declare(metadata i32** [[A_ADDR]], metadata [[META152:![0-9]+]], metadata !DIExpression()), !dbg [[DBG149]]
	// CHECK2-NEXT: [[TMP0:%.]] = load i64, i64 [[VLA_ADDR]], align 8, !dbg [[DBG152:![0-9]+]]			// CHECK2-NEXT: [[TMP0:%.]] = load i64, i64 [[VLA_ADDR]], align 8, !dbg [[DBG153:![0-9]+]]
	// CHECK2-NEXT: [[TMP1:%.]] = load i32, i32** [[A_ADDR]], align 8, !dbg [[DBG152]]			// CHECK2-NEXT: [[TMP1:%.]] = load i32, i32** [[A_ADDR]], align 8, !dbg [[DBG153]]
	// CHECK2-NEXT: [[TMP2:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG152]]			// CHECK2-NEXT: [[TMP2:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG153]]
	// CHECK2-NEXT: [[TMP3:%.]] = load i32, i32** [[DOTBOUND_TID__ADDR]], align 8, !dbg [[DBG152]]			// CHECK2-NEXT: [[TMP3:%.]] = load i32, i32** [[DOTBOUND_TID__ADDR]], align 8, !dbg [[DBG153]]
	// CHECK2-NEXT: [[TMP4:%.]] = load i32, i32** [[A_ADDR]], align 8, !dbg [[DBG152]]			// CHECK2-NEXT: [[TMP4:%.]] = load i32, i32** [[A_ADDR]], align 8, !dbg [[DBG153]]
	// CHECK2-NEXT: call void @.omp_outlined._debug__.5(i32* [[TMP2]], i32* [[TMP3]], i64 [[TMP0]], i32* [[TMP4]]) #[[ATTR6]], !dbg [[DBG152]]			// CHECK2-NEXT: call void @.omp_outlined._debug__.5(i32* [[TMP2]], i32* [[TMP3]], i64 [[TMP0]], i32* [[TMP4]]) #[[ATTR6]], !dbg [[DBG153]]
	// CHECK2-NEXT: ret void, !dbg [[DBG152]]			// CHECK2-NEXT: ret void, !dbg [[DBG153]]
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@_Z5tmainIPPcEiT_			// CHECK2-LABEL: define {{[^@]+}}@_Z5tmainIPPcEiT_
	// CHECK2-SAME: (i8** [[ARGC:%.*]]) #[[ATTR4]] comdat !dbg [[DBG153:![0-9]+]] {			// CHECK2-SAME: (i8** [[ARGC:%.*]]) #[[ATTR4]] comdat !dbg [[DBG154:![0-9]+]] {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	// CHECK2-NEXT: [[ARGC_ADDR:%.]] = alloca i8*, align 8			// CHECK2-NEXT: [[ARGC_ADDR:%.]] = alloca i8*, align 8
	// CHECK2-NEXT: store i8 [[ARGC]], i8* [[ARGC_ADDR]], align 8			// CHECK2-NEXT: store i8 [[ARGC]], i8* [[ARGC_ADDR]], align 8
	// CHECK2-NEXT: call void @llvm.dbg.declare(metadata i8*** [[ARGC_ADDR]], metadata [[META158:![0-9]+]], metadata !DIExpression()), !dbg [[DBG159:![0-9]+]]			// CHECK2-NEXT: call void @llvm.dbg.declare(metadata i8*** [[ARGC_ADDR]], metadata [[META159:![0-9]+]], metadata !DIExpression()), !dbg [[DBG160:![0-9]+]]
	// CHECK2-NEXT: [[TMP0:%.]] = load i8, i8** [[ARGC_ADDR]], align 8, !dbg [[DBG160:![0-9]+]]			// CHECK2-NEXT: [[TMP0:%.]] = load i8, i8** [[ARGC_ADDR]], align 8, !dbg [[DBG161:![0-9]+]]
	// CHECK2-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i8, i8** [[TMP0]], i64 0, !dbg [[DBG160]]			// CHECK2-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i8, i8** [[TMP0]], i64 0, !dbg [[DBG161]]
	// CHECK2-NEXT: [[TMP1:%.]] = load i8, i8** [[ARRAYIDX]], align 8, !dbg [[DBG160]]			// CHECK2-NEXT: [[TMP1:%.]] = load i8, i8** [[ARRAYIDX]], align 8, !dbg [[DBG161]]
	// CHECK2-NEXT: [[ARRAYIDX1:%.]] = getelementptr inbounds i8, i8 [[TMP1]], i64 0, !dbg [[DBG160]]			// CHECK2-NEXT: [[ARRAYIDX1:%.]] = getelementptr inbounds i8, i8 [[TMP1]], i64 0, !dbg [[DBG161]]
	// CHECK2-NEXT: [[TMP2:%.]] = load i8, i8 [[ARRAYIDX1]], align 1, !dbg [[DBG160]]			// CHECK2-NEXT: [[TMP2:%.]] = load i8, i8 [[ARRAYIDX1]], align 1, !dbg [[DBG161]]
	// CHECK2-NEXT: [[TMP3:%.*]] = zext i8 [[TMP2]] to i64, !dbg [[DBG161:![0-9]+]]			// CHECK2-NEXT: [[TMP3:%.*]] = zext i8 [[TMP2]] to i64, !dbg [[DBG162:![0-9]+]]
	// CHECK2-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB11:[0-9]+]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i8**, i64) @.omp_outlined..10 to void (i32, i32, ...)), i8** [[ARGC_ADDR]], i64 [[TMP3]]), !dbg [[DBG162:![0-9]+]]			// CHECK2-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB11:[0-9]+]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i8**, i64) @.omp_outlined..10 to void (i32, i32, ...)), i8** [[ARGC_ADDR]], i64 [[TMP3]]), !dbg [[DBG163:![0-9]+]]
	// CHECK2-NEXT: ret i32 0, !dbg [[DBG163:![0-9]+]]			// CHECK2-NEXT: ret i32 0, !dbg [[DBG164:![0-9]+]]
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined._debug__.9			// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined._debug__.9
	// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i8** nonnull align 8 dereferenceable(8) [[ARGC:%.]], i64 [[VLA:%.]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) !dbg [[DBG164:![0-9]+]] {			// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i8** nonnull align 8 dereferenceable(8) [[ARGC:%.]], i64 [[VLA:%.]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) !dbg [[DBG165:![0-9]+]] {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8			// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8
	// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8			// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8
	// CHECK2-NEXT: [[ARGC_ADDR:%.]] = alloca i8**, align 8			// CHECK2-NEXT: [[ARGC_ADDR:%.]] = alloca i8**, align 8
	// CHECK2-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8			// CHECK2-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
	// CHECK2-NEXT: [[VAR:%.]] = alloca double, align 8			// CHECK2-NEXT: [[VAR:%.]] = alloca double, align 8
	// CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK2-NEXT: call void @llvm.dbg.declare(metadata i32** [[DOTGLOBAL_TID__ADDR]], metadata [[META168:![0-9]+]], metadata !DIExpression()), !dbg [[DBG169:![0-9]+]]			// CHECK2-NEXT: call void @llvm.dbg.declare(metadata i32** [[DOTGLOBAL_TID__ADDR]], metadata [[META169:![0-9]+]], metadata !DIExpression()), !dbg [[DBG170:![0-9]+]]
	// CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8			// CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
	// CHECK2-NEXT: call void @llvm.dbg.declare(metadata i32** [[DOTBOUND_TID__ADDR]], metadata [[META170:![0-9]+]], metadata !DIExpression()), !dbg [[DBG169]]			// CHECK2-NEXT: call void @llvm.dbg.declare(metadata i32** [[DOTBOUND_TID__ADDR]], metadata [[META171:![0-9]+]], metadata !DIExpression()), !dbg [[DBG170]]
	// CHECK2-NEXT: store i8* [[ARGC]], i8** [[ARGC_ADDR]], align 8			// CHECK2-NEXT: store i8* [[ARGC]], i8** [[ARGC_ADDR]], align 8
	// CHECK2-NEXT: call void @llvm.dbg.declare(metadata i8**** [[ARGC_ADDR]], metadata [[META171:![0-9]+]], metadata !DIExpression()), !dbg [[DBG172:![0-9]+]]			// CHECK2-NEXT: call void @llvm.dbg.declare(metadata i8**** [[ARGC_ADDR]], metadata [[META172:![0-9]+]], metadata !DIExpression()), !dbg [[DBG173:![0-9]+]]
	// CHECK2-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8			// CHECK2-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
	// CHECK2-NEXT: call void @llvm.dbg.declare(metadata i64* [[VLA_ADDR]], metadata [[META173:![0-9]+]], metadata !DIExpression()), !dbg [[DBG169]]			// CHECK2-NEXT: call void @llvm.dbg.declare(metadata i64* [[VLA_ADDR]], metadata [[META174:![0-9]+]], metadata !DIExpression()), !dbg [[DBG170]]
	// CHECK2-NEXT: [[TMP0:%.]] = load i8, i8** [[ARGC_ADDR]], align 8, !dbg [[DBG174:![0-9]+]]			// CHECK2-NEXT: [[TMP0:%.]] = load i8, i8** [[ARGC_ADDR]], align 8, !dbg [[DBG175:![0-9]+]]
	// CHECK2-NEXT: [[TMP1:%.]] = load i64, i64 [[VLA_ADDR]], align 8, !dbg [[DBG174]]			// CHECK2-NEXT: [[TMP1:%.]] = load i64, i64 [[VLA_ADDR]], align 8, !dbg [[DBG175]]
	// CHECK2-NEXT: [[TMP2:%.]] = load i8, i8** [[TMP0]], align 8, !dbg [[DBG175:![0-9]+]]			// CHECK2-NEXT: [[TMP2:%.]] = load i8, i8** [[TMP0]], align 8, !dbg [[DBG176:![0-9]+]]
	// CHECK2-NEXT: invoke void @_Z3fooIPPcEvT_(i8** [[TMP2]])			// CHECK2-NEXT: invoke void @_Z3fooIPPcEvT_(i8** [[TMP2]])
	// CHECK2-NEXT: to label [[INVOKE_CONT:%.]] unwind label [[TERMINATE_LPAD:%.]], !dbg [[DBG177:![0-9]+]]			// CHECK2-NEXT: to label [[INVOKE_CONT:%.]] unwind label [[TERMINATE_LPAD:%.]], !dbg [[DBG178:![0-9]+]]
	// CHECK2: invoke.cont:			// CHECK2: invoke.cont:
	// CHECK2-NEXT: call void @llvm.dbg.declare(metadata double** [[VAR]], metadata [[META178:![0-9]+]], metadata !DIExpression()), !dbg [[DBG185:![0-9]+]]			// CHECK2-NEXT: call void @llvm.dbg.declare(metadata double** [[VAR]], metadata [[META179:![0-9]+]], metadata !DIExpression()), !dbg [[DBG186:![0-9]+]]
	// CHECK2-NEXT: [[TMP3:%.]] = load double, double** [[VAR]], align 8, !dbg [[DBG186:![0-9]+]]			// CHECK2-NEXT: [[TMP3:%.]] = load double, double** [[VAR]], align 8, !dbg [[DBG187:![0-9]+]]
	// CHECK2-NEXT: [[TMP4:%.*]] = mul nsw i64 0, [[TMP1]], !dbg [[DBG186]]			// CHECK2-NEXT: [[TMP4:%.*]] = mul nsw i64 0, [[TMP1]], !dbg [[DBG187]]
	// CHECK2-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds double, double [[TMP3]], i64 [[TMP4]], !dbg [[DBG186]]			// CHECK2-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds double, double [[TMP3]], i64 [[TMP4]], !dbg [[DBG187]]
	// CHECK2-NEXT: [[ARRAYIDX1:%.]] = getelementptr inbounds double, double [[ARRAYIDX]], i64 0, !dbg [[DBG186]]			// CHECK2-NEXT: [[ARRAYIDX1:%.]] = getelementptr inbounds double, double [[ARRAYIDX]], i64 0, !dbg [[DBG187]]
	// CHECK2-NEXT: ret void, !dbg [[DBG187:![0-9]+]]			// CHECK2-NEXT: ret void, !dbg [[DBG188:![0-9]+]]
	// CHECK2: terminate.lpad:			// CHECK2: terminate.lpad:
	// CHECK2-NEXT: [[TMP5:%.]] = landingpad { i8, i32 }			// CHECK2-NEXT: [[TMP5:%.]] = landingpad { i8, i32 }
	// CHECK2-NEXT: catch i8* null, !dbg [[DBG177]]			// CHECK2-NEXT: catch i8* null, !dbg [[DBG178]]
	// CHECK2-NEXT: [[TMP6:%.]] = extractvalue { i8, i32 } [[TMP5]], 0, !dbg [[DBG177]]			// CHECK2-NEXT: [[TMP6:%.]] = extractvalue { i8, i32 } [[TMP5]], 0, !dbg [[DBG178]]
	// CHECK2-NEXT: call void @__clang_call_terminate(i8* [[TMP6]]) #[[ATTR7]], !dbg [[DBG177]]			// CHECK2-NEXT: call void @__clang_call_terminate(i8* [[TMP6]]) #[[ATTR7]], !dbg [[DBG178]]
	// CHECK2-NEXT: unreachable, !dbg [[DBG177]]			// CHECK2-NEXT: unreachable, !dbg [[DBG178]]
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@_Z3fooIPPcEvT_			// CHECK2-LABEL: define {{[^@]+}}@_Z3fooIPPcEvT_
	// CHECK2-SAME: (i8** [[ARGC:%.*]]) #[[ATTR4]] comdat !dbg [[DBG188:![0-9]+]] {			// CHECK2-SAME: (i8** [[ARGC:%.*]]) #[[ATTR4]] comdat !dbg [[DBG189:![0-9]+]] {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	// CHECK2-NEXT: [[ARGC_ADDR:%.]] = alloca i8*, align 8			// CHECK2-NEXT: [[ARGC_ADDR:%.]] = alloca i8*, align 8
	// CHECK2-NEXT: store i8 [[ARGC]], i8* [[ARGC_ADDR]], align 8			// CHECK2-NEXT: store i8 [[ARGC]], i8* [[ARGC_ADDR]], align 8
	// CHECK2-NEXT: call void @llvm.dbg.declare(metadata i8*** [[ARGC_ADDR]], metadata [[META191:![0-9]+]], metadata !DIExpression()), !dbg [[DBG192:![0-9]+]]			// CHECK2-NEXT: call void @llvm.dbg.declare(metadata i8*** [[ARGC_ADDR]], metadata [[META192:![0-9]+]], metadata !DIExpression()), !dbg [[DBG193:![0-9]+]]
	// CHECK2-NEXT: ret void, !dbg [[DBG193:![0-9]+]]			// CHECK2-NEXT: ret void, !dbg [[DBG194:![0-9]+]]
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..10			// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..10
	// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i8** nonnull align 8 dereferenceable(8) [[ARGC:%.]], i64 [[VLA:%.]]) #[[ATTR3]] !dbg [[DBG194:![0-9]+]] {			// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i8** nonnull align 8 dereferenceable(8) [[ARGC:%.]], i64 [[VLA:%.]]) #[[ATTR3]] !dbg [[DBG195:![0-9]+]] {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8			// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8
	// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8			// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8
	// CHECK2-NEXT: [[ARGC_ADDR:%.]] = alloca i8**, align 8			// CHECK2-NEXT: [[ARGC_ADDR:%.]] = alloca i8**, align 8
	// CHECK2-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8			// CHECK2-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
	// CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK2-NEXT: call void @llvm.dbg.declare(metadata i32** [[DOTGLOBAL_TID__ADDR]], metadata [[META195:![0-9]+]], metadata !DIExpression()), !dbg [[DBG196:![0-9]+]]			// CHECK2-NEXT: call void @llvm.dbg.declare(metadata i32** [[DOTGLOBAL_TID__ADDR]], metadata [[META196:![0-9]+]], metadata !DIExpression()), !dbg [[DBG197:![0-9]+]]
	// CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8			// CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
	// CHECK2-NEXT: call void @llvm.dbg.declare(metadata i32** [[DOTBOUND_TID__ADDR]], metadata [[META197:![0-9]+]], metadata !DIExpression()), !dbg [[DBG196]]			// CHECK2-NEXT: call void @llvm.dbg.declare(metadata i32** [[DOTBOUND_TID__ADDR]], metadata [[META198:![0-9]+]], metadata !DIExpression()), !dbg [[DBG197]]
	// CHECK2-NEXT: store i8* [[ARGC]], i8** [[ARGC_ADDR]], align 8			// CHECK2-NEXT: store i8* [[ARGC]], i8** [[ARGC_ADDR]], align 8
	// CHECK2-NEXT: call void @llvm.dbg.declare(metadata i8**** [[ARGC_ADDR]], metadata [[META198:![0-9]+]], metadata !DIExpression()), !dbg [[DBG196]]			// CHECK2-NEXT: call void @llvm.dbg.declare(metadata i8**** [[ARGC_ADDR]], metadata [[META199:![0-9]+]], metadata !DIExpression()), !dbg [[DBG197]]
	// CHECK2-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8			// CHECK2-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
	// CHECK2-NEXT: call void @llvm.dbg.declare(metadata i64* [[VLA_ADDR]], metadata [[META199:![0-9]+]], metadata !DIExpression()), !dbg [[DBG196]]			// CHECK2-NEXT: call void @llvm.dbg.declare(metadata i64* [[VLA_ADDR]], metadata [[META200:![0-9]+]], metadata !DIExpression()), !dbg [[DBG197]]
	// CHECK2-NEXT: [[TMP0:%.]] = load i8, i8** [[ARGC_ADDR]], align 8, !dbg [[DBG200:![0-9]+]]			// CHECK2-NEXT: [[TMP0:%.]] = load i8, i8** [[ARGC_ADDR]], align 8, !dbg [[DBG201:![0-9]+]]
	// CHECK2-NEXT: [[TMP1:%.]] = load i64, i64 [[VLA_ADDR]], align 8, !dbg [[DBG200]]			// CHECK2-NEXT: [[TMP1:%.]] = load i64, i64 [[VLA_ADDR]], align 8, !dbg [[DBG201]]
	// CHECK2-NEXT: [[TMP2:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG200]]			// CHECK2-NEXT: [[TMP2:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG201]]
	// CHECK2-NEXT: [[TMP3:%.]] = load i32, i32** [[DOTBOUND_TID__ADDR]], align 8, !dbg [[DBG200]]			// CHECK2-NEXT: [[TMP3:%.]] = load i32, i32** [[DOTBOUND_TID__ADDR]], align 8, !dbg [[DBG201]]
	// CHECK2-NEXT: [[TMP4:%.]] = load i8, i8** [[ARGC_ADDR]], align 8, !dbg [[DBG200]]			// CHECK2-NEXT: [[TMP4:%.]] = load i8, i8** [[ARGC_ADDR]], align 8, !dbg [[DBG201]]
	// CHECK2-NEXT: call void @.omp_outlined._debug__.9(i32* [[TMP2]], i32* [[TMP3]], i8*** [[TMP4]], i64 [[TMP1]]) #[[ATTR6]], !dbg [[DBG200]]			// CHECK2-NEXT: call void @.omp_outlined._debug__.9(i32* [[TMP2]], i32* [[TMP3]], i8*** [[TMP4]], i64 [[TMP1]]) #[[ATTR6]], !dbg [[DBG201]]
	// CHECK2-NEXT: ret void, !dbg [[DBG200]]			// CHECK2-NEXT: ret void, !dbg [[DBG201]]
	//			//
	//			//
	// CHECK3-LABEL: define {{[^@]+}}@main			// CHECK3-LABEL: define {{[^@]+}}@main
	// CHECK3-SAME: (i32 [[ARGC:%.]], i8* [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] {			// CHECK3-SAME: (i32 [[ARGC:%.]], i8* [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] {
	// CHECK3-NEXT: entry:			// CHECK3-NEXT: entry:
	// CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4			// CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
	// CHECK3-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4			// CHECK3-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4
	// CHECK3-NEXT: [[ARGV_ADDR:%.]] = alloca i8*, align 8			// CHECK3-NEXT: [[ARGV_ADDR:%.]] = alloca i8*, align 8
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	// CHECK4-NEXT: entry:			// CHECK4-NEXT: entry:
	// CHECK4-NEXT: [[RETVAL:%.*]] = alloca i32, align 4			// CHECK4-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
	// CHECK4-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4			// CHECK4-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4
	// CHECK4-NEXT: [[ARGV_ADDR:%.]] = alloca i8*, align 8			// CHECK4-NEXT: [[ARGV_ADDR:%.]] = alloca i8*, align 8
	// CHECK4-NEXT: [[SAVED_STACK:%.]] = alloca i8, align 8			// CHECK4-NEXT: [[SAVED_STACK:%.]] = alloca i8, align 8
	// CHECK4-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8			// CHECK4-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8
	// CHECK4-NEXT: store i32 0, i32* [[RETVAL]], align 4			// CHECK4-NEXT: store i32 0, i32* [[RETVAL]], align 4
	// CHECK4-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4			// CHECK4-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4
	// CHECK4-NEXT: call void @llvm.dbg.declare(metadata i32* [[ARGC_ADDR]], metadata [[META17:![0-9]+]], metadata !DIExpression()), !dbg [[DBG18:![0-9]+]]			// CHECK4-NEXT: call void @llvm.dbg.declare(metadata i32* [[ARGC_ADDR]], metadata [[META18:![0-9]+]], metadata !DIExpression()), !dbg [[DBG19:![0-9]+]]
	// CHECK4-NEXT: store i8 [[ARGV]], i8* [[ARGV_ADDR]], align 8			// CHECK4-NEXT: store i8 [[ARGV]], i8* [[ARGV_ADDR]], align 8
	// CHECK4-NEXT: call void @llvm.dbg.declare(metadata i8*** [[ARGV_ADDR]], metadata [[META19:![0-9]+]], metadata !DIExpression()), !dbg [[DBG18]]			// CHECK4-NEXT: call void @llvm.dbg.declare(metadata i8*** [[ARGV_ADDR]], metadata [[META20:![0-9]+]], metadata !DIExpression()), !dbg [[DBG19]]
	// CHECK4-NEXT: [[TMP0:%.]] = load i32, i32 [[ARGC_ADDR]], align 4, !dbg [[DBG20:![0-9]+]]			// CHECK4-NEXT: [[TMP0:%.]] = load i32, i32 [[ARGC_ADDR]], align 4, !dbg [[DBG21:![0-9]+]]
	// CHECK4-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64, !dbg [[DBG20]]			// CHECK4-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64, !dbg [[DBG21]]
	// CHECK4-NEXT: [[TMP2:%.]] = call i8 @llvm.stacksave(), !dbg [[DBG20]]			// CHECK4-NEXT: [[TMP2:%.]] = call i8 @llvm.stacksave(), !dbg [[DBG21]]
	// CHECK4-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8, !dbg [[DBG20]]			// CHECK4-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8, !dbg [[DBG21]]
	// CHECK4-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 16, !dbg [[DBG20]]			// CHECK4-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 16, !dbg [[DBG21]]
	// CHECK4-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8, !dbg [[DBG20]]			// CHECK4-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8, !dbg [[DBG21]]
	// CHECK4-NEXT: call void @llvm.dbg.declare(metadata i64* [[__VLA_EXPR0]], metadata [[META21:![0-9]+]], metadata !DIExpression()), !dbg [[DBG23:![0-9]+]]			// CHECK4-NEXT: call void @llvm.dbg.declare(metadata i64* [[__VLA_EXPR0]], metadata [[META22:![0-9]+]], metadata !DIExpression()), !dbg [[DBG24:![0-9]+]]
	// CHECK4-NEXT: call void @llvm.dbg.declare(metadata i32* [[VLA]], metadata [[META24:![0-9]+]], metadata !DIExpression()), !dbg [[DBG20]]			// CHECK4-NEXT: call void @llvm.dbg.declare(metadata i32* [[VLA]], metadata [[META25:![0-9]+]], metadata !DIExpression()), !dbg [[DBG21]]
	// CHECK4-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB1:[0-9]+]]), !dbg [[DBG28:![0-9]+]]			// CHECK4-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB1:[0-9]+]]), !dbg [[DBG29:![0-9]+]]
	// CHECK4-NEXT: br label [[OMP_PARALLEL:%.*]]			// CHECK4-NEXT: br label [[OMP_PARALLEL:%.*]]
	// CHECK4: omp_parallel:			// CHECK4: omp_parallel:
	// CHECK4-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32, i32, ...)* bitcast (void (i32, i32, i32) @main..omp_par to void (i32, i32, ...)), i32 [[VLA]]), !dbg [[DBG29:![0-9]+]]			// CHECK4-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32, i32, ...)* bitcast (void (i32, i32, i32) @main..omp_par to void (i32, i32, ...)), i32 [[VLA]]), !dbg [[DBG30:![0-9]+]]
	// CHECK4-NEXT: br label [[OMP_PAR_OUTLINED_EXIT:%.*]]			// CHECK4-NEXT: br label [[OMP_PAR_OUTLINED_EXIT:%.*]]
	// CHECK4: omp.par.outlined.exit:			// CHECK4: omp.par.outlined.exit:
	// CHECK4-NEXT: br label [[OMP_PAR_EXIT_SPLIT:%.*]]			// CHECK4-NEXT: br label [[OMP_PAR_EXIT_SPLIT:%.*]]
	// CHECK4: omp.par.exit.split:			// CHECK4: omp.par.exit.split:
	// CHECK4-NEXT: [[TMP3:%.]] = load i8, i8** [[ARGV_ADDR]], align 8, !dbg [[DBG30:![0-9]+]]			// CHECK4-NEXT: [[TMP3:%.]] = load i8, i8** [[ARGV_ADDR]], align 8, !dbg [[DBG31:![0-9]+]]
	// CHECK4-NEXT: [[CALL:%.]] = call i32 @_Z5tmainIPPcEiT_(i8* [[TMP3]]), !dbg [[DBG30]]			// CHECK4-NEXT: [[CALL:%.]] = call i32 @_Z5tmainIPPcEiT_(i8* [[TMP3]]), !dbg [[DBG31]]
	// CHECK4-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4, !dbg [[DBG30]]			// CHECK4-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4, !dbg [[DBG31]]
	// CHECK4-NEXT: [[TMP4:%.]] = load i8, i8** [[SAVED_STACK]], align 8, !dbg [[DBG31:![0-9]+]]			// CHECK4-NEXT: [[TMP4:%.]] = load i8, i8** [[SAVED_STACK]], align 8, !dbg [[DBG32:![0-9]+]]
	// CHECK4-NEXT: call void @llvm.stackrestore(i8* [[TMP4]]), !dbg [[DBG31]]			// CHECK4-NEXT: call void @llvm.stackrestore(i8* [[TMP4]]), !dbg [[DBG32]]
	// CHECK4-NEXT: [[TMP5:%.]] = load i32, i32 [[RETVAL]], align 4, !dbg [[DBG31]]			// CHECK4-NEXT: [[TMP5:%.]] = load i32, i32 [[RETVAL]], align 4, !dbg [[DBG32]]
	// CHECK4-NEXT: ret i32 [[TMP5]], !dbg [[DBG31]]			// CHECK4-NEXT: ret i32 [[TMP5]], !dbg [[DBG32]]
	//			//
	//			//
	// CHECK4-LABEL: define {{[^@]+}}@main..omp_par			// CHECK4-LABEL: define {{[^@]+}}@main..omp_par
	// CHECK4-SAME: (i32* noalias [[TID_ADDR:%.]], i32 noalias [[ZERO_ADDR:%.]], i32 [[VLA:%.*]]) #[[ATTR1:[0-9]+]] !dbg [[DBG32:![0-9]+]] {			// CHECK4-SAME: (i32* noalias [[TID_ADDR:%.]], i32 noalias [[ZERO_ADDR:%.]], i32 [[VLA:%.*]]) #[[ATTR1:[0-9]+]] !dbg [[DBG33:![0-9]+]] {
	// CHECK4-NEXT: omp.par.entry:			// CHECK4-NEXT: omp.par.entry:
	// CHECK4-NEXT: [[TID_ADDR_LOCAL:%.*]] = alloca i32, align 4			// CHECK4-NEXT: [[TID_ADDR_LOCAL:%.*]] = alloca i32, align 4
	// CHECK4-NEXT: [[TMP0:%.]] = load i32, i32 [[TID_ADDR]], align 4			// CHECK4-NEXT: [[TMP0:%.]] = load i32, i32 [[TID_ADDR]], align 4
	// CHECK4-NEXT: store i32 [[TMP0]], i32* [[TID_ADDR_LOCAL]], align 4			// CHECK4-NEXT: store i32 [[TMP0]], i32* [[TID_ADDR_LOCAL]], align 4
	// CHECK4-NEXT: [[TID:%.]] = load i32, i32 [[TID_ADDR_LOCAL]], align 4			// CHECK4-NEXT: [[TID:%.]] = load i32, i32 [[TID_ADDR_LOCAL]], align 4
	// CHECK4-NEXT: br label [[OMP_PAR_REGION:%.*]]			// CHECK4-NEXT: br label [[OMP_PAR_REGION:%.*]]
	// CHECK4: omp.par.region:			// CHECK4: omp.par.region:
	// CHECK4-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[VLA]], i64 1, !dbg [[DBG34:![0-9]+]]			// CHECK4-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[VLA]], i64 1, !dbg [[DBG35:![0-9]+]]
	// CHECK4-NEXT: [[TMP1:%.]] = load i32, i32 [[ARRAYIDX]], align 4, !dbg [[DBG34]]			// CHECK4-NEXT: [[TMP1:%.]] = load i32, i32 [[ARRAYIDX]], align 4, !dbg [[DBG35]]
	// CHECK4-NEXT: call void @_Z3fooIiEvT_(i32 [[TMP1]]), !dbg [[DBG34]]			// CHECK4-NEXT: call void @_Z3fooIiEvT_(i32 [[TMP1]]), !dbg [[DBG35]]
	// CHECK4-NEXT: [[TMP2:%.]] = load i32, i32 @global, align 4, !dbg [[DBG34]]			// CHECK4-NEXT: [[TMP2:%.]] = load i32, i32 @global, align 4, !dbg [[DBG35]]
	// CHECK4-NEXT: [[ARRAYIDX1:%.]] = getelementptr inbounds i32, i32 [[VLA]], i64 1, !dbg [[DBG34]]			// CHECK4-NEXT: [[ARRAYIDX1:%.]] = getelementptr inbounds i32, i32 [[VLA]], i64 1, !dbg [[DBG35]]
	// CHECK4-NEXT: store i32 [[TMP2]], i32* [[ARRAYIDX1]], align 4, !dbg [[DBG34]]			// CHECK4-NEXT: store i32 [[TMP2]], i32* [[ARRAYIDX1]], align 4, !dbg [[DBG35]]
	// CHECK4-NEXT: br label [[OMP_PAR_PRE_FINALIZE:%.*]], !dbg [[DBG34]]			// CHECK4-NEXT: br label [[OMP_PAR_PRE_FINALIZE:%.*]], !dbg [[DBG35]]
	// CHECK4: omp.par.pre_finalize:			// CHECK4: omp.par.pre_finalize:
	// CHECK4-NEXT: br label [[OMP_PAR_OUTLINED_EXIT_EXITSTUB:%.*]], !dbg [[DBG34]]			// CHECK4-NEXT: br label [[OMP_PAR_OUTLINED_EXIT_EXITSTUB:%.*]], !dbg [[DBG35]]
	// CHECK4: omp.par.outlined.exit.exitStub:			// CHECK4: omp.par.outlined.exit.exitStub:
	// CHECK4-NEXT: ret void			// CHECK4-NEXT: ret void
	//			//
	//			//
	// CHECK4-LABEL: define {{[^@]+}}@_Z3fooIiEvT_			// CHECK4-LABEL: define {{[^@]+}}@_Z3fooIiEvT_
	// CHECK4-SAME: (i32 [[ARGC:%.*]]) #[[ATTR5:[0-9]+]] comdat !dbg [[DBG35:![0-9]+]] {			// CHECK4-SAME: (i32 [[ARGC:%.*]]) #[[ATTR5:[0-9]+]] comdat !dbg [[DBG36:![0-9]+]] {
	// CHECK4-NEXT: entry:			// CHECK4-NEXT: entry:
	// CHECK4-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4			// CHECK4-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4
	// CHECK4-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4			// CHECK4-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4
	// CHECK4-NEXT: call void @llvm.dbg.declare(metadata i32* [[ARGC_ADDR]], metadata [[META40:![0-9]+]], metadata !DIExpression()), !dbg [[DBG41:![0-9]+]]			// CHECK4-NEXT: call void @llvm.dbg.declare(metadata i32* [[ARGC_ADDR]], metadata [[META41:![0-9]+]], metadata !DIExpression()), !dbg [[DBG42:![0-9]+]]
	// CHECK4-NEXT: ret void, !dbg [[DBG41]]			// CHECK4-NEXT: ret void, !dbg [[DBG42]]
	//			//
	//			//
	// CHECK4-LABEL: define {{[^@]+}}@_Z5tmainIPPcEiT_			// CHECK4-LABEL: define {{[^@]+}}@_Z5tmainIPPcEiT_
	// CHECK4-SAME: (i8** [[ARGC:%.*]]) #[[ATTR6:[0-9]+]] comdat !dbg [[DBG44:![0-9]+]] {			// CHECK4-SAME: (i8** [[ARGC:%.*]]) #[[ATTR6:[0-9]+]] comdat !dbg [[DBG45:![0-9]+]] {
	// CHECK4-NEXT: entry:			// CHECK4-NEXT: entry:
	// CHECK4-NEXT: [[DOTRELOADED:%.*]] = alloca i64, align 8			// CHECK4-NEXT: [[DOTRELOADED:%.*]] = alloca i64, align 8
	// CHECK4-NEXT: [[ARGC_ADDR:%.]] = alloca i8*, align 8			// CHECK4-NEXT: [[ARGC_ADDR:%.]] = alloca i8*, align 8
	// CHECK4-NEXT: store i8 [[ARGC]], i8* [[ARGC_ADDR]], align 8			// CHECK4-NEXT: store i8 [[ARGC]], i8* [[ARGC_ADDR]], align 8
	// CHECK4-NEXT: call void @llvm.dbg.declare(metadata i8*** [[ARGC_ADDR]], metadata [[META49:![0-9]+]], metadata !DIExpression()), !dbg [[DBG50:![0-9]+]]			// CHECK4-NEXT: call void @llvm.dbg.declare(metadata i8*** [[ARGC_ADDR]], metadata [[META50:![0-9]+]], metadata !DIExpression()), !dbg [[DBG51:![0-9]+]]
	// CHECK4-NEXT: [[TMP0:%.]] = load i8, i8** [[ARGC_ADDR]], align 8, !dbg [[DBG51:![0-9]+]]			// CHECK4-NEXT: [[TMP0:%.]] = load i8, i8** [[ARGC_ADDR]], align 8, !dbg [[DBG52:![0-9]+]]
	// CHECK4-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i8, i8** [[TMP0]], i64 0, !dbg [[DBG51]]			// CHECK4-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i8, i8** [[TMP0]], i64 0, !dbg [[DBG52]]
	// CHECK4-NEXT: [[TMP1:%.]] = load i8, i8** [[ARRAYIDX]], align 8, !dbg [[DBG51]]			// CHECK4-NEXT: [[TMP1:%.]] = load i8, i8** [[ARRAYIDX]], align 8, !dbg [[DBG52]]
	// CHECK4-NEXT: [[ARRAYIDX1:%.]] = getelementptr inbounds i8, i8 [[TMP1]], i64 0, !dbg [[DBG51]]			// CHECK4-NEXT: [[ARRAYIDX1:%.]] = getelementptr inbounds i8, i8 [[TMP1]], i64 0, !dbg [[DBG52]]
	// CHECK4-NEXT: [[TMP2:%.]] = load i8, i8 [[ARRAYIDX1]], align 1, !dbg [[DBG51]]			// CHECK4-NEXT: [[TMP2:%.]] = load i8, i8 [[ARRAYIDX1]], align 1, !dbg [[DBG52]]
	// CHECK4-NEXT: [[TMP3:%.*]] = zext i8 [[TMP2]] to i64, !dbg [[DBG51]]			// CHECK4-NEXT: [[TMP3:%.*]] = zext i8 [[TMP2]] to i64, !dbg [[DBG52]]
	// CHECK4-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB3:[0-9]+]]), !dbg [[DBG52:![0-9]+]]			// CHECK4-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB3:[0-9]+]]), !dbg [[DBG53:![0-9]+]]
	// CHECK4-NEXT: store i64 [[TMP3]], i64* [[DOTRELOADED]], align 8			// CHECK4-NEXT: store i64 [[TMP3]], i64* [[DOTRELOADED]], align 8
	// CHECK4-NEXT: br label [[OMP_PARALLEL:%.*]]			// CHECK4-NEXT: br label [[OMP_PARALLEL:%.*]]
	// CHECK4: omp_parallel:			// CHECK4: omp_parallel:
	// CHECK4-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i8*) @_Z5tmainIPPcEiT_..omp_par to void (i32, i32, ...)), i64 [[DOTRELOADED]], i8*** [[ARGC_ADDR]]), !dbg [[DBG53:![0-9]+]]			// CHECK4-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i8*) @_Z5tmainIPPcEiT_..omp_par to void (i32, i32, ...)), i64 [[DOTRELOADED]], i8*** [[ARGC_ADDR]]), !dbg [[DBG54:![0-9]+]]
	// CHECK4-NEXT: br label [[OMP_PAR_OUTLINED_EXIT:%.*]]			// CHECK4-NEXT: br label [[OMP_PAR_OUTLINED_EXIT:%.*]]
	// CHECK4: omp.par.outlined.exit:			// CHECK4: omp.par.outlined.exit:
	// CHECK4-NEXT: br label [[OMP_PAR_EXIT_SPLIT:%.*]]			// CHECK4-NEXT: br label [[OMP_PAR_EXIT_SPLIT:%.*]]
	// CHECK4: omp.par.exit.split:			// CHECK4: omp.par.exit.split:
	// CHECK4-NEXT: ret i32 0, !dbg [[DBG55:![0-9]+]]			// CHECK4-NEXT: ret i32 0, !dbg [[DBG56:![0-9]+]]
	//			//
	//			//
	// CHECK4-LABEL: define {{[^@]+}}@_Z5tmainIPPcEiT_..omp_par			// CHECK4-LABEL: define {{[^@]+}}@_Z5tmainIPPcEiT_..omp_par
	// CHECK4-SAME: (i32* noalias [[TID_ADDR:%.]], i32 noalias [[ZERO_ADDR:%.]], i64 [[DOTRELOADED:%.]], i8** [[ARGC_ADDR:%.*]]) #[[ATTR1]] !dbg [[DBG56:![0-9]+]] {			// CHECK4-SAME: (i32* noalias [[TID_ADDR:%.]], i32 noalias [[ZERO_ADDR:%.]], i64 [[DOTRELOADED:%.]], i8** [[ARGC_ADDR:%.*]]) #[[ATTR1]] !dbg [[DBG57:![0-9]+]] {
	// CHECK4-NEXT: omp.par.entry:			// CHECK4-NEXT: omp.par.entry:
	// CHECK4-NEXT: [[TID_ADDR_LOCAL:%.*]] = alloca i32, align 4			// CHECK4-NEXT: [[TID_ADDR_LOCAL:%.*]] = alloca i32, align 4
	// CHECK4-NEXT: [[TMP0:%.]] = load i32, i32 [[TID_ADDR]], align 4			// CHECK4-NEXT: [[TMP0:%.]] = load i32, i32 [[TID_ADDR]], align 4
	// CHECK4-NEXT: store i32 [[TMP0]], i32* [[TID_ADDR_LOCAL]], align 4			// CHECK4-NEXT: store i32 [[TMP0]], i32* [[TID_ADDR_LOCAL]], align 4
	// CHECK4-NEXT: [[TID:%.]] = load i32, i32 [[TID_ADDR_LOCAL]], align 4			// CHECK4-NEXT: [[TID:%.]] = load i32, i32 [[TID_ADDR_LOCAL]], align 4
	// CHECK4-NEXT: [[TMP1:%.]] = load i64, i64 [[DOTRELOADED]], align 8			// CHECK4-NEXT: [[TMP1:%.]] = load i64, i64 [[DOTRELOADED]], align 8
	// CHECK4-NEXT: [[VAR:%.]] = alloca double, align 8			// CHECK4-NEXT: [[VAR:%.]] = alloca double, align 8
	// CHECK4-NEXT: br label [[OMP_PAR_REGION:%.*]]			// CHECK4-NEXT: br label [[OMP_PAR_REGION:%.*]]
	// CHECK4: omp.par.region:			// CHECK4: omp.par.region:
	// CHECK4-NEXT: [[TMP2:%.]] = load i8, i8** [[ARGC_ADDR]], align 8, !dbg [[DBG57:![0-9]+]]			// CHECK4-NEXT: [[TMP2:%.]] = load i8, i8** [[ARGC_ADDR]], align 8, !dbg [[DBG58:![0-9]+]]
	// CHECK4-NEXT: call void @_Z3fooIPPcEvT_(i8** [[TMP2]]), !dbg [[DBG57]]			// CHECK4-NEXT: call void @_Z3fooIPPcEvT_(i8** [[TMP2]]), !dbg [[DBG58]]
	// CHECK4-NEXT: call void @llvm.dbg.declare(metadata double** [[VAR]], metadata [[META58:![0-9]+]], metadata !DIExpression()), !dbg [[DBG65:![0-9]+]]			// CHECK4-NEXT: call void @llvm.dbg.declare(metadata double** [[VAR]], metadata [[META59:![0-9]+]], metadata !DIExpression()), !dbg [[DBG66:![0-9]+]]
	// CHECK4-NEXT: [[TMP3:%.]] = load double, double** [[VAR]], align 8, !dbg [[DBG65]]			// CHECK4-NEXT: [[TMP3:%.]] = load double, double** [[VAR]], align 8, !dbg [[DBG66]]
	// CHECK4-NEXT: [[TMP4:%.*]] = mul nsw i64 0, [[TMP1]], !dbg [[DBG65]]			// CHECK4-NEXT: [[TMP4:%.*]] = mul nsw i64 0, [[TMP1]], !dbg [[DBG66]]
	// CHECK4-NEXT: [[ARRAYIDX2:%.]] = getelementptr inbounds double, double [[TMP3]], i64 [[TMP4]], !dbg [[DBG65]]			// CHECK4-NEXT: [[ARRAYIDX2:%.]] = getelementptr inbounds double, double [[TMP3]], i64 [[TMP4]], !dbg [[DBG66]]
	// CHECK4-NEXT: [[ARRAYIDX3:%.]] = getelementptr inbounds double, double [[ARRAYIDX2]], i64 0, !dbg [[DBG65]]			// CHECK4-NEXT: [[ARRAYIDX3:%.]] = getelementptr inbounds double, double [[ARRAYIDX2]], i64 0, !dbg [[DBG66]]
	// CHECK4-NEXT: br label [[OMP_PAR_PRE_FINALIZE:%.*]], !dbg [[DBG66:![0-9]+]]			// CHECK4-NEXT: br label [[OMP_PAR_PRE_FINALIZE:%.*]], !dbg [[DBG67:![0-9]+]]
	// CHECK4: omp.par.pre_finalize:			// CHECK4: omp.par.pre_finalize:
	// CHECK4-NEXT: br label [[OMP_PAR_OUTLINED_EXIT_EXITSTUB:%.*]], !dbg [[DBG66]]			// CHECK4-NEXT: br label [[OMP_PAR_OUTLINED_EXIT_EXITSTUB:%.*]], !dbg [[DBG67]]
	// CHECK4: omp.par.outlined.exit.exitStub:			// CHECK4: omp.par.outlined.exit.exitStub:
	// CHECK4-NEXT: ret void			// CHECK4-NEXT: ret void
	//			//
	//			//
	// CHECK4-LABEL: define {{[^@]+}}@_Z3fooIPPcEvT_			// CHECK4-LABEL: define {{[^@]+}}@_Z3fooIPPcEvT_
	// CHECK4-SAME: (i8** [[ARGC:%.*]]) #[[ATTR5]] comdat !dbg [[DBG67:![0-9]+]] {			// CHECK4-SAME: (i8** [[ARGC:%.*]]) #[[ATTR5]] comdat !dbg [[DBG68:![0-9]+]] {
	// CHECK4-NEXT: entry:			// CHECK4-NEXT: entry:
	// CHECK4-NEXT: [[ARGC_ADDR:%.]] = alloca i8*, align 8			// CHECK4-NEXT: [[ARGC_ADDR:%.]] = alloca i8*, align 8
	// CHECK4-NEXT: store i8 [[ARGC]], i8* [[ARGC_ADDR]], align 8			// CHECK4-NEXT: store i8 [[ARGC]], i8* [[ARGC_ADDR]], align 8
	// CHECK4-NEXT: call void @llvm.dbg.declare(metadata i8*** [[ARGC_ADDR]], metadata [[META70:![0-9]+]], metadata !DIExpression()), !dbg [[DBG71:![0-9]+]]			// CHECK4-NEXT: call void @llvm.dbg.declare(metadata i8*** [[ARGC_ADDR]], metadata [[META71:![0-9]+]], metadata !DIExpression()), !dbg [[DBG72:![0-9]+]]
	// CHECK4-NEXT: ret void, !dbg [[DBG71]]			// CHECK4-NEXT: ret void, !dbg [[DBG72]]
	//
	//			//

clang/test/OpenMP/parallel_for_simd_aligned_codegen.cpp

	Show First 20 Lines • Show All 65 Lines • ▼ Show 20 Lines
	// CHECK1-NEXT: br label [[COND_END]]			// CHECK1-NEXT: br label [[COND_END]]
	// CHECK1: cond.end:			// CHECK1: cond.end:
	// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]			// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
	// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK1-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK1: omp.inner.for.cond:			// CHECK1: omp.inner.for.cond:
	// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !3
	// CHECK1-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK1-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !3
	// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK1: omp.inner.for.body:			// CHECK1: omp.inner.for.body:
	// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !3
	// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !3
	// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK1: omp.body.continue:			// CHECK1: omp.body.continue:
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK1: omp.inner.for.inc:			// CHECK1: omp.inner.for.inc:
	// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !3
	// CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK1-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]
	// CHECK1: omp.inner.for.end:			// CHECK1: omp.inner.for.end:
	// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK1: omp.loop.exit:			// CHECK1: omp.loop.exit:
	// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])			// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
	// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK1-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK1-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK1-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK1-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK1: .omp.final.then:			// CHECK1: .omp.final.then:
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	// CHECK2-NEXT: br label [[COND_END]]			// CHECK2-NEXT: br label [[COND_END]]
	// CHECK2: cond.end:			// CHECK2: cond.end:
	// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]			// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
	// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK2-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK2: omp.inner.for.cond:			// CHECK2: omp.inner.for.cond:
	// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !3
	// CHECK2-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK2-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !3
	// CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK2: omp.inner.for.body:			// CHECK2: omp.inner.for.body:
	// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !3
	// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !3
	// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK2: omp.body.continue:			// CHECK2: omp.body.continue:
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK2: omp.inner.for.inc:			// CHECK2: omp.inner.for.inc:
	// CHECK2-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !3
	// CHECK2-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK2-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK2-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]
	// CHECK2: omp.inner.for.end:			// CHECK2: omp.inner.for.end:
	// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK2: omp.loop.exit:			// CHECK2: omp.loop.exit:
	// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])			// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
	// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK2-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK2-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK2-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK2-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK2: .omp.final.then:			// CHECK2: .omp.final.then:
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	// CHECK3-NEXT: br label [[COND_END]]			// CHECK3-NEXT: br label [[COND_END]]
	// CHECK3: cond.end:			// CHECK3: cond.end:
	// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]			// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
	// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK3-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK3-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK3-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK3-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK3: omp.inner.for.cond:			// CHECK3: omp.inner.for.cond:
	// CHECK3-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK3-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !3
	// CHECK3-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK3-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !3
	// CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK3: omp.inner.for.body:			// CHECK3: omp.inner.for.body:
	// CHECK3-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK3-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !3
	// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !3
	// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK3: omp.body.continue:			// CHECK3: omp.body.continue:
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK3: omp.inner.for.inc:			// CHECK3: omp.inner.for.inc:
	// CHECK3-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK3-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !3
	// CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK3-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4			// CHECK3-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]
	// CHECK3: omp.inner.for.end:			// CHECK3: omp.inner.for.end:
	// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK3: omp.loop.exit:			// CHECK3: omp.loop.exit:
	// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])			// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
	// CHECK3-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK3-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK3-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK3-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK3-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK3-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK3: .omp.final.then:			// CHECK3: .omp.final.then:
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	// CHECK4-NEXT: br label [[COND_END]]			// CHECK4-NEXT: br label [[COND_END]]
	// CHECK4: cond.end:			// CHECK4: cond.end:
	// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]			// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
	// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK4-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK4-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK4-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK4-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK4: omp.inner.for.cond:			// CHECK4: omp.inner.for.cond:
	// CHECK4-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK4-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !3
	// CHECK4-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK4-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !3
	// CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK4: omp.inner.for.body:			// CHECK4: omp.inner.for.body:
	// CHECK4-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK4-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !3
	// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !3
	// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK4: omp.body.continue:			// CHECK4: omp.body.continue:
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK4: omp.inner.for.inc:			// CHECK4: omp.inner.for.inc:
	// CHECK4-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK4-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !3
	// CHECK4-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK4-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK4-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4			// CHECK4-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]
	// CHECK4: omp.inner.for.end:			// CHECK4: omp.inner.for.end:
	// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK4: omp.loop.exit:			// CHECK4: omp.loop.exit:
	// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])			// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
	// CHECK4-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK4-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK4-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK4-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK4-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK4-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK4: .omp.final.then:			// CHECK4: .omp.final.then:
	// CHECK4-NEXT: store i32 10, i32* [[I]], align 4			// CHECK4-NEXT: store i32 10, i32* [[I]], align 4
	// CHECK4-NEXT: br label [[DOTOMP_FINAL_DONE]]			// CHECK4-NEXT: br label [[DOTOMP_FINAL_DONE]]
	// CHECK4: .omp.final.done:			// CHECK4: .omp.final.done:
	// CHECK4-NEXT: ret void			// CHECK4-NEXT: ret void
	//			//

clang/test/OpenMP/parallel_private_codegen.cpp

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	// CHECK4-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP3]], -1			// CHECK4-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP3]], -1
	// CHECK4-NEXT: store i32 [[DEC]], i32* [[B]], align 4			// CHECK4-NEXT: store i32 [[DEC]], i32* [[B]], align 4
	// CHECK4-NEXT: [[TMP4:%.]] = load i32, i32** [[_TMP1]], align 8			// CHECK4-NEXT: [[TMP4:%.]] = load i32, i32** [[_TMP1]], align 8
	// CHECK4-NEXT: [[TMP5:%.]] = load i32, i32 [[TMP4]], align 4			// CHECK4-NEXT: [[TMP5:%.]] = load i32, i32 [[TMP4]], align 4
	// CHECK4-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP5]], 1			// CHECK4-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP5]], 1
	// CHECK4-NEXT: store i32 [[DIV]], i32* [[TMP4]], align 4			// CHECK4-NEXT: store i32 [[DIV]], i32* [[TMP4]], align 4
	// CHECK4-NEXT: ret void			// CHECK4-NEXT: ret void
	//			//
	//
	No newline at end of file

clang/test/OpenMP/parallel_reduction_codegen.cpp

This file is larger than 256 KB, so syntax highlighting is disabled by default.

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	// CHECK1-NEXT: [[TMP6:%.]] = load float, float [[T_VAR2]], align 4			// CHECK1-NEXT: [[TMP6:%.]] = load float, float [[T_VAR2]], align 4
	// CHECK1-NEXT: [[CONV:%.*]] = fptosi float [[TMP6]] to i32			// CHECK1-NEXT: [[CONV:%.*]] = fptosi float [[TMP6]] to i32
	// CHECK1-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[TMP0]], i64 0, i64 0			// CHECK1-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[TMP0]], i64 0, i64 0
	// CHECK1-NEXT: store i32 [[CONV]], i32* [[ARRAYIDX]], align 4			// CHECK1-NEXT: store i32 [[CONV]], i32* [[ARRAYIDX]], align 4
	// CHECK1-NEXT: [[ARRAYIDX6:%.]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S] [[TMP2]], i64 0, i64 0			// CHECK1-NEXT: [[ARRAYIDX6:%.]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S] [[TMP2]], i64 0, i64 0
	// CHECK1-NEXT: [[TMP7:%.]] = bitcast %struct.S [[ARRAYIDX6]] to i8*			// CHECK1-NEXT: [[TMP7:%.]] = bitcast %struct.S [[ARRAYIDX6]] to i8*
	// CHECK1-NEXT: [[TMP8:%.]] = bitcast %struct.S [[VAR3]] to i8*			// CHECK1-NEXT: [[TMP8:%.]] = bitcast %struct.S [[VAR3]] to i8*
	// CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP7]], i8* align 4 [[TMP8]], i64 4, i1 false)			// CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP7]], i8* align 4 [[TMP8]], i64 4, i1 false)
	// CHECK1-NEXT: br label [[WHILE_COND]], !llvm.loop [[LOOP4:![0-9]+]]			// CHECK1-NEXT: br label [[WHILE_COND]], !llvm.loop [[LOOP5:![0-9]+]]
	//			//
	//			//
	// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..4			// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..4
	// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], { float, float } nonnull align 4 dereferenceable(8) [[CF:%.*]]) #[[ATTR1]] {			// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], { float, float } nonnull align 4 dereferenceable(8) [[CF:%.*]]) #[[ATTR1]] {
	// CHECK1-NEXT: entry:			// CHECK1-NEXT: entry:
	// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8			// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8
	// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8			// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8
	// CHECK1-NEXT: [[CF_ADDR:%.]] = alloca { float, float }, align 8			// CHECK1-NEXT: [[CF_ADDR:%.]] = alloca { float, float }, align 8
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	// CHECK2-NEXT: [[TMP6:%.]] = load float, float [[T_VAR2]], align 4			// CHECK2-NEXT: [[TMP6:%.]] = load float, float [[T_VAR2]], align 4
	// CHECK2-NEXT: [[CONV:%.*]] = fptosi float [[TMP6]] to i32			// CHECK2-NEXT: [[CONV:%.*]] = fptosi float [[TMP6]] to i32
	// CHECK2-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[TMP0]], i64 0, i64 0			// CHECK2-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[TMP0]], i64 0, i64 0
	// CHECK2-NEXT: store i32 [[CONV]], i32* [[ARRAYIDX]], align 4			// CHECK2-NEXT: store i32 [[CONV]], i32* [[ARRAYIDX]], align 4
	// CHECK2-NEXT: [[ARRAYIDX6:%.]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S] [[TMP2]], i64 0, i64 0			// CHECK2-NEXT: [[ARRAYIDX6:%.]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S] [[TMP2]], i64 0, i64 0
	// CHECK2-NEXT: [[TMP7:%.]] = bitcast %struct.S [[ARRAYIDX6]] to i8*			// CHECK2-NEXT: [[TMP7:%.]] = bitcast %struct.S [[ARRAYIDX6]] to i8*
	// CHECK2-NEXT: [[TMP8:%.]] = bitcast %struct.S [[VAR3]] to i8*			// CHECK2-NEXT: [[TMP8:%.]] = bitcast %struct.S [[VAR3]] to i8*
	// CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP7]], i8* align 4 [[TMP8]], i64 4, i1 false)			// CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP7]], i8* align 4 [[TMP8]], i64 4, i1 false)
	// CHECK2-NEXT: br label [[WHILE_COND]], !llvm.loop [[LOOP4:![0-9]+]]			// CHECK2-NEXT: br label [[WHILE_COND]], !llvm.loop [[LOOP5:![0-9]+]]
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..4			// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..4
	// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], { float, float } nonnull align 4 dereferenceable(8) [[CF:%.*]]) #[[ATTR1]] {			// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], { float, float } nonnull align 4 dereferenceable(8) [[CF:%.*]]) #[[ATTR1]] {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8			// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8
	// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8			// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8
	// CHECK2-NEXT: [[CF_ADDR:%.]] = alloca { float, float }, align 8			// CHECK2-NEXT: [[CF_ADDR:%.]] = alloca { float, float }, align 8
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	// CHECK4-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP26]], [[TMP27]]			// CHECK4-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP26]], [[TMP27]]
	// CHECK4-NEXT: store i32 [[ADD2]], i32* [[TMP17]], align 4			// CHECK4-NEXT: store i32 [[ADD2]], i32* [[TMP17]], align 4
	// CHECK4-NEXT: [[TMP28:%.]] = load i32, i32 [[TMP23]], align 4			// CHECK4-NEXT: [[TMP28:%.]] = load i32, i32 [[TMP23]], align 4
	// CHECK4-NEXT: [[TMP29:%.]] = load i32, i32 [[TMP20]], align 4			// CHECK4-NEXT: [[TMP29:%.]] = load i32, i32 [[TMP20]], align 4
	// CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]			// CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]
	// CHECK4-NEXT: store i32 [[ADD3]], i32* [[TMP23]], align 4			// CHECK4-NEXT: store i32 [[ADD3]], i32* [[TMP23]], align 4
	// CHECK4-NEXT: ret void			// CHECK4-NEXT: ret void
	//			//
	//
	No newline at end of file

clang/test/OpenMP/parallel_sections_codegen.cpp

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	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	// CHECK2: terminate.lpad:			// CHECK2: terminate.lpad:
	// CHECK2-NEXT: [[TMP10:%.]] = landingpad { i8, i32 }			// CHECK2-NEXT: [[TMP10:%.]] = landingpad { i8, i32 }
	// CHECK2-NEXT: catch i8* null			// CHECK2-NEXT: catch i8* null
	// CHECK2-NEXT: [[TMP11:%.]] = extractvalue { i8, i32 } [[TMP10]], 0			// CHECK2-NEXT: [[TMP11:%.]] = extractvalue { i8, i32 } [[TMP10]], 0
	// CHECK2-NEXT: call void @__clang_call_terminate(i8* [[TMP11]]) #[[ATTR7]]			// CHECK2-NEXT: call void @__clang_call_terminate(i8* [[TMP11]]) #[[ATTR7]]
	// CHECK2-NEXT: unreachable			// CHECK2-NEXT: unreachable
	//			//
	//
	No newline at end of file

clang/test/OpenMP/sections_lastprivate_codegen.cpp

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	// CHECK8-NEXT: [[BLOCK:%.]] = bitcast i8 [[DOTBLOCK_DESCRIPTOR]] to <{ i8, i32, i32, i8, %struct.__block_descriptor, i32, i32 }>			// CHECK8-NEXT: [[BLOCK:%.]] = bitcast i8 [[DOTBLOCK_DESCRIPTOR]] to <{ i8, i32, i32, i8, %struct.__block_descriptor, i32, i32 }>
	// CHECK8-NEXT: store <{ i8, i32, i32, i8, %struct.__block_descriptor, i32, i32 }> [[BLOCK]], <{ i8, i32, i32, i8, %struct.__block_descriptor, i32, i32 }>* [[BLOCK_ADDR]], align 8			// CHECK8-NEXT: store <{ i8, i32, i32, i8, %struct.__block_descriptor, i32, i32 }> [[BLOCK]], <{ i8, i32, i32, i8, %struct.__block_descriptor, i32, i32 }>* [[BLOCK_ADDR]], align 8
	// CHECK8-NEXT: [[BLOCK_CAPTURE_ADDR:%.]] = getelementptr inbounds <{ i8, i32, i32, i8, %struct.__block_descriptor, i32, i32 }>, <{ i8, i32, i32, i8, %struct.__block_descriptor, i32, i32 }> [[BLOCK]], i32 0, i32 5			// CHECK8-NEXT: [[BLOCK_CAPTURE_ADDR:%.]] = getelementptr inbounds <{ i8, i32, i32, i8, %struct.__block_descriptor, i32, i32 }>, <{ i8, i32, i32, i8, %struct.__block_descriptor, i32, i32 }> [[BLOCK]], i32 0, i32 5
	// CHECK8-NEXT: store i32 2, i32* [[BLOCK_CAPTURE_ADDR]], align 8			// CHECK8-NEXT: store i32 2, i32* [[BLOCK_CAPTURE_ADDR]], align 8
	// CHECK8-NEXT: [[BLOCK_CAPTURE_ADDR1:%.]] = getelementptr inbounds <{ i8, i32, i32, i8, %struct.__block_descriptor, i32, i32 }>, <{ i8, i32, i32, i8, %struct.__block_descriptor, i32, i32 }> [[BLOCK]], i32 0, i32 6			// CHECK8-NEXT: [[BLOCK_CAPTURE_ADDR1:%.]] = getelementptr inbounds <{ i8, i32, i32, i8, %struct.__block_descriptor, i32, i32 }>, <{ i8, i32, i32, i8, %struct.__block_descriptor, i32, i32 }> [[BLOCK]], i32 0, i32 6
	// CHECK8-NEXT: store i32 29, i32* [[BLOCK_CAPTURE_ADDR1]], align 4			// CHECK8-NEXT: store i32 29, i32* [[BLOCK_CAPTURE_ADDR1]], align 4
	// CHECK8-NEXT: ret void			// CHECK8-NEXT: ret void
	//			//
	//
	No newline at end of file

clang/test/OpenMP/sections_private_codegen.cpp

	Show First 20 Lines • Show All 1,069 Lines • ▼ Show 20 Lines
	// CHECK4-NEXT: [[BLOCK:%.]] = bitcast i8 [[DOTBLOCK_DESCRIPTOR]] to <{ i8, i32, i32, i8, %struct.__block_descriptor, double, i32 }>			// CHECK4-NEXT: [[BLOCK:%.]] = bitcast i8 [[DOTBLOCK_DESCRIPTOR]] to <{ i8, i32, i32, i8, %struct.__block_descriptor, double, i32 }>
	// CHECK4-NEXT: store <{ i8, i32, i32, i8, %struct.__block_descriptor, double, i32 }> [[BLOCK]], <{ i8, i32, i32, i8, %struct.__block_descriptor, double, i32 }>* [[BLOCK_ADDR]], align 8			// CHECK4-NEXT: store <{ i8, i32, i32, i8, %struct.__block_descriptor, double, i32 }> [[BLOCK]], <{ i8, i32, i32, i8, %struct.__block_descriptor, double, i32 }>* [[BLOCK_ADDR]], align 8
	// CHECK4-NEXT: [[BLOCK_CAPTURE_ADDR:%.]] = getelementptr inbounds <{ i8, i32, i32, i8, %struct.__block_descriptor, double, i32 }>, <{ i8, i32, i32, i8, %struct.__block_descriptor, double, i32 }> [[BLOCK]], i32 0, i32 5			// CHECK4-NEXT: [[BLOCK_CAPTURE_ADDR:%.]] = getelementptr inbounds <{ i8, i32, i32, i8, %struct.__block_descriptor, double, i32 }>, <{ i8, i32, i32, i8, %struct.__block_descriptor, double, i32 }> [[BLOCK]], i32 0, i32 5
	// CHECK4-NEXT: store double 2.000000e+00, double* [[BLOCK_CAPTURE_ADDR]], align 8			// CHECK4-NEXT: store double 2.000000e+00, double* [[BLOCK_CAPTURE_ADDR]], align 8
	// CHECK4-NEXT: [[BLOCK_CAPTURE_ADDR1:%.]] = getelementptr inbounds <{ i8, i32, i32, i8, %struct.__block_descriptor, double, i32 }>, <{ i8, i32, i32, i8, %struct.__block_descriptor, double, i32 }> [[BLOCK]], i32 0, i32 6			// CHECK4-NEXT: [[BLOCK_CAPTURE_ADDR1:%.]] = getelementptr inbounds <{ i8, i32, i32, i8, %struct.__block_descriptor, double, i32 }>, <{ i8, i32, i32, i8, %struct.__block_descriptor, double, i32 }> [[BLOCK]], i32 0, i32 6
	// CHECK4-NEXT: store i32 222, i32* [[BLOCK_CAPTURE_ADDR1]], align 8			// CHECK4-NEXT: store i32 222, i32* [[BLOCK_CAPTURE_ADDR1]], align 8
	// CHECK4-NEXT: ret void			// CHECK4-NEXT: ret void
	//			//
	//
	No newline at end of file

clang/test/OpenMP/sections_reduction_codegen.cpp

	Show First 20 Lines • Show All 2,153 Lines • ▼ Show 20 Lines
	// CHECK4-NEXT: [[TMP10:%.]] = load i8, i8** [[TMP9]], align 8			// CHECK4-NEXT: [[TMP10:%.]] = load i8, i8** [[TMP9]], align 8
	// CHECK4-NEXT: [[TMP11:%.]] = bitcast i8 [[TMP10]] to double*			// CHECK4-NEXT: [[TMP11:%.]] = bitcast i8 [[TMP10]] to double*
	// CHECK4-NEXT: [[TMP12:%.]] = load double, double [[TMP11]], align 8			// CHECK4-NEXT: [[TMP12:%.]] = load double, double [[TMP11]], align 8
	// CHECK4-NEXT: [[TMP13:%.]] = load double, double [[TMP8]], align 8			// CHECK4-NEXT: [[TMP13:%.]] = load double, double [[TMP8]], align 8
	// CHECK4-NEXT: [[ADD:%.*]] = fadd double [[TMP12]], [[TMP13]]			// CHECK4-NEXT: [[ADD:%.*]] = fadd double [[TMP12]], [[TMP13]]
	// CHECK4-NEXT: store double [[ADD]], double* [[TMP11]], align 8			// CHECK4-NEXT: store double [[ADD]], double* [[TMP11]], align 8
	// CHECK4-NEXT: ret void			// CHECK4-NEXT: ret void
	//			//
	//
	No newline at end of file

clang/test/OpenMP/single_private_codegen.cpp

	Show First 20 Lines • Show All 842 Lines • ▼ Show 20 Lines
	// CHECK4-NEXT: [[BLOCK:%.]] = bitcast i8 [[DOTBLOCK_DESCRIPTOR]] to <{ i8, i32, i32, i8, %struct.__block_descriptor, double, i32 }>			// CHECK4-NEXT: [[BLOCK:%.]] = bitcast i8 [[DOTBLOCK_DESCRIPTOR]] to <{ i8, i32, i32, i8, %struct.__block_descriptor, double, i32 }>
	// CHECK4-NEXT: store <{ i8, i32, i32, i8, %struct.__block_descriptor, double, i32 }> [[BLOCK]], <{ i8, i32, i32, i8, %struct.__block_descriptor, double, i32 }>* [[BLOCK_ADDR]], align 8			// CHECK4-NEXT: store <{ i8, i32, i32, i8, %struct.__block_descriptor, double, i32 }> [[BLOCK]], <{ i8, i32, i32, i8, %struct.__block_descriptor, double, i32 }>* [[BLOCK_ADDR]], align 8
	// CHECK4-NEXT: [[BLOCK_CAPTURE_ADDR:%.]] = getelementptr inbounds <{ i8, i32, i32, i8, %struct.__block_descriptor, double, i32 }>, <{ i8, i32, i32, i8, %struct.__block_descriptor, double, i32 }> [[BLOCK]], i32 0, i32 5			// CHECK4-NEXT: [[BLOCK_CAPTURE_ADDR:%.]] = getelementptr inbounds <{ i8, i32, i32, i8, %struct.__block_descriptor, double, i32 }>, <{ i8, i32, i32, i8, %struct.__block_descriptor, double, i32 }> [[BLOCK]], i32 0, i32 5
	// CHECK4-NEXT: store double 2.000000e+00, double* [[BLOCK_CAPTURE_ADDR]], align 8			// CHECK4-NEXT: store double 2.000000e+00, double* [[BLOCK_CAPTURE_ADDR]], align 8
	// CHECK4-NEXT: [[BLOCK_CAPTURE_ADDR1:%.]] = getelementptr inbounds <{ i8, i32, i32, i8, %struct.__block_descriptor, double, i32 }>, <{ i8, i32, i32, i8, %struct.__block_descriptor, double, i32 }> [[BLOCK]], i32 0, i32 6			// CHECK4-NEXT: [[BLOCK_CAPTURE_ADDR1:%.]] = getelementptr inbounds <{ i8, i32, i32, i8, %struct.__block_descriptor, double, i32 }>, <{ i8, i32, i32, i8, %struct.__block_descriptor, double, i32 }> [[BLOCK]], i32 0, i32 6
	// CHECK4-NEXT: store i32 203, i32* [[BLOCK_CAPTURE_ADDR1]], align 8			// CHECK4-NEXT: store i32 203, i32* [[BLOCK_CAPTURE_ADDR1]], align 8
	// CHECK4-NEXT: ret void			// CHECK4-NEXT: ret void
	//			//
	//
	No newline at end of file

clang/test/OpenMP/target_data_map_codegen_hold.cpp

Show First 20 Lines • Show All 48 Lines • ▼ Show 20 Lines
// PTR_AND_OBJ = 0x10		// PTR_AND_OBJ = 0x10
// CLOSE = 0x400		// CLOSE = 0x400
// OMPX_HOLD = 0x2000		// OMPX_HOLD = 0x2000
// MEMBER_OF_1 = 0x1000000000000		// MEMBER_OF_1 = 0x1000000000000
// MEMBER_OF_7 = 0x7000000000000		// MEMBER_OF_7 = 0x7000000000000

//.		//.
// CHECK-PPC64LE: @.offload_sizes = private unnamed_addr constant [1 x i64] [i64 20]		// CHECK-PPC64LE: @.offload_sizes = private unnamed_addr constant [1 x i64] [i64 20]
// CHECK-PPC64LE: @.offload_maptypes = private unnamed_addr constant [1 x i64] [i64 [[#0x2001]]]		// CHECK-PPC64LE: @.offload_maptypes = private unnamed_addr constant [1 x i64] [i64 8193]
		// CHECK-PPC64LE: @0 = private unnamed_addr constant [23 x i8] c"
		// CHECK-PPC64LE: @1 = private unnamed_addr constant %struct.ident_t { i32 0, i32 2, i32 0, i32 22, i8* getelementptr inbounds ([23 x i8], [23 x i8]* @0, i32 0, i32 0) }, align 8
// CHECK-PPC64LE: @.offload_sizes.1 = private unnamed_addr constant [1 x i64] [i64 20]		// CHECK-PPC64LE: @.offload_sizes.1 = private unnamed_addr constant [1 x i64] [i64 20]
// CHECK-PPC64LE: @.offload_maptypes.2 = private unnamed_addr constant [1 x i64] [i64 [[#0x2405]]]		// CHECK-PPC64LE: @.offload_maptypes.2 = private unnamed_addr constant [1 x i64] [i64 9221]
// CHECK-PPC64LE: @.offload_sizes.3 = private unnamed_addr constant [1 x i64] [i64 4]		// CHECK-PPC64LE: @.offload_sizes.3 = private unnamed_addr constant [1 x i64] [i64 4]
// CHECK-PPC64LE: @.offload_maptypes.4 = private unnamed_addr constant [1 x i64] [i64 [[#0x2003]]]		// CHECK-PPC64LE: @.offload_maptypes.4 = private unnamed_addr constant [1 x i64] [i64 8195]
// CHECK-PPC64LE: @.offload_maptypes.5 = private unnamed_addr constant [11 x i64] [i64 [[#0x2000]], i64 [[#0x1000000002003]], i64 [[#0x1000000002010]], i64 [[#0x2010]], i64 [[#0x2013]], i64 [[#0x3]], i64 [[#0x2000]], i64 [[#0x7000000002003]], i64 [[#0x7000000002010]], i64 [[#0x2010]], i64 [[#0x2013]]]		// CHECK-PPC64LE: @.offload_maptypes.5 = private unnamed_addr constant [11 x i64] [i64 8192, i64 281474976718851, i64 281474976718864, i64 8208, i64 8211, i64 3, i64 8192, i64 1970324836982787, i64 1970324836982800, i64 8208, i64 8211]
//.		//.
// CHECK-I386: @.offload_sizes = private unnamed_addr constant [1 x i64] [i64 20]		// CHECK-I386: @.offload_sizes = private unnamed_addr constant [1 x i64] [i64 20]
// CHECK-I386: @.offload_maptypes = private unnamed_addr constant [1 x i64] [i64 [[#0x2001]]]		// CHECK-I386: @.offload_maptypes = private unnamed_addr constant [1 x i64] [i64 8193]
		// CHECK-I386: @0 = private unnamed_addr constant [23 x i8] c"
		// CHECK-I386: @1 = private unnamed_addr constant %struct.ident_t { i32 0, i32 2, i32 0, i32 22, i8* getelementptr inbounds ([23 x i8], [23 x i8]* @0, i32 0, i32 0) }, align 8
// CHECK-I386: @.offload_sizes.1 = private unnamed_addr constant [1 x i64] [i64 20]		// CHECK-I386: @.offload_sizes.1 = private unnamed_addr constant [1 x i64] [i64 20]
// CHECK-I386: @.offload_maptypes.2 = private unnamed_addr constant [1 x i64] [i64 [[#0x2405]]]		// CHECK-I386: @.offload_maptypes.2 = private unnamed_addr constant [1 x i64] [i64 9221]
// CHECK-I386: @.offload_sizes.3 = private unnamed_addr constant [1 x i64] [i64 4]		// CHECK-I386: @.offload_sizes.3 = private unnamed_addr constant [1 x i64] [i64 4]
// CHECK-I386: @.offload_maptypes.4 = private unnamed_addr constant [1 x i64] [i64 [[#0x2003]]]		// CHECK-I386: @.offload_maptypes.4 = private unnamed_addr constant [1 x i64] [i64 8195]
// CHECK-I386: @.offload_maptypes.5 = private unnamed_addr constant [11 x i64] [i64 [[#0x2000]], i64 [[#0x1000000002003]], i64 [[#0x1000000002010]], i64 [[#0x2010]], i64 [[#0x2013]], i64 [[#0x3]], i64 [[#0x2000]], i64 [[#0x7000000002003]], i64 [[#0x7000000002010]], i64 [[#0x2010]], i64 [[#0x2013]]]		// CHECK-I386: @.offload_maptypes.5 = private unnamed_addr constant [11 x i64] [i64 8192, i64 281474976718851, i64 281474976718864, i64 8208, i64 8211, i64 3, i64 8192, i64 1970324836982787, i64 1970324836982800, i64 8208, i64 8211]
//.		//.
// CHECK-PPC64LE-LABEL: @_Z3fooi(		// CHECK-PPC64LE-LABEL: @_Z3fooi(
// CHECK-PPC64LE-NEXT: entry:		// CHECK-PPC64LE-NEXT: entry:
// CHECK-PPC64LE-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4		// CHECK-PPC64LE-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4
// CHECK-PPC64LE-NEXT: [[LB:%.*]] = alloca [5 x float], align 4		// CHECK-PPC64LE-NEXT: [[LB:%.*]] = alloca [5 x float], align 4
// CHECK-PPC64LE-NEXT: [[PS1:%.]] = alloca %struct.S2, align 8		// CHECK-PPC64LE-NEXT: [[PS1:%.]] = alloca %struct.S2, align 8
// CHECK-PPC64LE-NEXT: [[PS2:%.]] = alloca %struct.S2, align 8		// CHECK-PPC64LE-NEXT: [[PS2:%.]] = alloca %struct.S2, align 8
// CHECK-PPC64LE-NEXT: [[DOTOFFLOAD_BASEPTRS:%.]] = alloca [1 x i8], align 8		// CHECK-PPC64LE-NEXT: [[DOTOFFLOAD_BASEPTRS:%.]] = alloca [1 x i8], align 8
▲ Show 20 Lines • Show All 522 Lines • ▼ Show 20 Lines	#pragma omp target data map(tofrom : ps1->s, arg) \
map(ompx_hold, tofrom : ps1->ps->ps->ps->s, ps2->s) \		map(ompx_hold, tofrom : ps1->ps->ps->ps->s, ps2->s) \
map(tofrom : ps2->ps->ps->ps->s)		map(tofrom : ps2->ps->ps->ps->s)
{		{
++(arg);		++(arg);
}		}
}		}

#endif		#endif
		//.
		// CHECK-PPC64LE: attributes #0 = { mustprogress noinline nounwind optnone "frame-pointer"="none" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="-altivec,-bpermd,-crypto,-direct-move,-extdiv,-htm,-isa-v206-instructions,-isa-v207-instructions,-isa-v30-instructions,-power8-vector,-power9-vector,-privileged,-rop-protect,-spe,-vsx" }
		// CHECK-PPC64LE: attributes #1 = { nounwind }
		//.
		// CHECK-I386: attributes #0 = { mustprogress noinline nounwind optnone "frame-pointer"="none" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+x87" }
		// CHECK-I386: attributes #1 = { nounwind }
		//.
		// CHECK-PPC64LE: !0 = !{i32 1, !"wchar_size", i32 4}
		// CHECK-PPC64LE: !1 = !{i32 7, !"openmp", i32 50}
		// CHECK-PPC64LE: !2 = !{!"clang version 14.0.0"}
		//.
		// CHECK-I386: !0 = !{i32 1, !"NumRegisterParameters", i32 0}
		// CHECK-I386: !1 = !{i32 1, !"wchar_size", i32 4}
		// CHECK-I386: !2 = !{i32 7, !"openmp", i32 50}
		// CHECK-I386: !3 = !{!"clang version 14.0.0"}
		//.

clang/test/OpenMP/target_globals_codegen.cpp

	Show All 9 Lines

	#ifndef HEADER			#ifndef HEADER
	#define HEADER			#define HEADER

	//.			//.
	// CHECK: @__omp_rtl_debug_kind = weak_odr constant i32 1			// CHECK: @__omp_rtl_debug_kind = weak_odr constant i32 1
	// CHECK: @__omp_rtl_assume_teams_oversubscription = weak_odr constant i32 0			// CHECK: @__omp_rtl_assume_teams_oversubscription = weak_odr constant i32 0
	// CHECK: @__omp_rtl_assume_threads_oversubscription = weak_odr constant i32 0			// CHECK: @__omp_rtl_assume_threads_oversubscription = weak_odr constant i32 0
				// CHECK: @0 = private unnamed_addr constant [23 x i8] c"
				// CHECK: @1 = private unnamed_addr constant %struct.ident_t { i32 0, i32 2, i32 0, i32 22, i8* getelementptr inbounds ([23 x i8], [23 x i8]* @0, i32 0, i32 0) }, align 8
				// CHECK: @__omp_offloading_2b_1007f3d__Z3foov_l61_kernel_info = global %"struct._OMP::KernelEnvironmentTy" { %struct.ident_t { i32 0, i32 2, i32 0, i32 22, i8* getelementptr inbounds ([23 x i8], [23 x i8]* @0, i32 0, i32 0) }, %"struct._OMP::ConfigurationEnvironmentTy" { i8 1, i8 1 }, i16 0 }
				// CHECK: @__omp_offloading_2b_1007f3d__Z3foov_l61_exec_mode = weak constant i8 1
				// CHECK: @llvm.compiler.used = appending global [1 x i8] [i8 @__omp_offloading_2b_1007f3d__Z3foov_l61_exec_mode], section "llvm.metadata"
	//.			//.
	// CHECK-EQ: @__omp_rtl_debug_kind = weak_odr constant i32 111			// CHECK-EQ: @__omp_rtl_debug_kind = weak_odr constant i32 111
	// CHECK-EQ: @__omp_rtl_assume_teams_oversubscription = weak_odr constant i32 0			// CHECK-EQ: @__omp_rtl_assume_teams_oversubscription = weak_odr constant i32 0
	// CHECK-EQ: @__omp_rtl_assume_threads_oversubscription = weak_odr constant i32 0			// CHECK-EQ: @__omp_rtl_assume_threads_oversubscription = weak_odr constant i32 0
				// CHECK-EQ: @0 = private unnamed_addr constant [23 x i8] c"
				// CHECK-EQ: @1 = private unnamed_addr constant %struct.ident_t { i32 0, i32 2, i32 0, i32 22, i8* getelementptr inbounds ([23 x i8], [23 x i8]* @0, i32 0, i32 0) }, align 8
				// CHECK-EQ: @__omp_offloading_2b_1007f3d__Z3foov_l61_kernel_info = global %"struct._OMP::KernelEnvironmentTy" { %struct.ident_t { i32 0, i32 2, i32 0, i32 22, i8* getelementptr inbounds ([23 x i8], [23 x i8]* @0, i32 0, i32 0) }, %"struct._OMP::ConfigurationEnvironmentTy" { i8 1, i8 1 }, i16 0 }
				// CHECK-EQ: @__omp_offloading_2b_1007f3d__Z3foov_l61_exec_mode = weak constant i8 1
				// CHECK-EQ: @llvm.compiler.used = appending global [1 x i8] [i8 @__omp_offloading_2b_1007f3d__Z3foov_l61_exec_mode], section "llvm.metadata"
	//.			//.
	// CHECK-DEFAULT: @__omp_rtl_debug_kind = weak_odr constant i32 0			// CHECK-DEFAULT: @__omp_rtl_debug_kind = weak_odr constant i32 0
	// CHECK-DEFAULT: @__omp_rtl_assume_teams_oversubscription = weak_odr constant i32 0			// CHECK-DEFAULT: @__omp_rtl_assume_teams_oversubscription = weak_odr constant i32 0
	// CHECK-DEFAULT: @__omp_rtl_assume_threads_oversubscription = weak_odr constant i32 0			// CHECK-DEFAULT: @__omp_rtl_assume_threads_oversubscription = weak_odr constant i32 0
				// CHECK-DEFAULT: @0 = private unnamed_addr constant [23 x i8] c"
				// CHECK-DEFAULT: @1 = private unnamed_addr constant %struct.ident_t { i32 0, i32 2, i32 0, i32 22, i8* getelementptr inbounds ([23 x i8], [23 x i8]* @0, i32 0, i32 0) }, align 8
				// CHECK-DEFAULT: @__omp_offloading_2b_1007f3d__Z3foov_l61_kernel_info = global %"struct._OMP::KernelEnvironmentTy" { %struct.ident_t { i32 0, i32 2, i32 0, i32 22, i8* getelementptr inbounds ([23 x i8], [23 x i8]* @0, i32 0, i32 0) }, %"struct._OMP::ConfigurationEnvironmentTy" { i8 1, i8 1 }, i16 0 }
				// CHECK-DEFAULT: @__omp_offloading_2b_1007f3d__Z3foov_l61_exec_mode = weak constant i8 1
				// CHECK-DEFAULT: @llvm.compiler.used = appending global [1 x i8] [i8 @__omp_offloading_2b_1007f3d__Z3foov_l61_exec_mode], section "llvm.metadata"
	//.			//.
	// CHECK-THREADS: @__omp_rtl_debug_kind = weak_odr constant i32 0			// CHECK-THREADS: @__omp_rtl_debug_kind = weak_odr constant i32 0
	// CHECK-THREADS: @__omp_rtl_assume_teams_oversubscription = weak_odr constant i32 0			// CHECK-THREADS: @__omp_rtl_assume_teams_oversubscription = weak_odr constant i32 0
	// CHECK-THREADS: @__omp_rtl_assume_threads_oversubscription = weak_odr constant i32 1			// CHECK-THREADS: @__omp_rtl_assume_threads_oversubscription = weak_odr constant i32 1
				// CHECK-THREADS: @0 = private unnamed_addr constant [23 x i8] c"
				// CHECK-THREADS: @1 = private unnamed_addr constant %struct.ident_t { i32 0, i32 2, i32 0, i32 22, i8* getelementptr inbounds ([23 x i8], [23 x i8]* @0, i32 0, i32 0) }, align 8
				// CHECK-THREADS: @__omp_offloading_2b_1007f3d__Z3foov_l61_kernel_info = global %"struct._OMP::KernelEnvironmentTy" { %struct.ident_t { i32 0, i32 2, i32 0, i32 22, i8* getelementptr inbounds ([23 x i8], [23 x i8]* @0, i32 0, i32 0) }, %"struct._OMP::ConfigurationEnvironmentTy" { i8 1, i8 1 }, i16 0 }
				// CHECK-THREADS: @__omp_offloading_2b_1007f3d__Z3foov_l61_exec_mode = weak constant i8 1
				// CHECK-THREADS: @llvm.compiler.used = appending global [1 x i8] [i8 @__omp_offloading_2b_1007f3d__Z3foov_l61_exec_mode], section "llvm.metadata"
	//.			//.
	// CHECK-TEAMS: @__omp_rtl_debug_kind = weak_odr constant i32 0			// CHECK-TEAMS: @__omp_rtl_debug_kind = weak_odr constant i32 0
	// CHECK-TEAMS: @__omp_rtl_assume_teams_oversubscription = weak_odr constant i32 1			// CHECK-TEAMS: @__omp_rtl_assume_teams_oversubscription = weak_odr constant i32 1
	// CHECK-TEAMS: @__omp_rtl_assume_threads_oversubscription = weak_odr constant i32 0			// CHECK-TEAMS: @__omp_rtl_assume_threads_oversubscription = weak_odr constant i32 0
				// CHECK-TEAMS: @0 = private unnamed_addr constant [23 x i8] c"
				// CHECK-TEAMS: @1 = private unnamed_addr constant %struct.ident_t { i32 0, i32 2, i32 0, i32 22, i8* getelementptr inbounds ([23 x i8], [23 x i8]* @0, i32 0, i32 0) }, align 8
				// CHECK-TEAMS: @__omp_offloading_2b_1007f3d__Z3foov_l61_kernel_info = global %"struct._OMP::KernelEnvironmentTy" { %struct.ident_t { i32 0, i32 2, i32 0, i32 22, i8* getelementptr inbounds ([23 x i8], [23 x i8]* @0, i32 0, i32 0) }, %"struct._OMP::ConfigurationEnvironmentTy" { i8 1, i8 1 }, i16 0 }
				// CHECK-TEAMS: @__omp_offloading_2b_1007f3d__Z3foov_l61_exec_mode = weak constant i8 1
				// CHECK-TEAMS: @llvm.compiler.used = appending global [1 x i8] [i8 @__omp_offloading_2b_1007f3d__Z3foov_l61_exec_mode], section "llvm.metadata"
	//.			//.
	void foo() {			void foo() {
	#pragma omp target			#pragma omp target
	{ }			{ }
	}			}

	#endif			#endif
				//.
				// CHECK: attributes #0 = { convergent noinline norecurse nounwind optnone "frame-pointer"="none" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+ptx32,+sm_20" }
				//.
				// CHECK-EQ: attributes #0 = { convergent noinline norecurse nounwind optnone "frame-pointer"="none" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+ptx32,+sm_20" }
				//.
				// CHECK-DEFAULT: attributes #0 = { convergent noinline norecurse nounwind optnone "frame-pointer"="none" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+ptx32,+sm_20" }
				//.
				// CHECK-THREADS: attributes #0 = { convergent noinline norecurse nounwind optnone "frame-pointer"="none" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+ptx32,+sm_20" }
				//.
				// CHECK-TEAMS: attributes #0 = { convergent noinline norecurse nounwind optnone "frame-pointer"="none" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+ptx32,+sm_20" }
				//.
				// CHECK: !0 = !{i32 0, i32 43, i32 16809789, !"_Z3foov", i32 61, i32 0}
				// CHECK: !1 = !{void ()* @__omp_offloading_2b_1007f3d__Z3foov_l61, !"kernel", i32 1}
				// CHECK: !2 = !{i32 1, !"wchar_size", i32 4}
				// CHECK: !3 = !{i32 7, !"openmp", i32 50}
				// CHECK: !4 = !{i32 7, !"openmp-device", i32 50}
				// CHECK: !5 = !{!"clang version 14.0.0"}
				//.
				// CHECK-EQ: !0 = !{i32 0, i32 43, i32 16809789, !"_Z3foov", i32 61, i32 0}
				// CHECK-EQ: !1 = !{void ()* @__omp_offloading_2b_1007f3d__Z3foov_l61, !"kernel", i32 1}
				// CHECK-EQ: !2 = !{i32 1, !"wchar_size", i32 4}
				// CHECK-EQ: !3 = !{i32 7, !"openmp", i32 50}
				// CHECK-EQ: !4 = !{i32 7, !"openmp-device", i32 50}
				// CHECK-EQ: !5 = !{!"clang version 14.0.0"}
				//.
				// CHECK-DEFAULT: !0 = !{i32 0, i32 43, i32 16809789, !"_Z3foov", i32 61, i32 0}
				// CHECK-DEFAULT: !1 = !{void ()* @__omp_offloading_2b_1007f3d__Z3foov_l61, !"kernel", i32 1}
				// CHECK-DEFAULT: !2 = !{i32 1, !"wchar_size", i32 4}
				// CHECK-DEFAULT: !3 = !{i32 7, !"openmp", i32 50}
				// CHECK-DEFAULT: !4 = !{i32 7, !"openmp-device", i32 50}
				// CHECK-DEFAULT: !5 = !{!"clang version 14.0.0"}
				//.
				// CHECK-THREADS: !0 = !{i32 0, i32 43, i32 16809789, !"_Z3foov", i32 61, i32 0}
				// CHECK-THREADS: !1 = !{void ()* @__omp_offloading_2b_1007f3d__Z3foov_l61, !"kernel", i32 1}
				// CHECK-THREADS: !2 = !{i32 1, !"wchar_size", i32 4}
				// CHECK-THREADS: !3 = !{i32 7, !"openmp", i32 50}
				// CHECK-THREADS: !4 = !{i32 7, !"openmp-device", i32 50}
				// CHECK-THREADS: !5 = !{!"clang version 14.0.0"}
				//.
				// CHECK-TEAMS: !0 = !{i32 0, i32 43, i32 16809789, !"_Z3foov", i32 61, i32 0}
				// CHECK-TEAMS: !1 = !{void ()* @__omp_offloading_2b_1007f3d__Z3foov_l61, !"kernel", i32 1}
				// CHECK-TEAMS: !2 = !{i32 1, !"wchar_size", i32 4}
				// CHECK-TEAMS: !3 = !{i32 7, !"openmp", i32 50}
				// CHECK-TEAMS: !4 = !{i32 7, !"openmp-device", i32 50}
				// CHECK-TEAMS: !5 = !{!"clang version 14.0.0"}
				//.

clang/test/OpenMP/target_map_codegen_hold.cpp

	Show First 20 Lines • Show All 77 Lines • ▼ Show 20 Lines
	// ALWAYS = 0x4			// ALWAYS = 0x4
	// TARGET_PARAM = 0x20			// TARGET_PARAM = 0x20
	// CLOSE = 0x400			// CLOSE = 0x400
	// OMPX_HOLD = 0x2000			// OMPX_HOLD = 0x2000
	// MEMBER_OF_1 = 0x1000000000000			// MEMBER_OF_1 = 0x1000000000000
	// MEMBER_OF_5 = 0x5000000000000			// MEMBER_OF_5 = 0x5000000000000

	//.			//.
	// CHECK-USE-PPC64LE: @.offload_maptypes = private unnamed_addr constant [7 x i64] [i64 [[#0x2020]], i64 [[#0x1000000002003]], i64 [[#0x1000000002003]], i64 [[#0x2023]], i64 [[#0x2020]], i64 [[#0x5000000002003]], i64 [[#0x5000000002003]]]			// CHECK-USE-PPC64LE: @.__omp_offloading_2b_ff075e__Z20explicit_maps_singlei_l702.region_id = weak constant i8 0
				// CHECK-USE-PPC64LE: @.offload_maptypes = private unnamed_addr constant [7 x i64] [i64 8224, i64 281474976718851, i64 281474976718851, i64 8227, i64 8224, i64 1407374883561475, i64 1407374883561475]
				// CHECK-USE-PPC64LE: @0 = private unnamed_addr constant [23 x i8] c"
				// CHECK-USE-PPC64LE: @1 = private unnamed_addr constant %struct.ident_t { i32 0, i32 2, i32 0, i32 22, i8* getelementptr inbounds ([23 x i8], [23 x i8]* @0, i32 0, i32 0) }, align 8
				// CHECK-USE-PPC64LE: @.__omp_offloading_2b_ff075e__Z20explicit_maps_singlei_l716.region_id = weak constant i8 0
	// CHECK-USE-PPC64LE: @.offload_sizes = private unnamed_addr constant [1 x i64] [i64 4]			// CHECK-USE-PPC64LE: @.offload_sizes = private unnamed_addr constant [1 x i64] [i64 4]
	// CHECK-USE-PPC64LE: @.offload_maptypes.1 = private unnamed_addr constant [1 x i64] [i64 [[#0x2427]]]			// CHECK-USE-PPC64LE: @.offload_maptypes.1 = private unnamed_addr constant [1 x i64] [i64 9255]
	// CHECK-USE-PPC64LE: @.offload_maptypes.2 = private unnamed_addr constant [3 x i64] [i64 [[#0x2020]], i64 [[#0x1000000002003]], i64 [[#0x1000000002003]]]			// CHECK-USE-PPC64LE: @.__omp_offloading_2b_ff075e__ZN2ST20test_present_membersEv_l967.region_id = weak constant i8 0
				// CHECK-USE-PPC64LE: @.offload_maptypes.2 = private unnamed_addr constant [3 x i64] [i64 8224, i64 281474976718851, i64 281474976718851]
				// CHECK-USE-PPC64LE: @.omp_offloading.entry_name = internal unnamed_addr constant [58 x i8] c"__omp_offloading_2b_ff075e__Z20explicit_maps_singlei_l702\00"
				// CHECK-USE-PPC64LE: @.omp_offloading.entry.__omp_offloading_2b_ff075e__Z20explicit_maps_singlei_l702 = weak constant %struct.__tgt_offload_entry { i8* @.__omp_offloading_2b_ff075e__Z20explicit_maps_singlei_l702.region_id, i8* getelementptr inbounds ([58 x i8], [58 x i8]* @.omp_offloading.entry_name, i32 0, i32 0), i64 0, i32 0, i32 0 }, section "omp_offloading_entries", align 1
				// CHECK-USE-PPC64LE: @.omp_offloading.entry_name.3 = internal unnamed_addr constant [58 x i8] c"__omp_offloading_2b_ff075e__Z20explicit_maps_singlei_l716\00"
				// CHECK-USE-PPC64LE: @.omp_offloading.entry.__omp_offloading_2b_ff075e__Z20explicit_maps_singlei_l716 = weak constant %struct.__tgt_offload_entry { i8* @.__omp_offloading_2b_ff075e__Z20explicit_maps_singlei_l716.region_id, i8* getelementptr inbounds ([58 x i8], [58 x i8]* @.omp_offloading.entry_name.3, i32 0, i32 0), i64 0, i32 0, i32 0 }, section "omp_offloading_entries", align 1
				// CHECK-USE-PPC64LE: @.omp_offloading.entry_name.4 = internal unnamed_addr constant [63 x i8] c"__omp_offloading_2b_ff075e__ZN2ST20test_present_membersEv_l967\00"
				// CHECK-USE-PPC64LE: @.omp_offloading.entry.__omp_offloading_2b_ff075e__ZN2ST20test_present_membersEv_l967 = weak constant %struct.__tgt_offload_entry { i8* @.__omp_offloading_2b_ff075e__ZN2ST20test_present_membersEv_l967.region_id, i8* getelementptr inbounds ([63 x i8], [63 x i8]* @.omp_offloading.entry_name.4, i32 0, i32 0), i64 0, i32 0, i32 0 }, section "omp_offloading_entries", align 1
				// CHECK-USE-PPC64LE: @llvm.global_ctors = appending global [1 x { i32, void (), i8 }] [{ i32, void (), i8 } { i32 0, void ()* @.omp_offloading.requires_reg, i8* null }]
	//.			//.
	// CHECK-USE-I386: @.offload_maptypes = private unnamed_addr constant [7 x i64] [i64 [[#0x2020]], i64 [[#0x1000000002003]], i64 [[#0x1000000002003]], i64 [[#0x2023]], i64 [[#0x2020]], i64 [[#0x5000000002003]], i64 [[#0x5000000002003]]]			// CHECK-USE-I386: @.__omp_offloading_2b_ff075e__Z20explicit_maps_singlei_l702.region_id = weak constant i8 0
				// CHECK-USE-I386: @.offload_maptypes = private unnamed_addr constant [7 x i64] [i64 8224, i64 281474976718851, i64 281474976718851, i64 8227, i64 8224, i64 1407374883561475, i64 1407374883561475]
				// CHECK-USE-I386: @0 = private unnamed_addr constant [23 x i8] c"
				// CHECK-USE-I386: @1 = private unnamed_addr constant %struct.ident_t { i32 0, i32 2, i32 0, i32 22, i8* getelementptr inbounds ([23 x i8], [23 x i8]* @0, i32 0, i32 0) }, align 8
				// CHECK-USE-I386: @.__omp_offloading_2b_ff075e__Z20explicit_maps_singlei_l716.region_id = weak constant i8 0
	// CHECK-USE-I386: @.offload_sizes = private unnamed_addr constant [1 x i64] [i64 4]			// CHECK-USE-I386: @.offload_sizes = private unnamed_addr constant [1 x i64] [i64 4]
	// CHECK-USE-I386: @.offload_maptypes.1 = private unnamed_addr constant [1 x i64] [i64 [[#0x2427]]]			// CHECK-USE-I386: @.offload_maptypes.1 = private unnamed_addr constant [1 x i64] [i64 9255]
	// CHECK-USE-I386: @.offload_maptypes.2 = private unnamed_addr constant [3 x i64] [i64 [[#0x2020]], i64 [[#0x1000000002003]], i64 [[#0x1000000002003]]]			// CHECK-USE-I386: @.__omp_offloading_2b_ff075e__ZN2ST20test_present_membersEv_l967.region_id = weak constant i8 0
				// CHECK-USE-I386: @.offload_maptypes.2 = private unnamed_addr constant [3 x i64] [i64 8224, i64 281474976718851, i64 281474976718851]
				// CHECK-USE-I386: @.omp_offloading.entry_name = internal unnamed_addr constant [58 x i8] c"__omp_offloading_2b_ff075e__Z20explicit_maps_singlei_l702\00"
				// CHECK-USE-I386: @.omp_offloading.entry.__omp_offloading_2b_ff075e__Z20explicit_maps_singlei_l702 = weak constant %struct.__tgt_offload_entry { i8* @.__omp_offloading_2b_ff075e__Z20explicit_maps_singlei_l702.region_id, i8* getelementptr inbounds ([58 x i8], [58 x i8]* @.omp_offloading.entry_name, i32 0, i32 0), i32 0, i32 0, i32 0 }, section "omp_offloading_entries", align 1
				// CHECK-USE-I386: @.omp_offloading.entry_name.3 = internal unnamed_addr constant [58 x i8] c"__omp_offloading_2b_ff075e__Z20explicit_maps_singlei_l716\00"
				// CHECK-USE-I386: @.omp_offloading.entry.__omp_offloading_2b_ff075e__Z20explicit_maps_singlei_l716 = weak constant %struct.__tgt_offload_entry { i8* @.__omp_offloading_2b_ff075e__Z20explicit_maps_singlei_l716.region_id, i8* getelementptr inbounds ([58 x i8], [58 x i8]* @.omp_offloading.entry_name.3, i32 0, i32 0), i32 0, i32 0, i32 0 }, section "omp_offloading_entries", align 1
				// CHECK-USE-I386: @.omp_offloading.entry_name.4 = internal unnamed_addr constant [63 x i8] c"__omp_offloading_2b_ff075e__ZN2ST20test_present_membersEv_l967\00"
				// CHECK-USE-I386: @.omp_offloading.entry.__omp_offloading_2b_ff075e__ZN2ST20test_present_membersEv_l967 = weak constant %struct.__tgt_offload_entry { i8* @.__omp_offloading_2b_ff075e__ZN2ST20test_present_membersEv_l967.region_id, i8* getelementptr inbounds ([63 x i8], [63 x i8]* @.omp_offloading.entry_name.4, i32 0, i32 0), i32 0, i32 0, i32 0 }, section "omp_offloading_entries", align 1
				// CHECK-USE-I386: @llvm.global_ctors = appending global [1 x { i32, void (), i8 }] [{ i32, void (), i8 } { i32 0, void ()* @.omp_offloading.requires_reg, i8* null }]
	//.			//.
	// CHECK-NOUSE-PPC64LE: @.offload_maptypes = private unnamed_addr constant [7 x i64] [i64 [[#0x2000]], i64 [[#0x1000000002003]], i64 [[#0x1000000002003]], i64 [[#0x2003]], i64 [[#0x2000]], i64 [[#0x5000000002003]], i64 [[#0x5000000002003]]]			// CHECK-NOUSE-PPC64LE: @.__omp_offloading_2b_ff075e__Z20explicit_maps_singlei_l702.region_id = weak constant i8 0
				// CHECK-NOUSE-PPC64LE: @.offload_maptypes = private unnamed_addr constant [7 x i64] [i64 8192, i64 281474976718851, i64 281474976718851, i64 8195, i64 8192, i64 1407374883561475, i64 1407374883561475]
				// CHECK-NOUSE-PPC64LE: @0 = private unnamed_addr constant [23 x i8] c"
				// CHECK-NOUSE-PPC64LE: @1 = private unnamed_addr constant %struct.ident_t { i32 0, i32 2, i32 0, i32 22, i8* getelementptr inbounds ([23 x i8], [23 x i8]* @0, i32 0, i32 0) }, align 8
				// CHECK-NOUSE-PPC64LE: @.__omp_offloading_2b_ff075e__Z20explicit_maps_singlei_l716.region_id = weak constant i8 0
	// CHECK-NOUSE-PPC64LE: @.offload_sizes = private unnamed_addr constant [1 x i64] [i64 4]			// CHECK-NOUSE-PPC64LE: @.offload_sizes = private unnamed_addr constant [1 x i64] [i64 4]
	// CHECK-NOUSE-PPC64LE: @.offload_maptypes.1 = private unnamed_addr constant [1 x i64] [i64 [[#0x2407]]]			// CHECK-NOUSE-PPC64LE: @.offload_maptypes.1 = private unnamed_addr constant [1 x i64] [i64 9223]
	// CHECK-NOUSE-PPC64LE: @.offload_maptypes.2 = private unnamed_addr constant [3 x i64] [i64 [[#0x2000]], i64 [[#0x1000000002003]], i64 [[#0x1000000002003]]]			// CHECK-NOUSE-PPC64LE: @.__omp_offloading_2b_ff075e__ZN2ST20test_present_membersEv_l967.region_id = weak constant i8 0
				// CHECK-NOUSE-PPC64LE: @.offload_maptypes.2 = private unnamed_addr constant [3 x i64] [i64 8192, i64 281474976718851, i64 281474976718851]
				// CHECK-NOUSE-PPC64LE: @.omp_offloading.entry_name = internal unnamed_addr constant [58 x i8] c"__omp_offloading_2b_ff075e__Z20explicit_maps_singlei_l702\00"
				// CHECK-NOUSE-PPC64LE: @.omp_offloading.entry.__omp_offloading_2b_ff075e__Z20explicit_maps_singlei_l702 = weak constant %struct.__tgt_offload_entry { i8* @.__omp_offloading_2b_ff075e__Z20explicit_maps_singlei_l702.region_id, i8* getelementptr inbounds ([58 x i8], [58 x i8]* @.omp_offloading.entry_name, i32 0, i32 0), i64 0, i32 0, i32 0 }, section "omp_offloading_entries", align 1
				// CHECK-NOUSE-PPC64LE: @.omp_offloading.entry_name.3 = internal unnamed_addr constant [58 x i8] c"__omp_offloading_2b_ff075e__Z20explicit_maps_singlei_l716\00"
				// CHECK-NOUSE-PPC64LE: @.omp_offloading.entry.__omp_offloading_2b_ff075e__Z20explicit_maps_singlei_l716 = weak constant %struct.__tgt_offload_entry { i8* @.__omp_offloading_2b_ff075e__Z20explicit_maps_singlei_l716.region_id, i8* getelementptr inbounds ([58 x i8], [58 x i8]* @.omp_offloading.entry_name.3, i32 0, i32 0), i64 0, i32 0, i32 0 }, section "omp_offloading_entries", align 1
				// CHECK-NOUSE-PPC64LE: @.omp_offloading.entry_name.4 = internal unnamed_addr constant [63 x i8] c"__omp_offloading_2b_ff075e__ZN2ST20test_present_membersEv_l967\00"
				// CHECK-NOUSE-PPC64LE: @.omp_offloading.entry.__omp_offloading_2b_ff075e__ZN2ST20test_present_membersEv_l967 = weak constant %struct.__tgt_offload_entry { i8* @.__omp_offloading_2b_ff075e__ZN2ST20test_present_membersEv_l967.region_id, i8* getelementptr inbounds ([63 x i8], [63 x i8]* @.omp_offloading.entry_name.4, i32 0, i32 0), i64 0, i32 0, i32 0 }, section "omp_offloading_entries", align 1
				// CHECK-NOUSE-PPC64LE: @llvm.global_ctors = appending global [1 x { i32, void (), i8 }] [{ i32, void (), i8 } { i32 0, void ()* @.omp_offloading.requires_reg, i8* null }]
	//.			//.
	// CHECK-NOUSE-I386: @.offload_maptypes = private unnamed_addr constant [7 x i64] [i64 [[#0x2000]], i64 [[#0x1000000002003]], i64 [[#0x1000000002003]], i64 [[#0x2003]], i64 [[#0x2000]], i64 [[#0x5000000002003]], i64 [[#0x5000000002003]]]			// CHECK-NOUSE-I386: @.__omp_offloading_2b_ff075e__Z20explicit_maps_singlei_l702.region_id = weak constant i8 0
				// CHECK-NOUSE-I386: @.offload_maptypes = private unnamed_addr constant [7 x i64] [i64 8192, i64 281474976718851, i64 281474976718851, i64 8195, i64 8192, i64 1407374883561475, i64 1407374883561475]
				// CHECK-NOUSE-I386: @0 = private unnamed_addr constant [23 x i8] c"
				// CHECK-NOUSE-I386: @1 = private unnamed_addr constant %struct.ident_t { i32 0, i32 2, i32 0, i32 22, i8* getelementptr inbounds ([23 x i8], [23 x i8]* @0, i32 0, i32 0) }, align 8
				// CHECK-NOUSE-I386: @.__omp_offloading_2b_ff075e__Z20explicit_maps_singlei_l716.region_id = weak constant i8 0
	// CHECK-NOUSE-I386: @.offload_sizes = private unnamed_addr constant [1 x i64] [i64 4]			// CHECK-NOUSE-I386: @.offload_sizes = private unnamed_addr constant [1 x i64] [i64 4]
	// CHECK-NOUSE-I386: @.offload_maptypes.1 = private unnamed_addr constant [1 x i64] [i64 [[#0x2407]]]			// CHECK-NOUSE-I386: @.offload_maptypes.1 = private unnamed_addr constant [1 x i64] [i64 9223]
	// CHECK-NOUSE-I386: @.offload_maptypes.2 = private unnamed_addr constant [3 x i64] [i64 [[#0x2000]], i64 [[#0x1000000002003]], i64 [[#0x1000000002003]]]			// CHECK-NOUSE-I386: @.__omp_offloading_2b_ff075e__ZN2ST20test_present_membersEv_l967.region_id = weak constant i8 0
				// CHECK-NOUSE-I386: @.offload_maptypes.2 = private unnamed_addr constant [3 x i64] [i64 8192, i64 281474976718851, i64 281474976718851]
				// CHECK-NOUSE-I386: @.omp_offloading.entry_name = internal unnamed_addr constant [58 x i8] c"__omp_offloading_2b_ff075e__Z20explicit_maps_singlei_l702\00"
				// CHECK-NOUSE-I386: @.omp_offloading.entry.__omp_offloading_2b_ff075e__Z20explicit_maps_singlei_l702 = weak constant %struct.__tgt_offload_entry { i8* @.__omp_offloading_2b_ff075e__Z20explicit_maps_singlei_l702.region_id, i8* getelementptr inbounds ([58 x i8], [58 x i8]* @.omp_offloading.entry_name, i32 0, i32 0), i32 0, i32 0, i32 0 }, section "omp_offloading_entries", align 1
				// CHECK-NOUSE-I386: @.omp_offloading.entry_name.3 = internal unnamed_addr constant [58 x i8] c"__omp_offloading_2b_ff075e__Z20explicit_maps_singlei_l716\00"
				// CHECK-NOUSE-I386: @.omp_offloading.entry.__omp_offloading_2b_ff075e__Z20explicit_maps_singlei_l716 = weak constant %struct.__tgt_offload_entry { i8* @.__omp_offloading_2b_ff075e__Z20explicit_maps_singlei_l716.region_id, i8* getelementptr inbounds ([58 x i8], [58 x i8]* @.omp_offloading.entry_name.3, i32 0, i32 0), i32 0, i32 0, i32 0 }, section "omp_offloading_entries", align 1
				// CHECK-NOUSE-I386: @.omp_offloading.entry_name.4 = internal unnamed_addr constant [63 x i8] c"__omp_offloading_2b_ff075e__ZN2ST20test_present_membersEv_l967\00"
				// CHECK-NOUSE-I386: @.omp_offloading.entry.__omp_offloading_2b_ff075e__ZN2ST20test_present_membersEv_l967 = weak constant %struct.__tgt_offload_entry { i8* @.__omp_offloading_2b_ff075e__ZN2ST20test_present_membersEv_l967.region_id, i8* getelementptr inbounds ([63 x i8], [63 x i8]* @.omp_offloading.entry_name.4, i32 0, i32 0), i32 0, i32 0, i32 0 }, section "omp_offloading_entries", align 1
				// CHECK-NOUSE-I386: @llvm.global_ctors = appending global [1 x { i32, void (), i8 }] [{ i32, void (), i8 } { i32 0, void ()* @.omp_offloading.requires_reg, i8* null }]
	//.			//.
	struct ST {			struct ST {
	int i;			int i;
	int j;			int j;
	void test_present_members();			void test_present_members();
	};			};

	// CHECK-USE-PPC64LE-LABEL: @_Z20explicit_maps_singlei(			// CHECK-USE-PPC64LE-LABEL: @_Z20explicit_maps_singlei(
	▲ Show 20 Lines • Show All 98 Lines • ▼ Show 20 Lines
	// CHECK-USE-PPC64LE-NEXT: store i32* [[J2]], i32** [[TMP54]], align 8			// CHECK-USE-PPC64LE-NEXT: store i32* [[J2]], i32** [[TMP54]], align 8
	// CHECK-USE-PPC64LE-NEXT: [[TMP55:%.]] = getelementptr inbounds [7 x i64], [7 x i64] [[DOTOFFLOAD_SIZES]], i32 0, i32 6			// CHECK-USE-PPC64LE-NEXT: [[TMP55:%.]] = getelementptr inbounds [7 x i64], [7 x i64] [[DOTOFFLOAD_SIZES]], i32 0, i32 6
	// CHECK-USE-PPC64LE-NEXT: store i64 4, i64* [[TMP55]], align 8			// CHECK-USE-PPC64LE-NEXT: store i64 4, i64* [[TMP55]], align 8
	// CHECK-USE-PPC64LE-NEXT: [[TMP56:%.]] = getelementptr inbounds [7 x i8], [7 x i8] [[DOTOFFLOAD_MAPPERS]], i64 0, i64 6			// CHECK-USE-PPC64LE-NEXT: [[TMP56:%.]] = getelementptr inbounds [7 x i8], [7 x i8] [[DOTOFFLOAD_MAPPERS]], i64 0, i64 6
	// CHECK-USE-PPC64LE-NEXT: store i8* null, i8** [[TMP56]], align 8			// CHECK-USE-PPC64LE-NEXT: store i8* null, i8** [[TMP56]], align 8
	// CHECK-USE-PPC64LE-NEXT: [[TMP57:%.]] = getelementptr inbounds [7 x i8], [7 x i8] [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0			// CHECK-USE-PPC64LE-NEXT: [[TMP57:%.]] = getelementptr inbounds [7 x i8], [7 x i8] [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
	// CHECK-USE-PPC64LE-NEXT: [[TMP58:%.]] = getelementptr inbounds [7 x i8], [7 x i8] [[DOTOFFLOAD_PTRS]], i32 0, i32 0			// CHECK-USE-PPC64LE-NEXT: [[TMP58:%.]] = getelementptr inbounds [7 x i8], [7 x i8] [[DOTOFFLOAD_PTRS]], i32 0, i32 0
	// CHECK-USE-PPC64LE-NEXT: [[TMP59:%.]] = getelementptr inbounds [7 x i64], [7 x i64] [[DOTOFFLOAD_SIZES]], i32 0, i32 0			// CHECK-USE-PPC64LE-NEXT: [[TMP59:%.]] = getelementptr inbounds [7 x i64], [7 x i64] [[DOTOFFLOAD_SIZES]], i32 0, i32 0
	// CHECK-USE-PPC64LE-NEXT: [[TMP60:%.]] = call i32 @__tgt_target_mapper(%struct.ident_t @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z20explicit_maps_singlei_l654.region_id, i32 7, i8 [[TMP57]], i8 [[TMP58]], i64* [[TMP59]], i64* getelementptr inbounds ([7 x i64], [7 x i64]* @.offload_maptypes, i32 0, i32 0), i8 null, i8 null)			// CHECK-USE-PPC64LE-NEXT: [[TMP60:%.]] = call i32 @__tgt_target_mapper(%struct.ident_t @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z20explicit_maps_singlei_l702.region_id, i32 7, i8 [[TMP57]], i8 [[TMP58]], i64* [[TMP59]], i64* getelementptr inbounds ([7 x i64], [7 x i64]* @.offload_maptypes, i32 0, i32 0), i8 null, i8 null)
	// CHECK-USE-PPC64LE-NEXT: [[TMP61:%.*]] = icmp ne i32 [[TMP60]], 0			// CHECK-USE-PPC64LE-NEXT: [[TMP61:%.*]] = icmp ne i32 [[TMP60]], 0
	// CHECK-USE-PPC64LE-NEXT: br i1 [[TMP61]], label [[OMP_OFFLOAD_FAILED:%.]], label [[OMP_OFFLOAD_CONT:%.]]			// CHECK-USE-PPC64LE-NEXT: br i1 [[TMP61]], label [[OMP_OFFLOAD_FAILED:%.]], label [[OMP_OFFLOAD_CONT:%.]]
	// CHECK-USE-PPC64LE: omp_offload.failed:			// CHECK-USE-PPC64LE: omp_offload.failed:
	// CHECK-USE-PPC64LE-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z20explicit_maps_singlei_l654(%struct.ST* [[ST1]], i32* [[A]], %struct.ST* [[ST2]]) #[[ATTR2:[0-9]+]]			// CHECK-USE-PPC64LE-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z20explicit_maps_singlei_l702(%struct.ST* [[ST1]], i32* [[A]], %struct.ST* [[ST2]]) #[[ATTR2:[0-9]+]]
	// CHECK-USE-PPC64LE-NEXT: br label [[OMP_OFFLOAD_CONT]]			// CHECK-USE-PPC64LE-NEXT: br label [[OMP_OFFLOAD_CONT]]
	// CHECK-USE-PPC64LE: omp_offload.cont:			// CHECK-USE-PPC64LE: omp_offload.cont:
	// CHECK-USE-PPC64LE-NEXT: [[TMP62:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 0			// CHECK-USE-PPC64LE-NEXT: [[TMP62:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 0
	// CHECK-USE-PPC64LE-NEXT: [[TMP63:%.]] = bitcast i8* [[TMP62]] to i32**			// CHECK-USE-PPC64LE-NEXT: [[TMP63:%.]] = bitcast i8* [[TMP62]] to i32**
	// CHECK-USE-PPC64LE-NEXT: store i32* [[A]], i32** [[TMP63]], align 8			// CHECK-USE-PPC64LE-NEXT: store i32* [[A]], i32** [[TMP63]], align 8
	// CHECK-USE-PPC64LE-NEXT: [[TMP64:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[DOTOFFLOAD_PTRS4]], i32 0, i32 0			// CHECK-USE-PPC64LE-NEXT: [[TMP64:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[DOTOFFLOAD_PTRS4]], i32 0, i32 0
	// CHECK-USE-PPC64LE-NEXT: [[TMP65:%.]] = bitcast i8* [[TMP64]] to i32**			// CHECK-USE-PPC64LE-NEXT: [[TMP65:%.]] = bitcast i8* [[TMP64]] to i32**
	// CHECK-USE-PPC64LE-NEXT: store i32* [[A]], i32** [[TMP65]], align 8			// CHECK-USE-PPC64LE-NEXT: store i32* [[A]], i32** [[TMP65]], align 8
	// CHECK-USE-PPC64LE-NEXT: [[TMP66:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[DOTOFFLOAD_MAPPERS5]], i64 0, i64 0			// CHECK-USE-PPC64LE-NEXT: [[TMP66:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[DOTOFFLOAD_MAPPERS5]], i64 0, i64 0
	// CHECK-USE-PPC64LE-NEXT: store i8* null, i8** [[TMP66]], align 8			// CHECK-USE-PPC64LE-NEXT: store i8* null, i8** [[TMP66]], align 8
	// CHECK-USE-PPC64LE-NEXT: [[TMP67:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 0			// CHECK-USE-PPC64LE-NEXT: [[TMP67:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 0
	// CHECK-USE-PPC64LE-NEXT: [[TMP68:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[DOTOFFLOAD_PTRS4]], i32 0, i32 0			// CHECK-USE-PPC64LE-NEXT: [[TMP68:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[DOTOFFLOAD_PTRS4]], i32 0, i32 0
	// CHECK-USE-PPC64LE-NEXT: [[TMP69:%.]] = call i32 @__tgt_target_mapper(%struct.ident_t @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z20explicit_maps_singlei_l668.region_id, i32 1, i8 [[TMP67]], i8 [[TMP68]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.1, i32 0, i32 0), i8 null, i8 null)			// CHECK-USE-PPC64LE-NEXT: [[TMP69:%.]] = call i32 @__tgt_target_mapper(%struct.ident_t @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z20explicit_maps_singlei_l716.region_id, i32 1, i8 [[TMP67]], i8 [[TMP68]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.1, i32 0, i32 0), i8 null, i8 null)
	// CHECK-USE-PPC64LE-NEXT: [[TMP70:%.*]] = icmp ne i32 [[TMP69]], 0			// CHECK-USE-PPC64LE-NEXT: [[TMP70:%.*]] = icmp ne i32 [[TMP69]], 0
	// CHECK-USE-PPC64LE-NEXT: br i1 [[TMP70]], label [[OMP_OFFLOAD_FAILED6:%.]], label [[OMP_OFFLOAD_CONT7:%.]]			// CHECK-USE-PPC64LE-NEXT: br i1 [[TMP70]], label [[OMP_OFFLOAD_FAILED6:%.]], label [[OMP_OFFLOAD_CONT7:%.]]
	// CHECK-USE-PPC64LE: omp_offload.failed6:			// CHECK-USE-PPC64LE: omp_offload.failed6:
	// CHECK-USE-PPC64LE-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z20explicit_maps_singlei_l668(i32* [[A]]) #[[ATTR2]]			// CHECK-USE-PPC64LE-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z20explicit_maps_singlei_l716(i32* [[A]]) #[[ATTR2]]
	// CHECK-USE-PPC64LE-NEXT: br label [[OMP_OFFLOAD_CONT7]]			// CHECK-USE-PPC64LE-NEXT: br label [[OMP_OFFLOAD_CONT7]]
	// CHECK-USE-PPC64LE: omp_offload.cont7:			// CHECK-USE-PPC64LE: omp_offload.cont7:
	// CHECK-USE-PPC64LE-NEXT: ret void			// CHECK-USE-PPC64LE-NEXT: ret void
	//			//
	// CHECK-USE-I386-LABEL: @_Z20explicit_maps_singlei(			// CHECK-USE-I386-LABEL: @_Z20explicit_maps_singlei(
	// CHECK-USE-I386-NEXT: entry:			// CHECK-USE-I386-NEXT: entry:
	// CHECK-USE-I386-NEXT: [[II_ADDR:%.*]] = alloca i32, align 4			// CHECK-USE-I386-NEXT: [[II_ADDR:%.*]] = alloca i32, align 4
	// CHECK-USE-I386-NEXT: [[A:%.*]] = alloca i32, align 4			// CHECK-USE-I386-NEXT: [[A:%.*]] = alloca i32, align 4
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	// CHECK-USE-I386-NEXT: store i32* [[J2]], i32** [[TMP54]], align 4			// CHECK-USE-I386-NEXT: store i32* [[J2]], i32** [[TMP54]], align 4
	// CHECK-USE-I386-NEXT: [[TMP55:%.]] = getelementptr inbounds [7 x i64], [7 x i64] [[DOTOFFLOAD_SIZES]], i32 0, i32 6			// CHECK-USE-I386-NEXT: [[TMP55:%.]] = getelementptr inbounds [7 x i64], [7 x i64] [[DOTOFFLOAD_SIZES]], i32 0, i32 6
	// CHECK-USE-I386-NEXT: store i64 4, i64* [[TMP55]], align 4			// CHECK-USE-I386-NEXT: store i64 4, i64* [[TMP55]], align 4
	// CHECK-USE-I386-NEXT: [[TMP56:%.]] = getelementptr inbounds [7 x i8], [7 x i8] [[DOTOFFLOAD_MAPPERS]], i32 0, i32 6			// CHECK-USE-I386-NEXT: [[TMP56:%.]] = getelementptr inbounds [7 x i8], [7 x i8] [[DOTOFFLOAD_MAPPERS]], i32 0, i32 6
	// CHECK-USE-I386-NEXT: store i8* null, i8** [[TMP56]], align 4			// CHECK-USE-I386-NEXT: store i8* null, i8** [[TMP56]], align 4
	// CHECK-USE-I386-NEXT: [[TMP57:%.]] = getelementptr inbounds [7 x i8], [7 x i8] [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0			// CHECK-USE-I386-NEXT: [[TMP57:%.]] = getelementptr inbounds [7 x i8], [7 x i8] [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
	// CHECK-USE-I386-NEXT: [[TMP58:%.]] = getelementptr inbounds [7 x i8], [7 x i8] [[DOTOFFLOAD_PTRS]], i32 0, i32 0			// CHECK-USE-I386-NEXT: [[TMP58:%.]] = getelementptr inbounds [7 x i8], [7 x i8] [[DOTOFFLOAD_PTRS]], i32 0, i32 0
	// CHECK-USE-I386-NEXT: [[TMP59:%.]] = getelementptr inbounds [7 x i64], [7 x i64] [[DOTOFFLOAD_SIZES]], i32 0, i32 0			// CHECK-USE-I386-NEXT: [[TMP59:%.]] = getelementptr inbounds [7 x i64], [7 x i64] [[DOTOFFLOAD_SIZES]], i32 0, i32 0
	// CHECK-USE-I386-NEXT: [[TMP60:%.]] = call i32 @__tgt_target_mapper(%struct.ident_t @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z20explicit_maps_singlei_l654.region_id, i32 7, i8 [[TMP57]], i8 [[TMP58]], i64* [[TMP59]], i64* getelementptr inbounds ([7 x i64], [7 x i64]* @.offload_maptypes, i32 0, i32 0), i8 null, i8 null)			// CHECK-USE-I386-NEXT: [[TMP60:%.]] = call i32 @__tgt_target_mapper(%struct.ident_t @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z20explicit_maps_singlei_l702.region_id, i32 7, i8 [[TMP57]], i8 [[TMP58]], i64* [[TMP59]], i64* getelementptr inbounds ([7 x i64], [7 x i64]* @.offload_maptypes, i32 0, i32 0), i8 null, i8 null)
	// CHECK-USE-I386-NEXT: [[TMP61:%.*]] = icmp ne i32 [[TMP60]], 0			// CHECK-USE-I386-NEXT: [[TMP61:%.*]] = icmp ne i32 [[TMP60]], 0
	// CHECK-USE-I386-NEXT: br i1 [[TMP61]], label [[OMP_OFFLOAD_FAILED:%.]], label [[OMP_OFFLOAD_CONT:%.]]			// CHECK-USE-I386-NEXT: br i1 [[TMP61]], label [[OMP_OFFLOAD_FAILED:%.]], label [[OMP_OFFLOAD_CONT:%.]]
	// CHECK-USE-I386: omp_offload.failed:			// CHECK-USE-I386: omp_offload.failed:
	// CHECK-USE-I386-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z20explicit_maps_singlei_l654(%struct.ST* [[ST1]], i32* [[A]], %struct.ST* [[ST2]]) #[[ATTR2:[0-9]+]]			// CHECK-USE-I386-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z20explicit_maps_singlei_l702(%struct.ST* [[ST1]], i32* [[A]], %struct.ST* [[ST2]]) #[[ATTR2:[0-9]+]]
	// CHECK-USE-I386-NEXT: br label [[OMP_OFFLOAD_CONT]]			// CHECK-USE-I386-NEXT: br label [[OMP_OFFLOAD_CONT]]
	// CHECK-USE-I386: omp_offload.cont:			// CHECK-USE-I386: omp_offload.cont:
	// CHECK-USE-I386-NEXT: [[TMP62:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 0			// CHECK-USE-I386-NEXT: [[TMP62:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 0
	// CHECK-USE-I386-NEXT: [[TMP63:%.]] = bitcast i8* [[TMP62]] to i32**			// CHECK-USE-I386-NEXT: [[TMP63:%.]] = bitcast i8* [[TMP62]] to i32**
	// CHECK-USE-I386-NEXT: store i32* [[A]], i32** [[TMP63]], align 4			// CHECK-USE-I386-NEXT: store i32* [[A]], i32** [[TMP63]], align 4
	// CHECK-USE-I386-NEXT: [[TMP64:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[DOTOFFLOAD_PTRS4]], i32 0, i32 0			// CHECK-USE-I386-NEXT: [[TMP64:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[DOTOFFLOAD_PTRS4]], i32 0, i32 0
	// CHECK-USE-I386-NEXT: [[TMP65:%.]] = bitcast i8* [[TMP64]] to i32**			// CHECK-USE-I386-NEXT: [[TMP65:%.]] = bitcast i8* [[TMP64]] to i32**
	// CHECK-USE-I386-NEXT: store i32* [[A]], i32** [[TMP65]], align 4			// CHECK-USE-I386-NEXT: store i32* [[A]], i32** [[TMP65]], align 4
	// CHECK-USE-I386-NEXT: [[TMP66:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[DOTOFFLOAD_MAPPERS5]], i32 0, i32 0			// CHECK-USE-I386-NEXT: [[TMP66:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[DOTOFFLOAD_MAPPERS5]], i32 0, i32 0
	// CHECK-USE-I386-NEXT: store i8* null, i8** [[TMP66]], align 4			// CHECK-USE-I386-NEXT: store i8* null, i8** [[TMP66]], align 4
	// CHECK-USE-I386-NEXT: [[TMP67:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 0			// CHECK-USE-I386-NEXT: [[TMP67:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 0
	// CHECK-USE-I386-NEXT: [[TMP68:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[DOTOFFLOAD_PTRS4]], i32 0, i32 0			// CHECK-USE-I386-NEXT: [[TMP68:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[DOTOFFLOAD_PTRS4]], i32 0, i32 0
	// CHECK-USE-I386-NEXT: [[TMP69:%.]] = call i32 @__tgt_target_mapper(%struct.ident_t @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z20explicit_maps_singlei_l668.region_id, i32 1, i8 [[TMP67]], i8 [[TMP68]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.1, i32 0, i32 0), i8 null, i8 null)			// CHECK-USE-I386-NEXT: [[TMP69:%.]] = call i32 @__tgt_target_mapper(%struct.ident_t @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z20explicit_maps_singlei_l716.region_id, i32 1, i8 [[TMP67]], i8 [[TMP68]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.1, i32 0, i32 0), i8 null, i8 null)
	// CHECK-USE-I386-NEXT: [[TMP70:%.*]] = icmp ne i32 [[TMP69]], 0			// CHECK-USE-I386-NEXT: [[TMP70:%.*]] = icmp ne i32 [[TMP69]], 0
	// CHECK-USE-I386-NEXT: br i1 [[TMP70]], label [[OMP_OFFLOAD_FAILED6:%.]], label [[OMP_OFFLOAD_CONT7:%.]]			// CHECK-USE-I386-NEXT: br i1 [[TMP70]], label [[OMP_OFFLOAD_FAILED6:%.]], label [[OMP_OFFLOAD_CONT7:%.]]
	// CHECK-USE-I386: omp_offload.failed6:			// CHECK-USE-I386: omp_offload.failed6:
	// CHECK-USE-I386-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z20explicit_maps_singlei_l668(i32* [[A]]) #[[ATTR2]]			// CHECK-USE-I386-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z20explicit_maps_singlei_l716(i32* [[A]]) #[[ATTR2]]
	// CHECK-USE-I386-NEXT: br label [[OMP_OFFLOAD_CONT7]]			// CHECK-USE-I386-NEXT: br label [[OMP_OFFLOAD_CONT7]]
	// CHECK-USE-I386: omp_offload.cont7:			// CHECK-USE-I386: omp_offload.cont7:
	// CHECK-USE-I386-NEXT: ret void			// CHECK-USE-I386-NEXT: ret void
	//			//
	// CHECK-NOUSE-PPC64LE-LABEL: @_Z20explicit_maps_singlei(			// CHECK-NOUSE-PPC64LE-LABEL: @_Z20explicit_maps_singlei(
	// CHECK-NOUSE-PPC64LE-NEXT: entry:			// CHECK-NOUSE-PPC64LE-NEXT: entry:
	// CHECK-NOUSE-PPC64LE-NEXT: [[II_ADDR:%.*]] = alloca i32, align 4			// CHECK-NOUSE-PPC64LE-NEXT: [[II_ADDR:%.*]] = alloca i32, align 4
	// CHECK-NOUSE-PPC64LE-NEXT: [[A:%.*]] = alloca i32, align 4			// CHECK-NOUSE-PPC64LE-NEXT: [[A:%.*]] = alloca i32, align 4
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	// CHECK-NOUSE-PPC64LE-NEXT: store i32* [[J2]], i32** [[TMP54]], align 8			// CHECK-NOUSE-PPC64LE-NEXT: store i32* [[J2]], i32** [[TMP54]], align 8
	// CHECK-NOUSE-PPC64LE-NEXT: [[TMP55:%.]] = getelementptr inbounds [7 x i64], [7 x i64] [[DOTOFFLOAD_SIZES]], i32 0, i32 6			// CHECK-NOUSE-PPC64LE-NEXT: [[TMP55:%.]] = getelementptr inbounds [7 x i64], [7 x i64] [[DOTOFFLOAD_SIZES]], i32 0, i32 6
	// CHECK-NOUSE-PPC64LE-NEXT: store i64 4, i64* [[TMP55]], align 8			// CHECK-NOUSE-PPC64LE-NEXT: store i64 4, i64* [[TMP55]], align 8
	// CHECK-NOUSE-PPC64LE-NEXT: [[TMP56:%.]] = getelementptr inbounds [7 x i8], [7 x i8] [[DOTOFFLOAD_MAPPERS]], i64 0, i64 6			// CHECK-NOUSE-PPC64LE-NEXT: [[TMP56:%.]] = getelementptr inbounds [7 x i8], [7 x i8] [[DOTOFFLOAD_MAPPERS]], i64 0, i64 6
	// CHECK-NOUSE-PPC64LE-NEXT: store i8* null, i8** [[TMP56]], align 8			// CHECK-NOUSE-PPC64LE-NEXT: store i8* null, i8** [[TMP56]], align 8
	// CHECK-NOUSE-PPC64LE-NEXT: [[TMP57:%.]] = getelementptr inbounds [7 x i8], [7 x i8] [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0			// CHECK-NOUSE-PPC64LE-NEXT: [[TMP57:%.]] = getelementptr inbounds [7 x i8], [7 x i8] [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
	// CHECK-NOUSE-PPC64LE-NEXT: [[TMP58:%.]] = getelementptr inbounds [7 x i8], [7 x i8] [[DOTOFFLOAD_PTRS]], i32 0, i32 0			// CHECK-NOUSE-PPC64LE-NEXT: [[TMP58:%.]] = getelementptr inbounds [7 x i8], [7 x i8] [[DOTOFFLOAD_PTRS]], i32 0, i32 0
	// CHECK-NOUSE-PPC64LE-NEXT: [[TMP59:%.]] = getelementptr inbounds [7 x i64], [7 x i64] [[DOTOFFLOAD_SIZES]], i32 0, i32 0			// CHECK-NOUSE-PPC64LE-NEXT: [[TMP59:%.]] = getelementptr inbounds [7 x i64], [7 x i64] [[DOTOFFLOAD_SIZES]], i32 0, i32 0
	// CHECK-NOUSE-PPC64LE-NEXT: [[TMP60:%.]] = call i32 @__tgt_target_mapper(%struct.ident_t @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z20explicit_maps_singlei_l654.region_id, i32 7, i8 [[TMP57]], i8 [[TMP58]], i64* [[TMP59]], i64* getelementptr inbounds ([7 x i64], [7 x i64]* @.offload_maptypes, i32 0, i32 0), i8 null, i8 null)			// CHECK-NOUSE-PPC64LE-NEXT: [[TMP60:%.]] = call i32 @__tgt_target_mapper(%struct.ident_t @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z20explicit_maps_singlei_l702.region_id, i32 7, i8 [[TMP57]], i8 [[TMP58]], i64* [[TMP59]], i64* getelementptr inbounds ([7 x i64], [7 x i64]* @.offload_maptypes, i32 0, i32 0), i8 null, i8 null)
	// CHECK-NOUSE-PPC64LE-NEXT: [[TMP61:%.*]] = icmp ne i32 [[TMP60]], 0			// CHECK-NOUSE-PPC64LE-NEXT: [[TMP61:%.*]] = icmp ne i32 [[TMP60]], 0
	// CHECK-NOUSE-PPC64LE-NEXT: br i1 [[TMP61]], label [[OMP_OFFLOAD_FAILED:%.]], label [[OMP_OFFLOAD_CONT:%.]]			// CHECK-NOUSE-PPC64LE-NEXT: br i1 [[TMP61]], label [[OMP_OFFLOAD_FAILED:%.]], label [[OMP_OFFLOAD_CONT:%.]]
	// CHECK-NOUSE-PPC64LE: omp_offload.failed:			// CHECK-NOUSE-PPC64LE: omp_offload.failed:
	// CHECK-NOUSE-PPC64LE-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z20explicit_maps_singlei_l654() #[[ATTR2:[0-9]+]]			// CHECK-NOUSE-PPC64LE-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z20explicit_maps_singlei_l702() #[[ATTR2:[0-9]+]]
	// CHECK-NOUSE-PPC64LE-NEXT: br label [[OMP_OFFLOAD_CONT]]			// CHECK-NOUSE-PPC64LE-NEXT: br label [[OMP_OFFLOAD_CONT]]
	// CHECK-NOUSE-PPC64LE: omp_offload.cont:			// CHECK-NOUSE-PPC64LE: omp_offload.cont:
	// CHECK-NOUSE-PPC64LE-NEXT: [[TMP62:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 0			// CHECK-NOUSE-PPC64LE-NEXT: [[TMP62:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 0
	// CHECK-NOUSE-PPC64LE-NEXT: [[TMP63:%.]] = bitcast i8* [[TMP62]] to i32**			// CHECK-NOUSE-PPC64LE-NEXT: [[TMP63:%.]] = bitcast i8* [[TMP62]] to i32**
	// CHECK-NOUSE-PPC64LE-NEXT: store i32* [[A]], i32** [[TMP63]], align 8			// CHECK-NOUSE-PPC64LE-NEXT: store i32* [[A]], i32** [[TMP63]], align 8
	// CHECK-NOUSE-PPC64LE-NEXT: [[TMP64:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[DOTOFFLOAD_PTRS4]], i32 0, i32 0			// CHECK-NOUSE-PPC64LE-NEXT: [[TMP64:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[DOTOFFLOAD_PTRS4]], i32 0, i32 0
	// CHECK-NOUSE-PPC64LE-NEXT: [[TMP65:%.]] = bitcast i8* [[TMP64]] to i32**			// CHECK-NOUSE-PPC64LE-NEXT: [[TMP65:%.]] = bitcast i8* [[TMP64]] to i32**
	// CHECK-NOUSE-PPC64LE-NEXT: store i32* [[A]], i32** [[TMP65]], align 8			// CHECK-NOUSE-PPC64LE-NEXT: store i32* [[A]], i32** [[TMP65]], align 8
	// CHECK-NOUSE-PPC64LE-NEXT: [[TMP66:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[DOTOFFLOAD_MAPPERS5]], i64 0, i64 0			// CHECK-NOUSE-PPC64LE-NEXT: [[TMP66:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[DOTOFFLOAD_MAPPERS5]], i64 0, i64 0
	// CHECK-NOUSE-PPC64LE-NEXT: store i8* null, i8** [[TMP66]], align 8			// CHECK-NOUSE-PPC64LE-NEXT: store i8* null, i8** [[TMP66]], align 8
	// CHECK-NOUSE-PPC64LE-NEXT: [[TMP67:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 0			// CHECK-NOUSE-PPC64LE-NEXT: [[TMP67:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 0
	// CHECK-NOUSE-PPC64LE-NEXT: [[TMP68:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[DOTOFFLOAD_PTRS4]], i32 0, i32 0			// CHECK-NOUSE-PPC64LE-NEXT: [[TMP68:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[DOTOFFLOAD_PTRS4]], i32 0, i32 0
	// CHECK-NOUSE-PPC64LE-NEXT: [[TMP69:%.]] = call i32 @__tgt_target_mapper(%struct.ident_t @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z20explicit_maps_singlei_l668.region_id, i32 1, i8 [[TMP67]], i8 [[TMP68]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.1, i32 0, i32 0), i8 null, i8 null)			// CHECK-NOUSE-PPC64LE-NEXT: [[TMP69:%.]] = call i32 @__tgt_target_mapper(%struct.ident_t @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z20explicit_maps_singlei_l716.region_id, i32 1, i8 [[TMP67]], i8 [[TMP68]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.1, i32 0, i32 0), i8 null, i8 null)
	// CHECK-NOUSE-PPC64LE-NEXT: [[TMP70:%.*]] = icmp ne i32 [[TMP69]], 0			// CHECK-NOUSE-PPC64LE-NEXT: [[TMP70:%.*]] = icmp ne i32 [[TMP69]], 0
	// CHECK-NOUSE-PPC64LE-NEXT: br i1 [[TMP70]], label [[OMP_OFFLOAD_FAILED6:%.]], label [[OMP_OFFLOAD_CONT7:%.]]			// CHECK-NOUSE-PPC64LE-NEXT: br i1 [[TMP70]], label [[OMP_OFFLOAD_FAILED6:%.]], label [[OMP_OFFLOAD_CONT7:%.]]
	// CHECK-NOUSE-PPC64LE: omp_offload.failed6:			// CHECK-NOUSE-PPC64LE: omp_offload.failed6:
	// CHECK-NOUSE-PPC64LE-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z20explicit_maps_singlei_l668() #[[ATTR2]]			// CHECK-NOUSE-PPC64LE-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z20explicit_maps_singlei_l716() #[[ATTR2]]
	// CHECK-NOUSE-PPC64LE-NEXT: br label [[OMP_OFFLOAD_CONT7]]			// CHECK-NOUSE-PPC64LE-NEXT: br label [[OMP_OFFLOAD_CONT7]]
	// CHECK-NOUSE-PPC64LE: omp_offload.cont7:			// CHECK-NOUSE-PPC64LE: omp_offload.cont7:
	// CHECK-NOUSE-PPC64LE-NEXT: ret void			// CHECK-NOUSE-PPC64LE-NEXT: ret void
	//			//
	// CHECK-NOUSE-I386-LABEL: @_Z20explicit_maps_singlei(			// CHECK-NOUSE-I386-LABEL: @_Z20explicit_maps_singlei(
	// CHECK-NOUSE-I386-NEXT: entry:			// CHECK-NOUSE-I386-NEXT: entry:
	// CHECK-NOUSE-I386-NEXT: [[II_ADDR:%.*]] = alloca i32, align 4			// CHECK-NOUSE-I386-NEXT: [[II_ADDR:%.*]] = alloca i32, align 4
	// CHECK-NOUSE-I386-NEXT: [[A:%.*]] = alloca i32, align 4			// CHECK-NOUSE-I386-NEXT: [[A:%.*]] = alloca i32, align 4
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	// CHECK-NOUSE-I386-NEXT: store i32* [[J2]], i32** [[TMP54]], align 4			// CHECK-NOUSE-I386-NEXT: store i32* [[J2]], i32** [[TMP54]], align 4
	// CHECK-NOUSE-I386-NEXT: [[TMP55:%.]] = getelementptr inbounds [7 x i64], [7 x i64] [[DOTOFFLOAD_SIZES]], i32 0, i32 6			// CHECK-NOUSE-I386-NEXT: [[TMP55:%.]] = getelementptr inbounds [7 x i64], [7 x i64] [[DOTOFFLOAD_SIZES]], i32 0, i32 6
	// CHECK-NOUSE-I386-NEXT: store i64 4, i64* [[TMP55]], align 4			// CHECK-NOUSE-I386-NEXT: store i64 4, i64* [[TMP55]], align 4
	// CHECK-NOUSE-I386-NEXT: [[TMP56:%.]] = getelementptr inbounds [7 x i8], [7 x i8] [[DOTOFFLOAD_MAPPERS]], i32 0, i32 6			// CHECK-NOUSE-I386-NEXT: [[TMP56:%.]] = getelementptr inbounds [7 x i8], [7 x i8] [[DOTOFFLOAD_MAPPERS]], i32 0, i32 6
	// CHECK-NOUSE-I386-NEXT: store i8* null, i8** [[TMP56]], align 4			// CHECK-NOUSE-I386-NEXT: store i8* null, i8** [[TMP56]], align 4
	// CHECK-NOUSE-I386-NEXT: [[TMP57:%.]] = getelementptr inbounds [7 x i8], [7 x i8] [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0			// CHECK-NOUSE-I386-NEXT: [[TMP57:%.]] = getelementptr inbounds [7 x i8], [7 x i8] [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
	// CHECK-NOUSE-I386-NEXT: [[TMP58:%.]] = getelementptr inbounds [7 x i8], [7 x i8] [[DOTOFFLOAD_PTRS]], i32 0, i32 0			// CHECK-NOUSE-I386-NEXT: [[TMP58:%.]] = getelementptr inbounds [7 x i8], [7 x i8] [[DOTOFFLOAD_PTRS]], i32 0, i32 0
	// CHECK-NOUSE-I386-NEXT: [[TMP59:%.]] = getelementptr inbounds [7 x i64], [7 x i64] [[DOTOFFLOAD_SIZES]], i32 0, i32 0			// CHECK-NOUSE-I386-NEXT: [[TMP59:%.]] = getelementptr inbounds [7 x i64], [7 x i64] [[DOTOFFLOAD_SIZES]], i32 0, i32 0
	// CHECK-NOUSE-I386-NEXT: [[TMP60:%.]] = call i32 @__tgt_target_mapper(%struct.ident_t @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z20explicit_maps_singlei_l654.region_id, i32 7, i8 [[TMP57]], i8 [[TMP58]], i64* [[TMP59]], i64* getelementptr inbounds ([7 x i64], [7 x i64]* @.offload_maptypes, i32 0, i32 0), i8 null, i8 null)			// CHECK-NOUSE-I386-NEXT: [[TMP60:%.]] = call i32 @__tgt_target_mapper(%struct.ident_t @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z20explicit_maps_singlei_l702.region_id, i32 7, i8 [[TMP57]], i8 [[TMP58]], i64* [[TMP59]], i64* getelementptr inbounds ([7 x i64], [7 x i64]* @.offload_maptypes, i32 0, i32 0), i8 null, i8 null)
	// CHECK-NOUSE-I386-NEXT: [[TMP61:%.*]] = icmp ne i32 [[TMP60]], 0			// CHECK-NOUSE-I386-NEXT: [[TMP61:%.*]] = icmp ne i32 [[TMP60]], 0
	// CHECK-NOUSE-I386-NEXT: br i1 [[TMP61]], label [[OMP_OFFLOAD_FAILED:%.]], label [[OMP_OFFLOAD_CONT:%.]]			// CHECK-NOUSE-I386-NEXT: br i1 [[TMP61]], label [[OMP_OFFLOAD_FAILED:%.]], label [[OMP_OFFLOAD_CONT:%.]]
	// CHECK-NOUSE-I386: omp_offload.failed:			// CHECK-NOUSE-I386: omp_offload.failed:
	// CHECK-NOUSE-I386-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z20explicit_maps_singlei_l654() #[[ATTR2:[0-9]+]]			// CHECK-NOUSE-I386-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z20explicit_maps_singlei_l702() #[[ATTR2:[0-9]+]]
	// CHECK-NOUSE-I386-NEXT: br label [[OMP_OFFLOAD_CONT]]			// CHECK-NOUSE-I386-NEXT: br label [[OMP_OFFLOAD_CONT]]
	// CHECK-NOUSE-I386: omp_offload.cont:			// CHECK-NOUSE-I386: omp_offload.cont:
	// CHECK-NOUSE-I386-NEXT: [[TMP62:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 0			// CHECK-NOUSE-I386-NEXT: [[TMP62:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 0
	// CHECK-NOUSE-I386-NEXT: [[TMP63:%.]] = bitcast i8* [[TMP62]] to i32**			// CHECK-NOUSE-I386-NEXT: [[TMP63:%.]] = bitcast i8* [[TMP62]] to i32**
	// CHECK-NOUSE-I386-NEXT: store i32* [[A]], i32** [[TMP63]], align 4			// CHECK-NOUSE-I386-NEXT: store i32* [[A]], i32** [[TMP63]], align 4
	// CHECK-NOUSE-I386-NEXT: [[TMP64:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[DOTOFFLOAD_PTRS4]], i32 0, i32 0			// CHECK-NOUSE-I386-NEXT: [[TMP64:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[DOTOFFLOAD_PTRS4]], i32 0, i32 0
	// CHECK-NOUSE-I386-NEXT: [[TMP65:%.]] = bitcast i8* [[TMP64]] to i32**			// CHECK-NOUSE-I386-NEXT: [[TMP65:%.]] = bitcast i8* [[TMP64]] to i32**
	// CHECK-NOUSE-I386-NEXT: store i32* [[A]], i32** [[TMP65]], align 4			// CHECK-NOUSE-I386-NEXT: store i32* [[A]], i32** [[TMP65]], align 4
	// CHECK-NOUSE-I386-NEXT: [[TMP66:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[DOTOFFLOAD_MAPPERS5]], i32 0, i32 0			// CHECK-NOUSE-I386-NEXT: [[TMP66:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[DOTOFFLOAD_MAPPERS5]], i32 0, i32 0
	// CHECK-NOUSE-I386-NEXT: store i8* null, i8** [[TMP66]], align 4			// CHECK-NOUSE-I386-NEXT: store i8* null, i8** [[TMP66]], align 4
	// CHECK-NOUSE-I386-NEXT: [[TMP67:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 0			// CHECK-NOUSE-I386-NEXT: [[TMP67:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 0
	// CHECK-NOUSE-I386-NEXT: [[TMP68:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[DOTOFFLOAD_PTRS4]], i32 0, i32 0			// CHECK-NOUSE-I386-NEXT: [[TMP68:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[DOTOFFLOAD_PTRS4]], i32 0, i32 0
	// CHECK-NOUSE-I386-NEXT: [[TMP69:%.]] = call i32 @__tgt_target_mapper(%struct.ident_t @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z20explicit_maps_singlei_l668.region_id, i32 1, i8 [[TMP67]], i8 [[TMP68]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.1, i32 0, i32 0), i8 null, i8 null)			// CHECK-NOUSE-I386-NEXT: [[TMP69:%.]] = call i32 @__tgt_target_mapper(%struct.ident_t @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z20explicit_maps_singlei_l716.region_id, i32 1, i8 [[TMP67]], i8 [[TMP68]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.1, i32 0, i32 0), i8 null, i8 null)
	// CHECK-NOUSE-I386-NEXT: [[TMP70:%.*]] = icmp ne i32 [[TMP69]], 0			// CHECK-NOUSE-I386-NEXT: [[TMP70:%.*]] = icmp ne i32 [[TMP69]], 0
	// CHECK-NOUSE-I386-NEXT: br i1 [[TMP70]], label [[OMP_OFFLOAD_FAILED6:%.]], label [[OMP_OFFLOAD_CONT7:%.]]			// CHECK-NOUSE-I386-NEXT: br i1 [[TMP70]], label [[OMP_OFFLOAD_FAILED6:%.]], label [[OMP_OFFLOAD_CONT7:%.]]
	// CHECK-NOUSE-I386: omp_offload.failed6:			// CHECK-NOUSE-I386: omp_offload.failed6:
	// CHECK-NOUSE-I386-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z20explicit_maps_singlei_l668() #[[ATTR2]]			// CHECK-NOUSE-I386-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z20explicit_maps_singlei_l716() #[[ATTR2]]
	// CHECK-NOUSE-I386-NEXT: br label [[OMP_OFFLOAD_CONT7]]			// CHECK-NOUSE-I386-NEXT: br label [[OMP_OFFLOAD_CONT7]]
	// CHECK-NOUSE-I386: omp_offload.cont7:			// CHECK-NOUSE-I386: omp_offload.cont7:
	// CHECK-NOUSE-I386-NEXT: ret void			// CHECK-NOUSE-I386-NEXT: ret void
	//			//
	void explicit_maps_single(int ii) {			void explicit_maps_single(int ii) {

	// Map of a scalar.			// Map of a scalar.
	int a = ii;			int a = ii;
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	// CHECK-USE-PPC64LE-NEXT: store i32* [[J]], i32** [[TMP22]], align 8			// CHECK-USE-PPC64LE-NEXT: store i32* [[J]], i32** [[TMP22]], align 8
	// CHECK-USE-PPC64LE-NEXT: [[TMP23:%.]] = getelementptr inbounds [3 x i64], [3 x i64] [[DOTOFFLOAD_SIZES]], i32 0, i32 2			// CHECK-USE-PPC64LE-NEXT: [[TMP23:%.]] = getelementptr inbounds [3 x i64], [3 x i64] [[DOTOFFLOAD_SIZES]], i32 0, i32 2
	// CHECK-USE-PPC64LE-NEXT: store i64 4, i64* [[TMP23]], align 8			// CHECK-USE-PPC64LE-NEXT: store i64 4, i64* [[TMP23]], align 8
	// CHECK-USE-PPC64LE-NEXT: [[TMP24:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2			// CHECK-USE-PPC64LE-NEXT: [[TMP24:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
	// CHECK-USE-PPC64LE-NEXT: store i8* null, i8** [[TMP24]], align 8			// CHECK-USE-PPC64LE-NEXT: store i8* null, i8** [[TMP24]], align 8
	// CHECK-USE-PPC64LE-NEXT: [[TMP25:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0			// CHECK-USE-PPC64LE-NEXT: [[TMP25:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
	// CHECK-USE-PPC64LE-NEXT: [[TMP26:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[DOTOFFLOAD_PTRS]], i32 0, i32 0			// CHECK-USE-PPC64LE-NEXT: [[TMP26:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[DOTOFFLOAD_PTRS]], i32 0, i32 0
	// CHECK-USE-PPC64LE-NEXT: [[TMP27:%.]] = getelementptr inbounds [3 x i64], [3 x i64] [[DOTOFFLOAD_SIZES]], i32 0, i32 0			// CHECK-USE-PPC64LE-NEXT: [[TMP27:%.]] = getelementptr inbounds [3 x i64], [3 x i64] [[DOTOFFLOAD_SIZES]], i32 0, i32 0
	// CHECK-USE-PPC64LE-NEXT: [[TMP28:%.]] = call i32 @__tgt_target_mapper(%struct.ident_t @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2ST20test_present_membersEv_l919.region_id, i32 3, i8 [[TMP25]], i8 [[TMP26]], i64* [[TMP27]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.2, i32 0, i32 0), i8 null, i8 null)			// CHECK-USE-PPC64LE-NEXT: [[TMP28:%.]] = call i32 @__tgt_target_mapper(%struct.ident_t @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2ST20test_present_membersEv_l967.region_id, i32 3, i8 [[TMP25]], i8 [[TMP26]], i64* [[TMP27]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.2, i32 0, i32 0), i8 null, i8 null)
	// CHECK-USE-PPC64LE-NEXT: [[TMP29:%.*]] = icmp ne i32 [[TMP28]], 0			// CHECK-USE-PPC64LE-NEXT: [[TMP29:%.*]] = icmp ne i32 [[TMP28]], 0
	// CHECK-USE-PPC64LE-NEXT: br i1 [[TMP29]], label [[OMP_OFFLOAD_FAILED:%.]], label [[OMP_OFFLOAD_CONT:%.]]			// CHECK-USE-PPC64LE-NEXT: br i1 [[TMP29]], label [[OMP_OFFLOAD_FAILED:%.]], label [[OMP_OFFLOAD_CONT:%.]]
	// CHECK-USE-PPC64LE: omp_offload.failed:			// CHECK-USE-PPC64LE: omp_offload.failed:
	// CHECK-USE-PPC64LE-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2ST20test_present_membersEv_l919(%struct.ST* [[THIS1]]) #[[ATTR2]]			// CHECK-USE-PPC64LE-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2ST20test_present_membersEv_l967(%struct.ST* [[THIS1]]) #[[ATTR2]]
	// CHECK-USE-PPC64LE-NEXT: br label [[OMP_OFFLOAD_CONT]]			// CHECK-USE-PPC64LE-NEXT: br label [[OMP_OFFLOAD_CONT]]
	// CHECK-USE-PPC64LE: omp_offload.cont:			// CHECK-USE-PPC64LE: omp_offload.cont:
	// CHECK-USE-PPC64LE-NEXT: ret void			// CHECK-USE-PPC64LE-NEXT: ret void
	//			//
	// CHECK-USE-I386-LABEL: @_ZN2ST20test_present_membersEv(			// CHECK-USE-I386-LABEL: @_ZN2ST20test_present_membersEv(
	// CHECK-USE-I386-NEXT: entry:			// CHECK-USE-I386-NEXT: entry:
	// CHECK-USE-I386-NEXT: [[THIS_ADDR:%.]] = alloca %struct.ST, align 4			// CHECK-USE-I386-NEXT: [[THIS_ADDR:%.]] = alloca %struct.ST, align 4
	// CHECK-USE-I386-NEXT: [[DOTOFFLOAD_BASEPTRS:%.]] = alloca [3 x i8], align 4			// CHECK-USE-I386-NEXT: [[DOTOFFLOAD_BASEPTRS:%.]] = alloca [3 x i8], align 4
	Show All 39 Lines
	// CHECK-USE-I386-NEXT: store i32* [[J]], i32** [[TMP22]], align 4			// CHECK-USE-I386-NEXT: store i32* [[J]], i32** [[TMP22]], align 4
	// CHECK-USE-I386-NEXT: [[TMP23:%.]] = getelementptr inbounds [3 x i64], [3 x i64] [[DOTOFFLOAD_SIZES]], i32 0, i32 2			// CHECK-USE-I386-NEXT: [[TMP23:%.]] = getelementptr inbounds [3 x i64], [3 x i64] [[DOTOFFLOAD_SIZES]], i32 0, i32 2
	// CHECK-USE-I386-NEXT: store i64 4, i64* [[TMP23]], align 4			// CHECK-USE-I386-NEXT: store i64 4, i64* [[TMP23]], align 4
	// CHECK-USE-I386-NEXT: [[TMP24:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2			// CHECK-USE-I386-NEXT: [[TMP24:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
	// CHECK-USE-I386-NEXT: store i8* null, i8** [[TMP24]], align 4			// CHECK-USE-I386-NEXT: store i8* null, i8** [[TMP24]], align 4
	// CHECK-USE-I386-NEXT: [[TMP25:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0			// CHECK-USE-I386-NEXT: [[TMP25:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
	// CHECK-USE-I386-NEXT: [[TMP26:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[DOTOFFLOAD_PTRS]], i32 0, i32 0			// CHECK-USE-I386-NEXT: [[TMP26:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[DOTOFFLOAD_PTRS]], i32 0, i32 0
	// CHECK-USE-I386-NEXT: [[TMP27:%.]] = getelementptr inbounds [3 x i64], [3 x i64] [[DOTOFFLOAD_SIZES]], i32 0, i32 0			// CHECK-USE-I386-NEXT: [[TMP27:%.]] = getelementptr inbounds [3 x i64], [3 x i64] [[DOTOFFLOAD_SIZES]], i32 0, i32 0
	// CHECK-USE-I386-NEXT: [[TMP28:%.]] = call i32 @__tgt_target_mapper(%struct.ident_t @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2ST20test_present_membersEv_l919.region_id, i32 3, i8 [[TMP25]], i8 [[TMP26]], i64* [[TMP27]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.2, i32 0, i32 0), i8 null, i8 null)			// CHECK-USE-I386-NEXT: [[TMP28:%.]] = call i32 @__tgt_target_mapper(%struct.ident_t @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2ST20test_present_membersEv_l967.region_id, i32 3, i8 [[TMP25]], i8 [[TMP26]], i64* [[TMP27]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.2, i32 0, i32 0), i8 null, i8 null)
	// CHECK-USE-I386-NEXT: [[TMP29:%.*]] = icmp ne i32 [[TMP28]], 0			// CHECK-USE-I386-NEXT: [[TMP29:%.*]] = icmp ne i32 [[TMP28]], 0
	// CHECK-USE-I386-NEXT: br i1 [[TMP29]], label [[OMP_OFFLOAD_FAILED:%.]], label [[OMP_OFFLOAD_CONT:%.]]			// CHECK-USE-I386-NEXT: br i1 [[TMP29]], label [[OMP_OFFLOAD_FAILED:%.]], label [[OMP_OFFLOAD_CONT:%.]]
	// CHECK-USE-I386: omp_offload.failed:			// CHECK-USE-I386: omp_offload.failed:
	// CHECK-USE-I386-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2ST20test_present_membersEv_l919(%struct.ST* [[THIS1]]) #[[ATTR2]]			// CHECK-USE-I386-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2ST20test_present_membersEv_l967(%struct.ST* [[THIS1]]) #[[ATTR2]]
	// CHECK-USE-I386-NEXT: br label [[OMP_OFFLOAD_CONT]]			// CHECK-USE-I386-NEXT: br label [[OMP_OFFLOAD_CONT]]
	// CHECK-USE-I386: omp_offload.cont:			// CHECK-USE-I386: omp_offload.cont:
	// CHECK-USE-I386-NEXT: ret void			// CHECK-USE-I386-NEXT: ret void
	//			//
	// CHECK-NOUSE-PPC64LE-LABEL: @_ZN2ST20test_present_membersEv(			// CHECK-NOUSE-PPC64LE-LABEL: @_ZN2ST20test_present_membersEv(
	// CHECK-NOUSE-PPC64LE-NEXT: entry:			// CHECK-NOUSE-PPC64LE-NEXT: entry:
	// CHECK-NOUSE-PPC64LE-NEXT: [[THIS_ADDR:%.]] = alloca %struct.ST, align 8			// CHECK-NOUSE-PPC64LE-NEXT: [[THIS_ADDR:%.]] = alloca %struct.ST, align 8
	// CHECK-NOUSE-PPC64LE-NEXT: [[DOTOFFLOAD_BASEPTRS:%.]] = alloca [3 x i8], align 8			// CHECK-NOUSE-PPC64LE-NEXT: [[DOTOFFLOAD_BASEPTRS:%.]] = alloca [3 x i8], align 8
	Show All 39 Lines
	// CHECK-NOUSE-PPC64LE-NEXT: store i32* [[J]], i32** [[TMP22]], align 8			// CHECK-NOUSE-PPC64LE-NEXT: store i32* [[J]], i32** [[TMP22]], align 8
	// CHECK-NOUSE-PPC64LE-NEXT: [[TMP23:%.]] = getelementptr inbounds [3 x i64], [3 x i64] [[DOTOFFLOAD_SIZES]], i32 0, i32 2			// CHECK-NOUSE-PPC64LE-NEXT: [[TMP23:%.]] = getelementptr inbounds [3 x i64], [3 x i64] [[DOTOFFLOAD_SIZES]], i32 0, i32 2
	// CHECK-NOUSE-PPC64LE-NEXT: store i64 4, i64* [[TMP23]], align 8			// CHECK-NOUSE-PPC64LE-NEXT: store i64 4, i64* [[TMP23]], align 8
	// CHECK-NOUSE-PPC64LE-NEXT: [[TMP24:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2			// CHECK-NOUSE-PPC64LE-NEXT: [[TMP24:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
	// CHECK-NOUSE-PPC64LE-NEXT: store i8* null, i8** [[TMP24]], align 8			// CHECK-NOUSE-PPC64LE-NEXT: store i8* null, i8** [[TMP24]], align 8
	// CHECK-NOUSE-PPC64LE-NEXT: [[TMP25:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0			// CHECK-NOUSE-PPC64LE-NEXT: [[TMP25:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
	// CHECK-NOUSE-PPC64LE-NEXT: [[TMP26:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[DOTOFFLOAD_PTRS]], i32 0, i32 0			// CHECK-NOUSE-PPC64LE-NEXT: [[TMP26:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[DOTOFFLOAD_PTRS]], i32 0, i32 0
	// CHECK-NOUSE-PPC64LE-NEXT: [[TMP27:%.]] = getelementptr inbounds [3 x i64], [3 x i64] [[DOTOFFLOAD_SIZES]], i32 0, i32 0			// CHECK-NOUSE-PPC64LE-NEXT: [[TMP27:%.]] = getelementptr inbounds [3 x i64], [3 x i64] [[DOTOFFLOAD_SIZES]], i32 0, i32 0
	// CHECK-NOUSE-PPC64LE-NEXT: [[TMP28:%.]] = call i32 @__tgt_target_mapper(%struct.ident_t @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2ST20test_present_membersEv_l919.region_id, i32 3, i8 [[TMP25]], i8 [[TMP26]], i64* [[TMP27]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.2, i32 0, i32 0), i8 null, i8 null)			// CHECK-NOUSE-PPC64LE-NEXT: [[TMP28:%.]] = call i32 @__tgt_target_mapper(%struct.ident_t @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2ST20test_present_membersEv_l967.region_id, i32 3, i8 [[TMP25]], i8 [[TMP26]], i64* [[TMP27]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.2, i32 0, i32 0), i8 null, i8 null)
	// CHECK-NOUSE-PPC64LE-NEXT: [[TMP29:%.*]] = icmp ne i32 [[TMP28]], 0			// CHECK-NOUSE-PPC64LE-NEXT: [[TMP29:%.*]] = icmp ne i32 [[TMP28]], 0
	// CHECK-NOUSE-PPC64LE-NEXT: br i1 [[TMP29]], label [[OMP_OFFLOAD_FAILED:%.]], label [[OMP_OFFLOAD_CONT:%.]]			// CHECK-NOUSE-PPC64LE-NEXT: br i1 [[TMP29]], label [[OMP_OFFLOAD_FAILED:%.]], label [[OMP_OFFLOAD_CONT:%.]]
	// CHECK-NOUSE-PPC64LE: omp_offload.failed:			// CHECK-NOUSE-PPC64LE: omp_offload.failed:
	// CHECK-NOUSE-PPC64LE-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2ST20test_present_membersEv_l919() #[[ATTR2]]			// CHECK-NOUSE-PPC64LE-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2ST20test_present_membersEv_l967() #[[ATTR2]]
	// CHECK-NOUSE-PPC64LE-NEXT: br label [[OMP_OFFLOAD_CONT]]			// CHECK-NOUSE-PPC64LE-NEXT: br label [[OMP_OFFLOAD_CONT]]
	// CHECK-NOUSE-PPC64LE: omp_offload.cont:			// CHECK-NOUSE-PPC64LE: omp_offload.cont:
	// CHECK-NOUSE-PPC64LE-NEXT: ret void			// CHECK-NOUSE-PPC64LE-NEXT: ret void
	//			//
	// CHECK-NOUSE-I386-LABEL: @_ZN2ST20test_present_membersEv(			// CHECK-NOUSE-I386-LABEL: @_ZN2ST20test_present_membersEv(
	// CHECK-NOUSE-I386-NEXT: entry:			// CHECK-NOUSE-I386-NEXT: entry:
	// CHECK-NOUSE-I386-NEXT: [[THIS_ADDR:%.]] = alloca %struct.ST, align 4			// CHECK-NOUSE-I386-NEXT: [[THIS_ADDR:%.]] = alloca %struct.ST, align 4
	// CHECK-NOUSE-I386-NEXT: [[DOTOFFLOAD_BASEPTRS:%.]] = alloca [3 x i8], align 4			// CHECK-NOUSE-I386-NEXT: [[DOTOFFLOAD_BASEPTRS:%.]] = alloca [3 x i8], align 4
	Show All 39 Lines
	// CHECK-NOUSE-I386-NEXT: store i32* [[J]], i32** [[TMP22]], align 4			// CHECK-NOUSE-I386-NEXT: store i32* [[J]], i32** [[TMP22]], align 4
	// CHECK-NOUSE-I386-NEXT: [[TMP23:%.]] = getelementptr inbounds [3 x i64], [3 x i64] [[DOTOFFLOAD_SIZES]], i32 0, i32 2			// CHECK-NOUSE-I386-NEXT: [[TMP23:%.]] = getelementptr inbounds [3 x i64], [3 x i64] [[DOTOFFLOAD_SIZES]], i32 0, i32 2
	// CHECK-NOUSE-I386-NEXT: store i64 4, i64* [[TMP23]], align 4			// CHECK-NOUSE-I386-NEXT: store i64 4, i64* [[TMP23]], align 4
	// CHECK-NOUSE-I386-NEXT: [[TMP24:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2			// CHECK-NOUSE-I386-NEXT: [[TMP24:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
	// CHECK-NOUSE-I386-NEXT: store i8* null, i8** [[TMP24]], align 4			// CHECK-NOUSE-I386-NEXT: store i8* null, i8** [[TMP24]], align 4
	// CHECK-NOUSE-I386-NEXT: [[TMP25:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0			// CHECK-NOUSE-I386-NEXT: [[TMP25:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
	// CHECK-NOUSE-I386-NEXT: [[TMP26:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[DOTOFFLOAD_PTRS]], i32 0, i32 0			// CHECK-NOUSE-I386-NEXT: [[TMP26:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[DOTOFFLOAD_PTRS]], i32 0, i32 0
	// CHECK-NOUSE-I386-NEXT: [[TMP27:%.]] = getelementptr inbounds [3 x i64], [3 x i64] [[DOTOFFLOAD_SIZES]], i32 0, i32 0			// CHECK-NOUSE-I386-NEXT: [[TMP27:%.]] = getelementptr inbounds [3 x i64], [3 x i64] [[DOTOFFLOAD_SIZES]], i32 0, i32 0
	// CHECK-NOUSE-I386-NEXT: [[TMP28:%.]] = call i32 @__tgt_target_mapper(%struct.ident_t @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2ST20test_present_membersEv_l919.region_id, i32 3, i8 [[TMP25]], i8 [[TMP26]], i64* [[TMP27]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.2, i32 0, i32 0), i8 null, i8 null)			// CHECK-NOUSE-I386-NEXT: [[TMP28:%.]] = call i32 @__tgt_target_mapper(%struct.ident_t @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2ST20test_present_membersEv_l967.region_id, i32 3, i8 [[TMP25]], i8 [[TMP26]], i64* [[TMP27]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.2, i32 0, i32 0), i8 null, i8 null)
	// CHECK-NOUSE-I386-NEXT: [[TMP29:%.*]] = icmp ne i32 [[TMP28]], 0			// CHECK-NOUSE-I386-NEXT: [[TMP29:%.*]] = icmp ne i32 [[TMP28]], 0
	// CHECK-NOUSE-I386-NEXT: br i1 [[TMP29]], label [[OMP_OFFLOAD_FAILED:%.]], label [[OMP_OFFLOAD_CONT:%.]]			// CHECK-NOUSE-I386-NEXT: br i1 [[TMP29]], label [[OMP_OFFLOAD_FAILED:%.]], label [[OMP_OFFLOAD_CONT:%.]]
	// CHECK-NOUSE-I386: omp_offload.failed:			// CHECK-NOUSE-I386: omp_offload.failed:
	// CHECK-NOUSE-I386-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2ST20test_present_membersEv_l919() #[[ATTR2]]			// CHECK-NOUSE-I386-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2ST20test_present_membersEv_l967() #[[ATTR2]]
	// CHECK-NOUSE-I386-NEXT: br label [[OMP_OFFLOAD_CONT]]			// CHECK-NOUSE-I386-NEXT: br label [[OMP_OFFLOAD_CONT]]
	// CHECK-NOUSE-I386: omp_offload.cont:			// CHECK-NOUSE-I386: omp_offload.cont:
	// CHECK-NOUSE-I386-NEXT: ret void			// CHECK-NOUSE-I386-NEXT: ret void
	//			//
	void ST::test_present_members() {			void ST::test_present_members() {
	// Make sure the struct picks up ompx_hold even if another element of the			// Make sure the struct picks up ompx_hold even if another element of the
	// struct doesn't have ompx_hold.			// struct doesn't have ompx_hold.
	#pragma omp target map(tofrom : i) map(ompx_hold, tofrom : j)			#pragma omp target map(tofrom : i) map(ompx_hold, tofrom : j)
	{			{
	#ifdef USE			#ifdef USE
	i++;			i++;
	j++;			j++;
	#endif			#endif
	}			}
	}			}

	#endif			#endif
				//.
				// CHECK-USE-PPC64LE: attributes #0 = { mustprogress noinline nounwind optnone "frame-pointer"="none" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="-altivec,-bpermd,-crypto,-direct-move,-extdiv,-htm,-isa-v206-instructions,-isa-v207-instructions,-isa-v30-instructions,-power8-vector,-power9-vector,-privileged,-rop-protect,-spe,-vsx" }
				// CHECK-USE-PPC64LE: attributes #1 = { noinline norecurse nounwind optnone "frame-pointer"="none" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="-altivec,-bpermd,-crypto,-direct-move,-extdiv,-htm,-isa-v206-instructions,-isa-v207-instructions,-isa-v30-instructions,-power8-vector,-power9-vector,-privileged,-rop-protect,-spe,-vsx" }
				// CHECK-USE-PPC64LE: attributes #2 = { nounwind }
				// CHECK-USE-PPC64LE: attributes #3 = { noinline nounwind "frame-pointer"="none" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="-altivec,-bpermd,-crypto,-direct-move,-extdiv,-htm,-isa-v206-instructions,-isa-v207-instructions,-isa-v30-instructions,-power8-vector,-power9-vector,-privileged,-rop-protect,-spe,-vsx" }
				//.
				// CHECK-USE-I386: attributes #0 = { mustprogress noinline nounwind optnone "frame-pointer"="none" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+x87" }
				// CHECK-USE-I386: attributes #1 = { noinline norecurse nounwind optnone "frame-pointer"="none" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+x87" }
				// CHECK-USE-I386: attributes #2 = { nounwind }
				// CHECK-USE-I386: attributes #3 = { noinline nounwind "frame-pointer"="none" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+x87" }
				//.
				// CHECK-NOUSE-PPC64LE: attributes #0 = { mustprogress noinline nounwind optnone "frame-pointer"="none" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="-altivec,-bpermd,-crypto,-direct-move,-extdiv,-htm,-isa-v206-instructions,-isa-v207-instructions,-isa-v30-instructions,-power8-vector,-power9-vector,-privileged,-rop-protect,-spe,-vsx" }
				// CHECK-NOUSE-PPC64LE: attributes #1 = { noinline norecurse nounwind optnone "frame-pointer"="none" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="-altivec,-bpermd,-crypto,-direct-move,-extdiv,-htm,-isa-v206-instructions,-isa-v207-instructions,-isa-v30-instructions,-power8-vector,-power9-vector,-privileged,-rop-protect,-spe,-vsx" }
				// CHECK-NOUSE-PPC64LE: attributes #2 = { nounwind }
				// CHECK-NOUSE-PPC64LE: attributes #3 = { noinline nounwind "frame-pointer"="none" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="-altivec,-bpermd,-crypto,-direct-move,-extdiv,-htm,-isa-v206-instructions,-isa-v207-instructions,-isa-v30-instructions,-power8-vector,-power9-vector,-privileged,-rop-protect,-spe,-vsx" }
				//.
				// CHECK-NOUSE-I386: attributes #0 = { mustprogress noinline nounwind optnone "frame-pointer"="none" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+x87" }
				// CHECK-NOUSE-I386: attributes #1 = { noinline norecurse nounwind optnone "frame-pointer"="none" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+x87" }
				// CHECK-NOUSE-I386: attributes #2 = { nounwind }
				// CHECK-NOUSE-I386: attributes #3 = { noinline nounwind "frame-pointer"="none" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+x87" }
				//.
				// CHECK-USE-PPC64LE: !0 = !{i32 0, i32 43, i32 16713566, !"_Z20explicit_maps_singlei", i32 702, i32 0}
				// CHECK-USE-PPC64LE: !1 = !{i32 0, i32 43, i32 16713566, !"_Z20explicit_maps_singlei", i32 716, i32 1}
				// CHECK-USE-PPC64LE: !2 = !{i32 0, i32 43, i32 16713566, !"_ZN2ST20test_present_membersEv", i32 967, i32 2}
				// CHECK-USE-PPC64LE: !3 = !{i32 1, !"wchar_size", i32 4}
				// CHECK-USE-PPC64LE: !4 = !{i32 7, !"openmp", i32 50}
				// CHECK-USE-PPC64LE: !5 = !{!"clang version 14.0.0"}
				//.
				// CHECK-USE-I386: !0 = !{i32 0, i32 43, i32 16713566, !"_Z20explicit_maps_singlei", i32 702, i32 0}
				// CHECK-USE-I386: !1 = !{i32 0, i32 43, i32 16713566, !"_Z20explicit_maps_singlei", i32 716, i32 1}
				// CHECK-USE-I386: !2 = !{i32 0, i32 43, i32 16713566, !"_ZN2ST20test_present_membersEv", i32 967, i32 2}
				// CHECK-USE-I386: !3 = !{i32 1, !"NumRegisterParameters", i32 0}
				// CHECK-USE-I386: !4 = !{i32 1, !"wchar_size", i32 4}
				// CHECK-USE-I386: !5 = !{i32 7, !"openmp", i32 50}
				// CHECK-USE-I386: !6 = !{!"clang version 14.0.0"}
				//.
				// CHECK-NOUSE-PPC64LE: !0 = !{i32 0, i32 43, i32 16713566, !"_Z20explicit_maps_singlei", i32 702, i32 0}
				// CHECK-NOUSE-PPC64LE: !1 = !{i32 0, i32 43, i32 16713566, !"_Z20explicit_maps_singlei", i32 716, i32 1}
				// CHECK-NOUSE-PPC64LE: !2 = !{i32 0, i32 43, i32 16713566, !"_ZN2ST20test_present_membersEv", i32 967, i32 2}
				// CHECK-NOUSE-PPC64LE: !3 = !{i32 1, !"wchar_size", i32 4}
				// CHECK-NOUSE-PPC64LE: !4 = !{i32 7, !"openmp", i32 50}
				// CHECK-NOUSE-PPC64LE: !5 = !{!"clang version 14.0.0"}
				//.
				// CHECK-NOUSE-I386: !0 = !{i32 0, i32 43, i32 16713566, !"_Z20explicit_maps_singlei", i32 702, i32 0}
				// CHECK-NOUSE-I386: !1 = !{i32 0, i32 43, i32 16713566, !"_Z20explicit_maps_singlei", i32 716, i32 1}
				// CHECK-NOUSE-I386: !2 = !{i32 0, i32 43, i32 16713566, !"_ZN2ST20test_present_membersEv", i32 967, i32 2}
				// CHECK-NOUSE-I386: !3 = !{i32 1, !"NumRegisterParameters", i32 0}
				// CHECK-NOUSE-I386: !4 = !{i32 1, !"wchar_size", i32 4}
				// CHECK-NOUSE-I386: !5 = !{i32 7, !"openmp", i32 50}
				// CHECK-NOUSE-I386: !6 = !{!"clang version 14.0.0"}
				//.

clang/test/OpenMP/target_parallel_debug_codegen.cpp

	Show First 20 Lines • Show All 89 Lines • ▼ Show 20 Lines
	// CHECK1-NEXT: [[TMP2:%.]] = load [10 x [10 x [10 x i32]]], [10 x [10 x [10 x i32]]]** [[TMP]], align 8, !dbg [[DBG47]]			// CHECK1-NEXT: [[TMP2:%.]] = load [10 x [10 x [10 x i32]]], [10 x [10 x [10 x i32]]]** [[TMP]], align 8, !dbg [[DBG47]]
	// CHECK1-NEXT: [[TMP3:%.]] = load [10 x [10 x i32]], [10 x [10 x i32]]** [[B_ADDR]], align 8, !dbg [[DBG47]]			// CHECK1-NEXT: [[TMP3:%.]] = load [10 x [10 x i32]], [10 x [10 x i32]]** [[B_ADDR]], align 8, !dbg [[DBG47]]
	// CHECK1-NEXT: store [10 x [10 x i32]]* [[TMP3]], [10 x [10 x i32]]** [[_TMP1]], align 8, !dbg [[DBG47]]			// CHECK1-NEXT: store [10 x [10 x i32]]* [[TMP3]], [10 x [10 x i32]]** [[_TMP1]], align 8, !dbg [[DBG47]]
	// CHECK1-NEXT: [[TMP4:%.]] = load [10 x [10 x i32]], [10 x [10 x i32]]** [[_TMP1]], align 8, !dbg [[DBG47]]			// CHECK1-NEXT: [[TMP4:%.]] = load [10 x [10 x i32]], [10 x [10 x i32]]** [[_TMP1]], align 8, !dbg [[DBG47]]
	// CHECK1-NEXT: [[TMP5:%.]] = load i8 addrspace(1), i8 addrspace(1)** [[BB_ADDR]], align 8, !dbg [[DBG47]]			// CHECK1-NEXT: [[TMP5:%.]] = load i8 addrspace(1), i8 addrspace(1)** [[BB_ADDR]], align 8, !dbg [[DBG47]]
	// CHECK1-NEXT: [[TMP6:%.]] = addrspacecast i8 addrspace(1) [[TMP5]] to i8*, !dbg [[DBG47]]			// CHECK1-NEXT: [[TMP6:%.]] = addrspacecast i8 addrspace(1) [[TMP5]] to i8*, !dbg [[DBG47]]
	// CHECK1-NEXT: store i8* [[TMP6]], i8** [[_TMP2]], align 8, !dbg [[DBG47]]			// CHECK1-NEXT: store i8* [[TMP6]], i8** [[_TMP2]], align 8, !dbg [[DBG47]]
	// CHECK1-NEXT: [[TMP7:%.]] = load i8, i8** [[_TMP2]], align 8, !dbg [[DBG47]]			// CHECK1-NEXT: [[TMP7:%.]] = load i8, i8** [[_TMP2]], align 8, !dbg [[DBG47]]
	// CHECK1-NEXT: [[TMP8:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1:[0-9]+]], i8 2, i1 false, i1 true), !dbg [[DBG47]]			// CHECK1-NEXT: [[TMP8:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l23_debug___kernel_info, i1 true), !dbg [[DBG47]]
	// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP8]], -1, !dbg [[DBG47]]			// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP8]], -1, !dbg [[DBG47]]
	// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]], !dbg [[DBG47]]			// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]], !dbg [[DBG47]]
	// CHECK1: user_code.entry:			// CHECK1: user_code.entry:
	// CHECK1-NEXT: [[TMP9:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB3:[0-9]+]])			// CHECK1-NEXT: [[TMP9:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB3:[0-9]+]])
	// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[A_ADDR]], align 4, !dbg [[DBG48:![0-9]+]]			// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[A_ADDR]], align 4, !dbg [[DBG48:![0-9]+]]
	// CHECK1-NEXT: [[CONV:%.]] = bitcast i64 [[A_CASTED]] to i32*, !dbg [[DBG48]]			// CHECK1-NEXT: [[CONV:%.]] = bitcast i64 [[A_CASTED]] to i32*, !dbg [[DBG48]]
	// CHECK1-NEXT: store i32 [[TMP10]], i32* [[CONV]], align 4, !dbg [[DBG48]]			// CHECK1-NEXT: store i32 [[TMP10]], i32* [[CONV]], align 4, !dbg [[DBG48]]
	// CHECK1-NEXT: [[TMP11:%.]] = load i64, i64 [[A_CASTED]], align 8, !dbg [[DBG48]]			// CHECK1-NEXT: [[TMP11:%.]] = load i64, i64 [[A_CASTED]], align 8, !dbg [[DBG48]]
	// CHECK1-NEXT: [[TMP12:%.]] = getelementptr inbounds [4 x i8], [4 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 0, !dbg [[DBG48]]			// CHECK1-NEXT: [[TMP12:%.]] = getelementptr inbounds [4 x i8], [4 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 0, !dbg [[DBG48]]
	// CHECK1-NEXT: [[TMP13:%.]] = bitcast [10 x [10 x [10 x i32]]] [[TMP2]] to i8*, !dbg [[DBG48]]			// CHECK1-NEXT: [[TMP13:%.]] = bitcast [10 x [10 x [10 x i32]]] [[TMP2]] to i8*, !dbg [[DBG48]]
	// CHECK1-NEXT: store i8* [[TMP13]], i8** [[TMP12]], align 8, !dbg [[DBG48]]			// CHECK1-NEXT: store i8* [[TMP13]], i8** [[TMP12]], align 8, !dbg [[DBG48]]
	// CHECK1-NEXT: [[TMP14:%.]] = getelementptr inbounds [4 x i8], [4 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 1, !dbg [[DBG48]]			// CHECK1-NEXT: [[TMP14:%.]] = getelementptr inbounds [4 x i8], [4 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 1, !dbg [[DBG48]]
	// CHECK1-NEXT: [[TMP15:%.]] = inttoptr i64 [[TMP11]] to i8, !dbg [[DBG48]]			// CHECK1-NEXT: [[TMP15:%.]] = inttoptr i64 [[TMP11]] to i8, !dbg [[DBG48]]
	// CHECK1-NEXT: store i8* [[TMP15]], i8** [[TMP14]], align 8, !dbg [[DBG48]]			// CHECK1-NEXT: store i8* [[TMP15]], i8** [[TMP14]], align 8, !dbg [[DBG48]]
	// CHECK1-NEXT: [[TMP16:%.]] = getelementptr inbounds [4 x i8], [4 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 2, !dbg [[DBG48]]			// CHECK1-NEXT: [[TMP16:%.]] = getelementptr inbounds [4 x i8], [4 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 2, !dbg [[DBG48]]
	// CHECK1-NEXT: [[TMP17:%.]] = bitcast [10 x [10 x i32]] [[TMP4]] to i8*, !dbg [[DBG48]]			// CHECK1-NEXT: [[TMP17:%.]] = bitcast [10 x [10 x i32]] [[TMP4]] to i8*, !dbg [[DBG48]]
	// CHECK1-NEXT: store i8* [[TMP17]], i8** [[TMP16]], align 8, !dbg [[DBG48]]			// CHECK1-NEXT: store i8* [[TMP17]], i8** [[TMP16]], align 8, !dbg [[DBG48]]
	// CHECK1-NEXT: [[TMP18:%.]] = getelementptr inbounds [4 x i8], [4 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 3, !dbg [[DBG48]]			// CHECK1-NEXT: [[TMP18:%.]] = getelementptr inbounds [4 x i8], [4 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 3, !dbg [[DBG48]]
	// CHECK1-NEXT: store i8* [[TMP7]], i8** [[TMP18]], align 8, !dbg [[DBG48]]			// CHECK1-NEXT: store i8* [[TMP7]], i8** [[TMP18]], align 8, !dbg [[DBG48]]
	// CHECK1-NEXT: [[TMP19:%.]] = bitcast [4 x i8]* [[CAPTURED_VARS_ADDRS]] to i8**, !dbg [[DBG48]]			// CHECK1-NEXT: [[TMP19:%.]] = bitcast [4 x i8]* [[CAPTURED_VARS_ADDRS]] to i8**, !dbg [[DBG48]]
	// CHECK1-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB3]], i32 [[TMP9]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32, i32, [10 x [10 x [10 x i32]]], i64, [10 x [10 x i32]], i8) @__omp_outlined__ to i8), i8 null, i8** [[TMP19]], i64 4), !dbg [[DBG48]]			// CHECK1-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB3]], i32 [[TMP9]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32, i32, [10 x [10 x [10 x i32]]], i64, [10 x [10 x i32]], i8) @__omp_outlined__ to i8), i8 null, i8** [[TMP19]], i64 4), !dbg [[DBG48]]
	// CHECK1-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB5:[0-9]+]], i8 2, i1 true), !dbg [[DBG49:![0-9]+]]			// CHECK1-NEXT: call void @__kmpc_target_deinit(i1 true), !dbg [[DBG49:![0-9]+]]
	// CHECK1-NEXT: ret void, !dbg [[DBG51:![0-9]+]]			// CHECK1-NEXT: ret void, !dbg [[DBG51:![0-9]+]]
	// CHECK1: worker.exit:			// CHECK1: worker.exit:
	// CHECK1-NEXT: ret void, !dbg [[DBG47]]			// CHECK1-NEXT: ret void, !dbg [[DBG47]]
	//			//
	//			//
	// CHECK1-LABEL: define {{[^@]+}}@__omp_outlined___debug__			// CHECK1-LABEL: define {{[^@]+}}@__omp_outlined___debug__
	// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], [10 x [10 x [10 x i32]]] addrspace(1) noalias [[C:%.]], i32 [[A:%.]], [10 x [10 x i32]]* noalias [[B:%.]], i8 addrspace(1) noalias [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG52:![0-9]+]] {			// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], [10 x [10 x [10 x i32]]] addrspace(1) noalias [[C:%.]], i32 [[A:%.]], [10 x [10 x i32]]* noalias [[B:%.]], i8 addrspace(1) noalias [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG52:![0-9]+]] {
	// CHECK1-NEXT: entry:			// CHECK1-NEXT: entry:
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	// CHECK1-NEXT: [[TMP3:%.]] = load [10 x [10 x i32]] addrspace(1), [10 x [10 x i32]] addrspace(1)** [[B_ADDR]], align 8, !dbg [[DBG137]]			// CHECK1-NEXT: [[TMP3:%.]] = load [10 x [10 x i32]] addrspace(1), [10 x [10 x i32]] addrspace(1)** [[B_ADDR]], align 8, !dbg [[DBG137]]
	// CHECK1-NEXT: [[TMP4:%.]] = addrspacecast [10 x [10 x i32]] addrspace(1) [[TMP3]] to [10 x [10 x i32]]*, !dbg [[DBG137]]			// CHECK1-NEXT: [[TMP4:%.]] = addrspacecast [10 x [10 x i32]] addrspace(1) [[TMP3]] to [10 x [10 x i32]]*, !dbg [[DBG137]]
	// CHECK1-NEXT: store [10 x [10 x i32]]* [[TMP4]], [10 x [10 x i32]]** [[_TMP1]], align 8, !dbg [[DBG137]]			// CHECK1-NEXT: store [10 x [10 x i32]]* [[TMP4]], [10 x [10 x i32]]** [[_TMP1]], align 8, !dbg [[DBG137]]
	// CHECK1-NEXT: [[TMP5:%.]] = load [10 x [10 x i32]], [10 x [10 x i32]]** [[_TMP1]], align 8, !dbg [[DBG137]]			// CHECK1-NEXT: [[TMP5:%.]] = load [10 x [10 x i32]], [10 x [10 x i32]]** [[_TMP1]], align 8, !dbg [[DBG137]]
	// CHECK1-NEXT: [[TMP6:%.]] = load i8 addrspace(1), i8 addrspace(1)** [[BB_ADDR]], align 8, !dbg [[DBG137]]			// CHECK1-NEXT: [[TMP6:%.]] = load i8 addrspace(1), i8 addrspace(1)** [[BB_ADDR]], align 8, !dbg [[DBG137]]
	// CHECK1-NEXT: [[TMP7:%.]] = addrspacecast i8 addrspace(1) [[TMP6]] to i8*, !dbg [[DBG137]]			// CHECK1-NEXT: [[TMP7:%.]] = addrspacecast i8 addrspace(1) [[TMP6]] to i8*, !dbg [[DBG137]]
	// CHECK1-NEXT: store i8* [[TMP7]], i8** [[_TMP2]], align 8, !dbg [[DBG137]]			// CHECK1-NEXT: store i8* [[TMP7]], i8** [[_TMP2]], align 8, !dbg [[DBG137]]
	// CHECK1-NEXT: [[TMP8:%.]] = load i8, i8** [[_TMP2]], align 8, !dbg [[DBG137]]			// CHECK1-NEXT: [[TMP8:%.]] = load i8, i8** [[_TMP2]], align 8, !dbg [[DBG137]]
	// CHECK1-NEXT: [[TMP9:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB7:[0-9]+]], i8 2, i1 false, i1 true), !dbg [[DBG137]]			// CHECK1-NEXT: [[TMP9:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l37_debug___kernel_info, i1 true), !dbg [[DBG137]]
	// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP9]], -1, !dbg [[DBG137]]			// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP9]], -1, !dbg [[DBG137]]
	// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]], !dbg [[DBG137]]			// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]], !dbg [[DBG137]]
	// CHECK1: user_code.entry:			// CHECK1: user_code.entry:
	// CHECK1-NEXT: [[TMP10:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB9:[0-9]+]])			// CHECK1-NEXT: [[TMP10:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB7:[0-9]+]])
	// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[A_ADDR]], align 4, !dbg [[DBG138:![0-9]+]]			// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[A_ADDR]], align 4, !dbg [[DBG138:![0-9]+]]
	// CHECK1-NEXT: [[CONV:%.]] = bitcast i64 [[A_CASTED]] to i32*, !dbg [[DBG138]]			// CHECK1-NEXT: [[CONV:%.]] = bitcast i64 [[A_CASTED]] to i32*, !dbg [[DBG138]]
	// CHECK1-NEXT: store i32 [[TMP11]], i32* [[CONV]], align 4, !dbg [[DBG138]]			// CHECK1-NEXT: store i32 [[TMP11]], i32* [[CONV]], align 4, !dbg [[DBG138]]
	// CHECK1-NEXT: [[TMP12:%.]] = load i64, i64 [[A_CASTED]], align 8, !dbg [[DBG138]]			// CHECK1-NEXT: [[TMP12:%.]] = load i64, i64 [[A_CASTED]], align 8, !dbg [[DBG138]]
	// CHECK1-NEXT: [[TMP13:%.]] = getelementptr inbounds [4 x i8], [4 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 0, !dbg [[DBG138]]			// CHECK1-NEXT: [[TMP13:%.]] = getelementptr inbounds [4 x i8], [4 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 0, !dbg [[DBG138]]
	// CHECK1-NEXT: [[TMP14:%.]] = bitcast [10 x [10 x [10 x i32]]] [[TMP2]] to i8*, !dbg [[DBG138]]			// CHECK1-NEXT: [[TMP14:%.]] = bitcast [10 x [10 x [10 x i32]]] [[TMP2]] to i8*, !dbg [[DBG138]]
	// CHECK1-NEXT: store i8* [[TMP14]], i8** [[TMP13]], align 8, !dbg [[DBG138]]			// CHECK1-NEXT: store i8* [[TMP14]], i8** [[TMP13]], align 8, !dbg [[DBG138]]
	// CHECK1-NEXT: [[TMP15:%.]] = getelementptr inbounds [4 x i8], [4 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 1, !dbg [[DBG138]]			// CHECK1-NEXT: [[TMP15:%.]] = getelementptr inbounds [4 x i8], [4 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 1, !dbg [[DBG138]]
	// CHECK1-NEXT: [[TMP16:%.]] = inttoptr i64 [[TMP12]] to i8, !dbg [[DBG138]]			// CHECK1-NEXT: [[TMP16:%.]] = inttoptr i64 [[TMP12]] to i8, !dbg [[DBG138]]
	// CHECK1-NEXT: store i8* [[TMP16]], i8** [[TMP15]], align 8, !dbg [[DBG138]]			// CHECK1-NEXT: store i8* [[TMP16]], i8** [[TMP15]], align 8, !dbg [[DBG138]]
	// CHECK1-NEXT: [[TMP17:%.]] = getelementptr inbounds [4 x i8], [4 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 2, !dbg [[DBG138]]			// CHECK1-NEXT: [[TMP17:%.]] = getelementptr inbounds [4 x i8], [4 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 2, !dbg [[DBG138]]
	// CHECK1-NEXT: [[TMP18:%.]] = bitcast [10 x [10 x i32]] [[TMP5]] to i8*, !dbg [[DBG138]]			// CHECK1-NEXT: [[TMP18:%.]] = bitcast [10 x [10 x i32]] [[TMP5]] to i8*, !dbg [[DBG138]]
	// CHECK1-NEXT: store i8* [[TMP18]], i8** [[TMP17]], align 8, !dbg [[DBG138]]			// CHECK1-NEXT: store i8* [[TMP18]], i8** [[TMP17]], align 8, !dbg [[DBG138]]
	// CHECK1-NEXT: [[TMP19:%.]] = getelementptr inbounds [4 x i8], [4 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 3, !dbg [[DBG138]]			// CHECK1-NEXT: [[TMP19:%.]] = getelementptr inbounds [4 x i8], [4 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 3, !dbg [[DBG138]]
	// CHECK1-NEXT: store i8* [[TMP8]], i8** [[TMP19]], align 8, !dbg [[DBG138]]			// CHECK1-NEXT: store i8* [[TMP8]], i8** [[TMP19]], align 8, !dbg [[DBG138]]
	// CHECK1-NEXT: [[TMP20:%.]] = bitcast [4 x i8]* [[CAPTURED_VARS_ADDRS]] to i8**, !dbg [[DBG138]]			// CHECK1-NEXT: [[TMP20:%.]] = bitcast [4 x i8]* [[CAPTURED_VARS_ADDRS]] to i8**, !dbg [[DBG138]]
	// CHECK1-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB9]], i32 [[TMP10]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32, i32, [10 x [10 x [10 x i32]]], i64, [10 x [10 x i32]], i8) @__omp_outlined__2 to i8), i8 null, i8** [[TMP20]], i64 4), !dbg [[DBG138]]			// CHECK1-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB7]], i32 [[TMP10]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32, i32, [10 x [10 x [10 x i32]]], i64, [10 x [10 x i32]], i8) @__omp_outlined__2 to i8), i8 null, i8** [[TMP20]], i64 4), !dbg [[DBG138]]
	// CHECK1-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB11:[0-9]+]], i8 2, i1 true), !dbg [[DBG139:![0-9]+]]			// CHECK1-NEXT: call void @__kmpc_target_deinit(i1 true), !dbg [[DBG139:![0-9]+]]
	// CHECK1-NEXT: ret void, !dbg [[DBG141:![0-9]+]]			// CHECK1-NEXT: ret void, !dbg [[DBG141:![0-9]+]]
	// CHECK1: worker.exit:			// CHECK1: worker.exit:
	// CHECK1-NEXT: ret void, !dbg [[DBG137]]			// CHECK1-NEXT: ret void, !dbg [[DBG137]]
	//			//
	//			//
	// CHECK1-LABEL: define {{[^@]+}}@__omp_outlined___debug__1			// CHECK1-LABEL: define {{[^@]+}}@__omp_outlined___debug__1
	// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], [10 x [10 x [10 x i32]]] addrspace(1) noalias [[C:%.]], i32 [[A:%.]], [10 x [10 x i32]] addrspace(1)* noalias [[B:%.]], i8 addrspace(1) noalias [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG142:![0-9]+]] {			// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], [10 x [10 x [10 x i32]]] addrspace(1) noalias [[C:%.]], i32 [[A:%.]], [10 x [10 x i32]] addrspace(1)* noalias [[B:%.]], i8 addrspace(1) noalias [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG142:![0-9]+]] {
	// CHECK1-NEXT: entry:			// CHECK1-NEXT: entry:
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	// CHECK1-NEXT: [[TMP6:%.]] = load [10 x [10 x i32]] addrspace(1), [10 x [10 x i32]] addrspace(1)** [[B_ADDR]], align 8, !dbg [[DBG212]]			// CHECK1-NEXT: [[TMP6:%.]] = load [10 x [10 x i32]] addrspace(1), [10 x [10 x i32]] addrspace(1)** [[B_ADDR]], align 8, !dbg [[DBG212]]
	// CHECK1-NEXT: [[TMP7:%.]] = addrspacecast [10 x [10 x i32]] addrspace(1) [[TMP6]] to [10 x [10 x i32]]*, !dbg [[DBG212]]			// CHECK1-NEXT: [[TMP7:%.]] = addrspacecast [10 x [10 x i32]] addrspace(1) [[TMP6]] to [10 x [10 x i32]]*, !dbg [[DBG212]]
	// CHECK1-NEXT: store [10 x [10 x i32]]* [[TMP7]], [10 x [10 x i32]]** [[_TMP2]], align 8, !dbg [[DBG212]]			// CHECK1-NEXT: store [10 x [10 x i32]]* [[TMP7]], [10 x [10 x i32]]** [[_TMP2]], align 8, !dbg [[DBG212]]
	// CHECK1-NEXT: [[TMP8:%.]] = load [10 x [10 x i32]], [10 x [10 x i32]]** [[_TMP2]], align 8, !dbg [[DBG212]]			// CHECK1-NEXT: [[TMP8:%.]] = load [10 x [10 x i32]], [10 x [10 x i32]]** [[_TMP2]], align 8, !dbg [[DBG212]]
	// CHECK1-NEXT: [[TMP9:%.]] = load i8 addrspace(1), i8 addrspace(1)** [[BB_ADDR]], align 8, !dbg [[DBG212]]			// CHECK1-NEXT: [[TMP9:%.]] = load i8 addrspace(1), i8 addrspace(1)** [[BB_ADDR]], align 8, !dbg [[DBG212]]
	// CHECK1-NEXT: [[TMP10:%.]] = addrspacecast i8 addrspace(1) [[TMP9]] to i8*, !dbg [[DBG212]]			// CHECK1-NEXT: [[TMP10:%.]] = addrspacecast i8 addrspace(1) [[TMP9]] to i8*, !dbg [[DBG212]]
	// CHECK1-NEXT: store i8* [[TMP10]], i8** [[_TMP3]], align 8, !dbg [[DBG212]]			// CHECK1-NEXT: store i8* [[TMP10]], i8** [[_TMP3]], align 8, !dbg [[DBG212]]
	// CHECK1-NEXT: [[TMP11:%.]] = load i8, i8** [[_TMP3]], align 8, !dbg [[DBG212]]			// CHECK1-NEXT: [[TMP11:%.]] = load i8, i8** [[_TMP3]], align 8, !dbg [[DBG212]]
	// CHECK1-NEXT: [[TMP12:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB13:[0-9]+]], i8 2, i1 false, i1 true), !dbg [[DBG212]]			// CHECK1-NEXT: [[TMP12:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l51_debug___kernel_info, i1 true), !dbg [[DBG212]]
	// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP12]], -1, !dbg [[DBG212]]			// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP12]], -1, !dbg [[DBG212]]
	// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]], !dbg [[DBG212]]			// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]], !dbg [[DBG212]]
	// CHECK1: user_code.entry:			// CHECK1: user_code.entry:
	// CHECK1-NEXT: [[TMP13:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB15:[0-9]+]])			// CHECK1-NEXT: [[TMP13:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB11:[0-9]+]])
	// CHECK1-NEXT: [[TMP14:%.]] = getelementptr inbounds [4 x i8], [4 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 0, !dbg [[DBG213:![0-9]+]]			// CHECK1-NEXT: [[TMP14:%.]] = getelementptr inbounds [4 x i8], [4 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 0, !dbg [[DBG213:![0-9]+]]
	// CHECK1-NEXT: [[TMP15:%.]] = bitcast [10 x [10 x [10 x i32]]] [[TMP2]] to i8*, !dbg [[DBG213]]			// CHECK1-NEXT: [[TMP15:%.]] = bitcast [10 x [10 x [10 x i32]]] [[TMP2]] to i8*, !dbg [[DBG213]]
	// CHECK1-NEXT: store i8* [[TMP15]], i8** [[TMP14]], align 8, !dbg [[DBG213]]			// CHECK1-NEXT: store i8* [[TMP15]], i8** [[TMP14]], align 8, !dbg [[DBG213]]
	// CHECK1-NEXT: [[TMP16:%.]] = getelementptr inbounds [4 x i8], [4 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 1, !dbg [[DBG213]]			// CHECK1-NEXT: [[TMP16:%.]] = getelementptr inbounds [4 x i8], [4 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 1, !dbg [[DBG213]]
	// CHECK1-NEXT: [[TMP17:%.]] = bitcast i32 [[TMP5]] to i8*, !dbg [[DBG213]]			// CHECK1-NEXT: [[TMP17:%.]] = bitcast i32 [[TMP5]] to i8*, !dbg [[DBG213]]
	// CHECK1-NEXT: store i8* [[TMP17]], i8** [[TMP16]], align 8, !dbg [[DBG213]]			// CHECK1-NEXT: store i8* [[TMP17]], i8** [[TMP16]], align 8, !dbg [[DBG213]]
	// CHECK1-NEXT: [[TMP18:%.]] = getelementptr inbounds [4 x i8], [4 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 2, !dbg [[DBG213]]			// CHECK1-NEXT: [[TMP18:%.]] = getelementptr inbounds [4 x i8], [4 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 2, !dbg [[DBG213]]
	// CHECK1-NEXT: [[TMP19:%.]] = bitcast [10 x [10 x i32]] [[TMP8]] to i8*, !dbg [[DBG213]]			// CHECK1-NEXT: [[TMP19:%.]] = bitcast [10 x [10 x i32]] [[TMP8]] to i8*, !dbg [[DBG213]]
	// CHECK1-NEXT: store i8* [[TMP19]], i8** [[TMP18]], align 8, !dbg [[DBG213]]			// CHECK1-NEXT: store i8* [[TMP19]], i8** [[TMP18]], align 8, !dbg [[DBG213]]
	// CHECK1-NEXT: [[TMP20:%.]] = getelementptr inbounds [4 x i8], [4 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 3, !dbg [[DBG213]]			// CHECK1-NEXT: [[TMP20:%.]] = getelementptr inbounds [4 x i8], [4 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 3, !dbg [[DBG213]]
	// CHECK1-NEXT: store i8* [[TMP11]], i8** [[TMP20]], align 8, !dbg [[DBG213]]			// CHECK1-NEXT: store i8* [[TMP11]], i8** [[TMP20]], align 8, !dbg [[DBG213]]
	// CHECK1-NEXT: [[TMP21:%.]] = bitcast [4 x i8]* [[CAPTURED_VARS_ADDRS]] to i8**, !dbg [[DBG213]]			// CHECK1-NEXT: [[TMP21:%.]] = bitcast [4 x i8]* [[CAPTURED_VARS_ADDRS]] to i8**, !dbg [[DBG213]]
	// CHECK1-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB15]], i32 [[TMP13]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32, i32, [10 x [10 x [10 x i32]]], i32, [10 x [10 x i32]], i8)* @__omp_outlined__4 to i8), i8 null, i8** [[TMP21]], i64 4), !dbg [[DBG213]]			// CHECK1-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB11]], i32 [[TMP13]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32, i32, [10 x [10 x [10 x i32]]], i32, [10 x [10 x i32]], i8)* @__omp_outlined__4 to i8), i8 null, i8** [[TMP21]], i64 4), !dbg [[DBG213]]
	// CHECK1-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB17:[0-9]+]], i8 2, i1 true), !dbg [[DBG214:![0-9]+]]			// CHECK1-NEXT: call void @__kmpc_target_deinit(i1 true), !dbg [[DBG214:![0-9]+]]
	// CHECK1-NEXT: ret void, !dbg [[DBG216:![0-9]+]]			// CHECK1-NEXT: ret void, !dbg [[DBG216:![0-9]+]]
	// CHECK1: worker.exit:			// CHECK1: worker.exit:
	// CHECK1-NEXT: ret void, !dbg [[DBG212]]			// CHECK1-NEXT: ret void, !dbg [[DBG212]]
	//			//
	//			//
	// CHECK1-LABEL: define {{[^@]+}}@__omp_outlined___debug__3			// CHECK1-LABEL: define {{[^@]+}}@__omp_outlined___debug__3
	// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], [10 x [10 x [10 x i32]]] addrspace(1) noalias [[C:%.]], i32 addrspace(1) noalias [[A:%.]], [10 x [10 x i32]] addrspace(1) noalias [[B:%.]], i8 addrspace(1) noalias [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG217:![0-9]+]] {			// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], [10 x [10 x [10 x i32]]] addrspace(1) noalias [[C:%.]], i32 addrspace(1) noalias [[A:%.]], [10 x [10 x i32]] addrspace(1) noalias [[B:%.]], i8 addrspace(1) noalias [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG217:![0-9]+]] {
	// CHECK1-NEXT: entry:			// CHECK1-NEXT: entry:
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clang/test/OpenMP/target_parallel_for_debug_codegen.cpp

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	// CHECK1-NEXT: [[TMP2:%.]] = load [10 x [10 x [10 x i32]]], [10 x [10 x [10 x i32]]]** [[TMP]], align 8, !dbg [[DBG41]]			// CHECK1-NEXT: [[TMP2:%.]] = load [10 x [10 x [10 x i32]]], [10 x [10 x [10 x i32]]]** [[TMP]], align 8, !dbg [[DBG41]]
	// CHECK1-NEXT: [[TMP3:%.]] = load [10 x [10 x i32]], [10 x [10 x i32]]** [[B_ADDR]], align 8, !dbg [[DBG41]]			// CHECK1-NEXT: [[TMP3:%.]] = load [10 x [10 x i32]], [10 x [10 x i32]]** [[B_ADDR]], align 8, !dbg [[DBG41]]
	// CHECK1-NEXT: store [10 x [10 x i32]]* [[TMP3]], [10 x [10 x i32]]** [[_TMP1]], align 8, !dbg [[DBG41]]			// CHECK1-NEXT: store [10 x [10 x i32]]* [[TMP3]], [10 x [10 x i32]]** [[_TMP1]], align 8, !dbg [[DBG41]]
	// CHECK1-NEXT: [[TMP4:%.]] = load [10 x [10 x i32]], [10 x [10 x i32]]** [[_TMP1]], align 8, !dbg [[DBG41]]			// CHECK1-NEXT: [[TMP4:%.]] = load [10 x [10 x i32]], [10 x [10 x i32]]** [[_TMP1]], align 8, !dbg [[DBG41]]
	// CHECK1-NEXT: [[TMP5:%.]] = load i8 addrspace(1), i8 addrspace(1)** [[BB_ADDR]], align 8, !dbg [[DBG41]]			// CHECK1-NEXT: [[TMP5:%.]] = load i8 addrspace(1), i8 addrspace(1)** [[BB_ADDR]], align 8, !dbg [[DBG41]]
	// CHECK1-NEXT: [[TMP6:%.]] = addrspacecast i8 addrspace(1) [[TMP5]] to i8*, !dbg [[DBG41]]			// CHECK1-NEXT: [[TMP6:%.]] = addrspacecast i8 addrspace(1) [[TMP5]] to i8*, !dbg [[DBG41]]
	// CHECK1-NEXT: store i8* [[TMP6]], i8** [[_TMP2]], align 8, !dbg [[DBG41]]			// CHECK1-NEXT: store i8* [[TMP6]], i8** [[_TMP2]], align 8, !dbg [[DBG41]]
	// CHECK1-NEXT: [[TMP7:%.]] = load i8, i8** [[_TMP2]], align 8, !dbg [[DBG41]]			// CHECK1-NEXT: [[TMP7:%.]] = load i8, i8** [[_TMP2]], align 8, !dbg [[DBG41]]
	// CHECK1-NEXT: [[TMP8:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1:[0-9]+]], i8 2, i1 false, i1 false), !dbg [[DBG41]]			// CHECK1-NEXT: [[TMP8:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l13_debug___kernel_info, i1 false), !dbg [[DBG41]]
	// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP8]], -1, !dbg [[DBG41]]			// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP8]], -1, !dbg [[DBG41]]
	// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]], !dbg [[DBG41]]			// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]], !dbg [[DBG41]]
	// CHECK1: user_code.entry:			// CHECK1: user_code.entry:
	// CHECK1-NEXT: [[TMP9:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB6:[0-9]+]])			// CHECK1-NEXT: [[TMP9:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB6:[0-9]+]])
	// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[A_ADDR]], align 4, !dbg [[DBG42:![0-9]+]]			// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[A_ADDR]], align 4, !dbg [[DBG42:![0-9]+]]
	// CHECK1-NEXT: [[CONV:%.]] = bitcast i64 [[A_CASTED]] to i32*, !dbg [[DBG42]]			// CHECK1-NEXT: [[CONV:%.]] = bitcast i64 [[A_CASTED]] to i32*, !dbg [[DBG42]]
	// CHECK1-NEXT: store i32 [[TMP10]], i32* [[CONV]], align 4, !dbg [[DBG42]]			// CHECK1-NEXT: store i32 [[TMP10]], i32* [[CONV]], align 4, !dbg [[DBG42]]
	// CHECK1-NEXT: [[TMP11:%.]] = load i64, i64 [[A_CASTED]], align 8, !dbg [[DBG42]]			// CHECK1-NEXT: [[TMP11:%.]] = load i64, i64 [[A_CASTED]], align 8, !dbg [[DBG42]]
	// CHECK1-NEXT: [[TMP12:%.]] = getelementptr inbounds [4 x i8], [4 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 0, !dbg [[DBG42]]			// CHECK1-NEXT: [[TMP12:%.]] = getelementptr inbounds [4 x i8], [4 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 0, !dbg [[DBG42]]
	// CHECK1-NEXT: [[TMP13:%.]] = bitcast [10 x [10 x [10 x i32]]] [[TMP2]] to i8*, !dbg [[DBG42]]			// CHECK1-NEXT: [[TMP13:%.]] = bitcast [10 x [10 x [10 x i32]]] [[TMP2]] to i8*, !dbg [[DBG42]]
	// CHECK1-NEXT: store i8* [[TMP13]], i8** [[TMP12]], align 8, !dbg [[DBG42]]			// CHECK1-NEXT: store i8* [[TMP13]], i8** [[TMP12]], align 8, !dbg [[DBG42]]
	// CHECK1-NEXT: [[TMP14:%.]] = getelementptr inbounds [4 x i8], [4 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 1, !dbg [[DBG42]]			// CHECK1-NEXT: [[TMP14:%.]] = getelementptr inbounds [4 x i8], [4 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 1, !dbg [[DBG42]]
	// CHECK1-NEXT: [[TMP15:%.]] = inttoptr i64 [[TMP11]] to i8, !dbg [[DBG42]]			// CHECK1-NEXT: [[TMP15:%.]] = inttoptr i64 [[TMP11]] to i8, !dbg [[DBG42]]
	// CHECK1-NEXT: store i8* [[TMP15]], i8** [[TMP14]], align 8, !dbg [[DBG42]]			// CHECK1-NEXT: store i8* [[TMP15]], i8** [[TMP14]], align 8, !dbg [[DBG42]]
	// CHECK1-NEXT: [[TMP16:%.]] = getelementptr inbounds [4 x i8], [4 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 2, !dbg [[DBG42]]			// CHECK1-NEXT: [[TMP16:%.]] = getelementptr inbounds [4 x i8], [4 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 2, !dbg [[DBG42]]
	// CHECK1-NEXT: [[TMP17:%.]] = bitcast [10 x [10 x i32]] [[TMP4]] to i8*, !dbg [[DBG42]]			// CHECK1-NEXT: [[TMP17:%.]] = bitcast [10 x [10 x i32]] [[TMP4]] to i8*, !dbg [[DBG42]]
	// CHECK1-NEXT: store i8* [[TMP17]], i8** [[TMP16]], align 8, !dbg [[DBG42]]			// CHECK1-NEXT: store i8* [[TMP17]], i8** [[TMP16]], align 8, !dbg [[DBG42]]
	// CHECK1-NEXT: [[TMP18:%.]] = getelementptr inbounds [4 x i8], [4 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 3, !dbg [[DBG42]]			// CHECK1-NEXT: [[TMP18:%.]] = getelementptr inbounds [4 x i8], [4 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 3, !dbg [[DBG42]]
	// CHECK1-NEXT: store i8* [[TMP7]], i8** [[TMP18]], align 8, !dbg [[DBG42]]			// CHECK1-NEXT: store i8* [[TMP7]], i8** [[TMP18]], align 8, !dbg [[DBG42]]
	// CHECK1-NEXT: [[TMP19:%.]] = load i8, i8 [[DOTCAPTURE_EXPR__ADDR]], align 1, !dbg [[DBG43:![0-9]+]]			// CHECK1-NEXT: [[TMP19:%.]] = load i8, i8 [[DOTCAPTURE_EXPR__ADDR]], align 1, !dbg [[DBG43:![0-9]+]]
	// CHECK1-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP19]] to i1, !dbg [[DBG43]]			// CHECK1-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP19]] to i1, !dbg [[DBG43]]
	// CHECK1-NEXT: [[TMP20:%.*]] = zext i1 [[TOBOOL]] to i32, !dbg [[DBG42]]			// CHECK1-NEXT: [[TMP20:%.*]] = zext i1 [[TOBOOL]] to i32, !dbg [[DBG42]]
	// CHECK1-NEXT: [[TMP21:%.]] = bitcast [4 x i8]* [[CAPTURED_VARS_ADDRS]] to i8**, !dbg [[DBG42]]			// CHECK1-NEXT: [[TMP21:%.]] = bitcast [4 x i8]* [[CAPTURED_VARS_ADDRS]] to i8**, !dbg [[DBG42]]
	// CHECK1-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB6]], i32 [[TMP9]], i32 [[TMP20]], i32 -1, i32 -1, i8* bitcast (void (i32, i32, [10 x [10 x [10 x i32]]], i64, [10 x [10 x i32]], i8) @__omp_outlined__ to i8), i8 null, i8** [[TMP21]], i64 4), !dbg [[DBG42]]			// CHECK1-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB6]], i32 [[TMP9]], i32 [[TMP20]], i32 -1, i32 -1, i8* bitcast (void (i32, i32, [10 x [10 x [10 x i32]]], i64, [10 x [10 x i32]], i8) @__omp_outlined__ to i8), i8 null, i8** [[TMP21]], i64 4), !dbg [[DBG42]]
	// CHECK1-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB8:[0-9]+]], i8 2, i1 false), !dbg [[DBG45:![0-9]+]]			// CHECK1-NEXT: call void @__kmpc_target_deinit(i1 false), !dbg [[DBG45:![0-9]+]]
	// CHECK1-NEXT: ret void, !dbg [[DBG46:![0-9]+]]			// CHECK1-NEXT: ret void, !dbg [[DBG46:![0-9]+]]
	// CHECK1: worker.exit:			// CHECK1: worker.exit:
	// CHECK1-NEXT: ret void, !dbg [[DBG41]]			// CHECK1-NEXT: ret void, !dbg [[DBG41]]
	//			//
	//			//
	// CHECK1-LABEL: define {{[^@]+}}@__omp_outlined___debug__			// CHECK1-LABEL: define {{[^@]+}}@__omp_outlined___debug__
	// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], [10 x [10 x [10 x i32]]] addrspace(1) noalias [[C:%.]], i32 [[A:%.]], [10 x [10 x i32]]* noalias [[B:%.]], i8 addrspace(1) noalias [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG47:![0-9]+]] {			// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], [10 x [10 x [10 x i32]]] addrspace(1) noalias [[C:%.]], i32 [[A:%.]], [10 x [10 x i32]]* noalias [[B:%.]], i8 addrspace(1) noalias [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG47:![0-9]+]] {
	// CHECK1-NEXT: entry:			// CHECK1-NEXT: entry:
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	// CHECK1-NEXT: [[TMP3:%.]] = load [10 x [10 x i32]] addrspace(1), [10 x [10 x i32]] addrspace(1)** [[B_ADDR]], align 8, !dbg [[DBG146]]			// CHECK1-NEXT: [[TMP3:%.]] = load [10 x [10 x i32]] addrspace(1), [10 x [10 x i32]] addrspace(1)** [[B_ADDR]], align 8, !dbg [[DBG146]]
	// CHECK1-NEXT: [[TMP4:%.]] = addrspacecast [10 x [10 x i32]] addrspace(1) [[TMP3]] to [10 x [10 x i32]]*, !dbg [[DBG146]]			// CHECK1-NEXT: [[TMP4:%.]] = addrspacecast [10 x [10 x i32]] addrspace(1) [[TMP3]] to [10 x [10 x i32]]*, !dbg [[DBG146]]
	// CHECK1-NEXT: store [10 x [10 x i32]]* [[TMP4]], [10 x [10 x i32]]** [[_TMP1]], align 8, !dbg [[DBG146]]			// CHECK1-NEXT: store [10 x [10 x i32]]* [[TMP4]], [10 x [10 x i32]]** [[_TMP1]], align 8, !dbg [[DBG146]]
	// CHECK1-NEXT: [[TMP5:%.]] = load [10 x [10 x i32]], [10 x [10 x i32]]** [[_TMP1]], align 8, !dbg [[DBG146]]			// CHECK1-NEXT: [[TMP5:%.]] = load [10 x [10 x i32]], [10 x [10 x i32]]** [[_TMP1]], align 8, !dbg [[DBG146]]
	// CHECK1-NEXT: [[TMP6:%.]] = load i8 addrspace(1), i8 addrspace(1)** [[BB_ADDR]], align 8, !dbg [[DBG146]]			// CHECK1-NEXT: [[TMP6:%.]] = load i8 addrspace(1), i8 addrspace(1)** [[BB_ADDR]], align 8, !dbg [[DBG146]]
	// CHECK1-NEXT: [[TMP7:%.]] = addrspacecast i8 addrspace(1) [[TMP6]] to i8*, !dbg [[DBG146]]			// CHECK1-NEXT: [[TMP7:%.]] = addrspacecast i8 addrspace(1) [[TMP6]] to i8*, !dbg [[DBG146]]
	// CHECK1-NEXT: store i8* [[TMP7]], i8** [[_TMP2]], align 8, !dbg [[DBG146]]			// CHECK1-NEXT: store i8* [[TMP7]], i8** [[_TMP2]], align 8, !dbg [[DBG146]]
	// CHECK1-NEXT: [[TMP8:%.]] = load i8, i8** [[_TMP2]], align 8, !dbg [[DBG146]]			// CHECK1-NEXT: [[TMP8:%.]] = load i8, i8** [[_TMP2]], align 8, !dbg [[DBG146]]
	// CHECK1-NEXT: [[TMP9:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB10:[0-9]+]], i8 2, i1 false, i1 false), !dbg [[DBG146]]			// CHECK1-NEXT: [[TMP9:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l27_debug___kernel_info, i1 false), !dbg [[DBG146]]
	// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP9]], -1, !dbg [[DBG146]]			// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP9]], -1, !dbg [[DBG146]]
	// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]], !dbg [[DBG146]]			// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]], !dbg [[DBG146]]
	// CHECK1: user_code.entry:			// CHECK1: user_code.entry:
	// CHECK1-NEXT: [[TMP10:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB15:[0-9]+]])			// CHECK1-NEXT: [[TMP10:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB13:[0-9]+]])
	// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[A_ADDR]], align 4, !dbg [[DBG147:![0-9]+]]			// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[A_ADDR]], align 4, !dbg [[DBG147:![0-9]+]]
	// CHECK1-NEXT: [[CONV:%.]] = bitcast i64 [[A_CASTED]] to i32*, !dbg [[DBG147]]			// CHECK1-NEXT: [[CONV:%.]] = bitcast i64 [[A_CASTED]] to i32*, !dbg [[DBG147]]
	// CHECK1-NEXT: store i32 [[TMP11]], i32* [[CONV]], align 4, !dbg [[DBG147]]			// CHECK1-NEXT: store i32 [[TMP11]], i32* [[CONV]], align 4, !dbg [[DBG147]]
	// CHECK1-NEXT: [[TMP12:%.]] = load i64, i64 [[A_CASTED]], align 8, !dbg [[DBG147]]			// CHECK1-NEXT: [[TMP12:%.]] = load i64, i64 [[A_CASTED]], align 8, !dbg [[DBG147]]
	// CHECK1-NEXT: [[TMP13:%.]] = getelementptr inbounds [4 x i8], [4 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 0, !dbg [[DBG147]]			// CHECK1-NEXT: [[TMP13:%.]] = getelementptr inbounds [4 x i8], [4 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 0, !dbg [[DBG147]]
	// CHECK1-NEXT: [[TMP14:%.]] = bitcast [10 x [10 x [10 x i32]]] [[TMP2]] to i8*, !dbg [[DBG147]]			// CHECK1-NEXT: [[TMP14:%.]] = bitcast [10 x [10 x [10 x i32]]] [[TMP2]] to i8*, !dbg [[DBG147]]
	// CHECK1-NEXT: store i8* [[TMP14]], i8** [[TMP13]], align 8, !dbg [[DBG147]]			// CHECK1-NEXT: store i8* [[TMP14]], i8** [[TMP13]], align 8, !dbg [[DBG147]]
	// CHECK1-NEXT: [[TMP15:%.]] = getelementptr inbounds [4 x i8], [4 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 1, !dbg [[DBG147]]			// CHECK1-NEXT: [[TMP15:%.]] = getelementptr inbounds [4 x i8], [4 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 1, !dbg [[DBG147]]
	// CHECK1-NEXT: [[TMP16:%.]] = inttoptr i64 [[TMP12]] to i8, !dbg [[DBG147]]			// CHECK1-NEXT: [[TMP16:%.]] = inttoptr i64 [[TMP12]] to i8, !dbg [[DBG147]]
	// CHECK1-NEXT: store i8* [[TMP16]], i8** [[TMP15]], align 8, !dbg [[DBG147]]			// CHECK1-NEXT: store i8* [[TMP16]], i8** [[TMP15]], align 8, !dbg [[DBG147]]
	// CHECK1-NEXT: [[TMP17:%.]] = getelementptr inbounds [4 x i8], [4 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 2, !dbg [[DBG147]]			// CHECK1-NEXT: [[TMP17:%.]] = getelementptr inbounds [4 x i8], [4 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 2, !dbg [[DBG147]]
	// CHECK1-NEXT: [[TMP18:%.]] = bitcast [10 x [10 x i32]] [[TMP5]] to i8*, !dbg [[DBG147]]			// CHECK1-NEXT: [[TMP18:%.]] = bitcast [10 x [10 x i32]] [[TMP5]] to i8*, !dbg [[DBG147]]
	// CHECK1-NEXT: store i8* [[TMP18]], i8** [[TMP17]], align 8, !dbg [[DBG147]]			// CHECK1-NEXT: store i8* [[TMP18]], i8** [[TMP17]], align 8, !dbg [[DBG147]]
	// CHECK1-NEXT: [[TMP19:%.]] = getelementptr inbounds [4 x i8], [4 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 3, !dbg [[DBG147]]			// CHECK1-NEXT: [[TMP19:%.]] = getelementptr inbounds [4 x i8], [4 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 3, !dbg [[DBG147]]
	// CHECK1-NEXT: store i8* [[TMP8]], i8** [[TMP19]], align 8, !dbg [[DBG147]]			// CHECK1-NEXT: store i8* [[TMP8]], i8** [[TMP19]], align 8, !dbg [[DBG147]]
	// CHECK1-NEXT: [[TMP20:%.]] = bitcast [4 x i8]* [[CAPTURED_VARS_ADDRS]] to i8**, !dbg [[DBG147]]			// CHECK1-NEXT: [[TMP20:%.]] = bitcast [4 x i8]* [[CAPTURED_VARS_ADDRS]] to i8**, !dbg [[DBG147]]
	// CHECK1-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB15]], i32 [[TMP10]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32, i32, [10 x [10 x [10 x i32]]], i64, [10 x [10 x i32]], i8) @__omp_outlined__2 to i8), i8 null, i8** [[TMP20]], i64 4), !dbg [[DBG147]]			// CHECK1-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB13]], i32 [[TMP10]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32, i32, [10 x [10 x [10 x i32]]], i64, [10 x [10 x i32]], i8) @__omp_outlined__2 to i8), i8 null, i8** [[TMP20]], i64 4), !dbg [[DBG147]]
	// CHECK1-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB17:[0-9]+]], i8 2, i1 false), !dbg [[DBG148:![0-9]+]]			// CHECK1-NEXT: call void @__kmpc_target_deinit(i1 false), !dbg [[DBG148:![0-9]+]]
	// CHECK1-NEXT: ret void, !dbg [[DBG150:![0-9]+]]			// CHECK1-NEXT: ret void, !dbg [[DBG150:![0-9]+]]
	// CHECK1: worker.exit:			// CHECK1: worker.exit:
	// CHECK1-NEXT: ret void, !dbg [[DBG146]]			// CHECK1-NEXT: ret void, !dbg [[DBG146]]
	//			//
	//			//
	// CHECK1-LABEL: define {{[^@]+}}@__omp_outlined___debug__1			// CHECK1-LABEL: define {{[^@]+}}@__omp_outlined___debug__1
	// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], [10 x [10 x [10 x i32]]] addrspace(1) noalias [[C:%.]], i32 [[A:%.]], [10 x [10 x i32]] addrspace(1)* noalias [[B:%.]], i8 addrspace(1) noalias [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG151:![0-9]+]] {			// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], [10 x [10 x [10 x i32]]] addrspace(1) noalias [[C:%.]], i32 [[A:%.]], [10 x [10 x i32]] addrspace(1)* noalias [[B:%.]], i8 addrspace(1) noalias [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG151:![0-9]+]] {
	// CHECK1-NEXT: entry:			// CHECK1-NEXT: entry:
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	// CHECK1-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4, !dbg [[DBG168]]			// CHECK1-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4, !dbg [[DBG168]]
	// CHECK1-NEXT: call void @llvm.dbg.declare(metadata i32* [[DOTOMP_STRIDE]], metadata [[META170:![0-9]+]], metadata !DIExpression()), !dbg [[DBG155]]			// CHECK1-NEXT: call void @llvm.dbg.declare(metadata i32* [[DOTOMP_STRIDE]], metadata [[META170:![0-9]+]], metadata !DIExpression()), !dbg [[DBG155]]
	// CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4, !dbg [[DBG168]]			// CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4, !dbg [[DBG168]]
	// CHECK1-NEXT: call void @llvm.dbg.declare(metadata i32* [[DOTOMP_IS_LAST]], metadata [[META171:![0-9]+]], metadata !DIExpression()), !dbg [[DBG155]]			// CHECK1-NEXT: call void @llvm.dbg.declare(metadata i32* [[DOTOMP_IS_LAST]], metadata [[META171:![0-9]+]], metadata !DIExpression()), !dbg [[DBG155]]
	// CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4, !dbg [[DBG168]]			// CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4, !dbg [[DBG168]]
	// CHECK1-NEXT: call void @llvm.dbg.declare(metadata i32* [[I]], metadata [[META172:![0-9]+]], metadata !DIExpression()), !dbg [[DBG155]]			// CHECK1-NEXT: call void @llvm.dbg.declare(metadata i32* [[I]], metadata [[META172:![0-9]+]], metadata !DIExpression()), !dbg [[DBG155]]
	// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG165]]			// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG165]]
	// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[TMP9]], align 4, !dbg [[DBG165]]			// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[TMP9]], align 4, !dbg [[DBG165]]
	// CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB12:[0-9]+]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1), !dbg [[DBG173:![0-9]+]]			// CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB10:[0-9]+]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1), !dbg [[DBG173:![0-9]+]]
	// CHECK1-NEXT: br label [[OMP_DISPATCH_COND:%.*]], !dbg [[DBG165]]			// CHECK1-NEXT: br label [[OMP_DISPATCH_COND:%.*]], !dbg [[DBG165]]
	// CHECK1: omp.dispatch.cond:			// CHECK1: omp.dispatch.cond:
	// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !dbg [[DBG168]]			// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !dbg [[DBG168]]
	// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 9, !dbg [[DBG168]]			// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 9, !dbg [[DBG168]]
	// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.]], label [[COND_FALSE:%.]], !dbg [[DBG168]]			// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.]], label [[COND_FALSE:%.]], !dbg [[DBG168]]
	// CHECK1: cond.true:			// CHECK1: cond.true:
	// CHECK1-NEXT: br label [[COND_END:%.*]], !dbg [[DBG168]]			// CHECK1-NEXT: br label [[COND_END:%.*]], !dbg [[DBG168]]
	// CHECK1: cond.false:			// CHECK1: cond.false:
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	// CHECK1-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP26]], [[TMP27]], !dbg [[DBG165]]			// CHECK1-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP26]], [[TMP27]], !dbg [[DBG165]]
	// CHECK1-NEXT: store i32 [[ADD24]], i32* [[DOTOMP_LB]], align 4, !dbg [[DBG165]]			// CHECK1-NEXT: store i32 [[ADD24]], i32* [[DOTOMP_LB]], align 4, !dbg [[DBG165]]
	// CHECK1-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !dbg [[DBG168]]			// CHECK1-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !dbg [[DBG168]]
	// CHECK1-NEXT: [[TMP29:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !dbg [[DBG168]]			// CHECK1-NEXT: [[TMP29:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !dbg [[DBG168]]
	// CHECK1-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]], !dbg [[DBG165]]			// CHECK1-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]], !dbg [[DBG165]]
	// CHECK1-NEXT: store i32 [[ADD25]], i32* [[DOTOMP_UB]], align 4, !dbg [[DBG165]]			// CHECK1-NEXT: store i32 [[ADD25]], i32* [[DOTOMP_UB]], align 4, !dbg [[DBG165]]
	// CHECK1-NEXT: br label [[OMP_DISPATCH_COND]], !dbg [[DBG173]], !llvm.loop [[LOOP203:![0-9]+]]			// CHECK1-NEXT: br label [[OMP_DISPATCH_COND]], !dbg [[DBG173]], !llvm.loop [[LOOP203:![0-9]+]]
	// CHECK1: omp.dispatch.end:			// CHECK1: omp.dispatch.end:
	// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB14:[0-9]+]], i32 [[TMP10]]), !dbg [[DBG202:![0-9]+]]			// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB12:[0-9]+]], i32 [[TMP10]]), !dbg [[DBG202:![0-9]+]]
	// CHECK1-NEXT: ret void, !dbg [[DBG204:![0-9]+]]			// CHECK1-NEXT: ret void, !dbg [[DBG204:![0-9]+]]
	//			//
	//			//
	// CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__2			// CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__2
	// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], [10 x [10 x [10 x i32]]] nonnull align 4 dereferenceable(4000) [[C:%.]], i64 [[A:%.]], [10 x [10 x i32]]* nonnull align 4 dereferenceable(400) [[B:%.]], i8 nonnull align 1 dereferenceable(1) [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG205:![0-9]+]] {			// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], [10 x [10 x [10 x i32]]] nonnull align 4 dereferenceable(4000) [[C:%.]], i64 [[A:%.]], [10 x [10 x i32]]* nonnull align 4 dereferenceable(400) [[B:%.]], i8 nonnull align 1 dereferenceable(1) [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG205:![0-9]+]] {
	// CHECK1-NEXT: entry:			// CHECK1-NEXT: entry:
	// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8			// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8
	// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8			// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8
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	// CHECK1-NEXT: [[TMP6:%.]] = load [10 x [10 x i32]] addrspace(1), [10 x [10 x i32]] addrspace(1)** [[B_ADDR]], align 8, !dbg [[DBG236]]			// CHECK1-NEXT: [[TMP6:%.]] = load [10 x [10 x i32]] addrspace(1), [10 x [10 x i32]] addrspace(1)** [[B_ADDR]], align 8, !dbg [[DBG236]]
	// CHECK1-NEXT: [[TMP7:%.]] = addrspacecast [10 x [10 x i32]] addrspace(1) [[TMP6]] to [10 x [10 x i32]]*, !dbg [[DBG236]]			// CHECK1-NEXT: [[TMP7:%.]] = addrspacecast [10 x [10 x i32]] addrspace(1) [[TMP6]] to [10 x [10 x i32]]*, !dbg [[DBG236]]
	// CHECK1-NEXT: store [10 x [10 x i32]]* [[TMP7]], [10 x [10 x i32]]** [[_TMP2]], align 8, !dbg [[DBG236]]			// CHECK1-NEXT: store [10 x [10 x i32]]* [[TMP7]], [10 x [10 x i32]]** [[_TMP2]], align 8, !dbg [[DBG236]]
	// CHECK1-NEXT: [[TMP8:%.]] = load [10 x [10 x i32]], [10 x [10 x i32]]** [[_TMP2]], align 8, !dbg [[DBG236]]			// CHECK1-NEXT: [[TMP8:%.]] = load [10 x [10 x i32]], [10 x [10 x i32]]** [[_TMP2]], align 8, !dbg [[DBG236]]
	// CHECK1-NEXT: [[TMP9:%.]] = load i8 addrspace(1), i8 addrspace(1)** [[BB_ADDR]], align 8, !dbg [[DBG236]]			// CHECK1-NEXT: [[TMP9:%.]] = load i8 addrspace(1), i8 addrspace(1)** [[BB_ADDR]], align 8, !dbg [[DBG236]]
	// CHECK1-NEXT: [[TMP10:%.]] = addrspacecast i8 addrspace(1) [[TMP9]] to i8*, !dbg [[DBG236]]			// CHECK1-NEXT: [[TMP10:%.]] = addrspacecast i8 addrspace(1) [[TMP9]] to i8*, !dbg [[DBG236]]
	// CHECK1-NEXT: store i8* [[TMP10]], i8** [[_TMP3]], align 8, !dbg [[DBG236]]			// CHECK1-NEXT: store i8* [[TMP10]], i8** [[_TMP3]], align 8, !dbg [[DBG236]]
	// CHECK1-NEXT: [[TMP11:%.]] = load i8, i8** [[_TMP3]], align 8, !dbg [[DBG236]]			// CHECK1-NEXT: [[TMP11:%.]] = load i8, i8** [[_TMP3]], align 8, !dbg [[DBG236]]
	// CHECK1-NEXT: [[TMP12:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB19:[0-9]+]], i8 2, i1 false, i1 false), !dbg [[DBG236]]			// CHECK1-NEXT: [[TMP12:%.]] = call i32 @__kmpc_target_init(%"struct._OMP::KernelEnvironmentTy" @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l41_debug___kernel_info, i1 false), !dbg [[DBG236]]
	// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP12]], -1, !dbg [[DBG236]]			// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP12]], -1, !dbg [[DBG236]]
	// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]], !dbg [[DBG236]]			// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[WORKER_EXIT:%.]], !dbg [[DBG236]]
	// CHECK1: user_code.entry:			// CHECK1: user_code.entry:
	// CHECK1-NEXT: [[TMP13:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB24:[0-9]+]])			// CHECK1-NEXT: [[TMP13:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB20:[0-9]+]])
	// CHECK1-NEXT: [[TMP14:%.]] = getelementptr inbounds [4 x i8], [4 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 0, !dbg [[DBG237:![0-9]+]]			// CHECK1-NEXT: [[TMP14:%.]] = getelementptr inbounds [4 x i8], [4 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 0, !dbg [[DBG237:![0-9]+]]
	// CHECK1-NEXT: [[TMP15:%.]] = bitcast [10 x [10 x [10 x i32]]] [[TMP2]] to i8*, !dbg [[DBG237]]			// CHECK1-NEXT: [[TMP15:%.]] = bitcast [10 x [10 x [10 x i32]]] [[TMP2]] to i8*, !dbg [[DBG237]]
	// CHECK1-NEXT: store i8* [[TMP15]], i8** [[TMP14]], align 8, !dbg [[DBG237]]			// CHECK1-NEXT: store i8* [[TMP15]], i8** [[TMP14]], align 8, !dbg [[DBG237]]
	// CHECK1-NEXT: [[TMP16:%.]] = getelementptr inbounds [4 x i8], [4 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 1, !dbg [[DBG237]]			// CHECK1-NEXT: [[TMP16:%.]] = getelementptr inbounds [4 x i8], [4 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 1, !dbg [[DBG237]]
	// CHECK1-NEXT: [[TMP17:%.]] = bitcast i32 [[TMP5]] to i8*, !dbg [[DBG237]]			// CHECK1-NEXT: [[TMP17:%.]] = bitcast i32 [[TMP5]] to i8*, !dbg [[DBG237]]
	// CHECK1-NEXT: store i8* [[TMP17]], i8** [[TMP16]], align 8, !dbg [[DBG237]]			// CHECK1-NEXT: store i8* [[TMP17]], i8** [[TMP16]], align 8, !dbg [[DBG237]]
	// CHECK1-NEXT: [[TMP18:%.]] = getelementptr inbounds [4 x i8], [4 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 2, !dbg [[DBG237]]			// CHECK1-NEXT: [[TMP18:%.]] = getelementptr inbounds [4 x i8], [4 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 2, !dbg [[DBG237]]
	// CHECK1-NEXT: [[TMP19:%.]] = bitcast [10 x [10 x i32]] [[TMP8]] to i8*, !dbg [[DBG237]]			// CHECK1-NEXT: [[TMP19:%.]] = bitcast [10 x [10 x i32]] [[TMP8]] to i8*, !dbg [[DBG237]]
	// CHECK1-NEXT: store i8* [[TMP19]], i8** [[TMP18]], align 8, !dbg [[DBG237]]			// CHECK1-NEXT: store i8* [[TMP19]], i8** [[TMP18]], align 8, !dbg [[DBG237]]
	// CHECK1-NEXT: [[TMP20:%.]] = getelementptr inbounds [4 x i8], [4 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 3, !dbg [[DBG237]]			// CHECK1-NEXT: [[TMP20:%.]] = getelementptr inbounds [4 x i8], [4 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 3, !dbg [[DBG237]]
	// CHECK1-NEXT: store i8* [[TMP11]], i8** [[TMP20]], align 8, !dbg [[DBG237]]			// CHECK1-NEXT: store i8* [[TMP11]], i8** [[TMP20]], align 8, !dbg [[DBG237]]
	// CHECK1-NEXT: [[TMP21:%.]] = bitcast [4 x i8]* [[CAPTURED_VARS_ADDRS]] to i8**, !dbg [[DBG237]]			// CHECK1-NEXT: [[TMP21:%.]] = bitcast [4 x i8]* [[CAPTURED_VARS_ADDRS]] to i8**, !dbg [[DBG237]]
	// CHECK1-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB24]], i32 [[TMP13]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32, i32, [10 x [10 x [10 x i32]]], i32, [10 x [10 x i32]], i8)* @__omp_outlined__4 to i8), i8 null, i8** [[TMP21]], i64 4), !dbg [[DBG237]]			// CHECK1-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB20]], i32 [[TMP13]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32, i32, [10 x [10 x [10 x i32]]], i32, [10 x [10 x i32]], i8)* @__omp_outlined__4 to i8), i8 null, i8** [[TMP21]], i64 4), !dbg [[DBG237]]
	// CHECK1-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB26:[0-9]+]], i8 2, i1 false), !dbg [[DBG238:![0-9]+]]			// CHECK1-NEXT: call void @__kmpc_target_deinit(i1 false), !dbg [[DBG238:![0-9]+]]
	// CHECK1-NEXT: ret void, !dbg [[DBG240:![0-9]+]]			// CHECK1-NEXT: ret void, !dbg [[DBG240:![0-9]+]]
	// CHECK1: worker.exit:			// CHECK1: worker.exit:
	// CHECK1-NEXT: ret void, !dbg [[DBG236]]			// CHECK1-NEXT: ret void, !dbg [[DBG236]]
	//			//
	//			//
	// CHECK1-LABEL: define {{[^@]+}}@__omp_outlined___debug__3			// CHECK1-LABEL: define {{[^@]+}}@__omp_outlined___debug__3
	// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], [10 x [10 x [10 x i32]]] addrspace(1) noalias [[C:%.]], i32 addrspace(1) noalias [[A:%.]], [10 x [10 x i32]] addrspace(1) noalias [[B:%.]], i8 addrspace(1) noalias [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG241:![0-9]+]] {			// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], [10 x [10 x [10 x i32]]] addrspace(1) noalias [[C:%.]], i32 addrspace(1) noalias [[A:%.]], [10 x [10 x i32]] addrspace(1) noalias [[B:%.]], i8 addrspace(1) noalias [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG241:![0-9]+]] {
	// CHECK1-NEXT: entry:			// CHECK1-NEXT: entry:
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	// CHECK1-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4, !dbg [[DBG258]]			// CHECK1-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4, !dbg [[DBG258]]
	// CHECK1-NEXT: call void @llvm.dbg.declare(metadata i32* [[DOTOMP_STRIDE]], metadata [[META260:![0-9]+]], metadata !DIExpression()), !dbg [[DBG245]]			// CHECK1-NEXT: call void @llvm.dbg.declare(metadata i32* [[DOTOMP_STRIDE]], metadata [[META260:![0-9]+]], metadata !DIExpression()), !dbg [[DBG245]]
	// CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4, !dbg [[DBG258]]			// CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4, !dbg [[DBG258]]
	// CHECK1-NEXT: call void @llvm.dbg.declare(metadata i32* [[DOTOMP_IS_LAST]], metadata [[META261:![0-9]+]], metadata !DIExpression()), !dbg [[DBG245]]			// CHECK1-NEXT: call void @llvm.dbg.declare(metadata i32* [[DOTOMP_IS_LAST]], metadata [[META261:![0-9]+]], metadata !DIExpression()), !dbg [[DBG245]]
	// CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4, !dbg [[DBG258]]			// CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4, !dbg [[DBG258]]
	// CHECK1-NEXT: call void @llvm.dbg.declare(metadata i32* [[I]], metadata [[META262:![0-9]+]], metadata !DIExpression()), !dbg [[DBG245]]			// CHECK1-NEXT: call void @llvm.dbg.declare(metadata i32* [[I]], metadata [[META262:![0-9]+]], metadata !DIExpression()), !dbg [[DBG245]]
	// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG255]]			// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG255]]
	// CHECK1-NEXT: [[TMP13:%.]] = load i32, i32 [[TMP12]], align 4, !dbg [[DBG255]]			// CHECK1-NEXT: [[TMP13:%.]] = load i32, i32 [[TMP12]], align 4, !dbg [[DBG255]]
	// CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB21:[0-9]+]], i32 [[TMP13]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1), !dbg [[DBG263:![0-9]+]]			// CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB17:[0-9]+]], i32 [[TMP13]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1), !dbg [[DBG263:![0-9]+]]
	// CHECK1-NEXT: br label [[OMP_DISPATCH_COND:%.*]], !dbg [[DBG255]]			// CHECK1-NEXT: br label [[OMP_DISPATCH_COND:%.*]], !dbg [[DBG255]]
	// CHECK1: omp.dispatch.cond:			// CHECK1: omp.dispatch.cond:
	// CHECK1-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !dbg [[DBG258]]			// CHECK1-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !dbg [[DBG258]]
	// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP14]], 9, !dbg [[DBG258]]			// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP14]], 9, !dbg [[DBG258]]
	// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.]], label [[COND_FALSE:%.]], !dbg [[DBG258]]			// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.]], label [[COND_FALSE:%.]], !dbg [[DBG258]]
	// CHECK1: cond.true:			// CHECK1: cond.true:
	// CHECK1-NEXT: br label [[COND_END:%.*]], !dbg [[DBG258]]			// CHECK1-NEXT: br label [[COND_END:%.*]], !dbg [[DBG258]]
	// CHECK1: cond.false:			// CHECK1: cond.false:
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	// CHECK1-NEXT: [[ADD28:%.*]] = add nsw i32 [[TMP30]], [[TMP31]], !dbg [[DBG255]]			// CHECK1-NEXT: [[ADD28:%.*]] = add nsw i32 [[TMP30]], [[TMP31]], !dbg [[DBG255]]
	// CHECK1-NEXT: store i32 [[ADD28]], i32* [[DOTOMP_LB]], align 4, !dbg [[DBG255]]			// CHECK1-NEXT: store i32 [[ADD28]], i32* [[DOTOMP_LB]], align 4, !dbg [[DBG255]]
	// CHECK1-NEXT: [[TMP32:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !dbg [[DBG258]]			// CHECK1-NEXT: [[TMP32:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !dbg [[DBG258]]
	// CHECK1-NEXT: [[TMP33:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !dbg [[DBG258]]			// CHECK1-NEXT: [[TMP33:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !dbg [[DBG258]]
	// CHECK1-NEXT: [[ADD29:%.*]] = add nsw i32 [[TMP32]], [[TMP33]], !dbg [[DBG255]]			// CHECK1-NEXT: [[ADD29:%.*]] = add nsw i32 [[TMP32]], [[TMP33]], !dbg [[DBG255]]
	// CHECK1-NEXT: store i32 [[ADD29]], i32* [[DOTOMP_UB]], align 4, !dbg [[DBG255]]			// CHECK1-NEXT: store i32 [[ADD29]], i32* [[DOTOMP_UB]], align 4, !dbg [[DBG255]]
	// CHECK1-NEXT: br label [[OMP_DISPATCH_COND]], !dbg [[DBG263]], !llvm.loop [[LOOP294:![0-9]+]]			// CHECK1-NEXT: br label [[OMP_DISPATCH_COND]], !dbg [[DBG263]], !llvm.loop [[LOOP294:![0-9]+]]
	// CHECK1: omp.dispatch.end:			// CHECK1: omp.dispatch.end:
	// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB23:[0-9]+]], i32 [[TMP13]]), !dbg [[DBG293:![0-9]+]]			// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB19:[0-9]+]], i32 [[TMP13]]), !dbg [[DBG293:![0-9]+]]
	// CHECK1-NEXT: ret void, !dbg [[DBG295:![0-9]+]]			// CHECK1-NEXT: ret void, !dbg [[DBG295:![0-9]+]]
	//			//
	//			//
	// CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__4			// CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__4
	// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], [10 x [10 x [10 x i32]]] nonnull align 4 dereferenceable(4000) [[C:%.]], i32 nonnull align 4 dereferenceable(4) [[A:%.]], [10 x [10 x i32]] nonnull align 4 dereferenceable(400) [[B:%.]], i8 nonnull align 1 dereferenceable(1) [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG296:![0-9]+]] {			// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], [10 x [10 x [10 x i32]]] nonnull align 4 dereferenceable(4000) [[C:%.]], i32 nonnull align 4 dereferenceable(4) [[A:%.]], [10 x [10 x i32]] nonnull align 4 dereferenceable(400) [[B:%.]], i8 nonnull align 1 dereferenceable(1) [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG296:![0-9]+]] {
	// CHECK1-NEXT: entry:			// CHECK1-NEXT: entry:
	// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8			// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8
	// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8			// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8
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clang/test/OpenMP/target_teams_distribute_parallel_for_proc_bind_codegen.cpp

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	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg			// CHECK2-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
	// CHECK2-SAME: () #[[ATTR4:[0-9]+]] {			// CHECK2-SAME: () #[[ATTR4:[0-9]+]] {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	// CHECK2-NEXT: call void @__tgt_register_requires(i64 1)			// CHECK2-NEXT: call void @__tgt_register_requires(i64 1)
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	//			//
	//
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clang/test/OpenMP/target_teams_distribute_parallel_for_reduction_codegen.cpp

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	//			//
	//			//
	// CHECK6-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg			// CHECK6-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
	// CHECK6-SAME: () #[[ATTR6:[0-9]+]] {			// CHECK6-SAME: () #[[ATTR6:[0-9]+]] {
	// CHECK6-NEXT: entry:			// CHECK6-NEXT: entry:
	// CHECK6-NEXT: call void @__tgt_register_requires(i64 1)			// CHECK6-NEXT: call void @__tgt_register_requires(i64 1)
	// CHECK6-NEXT: ret void			// CHECK6-NEXT: ret void
	//			//
	//
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clang/test/OpenMP/target_teams_distribute_parallel_for_simd_codegen.cpp

This file is larger than 256 KB, so syntax highlighting is disabled by default.

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	// CHECK1-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8			// CHECK1-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8
	// CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8			// CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
	// CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8			// CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8
	// CHECK1-NEXT: [[CONV:%.]] = bitcast i64 [[I_ADDR]] to i32*			// CHECK1-NEXT: [[CONV:%.]] = bitcast i64 [[I_ADDR]] to i32*
	// CHECK1-NEXT: [[CONV3:%.]] = bitcast i64 [[N_ADDR]] to i32*			// CHECK1-NEXT: [[CONV3:%.]] = bitcast i64 [[N_ADDR]] to i32*
	// CHECK1-NEXT: [[TMP1:%.]] = load [1000 x i32], [1000 x i32]** [[A_ADDR]], align 8			// CHECK1-NEXT: [[TMP1:%.]] = load [1000 x i32], [1000 x i32]** [[A_ADDR]], align 8
	// CHECK1-NEXT: [[CONV4:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__ADDR]] to i32*			// CHECK1-NEXT: [[CONV4:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__ADDR]] to i32*
	// CHECK1-NEXT: [[CONV5:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__ADDR2]] to i32*			// CHECK1-NEXT: [[CONV5:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__ADDR2]] to i32*
	// CHECK1-NEXT: [[TMP2:%.]] = load i32, i32 [[CONV4]], align 4			// CHECK1-NEXT: [[TMP2:%.]] = load i32, i32 [[CONV4]], align 8
	// CHECK1-NEXT: [[TMP3:%.]] = load i32, i32 [[CONV5]], align 4			// CHECK1-NEXT: [[TMP3:%.]] = load i32, i32 [[CONV5]], align 8
	// CHECK1-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB4]], i32 [[TMP0]], i32 [[TMP2]], i32 [[TMP3]])			// CHECK1-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB4]], i32 [[TMP0]], i32 [[TMP2]], i32 [[TMP3]])
	// CHECK1-NEXT: [[TMP4:%.]] = load i32, i32 [[CONV]], align 4			// CHECK1-NEXT: [[TMP4:%.]] = load i32, i32 [[CONV]], align 8
	// CHECK1-NEXT: [[CONV6:%.]] = bitcast i64 [[I_CASTED]] to i32*			// CHECK1-NEXT: [[CONV6:%.]] = bitcast i64 [[I_CASTED]] to i32*
	// CHECK1-NEXT: store i32 [[TMP4]], i32* [[CONV6]], align 4			// CHECK1-NEXT: store i32 [[TMP4]], i32* [[CONV6]], align 4
	// CHECK1-NEXT: [[TMP5:%.]] = load i64, i64 [[I_CASTED]], align 8			// CHECK1-NEXT: [[TMP5:%.]] = load i64, i64 [[I_CASTED]], align 8
	// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[CONV3]], align 4			// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[CONV3]], align 8
	// CHECK1-NEXT: [[CONV7:%.]] = bitcast i64 [[N_CASTED]] to i32*			// CHECK1-NEXT: [[CONV7:%.]] = bitcast i64 [[N_CASTED]] to i32*
	// CHECK1-NEXT: store i32 [[TMP6]], i32* [[CONV7]], align 4			// CHECK1-NEXT: store i32 [[TMP6]], i32* [[CONV7]], align 4
	// CHECK1-NEXT: [[TMP7:%.]] = load i64, i64 [[N_CASTED]], align 8			// CHECK1-NEXT: [[TMP7:%.]] = load i64, i64 [[N_CASTED]], align 8
	// CHECK1-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB4]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, [1000 x i32]) @.omp_outlined. to void (i32, i32, ...)), i64 [[TMP5]], i64 [[TMP7]], [1000 x i32] [[TMP1]])			// CHECK1-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB4]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, [1000 x i32]) @.omp_outlined. to void (i32, i32, ...)), i64 [[TMP5]], i64 [[TMP7]], [1000 x i32] [[TMP1]])
	// CHECK1-NEXT: ret void			// CHECK1-NEXT: ret void
	//			//
	//			//
	// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined.			// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined.
	Show All 19 Lines
	// CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8			// CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
	// CHECK1-NEXT: store i64 [[I]], i64* [[I_ADDR]], align 8			// CHECK1-NEXT: store i64 [[I]], i64* [[I_ADDR]], align 8
	// CHECK1-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8			// CHECK1-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
	// CHECK1-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8			// CHECK1-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8
	// CHECK1-NEXT: [[CONV:%.]] = bitcast i64 [[I_ADDR]] to i32*			// CHECK1-NEXT: [[CONV:%.]] = bitcast i64 [[I_ADDR]] to i32*
	// CHECK1-NEXT: [[CONV1:%.]] = bitcast i64 [[N_ADDR]] to i32*			// CHECK1-NEXT: [[CONV1:%.]] = bitcast i64 [[N_ADDR]] to i32*
	// CHECK1-NEXT: [[TMP0:%.]] = load [1000 x i32], [1000 x i32]** [[A_ADDR]], align 8			// CHECK1-NEXT: [[TMP0:%.]] = load [1000 x i32], [1000 x i32]** [[A_ADDR]], align 8
	// CHECK1-NEXT: [[TMP1:%.]] = load i32, i32 [[CONV1]], align 4			// CHECK1-NEXT: [[TMP1:%.]] = load i32, i32 [[CONV1]], align 8
	// CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4			// CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
	// CHECK1-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4			// CHECK1-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4
	// CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0			// CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
	// CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1			// CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
	// CHECK1-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1			// CHECK1-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1
	// CHECK1-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4			// CHECK1-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4
	// CHECK1-NEXT: store i32 0, i32* [[I4]], align 4			// CHECK1-NEXT: store i32 0, i32* [[I4]], align 4
	// CHECK1-NEXT: [[TMP3:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4			// CHECK1-NEXT: [[TMP3:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4
	Show All 35 Lines
	// CHECK1-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK1-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK1-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64			// CHECK1-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64
	// CHECK1-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK1-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4
	// CHECK1-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64			// CHECK1-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
	// CHECK1-NEXT: [[TMP18:%.]] = load i32, i32 [[I5]], align 4			// CHECK1-NEXT: [[TMP18:%.]] = load i32, i32 [[I5]], align 4
	// CHECK1-NEXT: [[CONV8:%.]] = bitcast i64 [[I_CASTED]] to i32*			// CHECK1-NEXT: [[CONV8:%.]] = bitcast i64 [[I_CASTED]] to i32*
	// CHECK1-NEXT: store i32 [[TMP18]], i32* [[CONV8]], align 4			// CHECK1-NEXT: store i32 [[TMP18]], i32* [[CONV8]], align 4
	// CHECK1-NEXT: [[TMP19:%.]] = load i64, i64 [[I_CASTED]], align 8			// CHECK1-NEXT: [[TMP19:%.]] = load i64, i64 [[I_CASTED]], align 8
	// CHECK1-NEXT: [[TMP20:%.]] = load i32, i32 [[CONV1]], align 4			// CHECK1-NEXT: [[TMP20:%.]] = load i32, i32 [[CONV1]], align 8
	// CHECK1-NEXT: [[CONV9:%.]] = bitcast i64 [[N_CASTED]] to i32*			// CHECK1-NEXT: [[CONV9:%.]] = bitcast i64 [[N_CASTED]] to i32*
	// CHECK1-NEXT: store i32 [[TMP20]], i32* [[CONV9]], align 4			// CHECK1-NEXT: store i32 [[TMP20]], i32* [[CONV9]], align 4
	// CHECK1-NEXT: [[TMP21:%.]] = load i64, i64 [[N_CASTED]], align 8			// CHECK1-NEXT: [[TMP21:%.]] = load i64, i64 [[N_CASTED]], align 8
	// CHECK1-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 5, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i64, i64, [1000 x i32]) @.omp_outlined..1 to void (i32, i32, ...)), i64 [[TMP15]], i64 [[TMP17]], i64 [[TMP19]], i64 [[TMP21]], [1000 x i32] [[TMP0]])			// CHECK1-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 5, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i64, i64, [1000 x i32]) @.omp_outlined..1 to void (i32, i32, ...)), i64 [[TMP15]], i64 [[TMP17]], i64 [[TMP19]], i64 [[TMP21]], [1000 x i32] [[TMP0]])
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK1: omp.inner.for.inc:			// CHECK1: omp.inner.for.inc:
	// CHECK1-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK1-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK1-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4
	Show All 10 Lines
	// CHECK1-NEXT: [[TMP27:%.*]] = icmp ne i32 [[TMP26]], 0			// CHECK1-NEXT: [[TMP27:%.*]] = icmp ne i32 [[TMP26]], 0
	// CHECK1-NEXT: br i1 [[TMP27]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK1-NEXT: br i1 [[TMP27]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK1: .omp.final.then:			// CHECK1: .omp.final.then:
	// CHECK1-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4			// CHECK1-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4
	// CHECK1-NEXT: [[SUB10:%.*]] = sub nsw i32 [[TMP28]], 0			// CHECK1-NEXT: [[SUB10:%.*]] = sub nsw i32 [[TMP28]], 0
	// CHECK1-NEXT: [[DIV11:%.*]] = sdiv i32 [[SUB10]], 1			// CHECK1-NEXT: [[DIV11:%.*]] = sdiv i32 [[SUB10]], 1
	// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV11]], 1			// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV11]], 1
	// CHECK1-NEXT: [[ADD12:%.*]] = add nsw i32 0, [[MUL]]			// CHECK1-NEXT: [[ADD12:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK1-NEXT: store i32 [[ADD12]], i32* [[CONV]], align 4			// CHECK1-NEXT: store i32 [[ADD12]], i32* [[CONV]], align 8
	// CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]]			// CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]]
	// CHECK1: .omp.final.done:			// CHECK1: .omp.final.done:
	// CHECK1-NEXT: br label [[OMP_PRECOND_END]]			// CHECK1-NEXT: br label [[OMP_PRECOND_END]]
	// CHECK1: omp.precond.end:			// CHECK1: omp.precond.end:
	// CHECK1-NEXT: ret void			// CHECK1-NEXT: ret void
	//			//
	//			//
	// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1			// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1
	Show All 24 Lines
	// CHECK1-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8			// CHECK1-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
	// CHECK1-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8			// CHECK1-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
	// CHECK1-NEXT: store i64 [[I]], i64* [[I_ADDR]], align 8			// CHECK1-NEXT: store i64 [[I]], i64* [[I_ADDR]], align 8
	// CHECK1-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8			// CHECK1-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
	// CHECK1-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8			// CHECK1-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8
	// CHECK1-NEXT: [[CONV:%.]] = bitcast i64 [[I_ADDR]] to i32*			// CHECK1-NEXT: [[CONV:%.]] = bitcast i64 [[I_ADDR]] to i32*
	// CHECK1-NEXT: [[CONV1:%.]] = bitcast i64 [[N_ADDR]] to i32*			// CHECK1-NEXT: [[CONV1:%.]] = bitcast i64 [[N_ADDR]] to i32*
	// CHECK1-NEXT: [[TMP0:%.]] = load [1000 x i32], [1000 x i32]** [[A_ADDR]], align 8			// CHECK1-NEXT: [[TMP0:%.]] = load [1000 x i32], [1000 x i32]** [[A_ADDR]], align 8
	// CHECK1-NEXT: [[TMP1:%.]] = load i32, i32 [[CONV1]], align 4			// CHECK1-NEXT: [[TMP1:%.]] = load i32, i32 [[CONV1]], align 8
	// CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4			// CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
	// CHECK1-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4			// CHECK1-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4
	// CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0			// CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
	// CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1			// CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
	// CHECK1-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1			// CHECK1-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1
	// CHECK1-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4			// CHECK1-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4
	// CHECK1-NEXT: store i32 0, i32* [[I4]], align 4			// CHECK1-NEXT: store i32 0, i32* [[I4]], align 4
	// CHECK1-NEXT: [[TMP3:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4			// CHECK1-NEXT: [[TMP3:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4
	// CHECK1-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]]			// CHECK1-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]]
	// CHECK1-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.]], label [[OMP_PRECOND_END:%.]]			// CHECK1-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.]], label [[OMP_PRECOND_END:%.]]
	// CHECK1: omp.precond.then:			// CHECK1: omp.precond.then:
	// CHECK1-NEXT: [[ARRAYDECAY:%.]] = getelementptr inbounds [1000 x i32], [1000 x i32] [[TMP0]], i64 0, i64 0			// CHECK1-NEXT: [[ARRAYDECAY:%.]] = getelementptr inbounds [1000 x i32], [1000 x i32] [[TMP0]], i64 0, i64 0
	// CHECK1-NEXT: call void @llvm.assume(i1 true) [ "align"(i32* [[ARRAYDECAY]], i64 8) ]			// CHECK1-NEXT: call void @llvm.assume(i1 true) [ "align"(i32* [[ARRAYDECAY]], i64 8) ]
	// CHECK1-NEXT: [[TMP4:%.]] = load i32, i32 [[CONV]], align 4			// CHECK1-NEXT: [[TMP4:%.]] = load i32, i32 [[CONV]], align 8
	// CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTLINEAR_START]], align 4			// CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTLINEAR_START]], align 4
	// CHECK1-NEXT: [[TMP5:%.]] = load i32, i32 [[CONV1]], align 4			// CHECK1-NEXT: [[TMP5:%.]] = load i32, i32 [[CONV1]], align 8
	// CHECK1-NEXT: store i32 [[TMP5]], i32* [[DOTLINEAR_STEP]], align 4			// CHECK1-NEXT: store i32 [[TMP5]], i32* [[DOTLINEAR_STEP]], align 4
	// CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4			// CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
	// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2]], align 4			// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2]], align 4
	// CHECK1-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4			// CHECK1-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4
	// CHECK1-NEXT: [[TMP7:%.]] = load i64, i64 [[DOTPREVIOUS_LB__ADDR]], align 8			// CHECK1-NEXT: [[TMP7:%.]] = load i64, i64 [[DOTPREVIOUS_LB__ADDR]], align 8
	// CHECK1-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP7]] to i32			// CHECK1-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP7]] to i32
	// CHECK1-NEXT: [[TMP8:%.]] = load i64, i64 [[DOTPREVIOUS_UB__ADDR]], align 8			// CHECK1-NEXT: [[TMP8:%.]] = load i64, i64 [[DOTPREVIOUS_UB__ADDR]], align 8
	// CHECK1-NEXT: [[CONV6:%.*]] = trunc i64 [[TMP8]] to i32			// CHECK1-NEXT: [[CONV6:%.*]] = trunc i64 [[TMP8]] to i32
	▲ Show 20 Lines • Show All 55 Lines • ▼ Show 20 Lines
	// CHECK1-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0			// CHECK1-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0
	// CHECK1-NEXT: br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK1-NEXT: br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK1: .omp.final.then:			// CHECK1: .omp.final.then:
	// CHECK1-NEXT: [[TMP27:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4			// CHECK1-NEXT: [[TMP27:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4
	// CHECK1-NEXT: [[SUB12:%.*]] = sub nsw i32 [[TMP27]], 0			// CHECK1-NEXT: [[SUB12:%.*]] = sub nsw i32 [[TMP27]], 0
	// CHECK1-NEXT: [[DIV13:%.*]] = sdiv i32 [[SUB12]], 1			// CHECK1-NEXT: [[DIV13:%.*]] = sdiv i32 [[SUB12]], 1
	// CHECK1-NEXT: [[MUL14:%.*]] = mul nsw i32 [[DIV13]], 1			// CHECK1-NEXT: [[MUL14:%.*]] = mul nsw i32 [[DIV13]], 1
	// CHECK1-NEXT: [[ADD15:%.*]] = add nsw i32 0, [[MUL14]]			// CHECK1-NEXT: [[ADD15:%.*]] = add nsw i32 0, [[MUL14]]
	// CHECK1-NEXT: store i32 [[ADD15]], i32* [[CONV]], align 4			// CHECK1-NEXT: store i32 [[ADD15]], i32* [[CONV]], align 8
	// CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]]			// CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]]
	// CHECK1: .omp.final.done:			// CHECK1: .omp.final.done:
	// CHECK1-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK1-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK1-NEXT: [[TMP29:%.*]] = icmp ne i32 [[TMP28]], 0			// CHECK1-NEXT: [[TMP29:%.*]] = icmp ne i32 [[TMP28]], 0
	// CHECK1-NEXT: br i1 [[TMP29]], label [[DOTOMP_LINEAR_PU:%.]], label [[DOTOMP_LINEAR_PU_DONE:%.]]			// CHECK1-NEXT: br i1 [[TMP29]], label [[DOTOMP_LINEAR_PU:%.]], label [[DOTOMP_LINEAR_PU_DONE:%.]]
	// CHECK1: .omp.linear.pu:			// CHECK1: .omp.linear.pu:
	// CHECK1-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]]			// CHECK1-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]]
	// CHECK1: .omp.linear.pu.done:			// CHECK1: .omp.linear.pu.done:
	Show All 9 Lines
	// CHECK1-NEXT: [[A_ADDR:%.]] = alloca [1000 x i32], align 8			// CHECK1-NEXT: [[A_ADDR:%.]] = alloca [1000 x i32], align 8
	// CHECK1-NEXT: [[G_ADDR:%.]] = alloca i32, align 8			// CHECK1-NEXT: [[G_ADDR:%.]] = alloca i32, align 8
	// CHECK1-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8			// CHECK1-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8
	// CHECK1-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8			// CHECK1-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
	// CHECK1-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8			// CHECK1-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8
	// CHECK1-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8			// CHECK1-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8
	// CHECK1-NEXT: [[CONV:%.]] = bitcast i64 [[N_ADDR]] to i32*			// CHECK1-NEXT: [[CONV:%.]] = bitcast i64 [[N_ADDR]] to i32*
	// CHECK1-NEXT: [[TMP0:%.]] = load [1000 x i32], [1000 x i32]** [[A_ADDR]], align 8			// CHECK1-NEXT: [[TMP0:%.]] = load [1000 x i32], [1000 x i32]** [[A_ADDR]], align 8
	// CHECK1-NEXT: [[TMP1:%.]] = load i32, i32 [[CONV]], align 4			// CHECK1-NEXT: [[TMP1:%.]] = load i32, i32 [[CONV]], align 8
	// CHECK1-NEXT: [[CONV1:%.]] = bitcast i64 [[N_CASTED]] to i32*			// CHECK1-NEXT: [[CONV1:%.]] = bitcast i64 [[N_CASTED]] to i32*
	// CHECK1-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4			// CHECK1-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4
	// CHECK1-NEXT: [[TMP2:%.]] = load i64, i64 [[N_CASTED]], align 8			// CHECK1-NEXT: [[TMP2:%.]] = load i64, i64 [[N_CASTED]], align 8
	// CHECK1-NEXT: [[TMP3:%.]] = load i32, i32** [[G_ADDR]], align 8			// CHECK1-NEXT: [[TMP3:%.]] = load i32, i32** [[G_ADDR]], align 8
	// CHECK1-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB4]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i64, [1000 x i32], i32)* @.omp_outlined..2 to void (i32, i32, ...)), i64 [[TMP2]], [1000 x i32] [[TMP0]], i32* [[TMP3]])			// CHECK1-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB4]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i64, [1000 x i32], i32)* @.omp_outlined..2 to void (i32, i32, ...)), i64 [[TMP2]], [1000 x i32] [[TMP0]], i32* [[TMP3]])
	// CHECK1-NEXT: ret void			// CHECK1-NEXT: ret void
	//			//
	//			//
	Show All 18 Lines
	// CHECK1-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8			// CHECK1-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8
	// CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8			// CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
	// CHECK1-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8			// CHECK1-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
	// CHECK1-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8			// CHECK1-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8
	// CHECK1-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8			// CHECK1-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8
	// CHECK1-NEXT: [[CONV:%.]] = bitcast i64 [[N_ADDR]] to i32*			// CHECK1-NEXT: [[CONV:%.]] = bitcast i64 [[N_ADDR]] to i32*
	// CHECK1-NEXT: [[TMP0:%.]] = load [1000 x i32], [1000 x i32]** [[A_ADDR]], align 8			// CHECK1-NEXT: [[TMP0:%.]] = load [1000 x i32], [1000 x i32]** [[A_ADDR]], align 8
	// CHECK1-NEXT: [[TMP1:%.]] = load i32, i32 [[CONV]], align 4			// CHECK1-NEXT: [[TMP1:%.]] = load i32, i32 [[CONV]], align 8
	// CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4			// CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
	// CHECK1-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4			// CHECK1-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4
	// CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0			// CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
	// CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1			// CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
	// CHECK1-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1			// CHECK1-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
	// CHECK1-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4			// CHECK1-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4
	// CHECK1-NEXT: store i32 0, i32* [[I]], align 4			// CHECK1-NEXT: store i32 0, i32* [[I]], align 4
	// CHECK1-NEXT: [[TMP3:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4			// CHECK1-NEXT: [[TMP3:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4
	Show All 29 Lines
	// CHECK1-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !11			// CHECK1-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !11
	// CHECK1-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]]			// CHECK1-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]]
	// CHECK1-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK1-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK1: omp.inner.for.body:			// CHECK1: omp.inner.for.body:
	// CHECK1-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !11			// CHECK1-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !11
	// CHECK1-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64			// CHECK1-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64
	// CHECK1-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !11			// CHECK1-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !11
	// CHECK1-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64			// CHECK1-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
	// CHECK1-NEXT: [[TMP18:%.]] = load i32, i32 [[CONV]], align 4, !llvm.access.group !11			// CHECK1-NEXT: [[TMP18:%.]] = load i32, i32 [[CONV]], align 8, !llvm.access.group !11
	// CHECK1-NEXT: [[CONV6:%.]] = bitcast i64 [[N_CASTED]] to i32*			// CHECK1-NEXT: [[CONV6:%.]] = bitcast i64 [[N_CASTED]] to i32*
	// CHECK1-NEXT: store i32 [[TMP18]], i32* [[CONV6]], align 4, !llvm.access.group !11			// CHECK1-NEXT: store i32 [[TMP18]], i32* [[CONV6]], align 4, !llvm.access.group !11
	// CHECK1-NEXT: [[TMP19:%.]] = load i64, i64 [[N_CASTED]], align 8, !llvm.access.group !11			// CHECK1-NEXT: [[TMP19:%.]] = load i64, i64 [[N_CASTED]], align 8, !llvm.access.group !11
	// CHECK1-NEXT: [[TMP20:%.]] = load i32, i32** [[G_ADDR]], align 8, !llvm.access.group !11			// CHECK1-NEXT: [[TMP20:%.]] = load i32, i32** [[G_ADDR]], align 8, !llvm.access.group !11
	// CHECK1-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 5, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i64, [1000 x i32], i32)* @.omp_outlined..3 to void (i32, i32, ...)), i64 [[TMP15]], i64 [[TMP17]], i64 [[TMP19]], [1000 x i32] [[TMP0]], i32* [[TMP20]]), !llvm.access.group !11			// CHECK1-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 5, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i64, [1000 x i32], i32)* @.omp_outlined..3 to void (i32, i32, ...)), i64 [[TMP15]], i64 [[TMP17]], i64 [[TMP19]], [1000 x i32] [[TMP0]], i32* [[TMP20]]), !llvm.access.group !11
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK1: omp.inner.for.inc:			// CHECK1: omp.inner.for.inc:
	// CHECK1-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11			// CHECK1-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11
	▲ Show 20 Lines • Show All 48 Lines • ▼ Show 20 Lines
	// CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8			// CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
	// CHECK1-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8			// CHECK1-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
	// CHECK1-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8			// CHECK1-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
	// CHECK1-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8			// CHECK1-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
	// CHECK1-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8			// CHECK1-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8
	// CHECK1-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8			// CHECK1-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8
	// CHECK1-NEXT: [[CONV:%.]] = bitcast i64 [[N_ADDR]] to i32*			// CHECK1-NEXT: [[CONV:%.]] = bitcast i64 [[N_ADDR]] to i32*
	// CHECK1-NEXT: [[TMP0:%.]] = load [1000 x i32], [1000 x i32]** [[A_ADDR]], align 8			// CHECK1-NEXT: [[TMP0:%.]] = load [1000 x i32], [1000 x i32]** [[A_ADDR]], align 8
	// CHECK1-NEXT: [[TMP1:%.]] = load i32, i32 [[CONV]], align 4			// CHECK1-NEXT: [[TMP1:%.]] = load i32, i32 [[CONV]], align 8
	// CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4			// CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
	// CHECK1-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4			// CHECK1-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4
	// CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0			// CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
	// CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1			// CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
	// CHECK1-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1			// CHECK1-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
	// CHECK1-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4			// CHECK1-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4
	// CHECK1-NEXT: store i32 0, i32* [[I]], align 4			// CHECK1-NEXT: store i32 0, i32* [[I]], align 4
	// CHECK1-NEXT: [[TMP3:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4			// CHECK1-NEXT: [[TMP3:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4
	▲ Show 20 Lines • Show All 271 Lines • ▼ Show 20 Lines
	// CHECK2-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8			// CHECK2-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8
	// CHECK2-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8			// CHECK2-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
	// CHECK2-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8			// CHECK2-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8
	// CHECK2-NEXT: [[CONV:%.]] = bitcast i64 [[I_ADDR]] to i32*			// CHECK2-NEXT: [[CONV:%.]] = bitcast i64 [[I_ADDR]] to i32*
	// CHECK2-NEXT: [[CONV3:%.]] = bitcast i64 [[N_ADDR]] to i32*			// CHECK2-NEXT: [[CONV3:%.]] = bitcast i64 [[N_ADDR]] to i32*
	// CHECK2-NEXT: [[TMP1:%.]] = load [1000 x i32], [1000 x i32]** [[A_ADDR]], align 8			// CHECK2-NEXT: [[TMP1:%.]] = load [1000 x i32], [1000 x i32]** [[A_ADDR]], align 8
	// CHECK2-NEXT: [[CONV4:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__ADDR]] to i32*			// CHECK2-NEXT: [[CONV4:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__ADDR]] to i32*
	// CHECK2-NEXT: [[CONV5:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__ADDR2]] to i32*			// CHECK2-NEXT: [[CONV5:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__ADDR2]] to i32*
	// CHECK2-NEXT: [[TMP2:%.]] = load i32, i32 [[CONV4]], align 4			// CHECK2-NEXT: [[TMP2:%.]] = load i32, i32 [[CONV4]], align 8
	// CHECK2-NEXT: [[TMP3:%.]] = load i32, i32 [[CONV5]], align 4			// CHECK2-NEXT: [[TMP3:%.]] = load i32, i32 [[CONV5]], align 8
	// CHECK2-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB4]], i32 [[TMP0]], i32 [[TMP2]], i32 [[TMP3]])			// CHECK2-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB4]], i32 [[TMP0]], i32 [[TMP2]], i32 [[TMP3]])
	// CHECK2-NEXT: [[TMP4:%.]] = load i32, i32 [[CONV]], align 4			// CHECK2-NEXT: [[TMP4:%.]] = load i32, i32 [[CONV]], align 8
	// CHECK2-NEXT: [[CONV6:%.]] = bitcast i64 [[I_CASTED]] to i32*			// CHECK2-NEXT: [[CONV6:%.]] = bitcast i64 [[I_CASTED]] to i32*
	// CHECK2-NEXT: store i32 [[TMP4]], i32* [[CONV6]], align 4			// CHECK2-NEXT: store i32 [[TMP4]], i32* [[CONV6]], align 4
	// CHECK2-NEXT: [[TMP5:%.]] = load i64, i64 [[I_CASTED]], align 8			// CHECK2-NEXT: [[TMP5:%.]] = load i64, i64 [[I_CASTED]], align 8
	// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[CONV3]], align 4			// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[CONV3]], align 8
	// CHECK2-NEXT: [[CONV7:%.]] = bitcast i64 [[N_CASTED]] to i32*			// CHECK2-NEXT: [[CONV7:%.]] = bitcast i64 [[N_CASTED]] to i32*
	// CHECK2-NEXT: store i32 [[TMP6]], i32* [[CONV7]], align 4			// CHECK2-NEXT: store i32 [[TMP6]], i32* [[CONV7]], align 4
	// CHECK2-NEXT: [[TMP7:%.]] = load i64, i64 [[N_CASTED]], align 8			// CHECK2-NEXT: [[TMP7:%.]] = load i64, i64 [[N_CASTED]], align 8
	// CHECK2-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB4]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, [1000 x i32]) @.omp_outlined. to void (i32, i32, ...)), i64 [[TMP5]], i64 [[TMP7]], [1000 x i32] [[TMP1]])			// CHECK2-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB4]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, [1000 x i32]) @.omp_outlined. to void (i32, i32, ...)), i64 [[TMP5]], i64 [[TMP7]], [1000 x i32] [[TMP1]])
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined.			// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined.
	Show All 19 Lines
	// CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8			// CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
	// CHECK2-NEXT: store i64 [[I]], i64* [[I_ADDR]], align 8			// CHECK2-NEXT: store i64 [[I]], i64* [[I_ADDR]], align 8
	// CHECK2-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8			// CHECK2-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
	// CHECK2-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8			// CHECK2-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8
	// CHECK2-NEXT: [[CONV:%.]] = bitcast i64 [[I_ADDR]] to i32*			// CHECK2-NEXT: [[CONV:%.]] = bitcast i64 [[I_ADDR]] to i32*
	// CHECK2-NEXT: [[CONV1:%.]] = bitcast i64 [[N_ADDR]] to i32*			// CHECK2-NEXT: [[CONV1:%.]] = bitcast i64 [[N_ADDR]] to i32*
	// CHECK2-NEXT: [[TMP0:%.]] = load [1000 x i32], [1000 x i32]** [[A_ADDR]], align 8			// CHECK2-NEXT: [[TMP0:%.]] = load [1000 x i32], [1000 x i32]** [[A_ADDR]], align 8
	// CHECK2-NEXT: [[TMP1:%.]] = load i32, i32 [[CONV1]], align 4			// CHECK2-NEXT: [[TMP1:%.]] = load i32, i32 [[CONV1]], align 8
	// CHECK2-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4			// CHECK2-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
	// CHECK2-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4			// CHECK2-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4
	// CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0			// CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
	// CHECK2-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1			// CHECK2-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
	// CHECK2-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1			// CHECK2-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1
	// CHECK2-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4			// CHECK2-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4
	// CHECK2-NEXT: store i32 0, i32* [[I4]], align 4			// CHECK2-NEXT: store i32 0, i32* [[I4]], align 4
	// CHECK2-NEXT: [[TMP3:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4			// CHECK2-NEXT: [[TMP3:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4
	Show All 35 Lines
	// CHECK2-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK2-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK2-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64			// CHECK2-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64
	// CHECK2-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK2-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4
	// CHECK2-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64			// CHECK2-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
	// CHECK2-NEXT: [[TMP18:%.]] = load i32, i32 [[I5]], align 4			// CHECK2-NEXT: [[TMP18:%.]] = load i32, i32 [[I5]], align 4
	// CHECK2-NEXT: [[CONV8:%.]] = bitcast i64 [[I_CASTED]] to i32*			// CHECK2-NEXT: [[CONV8:%.]] = bitcast i64 [[I_CASTED]] to i32*
	// CHECK2-NEXT: store i32 [[TMP18]], i32* [[CONV8]], align 4			// CHECK2-NEXT: store i32 [[TMP18]], i32* [[CONV8]], align 4
	// CHECK2-NEXT: [[TMP19:%.]] = load i64, i64 [[I_CASTED]], align 8			// CHECK2-NEXT: [[TMP19:%.]] = load i64, i64 [[I_CASTED]], align 8
	// CHECK2-NEXT: [[TMP20:%.]] = load i32, i32 [[CONV1]], align 4			// CHECK2-NEXT: [[TMP20:%.]] = load i32, i32 [[CONV1]], align 8
	// CHECK2-NEXT: [[CONV9:%.]] = bitcast i64 [[N_CASTED]] to i32*			// CHECK2-NEXT: [[CONV9:%.]] = bitcast i64 [[N_CASTED]] to i32*
	// CHECK2-NEXT: store i32 [[TMP20]], i32* [[CONV9]], align 4			// CHECK2-NEXT: store i32 [[TMP20]], i32* [[CONV9]], align 4
	// CHECK2-NEXT: [[TMP21:%.]] = load i64, i64 [[N_CASTED]], align 8			// CHECK2-NEXT: [[TMP21:%.]] = load i64, i64 [[N_CASTED]], align 8
	// CHECK2-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 5, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i64, i64, [1000 x i32]) @.omp_outlined..1 to void (i32, i32, ...)), i64 [[TMP15]], i64 [[TMP17]], i64 [[TMP19]], i64 [[TMP21]], [1000 x i32] [[TMP0]])			// CHECK2-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 5, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i64, i64, [1000 x i32]) @.omp_outlined..1 to void (i32, i32, ...)), i64 [[TMP15]], i64 [[TMP17]], i64 [[TMP19]], i64 [[TMP21]], [1000 x i32] [[TMP0]])
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK2: omp.inner.for.inc:			// CHECK2: omp.inner.for.inc:
	// CHECK2-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK2-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK2-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4
	Show All 10 Lines
	// CHECK2-NEXT: [[TMP27:%.*]] = icmp ne i32 [[TMP26]], 0			// CHECK2-NEXT: [[TMP27:%.*]] = icmp ne i32 [[TMP26]], 0
	// CHECK2-NEXT: br i1 [[TMP27]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK2-NEXT: br i1 [[TMP27]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK2: .omp.final.then:			// CHECK2: .omp.final.then:
	// CHECK2-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4			// CHECK2-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4
	// CHECK2-NEXT: [[SUB10:%.*]] = sub nsw i32 [[TMP28]], 0			// CHECK2-NEXT: [[SUB10:%.*]] = sub nsw i32 [[TMP28]], 0
	// CHECK2-NEXT: [[DIV11:%.*]] = sdiv i32 [[SUB10]], 1			// CHECK2-NEXT: [[DIV11:%.*]] = sdiv i32 [[SUB10]], 1
	// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV11]], 1			// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV11]], 1
	// CHECK2-NEXT: [[ADD12:%.*]] = add nsw i32 0, [[MUL]]			// CHECK2-NEXT: [[ADD12:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK2-NEXT: store i32 [[ADD12]], i32* [[CONV]], align 4			// CHECK2-NEXT: store i32 [[ADD12]], i32* [[CONV]], align 8
	// CHECK2-NEXT: br label [[DOTOMP_FINAL_DONE]]			// CHECK2-NEXT: br label [[DOTOMP_FINAL_DONE]]
	// CHECK2: .omp.final.done:			// CHECK2: .omp.final.done:
	// CHECK2-NEXT: br label [[OMP_PRECOND_END]]			// CHECK2-NEXT: br label [[OMP_PRECOND_END]]
	// CHECK2: omp.precond.end:			// CHECK2: omp.precond.end:
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..1			// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..1
	Show All 24 Lines
	// CHECK2-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8			// CHECK2-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
	// CHECK2-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8			// CHECK2-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
	// CHECK2-NEXT: store i64 [[I]], i64* [[I_ADDR]], align 8			// CHECK2-NEXT: store i64 [[I]], i64* [[I_ADDR]], align 8
	// CHECK2-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8			// CHECK2-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
	// CHECK2-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8			// CHECK2-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8
	// CHECK2-NEXT: [[CONV:%.]] = bitcast i64 [[I_ADDR]] to i32*			// CHECK2-NEXT: [[CONV:%.]] = bitcast i64 [[I_ADDR]] to i32*
	// CHECK2-NEXT: [[CONV1:%.]] = bitcast i64 [[N_ADDR]] to i32*			// CHECK2-NEXT: [[CONV1:%.]] = bitcast i64 [[N_ADDR]] to i32*
	// CHECK2-NEXT: [[TMP0:%.]] = load [1000 x i32], [1000 x i32]** [[A_ADDR]], align 8			// CHECK2-NEXT: [[TMP0:%.]] = load [1000 x i32], [1000 x i32]** [[A_ADDR]], align 8
	// CHECK2-NEXT: [[TMP1:%.]] = load i32, i32 [[CONV1]], align 4			// CHECK2-NEXT: [[TMP1:%.]] = load i32, i32 [[CONV1]], align 8
	// CHECK2-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4			// CHECK2-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
	// CHECK2-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4			// CHECK2-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4
	// CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0			// CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
	// CHECK2-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1			// CHECK2-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
	// CHECK2-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1			// CHECK2-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1
	// CHECK2-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4			// CHECK2-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4
	// CHECK2-NEXT: store i32 0, i32* [[I4]], align 4			// CHECK2-NEXT: store i32 0, i32* [[I4]], align 4
	// CHECK2-NEXT: [[TMP3:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4			// CHECK2-NEXT: [[TMP3:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4
	// CHECK2-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]]			// CHECK2-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]]
	// CHECK2-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.]], label [[OMP_PRECOND_END:%.]]			// CHECK2-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.]], label [[OMP_PRECOND_END:%.]]
	// CHECK2: omp.precond.then:			// CHECK2: omp.precond.then:
	// CHECK2-NEXT: [[ARRAYDECAY:%.]] = getelementptr inbounds [1000 x i32], [1000 x i32] [[TMP0]], i64 0, i64 0			// CHECK2-NEXT: [[ARRAYDECAY:%.]] = getelementptr inbounds [1000 x i32], [1000 x i32] [[TMP0]], i64 0, i64 0
	// CHECK2-NEXT: call void @llvm.assume(i1 true) [ "align"(i32* [[ARRAYDECAY]], i64 8) ]			// CHECK2-NEXT: call void @llvm.assume(i1 true) [ "align"(i32* [[ARRAYDECAY]], i64 8) ]
	// CHECK2-NEXT: [[TMP4:%.]] = load i32, i32 [[CONV]], align 4			// CHECK2-NEXT: [[TMP4:%.]] = load i32, i32 [[CONV]], align 8
	// CHECK2-NEXT: store i32 [[TMP4]], i32* [[DOTLINEAR_START]], align 4			// CHECK2-NEXT: store i32 [[TMP4]], i32* [[DOTLINEAR_START]], align 4
	// CHECK2-NEXT: [[TMP5:%.]] = load i32, i32 [[CONV1]], align 4			// CHECK2-NEXT: [[TMP5:%.]] = load i32, i32 [[CONV1]], align 8
	// CHECK2-NEXT: store i32 [[TMP5]], i32* [[DOTLINEAR_STEP]], align 4			// CHECK2-NEXT: store i32 [[TMP5]], i32* [[DOTLINEAR_STEP]], align 4
	// CHECK2-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4			// CHECK2-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
	// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2]], align 4			// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2]], align 4
	// CHECK2-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4			// CHECK2-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4
	// CHECK2-NEXT: [[TMP7:%.]] = load i64, i64 [[DOTPREVIOUS_LB__ADDR]], align 8			// CHECK2-NEXT: [[TMP7:%.]] = load i64, i64 [[DOTPREVIOUS_LB__ADDR]], align 8
	// CHECK2-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP7]] to i32			// CHECK2-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP7]] to i32
	// CHECK2-NEXT: [[TMP8:%.]] = load i64, i64 [[DOTPREVIOUS_UB__ADDR]], align 8			// CHECK2-NEXT: [[TMP8:%.]] = load i64, i64 [[DOTPREVIOUS_UB__ADDR]], align 8
	// CHECK2-NEXT: [[CONV6:%.*]] = trunc i64 [[TMP8]] to i32			// CHECK2-NEXT: [[CONV6:%.*]] = trunc i64 [[TMP8]] to i32
	▲ Show 20 Lines • Show All 55 Lines • ▼ Show 20 Lines
	// CHECK2-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0			// CHECK2-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0
	// CHECK2-NEXT: br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK2-NEXT: br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK2: .omp.final.then:			// CHECK2: .omp.final.then:
	// CHECK2-NEXT: [[TMP27:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4			// CHECK2-NEXT: [[TMP27:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4
	// CHECK2-NEXT: [[SUB12:%.*]] = sub nsw i32 [[TMP27]], 0			// CHECK2-NEXT: [[SUB12:%.*]] = sub nsw i32 [[TMP27]], 0
	// CHECK2-NEXT: [[DIV13:%.*]] = sdiv i32 [[SUB12]], 1			// CHECK2-NEXT: [[DIV13:%.*]] = sdiv i32 [[SUB12]], 1
	// CHECK2-NEXT: [[MUL14:%.*]] = mul nsw i32 [[DIV13]], 1			// CHECK2-NEXT: [[MUL14:%.*]] = mul nsw i32 [[DIV13]], 1
	// CHECK2-NEXT: [[ADD15:%.*]] = add nsw i32 0, [[MUL14]]			// CHECK2-NEXT: [[ADD15:%.*]] = add nsw i32 0, [[MUL14]]
	// CHECK2-NEXT: store i32 [[ADD15]], i32* [[CONV]], align 4			// CHECK2-NEXT: store i32 [[ADD15]], i32* [[CONV]], align 8
	// CHECK2-NEXT: br label [[DOTOMP_FINAL_DONE]]			// CHECK2-NEXT: br label [[DOTOMP_FINAL_DONE]]
	// CHECK2: .omp.final.done:			// CHECK2: .omp.final.done:
	// CHECK2-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK2-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK2-NEXT: [[TMP29:%.*]] = icmp ne i32 [[TMP28]], 0			// CHECK2-NEXT: [[TMP29:%.*]] = icmp ne i32 [[TMP28]], 0
	// CHECK2-NEXT: br i1 [[TMP29]], label [[DOTOMP_LINEAR_PU:%.]], label [[DOTOMP_LINEAR_PU_DONE:%.]]			// CHECK2-NEXT: br i1 [[TMP29]], label [[DOTOMP_LINEAR_PU:%.]], label [[DOTOMP_LINEAR_PU_DONE:%.]]
	// CHECK2: .omp.linear.pu:			// CHECK2: .omp.linear.pu:
	// CHECK2-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]]			// CHECK2-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]]
	// CHECK2: .omp.linear.pu.done:			// CHECK2: .omp.linear.pu.done:
	Show All 9 Lines
	// CHECK2-NEXT: [[A_ADDR:%.]] = alloca [1000 x i32], align 8			// CHECK2-NEXT: [[A_ADDR:%.]] = alloca [1000 x i32], align 8
	// CHECK2-NEXT: [[G_ADDR:%.]] = alloca i32, align 8			// CHECK2-NEXT: [[G_ADDR:%.]] = alloca i32, align 8
	// CHECK2-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8			// CHECK2-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8
	// CHECK2-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8			// CHECK2-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
	// CHECK2-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8			// CHECK2-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8
	// CHECK2-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8			// CHECK2-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8
	// CHECK2-NEXT: [[CONV:%.]] = bitcast i64 [[N_ADDR]] to i32*			// CHECK2-NEXT: [[CONV:%.]] = bitcast i64 [[N_ADDR]] to i32*
	// CHECK2-NEXT: [[TMP0:%.]] = load [1000 x i32], [1000 x i32]** [[A_ADDR]], align 8			// CHECK2-NEXT: [[TMP0:%.]] = load [1000 x i32], [1000 x i32]** [[A_ADDR]], align 8
	// CHECK2-NEXT: [[TMP1:%.]] = load i32, i32 [[CONV]], align 4			// CHECK2-NEXT: [[TMP1:%.]] = load i32, i32 [[CONV]], align 8
	// CHECK2-NEXT: [[CONV1:%.]] = bitcast i64 [[N_CASTED]] to i32*			// CHECK2-NEXT: [[CONV1:%.]] = bitcast i64 [[N_CASTED]] to i32*
	// CHECK2-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4			// CHECK2-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4
	// CHECK2-NEXT: [[TMP2:%.]] = load i64, i64 [[N_CASTED]], align 8			// CHECK2-NEXT: [[TMP2:%.]] = load i64, i64 [[N_CASTED]], align 8
	// CHECK2-NEXT: [[TMP3:%.]] = load i32, i32** [[G_ADDR]], align 8			// CHECK2-NEXT: [[TMP3:%.]] = load i32, i32** [[G_ADDR]], align 8
	// CHECK2-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB4]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i64, [1000 x i32], i32)* @.omp_outlined..2 to void (i32, i32, ...)), i64 [[TMP2]], [1000 x i32] [[TMP0]], i32* [[TMP3]])			// CHECK2-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB4]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i64, [1000 x i32], i32)* @.omp_outlined..2 to void (i32, i32, ...)), i64 [[TMP2]], [1000 x i32] [[TMP0]], i32* [[TMP3]])
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	//			//
	//			//
	Show All 18 Lines
	// CHECK2-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8			// CHECK2-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8
	// CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8			// CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
	// CHECK2-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8			// CHECK2-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
	// CHECK2-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8			// CHECK2-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8
	// CHECK2-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8			// CHECK2-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8
	// CHECK2-NEXT: [[CONV:%.]] = bitcast i64 [[N_ADDR]] to i32*			// CHECK2-NEXT: [[CONV:%.]] = bitcast i64 [[N_ADDR]] to i32*
	// CHECK2-NEXT: [[TMP0:%.]] = load [1000 x i32], [1000 x i32]** [[A_ADDR]], align 8			// CHECK2-NEXT: [[TMP0:%.]] = load [1000 x i32], [1000 x i32]** [[A_ADDR]], align 8
	// CHECK2-NEXT: [[TMP1:%.]] = load i32, i32 [[CONV]], align 4			// CHECK2-NEXT: [[TMP1:%.]] = load i32, i32 [[CONV]], align 8
	// CHECK2-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4			// CHECK2-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
	// CHECK2-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4			// CHECK2-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4
	// CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0			// CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
	// CHECK2-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1			// CHECK2-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
	// CHECK2-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1			// CHECK2-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
	// CHECK2-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4			// CHECK2-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4
	// CHECK2-NEXT: store i32 0, i32* [[I]], align 4			// CHECK2-NEXT: store i32 0, i32* [[I]], align 4
	// CHECK2-NEXT: [[TMP3:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4			// CHECK2-NEXT: [[TMP3:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4
	Show All 29 Lines
	// CHECK2-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !11			// CHECK2-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !11
	// CHECK2-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]]			// CHECK2-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]]
	// CHECK2-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK2-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK2: omp.inner.for.body:			// CHECK2: omp.inner.for.body:
	// CHECK2-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !11			// CHECK2-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !11
	// CHECK2-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64			// CHECK2-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64
	// CHECK2-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !11			// CHECK2-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !11
	// CHECK2-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64			// CHECK2-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
	// CHECK2-NEXT: [[TMP18:%.]] = load i32, i32 [[CONV]], align 4, !llvm.access.group !11			// CHECK2-NEXT: [[TMP18:%.]] = load i32, i32 [[CONV]], align 8, !llvm.access.group !11
	// CHECK2-NEXT: [[CONV6:%.]] = bitcast i64 [[N_CASTED]] to i32*			// CHECK2-NEXT: [[CONV6:%.]] = bitcast i64 [[N_CASTED]] to i32*
	// CHECK2-NEXT: store i32 [[TMP18]], i32* [[CONV6]], align 4, !llvm.access.group !11			// CHECK2-NEXT: store i32 [[TMP18]], i32* [[CONV6]], align 4, !llvm.access.group !11
	// CHECK2-NEXT: [[TMP19:%.]] = load i64, i64 [[N_CASTED]], align 8, !llvm.access.group !11			// CHECK2-NEXT: [[TMP19:%.]] = load i64, i64 [[N_CASTED]], align 8, !llvm.access.group !11
	// CHECK2-NEXT: [[TMP20:%.]] = load i32, i32** [[G_ADDR]], align 8, !llvm.access.group !11			// CHECK2-NEXT: [[TMP20:%.]] = load i32, i32** [[G_ADDR]], align 8, !llvm.access.group !11
	// CHECK2-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 5, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i64, [1000 x i32], i32)* @.omp_outlined..3 to void (i32, i32, ...)), i64 [[TMP15]], i64 [[TMP17]], i64 [[TMP19]], [1000 x i32] [[TMP0]], i32* [[TMP20]]), !llvm.access.group !11			// CHECK2-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 5, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i64, [1000 x i32], i32)* @.omp_outlined..3 to void (i32, i32, ...)), i64 [[TMP15]], i64 [[TMP17]], i64 [[TMP19]], [1000 x i32] [[TMP0]], i32* [[TMP20]]), !llvm.access.group !11
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK2: omp.inner.for.inc:			// CHECK2: omp.inner.for.inc:
	// CHECK2-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11			// CHECK2-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11
	▲ Show 20 Lines • Show All 48 Lines • ▼ Show 20 Lines
	// CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8			// CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
	// CHECK2-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8			// CHECK2-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
	// CHECK2-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8			// CHECK2-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
	// CHECK2-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8			// CHECK2-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
	// CHECK2-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8			// CHECK2-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8
	// CHECK2-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8			// CHECK2-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8
	// CHECK2-NEXT: [[CONV:%.]] = bitcast i64 [[N_ADDR]] to i32*			// CHECK2-NEXT: [[CONV:%.]] = bitcast i64 [[N_ADDR]] to i32*
	// CHECK2-NEXT: [[TMP0:%.]] = load [1000 x i32], [1000 x i32]** [[A_ADDR]], align 8			// CHECK2-NEXT: [[TMP0:%.]] = load [1000 x i32], [1000 x i32]** [[A_ADDR]], align 8
	// CHECK2-NEXT: [[TMP1:%.]] = load i32, i32 [[CONV]], align 4			// CHECK2-NEXT: [[TMP1:%.]] = load i32, i32 [[CONV]], align 8
	// CHECK2-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4			// CHECK2-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
	// CHECK2-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4			// CHECK2-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4
	// CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0			// CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
	// CHECK2-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1			// CHECK2-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
	// CHECK2-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1			// CHECK2-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
	// CHECK2-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4			// CHECK2-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4
	// CHECK2-NEXT: store i32 0, i32* [[I]], align 4			// CHECK2-NEXT: store i32 0, i32* [[I]], align 4
	// CHECK2-NEXT: [[TMP3:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4			// CHECK2-NEXT: [[TMP3:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4
	▲ Show 20 Lines • Show All 2,063 Lines • ▼ Show 20 Lines
	// CHECK9-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8			// CHECK9-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8
	// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8			// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
	// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8			// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8
	// CHECK9-NEXT: [[CONV:%.]] = bitcast i64 [[I_ADDR]] to i32*			// CHECK9-NEXT: [[CONV:%.]] = bitcast i64 [[I_ADDR]] to i32*
	// CHECK9-NEXT: [[CONV3:%.]] = bitcast i64 [[N_ADDR]] to i32*			// CHECK9-NEXT: [[CONV3:%.]] = bitcast i64 [[N_ADDR]] to i32*
	// CHECK9-NEXT: [[TMP1:%.]] = load [1000 x i32], [1000 x i32]** [[A_ADDR]], align 8			// CHECK9-NEXT: [[TMP1:%.]] = load [1000 x i32], [1000 x i32]** [[A_ADDR]], align 8
	// CHECK9-NEXT: [[CONV4:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__ADDR]] to i32*			// CHECK9-NEXT: [[CONV4:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__ADDR]] to i32*
	// CHECK9-NEXT: [[CONV5:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__ADDR2]] to i32*			// CHECK9-NEXT: [[CONV5:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__ADDR2]] to i32*
	// CHECK9-NEXT: [[TMP2:%.]] = load i32, i32 [[CONV4]], align 4			// CHECK9-NEXT: [[TMP2:%.]] = load i32, i32 [[CONV4]], align 8
	// CHECK9-NEXT: [[TMP3:%.]] = load i32, i32 [[CONV5]], align 4			// CHECK9-NEXT: [[TMP3:%.]] = load i32, i32 [[CONV5]], align 8
	// CHECK9-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB4]], i32 [[TMP0]], i32 [[TMP2]], i32 [[TMP3]])			// CHECK9-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB4]], i32 [[TMP0]], i32 [[TMP2]], i32 [[TMP3]])
	// CHECK9-NEXT: [[TMP4:%.]] = load i32, i32 [[CONV]], align 4			// CHECK9-NEXT: [[TMP4:%.]] = load i32, i32 [[CONV]], align 8
	// CHECK9-NEXT: [[CONV6:%.]] = bitcast i64 [[I_CASTED]] to i32*			// CHECK9-NEXT: [[CONV6:%.]] = bitcast i64 [[I_CASTED]] to i32*
	// CHECK9-NEXT: store i32 [[TMP4]], i32* [[CONV6]], align 4			// CHECK9-NEXT: store i32 [[TMP4]], i32* [[CONV6]], align 4
	// CHECK9-NEXT: [[TMP5:%.]] = load i64, i64 [[I_CASTED]], align 8			// CHECK9-NEXT: [[TMP5:%.]] = load i64, i64 [[I_CASTED]], align 8
	// CHECK9-NEXT: [[TMP6:%.]] = load i32, i32 [[CONV3]], align 4			// CHECK9-NEXT: [[TMP6:%.]] = load i32, i32 [[CONV3]], align 8
	// CHECK9-NEXT: [[CONV7:%.]] = bitcast i64 [[N_CASTED]] to i32*			// CHECK9-NEXT: [[CONV7:%.]] = bitcast i64 [[N_CASTED]] to i32*
	// CHECK9-NEXT: store i32 [[TMP6]], i32* [[CONV7]], align 4			// CHECK9-NEXT: store i32 [[TMP6]], i32* [[CONV7]], align 4
	// CHECK9-NEXT: [[TMP7:%.]] = load i64, i64 [[N_CASTED]], align 8			// CHECK9-NEXT: [[TMP7:%.]] = load i64, i64 [[N_CASTED]], align 8
	// CHECK9-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB4]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, [1000 x i32]) @.omp_outlined. to void (i32, i32, ...)), i64 [[TMP5]], i64 [[TMP7]], [1000 x i32] [[TMP1]])			// CHECK9-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB4]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, [1000 x i32]) @.omp_outlined. to void (i32, i32, ...)), i64 [[TMP5]], i64 [[TMP7]], [1000 x i32] [[TMP1]])
	// CHECK9-NEXT: ret void			// CHECK9-NEXT: ret void
	//			//
	//			//
	// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined.			// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined.
	Show All 19 Lines
	// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8			// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
	// CHECK9-NEXT: store i64 [[I]], i64* [[I_ADDR]], align 8			// CHECK9-NEXT: store i64 [[I]], i64* [[I_ADDR]], align 8
	// CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8			// CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
	// CHECK9-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8			// CHECK9-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8
	// CHECK9-NEXT: [[CONV:%.]] = bitcast i64 [[I_ADDR]] to i32*			// CHECK9-NEXT: [[CONV:%.]] = bitcast i64 [[I_ADDR]] to i32*
	// CHECK9-NEXT: [[CONV1:%.]] = bitcast i64 [[N_ADDR]] to i32*			// CHECK9-NEXT: [[CONV1:%.]] = bitcast i64 [[N_ADDR]] to i32*
	// CHECK9-NEXT: [[TMP0:%.]] = load [1000 x i32], [1000 x i32]** [[A_ADDR]], align 8			// CHECK9-NEXT: [[TMP0:%.]] = load [1000 x i32], [1000 x i32]** [[A_ADDR]], align 8
	// CHECK9-NEXT: [[TMP1:%.]] = load i32, i32 [[CONV1]], align 4			// CHECK9-NEXT: [[TMP1:%.]] = load i32, i32 [[CONV1]], align 8
	// CHECK9-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4			// CHECK9-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
	// CHECK9-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4			// CHECK9-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4
	// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0			// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
	// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1			// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
	// CHECK9-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1			// CHECK9-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1
	// CHECK9-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4			// CHECK9-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4
	// CHECK9-NEXT: store i32 0, i32* [[I4]], align 4			// CHECK9-NEXT: store i32 0, i32* [[I4]], align 4
	// CHECK9-NEXT: [[TMP3:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4			// CHECK9-NEXT: [[TMP3:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4
	Show All 35 Lines
	// CHECK9-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK9-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK9-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64			// CHECK9-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64
	// CHECK9-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK9-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4
	// CHECK9-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64			// CHECK9-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
	// CHECK9-NEXT: [[TMP18:%.]] = load i32, i32 [[I5]], align 4			// CHECK9-NEXT: [[TMP18:%.]] = load i32, i32 [[I5]], align 4
	// CHECK9-NEXT: [[CONV8:%.]] = bitcast i64 [[I_CASTED]] to i32*			// CHECK9-NEXT: [[CONV8:%.]] = bitcast i64 [[I_CASTED]] to i32*
	// CHECK9-NEXT: store i32 [[TMP18]], i32* [[CONV8]], align 4			// CHECK9-NEXT: store i32 [[TMP18]], i32* [[CONV8]], align 4
	// CHECK9-NEXT: [[TMP19:%.]] = load i64, i64 [[I_CASTED]], align 8			// CHECK9-NEXT: [[TMP19:%.]] = load i64, i64 [[I_CASTED]], align 8
	// CHECK9-NEXT: [[TMP20:%.]] = load i32, i32 [[CONV1]], align 4			// CHECK9-NEXT: [[TMP20:%.]] = load i32, i32 [[CONV1]], align 8
	// CHECK9-NEXT: [[CONV9:%.]] = bitcast i64 [[N_CASTED]] to i32*			// CHECK9-NEXT: [[CONV9:%.]] = bitcast i64 [[N_CASTED]] to i32*
	// CHECK9-NEXT: store i32 [[TMP20]], i32* [[CONV9]], align 4			// CHECK9-NEXT: store i32 [[TMP20]], i32* [[CONV9]], align 4
	// CHECK9-NEXT: [[TMP21:%.]] = load i64, i64 [[N_CASTED]], align 8			// CHECK9-NEXT: [[TMP21:%.]] = load i64, i64 [[N_CASTED]], align 8
	// CHECK9-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 5, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i64, i64, [1000 x i32]) @.omp_outlined..1 to void (i32, i32, ...)), i64 [[TMP15]], i64 [[TMP17]], i64 [[TMP19]], i64 [[TMP21]], [1000 x i32] [[TMP0]])			// CHECK9-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 5, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i64, i64, [1000 x i32]) @.omp_outlined..1 to void (i32, i32, ...)), i64 [[TMP15]], i64 [[TMP17]], i64 [[TMP19]], i64 [[TMP21]], [1000 x i32] [[TMP0]])
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK9: omp.inner.for.inc:			// CHECK9: omp.inner.for.inc:
	// CHECK9-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK9-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK9-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4
	Show All 10 Lines
	// CHECK9-NEXT: [[TMP27:%.*]] = icmp ne i32 [[TMP26]], 0			// CHECK9-NEXT: [[TMP27:%.*]] = icmp ne i32 [[TMP26]], 0
	// CHECK9-NEXT: br i1 [[TMP27]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK9-NEXT: br i1 [[TMP27]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK9: .omp.final.then:			// CHECK9: .omp.final.then:
	// CHECK9-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4			// CHECK9-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4
	// CHECK9-NEXT: [[SUB10:%.*]] = sub nsw i32 [[TMP28]], 0			// CHECK9-NEXT: [[SUB10:%.*]] = sub nsw i32 [[TMP28]], 0
	// CHECK9-NEXT: [[DIV11:%.*]] = sdiv i32 [[SUB10]], 1			// CHECK9-NEXT: [[DIV11:%.*]] = sdiv i32 [[SUB10]], 1
	// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV11]], 1			// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV11]], 1
	// CHECK9-NEXT: [[ADD12:%.*]] = add nsw i32 0, [[MUL]]			// CHECK9-NEXT: [[ADD12:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK9-NEXT: store i32 [[ADD12]], i32* [[CONV]], align 4			// CHECK9-NEXT: store i32 [[ADD12]], i32* [[CONV]], align 8
	// CHECK9-NEXT: br label [[DOTOMP_FINAL_DONE]]			// CHECK9-NEXT: br label [[DOTOMP_FINAL_DONE]]
	// CHECK9: .omp.final.done:			// CHECK9: .omp.final.done:
	// CHECK9-NEXT: br label [[OMP_PRECOND_END]]			// CHECK9-NEXT: br label [[OMP_PRECOND_END]]
	// CHECK9: omp.precond.end:			// CHECK9: omp.precond.end:
	// CHECK9-NEXT: ret void			// CHECK9-NEXT: ret void
	//			//
	//			//
	// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1			// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1
	Show All 24 Lines
	// CHECK9-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8			// CHECK9-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
	// CHECK9-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8			// CHECK9-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
	// CHECK9-NEXT: store i64 [[I]], i64* [[I_ADDR]], align 8			// CHECK9-NEXT: store i64 [[I]], i64* [[I_ADDR]], align 8
	// CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8			// CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
	// CHECK9-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8			// CHECK9-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8
	// CHECK9-NEXT: [[CONV:%.]] = bitcast i64 [[I_ADDR]] to i32*			// CHECK9-NEXT: [[CONV:%.]] = bitcast i64 [[I_ADDR]] to i32*
	// CHECK9-NEXT: [[CONV1:%.]] = bitcast i64 [[N_ADDR]] to i32*			// CHECK9-NEXT: [[CONV1:%.]] = bitcast i64 [[N_ADDR]] to i32*
	// CHECK9-NEXT: [[TMP0:%.]] = load [1000 x i32], [1000 x i32]** [[A_ADDR]], align 8			// CHECK9-NEXT: [[TMP0:%.]] = load [1000 x i32], [1000 x i32]** [[A_ADDR]], align 8
	// CHECK9-NEXT: [[TMP1:%.]] = load i32, i32 [[CONV1]], align 4			// CHECK9-NEXT: [[TMP1:%.]] = load i32, i32 [[CONV1]], align 8
	// CHECK9-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4			// CHECK9-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
	// CHECK9-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4			// CHECK9-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4
	// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0			// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
	// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1			// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
	// CHECK9-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1			// CHECK9-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1
	// CHECK9-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4			// CHECK9-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4
	// CHECK9-NEXT: store i32 0, i32* [[I4]], align 4			// CHECK9-NEXT: store i32 0, i32* [[I4]], align 4
	// CHECK9-NEXT: [[TMP3:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4			// CHECK9-NEXT: [[TMP3:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4
	// CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]]			// CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]]
	// CHECK9-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.]], label [[OMP_PRECOND_END:%.]]			// CHECK9-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.]], label [[OMP_PRECOND_END:%.]]
	// CHECK9: omp.precond.then:			// CHECK9: omp.precond.then:
	// CHECK9-NEXT: [[ARRAYDECAY:%.]] = getelementptr inbounds [1000 x i32], [1000 x i32] [[TMP0]], i64 0, i64 0			// CHECK9-NEXT: [[ARRAYDECAY:%.]] = getelementptr inbounds [1000 x i32], [1000 x i32] [[TMP0]], i64 0, i64 0
	// CHECK9-NEXT: call void @llvm.assume(i1 true) [ "align"(i32* [[ARRAYDECAY]], i64 8) ]			// CHECK9-NEXT: call void @llvm.assume(i1 true) [ "align"(i32* [[ARRAYDECAY]], i64 8) ]
	// CHECK9-NEXT: [[TMP4:%.]] = load i32, i32 [[CONV]], align 4			// CHECK9-NEXT: [[TMP4:%.]] = load i32, i32 [[CONV]], align 8
	// CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTLINEAR_START]], align 4			// CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTLINEAR_START]], align 4
	// CHECK9-NEXT: [[TMP5:%.]] = load i32, i32 [[CONV1]], align 4			// CHECK9-NEXT: [[TMP5:%.]] = load i32, i32 [[CONV1]], align 8
	// CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTLINEAR_STEP]], align 4			// CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTLINEAR_STEP]], align 4
	// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4			// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
	// CHECK9-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2]], align 4			// CHECK9-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2]], align 4
	// CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4			// CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4
	// CHECK9-NEXT: [[TMP7:%.]] = load i64, i64 [[DOTPREVIOUS_LB__ADDR]], align 8			// CHECK9-NEXT: [[TMP7:%.]] = load i64, i64 [[DOTPREVIOUS_LB__ADDR]], align 8
	// CHECK9-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP7]] to i32			// CHECK9-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP7]] to i32
	// CHECK9-NEXT: [[TMP8:%.]] = load i64, i64 [[DOTPREVIOUS_UB__ADDR]], align 8			// CHECK9-NEXT: [[TMP8:%.]] = load i64, i64 [[DOTPREVIOUS_UB__ADDR]], align 8
	// CHECK9-NEXT: [[CONV6:%.*]] = trunc i64 [[TMP8]] to i32			// CHECK9-NEXT: [[CONV6:%.*]] = trunc i64 [[TMP8]] to i32
	▲ Show 20 Lines • Show All 55 Lines • ▼ Show 20 Lines
	// CHECK9-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0			// CHECK9-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0
	// CHECK9-NEXT: br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK9-NEXT: br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK9: .omp.final.then:			// CHECK9: .omp.final.then:
	// CHECK9-NEXT: [[TMP27:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4			// CHECK9-NEXT: [[TMP27:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4
	// CHECK9-NEXT: [[SUB12:%.*]] = sub nsw i32 [[TMP27]], 0			// CHECK9-NEXT: [[SUB12:%.*]] = sub nsw i32 [[TMP27]], 0
	// CHECK9-NEXT: [[DIV13:%.*]] = sdiv i32 [[SUB12]], 1			// CHECK9-NEXT: [[DIV13:%.*]] = sdiv i32 [[SUB12]], 1
	// CHECK9-NEXT: [[MUL14:%.*]] = mul nsw i32 [[DIV13]], 1			// CHECK9-NEXT: [[MUL14:%.*]] = mul nsw i32 [[DIV13]], 1
	// CHECK9-NEXT: [[ADD15:%.*]] = add nsw i32 0, [[MUL14]]			// CHECK9-NEXT: [[ADD15:%.*]] = add nsw i32 0, [[MUL14]]
	// CHECK9-NEXT: store i32 [[ADD15]], i32* [[CONV]], align 4			// CHECK9-NEXT: store i32 [[ADD15]], i32* [[CONV]], align 8
	// CHECK9-NEXT: br label [[DOTOMP_FINAL_DONE]]			// CHECK9-NEXT: br label [[DOTOMP_FINAL_DONE]]
	// CHECK9: .omp.final.done:			// CHECK9: .omp.final.done:
	// CHECK9-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK9-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK9-NEXT: [[TMP29:%.*]] = icmp ne i32 [[TMP28]], 0			// CHECK9-NEXT: [[TMP29:%.*]] = icmp ne i32 [[TMP28]], 0
	// CHECK9-NEXT: br i1 [[TMP29]], label [[DOTOMP_LINEAR_PU:%.]], label [[DOTOMP_LINEAR_PU_DONE:%.]]			// CHECK9-NEXT: br i1 [[TMP29]], label [[DOTOMP_LINEAR_PU:%.]], label [[DOTOMP_LINEAR_PU_DONE:%.]]
	// CHECK9: .omp.linear.pu:			// CHECK9: .omp.linear.pu:
	// CHECK9-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]]			// CHECK9-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]]
	// CHECK9: .omp.linear.pu.done:			// CHECK9: .omp.linear.pu.done:
	Show All 9 Lines
	// CHECK9-NEXT: [[A_ADDR:%.]] = alloca [1000 x i32], align 8			// CHECK9-NEXT: [[A_ADDR:%.]] = alloca [1000 x i32], align 8
	// CHECK9-NEXT: [[G_ADDR:%.]] = alloca i32, align 8			// CHECK9-NEXT: [[G_ADDR:%.]] = alloca i32, align 8
	// CHECK9-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8			// CHECK9-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8
	// CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8			// CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
	// CHECK9-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8			// CHECK9-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8
	// CHECK9-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8			// CHECK9-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8
	// CHECK9-NEXT: [[CONV:%.]] = bitcast i64 [[N_ADDR]] to i32*			// CHECK9-NEXT: [[CONV:%.]] = bitcast i64 [[N_ADDR]] to i32*
	// CHECK9-NEXT: [[TMP0:%.]] = load [1000 x i32], [1000 x i32]** [[A_ADDR]], align 8			// CHECK9-NEXT: [[TMP0:%.]] = load [1000 x i32], [1000 x i32]** [[A_ADDR]], align 8
	// CHECK9-NEXT: [[TMP1:%.]] = load i32, i32 [[CONV]], align 4			// CHECK9-NEXT: [[TMP1:%.]] = load i32, i32 [[CONV]], align 8
	// CHECK9-NEXT: [[CONV1:%.]] = bitcast i64 [[N_CASTED]] to i32*			// CHECK9-NEXT: [[CONV1:%.]] = bitcast i64 [[N_CASTED]] to i32*
	// CHECK9-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4			// CHECK9-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4
	// CHECK9-NEXT: [[TMP2:%.]] = load i64, i64 [[N_CASTED]], align 8			// CHECK9-NEXT: [[TMP2:%.]] = load i64, i64 [[N_CASTED]], align 8
	// CHECK9-NEXT: [[TMP3:%.]] = load i32, i32** [[G_ADDR]], align 8			// CHECK9-NEXT: [[TMP3:%.]] = load i32, i32** [[G_ADDR]], align 8
	// CHECK9-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB4]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i64, [1000 x i32], i32)* @.omp_outlined..2 to void (i32, i32, ...)), i64 [[TMP2]], [1000 x i32] [[TMP0]], i32* [[TMP3]])			// CHECK9-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB4]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i64, [1000 x i32], i32)* @.omp_outlined..2 to void (i32, i32, ...)), i64 [[TMP2]], [1000 x i32] [[TMP0]], i32* [[TMP3]])
	// CHECK9-NEXT: ret void			// CHECK9-NEXT: ret void
	//			//
	//			//
	Show All 18 Lines
	// CHECK9-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8			// CHECK9-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8
	// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8			// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
	// CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8			// CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
	// CHECK9-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8			// CHECK9-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8
	// CHECK9-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8			// CHECK9-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8
	// CHECK9-NEXT: [[CONV:%.]] = bitcast i64 [[N_ADDR]] to i32*			// CHECK9-NEXT: [[CONV:%.]] = bitcast i64 [[N_ADDR]] to i32*
	// CHECK9-NEXT: [[TMP0:%.]] = load [1000 x i32], [1000 x i32]** [[A_ADDR]], align 8			// CHECK9-NEXT: [[TMP0:%.]] = load [1000 x i32], [1000 x i32]** [[A_ADDR]], align 8
	// CHECK9-NEXT: [[TMP1:%.]] = load i32, i32 [[CONV]], align 4			// CHECK9-NEXT: [[TMP1:%.]] = load i32, i32 [[CONV]], align 8
	// CHECK9-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4			// CHECK9-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
	// CHECK9-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4			// CHECK9-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4
	// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0			// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
	// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1			// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
	// CHECK9-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1			// CHECK9-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
	// CHECK9-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4			// CHECK9-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4
	// CHECK9-NEXT: store i32 0, i32* [[I]], align 4			// CHECK9-NEXT: store i32 0, i32* [[I]], align 4
	// CHECK9-NEXT: [[TMP3:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4			// CHECK9-NEXT: [[TMP3:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4
	Show All 29 Lines
	// CHECK9-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !12			// CHECK9-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !12
	// CHECK9-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]]			// CHECK9-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]]
	// CHECK9-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK9-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK9: omp.inner.for.body:			// CHECK9: omp.inner.for.body:
	// CHECK9-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !12			// CHECK9-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !12
	// CHECK9-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64			// CHECK9-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64
	// CHECK9-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !12			// CHECK9-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !12
	// CHECK9-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64			// CHECK9-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
	// CHECK9-NEXT: [[TMP18:%.]] = load i32, i32 [[CONV]], align 4, !llvm.access.group !12			// CHECK9-NEXT: [[TMP18:%.]] = load i32, i32 [[CONV]], align 8, !llvm.access.group !12
	// CHECK9-NEXT: [[CONV6:%.]] = bitcast i64 [[N_CASTED]] to i32*			// CHECK9-NEXT: [[CONV6:%.]] = bitcast i64 [[N_CASTED]] to i32*
	// CHECK9-NEXT: store i32 [[TMP18]], i32* [[CONV6]], align 4, !llvm.access.group !12			// CHECK9-NEXT: store i32 [[TMP18]], i32* [[CONV6]], align 4, !llvm.access.group !12
	// CHECK9-NEXT: [[TMP19:%.]] = load i64, i64 [[N_CASTED]], align 8, !llvm.access.group !12			// CHECK9-NEXT: [[TMP19:%.]] = load i64, i64 [[N_CASTED]], align 8, !llvm.access.group !12
	// CHECK9-NEXT: [[TMP20:%.]] = load i32, i32** [[G_ADDR]], align 8, !llvm.access.group !12			// CHECK9-NEXT: [[TMP20:%.]] = load i32, i32** [[G_ADDR]], align 8, !llvm.access.group !12
	// CHECK9-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 5, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i64, [1000 x i32], i32)* @.omp_outlined..3 to void (i32, i32, ...)), i64 [[TMP15]], i64 [[TMP17]], i64 [[TMP19]], [1000 x i32] [[TMP0]], i32* [[TMP20]]), !llvm.access.group !12			// CHECK9-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 5, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i64, [1000 x i32], i32)* @.omp_outlined..3 to void (i32, i32, ...)), i64 [[TMP15]], i64 [[TMP17]], i64 [[TMP19]], [1000 x i32] [[TMP0]], i32* [[TMP20]]), !llvm.access.group !12
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK9: omp.inner.for.inc:			// CHECK9: omp.inner.for.inc:
	// CHECK9-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12			// CHECK9-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12
	▲ Show 20 Lines • Show All 48 Lines • ▼ Show 20 Lines
	// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8			// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
	// CHECK9-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8			// CHECK9-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
	// CHECK9-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8			// CHECK9-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
	// CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8			// CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
	// CHECK9-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8			// CHECK9-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8
	// CHECK9-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8			// CHECK9-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8
	// CHECK9-NEXT: [[CONV:%.]] = bitcast i64 [[N_ADDR]] to i32*			// CHECK9-NEXT: [[CONV:%.]] = bitcast i64 [[N_ADDR]] to i32*
	// CHECK9-NEXT: [[TMP0:%.]] = load [1000 x i32], [1000 x i32]** [[A_ADDR]], align 8			// CHECK9-NEXT: [[TMP0:%.]] = load [1000 x i32], [1000 x i32]** [[A_ADDR]], align 8
	// CHECK9-NEXT: [[TMP1:%.]] = load i32, i32 [[CONV]], align 4			// CHECK9-NEXT: [[TMP1:%.]] = load i32, i32 [[CONV]], align 8
	// CHECK9-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4			// CHECK9-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
	// CHECK9-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4			// CHECK9-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4
	// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0			// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
	// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1			// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
	// CHECK9-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1			// CHECK9-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
	// CHECK9-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4			// CHECK9-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4
	// CHECK9-NEXT: store i32 0, i32* [[I]], align 4			// CHECK9-NEXT: store i32 0, i32* [[I]], align 4
	// CHECK9-NEXT: [[TMP3:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4			// CHECK9-NEXT: [[TMP3:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4
	▲ Show 20 Lines • Show All 94 Lines • ▼ Show 20 Lines
	// CHECK10-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8			// CHECK10-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8
	// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8			// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
	// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8			// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8
	// CHECK10-NEXT: [[CONV:%.]] = bitcast i64 [[I_ADDR]] to i32*			// CHECK10-NEXT: [[CONV:%.]] = bitcast i64 [[I_ADDR]] to i32*
	// CHECK10-NEXT: [[CONV3:%.]] = bitcast i64 [[N_ADDR]] to i32*			// CHECK10-NEXT: [[CONV3:%.]] = bitcast i64 [[N_ADDR]] to i32*
	// CHECK10-NEXT: [[TMP1:%.]] = load [1000 x i32], [1000 x i32]** [[A_ADDR]], align 8			// CHECK10-NEXT: [[TMP1:%.]] = load [1000 x i32], [1000 x i32]** [[A_ADDR]], align 8
	// CHECK10-NEXT: [[CONV4:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__ADDR]] to i32*			// CHECK10-NEXT: [[CONV4:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__ADDR]] to i32*
	// CHECK10-NEXT: [[CONV5:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__ADDR2]] to i32*			// CHECK10-NEXT: [[CONV5:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__ADDR2]] to i32*
	// CHECK10-NEXT: [[TMP2:%.]] = load i32, i32 [[CONV4]], align 4			// CHECK10-NEXT: [[TMP2:%.]] = load i32, i32 [[CONV4]], align 8
	// CHECK10-NEXT: [[TMP3:%.]] = load i32, i32 [[CONV5]], align 4			// CHECK10-NEXT: [[TMP3:%.]] = load i32, i32 [[CONV5]], align 8
	// CHECK10-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB4]], i32 [[TMP0]], i32 [[TMP2]], i32 [[TMP3]])			// CHECK10-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB4]], i32 [[TMP0]], i32 [[TMP2]], i32 [[TMP3]])
	// CHECK10-NEXT: [[TMP4:%.]] = load i32, i32 [[CONV]], align 4			// CHECK10-NEXT: [[TMP4:%.]] = load i32, i32 [[CONV]], align 8
	// CHECK10-NEXT: [[CONV6:%.]] = bitcast i64 [[I_CASTED]] to i32*			// CHECK10-NEXT: [[CONV6:%.]] = bitcast i64 [[I_CASTED]] to i32*
	// CHECK10-NEXT: store i32 [[TMP4]], i32* [[CONV6]], align 4			// CHECK10-NEXT: store i32 [[TMP4]], i32* [[CONV6]], align 4
	// CHECK10-NEXT: [[TMP5:%.]] = load i64, i64 [[I_CASTED]], align 8			// CHECK10-NEXT: [[TMP5:%.]] = load i64, i64 [[I_CASTED]], align 8
	// CHECK10-NEXT: [[TMP6:%.]] = load i32, i32 [[CONV3]], align 4			// CHECK10-NEXT: [[TMP6:%.]] = load i32, i32 [[CONV3]], align 8
	// CHECK10-NEXT: [[CONV7:%.]] = bitcast i64 [[N_CASTED]] to i32*			// CHECK10-NEXT: [[CONV7:%.]] = bitcast i64 [[N_CASTED]] to i32*
	// CHECK10-NEXT: store i32 [[TMP6]], i32* [[CONV7]], align 4			// CHECK10-NEXT: store i32 [[TMP6]], i32* [[CONV7]], align 4
	// CHECK10-NEXT: [[TMP7:%.]] = load i64, i64 [[N_CASTED]], align 8			// CHECK10-NEXT: [[TMP7:%.]] = load i64, i64 [[N_CASTED]], align 8
	// CHECK10-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB4]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, [1000 x i32]) @.omp_outlined. to void (i32, i32, ...)), i64 [[TMP5]], i64 [[TMP7]], [1000 x i32] [[TMP1]])			// CHECK10-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB4]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, [1000 x i32]) @.omp_outlined. to void (i32, i32, ...)), i64 [[TMP5]], i64 [[TMP7]], [1000 x i32] [[TMP1]])
	// CHECK10-NEXT: ret void			// CHECK10-NEXT: ret void
	//			//
	//			//
	// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined.			// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined.
	Show All 19 Lines
	// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8			// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
	// CHECK10-NEXT: store i64 [[I]], i64* [[I_ADDR]], align 8			// CHECK10-NEXT: store i64 [[I]], i64* [[I_ADDR]], align 8
	// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8			// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
	// CHECK10-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8			// CHECK10-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8
	// CHECK10-NEXT: [[CONV:%.]] = bitcast i64 [[I_ADDR]] to i32*			// CHECK10-NEXT: [[CONV:%.]] = bitcast i64 [[I_ADDR]] to i32*
	// CHECK10-NEXT: [[CONV1:%.]] = bitcast i64 [[N_ADDR]] to i32*			// CHECK10-NEXT: [[CONV1:%.]] = bitcast i64 [[N_ADDR]] to i32*
	// CHECK10-NEXT: [[TMP0:%.]] = load [1000 x i32], [1000 x i32]** [[A_ADDR]], align 8			// CHECK10-NEXT: [[TMP0:%.]] = load [1000 x i32], [1000 x i32]** [[A_ADDR]], align 8
	// CHECK10-NEXT: [[TMP1:%.]] = load i32, i32 [[CONV1]], align 4			// CHECK10-NEXT: [[TMP1:%.]] = load i32, i32 [[CONV1]], align 8
	// CHECK10-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4			// CHECK10-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
	// CHECK10-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4			// CHECK10-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4
	// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0			// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
	// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1			// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
	// CHECK10-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1			// CHECK10-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1
	// CHECK10-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4			// CHECK10-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4
	// CHECK10-NEXT: store i32 0, i32* [[I4]], align 4			// CHECK10-NEXT: store i32 0, i32* [[I4]], align 4
	// CHECK10-NEXT: [[TMP3:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4			// CHECK10-NEXT: [[TMP3:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4
	Show All 35 Lines
	// CHECK10-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK10-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK10-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64			// CHECK10-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64
	// CHECK10-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK10-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4
	// CHECK10-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64			// CHECK10-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
	// CHECK10-NEXT: [[TMP18:%.]] = load i32, i32 [[I5]], align 4			// CHECK10-NEXT: [[TMP18:%.]] = load i32, i32 [[I5]], align 4
	// CHECK10-NEXT: [[CONV8:%.]] = bitcast i64 [[I_CASTED]] to i32*			// CHECK10-NEXT: [[CONV8:%.]] = bitcast i64 [[I_CASTED]] to i32*
	// CHECK10-NEXT: store i32 [[TMP18]], i32* [[CONV8]], align 4			// CHECK10-NEXT: store i32 [[TMP18]], i32* [[CONV8]], align 4
	// CHECK10-NEXT: [[TMP19:%.]] = load i64, i64 [[I_CASTED]], align 8			// CHECK10-NEXT: [[TMP19:%.]] = load i64, i64 [[I_CASTED]], align 8
	// CHECK10-NEXT: [[TMP20:%.]] = load i32, i32 [[CONV1]], align 4			// CHECK10-NEXT: [[TMP20:%.]] = load i32, i32 [[CONV1]], align 8
	// CHECK10-NEXT: [[CONV9:%.]] = bitcast i64 [[N_CASTED]] to i32*			// CHECK10-NEXT: [[CONV9:%.]] = bitcast i64 [[N_CASTED]] to i32*
	// CHECK10-NEXT: store i32 [[TMP20]], i32* [[CONV9]], align 4			// CHECK10-NEXT: store i32 [[TMP20]], i32* [[CONV9]], align 4
	// CHECK10-NEXT: [[TMP21:%.]] = load i64, i64 [[N_CASTED]], align 8			// CHECK10-NEXT: [[TMP21:%.]] = load i64, i64 [[N_CASTED]], align 8
	// CHECK10-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 5, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i64, i64, [1000 x i32]) @.omp_outlined..1 to void (i32, i32, ...)), i64 [[TMP15]], i64 [[TMP17]], i64 [[TMP19]], i64 [[TMP21]], [1000 x i32] [[TMP0]])			// CHECK10-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 5, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i64, i64, [1000 x i32]) @.omp_outlined..1 to void (i32, i32, ...)), i64 [[TMP15]], i64 [[TMP17]], i64 [[TMP19]], i64 [[TMP21]], [1000 x i32] [[TMP0]])
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK10: omp.inner.for.inc:			// CHECK10: omp.inner.for.inc:
	// CHECK10-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK10-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK10-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4
	Show All 10 Lines
	// CHECK10-NEXT: [[TMP27:%.*]] = icmp ne i32 [[TMP26]], 0			// CHECK10-NEXT: [[TMP27:%.*]] = icmp ne i32 [[TMP26]], 0
	// CHECK10-NEXT: br i1 [[TMP27]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK10-NEXT: br i1 [[TMP27]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK10: .omp.final.then:			// CHECK10: .omp.final.then:
	// CHECK10-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4			// CHECK10-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4
	// CHECK10-NEXT: [[SUB10:%.*]] = sub nsw i32 [[TMP28]], 0			// CHECK10-NEXT: [[SUB10:%.*]] = sub nsw i32 [[TMP28]], 0
	// CHECK10-NEXT: [[DIV11:%.*]] = sdiv i32 [[SUB10]], 1			// CHECK10-NEXT: [[DIV11:%.*]] = sdiv i32 [[SUB10]], 1
	// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV11]], 1			// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV11]], 1
	// CHECK10-NEXT: [[ADD12:%.*]] = add nsw i32 0, [[MUL]]			// CHECK10-NEXT: [[ADD12:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK10-NEXT: store i32 [[ADD12]], i32* [[CONV]], align 4			// CHECK10-NEXT: store i32 [[ADD12]], i32* [[CONV]], align 8
	// CHECK10-NEXT: br label [[DOTOMP_FINAL_DONE]]			// CHECK10-NEXT: br label [[DOTOMP_FINAL_DONE]]
	// CHECK10: .omp.final.done:			// CHECK10: .omp.final.done:
	// CHECK10-NEXT: br label [[OMP_PRECOND_END]]			// CHECK10-NEXT: br label [[OMP_PRECOND_END]]
	// CHECK10: omp.precond.end:			// CHECK10: omp.precond.end:
	// CHECK10-NEXT: ret void			// CHECK10-NEXT: ret void
	//			//
	//			//
	// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1			// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1
	Show All 24 Lines
	// CHECK10-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8			// CHECK10-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
	// CHECK10-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8			// CHECK10-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
	// CHECK10-NEXT: store i64 [[I]], i64* [[I_ADDR]], align 8			// CHECK10-NEXT: store i64 [[I]], i64* [[I_ADDR]], align 8
	// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8			// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
	// CHECK10-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8			// CHECK10-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8
	// CHECK10-NEXT: [[CONV:%.]] = bitcast i64 [[I_ADDR]] to i32*			// CHECK10-NEXT: [[CONV:%.]] = bitcast i64 [[I_ADDR]] to i32*
	// CHECK10-NEXT: [[CONV1:%.]] = bitcast i64 [[N_ADDR]] to i32*			// CHECK10-NEXT: [[CONV1:%.]] = bitcast i64 [[N_ADDR]] to i32*
	// CHECK10-NEXT: [[TMP0:%.]] = load [1000 x i32], [1000 x i32]** [[A_ADDR]], align 8			// CHECK10-NEXT: [[TMP0:%.]] = load [1000 x i32], [1000 x i32]** [[A_ADDR]], align 8
	// CHECK10-NEXT: [[TMP1:%.]] = load i32, i32 [[CONV1]], align 4			// CHECK10-NEXT: [[TMP1:%.]] = load i32, i32 [[CONV1]], align 8
	// CHECK10-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4			// CHECK10-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
	// CHECK10-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4			// CHECK10-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4
	// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0			// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
	// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1			// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
	// CHECK10-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1			// CHECK10-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1
	// CHECK10-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4			// CHECK10-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4
	// CHECK10-NEXT: store i32 0, i32* [[I4]], align 4			// CHECK10-NEXT: store i32 0, i32* [[I4]], align 4
	// CHECK10-NEXT: [[TMP3:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4			// CHECK10-NEXT: [[TMP3:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4
	// CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]]			// CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]]
	// CHECK10-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.]], label [[OMP_PRECOND_END:%.]]			// CHECK10-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.]], label [[OMP_PRECOND_END:%.]]
	// CHECK10: omp.precond.then:			// CHECK10: omp.precond.then:
	// CHECK10-NEXT: [[ARRAYDECAY:%.]] = getelementptr inbounds [1000 x i32], [1000 x i32] [[TMP0]], i64 0, i64 0			// CHECK10-NEXT: [[ARRAYDECAY:%.]] = getelementptr inbounds [1000 x i32], [1000 x i32] [[TMP0]], i64 0, i64 0
	// CHECK10-NEXT: call void @llvm.assume(i1 true) [ "align"(i32* [[ARRAYDECAY]], i64 8) ]			// CHECK10-NEXT: call void @llvm.assume(i1 true) [ "align"(i32* [[ARRAYDECAY]], i64 8) ]
	// CHECK10-NEXT: [[TMP4:%.]] = load i32, i32 [[CONV]], align 4			// CHECK10-NEXT: [[TMP4:%.]] = load i32, i32 [[CONV]], align 8
	// CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTLINEAR_START]], align 4			// CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTLINEAR_START]], align 4
	// CHECK10-NEXT: [[TMP5:%.]] = load i32, i32 [[CONV1]], align 4			// CHECK10-NEXT: [[TMP5:%.]] = load i32, i32 [[CONV1]], align 8
	// CHECK10-NEXT: store i32 [[TMP5]], i32* [[DOTLINEAR_STEP]], align 4			// CHECK10-NEXT: store i32 [[TMP5]], i32* [[DOTLINEAR_STEP]], align 4
	// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4			// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
	// CHECK10-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2]], align 4			// CHECK10-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2]], align 4
	// CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4			// CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4
	// CHECK10-NEXT: [[TMP7:%.]] = load i64, i64 [[DOTPREVIOUS_LB__ADDR]], align 8			// CHECK10-NEXT: [[TMP7:%.]] = load i64, i64 [[DOTPREVIOUS_LB__ADDR]], align 8
	// CHECK10-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP7]] to i32			// CHECK10-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP7]] to i32
	// CHECK10-NEXT: [[TMP8:%.]] = load i64, i64 [[DOTPREVIOUS_UB__ADDR]], align 8			// CHECK10-NEXT: [[TMP8:%.]] = load i64, i64 [[DOTPREVIOUS_UB__ADDR]], align 8
	// CHECK10-NEXT: [[CONV6:%.*]] = trunc i64 [[TMP8]] to i32			// CHECK10-NEXT: [[CONV6:%.*]] = trunc i64 [[TMP8]] to i32
	▲ Show 20 Lines • Show All 55 Lines • ▼ Show 20 Lines
	// CHECK10-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0			// CHECK10-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0
	// CHECK10-NEXT: br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK10-NEXT: br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK10: .omp.final.then:			// CHECK10: .omp.final.then:
	// CHECK10-NEXT: [[TMP27:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4			// CHECK10-NEXT: [[TMP27:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4
	// CHECK10-NEXT: [[SUB12:%.*]] = sub nsw i32 [[TMP27]], 0			// CHECK10-NEXT: [[SUB12:%.*]] = sub nsw i32 [[TMP27]], 0
	// CHECK10-NEXT: [[DIV13:%.*]] = sdiv i32 [[SUB12]], 1			// CHECK10-NEXT: [[DIV13:%.*]] = sdiv i32 [[SUB12]], 1
	// CHECK10-NEXT: [[MUL14:%.*]] = mul nsw i32 [[DIV13]], 1			// CHECK10-NEXT: [[MUL14:%.*]] = mul nsw i32 [[DIV13]], 1
	// CHECK10-NEXT: [[ADD15:%.*]] = add nsw i32 0, [[MUL14]]			// CHECK10-NEXT: [[ADD15:%.*]] = add nsw i32 0, [[MUL14]]
	// CHECK10-NEXT: store i32 [[ADD15]], i32* [[CONV]], align 4			// CHECK10-NEXT: store i32 [[ADD15]], i32* [[CONV]], align 8
	// CHECK10-NEXT: br label [[DOTOMP_FINAL_DONE]]			// CHECK10-NEXT: br label [[DOTOMP_FINAL_DONE]]
	// CHECK10: .omp.final.done:			// CHECK10: .omp.final.done:
	// CHECK10-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK10-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK10-NEXT: [[TMP29:%.*]] = icmp ne i32 [[TMP28]], 0			// CHECK10-NEXT: [[TMP29:%.*]] = icmp ne i32 [[TMP28]], 0
	// CHECK10-NEXT: br i1 [[TMP29]], label [[DOTOMP_LINEAR_PU:%.]], label [[DOTOMP_LINEAR_PU_DONE:%.]]			// CHECK10-NEXT: br i1 [[TMP29]], label [[DOTOMP_LINEAR_PU:%.]], label [[DOTOMP_LINEAR_PU_DONE:%.]]
	// CHECK10: .omp.linear.pu:			// CHECK10: .omp.linear.pu:
	// CHECK10-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]]			// CHECK10-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]]
	// CHECK10: .omp.linear.pu.done:			// CHECK10: .omp.linear.pu.done:
	Show All 9 Lines
	// CHECK10-NEXT: [[A_ADDR:%.]] = alloca [1000 x i32], align 8			// CHECK10-NEXT: [[A_ADDR:%.]] = alloca [1000 x i32], align 8
	// CHECK10-NEXT: [[G_ADDR:%.]] = alloca i32, align 8			// CHECK10-NEXT: [[G_ADDR:%.]] = alloca i32, align 8
	// CHECK10-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8			// CHECK10-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8
	// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8			// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
	// CHECK10-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8			// CHECK10-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8
	// CHECK10-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8			// CHECK10-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8
	// CHECK10-NEXT: [[CONV:%.]] = bitcast i64 [[N_ADDR]] to i32*			// CHECK10-NEXT: [[CONV:%.]] = bitcast i64 [[N_ADDR]] to i32*
	// CHECK10-NEXT: [[TMP0:%.]] = load [1000 x i32], [1000 x i32]** [[A_ADDR]], align 8			// CHECK10-NEXT: [[TMP0:%.]] = load [1000 x i32], [1000 x i32]** [[A_ADDR]], align 8
	// CHECK10-NEXT: [[TMP1:%.]] = load i32, i32 [[CONV]], align 4			// CHECK10-NEXT: [[TMP1:%.]] = load i32, i32 [[CONV]], align 8
	// CHECK10-NEXT: [[CONV1:%.]] = bitcast i64 [[N_CASTED]] to i32*			// CHECK10-NEXT: [[CONV1:%.]] = bitcast i64 [[N_CASTED]] to i32*
	// CHECK10-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4			// CHECK10-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4
	// CHECK10-NEXT: [[TMP2:%.]] = load i64, i64 [[N_CASTED]], align 8			// CHECK10-NEXT: [[TMP2:%.]] = load i64, i64 [[N_CASTED]], align 8
	// CHECK10-NEXT: [[TMP3:%.]] = load i32, i32** [[G_ADDR]], align 8			// CHECK10-NEXT: [[TMP3:%.]] = load i32, i32** [[G_ADDR]], align 8
	// CHECK10-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB4]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i64, [1000 x i32], i32)* @.omp_outlined..2 to void (i32, i32, ...)), i64 [[TMP2]], [1000 x i32] [[TMP0]], i32* [[TMP3]])			// CHECK10-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB4]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i64, [1000 x i32], i32)* @.omp_outlined..2 to void (i32, i32, ...)), i64 [[TMP2]], [1000 x i32] [[TMP0]], i32* [[TMP3]])
	// CHECK10-NEXT: ret void			// CHECK10-NEXT: ret void
	//			//
	//			//
	Show All 18 Lines
	// CHECK10-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8			// CHECK10-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8
	// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8			// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
	// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8			// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
	// CHECK10-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8			// CHECK10-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8
	// CHECK10-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8			// CHECK10-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8
	// CHECK10-NEXT: [[CONV:%.]] = bitcast i64 [[N_ADDR]] to i32*			// CHECK10-NEXT: [[CONV:%.]] = bitcast i64 [[N_ADDR]] to i32*
	// CHECK10-NEXT: [[TMP0:%.]] = load [1000 x i32], [1000 x i32]** [[A_ADDR]], align 8			// CHECK10-NEXT: [[TMP0:%.]] = load [1000 x i32], [1000 x i32]** [[A_ADDR]], align 8
	// CHECK10-NEXT: [[TMP1:%.]] = load i32, i32 [[CONV]], align 4			// CHECK10-NEXT: [[TMP1:%.]] = load i32, i32 [[CONV]], align 8
	// CHECK10-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4			// CHECK10-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
	// CHECK10-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4			// CHECK10-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4
	// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0			// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
	// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1			// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
	// CHECK10-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1			// CHECK10-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
	// CHECK10-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4			// CHECK10-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4
	// CHECK10-NEXT: store i32 0, i32* [[I]], align 4			// CHECK10-NEXT: store i32 0, i32* [[I]], align 4
	// CHECK10-NEXT: [[TMP3:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4			// CHECK10-NEXT: [[TMP3:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4
	Show All 29 Lines
	// CHECK10-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !12			// CHECK10-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !12
	// CHECK10-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]]			// CHECK10-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]]
	// CHECK10-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK10-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK10: omp.inner.for.body:			// CHECK10: omp.inner.for.body:
	// CHECK10-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !12			// CHECK10-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !12
	// CHECK10-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64			// CHECK10-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64
	// CHECK10-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !12			// CHECK10-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !12
	// CHECK10-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64			// CHECK10-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
	// CHECK10-NEXT: [[TMP18:%.]] = load i32, i32 [[CONV]], align 4, !llvm.access.group !12			// CHECK10-NEXT: [[TMP18:%.]] = load i32, i32 [[CONV]], align 8, !llvm.access.group !12
	// CHECK10-NEXT: [[CONV6:%.]] = bitcast i64 [[N_CASTED]] to i32*			// CHECK10-NEXT: [[CONV6:%.]] = bitcast i64 [[N_CASTED]] to i32*
	// CHECK10-NEXT: store i32 [[TMP18]], i32* [[CONV6]], align 4, !llvm.access.group !12			// CHECK10-NEXT: store i32 [[TMP18]], i32* [[CONV6]], align 4, !llvm.access.group !12
	// CHECK10-NEXT: [[TMP19:%.]] = load i64, i64 [[N_CASTED]], align 8, !llvm.access.group !12			// CHECK10-NEXT: [[TMP19:%.]] = load i64, i64 [[N_CASTED]], align 8, !llvm.access.group !12
	// CHECK10-NEXT: [[TMP20:%.]] = load i32, i32** [[G_ADDR]], align 8, !llvm.access.group !12			// CHECK10-NEXT: [[TMP20:%.]] = load i32, i32** [[G_ADDR]], align 8, !llvm.access.group !12
	// CHECK10-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 5, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i64, [1000 x i32], i32)* @.omp_outlined..3 to void (i32, i32, ...)), i64 [[TMP15]], i64 [[TMP17]], i64 [[TMP19]], [1000 x i32] [[TMP0]], i32* [[TMP20]]), !llvm.access.group !12			// CHECK10-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 5, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i64, [1000 x i32], i32)* @.omp_outlined..3 to void (i32, i32, ...)), i64 [[TMP15]], i64 [[TMP17]], i64 [[TMP19]], [1000 x i32] [[TMP0]], i32* [[TMP20]]), !llvm.access.group !12
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK10: omp.inner.for.inc:			// CHECK10: omp.inner.for.inc:
	// CHECK10-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12			// CHECK10-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12
	▲ Show 20 Lines • Show All 48 Lines • ▼ Show 20 Lines
	// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8			// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
	// CHECK10-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8			// CHECK10-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
	// CHECK10-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8			// CHECK10-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
	// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8			// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
	// CHECK10-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8			// CHECK10-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8
	// CHECK10-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8			// CHECK10-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8
	// CHECK10-NEXT: [[CONV:%.]] = bitcast i64 [[N_ADDR]] to i32*			// CHECK10-NEXT: [[CONV:%.]] = bitcast i64 [[N_ADDR]] to i32*
	// CHECK10-NEXT: [[TMP0:%.]] = load [1000 x i32], [1000 x i32]** [[A_ADDR]], align 8			// CHECK10-NEXT: [[TMP0:%.]] = load [1000 x i32], [1000 x i32]** [[A_ADDR]], align 8
	// CHECK10-NEXT: [[TMP1:%.]] = load i32, i32 [[CONV]], align 4			// CHECK10-NEXT: [[TMP1:%.]] = load i32, i32 [[CONV]], align 8
	// CHECK10-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4			// CHECK10-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
	// CHECK10-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4			// CHECK10-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4
	// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0			// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
	// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1			// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
	// CHECK10-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1			// CHECK10-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
	// CHECK10-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4			// CHECK10-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4
	// CHECK10-NEXT: store i32 0, i32* [[I]], align 4			// CHECK10-NEXT: store i32 0, i32* [[I]], align 4
	// CHECK10-NEXT: [[TMP3:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4			// CHECK10-NEXT: [[TMP3:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4
	▲ Show 20 Lines • Show All 1,698 Lines • Show Last 20 Lines

clang/test/OpenMP/target_teams_distribute_parallel_for_simd_collapse_codegen.cpp

This file is larger than 256 KB, so syntax highlighting is disabled by default.

	Show First 20 Lines • Show All 1,455 Lines • ▼ Show 20 Lines
	// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8			// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
	// CHECK9-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8			// CHECK9-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
	// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8			// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
	// CHECK9-NEXT: [[CONV:%.]] = bitcast i64 [[N_ADDR]] to i32*			// CHECK9-NEXT: [[CONV:%.]] = bitcast i64 [[N_ADDR]] to i32*
	// CHECK9-NEXT: [[CONV3:%.]] = bitcast i64 [[M_ADDR]] to i32*			// CHECK9-NEXT: [[CONV3:%.]] = bitcast i64 [[M_ADDR]] to i32*
	// CHECK9-NEXT: [[TMP0:%.]] = load i64, i64 [[VLA_ADDR]], align 8			// CHECK9-NEXT: [[TMP0:%.]] = load i64, i64 [[VLA_ADDR]], align 8
	// CHECK9-NEXT: [[TMP1:%.]] = load i64, i64 [[VLA_ADDR2]], align 8			// CHECK9-NEXT: [[TMP1:%.]] = load i64, i64 [[VLA_ADDR2]], align 8
	// CHECK9-NEXT: [[TMP2:%.]] = load i32, i32** [[A_ADDR]], align 8			// CHECK9-NEXT: [[TMP2:%.]] = load i32, i32** [[A_ADDR]], align 8
	// CHECK9-NEXT: [[TMP3:%.]] = load i32, i32 [[CONV]], align 4			// CHECK9-NEXT: [[TMP3:%.]] = load i32, i32 [[CONV]], align 8
	// CHECK9-NEXT: [[CONV4:%.]] = bitcast i64 [[N_CASTED]] to i32*			// CHECK9-NEXT: [[CONV4:%.]] = bitcast i64 [[N_CASTED]] to i32*
	// CHECK9-NEXT: store i32 [[TMP3]], i32* [[CONV4]], align 4			// CHECK9-NEXT: store i32 [[TMP3]], i32* [[CONV4]], align 4
	// CHECK9-NEXT: [[TMP4:%.]] = load i64, i64 [[N_CASTED]], align 8			// CHECK9-NEXT: [[TMP4:%.]] = load i64, i64 [[N_CASTED]], align 8
	// CHECK9-NEXT: [[TMP5:%.]] = load i32, i32 [[CONV3]], align 4			// CHECK9-NEXT: [[TMP5:%.]] = load i32, i32 [[CONV3]], align 8
	// CHECK9-NEXT: [[CONV5:%.]] = bitcast i64 [[M_CASTED]] to i32*			// CHECK9-NEXT: [[CONV5:%.]] = bitcast i64 [[M_CASTED]] to i32*
	// CHECK9-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4			// CHECK9-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4
	// CHECK9-NEXT: [[TMP6:%.]] = load i64, i64 [[M_CASTED]], align 8			// CHECK9-NEXT: [[TMP6:%.]] = load i64, i64 [[M_CASTED]], align 8
	// CHECK9-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i64, i64, i32) @.omp_outlined. to void (i32, i32, ...)), i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP0]], i64 [[TMP1]], i32 [[TMP2]])			// CHECK9-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i64, i64, i32) @.omp_outlined. to void (i32, i32, ...)), i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP0]], i64 [[TMP1]], i32 [[TMP2]])
	// CHECK9-NEXT: ret void			// CHECK9-NEXT: ret void
	//			//
	//			//
	// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined.			// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined.
	Show All 29 Lines
	// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8			// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
	// CHECK9-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8			// CHECK9-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
	// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8			// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
	// CHECK9-NEXT: [[CONV:%.]] = bitcast i64 [[N_ADDR]] to i32*			// CHECK9-NEXT: [[CONV:%.]] = bitcast i64 [[N_ADDR]] to i32*
	// CHECK9-NEXT: [[CONV3:%.]] = bitcast i64 [[M_ADDR]] to i32*			// CHECK9-NEXT: [[CONV3:%.]] = bitcast i64 [[M_ADDR]] to i32*
	// CHECK9-NEXT: [[TMP0:%.]] = load i64, i64 [[VLA_ADDR]], align 8			// CHECK9-NEXT: [[TMP0:%.]] = load i64, i64 [[VLA_ADDR]], align 8
	// CHECK9-NEXT: [[TMP1:%.]] = load i64, i64 [[VLA_ADDR2]], align 8			// CHECK9-NEXT: [[TMP1:%.]] = load i64, i64 [[VLA_ADDR2]], align 8
	// CHECK9-NEXT: [[TMP2:%.]] = load i32, i32** [[A_ADDR]], align 8			// CHECK9-NEXT: [[TMP2:%.]] = load i32, i32** [[A_ADDR]], align 8
	// CHECK9-NEXT: [[TMP3:%.]] = load i32, i32 [[CONV]], align 4			// CHECK9-NEXT: [[TMP3:%.]] = load i32, i32 [[CONV]], align 8
	// CHECK9-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4			// CHECK9-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4
	// CHECK9-NEXT: [[TMP4:%.]] = load i32, i32 [[CONV3]], align 4			// CHECK9-NEXT: [[TMP4:%.]] = load i32, i32 [[CONV3]], align 8
	// CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_5]], align 4			// CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_5]], align 4
	// CHECK9-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4			// CHECK9-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4
	// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0			// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0
	// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1			// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
	// CHECK9-NEXT: [[CONV7:%.*]] = sext i32 [[DIV]] to i64			// CHECK9-NEXT: [[CONV7:%.*]] = sext i32 [[DIV]] to i64
	// CHECK9-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_5]], align 4			// CHECK9-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_5]], align 4
	// CHECK9-NEXT: [[SUB8:%.*]] = sub nsw i32 [[TMP6]], 0			// CHECK9-NEXT: [[SUB8:%.*]] = sub nsw i32 [[TMP6]], 0
	// CHECK9-NEXT: [[DIV9:%.*]] = sdiv i32 [[SUB8]], 1			// CHECK9-NEXT: [[DIV9:%.*]] = sdiv i32 [[SUB8]], 1
	Show All 38 Lines
	// CHECK9: omp.inner.for.cond:			// CHECK9: omp.inner.for.cond:
	// CHECK9-NEXT: [[TMP17:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !5			// CHECK9-NEXT: [[TMP17:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !5
	// CHECK9-NEXT: [[TMP18:%.]] = load i64, i64 [[DOTOMP_COMB_UB]], align 8, !llvm.access.group !5			// CHECK9-NEXT: [[TMP18:%.]] = load i64, i64 [[DOTOMP_COMB_UB]], align 8, !llvm.access.group !5
	// CHECK9-NEXT: [[CMP16:%.*]] = icmp sle i64 [[TMP17]], [[TMP18]]			// CHECK9-NEXT: [[CMP16:%.*]] = icmp sle i64 [[TMP17]], [[TMP18]]
	// CHECK9-NEXT: br i1 [[CMP16]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK9-NEXT: br i1 [[CMP16]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK9: omp.inner.for.body:			// CHECK9: omp.inner.for.body:
	// CHECK9-NEXT: [[TMP19:%.]] = load i64, i64 [[DOTOMP_COMB_LB]], align 8, !llvm.access.group !5			// CHECK9-NEXT: [[TMP19:%.]] = load i64, i64 [[DOTOMP_COMB_LB]], align 8, !llvm.access.group !5
	// CHECK9-NEXT: [[TMP20:%.]] = load i64, i64 [[DOTOMP_COMB_UB]], align 8, !llvm.access.group !5			// CHECK9-NEXT: [[TMP20:%.]] = load i64, i64 [[DOTOMP_COMB_UB]], align 8, !llvm.access.group !5
	// CHECK9-NEXT: [[TMP21:%.]] = load i32, i32 [[CONV]], align 4, !llvm.access.group !5			// CHECK9-NEXT: [[TMP21:%.]] = load i32, i32 [[CONV]], align 8, !llvm.access.group !5
	// CHECK9-NEXT: [[CONV17:%.]] = bitcast i64 [[N_CASTED]] to i32*			// CHECK9-NEXT: [[CONV17:%.]] = bitcast i64 [[N_CASTED]] to i32*
	// CHECK9-NEXT: store i32 [[TMP21]], i32* [[CONV17]], align 4, !llvm.access.group !5			// CHECK9-NEXT: store i32 [[TMP21]], i32* [[CONV17]], align 4, !llvm.access.group !5
	// CHECK9-NEXT: [[TMP22:%.]] = load i64, i64 [[N_CASTED]], align 8, !llvm.access.group !5			// CHECK9-NEXT: [[TMP22:%.]] = load i64, i64 [[N_CASTED]], align 8, !llvm.access.group !5
	// CHECK9-NEXT: [[TMP23:%.]] = load i32, i32 [[CONV3]], align 4, !llvm.access.group !5			// CHECK9-NEXT: [[TMP23:%.]] = load i32, i32 [[CONV3]], align 8, !llvm.access.group !5
	// CHECK9-NEXT: [[CONV18:%.]] = bitcast i64 [[M_CASTED]] to i32*			// CHECK9-NEXT: [[CONV18:%.]] = bitcast i64 [[M_CASTED]] to i32*
	// CHECK9-NEXT: store i32 [[TMP23]], i32* [[CONV18]], align 4, !llvm.access.group !5			// CHECK9-NEXT: store i32 [[TMP23]], i32* [[CONV18]], align 4, !llvm.access.group !5
	// CHECK9-NEXT: [[TMP24:%.]] = load i64, i64 [[M_CASTED]], align 8, !llvm.access.group !5			// CHECK9-NEXT: [[TMP24:%.]] = load i64, i64 [[M_CASTED]], align 8, !llvm.access.group !5
	// CHECK9-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i64, i64, i64, i64, i32) @.omp_outlined..1 to void (i32, i32, ...)), i64 [[TMP19]], i64 [[TMP20]], i64 [[TMP22]], i64 [[TMP24]], i64 [[TMP0]], i64 [[TMP1]], i32 [[TMP2]]), !llvm.access.group !5			// CHECK9-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i64, i64, i64, i64, i32) @.omp_outlined..1 to void (i32, i32, ...)), i64 [[TMP19]], i64 [[TMP20]], i64 [[TMP22]], i64 [[TMP24]], i64 [[TMP0]], i64 [[TMP1]], i32 [[TMP2]]), !llvm.access.group !5
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK9: omp.inner.for.inc:			// CHECK9: omp.inner.for.inc:
	// CHECK9-NEXT: [[TMP25:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !5			// CHECK9-NEXT: [[TMP25:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !5
	// CHECK9-NEXT: [[TMP26:%.]] = load i64, i64 [[DOTOMP_STRIDE]], align 8, !llvm.access.group !5			// CHECK9-NEXT: [[TMP26:%.]] = load i64, i64 [[DOTOMP_STRIDE]], align 8, !llvm.access.group !5
	▲ Show 20 Lines • Show All 64 Lines • ▼ Show 20 Lines
	// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8			// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
	// CHECK9-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8			// CHECK9-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
	// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8			// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
	// CHECK9-NEXT: [[CONV:%.]] = bitcast i64 [[N_ADDR]] to i32*			// CHECK9-NEXT: [[CONV:%.]] = bitcast i64 [[N_ADDR]] to i32*
	// CHECK9-NEXT: [[CONV3:%.]] = bitcast i64 [[M_ADDR]] to i32*			// CHECK9-NEXT: [[CONV3:%.]] = bitcast i64 [[M_ADDR]] to i32*
	// CHECK9-NEXT: [[TMP0:%.]] = load i64, i64 [[VLA_ADDR]], align 8			// CHECK9-NEXT: [[TMP0:%.]] = load i64, i64 [[VLA_ADDR]], align 8
	// CHECK9-NEXT: [[TMP1:%.]] = load i64, i64 [[VLA_ADDR2]], align 8			// CHECK9-NEXT: [[TMP1:%.]] = load i64, i64 [[VLA_ADDR2]], align 8
	// CHECK9-NEXT: [[TMP2:%.]] = load i32, i32** [[A_ADDR]], align 8			// CHECK9-NEXT: [[TMP2:%.]] = load i32, i32** [[A_ADDR]], align 8
	// CHECK9-NEXT: [[TMP3:%.]] = load i32, i32 [[CONV]], align 4			// CHECK9-NEXT: [[TMP3:%.]] = load i32, i32 [[CONV]], align 8
	// CHECK9-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4			// CHECK9-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4
	// CHECK9-NEXT: [[TMP4:%.]] = load i32, i32 [[CONV3]], align 4			// CHECK9-NEXT: [[TMP4:%.]] = load i32, i32 [[CONV3]], align 8
	// CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_5]], align 4			// CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_5]], align 4
	// CHECK9-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4			// CHECK9-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4
	// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0			// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0
	// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1			// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
	// CHECK9-NEXT: [[CONV7:%.*]] = sext i32 [[DIV]] to i64			// CHECK9-NEXT: [[CONV7:%.*]] = sext i32 [[DIV]] to i64
	// CHECK9-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_5]], align 4			// CHECK9-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_5]], align 4
	// CHECK9-NEXT: [[SUB8:%.*]] = sub nsw i32 [[TMP6]], 0			// CHECK9-NEXT: [[SUB8:%.*]] = sub nsw i32 [[TMP6]], 0
	// CHECK9-NEXT: [[DIV9:%.*]] = sdiv i32 [[SUB8]], 1			// CHECK9-NEXT: [[DIV9:%.*]] = sdiv i32 [[SUB8]], 1
	▲ Show 20 Lines • Show All 490 Lines • ▼ Show 20 Lines
	// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8			// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
	// CHECK10-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8			// CHECK10-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
	// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8			// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
	// CHECK10-NEXT: [[CONV:%.]] = bitcast i64 [[N_ADDR]] to i32*			// CHECK10-NEXT: [[CONV:%.]] = bitcast i64 [[N_ADDR]] to i32*
	// CHECK10-NEXT: [[CONV3:%.]] = bitcast i64 [[M_ADDR]] to i32*			// CHECK10-NEXT: [[CONV3:%.]] = bitcast i64 [[M_ADDR]] to i32*
	// CHECK10-NEXT: [[TMP0:%.]] = load i64, i64 [[VLA_ADDR]], align 8			// CHECK10-NEXT: [[TMP0:%.]] = load i64, i64 [[VLA_ADDR]], align 8
	// CHECK10-NEXT: [[TMP1:%.]] = load i64, i64 [[VLA_ADDR2]], align 8			// CHECK10-NEXT: [[TMP1:%.]] = load i64, i64 [[VLA_ADDR2]], align 8
	// CHECK10-NEXT: [[TMP2:%.]] = load i32, i32** [[A_ADDR]], align 8			// CHECK10-NEXT: [[TMP2:%.]] = load i32, i32** [[A_ADDR]], align 8
	// CHECK10-NEXT: [[TMP3:%.]] = load i32, i32 [[CONV]], align 4			// CHECK10-NEXT: [[TMP3:%.]] = load i32, i32 [[CONV]], align 8
	// CHECK10-NEXT: [[CONV4:%.]] = bitcast i64 [[N_CASTED]] to i32*			// CHECK10-NEXT: [[CONV4:%.]] = bitcast i64 [[N_CASTED]] to i32*
	// CHECK10-NEXT: store i32 [[TMP3]], i32* [[CONV4]], align 4			// CHECK10-NEXT: store i32 [[TMP3]], i32* [[CONV4]], align 4
	// CHECK10-NEXT: [[TMP4:%.]] = load i64, i64 [[N_CASTED]], align 8			// CHECK10-NEXT: [[TMP4:%.]] = load i64, i64 [[N_CASTED]], align 8
	// CHECK10-NEXT: [[TMP5:%.]] = load i32, i32 [[CONV3]], align 4			// CHECK10-NEXT: [[TMP5:%.]] = load i32, i32 [[CONV3]], align 8
	// CHECK10-NEXT: [[CONV5:%.]] = bitcast i64 [[M_CASTED]] to i32*			// CHECK10-NEXT: [[CONV5:%.]] = bitcast i64 [[M_CASTED]] to i32*
	// CHECK10-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4			// CHECK10-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4
	// CHECK10-NEXT: [[TMP6:%.]] = load i64, i64 [[M_CASTED]], align 8			// CHECK10-NEXT: [[TMP6:%.]] = load i64, i64 [[M_CASTED]], align 8
	// CHECK10-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i64, i64, i32) @.omp_outlined. to void (i32, i32, ...)), i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP0]], i64 [[TMP1]], i32 [[TMP2]])			// CHECK10-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i64, i64, i32) @.omp_outlined. to void (i32, i32, ...)), i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP0]], i64 [[TMP1]], i32 [[TMP2]])
	// CHECK10-NEXT: ret void			// CHECK10-NEXT: ret void
	//			//
	//			//
	// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined.			// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined.
	Show All 29 Lines
	// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8			// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
	// CHECK10-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8			// CHECK10-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
	// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8			// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
	// CHECK10-NEXT: [[CONV:%.]] = bitcast i64 [[N_ADDR]] to i32*			// CHECK10-NEXT: [[CONV:%.]] = bitcast i64 [[N_ADDR]] to i32*
	// CHECK10-NEXT: [[CONV3:%.]] = bitcast i64 [[M_ADDR]] to i32*			// CHECK10-NEXT: [[CONV3:%.]] = bitcast i64 [[M_ADDR]] to i32*
	// CHECK10-NEXT: [[TMP0:%.]] = load i64, i64 [[VLA_ADDR]], align 8			// CHECK10-NEXT: [[TMP0:%.]] = load i64, i64 [[VLA_ADDR]], align 8
	// CHECK10-NEXT: [[TMP1:%.]] = load i64, i64 [[VLA_ADDR2]], align 8			// CHECK10-NEXT: [[TMP1:%.]] = load i64, i64 [[VLA_ADDR2]], align 8
	// CHECK10-NEXT: [[TMP2:%.]] = load i32, i32** [[A_ADDR]], align 8			// CHECK10-NEXT: [[TMP2:%.]] = load i32, i32** [[A_ADDR]], align 8
	// CHECK10-NEXT: [[TMP3:%.]] = load i32, i32 [[CONV]], align 4			// CHECK10-NEXT: [[TMP3:%.]] = load i32, i32 [[CONV]], align 8
	// CHECK10-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4			// CHECK10-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4
	// CHECK10-NEXT: [[TMP4:%.]] = load i32, i32 [[CONV3]], align 4			// CHECK10-NEXT: [[TMP4:%.]] = load i32, i32 [[CONV3]], align 8
	// CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_5]], align 4			// CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_5]], align 4
	// CHECK10-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4			// CHECK10-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4
	// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0			// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0
	// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1			// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
	// CHECK10-NEXT: [[CONV7:%.*]] = sext i32 [[DIV]] to i64			// CHECK10-NEXT: [[CONV7:%.*]] = sext i32 [[DIV]] to i64
	// CHECK10-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_5]], align 4			// CHECK10-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_5]], align 4
	// CHECK10-NEXT: [[SUB8:%.*]] = sub nsw i32 [[TMP6]], 0			// CHECK10-NEXT: [[SUB8:%.*]] = sub nsw i32 [[TMP6]], 0
	// CHECK10-NEXT: [[DIV9:%.*]] = sdiv i32 [[SUB8]], 1			// CHECK10-NEXT: [[DIV9:%.*]] = sdiv i32 [[SUB8]], 1
	Show All 38 Lines
	// CHECK10: omp.inner.for.cond:			// CHECK10: omp.inner.for.cond:
	// CHECK10-NEXT: [[TMP17:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !5			// CHECK10-NEXT: [[TMP17:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !5
	// CHECK10-NEXT: [[TMP18:%.]] = load i64, i64 [[DOTOMP_COMB_UB]], align 8, !llvm.access.group !5			// CHECK10-NEXT: [[TMP18:%.]] = load i64, i64 [[DOTOMP_COMB_UB]], align 8, !llvm.access.group !5
	// CHECK10-NEXT: [[CMP16:%.*]] = icmp sle i64 [[TMP17]], [[TMP18]]			// CHECK10-NEXT: [[CMP16:%.*]] = icmp sle i64 [[TMP17]], [[TMP18]]
	// CHECK10-NEXT: br i1 [[CMP16]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK10-NEXT: br i1 [[CMP16]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK10: omp.inner.for.body:			// CHECK10: omp.inner.for.body:
	// CHECK10-NEXT: [[TMP19:%.]] = load i64, i64 [[DOTOMP_COMB_LB]], align 8, !llvm.access.group !5			// CHECK10-NEXT: [[TMP19:%.]] = load i64, i64 [[DOTOMP_COMB_LB]], align 8, !llvm.access.group !5
	// CHECK10-NEXT: [[TMP20:%.]] = load i64, i64 [[DOTOMP_COMB_UB]], align 8, !llvm.access.group !5			// CHECK10-NEXT: [[TMP20:%.]] = load i64, i64 [[DOTOMP_COMB_UB]], align 8, !llvm.access.group !5
	// CHECK10-NEXT: [[TMP21:%.]] = load i32, i32 [[CONV]], align 4, !llvm.access.group !5			// CHECK10-NEXT: [[TMP21:%.]] = load i32, i32 [[CONV]], align 8, !llvm.access.group !5
	// CHECK10-NEXT: [[CONV17:%.]] = bitcast i64 [[N_CASTED]] to i32*			// CHECK10-NEXT: [[CONV17:%.]] = bitcast i64 [[N_CASTED]] to i32*
	// CHECK10-NEXT: store i32 [[TMP21]], i32* [[CONV17]], align 4, !llvm.access.group !5			// CHECK10-NEXT: store i32 [[TMP21]], i32* [[CONV17]], align 4, !llvm.access.group !5
	// CHECK10-NEXT: [[TMP22:%.]] = load i64, i64 [[N_CASTED]], align 8, !llvm.access.group !5			// CHECK10-NEXT: [[TMP22:%.]] = load i64, i64 [[N_CASTED]], align 8, !llvm.access.group !5
	// CHECK10-NEXT: [[TMP23:%.]] = load i32, i32 [[CONV3]], align 4, !llvm.access.group !5			// CHECK10-NEXT: [[TMP23:%.]] = load i32, i32 [[CONV3]], align 8, !llvm.access.group !5
	// CHECK10-NEXT: [[CONV18:%.]] = bitcast i64 [[M_CASTED]] to i32*			// CHECK10-NEXT: [[CONV18:%.]] = bitcast i64 [[M_CASTED]] to i32*
	// CHECK10-NEXT: store i32 [[TMP23]], i32* [[CONV18]], align 4, !llvm.access.group !5			// CHECK10-NEXT: store i32 [[TMP23]], i32* [[CONV18]], align 4, !llvm.access.group !5
	// CHECK10-NEXT: [[TMP24:%.]] = load i64, i64 [[M_CASTED]], align 8, !llvm.access.group !5			// CHECK10-NEXT: [[TMP24:%.]] = load i64, i64 [[M_CASTED]], align 8, !llvm.access.group !5
	// CHECK10-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i64, i64, i64, i64, i32) @.omp_outlined..1 to void (i32, i32, ...)), i64 [[TMP19]], i64 [[TMP20]], i64 [[TMP22]], i64 [[TMP24]], i64 [[TMP0]], i64 [[TMP1]], i32 [[TMP2]]), !llvm.access.group !5			// CHECK10-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i64, i64, i64, i64, i32) @.omp_outlined..1 to void (i32, i32, ...)), i64 [[TMP19]], i64 [[TMP20]], i64 [[TMP22]], i64 [[TMP24]], i64 [[TMP0]], i64 [[TMP1]], i32 [[TMP2]]), !llvm.access.group !5
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK10: omp.inner.for.inc:			// CHECK10: omp.inner.for.inc:
	// CHECK10-NEXT: [[TMP25:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !5			// CHECK10-NEXT: [[TMP25:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !5
	// CHECK10-NEXT: [[TMP26:%.]] = load i64, i64 [[DOTOMP_STRIDE]], align 8, !llvm.access.group !5			// CHECK10-NEXT: [[TMP26:%.]] = load i64, i64 [[DOTOMP_STRIDE]], align 8, !llvm.access.group !5
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	// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8			// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
	// CHECK10-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8			// CHECK10-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
	// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8			// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
	// CHECK10-NEXT: [[CONV:%.]] = bitcast i64 [[N_ADDR]] to i32*			// CHECK10-NEXT: [[CONV:%.]] = bitcast i64 [[N_ADDR]] to i32*
	// CHECK10-NEXT: [[CONV3:%.]] = bitcast i64 [[M_ADDR]] to i32*			// CHECK10-NEXT: [[CONV3:%.]] = bitcast i64 [[M_ADDR]] to i32*
	// CHECK10-NEXT: [[TMP0:%.]] = load i64, i64 [[VLA_ADDR]], align 8			// CHECK10-NEXT: [[TMP0:%.]] = load i64, i64 [[VLA_ADDR]], align 8
	// CHECK10-NEXT: [[TMP1:%.]] = load i64, i64 [[VLA_ADDR2]], align 8			// CHECK10-NEXT: [[TMP1:%.]] = load i64, i64 [[VLA_ADDR2]], align 8
	// CHECK10-NEXT: [[TMP2:%.]] = load i32, i32** [[A_ADDR]], align 8			// CHECK10-NEXT: [[TMP2:%.]] = load i32, i32** [[A_ADDR]], align 8
	// CHECK10-NEXT: [[TMP3:%.]] = load i32, i32 [[CONV]], align 4			// CHECK10-NEXT: [[TMP3:%.]] = load i32, i32 [[CONV]], align 8
	// CHECK10-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4			// CHECK10-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4
	// CHECK10-NEXT: [[TMP4:%.]] = load i32, i32 [[CONV3]], align 4			// CHECK10-NEXT: [[TMP4:%.]] = load i32, i32 [[CONV3]], align 8
	// CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_5]], align 4			// CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_5]], align 4
	// CHECK10-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4			// CHECK10-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4
	// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0			// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0
	// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1			// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
	// CHECK10-NEXT: [[CONV7:%.*]] = sext i32 [[DIV]] to i64			// CHECK10-NEXT: [[CONV7:%.*]] = sext i32 [[DIV]] to i64
	// CHECK10-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_5]], align 4			// CHECK10-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_5]], align 4
	// CHECK10-NEXT: [[SUB8:%.*]] = sub nsw i32 [[TMP6]], 0			// CHECK10-NEXT: [[SUB8:%.*]] = sub nsw i32 [[TMP6]], 0
	// CHECK10-NEXT: [[DIV9:%.*]] = sdiv i32 [[SUB8]], 1			// CHECK10-NEXT: [[DIV9:%.*]] = sdiv i32 [[SUB8]], 1
	▲ Show 20 Lines • Show All 2,511 Lines • Show Last 20 Lines

clang/test/OpenMP/target_teams_distribute_parallel_for_simd_dist_schedule_codegen.cpp

This file is larger than 256 KB, so syntax highlighting is disabled by default.

	Show First 20 Lines • Show All 3,289 Lines • ▼ Show 20 Lines
	// CHECK9-NEXT: [[A_ADDR:%.]] = alloca i32, align 8			// CHECK9-NEXT: [[A_ADDR:%.]] = alloca i32, align 8
	// CHECK9-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8			// CHECK9-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8
	// CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8			// CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
	// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8			// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
	// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8			// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
	// CHECK9-NEXT: [[CONV:%.]] = bitcast i64 [[N_ADDR]] to i32*			// CHECK9-NEXT: [[CONV:%.]] = bitcast i64 [[N_ADDR]] to i32*
	// CHECK9-NEXT: [[TMP0:%.]] = load i64, i64 [[VLA_ADDR]], align 8			// CHECK9-NEXT: [[TMP0:%.]] = load i64, i64 [[VLA_ADDR]], align 8
	// CHECK9-NEXT: [[TMP1:%.]] = load i32, i32** [[A_ADDR]], align 8			// CHECK9-NEXT: [[TMP1:%.]] = load i32, i32** [[A_ADDR]], align 8
	// CHECK9-NEXT: [[TMP2:%.]] = load i32, i32 [[CONV]], align 4			// CHECK9-NEXT: [[TMP2:%.]] = load i32, i32 [[CONV]], align 8
	// CHECK9-NEXT: [[CONV1:%.]] = bitcast i64 [[N_CASTED]] to i32*			// CHECK9-NEXT: [[CONV1:%.]] = bitcast i64 [[N_CASTED]] to i32*
	// CHECK9-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4			// CHECK9-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4
	// CHECK9-NEXT: [[TMP3:%.]] = load i64, i64 [[N_CASTED]], align 8			// CHECK9-NEXT: [[TMP3:%.]] = load i64, i64 [[N_CASTED]], align 8
	// CHECK9-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i32) @.omp_outlined. to void (i32, i32, ...)), i64 [[TMP3]], i64 [[TMP0]], i32 [[TMP1]])			// CHECK9-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i32) @.omp_outlined. to void (i32, i32, ...)), i64 [[TMP3]], i64 [[TMP0]], i32 [[TMP1]])
	// CHECK9-NEXT: ret void			// CHECK9-NEXT: ret void
	//			//
	//			//
	// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined.			// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined.
	Show All 18 Lines
	// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8			// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
	// CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8			// CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
	// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8			// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
	// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8			// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
	// CHECK9-NEXT: [[CONV:%.]] = bitcast i64 [[N_ADDR]] to i32*			// CHECK9-NEXT: [[CONV:%.]] = bitcast i64 [[N_ADDR]] to i32*
	// CHECK9-NEXT: [[TMP0:%.]] = load i64, i64 [[VLA_ADDR]], align 8			// CHECK9-NEXT: [[TMP0:%.]] = load i64, i64 [[VLA_ADDR]], align 8
	// CHECK9-NEXT: [[TMP1:%.]] = load i32, i32** [[A_ADDR]], align 8			// CHECK9-NEXT: [[TMP1:%.]] = load i32, i32** [[A_ADDR]], align 8
	// CHECK9-NEXT: [[TMP2:%.]] = load i32, i32 [[CONV]], align 4			// CHECK9-NEXT: [[TMP2:%.]] = load i32, i32 [[CONV]], align 8
	// CHECK9-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4			// CHECK9-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
	// CHECK9-NEXT: [[TMP3:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4			// CHECK9-NEXT: [[TMP3:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4
	// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0			// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
	// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1			// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
	// CHECK9-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1			// CHECK9-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
	// CHECK9-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4			// CHECK9-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4
	// CHECK9-NEXT: store i32 0, i32* [[I]], align 4			// CHECK9-NEXT: store i32 0, i32* [[I]], align 4
	// CHECK9-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4			// CHECK9-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4
	Show All 29 Lines
	// CHECK9-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !9			// CHECK9-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !9
	// CHECK9-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]			// CHECK9-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
	// CHECK9-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK9-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK9: omp.inner.for.body:			// CHECK9: omp.inner.for.body:
	// CHECK9-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !9			// CHECK9-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !9
	// CHECK9-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64			// CHECK9-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64
	// CHECK9-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !9			// CHECK9-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !9
	// CHECK9-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64			// CHECK9-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
	// CHECK9-NEXT: [[TMP19:%.]] = load i32, i32 [[CONV]], align 4, !llvm.access.group !9			// CHECK9-NEXT: [[TMP19:%.]] = load i32, i32 [[CONV]], align 8, !llvm.access.group !9
	// CHECK9-NEXT: [[CONV6:%.]] = bitcast i64 [[N_CASTED]] to i32*			// CHECK9-NEXT: [[CONV6:%.]] = bitcast i64 [[N_CASTED]] to i32*
	// CHECK9-NEXT: store i32 [[TMP19]], i32* [[CONV6]], align 4, !llvm.access.group !9			// CHECK9-NEXT: store i32 [[TMP19]], i32* [[CONV6]], align 4, !llvm.access.group !9
	// CHECK9-NEXT: [[TMP20:%.]] = load i64, i64 [[N_CASTED]], align 8, !llvm.access.group !9			// CHECK9-NEXT: [[TMP20:%.]] = load i64, i64 [[N_CASTED]], align 8, !llvm.access.group !9
	// CHECK9-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i64, i64, i32) @.omp_outlined..1 to void (i32, i32, ...)), i64 [[TMP16]], i64 [[TMP18]], i64 [[TMP20]], i64 [[TMP0]], i32 [[TMP1]]), !llvm.access.group !9			// CHECK9-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i64, i64, i32) @.omp_outlined..1 to void (i32, i32, ...)), i64 [[TMP16]], i64 [[TMP18]], i64 [[TMP20]], i64 [[TMP0]], i32 [[TMP1]]), !llvm.access.group !9
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK9: omp.inner.for.inc:			// CHECK9: omp.inner.for.inc:
	// CHECK9-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9			// CHECK9-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK9-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !9			// CHECK9-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !9
	▲ Show 20 Lines • Show All 48 Lines • ▼ Show 20 Lines
	// CHECK9-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8			// CHECK9-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
	// CHECK9-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8			// CHECK9-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
	// CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8			// CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
	// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8			// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
	// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8			// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
	// CHECK9-NEXT: [[CONV:%.]] = bitcast i64 [[N_ADDR]] to i32*			// CHECK9-NEXT: [[CONV:%.]] = bitcast i64 [[N_ADDR]] to i32*
	// CHECK9-NEXT: [[TMP0:%.]] = load i64, i64 [[VLA_ADDR]], align 8			// CHECK9-NEXT: [[TMP0:%.]] = load i64, i64 [[VLA_ADDR]], align 8
	// CHECK9-NEXT: [[TMP1:%.]] = load i32, i32** [[A_ADDR]], align 8			// CHECK9-NEXT: [[TMP1:%.]] = load i32, i32** [[A_ADDR]], align 8
	// CHECK9-NEXT: [[TMP2:%.]] = load i32, i32 [[CONV]], align 4			// CHECK9-NEXT: [[TMP2:%.]] = load i32, i32 [[CONV]], align 8
	// CHECK9-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4			// CHECK9-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
	// CHECK9-NEXT: [[TMP3:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4			// CHECK9-NEXT: [[TMP3:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4
	// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0			// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
	// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1			// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
	// CHECK9-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1			// CHECK9-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
	// CHECK9-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4			// CHECK9-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4
	// CHECK9-NEXT: store i32 0, i32* [[I]], align 4			// CHECK9-NEXT: store i32 0, i32* [[I]], align 4
	// CHECK9-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4			// CHECK9-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4
	▲ Show 20 Lines • Show All 83 Lines • ▼ Show 20 Lines
	// CHECK9-NEXT: [[A_ADDR:%.]] = alloca i32, align 8			// CHECK9-NEXT: [[A_ADDR:%.]] = alloca i32, align 8
	// CHECK9-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8			// CHECK9-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8
	// CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8			// CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
	// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8			// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
	// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8			// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
	// CHECK9-NEXT: [[CONV:%.]] = bitcast i64 [[N_ADDR]] to i32*			// CHECK9-NEXT: [[CONV:%.]] = bitcast i64 [[N_ADDR]] to i32*
	// CHECK9-NEXT: [[TMP0:%.]] = load i64, i64 [[VLA_ADDR]], align 8			// CHECK9-NEXT: [[TMP0:%.]] = load i64, i64 [[VLA_ADDR]], align 8
	// CHECK9-NEXT: [[TMP1:%.]] = load i32, i32** [[A_ADDR]], align 8			// CHECK9-NEXT: [[TMP1:%.]] = load i32, i32** [[A_ADDR]], align 8
	// CHECK9-NEXT: [[TMP2:%.]] = load i32, i32 [[CONV]], align 4			// CHECK9-NEXT: [[TMP2:%.]] = load i32, i32 [[CONV]], align 8
	// CHECK9-NEXT: [[CONV1:%.]] = bitcast i64 [[N_CASTED]] to i32*			// CHECK9-NEXT: [[CONV1:%.]] = bitcast i64 [[N_CASTED]] to i32*
	// CHECK9-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4			// CHECK9-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4
	// CHECK9-NEXT: [[TMP3:%.]] = load i64, i64 [[N_CASTED]], align 8			// CHECK9-NEXT: [[TMP3:%.]] = load i64, i64 [[N_CASTED]], align 8
	// CHECK9-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i32) @.omp_outlined..2 to void (i32, i32, ...)), i64 [[TMP3]], i64 [[TMP0]], i32 [[TMP1]])			// CHECK9-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i32) @.omp_outlined..2 to void (i32, i32, ...)), i64 [[TMP3]], i64 [[TMP0]], i32 [[TMP1]])
	// CHECK9-NEXT: ret void			// CHECK9-NEXT: ret void
	//			//
	//			//
	// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..2			// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..2
	Show All 18 Lines
	// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8			// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
	// CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8			// CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
	// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8			// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
	// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8			// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
	// CHECK9-NEXT: [[CONV:%.]] = bitcast i64 [[N_ADDR]] to i32*			// CHECK9-NEXT: [[CONV:%.]] = bitcast i64 [[N_ADDR]] to i32*
	// CHECK9-NEXT: [[TMP0:%.]] = load i64, i64 [[VLA_ADDR]], align 8			// CHECK9-NEXT: [[TMP0:%.]] = load i64, i64 [[VLA_ADDR]], align 8
	// CHECK9-NEXT: [[TMP1:%.]] = load i32, i32** [[A_ADDR]], align 8			// CHECK9-NEXT: [[TMP1:%.]] = load i32, i32** [[A_ADDR]], align 8
	// CHECK9-NEXT: [[TMP2:%.]] = load i32, i32 [[CONV]], align 4			// CHECK9-NEXT: [[TMP2:%.]] = load i32, i32 [[CONV]], align 8
	// CHECK9-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4			// CHECK9-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
	// CHECK9-NEXT: [[TMP3:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4			// CHECK9-NEXT: [[TMP3:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4
	// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0			// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
	// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1			// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
	// CHECK9-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1			// CHECK9-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
	// CHECK9-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4			// CHECK9-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4
	// CHECK9-NEXT: store i32 0, i32* [[I]], align 4			// CHECK9-NEXT: store i32 0, i32* [[I]], align 4
	// CHECK9-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4			// CHECK9-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4
	Show All 29 Lines
	// CHECK9-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !18			// CHECK9-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !18
	// CHECK9-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]			// CHECK9-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
	// CHECK9-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK9-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK9: omp.inner.for.body:			// CHECK9: omp.inner.for.body:
	// CHECK9-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !18			// CHECK9-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !18
	// CHECK9-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64			// CHECK9-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64
	// CHECK9-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !18			// CHECK9-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !18
	// CHECK9-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64			// CHECK9-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
	// CHECK9-NEXT: [[TMP19:%.]] = load i32, i32 [[CONV]], align 4, !llvm.access.group !18			// CHECK9-NEXT: [[TMP19:%.]] = load i32, i32 [[CONV]], align 8, !llvm.access.group !18
	// CHECK9-NEXT: [[CONV6:%.]] = bitcast i64 [[N_CASTED]] to i32*			// CHECK9-NEXT: [[CONV6:%.]] = bitcast i64 [[N_CASTED]] to i32*
	// CHECK9-NEXT: store i32 [[TMP19]], i32* [[CONV6]], align 4, !llvm.access.group !18			// CHECK9-NEXT: store i32 [[TMP19]], i32* [[CONV6]], align 4, !llvm.access.group !18
	// CHECK9-NEXT: [[TMP20:%.]] = load i64, i64 [[N_CASTED]], align 8, !llvm.access.group !18			// CHECK9-NEXT: [[TMP20:%.]] = load i64, i64 [[N_CASTED]], align 8, !llvm.access.group !18
	// CHECK9-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i64, i64, i32) @.omp_outlined..3 to void (i32, i32, ...)), i64 [[TMP16]], i64 [[TMP18]], i64 [[TMP20]], i64 [[TMP0]], i32 [[TMP1]]), !llvm.access.group !18			// CHECK9-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i64, i64, i32) @.omp_outlined..3 to void (i32, i32, ...)), i64 [[TMP16]], i64 [[TMP18]], i64 [[TMP20]], i64 [[TMP0]], i32 [[TMP1]]), !llvm.access.group !18
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK9: omp.inner.for.inc:			// CHECK9: omp.inner.for.inc:
	// CHECK9-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18			// CHECK9-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK9-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !18			// CHECK9-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !18
	▲ Show 20 Lines • Show All 48 Lines • ▼ Show 20 Lines
	// CHECK9-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8			// CHECK9-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
	// CHECK9-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8			// CHECK9-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
	// CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8			// CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
	// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8			// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
	// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8			// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
	// CHECK9-NEXT: [[CONV:%.]] = bitcast i64 [[N_ADDR]] to i32*			// CHECK9-NEXT: [[CONV:%.]] = bitcast i64 [[N_ADDR]] to i32*
	// CHECK9-NEXT: [[TMP0:%.]] = load i64, i64 [[VLA_ADDR]], align 8			// CHECK9-NEXT: [[TMP0:%.]] = load i64, i64 [[VLA_ADDR]], align 8
	// CHECK9-NEXT: [[TMP1:%.]] = load i32, i32** [[A_ADDR]], align 8			// CHECK9-NEXT: [[TMP1:%.]] = load i32, i32** [[A_ADDR]], align 8
	// CHECK9-NEXT: [[TMP2:%.]] = load i32, i32 [[CONV]], align 4			// CHECK9-NEXT: [[TMP2:%.]] = load i32, i32 [[CONV]], align 8
	// CHECK9-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4			// CHECK9-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
	// CHECK9-NEXT: [[TMP3:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4			// CHECK9-NEXT: [[TMP3:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4
	// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0			// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
	// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1			// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
	// CHECK9-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1			// CHECK9-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
	// CHECK9-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4			// CHECK9-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4
	// CHECK9-NEXT: store i32 0, i32* [[I]], align 4			// CHECK9-NEXT: store i32 0, i32* [[I]], align 4
	// CHECK9-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4			// CHECK9-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4
	▲ Show 20 Lines • Show All 87 Lines • ▼ Show 20 Lines
	// CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8			// CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
	// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8			// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
	// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8			// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
	// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8			// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
	// CHECK9-NEXT: [[CONV:%.]] = bitcast i64 [[N_ADDR]] to i32*			// CHECK9-NEXT: [[CONV:%.]] = bitcast i64 [[N_ADDR]] to i32*
	// CHECK9-NEXT: [[TMP0:%.]] = load i64, i64 [[VLA_ADDR]], align 8			// CHECK9-NEXT: [[TMP0:%.]] = load i64, i64 [[VLA_ADDR]], align 8
	// CHECK9-NEXT: [[TMP1:%.]] = load i32, i32** [[A_ADDR]], align 8			// CHECK9-NEXT: [[TMP1:%.]] = load i32, i32** [[A_ADDR]], align 8
	// CHECK9-NEXT: [[CONV1:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__ADDR]] to i32*			// CHECK9-NEXT: [[CONV1:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__ADDR]] to i32*
	// CHECK9-NEXT: [[TMP2:%.]] = load i32, i32 [[CONV]], align 4			// CHECK9-NEXT: [[TMP2:%.]] = load i32, i32 [[CONV]], align 8
	// CHECK9-NEXT: [[CONV2:%.]] = bitcast i64 [[N_CASTED]] to i32*			// CHECK9-NEXT: [[CONV2:%.]] = bitcast i64 [[N_CASTED]] to i32*
	// CHECK9-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4			// CHECK9-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4
	// CHECK9-NEXT: [[TMP3:%.]] = load i64, i64 [[N_CASTED]], align 8			// CHECK9-NEXT: [[TMP3:%.]] = load i64, i64 [[N_CASTED]], align 8
	// CHECK9-NEXT: [[TMP4:%.]] = load i32, i32 [[CONV1]], align 4			// CHECK9-NEXT: [[TMP4:%.]] = load i32, i32 [[CONV1]], align 8
	// CHECK9-NEXT: [[CONV3:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED]] to i32*			// CHECK9-NEXT: [[CONV3:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED]] to i32*
	// CHECK9-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4			// CHECK9-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
	// CHECK9-NEXT: [[TMP5:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED]], align 8			// CHECK9-NEXT: [[TMP5:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED]], align 8
	// CHECK9-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i32, i64) @.omp_outlined..5 to void (i32, i32, ...)), i64 [[TMP3]], i64 [[TMP0]], i32 [[TMP1]], i64 [[TMP5]])			// CHECK9-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i32, i64) @.omp_outlined..5 to void (i32, i32, ...)), i64 [[TMP3]], i64 [[TMP0]], i32 [[TMP1]], i64 [[TMP5]])
	// CHECK9-NEXT: ret void			// CHECK9-NEXT: ret void
	//			//
	//			//
	// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..5			// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..5
	Show All 22 Lines
	// CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8			// CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
	// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8			// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
	// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8			// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
	// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8			// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
	// CHECK9-NEXT: [[CONV:%.]] = bitcast i64 [[N_ADDR]] to i32*			// CHECK9-NEXT: [[CONV:%.]] = bitcast i64 [[N_ADDR]] to i32*
	// CHECK9-NEXT: [[TMP0:%.]] = load i64, i64 [[VLA_ADDR]], align 8			// CHECK9-NEXT: [[TMP0:%.]] = load i64, i64 [[VLA_ADDR]], align 8
	// CHECK9-NEXT: [[TMP1:%.]] = load i32, i32** [[A_ADDR]], align 8			// CHECK9-NEXT: [[TMP1:%.]] = load i32, i32** [[A_ADDR]], align 8
	// CHECK9-NEXT: [[CONV1:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__ADDR]] to i32*			// CHECK9-NEXT: [[CONV1:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__ADDR]] to i32*
	// CHECK9-NEXT: [[TMP2:%.]] = load i32, i32 [[CONV]], align 4			// CHECK9-NEXT: [[TMP2:%.]] = load i32, i32 [[CONV]], align 8
	// CHECK9-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4			// CHECK9-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4
	// CHECK9-NEXT: [[TMP3:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2]], align 4			// CHECK9-NEXT: [[TMP3:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2]], align 4
	// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0			// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
	// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1			// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
	// CHECK9-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1			// CHECK9-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1
	// CHECK9-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_3]], align 4			// CHECK9-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_3]], align 4
	// CHECK9-NEXT: store i32 0, i32* [[I]], align 4			// CHECK9-NEXT: store i32 0, i32* [[I]], align 4
	// CHECK9-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2]], align 4			// CHECK9-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2]], align 4
	// CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]]			// CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]]
	// CHECK9-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.]], label [[OMP_PRECOND_END:%.]]			// CHECK9-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.]], label [[OMP_PRECOND_END:%.]]
	// CHECK9: omp.precond.then:			// CHECK9: omp.precond.then:
	// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4			// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
	// CHECK9-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_3]], align 4			// CHECK9-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_3]], align 4
	// CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4			// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
	// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4			// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
	// CHECK9-NEXT: [[TMP6:%.]] = load i32, i32 [[CONV1]], align 4			// CHECK9-NEXT: [[TMP6:%.]] = load i32, i32 [[CONV1]], align 8
	// CHECK9-NEXT: [[TMP7:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK9-NEXT: [[TMP7:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK9-NEXT: [[TMP8:%.]] = load i32, i32 [[TMP7]], align 4			// CHECK9-NEXT: [[TMP8:%.]] = load i32, i32 [[TMP7]], align 4
	// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP6]])			// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP6]])
	// CHECK9-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK9-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4
	// CHECK9-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_3]], align 4			// CHECK9-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_3]], align 4
	// CHECK9-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]]			// CHECK9-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]]
	// CHECK9-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.]], label [[COND_FALSE:%.]]			// CHECK9-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.]], label [[COND_FALSE:%.]]
	// CHECK9: cond.true:			// CHECK9: cond.true:
	Show All 14 Lines
	// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP15]], 1			// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP15]], 1
	// CHECK9-NEXT: [[CMP7:%.*]] = icmp slt i32 [[TMP14]], [[ADD]]			// CHECK9-NEXT: [[CMP7:%.*]] = icmp slt i32 [[TMP14]], [[ADD]]
	// CHECK9-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK9-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK9: omp.inner.for.body:			// CHECK9: omp.inner.for.body:
	// CHECK9-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !24			// CHECK9-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !24
	// CHECK9-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64			// CHECK9-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
	// CHECK9-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !24			// CHECK9-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !24
	// CHECK9-NEXT: [[TMP19:%.*]] = zext i32 [[TMP18]] to i64			// CHECK9-NEXT: [[TMP19:%.*]] = zext i32 [[TMP18]] to i64
	// CHECK9-NEXT: [[TMP20:%.]] = load i32, i32 [[CONV]], align 4, !llvm.access.group !24			// CHECK9-NEXT: [[TMP20:%.]] = load i32, i32 [[CONV]], align 8, !llvm.access.group !24
	// CHECK9-NEXT: [[CONV8:%.]] = bitcast i64 [[N_CASTED]] to i32*			// CHECK9-NEXT: [[CONV8:%.]] = bitcast i64 [[N_CASTED]] to i32*
	// CHECK9-NEXT: store i32 [[TMP20]], i32* [[CONV8]], align 4, !llvm.access.group !24			// CHECK9-NEXT: store i32 [[TMP20]], i32* [[CONV8]], align 4, !llvm.access.group !24
	// CHECK9-NEXT: [[TMP21:%.]] = load i64, i64 [[N_CASTED]], align 8, !llvm.access.group !24			// CHECK9-NEXT: [[TMP21:%.]] = load i64, i64 [[N_CASTED]], align 8, !llvm.access.group !24
	// CHECK9-NEXT: [[TMP22:%.]] = load i32, i32 [[CONV1]], align 4, !llvm.access.group !24			// CHECK9-NEXT: [[TMP22:%.]] = load i32, i32 [[CONV1]], align 8, !llvm.access.group !24
	// CHECK9-NEXT: [[CONV9:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED]] to i32*			// CHECK9-NEXT: [[CONV9:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED]] to i32*
	// CHECK9-NEXT: store i32 [[TMP22]], i32* [[CONV9]], align 4, !llvm.access.group !24			// CHECK9-NEXT: store i32 [[TMP22]], i32* [[CONV9]], align 4, !llvm.access.group !24
	// CHECK9-NEXT: [[TMP23:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !24			// CHECK9-NEXT: [[TMP23:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !24
	// CHECK9-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i64, i64, i32, i64) @.omp_outlined..6 to void (i32, i32, ...)), i64 [[TMP17]], i64 [[TMP19]], i64 [[TMP21]], i64 [[TMP0]], i32 [[TMP1]], i64 [[TMP23]]), !llvm.access.group !24			// CHECK9-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i64, i64, i32, i64) @.omp_outlined..6 to void (i32, i32, ...)), i64 [[TMP17]], i64 [[TMP19]], i64 [[TMP21]], i64 [[TMP0]], i32 [[TMP1]], i64 [[TMP23]]), !llvm.access.group !24
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK9: omp.inner.for.inc:			// CHECK9: omp.inner.for.inc:
	// CHECK9-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !24			// CHECK9-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !24
	// CHECK9-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !24			// CHECK9-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !24
	▲ Show 20 Lines • Show All 74 Lines • ▼ Show 20 Lines
	// CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8			// CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
	// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8			// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
	// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8			// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
	// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8			// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
	// CHECK9-NEXT: [[CONV:%.]] = bitcast i64 [[N_ADDR]] to i32*			// CHECK9-NEXT: [[CONV:%.]] = bitcast i64 [[N_ADDR]] to i32*
	// CHECK9-NEXT: [[TMP0:%.]] = load i64, i64 [[VLA_ADDR]], align 8			// CHECK9-NEXT: [[TMP0:%.]] = load i64, i64 [[VLA_ADDR]], align 8
	// CHECK9-NEXT: [[TMP1:%.]] = load i32, i32** [[A_ADDR]], align 8			// CHECK9-NEXT: [[TMP1:%.]] = load i32, i32** [[A_ADDR]], align 8
	// CHECK9-NEXT: [[CONV1:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__ADDR]] to i32*			// CHECK9-NEXT: [[CONV1:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__ADDR]] to i32*
	// CHECK9-NEXT: [[TMP2:%.]] = load i32, i32 [[CONV]], align 4			// CHECK9-NEXT: [[TMP2:%.]] = load i32, i32 [[CONV]], align 8
	// CHECK9-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4			// CHECK9-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4
	// CHECK9-NEXT: [[TMP3:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2]], align 4			// CHECK9-NEXT: [[TMP3:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2]], align 4
	// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0			// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
	// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1			// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
	// CHECK9-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1			// CHECK9-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1
	// CHECK9-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_3]], align 4			// CHECK9-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_3]], align 4
	// CHECK9-NEXT: store i32 0, i32* [[I]], align 4			// CHECK9-NEXT: store i32 0, i32* [[I]], align 4
	// CHECK9-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2]], align 4			// CHECK9-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2]], align 4
	▲ Show 20 Lines • Show All 501 Lines • ▼ Show 20 Lines
	// CHECK9-NEXT: entry:			// CHECK9-NEXT: entry:
	// CHECK9-NEXT: [[A_ADDR:%.]] = alloca [10 x i32], align 8			// CHECK9-NEXT: [[A_ADDR:%.]] = alloca [10 x i32], align 8
	// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8			// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
	// CHECK9-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8			// CHECK9-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
	// CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8			// CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8
	// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8			// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
	// CHECK9-NEXT: [[TMP0:%.]] = load [10 x i32], [10 x i32]** [[A_ADDR]], align 8			// CHECK9-NEXT: [[TMP0:%.]] = load [10 x i32], [10 x i32]** [[A_ADDR]], align 8
	// CHECK9-NEXT: [[CONV:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__ADDR]] to i32*			// CHECK9-NEXT: [[CONV:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__ADDR]] to i32*
	// CHECK9-NEXT: [[TMP1:%.]] = load i32, i32 [[CONV]], align 4			// CHECK9-NEXT: [[TMP1:%.]] = load i32, i32 [[CONV]], align 8
	// CHECK9-NEXT: [[CONV1:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED]] to i32*			// CHECK9-NEXT: [[CONV1:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED]] to i32*
	// CHECK9-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4			// CHECK9-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4
	// CHECK9-NEXT: [[TMP2:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED]], align 8			// CHECK9-NEXT: [[TMP2:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED]], align 8
	// CHECK9-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, [10 x i32], i64) @.omp_outlined..15 to void (i32, i32, ...)), [10 x i32] [[TMP0]], i64 [[TMP2]])			// CHECK9-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, [10 x i32], i64) @.omp_outlined..15 to void (i32, i32, ...)), [10 x i32] [[TMP0]], i64 [[TMP2]])
	// CHECK9-NEXT: ret void			// CHECK9-NEXT: ret void
	//			//
	//			//
	// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..15			// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..15
	Show All 16 Lines
	// CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8			// CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8
	// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8			// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
	// CHECK9-NEXT: [[TMP0:%.]] = load [10 x i32], [10 x i32]** [[A_ADDR]], align 8			// CHECK9-NEXT: [[TMP0:%.]] = load [10 x i32], [10 x i32]** [[A_ADDR]], align 8
	// CHECK9-NEXT: [[CONV:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__ADDR]] to i32*			// CHECK9-NEXT: [[CONV:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__ADDR]] to i32*
	// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4			// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
	// CHECK9-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4			// CHECK9-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4			// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
	// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4			// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
	// CHECK9-NEXT: [[TMP1:%.]] = load i32, i32 [[CONV]], align 4			// CHECK9-NEXT: [[TMP1:%.]] = load i32, i32 [[CONV]], align 8
	// CHECK9-NEXT: [[TMP2:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK9-NEXT: [[TMP2:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK9-NEXT: [[TMP3:%.]] = load i32, i32 [[TMP2]], align 4			// CHECK9-NEXT: [[TMP3:%.]] = load i32, i32 [[TMP2]], align 4
	// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP1]])			// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP1]])
	// CHECK9-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK9-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4
	// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 9			// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 9
	// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.]], label [[COND_FALSE:%.]]			// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.]], label [[COND_FALSE:%.]]
	// CHECK9: cond.true:			// CHECK9: cond.true:
	// CHECK9-NEXT: br label [[COND_END:%.*]]			// CHECK9-NEXT: br label [[COND_END:%.*]]
	Show All 10 Lines
	// CHECK9-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !42			// CHECK9-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !42
	// CHECK9-NEXT: [[CMP1:%.*]] = icmp slt i32 [[TMP7]], 10			// CHECK9-NEXT: [[CMP1:%.*]] = icmp slt i32 [[TMP7]], 10
	// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK9: omp.inner.for.body:			// CHECK9: omp.inner.for.body:
	// CHECK9-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !42			// CHECK9-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !42
	// CHECK9-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64			// CHECK9-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
	// CHECK9-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !42			// CHECK9-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !42
	// CHECK9-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64			// CHECK9-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
	// CHECK9-NEXT: [[TMP12:%.]] = load i32, i32 [[CONV]], align 4, !llvm.access.group !42			// CHECK9-NEXT: [[TMP12:%.]] = load i32, i32 [[CONV]], align 8, !llvm.access.group !42
	// CHECK9-NEXT: [[CONV2:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED]] to i32*			// CHECK9-NEXT: [[CONV2:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED]] to i32*
	// CHECK9-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4, !llvm.access.group !42			// CHECK9-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4, !llvm.access.group !42
	// CHECK9-NEXT: [[TMP13:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !42			// CHECK9-NEXT: [[TMP13:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !42
	// CHECK9-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, [10 x i32], i64) @.omp_outlined..16 to void (i32, i32, ...)), i64 [[TMP9]], i64 [[TMP11]], [10 x i32] [[TMP0]], i64 [[TMP13]]), !llvm.access.group !42			// CHECK9-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, [10 x i32], i64) @.omp_outlined..16 to void (i32, i32, ...)), i64 [[TMP9]], i64 [[TMP11]], [10 x i32] [[TMP0]], i64 [[TMP13]]), !llvm.access.group !42
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK9: omp.inner.for.inc:			// CHECK9: omp.inner.for.inc:
	// CHECK9-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !42			// CHECK9-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !42
	// CHECK9-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !42			// CHECK9-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !42
	▲ Show 20 Lines • Show All 377 Lines • ▼ Show 20 Lines
	// CHECK10-NEXT: [[A_ADDR:%.]] = alloca i32, align 8			// CHECK10-NEXT: [[A_ADDR:%.]] = alloca i32, align 8
	// CHECK10-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8			// CHECK10-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8
	// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8			// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
	// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8			// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
	// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8			// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
	// CHECK10-NEXT: [[CONV:%.]] = bitcast i64 [[N_ADDR]] to i32*			// CHECK10-NEXT: [[CONV:%.]] = bitcast i64 [[N_ADDR]] to i32*
	// CHECK10-NEXT: [[TMP0:%.]] = load i64, i64 [[VLA_ADDR]], align 8			// CHECK10-NEXT: [[TMP0:%.]] = load i64, i64 [[VLA_ADDR]], align 8
	// CHECK10-NEXT: [[TMP1:%.]] = load i32, i32** [[A_ADDR]], align 8			// CHECK10-NEXT: [[TMP1:%.]] = load i32, i32** [[A_ADDR]], align 8
	// CHECK10-NEXT: [[TMP2:%.]] = load i32, i32 [[CONV]], align 4			// CHECK10-NEXT: [[TMP2:%.]] = load i32, i32 [[CONV]], align 8
	// CHECK10-NEXT: [[CONV1:%.]] = bitcast i64 [[N_CASTED]] to i32*			// CHECK10-NEXT: [[CONV1:%.]] = bitcast i64 [[N_CASTED]] to i32*
	// CHECK10-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4			// CHECK10-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4
	// CHECK10-NEXT: [[TMP3:%.]] = load i64, i64 [[N_CASTED]], align 8			// CHECK10-NEXT: [[TMP3:%.]] = load i64, i64 [[N_CASTED]], align 8
	// CHECK10-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i32) @.omp_outlined. to void (i32, i32, ...)), i64 [[TMP3]], i64 [[TMP0]], i32 [[TMP1]])			// CHECK10-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i32) @.omp_outlined. to void (i32, i32, ...)), i64 [[TMP3]], i64 [[TMP0]], i32 [[TMP1]])
	// CHECK10-NEXT: ret void			// CHECK10-NEXT: ret void
	//			//
	//			//
	// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined.			// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined.
	Show All 18 Lines
	// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8			// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
	// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8			// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
	// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8			// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
	// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8			// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
	// CHECK10-NEXT: [[CONV:%.]] = bitcast i64 [[N_ADDR]] to i32*			// CHECK10-NEXT: [[CONV:%.]] = bitcast i64 [[N_ADDR]] to i32*
	// CHECK10-NEXT: [[TMP0:%.]] = load i64, i64 [[VLA_ADDR]], align 8			// CHECK10-NEXT: [[TMP0:%.]] = load i64, i64 [[VLA_ADDR]], align 8
	// CHECK10-NEXT: [[TMP1:%.]] = load i32, i32** [[A_ADDR]], align 8			// CHECK10-NEXT: [[TMP1:%.]] = load i32, i32** [[A_ADDR]], align 8
	// CHECK10-NEXT: [[TMP2:%.]] = load i32, i32 [[CONV]], align 4			// CHECK10-NEXT: [[TMP2:%.]] = load i32, i32 [[CONV]], align 8
	// CHECK10-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4			// CHECK10-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
	// CHECK10-NEXT: [[TMP3:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4			// CHECK10-NEXT: [[TMP3:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4
	// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0			// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
	// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1			// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
	// CHECK10-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1			// CHECK10-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
	// CHECK10-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4			// CHECK10-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4
	// CHECK10-NEXT: store i32 0, i32* [[I]], align 4			// CHECK10-NEXT: store i32 0, i32* [[I]], align 4
	// CHECK10-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4			// CHECK10-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4
	Show All 29 Lines
	// CHECK10-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !9			// CHECK10-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !9
	// CHECK10-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]			// CHECK10-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
	// CHECK10-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK10-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK10: omp.inner.for.body:			// CHECK10: omp.inner.for.body:
	// CHECK10-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !9			// CHECK10-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !9
	// CHECK10-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64			// CHECK10-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64
	// CHECK10-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !9			// CHECK10-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !9
	// CHECK10-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64			// CHECK10-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
	// CHECK10-NEXT: [[TMP19:%.]] = load i32, i32 [[CONV]], align 4, !llvm.access.group !9			// CHECK10-NEXT: [[TMP19:%.]] = load i32, i32 [[CONV]], align 8, !llvm.access.group !9
	// CHECK10-NEXT: [[CONV6:%.]] = bitcast i64 [[N_CASTED]] to i32*			// CHECK10-NEXT: [[CONV6:%.]] = bitcast i64 [[N_CASTED]] to i32*
	// CHECK10-NEXT: store i32 [[TMP19]], i32* [[CONV6]], align 4, !llvm.access.group !9			// CHECK10-NEXT: store i32 [[TMP19]], i32* [[CONV6]], align 4, !llvm.access.group !9
	// CHECK10-NEXT: [[TMP20:%.]] = load i64, i64 [[N_CASTED]], align 8, !llvm.access.group !9			// CHECK10-NEXT: [[TMP20:%.]] = load i64, i64 [[N_CASTED]], align 8, !llvm.access.group !9
	// CHECK10-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i64, i64, i32) @.omp_outlined..1 to void (i32, i32, ...)), i64 [[TMP16]], i64 [[TMP18]], i64 [[TMP20]], i64 [[TMP0]], i32 [[TMP1]]), !llvm.access.group !9			// CHECK10-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i64, i64, i32) @.omp_outlined..1 to void (i32, i32, ...)), i64 [[TMP16]], i64 [[TMP18]], i64 [[TMP20]], i64 [[TMP0]], i32 [[TMP1]]), !llvm.access.group !9
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK10: omp.inner.for.inc:			// CHECK10: omp.inner.for.inc:
	// CHECK10-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9			// CHECK10-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK10-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !9			// CHECK10-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !9
	▲ Show 20 Lines • Show All 48 Lines • ▼ Show 20 Lines
	// CHECK10-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8			// CHECK10-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
	// CHECK10-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8			// CHECK10-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
	// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8			// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
	// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8			// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
	// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8			// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
	// CHECK10-NEXT: [[CONV:%.]] = bitcast i64 [[N_ADDR]] to i32*			// CHECK10-NEXT: [[CONV:%.]] = bitcast i64 [[N_ADDR]] to i32*
	// CHECK10-NEXT: [[TMP0:%.]] = load i64, i64 [[VLA_ADDR]], align 8			// CHECK10-NEXT: [[TMP0:%.]] = load i64, i64 [[VLA_ADDR]], align 8
	// CHECK10-NEXT: [[TMP1:%.]] = load i32, i32** [[A_ADDR]], align 8			// CHECK10-NEXT: [[TMP1:%.]] = load i32, i32** [[A_ADDR]], align 8
	// CHECK10-NEXT: [[TMP2:%.]] = load i32, i32 [[CONV]], align 4			// CHECK10-NEXT: [[TMP2:%.]] = load i32, i32 [[CONV]], align 8
	// CHECK10-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4			// CHECK10-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
	// CHECK10-NEXT: [[TMP3:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4			// CHECK10-NEXT: [[TMP3:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4
	// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0			// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
	// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1			// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
	// CHECK10-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1			// CHECK10-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
	// CHECK10-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4			// CHECK10-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4
	// CHECK10-NEXT: store i32 0, i32* [[I]], align 4			// CHECK10-NEXT: store i32 0, i32* [[I]], align 4
	// CHECK10-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4			// CHECK10-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4
	▲ Show 20 Lines • Show All 83 Lines • ▼ Show 20 Lines
	// CHECK10-NEXT: [[A_ADDR:%.]] = alloca i32, align 8			// CHECK10-NEXT: [[A_ADDR:%.]] = alloca i32, align 8
	// CHECK10-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8			// CHECK10-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8
	// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8			// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
	// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8			// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
	// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8			// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
	// CHECK10-NEXT: [[CONV:%.]] = bitcast i64 [[N_ADDR]] to i32*			// CHECK10-NEXT: [[CONV:%.]] = bitcast i64 [[N_ADDR]] to i32*
	// CHECK10-NEXT: [[TMP0:%.]] = load i64, i64 [[VLA_ADDR]], align 8			// CHECK10-NEXT: [[TMP0:%.]] = load i64, i64 [[VLA_ADDR]], align 8
	// CHECK10-NEXT: [[TMP1:%.]] = load i32, i32** [[A_ADDR]], align 8			// CHECK10-NEXT: [[TMP1:%.]] = load i32, i32** [[A_ADDR]], align 8
	// CHECK10-NEXT: [[TMP2:%.]] = load i32, i32 [[CONV]], align 4			// CHECK10-NEXT: [[TMP2:%.]] = load i32, i32 [[CONV]], align 8
	// CHECK10-NEXT: [[CONV1:%.]] = bitcast i64 [[N_CASTED]] to i32*			// CHECK10-NEXT: [[CONV1:%.]] = bitcast i64 [[N_CASTED]] to i32*
	// CHECK10-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4			// CHECK10-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4
	// CHECK10-NEXT: [[TMP3:%.]] = load i64, i64 [[N_CASTED]], align 8			// CHECK10-NEXT: [[TMP3:%.]] = load i64, i64 [[N_CASTED]], align 8
	// CHECK10-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i32) @.omp_outlined..2 to void (i32, i32, ...)), i64 [[TMP3]], i64 [[TMP0]], i32 [[TMP1]])			// CHECK10-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i32) @.omp_outlined..2 to void (i32, i32, ...)), i64 [[TMP3]], i64 [[TMP0]], i32 [[TMP1]])
	// CHECK10-NEXT: ret void			// CHECK10-NEXT: ret void
	//			//
	//			//
	// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..2			// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..2
	Show All 18 Lines
	// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8			// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
	// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8			// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
	// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8			// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
	// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8			// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
	// CHECK10-NEXT: [[CONV:%.]] = bitcast i64 [[N_ADDR]] to i32*			// CHECK10-NEXT: [[CONV:%.]] = bitcast i64 [[N_ADDR]] to i32*
	// CHECK10-NEXT: [[TMP0:%.]] = load i64, i64 [[VLA_ADDR]], align 8			// CHECK10-NEXT: [[TMP0:%.]] = load i64, i64 [[VLA_ADDR]], align 8
	// CHECK10-NEXT: [[TMP1:%.]] = load i32, i32** [[A_ADDR]], align 8			// CHECK10-NEXT: [[TMP1:%.]] = load i32, i32** [[A_ADDR]], align 8
	// CHECK10-NEXT: [[TMP2:%.]] = load i32, i32 [[CONV]], align 4			// CHECK10-NEXT: [[TMP2:%.]] = load i32, i32 [[CONV]], align 8
	// CHECK10-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4			// CHECK10-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
	// CHECK10-NEXT: [[TMP3:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4			// CHECK10-NEXT: [[TMP3:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4
	// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0			// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
	// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1			// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
	// CHECK10-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1			// CHECK10-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
	// CHECK10-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4			// CHECK10-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4
	// CHECK10-NEXT: store i32 0, i32* [[I]], align 4			// CHECK10-NEXT: store i32 0, i32* [[I]], align 4
	// CHECK10-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4			// CHECK10-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4
	Show All 29 Lines
	// CHECK10-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !18			// CHECK10-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !18
	// CHECK10-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]			// CHECK10-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
	// CHECK10-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK10-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK10: omp.inner.for.body:			// CHECK10: omp.inner.for.body:
	// CHECK10-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !18			// CHECK10-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !18
	// CHECK10-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64			// CHECK10-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64
	// CHECK10-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !18			// CHECK10-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !18
	// CHECK10-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64			// CHECK10-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
	// CHECK10-NEXT: [[TMP19:%.]] = load i32, i32 [[CONV]], align 4, !llvm.access.group !18			// CHECK10-NEXT: [[TMP19:%.]] = load i32, i32 [[CONV]], align 8, !llvm.access.group !18
	// CHECK10-NEXT: [[CONV6:%.]] = bitcast i64 [[N_CASTED]] to i32*			// CHECK10-NEXT: [[CONV6:%.]] = bitcast i64 [[N_CASTED]] to i32*
	// CHECK10-NEXT: store i32 [[TMP19]], i32* [[CONV6]], align 4, !llvm.access.group !18			// CHECK10-NEXT: store i32 [[TMP19]], i32* [[CONV6]], align 4, !llvm.access.group !18
	// CHECK10-NEXT: [[TMP20:%.]] = load i64, i64 [[N_CASTED]], align 8, !llvm.access.group !18			// CHECK10-NEXT: [[TMP20:%.]] = load i64, i64 [[N_CASTED]], align 8, !llvm.access.group !18
	// CHECK10-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i64, i64, i32) @.omp_outlined..3 to void (i32, i32, ...)), i64 [[TMP16]], i64 [[TMP18]], i64 [[TMP20]], i64 [[TMP0]], i32 [[TMP1]]), !llvm.access.group !18			// CHECK10-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i64, i64, i32) @.omp_outlined..3 to void (i32, i32, ...)), i64 [[TMP16]], i64 [[TMP18]], i64 [[TMP20]], i64 [[TMP0]], i32 [[TMP1]]), !llvm.access.group !18
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK10: omp.inner.for.inc:			// CHECK10: omp.inner.for.inc:
	// CHECK10-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18			// CHECK10-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK10-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !18			// CHECK10-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !18
	▲ Show 20 Lines • Show All 48 Lines • ▼ Show 20 Lines
	// CHECK10-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8			// CHECK10-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
	// CHECK10-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8			// CHECK10-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
	// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8			// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
	// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8			// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
	// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8			// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
	// CHECK10-NEXT: [[CONV:%.]] = bitcast i64 [[N_ADDR]] to i32*			// CHECK10-NEXT: [[CONV:%.]] = bitcast i64 [[N_ADDR]] to i32*
	// CHECK10-NEXT: [[TMP0:%.]] = load i64, i64 [[VLA_ADDR]], align 8			// CHECK10-NEXT: [[TMP0:%.]] = load i64, i64 [[VLA_ADDR]], align 8
	// CHECK10-NEXT: [[TMP1:%.]] = load i32, i32** [[A_ADDR]], align 8			// CHECK10-NEXT: [[TMP1:%.]] = load i32, i32** [[A_ADDR]], align 8
	// CHECK10-NEXT: [[TMP2:%.]] = load i32, i32 [[CONV]], align 4			// CHECK10-NEXT: [[TMP2:%.]] = load i32, i32 [[CONV]], align 8
	// CHECK10-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4			// CHECK10-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
	// CHECK10-NEXT: [[TMP3:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4			// CHECK10-NEXT: [[TMP3:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4
	// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0			// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
	// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1			// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
	// CHECK10-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1			// CHECK10-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
	// CHECK10-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4			// CHECK10-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4
	// CHECK10-NEXT: store i32 0, i32* [[I]], align 4			// CHECK10-NEXT: store i32 0, i32* [[I]], align 4
	// CHECK10-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4			// CHECK10-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4
	▲ Show 20 Lines • Show All 87 Lines • ▼ Show 20 Lines
	// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8			// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
	// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8			// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
	// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8			// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
	// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8			// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
	// CHECK10-NEXT: [[CONV:%.]] = bitcast i64 [[N_ADDR]] to i32*			// CHECK10-NEXT: [[CONV:%.]] = bitcast i64 [[N_ADDR]] to i32*
	// CHECK10-NEXT: [[TMP0:%.]] = load i64, i64 [[VLA_ADDR]], align 8			// CHECK10-NEXT: [[TMP0:%.]] = load i64, i64 [[VLA_ADDR]], align 8
	// CHECK10-NEXT: [[TMP1:%.]] = load i32, i32** [[A_ADDR]], align 8			// CHECK10-NEXT: [[TMP1:%.]] = load i32, i32** [[A_ADDR]], align 8
	// CHECK10-NEXT: [[CONV1:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__ADDR]] to i32*			// CHECK10-NEXT: [[CONV1:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__ADDR]] to i32*
	// CHECK10-NEXT: [[TMP2:%.]] = load i32, i32 [[CONV]], align 4			// CHECK10-NEXT: [[TMP2:%.]] = load i32, i32 [[CONV]], align 8
	// CHECK10-NEXT: [[CONV2:%.]] = bitcast i64 [[N_CASTED]] to i32*			// CHECK10-NEXT: [[CONV2:%.]] = bitcast i64 [[N_CASTED]] to i32*
	// CHECK10-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4			// CHECK10-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4
	// CHECK10-NEXT: [[TMP3:%.]] = load i64, i64 [[N_CASTED]], align 8			// CHECK10-NEXT: [[TMP3:%.]] = load i64, i64 [[N_CASTED]], align 8
	// CHECK10-NEXT: [[TMP4:%.]] = load i32, i32 [[CONV1]], align 4			// CHECK10-NEXT: [[TMP4:%.]] = load i32, i32 [[CONV1]], align 8
	// CHECK10-NEXT: [[CONV3:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED]] to i32*			// CHECK10-NEXT: [[CONV3:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED]] to i32*
	// CHECK10-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4			// CHECK10-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
	// CHECK10-NEXT: [[TMP5:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED]], align 8			// CHECK10-NEXT: [[TMP5:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED]], align 8
	// CHECK10-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i32, i64) @.omp_outlined..5 to void (i32, i32, ...)), i64 [[TMP3]], i64 [[TMP0]], i32 [[TMP1]], i64 [[TMP5]])			// CHECK10-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i32, i64) @.omp_outlined..5 to void (i32, i32, ...)), i64 [[TMP3]], i64 [[TMP0]], i32 [[TMP1]], i64 [[TMP5]])
	// CHECK10-NEXT: ret void			// CHECK10-NEXT: ret void
	//			//
	//			//
	// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..5			// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..5
	Show All 22 Lines
	// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8			// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
	// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8			// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
	// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8			// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
	// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8			// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
	// CHECK10-NEXT: [[CONV:%.]] = bitcast i64 [[N_ADDR]] to i32*			// CHECK10-NEXT: [[CONV:%.]] = bitcast i64 [[N_ADDR]] to i32*
	// CHECK10-NEXT: [[TMP0:%.]] = load i64, i64 [[VLA_ADDR]], align 8			// CHECK10-NEXT: [[TMP0:%.]] = load i64, i64 [[VLA_ADDR]], align 8
	// CHECK10-NEXT: [[TMP1:%.]] = load i32, i32** [[A_ADDR]], align 8			// CHECK10-NEXT: [[TMP1:%.]] = load i32, i32** [[A_ADDR]], align 8
	// CHECK10-NEXT: [[CONV1:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__ADDR]] to i32*			// CHECK10-NEXT: [[CONV1:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__ADDR]] to i32*
	// CHECK10-NEXT: [[TMP2:%.]] = load i32, i32 [[CONV]], align 4			// CHECK10-NEXT: [[TMP2:%.]] = load i32, i32 [[CONV]], align 8
	// CHECK10-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4			// CHECK10-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4
	// CHECK10-NEXT: [[TMP3:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2]], align 4			// CHECK10-NEXT: [[TMP3:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2]], align 4
	// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0			// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
	// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1			// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
	// CHECK10-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1			// CHECK10-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1
	// CHECK10-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_3]], align 4			// CHECK10-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_3]], align 4
	// CHECK10-NEXT: store i32 0, i32* [[I]], align 4			// CHECK10-NEXT: store i32 0, i32* [[I]], align 4
	// CHECK10-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2]], align 4			// CHECK10-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2]], align 4
	// CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]]			// CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]]
	// CHECK10-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.]], label [[OMP_PRECOND_END:%.]]			// CHECK10-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.]], label [[OMP_PRECOND_END:%.]]
	// CHECK10: omp.precond.then:			// CHECK10: omp.precond.then:
	// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4			// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
	// CHECK10-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_3]], align 4			// CHECK10-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_3]], align 4
	// CHECK10-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK10-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4			// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
	// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4			// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
	// CHECK10-NEXT: [[TMP6:%.]] = load i32, i32 [[CONV1]], align 4			// CHECK10-NEXT: [[TMP6:%.]] = load i32, i32 [[CONV1]], align 8
	// CHECK10-NEXT: [[TMP7:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK10-NEXT: [[TMP7:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK10-NEXT: [[TMP8:%.]] = load i32, i32 [[TMP7]], align 4			// CHECK10-NEXT: [[TMP8:%.]] = load i32, i32 [[TMP7]], align 4
	// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP6]])			// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP6]])
	// CHECK10-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK10-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4
	// CHECK10-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_3]], align 4			// CHECK10-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_3]], align 4
	// CHECK10-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]]			// CHECK10-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]]
	// CHECK10-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.]], label [[COND_FALSE:%.]]			// CHECK10-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.]], label [[COND_FALSE:%.]]
	// CHECK10: cond.true:			// CHECK10: cond.true:
	Show All 14 Lines
	// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP15]], 1			// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP15]], 1
	// CHECK10-NEXT: [[CMP7:%.*]] = icmp slt i32 [[TMP14]], [[ADD]]			// CHECK10-NEXT: [[CMP7:%.*]] = icmp slt i32 [[TMP14]], [[ADD]]
	// CHECK10-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK10-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK10: omp.inner.for.body:			// CHECK10: omp.inner.for.body:
	// CHECK10-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !24			// CHECK10-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !24
	// CHECK10-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64			// CHECK10-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
	// CHECK10-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !24			// CHECK10-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !24
	// CHECK10-NEXT: [[TMP19:%.*]] = zext i32 [[TMP18]] to i64			// CHECK10-NEXT: [[TMP19:%.*]] = zext i32 [[TMP18]] to i64
	// CHECK10-NEXT: [[TMP20:%.]] = load i32, i32 [[CONV]], align 4, !llvm.access.group !24			// CHECK10-NEXT: [[TMP20:%.]] = load i32, i32 [[CONV]], align 8, !llvm.access.group !24
	// CHECK10-NEXT: [[CONV8:%.]] = bitcast i64 [[N_CASTED]] to i32*			// CHECK10-NEXT: [[CONV8:%.]] = bitcast i64 [[N_CASTED]] to i32*
	// CHECK10-NEXT: store i32 [[TMP20]], i32* [[CONV8]], align 4, !llvm.access.group !24			// CHECK10-NEXT: store i32 [[TMP20]], i32* [[CONV8]], align 4, !llvm.access.group !24
	// CHECK10-NEXT: [[TMP21:%.]] = load i64, i64 [[N_CASTED]], align 8, !llvm.access.group !24			// CHECK10-NEXT: [[TMP21:%.]] = load i64, i64 [[N_CASTED]], align 8, !llvm.access.group !24
	// CHECK10-NEXT: [[TMP22:%.]] = load i32, i32 [[CONV1]], align 4, !llvm.access.group !24			// CHECK10-NEXT: [[TMP22:%.]] = load i32, i32 [[CONV1]], align 8, !llvm.access.group !24
	// CHECK10-NEXT: [[CONV9:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED]] to i32*			// CHECK10-NEXT: [[CONV9:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED]] to i32*
	// CHECK10-NEXT: store i32 [[TMP22]], i32* [[CONV9]], align 4, !llvm.access.group !24			// CHECK10-NEXT: store i32 [[TMP22]], i32* [[CONV9]], align 4, !llvm.access.group !24
	// CHECK10-NEXT: [[TMP23:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !24			// CHECK10-NEXT: [[TMP23:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !24
	// CHECK10-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i64, i64, i32, i64) @.omp_outlined..6 to void (i32, i32, ...)), i64 [[TMP17]], i64 [[TMP19]], i64 [[TMP21]], i64 [[TMP0]], i32 [[TMP1]], i64 [[TMP23]]), !llvm.access.group !24			// CHECK10-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i64, i64, i32, i64) @.omp_outlined..6 to void (i32, i32, ...)), i64 [[TMP17]], i64 [[TMP19]], i64 [[TMP21]], i64 [[TMP0]], i32 [[TMP1]], i64 [[TMP23]]), !llvm.access.group !24
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK10: omp.inner.for.inc:			// CHECK10: omp.inner.for.inc:
	// CHECK10-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !24			// CHECK10-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !24
	// CHECK10-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !24			// CHECK10-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !24
	▲ Show 20 Lines • Show All 74 Lines • ▼ Show 20 Lines
	// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8			// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
	// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8			// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
	// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8			// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
	// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8			// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
	// CHECK10-NEXT: [[CONV:%.]] = bitcast i64 [[N_ADDR]] to i32*			// CHECK10-NEXT: [[CONV:%.]] = bitcast i64 [[N_ADDR]] to i32*
	// CHECK10-NEXT: [[TMP0:%.]] = load i64, i64 [[VLA_ADDR]], align 8			// CHECK10-NEXT: [[TMP0:%.]] = load i64, i64 [[VLA_ADDR]], align 8
	// CHECK10-NEXT: [[TMP1:%.]] = load i32, i32** [[A_ADDR]], align 8			// CHECK10-NEXT: [[TMP1:%.]] = load i32, i32** [[A_ADDR]], align 8
	// CHECK10-NEXT: [[CONV1:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__ADDR]] to i32*			// CHECK10-NEXT: [[CONV1:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__ADDR]] to i32*
	// CHECK10-NEXT: [[TMP2:%.]] = load i32, i32 [[CONV]], align 4			// CHECK10-NEXT: [[TMP2:%.]] = load i32, i32 [[CONV]], align 8
	// CHECK10-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4			// CHECK10-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4
	// CHECK10-NEXT: [[TMP3:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2]], align 4			// CHECK10-NEXT: [[TMP3:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2]], align 4
	// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0			// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
	// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1			// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
	// CHECK10-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1			// CHECK10-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1
	// CHECK10-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_3]], align 4			// CHECK10-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_3]], align 4
	// CHECK10-NEXT: store i32 0, i32* [[I]], align 4			// CHECK10-NEXT: store i32 0, i32* [[I]], align 4
	// CHECK10-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2]], align 4			// CHECK10-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2]], align 4
	▲ Show 20 Lines • Show All 501 Lines • ▼ Show 20 Lines
	// CHECK10-NEXT: entry:			// CHECK10-NEXT: entry:
	// CHECK10-NEXT: [[A_ADDR:%.]] = alloca [10 x i32], align 8			// CHECK10-NEXT: [[A_ADDR:%.]] = alloca [10 x i32], align 8
	// CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8			// CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
	// CHECK10-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8			// CHECK10-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
	// CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8			// CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8
	// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8			// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
	// CHECK10-NEXT: [[TMP0:%.]] = load [10 x i32], [10 x i32]** [[A_ADDR]], align 8			// CHECK10-NEXT: [[TMP0:%.]] = load [10 x i32], [10 x i32]** [[A_ADDR]], align 8
	// CHECK10-NEXT: [[CONV:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__ADDR]] to i32*			// CHECK10-NEXT: [[CONV:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__ADDR]] to i32*
	// CHECK10-NEXT: [[TMP1:%.]] = load i32, i32 [[CONV]], align 4			// CHECK10-NEXT: [[TMP1:%.]] = load i32, i32 [[CONV]], align 8
	// CHECK10-NEXT: [[CONV1:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED]] to i32*			// CHECK10-NEXT: [[CONV1:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED]] to i32*
	// CHECK10-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4			// CHECK10-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4
	// CHECK10-NEXT: [[TMP2:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED]], align 8			// CHECK10-NEXT: [[TMP2:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED]], align 8
	// CHECK10-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, [10 x i32], i64) @.omp_outlined..15 to void (i32, i32, ...)), [10 x i32] [[TMP0]], i64 [[TMP2]])			// CHECK10-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, [10 x i32], i64) @.omp_outlined..15 to void (i32, i32, ...)), [10 x i32] [[TMP0]], i64 [[TMP2]])
	// CHECK10-NEXT: ret void			// CHECK10-NEXT: ret void
	//			//
	//			//
	// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..15			// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..15
	Show All 16 Lines
	// CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8			// CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8
	// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8			// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
	// CHECK10-NEXT: [[TMP0:%.]] = load [10 x i32], [10 x i32]** [[A_ADDR]], align 8			// CHECK10-NEXT: [[TMP0:%.]] = load [10 x i32], [10 x i32]** [[A_ADDR]], align 8
	// CHECK10-NEXT: [[CONV:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__ADDR]] to i32*			// CHECK10-NEXT: [[CONV:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__ADDR]] to i32*
	// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4			// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
	// CHECK10-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4			// CHECK10-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4			// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
	// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4			// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
	// CHECK10-NEXT: [[TMP1:%.]] = load i32, i32 [[CONV]], align 4			// CHECK10-NEXT: [[TMP1:%.]] = load i32, i32 [[CONV]], align 8
	// CHECK10-NEXT: [[TMP2:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK10-NEXT: [[TMP2:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK10-NEXT: [[TMP3:%.]] = load i32, i32 [[TMP2]], align 4			// CHECK10-NEXT: [[TMP3:%.]] = load i32, i32 [[TMP2]], align 4
	// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP1]])			// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP1]])
	// CHECK10-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK10-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4
	// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 9			// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 9
	// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.]], label [[COND_FALSE:%.]]			// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.]], label [[COND_FALSE:%.]]
	// CHECK10: cond.true:			// CHECK10: cond.true:
	// CHECK10-NEXT: br label [[COND_END:%.*]]			// CHECK10-NEXT: br label [[COND_END:%.*]]
	Show All 10 Lines
	// CHECK10-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !42			// CHECK10-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !42
	// CHECK10-NEXT: [[CMP1:%.*]] = icmp slt i32 [[TMP7]], 10			// CHECK10-NEXT: [[CMP1:%.*]] = icmp slt i32 [[TMP7]], 10
	// CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK10: omp.inner.for.body:			// CHECK10: omp.inner.for.body:
	// CHECK10-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !42			// CHECK10-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !42
	// CHECK10-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64			// CHECK10-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
	// CHECK10-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !42			// CHECK10-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !42
	// CHECK10-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64			// CHECK10-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
	// CHECK10-NEXT: [[TMP12:%.]] = load i32, i32 [[CONV]], align 4, !llvm.access.group !42			// CHECK10-NEXT: [[TMP12:%.]] = load i32, i32 [[CONV]], align 8, !llvm.access.group !42
	// CHECK10-NEXT: [[CONV2:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED]] to i32*			// CHECK10-NEXT: [[CONV2:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED]] to i32*
	// CHECK10-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4, !llvm.access.group !42			// CHECK10-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4, !llvm.access.group !42
	// CHECK10-NEXT: [[TMP13:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !42			// CHECK10-NEXT: [[TMP13:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !42
	// CHECK10-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, [10 x i32], i64) @.omp_outlined..16 to void (i32, i32, ...)), i64 [[TMP9]], i64 [[TMP11]], [10 x i32] [[TMP0]], i64 [[TMP13]]), !llvm.access.group !42			// CHECK10-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, [10 x i32], i64) @.omp_outlined..16 to void (i32, i32, ...)), i64 [[TMP9]], i64 [[TMP11]], [10 x i32] [[TMP0]], i64 [[TMP13]]), !llvm.access.group !42
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK10: omp.inner.for.inc:			// CHECK10: omp.inner.for.inc:
	// CHECK10-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !42			// CHECK10-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !42
	// CHECK10-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !42			// CHECK10-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !42
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clang/test/OpenMP/target_teams_distribute_parallel_for_simd_firstprivate_codegen.cpp

This file is larger than 256 KB, so syntax highlighting is disabled by default.

	Show First 20 Lines • Show All 398 Lines • ▼ Show 20 Lines
	// CHECK1-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8			// CHECK1-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8
	// CHECK1-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8			// CHECK1-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8
	// CHECK1-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8			// CHECK1-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8
	// CHECK1-NEXT: [[TMP0:%.]] = load [2 x i32], [2 x i32]** [[VEC_ADDR]], align 8			// CHECK1-NEXT: [[TMP0:%.]] = load [2 x i32], [2 x i32]** [[VEC_ADDR]], align 8
	// CHECK1-NEXT: [[CONV:%.]] = bitcast i64 [[T_VAR_ADDR]] to i32*			// CHECK1-NEXT: [[CONV:%.]] = bitcast i64 [[T_VAR_ADDR]] to i32*
	// CHECK1-NEXT: [[TMP1:%.]] = load [2 x %struct.S], [2 x %struct.S]** [[S_ARR_ADDR]], align 8			// CHECK1-NEXT: [[TMP1:%.]] = load [2 x %struct.S], [2 x %struct.S]** [[S_ARR_ADDR]], align 8
	// CHECK1-NEXT: [[TMP2:%.]] = load %struct.S, %struct.S** [[VAR_ADDR]], align 8			// CHECK1-NEXT: [[TMP2:%.]] = load %struct.S, %struct.S** [[VAR_ADDR]], align 8
	// CHECK1-NEXT: [[CONV1:%.]] = bitcast i64 [[SIVAR_ADDR]] to i32*			// CHECK1-NEXT: [[CONV1:%.]] = bitcast i64 [[SIVAR_ADDR]] to i32*
	// CHECK1-NEXT: [[TMP3:%.]] = load i32, i32 [[CONV]], align 4			// CHECK1-NEXT: [[TMP3:%.]] = load i32, i32 [[CONV]], align 8
	// CHECK1-NEXT: [[CONV2:%.]] = bitcast i64 [[T_VAR_CASTED]] to i32*			// CHECK1-NEXT: [[CONV2:%.]] = bitcast i64 [[T_VAR_CASTED]] to i32*
	// CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4			// CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
	// CHECK1-NEXT: [[TMP4:%.]] = load i64, i64 [[T_VAR_CASTED]], align 8			// CHECK1-NEXT: [[TMP4:%.]] = load i64, i64 [[T_VAR_CASTED]], align 8
	// CHECK1-NEXT: [[TMP5:%.]] = load i32, i32 [[CONV1]], align 4			// CHECK1-NEXT: [[TMP5:%.]] = load i32, i32 [[CONV1]], align 8
	// CHECK1-NEXT: [[CONV3:%.]] = bitcast i64 [[SIVAR_CASTED]] to i32*			// CHECK1-NEXT: [[CONV3:%.]] = bitcast i64 [[SIVAR_CASTED]] to i32*
	// CHECK1-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4			// CHECK1-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4
	// CHECK1-NEXT: [[TMP6:%.]] = load i64, i64 [[SIVAR_CASTED]], align 8			// CHECK1-NEXT: [[TMP6:%.]] = load i64, i64 [[SIVAR_CASTED]], align 8
	// CHECK1-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32, i32, ...)* bitcast (void (i32, i32, [2 x i32], i64, [2 x %struct.S], %struct.S, i64) @.omp_outlined. to void (i32, i32, ...)), [2 x i32] [[TMP0]], i64 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP2]], i64 [[TMP6]])			// CHECK1-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32, i32, ...)* bitcast (void (i32, i32, [2 x i32], i64, [2 x %struct.S], %struct.S, i64) @.omp_outlined. to void (i32, i32, ...)), [2 x i32] [[TMP0]], i64 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP2]], i64 [[TMP6]])
	// CHECK1-NEXT: ret void			// CHECK1-NEXT: ret void
	//			//
	//			//
	// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined.			// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined.
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	// CHECK1-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]			// CHECK1-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]
	// CHECK1: omp.inner.for.cond.cleanup:			// CHECK1: omp.inner.for.cond.cleanup:
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
	// CHECK1: omp.inner.for.body:			// CHECK1: omp.inner.for.body:
	// CHECK1-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !5			// CHECK1-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !5
	// CHECK1-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64			// CHECK1-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64
	// CHECK1-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5			// CHECK1-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5
	// CHECK1-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64			// CHECK1-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
	// CHECK1-NEXT: [[TMP18:%.]] = load i32, i32 [[CONV]], align 4, !llvm.access.group !5			// CHECK1-NEXT: [[TMP18:%.]] = load i32, i32 [[CONV]], align 8, !llvm.access.group !5
	// CHECK1-NEXT: [[CONV8:%.]] = bitcast i64 [[T_VAR_CASTED]] to i32*			// CHECK1-NEXT: [[CONV8:%.]] = bitcast i64 [[T_VAR_CASTED]] to i32*
	// CHECK1-NEXT: store i32 [[TMP18]], i32* [[CONV8]], align 4, !llvm.access.group !5			// CHECK1-NEXT: store i32 [[TMP18]], i32* [[CONV8]], align 4, !llvm.access.group !5
	// CHECK1-NEXT: [[TMP19:%.]] = load i64, i64 [[T_VAR_CASTED]], align 8, !llvm.access.group !5			// CHECK1-NEXT: [[TMP19:%.]] = load i64, i64 [[T_VAR_CASTED]], align 8, !llvm.access.group !5
	// CHECK1-NEXT: [[TMP20:%.]] = load i32, i32 [[CONV1]], align 4, !llvm.access.group !5			// CHECK1-NEXT: [[TMP20:%.]] = load i32, i32 [[CONV1]], align 8, !llvm.access.group !5
	// CHECK1-NEXT: [[CONV9:%.]] = bitcast i64 [[SIVAR_CASTED]] to i32*			// CHECK1-NEXT: [[CONV9:%.]] = bitcast i64 [[SIVAR_CASTED]] to i32*
	// CHECK1-NEXT: store i32 [[TMP20]], i32* [[CONV9]], align 4, !llvm.access.group !5			// CHECK1-NEXT: store i32 [[TMP20]], i32* [[CONV9]], align 4, !llvm.access.group !5
	// CHECK1-NEXT: [[TMP21:%.]] = load i64, i64 [[SIVAR_CASTED]], align 8, !llvm.access.group !5			// CHECK1-NEXT: [[TMP21:%.]] = load i64, i64 [[SIVAR_CASTED]], align 8, !llvm.access.group !5
	// CHECK1-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, [2 x i32], i64, [2 x %struct.S], %struct.S, i64) @.omp_outlined..3 to void (i32, i32, ...)), i64 [[TMP15]], i64 [[TMP17]], [2 x i32] [[VEC2]], i64 [[TMP19]], [2 x %struct.S]* [[S_ARR3]], %struct.S* [[VAR5]], i64 [[TMP21]]), !llvm.access.group !5			// CHECK1-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, [2 x i32], i64, [2 x %struct.S], %struct.S, i64) @.omp_outlined..3 to void (i32, i32, ...)), i64 [[TMP15]], i64 [[TMP17]], [2 x i32] [[VEC2]], i64 [[TMP19]], [2 x %struct.S]* [[S_ARR3]], %struct.S* [[VAR5]], i64 [[TMP21]]), !llvm.access.group !5
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK1: omp.inner.for.inc:			// CHECK1: omp.inner.for.inc:
	// CHECK1-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5			// CHECK1-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK1-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !5			// CHECK1-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !5
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	// CHECK1-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]			// CHECK1-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]
	// CHECK1: omp.inner.for.cond.cleanup:			// CHECK1: omp.inner.for.cond.cleanup:
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
	// CHECK1: omp.inner.for.body:			// CHECK1: omp.inner.for.body:
	// CHECK1-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9			// CHECK1-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1			// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1
	// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9			// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9
	// CHECK1-NEXT: [[TMP17:%.]] = load i32, i32 [[CONV]], align 4, !llvm.access.group !9			// CHECK1-NEXT: [[TMP17:%.]] = load i32, i32 [[CONV]], align 8, !llvm.access.group !9
	// CHECK1-NEXT: [[TMP18:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !9			// CHECK1-NEXT: [[TMP18:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !9
	// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP18]] to i64			// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP18]] to i64
	// CHECK1-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC4]], i64 0, i64 [[IDXPROM]]			// CHECK1-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC4]], i64 0, i64 [[IDXPROM]]
	// CHECK1-NEXT: store i32 [[TMP17]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !9			// CHECK1-NEXT: store i32 [[TMP17]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !9
	// CHECK1-NEXT: [[TMP19:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !9			// CHECK1-NEXT: [[TMP19:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !9
	// CHECK1-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP19]] to i64			// CHECK1-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP19]] to i64
	// CHECK1-NEXT: [[ARRAYIDX11:%.]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S] [[S_ARR5]], i64 0, i64 [[IDXPROM10]]			// CHECK1-NEXT: [[ARRAYIDX11:%.]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S] [[S_ARR5]], i64 0, i64 [[IDXPROM10]]
	// CHECK1-NEXT: [[TMP20:%.]] = bitcast %struct.S [[ARRAYIDX11]] to i8*			// CHECK1-NEXT: [[TMP20:%.]] = bitcast %struct.S [[ARRAYIDX11]] to i8*
	// CHECK1-NEXT: [[TMP21:%.]] = bitcast %struct.S [[VAR7]] to i8*			// CHECK1-NEXT: [[TMP21:%.]] = bitcast %struct.S [[VAR7]] to i8*
	// CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i64 4, i1 false), !llvm.access.group !9			// CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i64 4, i1 false), !llvm.access.group !9
	// CHECK1-NEXT: [[TMP22:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !9			// CHECK1-NEXT: [[TMP22:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !9
	// CHECK1-NEXT: [[TMP23:%.]] = load i32, i32 [[CONV1]], align 4, !llvm.access.group !9			// CHECK1-NEXT: [[TMP23:%.]] = load i32, i32 [[CONV1]], align 8, !llvm.access.group !9
	// CHECK1-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP23]], [[TMP22]]			// CHECK1-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP23]], [[TMP22]]
	// CHECK1-NEXT: store i32 [[ADD12]], i32* [[CONV1]], align 4, !llvm.access.group !9			// CHECK1-NEXT: store i32 [[ADD12]], i32* [[CONV1]], align 8, !llvm.access.group !9
	// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK1: omp.body.continue:			// CHECK1: omp.body.continue:
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK1: omp.inner.for.inc:			// CHECK1: omp.inner.for.inc:
	// CHECK1-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9			// CHECK1-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK1-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP24]], 1			// CHECK1-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP24]], 1
	// CHECK1-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9			// CHECK1-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]
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	// CHECK1-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8			// CHECK1-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8
	// CHECK1-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8			// CHECK1-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
	// CHECK1-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8			// CHECK1-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8
	// CHECK1-NEXT: [[TMP0:%.]] = load [2 x i32], [2 x i32]** [[VEC_ADDR]], align 8			// CHECK1-NEXT: [[TMP0:%.]] = load [2 x i32], [2 x i32]** [[VEC_ADDR]], align 8
	// CHECK1-NEXT: [[CONV:%.]] = bitcast i64 [[T_VAR_ADDR]] to i32*			// CHECK1-NEXT: [[CONV:%.]] = bitcast i64 [[T_VAR_ADDR]] to i32*
	// CHECK1-NEXT: [[TMP1:%.]] = load [2 x %struct.S.0], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8			// CHECK1-NEXT: [[TMP1:%.]] = load [2 x %struct.S.0], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
	// CHECK1-NEXT: [[TMP2:%.]] = load %struct.S.0, %struct.S.0** [[VAR_ADDR]], align 8			// CHECK1-NEXT: [[TMP2:%.]] = load %struct.S.0, %struct.S.0** [[VAR_ADDR]], align 8
	// CHECK1-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8			// CHECK1-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8
	// CHECK1-NEXT: [[TMP3:%.]] = load i32, i32 [[CONV]], align 4			// CHECK1-NEXT: [[TMP3:%.]] = load i32, i32 [[CONV]], align 8
	// CHECK1-NEXT: [[CONV1:%.]] = bitcast i64 [[T_VAR_CASTED]] to i32*			// CHECK1-NEXT: [[CONV1:%.]] = bitcast i64 [[T_VAR_CASTED]] to i32*
	// CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4			// CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4
	// CHECK1-NEXT: [[TMP4:%.]] = load i64, i64 [[T_VAR_CASTED]], align 8			// CHECK1-NEXT: [[TMP4:%.]] = load i64, i64 [[T_VAR_CASTED]], align 8
	// CHECK1-NEXT: [[TMP5:%.]] = load %struct.S.0, %struct.S.0** [[TMP]], align 8			// CHECK1-NEXT: [[TMP5:%.]] = load %struct.S.0, %struct.S.0** [[TMP]], align 8
	// CHECK1-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32, i32, ...)* bitcast (void (i32, i32, [2 x i32], i64, [2 x %struct.S.0], %struct.S.0) @.omp_outlined..4 to void (i32, i32, ...)), [2 x i32] [[TMP0]], i64 [[TMP4]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP5]])			// CHECK1-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32, i32, ...)* bitcast (void (i32, i32, [2 x i32], i64, [2 x %struct.S.0], %struct.S.0) @.omp_outlined..4 to void (i32, i32, ...)), [2 x i32] [[TMP0]], i64 [[TMP4]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP5]])
	// CHECK1-NEXT: ret void			// CHECK1-NEXT: ret void
	//			//
	//			//
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	// CHECK1-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]			// CHECK1-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]
	// CHECK1: omp.inner.for.cond.cleanup:			// CHECK1: omp.inner.for.cond.cleanup:
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
	// CHECK1: omp.inner.for.body:			// CHECK1: omp.inner.for.body:
	// CHECK1-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !14			// CHECK1-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !14
	// CHECK1-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64			// CHECK1-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64
	// CHECK1-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !14			// CHECK1-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !14
	// CHECK1-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64			// CHECK1-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
	// CHECK1-NEXT: [[TMP19:%.]] = load i32, i32 [[CONV]], align 4, !llvm.access.group !14			// CHECK1-NEXT: [[TMP19:%.]] = load i32, i32 [[CONV]], align 8, !llvm.access.group !14
	// CHECK1-NEXT: [[CONV9:%.]] = bitcast i64 [[T_VAR_CASTED]] to i32*			// CHECK1-NEXT: [[CONV9:%.]] = bitcast i64 [[T_VAR_CASTED]] to i32*
	// CHECK1-NEXT: store i32 [[TMP19]], i32* [[CONV9]], align 4, !llvm.access.group !14			// CHECK1-NEXT: store i32 [[TMP19]], i32* [[CONV9]], align 4, !llvm.access.group !14
	// CHECK1-NEXT: [[TMP20:%.]] = load i64, i64 [[T_VAR_CASTED]], align 8, !llvm.access.group !14			// CHECK1-NEXT: [[TMP20:%.]] = load i64, i64 [[T_VAR_CASTED]], align 8, !llvm.access.group !14
	// CHECK1-NEXT: [[TMP21:%.]] = load %struct.S.0, %struct.S.0** [[_TMP7]], align 8, !llvm.access.group !14			// CHECK1-NEXT: [[TMP21:%.]] = load %struct.S.0, %struct.S.0** [[_TMP7]], align 8, !llvm.access.group !14
	// CHECK1-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, [2 x i32], i64, [2 x %struct.S.0], %struct.S.0) @.omp_outlined..5 to void (i32, i32, ...)), i64 [[TMP16]], i64 [[TMP18]], [2 x i32] [[VEC2]], i64 [[TMP20]], [2 x %struct.S.0]* [[S_ARR3]], %struct.S.0* [[TMP21]]), !llvm.access.group !14			// CHECK1-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, [2 x i32], i64, [2 x %struct.S.0], %struct.S.0) @.omp_outlined..5 to void (i32, i32, ...)), i64 [[TMP16]], i64 [[TMP18]], [2 x i32] [[VEC2]], i64 [[TMP20]], [2 x %struct.S.0]* [[S_ARR3]], %struct.S.0* [[TMP21]]), !llvm.access.group !14
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK1: omp.inner.for.inc:			// CHECK1: omp.inner.for.inc:
	// CHECK1-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14			// CHECK1-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14
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	// CHECK1-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]			// CHECK1-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]
	// CHECK1: omp.inner.for.cond.cleanup:			// CHECK1: omp.inner.for.cond.cleanup:
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
	// CHECK1: omp.inner.for.body:			// CHECK1: omp.inner.for.body:
	// CHECK1-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !17			// CHECK1-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !17
	// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1			// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1
	// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !17			// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !17
	// CHECK1-NEXT: [[TMP18:%.]] = load i32, i32 [[CONV]], align 4, !llvm.access.group !17			// CHECK1-NEXT: [[TMP18:%.]] = load i32, i32 [[CONV]], align 8, !llvm.access.group !17
	// CHECK1-NEXT: [[TMP19:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !17			// CHECK1-NEXT: [[TMP19:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !17
	// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64			// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64
	// CHECK1-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC4]], i64 0, i64 [[IDXPROM]]			// CHECK1-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC4]], i64 0, i64 [[IDXPROM]]
	// CHECK1-NEXT: store i32 [[TMP18]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !17			// CHECK1-NEXT: store i32 [[TMP18]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !17
	// CHECK1-NEXT: [[TMP20:%.]] = load %struct.S.0, %struct.S.0** [[_TMP9]], align 8, !llvm.access.group !17			// CHECK1-NEXT: [[TMP20:%.]] = load %struct.S.0, %struct.S.0** [[_TMP9]], align 8, !llvm.access.group !17
	// CHECK1-NEXT: [[TMP21:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !17			// CHECK1-NEXT: [[TMP21:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !17
	// CHECK1-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP21]] to i64			// CHECK1-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP21]] to i64
	// CHECK1-NEXT: [[ARRAYIDX12:%.]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0] [[S_ARR5]], i64 0, i64 [[IDXPROM11]]			// CHECK1-NEXT: [[ARRAYIDX12:%.]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0] [[S_ARR5]], i64 0, i64 [[IDXPROM11]]
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	// CHECK2-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8			// CHECK2-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8
	// CHECK2-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8			// CHECK2-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8
	// CHECK2-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8			// CHECK2-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8
	// CHECK2-NEXT: [[TMP0:%.]] = load [2 x i32], [2 x i32]** [[VEC_ADDR]], align 8			// CHECK2-NEXT: [[TMP0:%.]] = load [2 x i32], [2 x i32]** [[VEC_ADDR]], align 8
	// CHECK2-NEXT: [[CONV:%.]] = bitcast i64 [[T_VAR_ADDR]] to i32*			// CHECK2-NEXT: [[CONV:%.]] = bitcast i64 [[T_VAR_ADDR]] to i32*
	// CHECK2-NEXT: [[TMP1:%.]] = load [2 x %struct.S], [2 x %struct.S]** [[S_ARR_ADDR]], align 8			// CHECK2-NEXT: [[TMP1:%.]] = load [2 x %struct.S], [2 x %struct.S]** [[S_ARR_ADDR]], align 8
	// CHECK2-NEXT: [[TMP2:%.]] = load %struct.S, %struct.S** [[VAR_ADDR]], align 8			// CHECK2-NEXT: [[TMP2:%.]] = load %struct.S, %struct.S** [[VAR_ADDR]], align 8
	// CHECK2-NEXT: [[CONV1:%.]] = bitcast i64 [[SIVAR_ADDR]] to i32*			// CHECK2-NEXT: [[CONV1:%.]] = bitcast i64 [[SIVAR_ADDR]] to i32*
	// CHECK2-NEXT: [[TMP3:%.]] = load i32, i32 [[CONV]], align 4			// CHECK2-NEXT: [[TMP3:%.]] = load i32, i32 [[CONV]], align 8
	// CHECK2-NEXT: [[CONV2:%.]] = bitcast i64 [[T_VAR_CASTED]] to i32*			// CHECK2-NEXT: [[CONV2:%.]] = bitcast i64 [[T_VAR_CASTED]] to i32*
	// CHECK2-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4			// CHECK2-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
	// CHECK2-NEXT: [[TMP4:%.]] = load i64, i64 [[T_VAR_CASTED]], align 8			// CHECK2-NEXT: [[TMP4:%.]] = load i64, i64 [[T_VAR_CASTED]], align 8
	// CHECK2-NEXT: [[TMP5:%.]] = load i32, i32 [[CONV1]], align 4			// CHECK2-NEXT: [[TMP5:%.]] = load i32, i32 [[CONV1]], align 8
	// CHECK2-NEXT: [[CONV3:%.]] = bitcast i64 [[SIVAR_CASTED]] to i32*			// CHECK2-NEXT: [[CONV3:%.]] = bitcast i64 [[SIVAR_CASTED]] to i32*
	// CHECK2-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4			// CHECK2-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4
	// CHECK2-NEXT: [[TMP6:%.]] = load i64, i64 [[SIVAR_CASTED]], align 8			// CHECK2-NEXT: [[TMP6:%.]] = load i64, i64 [[SIVAR_CASTED]], align 8
	// CHECK2-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32, i32, ...)* bitcast (void (i32, i32, [2 x i32], i64, [2 x %struct.S], %struct.S, i64) @.omp_outlined. to void (i32, i32, ...)), [2 x i32] [[TMP0]], i64 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP2]], i64 [[TMP6]])			// CHECK2-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32, i32, ...)* bitcast (void (i32, i32, [2 x i32], i64, [2 x %struct.S], %struct.S, i64) @.omp_outlined. to void (i32, i32, ...)), [2 x i32] [[TMP0]], i64 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP2]], i64 [[TMP6]])
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined.			// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined.
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	// CHECK2-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]			// CHECK2-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]
	// CHECK2: omp.inner.for.cond.cleanup:			// CHECK2: omp.inner.for.cond.cleanup:
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_END:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
	// CHECK2: omp.inner.for.body:			// CHECK2: omp.inner.for.body:
	// CHECK2-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !5			// CHECK2-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !5
	// CHECK2-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64			// CHECK2-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64
	// CHECK2-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5			// CHECK2-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5
	// CHECK2-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64			// CHECK2-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
	// CHECK2-NEXT: [[TMP18:%.]] = load i32, i32 [[CONV]], align 4, !llvm.access.group !5			// CHECK2-NEXT: [[TMP18:%.]] = load i32, i32 [[CONV]], align 8, !llvm.access.group !5
	// CHECK2-NEXT: [[CONV8:%.]] = bitcast i64 [[T_VAR_CASTED]] to i32*			// CHECK2-NEXT: [[CONV8:%.]] = bitcast i64 [[T_VAR_CASTED]] to i32*
	// CHECK2-NEXT: store i32 [[TMP18]], i32* [[CONV8]], align 4, !llvm.access.group !5			// CHECK2-NEXT: store i32 [[TMP18]], i32* [[CONV8]], align 4, !llvm.access.group !5
	// CHECK2-NEXT: [[TMP19:%.]] = load i64, i64 [[T_VAR_CASTED]], align 8, !llvm.access.group !5			// CHECK2-NEXT: [[TMP19:%.]] = load i64, i64 [[T_VAR_CASTED]], align 8, !llvm.access.group !5
	// CHECK2-NEXT: [[TMP20:%.]] = load i32, i32 [[CONV1]], align 4, !llvm.access.group !5			// CHECK2-NEXT: [[TMP20:%.]] = load i32, i32 [[CONV1]], align 8, !llvm.access.group !5
	// CHECK2-NEXT: [[CONV9:%.]] = bitcast i64 [[SIVAR_CASTED]] to i32*			// CHECK2-NEXT: [[CONV9:%.]] = bitcast i64 [[SIVAR_CASTED]] to i32*
	// CHECK2-NEXT: store i32 [[TMP20]], i32* [[CONV9]], align 4, !llvm.access.group !5			// CHECK2-NEXT: store i32 [[TMP20]], i32* [[CONV9]], align 4, !llvm.access.group !5
	// CHECK2-NEXT: [[TMP21:%.]] = load i64, i64 [[SIVAR_CASTED]], align 8, !llvm.access.group !5			// CHECK2-NEXT: [[TMP21:%.]] = load i64, i64 [[SIVAR_CASTED]], align 8, !llvm.access.group !5
	// CHECK2-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, [2 x i32], i64, [2 x %struct.S], %struct.S, i64) @.omp_outlined..3 to void (i32, i32, ...)), i64 [[TMP15]], i64 [[TMP17]], [2 x i32] [[VEC2]], i64 [[TMP19]], [2 x %struct.S]* [[S_ARR3]], %struct.S* [[VAR5]], i64 [[TMP21]]), !llvm.access.group !5			// CHECK2-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, [2 x i32], i64, [2 x %struct.S], %struct.S, i64) @.omp_outlined..3 to void (i32, i32, ...)), i64 [[TMP15]], i64 [[TMP17]], [2 x i32] [[VEC2]], i64 [[TMP19]], [2 x %struct.S]* [[S_ARR3]], %struct.S* [[VAR5]], i64 [[TMP21]]), !llvm.access.group !5
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK2: omp.inner.for.inc:			// CHECK2: omp.inner.for.inc:
	// CHECK2-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5			// CHECK2-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK2-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !5			// CHECK2-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !5
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	// CHECK2-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]			// CHECK2-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]
	// CHECK2: omp.inner.for.cond.cleanup:			// CHECK2: omp.inner.for.cond.cleanup:
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_END:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
	// CHECK2: omp.inner.for.body:			// CHECK2: omp.inner.for.body:
	// CHECK2-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9			// CHECK2-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1			// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1
	// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9			// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9
	// CHECK2-NEXT: [[TMP17:%.]] = load i32, i32 [[CONV]], align 4, !llvm.access.group !9			// CHECK2-NEXT: [[TMP17:%.]] = load i32, i32 [[CONV]], align 8, !llvm.access.group !9
	// CHECK2-NEXT: [[TMP18:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !9			// CHECK2-NEXT: [[TMP18:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !9
	// CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP18]] to i64			// CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP18]] to i64
	// CHECK2-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC4]], i64 0, i64 [[IDXPROM]]			// CHECK2-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC4]], i64 0, i64 [[IDXPROM]]
	// CHECK2-NEXT: store i32 [[TMP17]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !9			// CHECK2-NEXT: store i32 [[TMP17]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !9
	// CHECK2-NEXT: [[TMP19:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !9			// CHECK2-NEXT: [[TMP19:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !9
	// CHECK2-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP19]] to i64			// CHECK2-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP19]] to i64
	// CHECK2-NEXT: [[ARRAYIDX11:%.]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S] [[S_ARR5]], i64 0, i64 [[IDXPROM10]]			// CHECK2-NEXT: [[ARRAYIDX11:%.]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S] [[S_ARR5]], i64 0, i64 [[IDXPROM10]]
	// CHECK2-NEXT: [[TMP20:%.]] = bitcast %struct.S [[ARRAYIDX11]] to i8*			// CHECK2-NEXT: [[TMP20:%.]] = bitcast %struct.S [[ARRAYIDX11]] to i8*
	// CHECK2-NEXT: [[TMP21:%.]] = bitcast %struct.S [[VAR7]] to i8*			// CHECK2-NEXT: [[TMP21:%.]] = bitcast %struct.S [[VAR7]] to i8*
	// CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i64 4, i1 false), !llvm.access.group !9			// CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i64 4, i1 false), !llvm.access.group !9
	// CHECK2-NEXT: [[TMP22:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !9			// CHECK2-NEXT: [[TMP22:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !9
	// CHECK2-NEXT: [[TMP23:%.]] = load i32, i32 [[CONV1]], align 4, !llvm.access.group !9			// CHECK2-NEXT: [[TMP23:%.]] = load i32, i32 [[CONV1]], align 8, !llvm.access.group !9
	// CHECK2-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP23]], [[TMP22]]			// CHECK2-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP23]], [[TMP22]]
	// CHECK2-NEXT: store i32 [[ADD12]], i32* [[CONV1]], align 4, !llvm.access.group !9			// CHECK2-NEXT: store i32 [[ADD12]], i32* [[CONV1]], align 8, !llvm.access.group !9
	// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK2: omp.body.continue:			// CHECK2: omp.body.continue:
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK2: omp.inner.for.inc:			// CHECK2: omp.inner.for.inc:
	// CHECK2-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9			// CHECK2-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK2-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP24]], 1			// CHECK2-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP24]], 1
	// CHECK2-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9			// CHECK2-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]
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	// CHECK2-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8			// CHECK2-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8
	// CHECK2-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8			// CHECK2-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
	// CHECK2-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8			// CHECK2-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8
	// CHECK2-NEXT: [[TMP0:%.]] = load [2 x i32], [2 x i32]** [[VEC_ADDR]], align 8			// CHECK2-NEXT: [[TMP0:%.]] = load [2 x i32], [2 x i32]** [[VEC_ADDR]], align 8
	// CHECK2-NEXT: [[CONV:%.]] = bitcast i64 [[T_VAR_ADDR]] to i32*			// CHECK2-NEXT: [[CONV:%.]] = bitcast i64 [[T_VAR_ADDR]] to i32*
	// CHECK2-NEXT: [[TMP1:%.]] = load [2 x %struct.S.0], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8			// CHECK2-NEXT: [[TMP1:%.]] = load [2 x %struct.S.0], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
	// CHECK2-NEXT: [[TMP2:%.]] = load %struct.S.0, %struct.S.0** [[VAR_ADDR]], align 8			// CHECK2-NEXT: [[TMP2:%.]] = load %struct.S.0, %struct.S.0** [[VAR_ADDR]], align 8
	// CHECK2-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8			// CHECK2-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8
	// CHECK2-NEXT: [[TMP3:%.]] = load i32, i32 [[CONV]], align 4			// CHECK2-NEXT: [[TMP3:%.]] = load i32, i32 [[CONV]], align 8
	// CHECK2-NEXT: [[CONV1:%.]] = bitcast i64 [[T_VAR_CASTED]] to i32*			// CHECK2-NEXT: [[CONV1:%.]] = bitcast i64 [[T_VAR_CASTED]] to i32*
	// CHECK2-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4			// CHECK2-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4
	// CHECK2-NEXT: [[TMP4:%.]] = load i64, i64 [[T_VAR_CASTED]], align 8			// CHECK2-NEXT: [[TMP4:%.]] = load i64, i64 [[T_VAR_CASTED]], align 8
	// CHECK2-NEXT: [[TMP5:%.]] = load %struct.S.0, %struct.S.0** [[TMP]], align 8			// CHECK2-NEXT: [[TMP5:%.]] = load %struct.S.0, %struct.S.0** [[TMP]], align 8
	// CHECK2-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32, i32, ...)* bitcast (void (i32, i32, [2 x i32], i64, [2 x %struct.S.0], %struct.S.0) @.omp_outlined..4 to void (i32, i32, ...)), [2 x i32] [[TMP0]], i64 [[TMP4]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP5]])			// CHECK2-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32, i32, ...)* bitcast (void (i32, i32, [2 x i32], i64, [2 x %struct.S.0], %struct.S.0) @.omp_outlined..4 to void (i32, i32, ...)), [2 x i32] [[TMP0]], i64 [[TMP4]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP5]])
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	//			//
	//			//
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	// CHECK2-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]			// CHECK2-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]
	// CHECK2: omp.inner.for.cond.cleanup:			// CHECK2: omp.inner.for.cond.cleanup:
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_END:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
	// CHECK2: omp.inner.for.body:			// CHECK2: omp.inner.for.body:
	// CHECK2-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !14			// CHECK2-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !14
	// CHECK2-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64			// CHECK2-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64
	// CHECK2-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !14			// CHECK2-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !14
	// CHECK2-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64			// CHECK2-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
	// CHECK2-NEXT: [[TMP19:%.]] = load i32, i32 [[CONV]], align 4, !llvm.access.group !14			// CHECK2-NEXT: [[TMP19:%.]] = load i32, i32 [[CONV]], align 8, !llvm.access.group !14
	// CHECK2-NEXT: [[CONV9:%.]] = bitcast i64 [[T_VAR_CASTED]] to i32*			// CHECK2-NEXT: [[CONV9:%.]] = bitcast i64 [[T_VAR_CASTED]] to i32*
	// CHECK2-NEXT: store i32 [[TMP19]], i32* [[CONV9]], align 4, !llvm.access.group !14			// CHECK2-NEXT: store i32 [[TMP19]], i32* [[CONV9]], align 4, !llvm.access.group !14
	// CHECK2-NEXT: [[TMP20:%.]] = load i64, i64 [[T_VAR_CASTED]], align 8, !llvm.access.group !14			// CHECK2-NEXT: [[TMP20:%.]] = load i64, i64 [[T_VAR_CASTED]], align 8, !llvm.access.group !14
	// CHECK2-NEXT: [[TMP21:%.]] = load %struct.S.0, %struct.S.0** [[_TMP7]], align 8, !llvm.access.group !14			// CHECK2-NEXT: [[TMP21:%.]] = load %struct.S.0, %struct.S.0** [[_TMP7]], align 8, !llvm.access.group !14
	// CHECK2-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, [2 x i32], i64, [2 x %struct.S.0], %struct.S.0) @.omp_outlined..5 to void (i32, i32, ...)), i64 [[TMP16]], i64 [[TMP18]], [2 x i32] [[VEC2]], i64 [[TMP20]], [2 x %struct.S.0]* [[S_ARR3]], %struct.S.0* [[TMP21]]), !llvm.access.group !14			// CHECK2-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, [2 x i32], i64, [2 x %struct.S.0], %struct.S.0) @.omp_outlined..5 to void (i32, i32, ...)), i64 [[TMP16]], i64 [[TMP18]], [2 x i32] [[VEC2]], i64 [[TMP20]], [2 x %struct.S.0]* [[S_ARR3]], %struct.S.0* [[TMP21]]), !llvm.access.group !14
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK2: omp.inner.for.inc:			// CHECK2: omp.inner.for.inc:
	// CHECK2-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14			// CHECK2-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14
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	// CHECK2-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]			// CHECK2-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]
	// CHECK2: omp.inner.for.cond.cleanup:			// CHECK2: omp.inner.for.cond.cleanup:
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_END:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
	// CHECK2: omp.inner.for.body:			// CHECK2: omp.inner.for.body:
	// CHECK2-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !17			// CHECK2-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !17
	// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1			// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1
	// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !17			// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !17
	// CHECK2-NEXT: [[TMP18:%.]] = load i32, i32 [[CONV]], align 4, !llvm.access.group !17			// CHECK2-NEXT: [[TMP18:%.]] = load i32, i32 [[CONV]], align 8, !llvm.access.group !17
	// CHECK2-NEXT: [[TMP19:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !17			// CHECK2-NEXT: [[TMP19:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !17
	// CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64			// CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64
	// CHECK2-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC4]], i64 0, i64 [[IDXPROM]]			// CHECK2-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC4]], i64 0, i64 [[IDXPROM]]
	// CHECK2-NEXT: store i32 [[TMP18]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !17			// CHECK2-NEXT: store i32 [[TMP18]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !17
	// CHECK2-NEXT: [[TMP20:%.]] = load %struct.S.0, %struct.S.0** [[_TMP9]], align 8, !llvm.access.group !17			// CHECK2-NEXT: [[TMP20:%.]] = load %struct.S.0, %struct.S.0** [[_TMP9]], align 8, !llvm.access.group !17
	// CHECK2-NEXT: [[TMP21:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !17			// CHECK2-NEXT: [[TMP21:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !17
	// CHECK2-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP21]] to i64			// CHECK2-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP21]] to i64
	// CHECK2-NEXT: [[ARRAYIDX12:%.]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0] [[S_ARR5]], i64 0, i64 [[IDXPROM11]]			// CHECK2-NEXT: [[ARRAYIDX12:%.]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0] [[S_ARR5]], i64 0, i64 [[IDXPROM11]]
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	// CHECK5-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8			// CHECK5-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8
	// CHECK5-NEXT: store i64 [[G]], i64* [[G_ADDR]], align 8			// CHECK5-NEXT: store i64 [[G]], i64* [[G_ADDR]], align 8
	// CHECK5-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8			// CHECK5-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8
	// CHECK5-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8			// CHECK5-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8
	// CHECK5-NEXT: [[CONV:%.]] = bitcast i64 [[G_ADDR]] to i32*			// CHECK5-NEXT: [[CONV:%.]] = bitcast i64 [[G_ADDR]] to i32*
	// CHECK5-NEXT: [[CONV1:%.]] = bitcast i64 [[G1_ADDR]] to i32*			// CHECK5-NEXT: [[CONV1:%.]] = bitcast i64 [[G1_ADDR]] to i32*
	// CHECK5-NEXT: [[CONV2:%.]] = bitcast i64 [[SIVAR_ADDR]] to i32*			// CHECK5-NEXT: [[CONV2:%.]] = bitcast i64 [[SIVAR_ADDR]] to i32*
	// CHECK5-NEXT: store i32* [[CONV1]], i32** [[TMP]], align 8			// CHECK5-NEXT: store i32* [[CONV1]], i32** [[TMP]], align 8
	// CHECK5-NEXT: [[TMP0:%.]] = load i32, i32 [[CONV]], align 4			// CHECK5-NEXT: [[TMP0:%.]] = load i32, i32 [[CONV]], align 8
	// CHECK5-NEXT: [[CONV3:%.]] = bitcast i64 [[G_CASTED]] to i32*			// CHECK5-NEXT: [[CONV3:%.]] = bitcast i64 [[G_CASTED]] to i32*
	// CHECK5-NEXT: store i32 [[TMP0]], i32* [[CONV3]], align 4			// CHECK5-NEXT: store i32 [[TMP0]], i32* [[CONV3]], align 4
	// CHECK5-NEXT: [[TMP1:%.]] = load i64, i64 [[G_CASTED]], align 8			// CHECK5-NEXT: [[TMP1:%.]] = load i64, i64 [[G_CASTED]], align 8
	// CHECK5-NEXT: [[TMP2:%.]] = load i32, i32** [[TMP]], align 8			// CHECK5-NEXT: [[TMP2:%.]] = load i32, i32** [[TMP]], align 8
	// CHECK5-NEXT: [[TMP3:%.]] = load volatile i32, i32 [[TMP2]], align 4			// CHECK5-NEXT: [[TMP3:%.]] = load volatile i32, i32 [[TMP2]], align 4
	// CHECK5-NEXT: [[CONV4:%.]] = bitcast i64 [[G1_CASTED]] to i32*			// CHECK5-NEXT: [[CONV4:%.]] = bitcast i64 [[G1_CASTED]] to i32*
	// CHECK5-NEXT: store i32 [[TMP3]], i32* [[CONV4]], align 4			// CHECK5-NEXT: store i32 [[TMP3]], i32* [[CONV4]], align 4
	// CHECK5-NEXT: [[TMP4:%.]] = load i64, i64 [[G1_CASTED]], align 8			// CHECK5-NEXT: [[TMP4:%.]] = load i64, i64 [[G1_CASTED]], align 8
	// CHECK5-NEXT: [[TMP5:%.]] = load i32, i32 [[CONV2]], align 4			// CHECK5-NEXT: [[TMP5:%.]] = load i32, i32 [[CONV2]], align 8
	// CHECK5-NEXT: [[CONV5:%.]] = bitcast i64 [[SIVAR_CASTED]] to i32*			// CHECK5-NEXT: [[CONV5:%.]] = bitcast i64 [[SIVAR_CASTED]] to i32*
	// CHECK5-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4			// CHECK5-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4
	// CHECK5-NEXT: [[TMP6:%.]] = load i64, i64 [[SIVAR_CASTED]], align 8			// CHECK5-NEXT: [[TMP6:%.]] = load i64, i64 [[SIVAR_CASTED]], align 8
	// CHECK5-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i64)* @.omp_outlined. to void (i32, i32, ...)*), i64 [[TMP1]], i64 [[TMP4]], i64 [[TMP6]])			// CHECK5-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i64)* @.omp_outlined. to void (i32, i32, ...)*), i64 [[TMP1]], i64 [[TMP4]], i64 [[TMP6]])
	// CHECK5-NEXT: ret void			// CHECK5-NEXT: ret void
	//			//
	//			//
	// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined.			// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined.
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	// CHECK5-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !4			// CHECK5-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !4
	// CHECK5-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK5-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK5-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK5-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK5: omp.inner.for.body:			// CHECK5: omp.inner.for.body:
	// CHECK5-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !4			// CHECK5-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !4
	// CHECK5-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64			// CHECK5-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
	// CHECK5-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !4			// CHECK5-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !4
	// CHECK5-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK5-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK5-NEXT: [[TMP11:%.]] = load i32, i32 [[CONV]], align 4, !llvm.access.group !4			// CHECK5-NEXT: [[TMP11:%.]] = load i32, i32 [[CONV]], align 8, !llvm.access.group !4
	// CHECK5-NEXT: [[CONV5:%.]] = bitcast i64 [[G_CASTED]] to i32*			// CHECK5-NEXT: [[CONV5:%.]] = bitcast i64 [[G_CASTED]] to i32*
	// CHECK5-NEXT: store i32 [[TMP11]], i32* [[CONV5]], align 4, !llvm.access.group !4			// CHECK5-NEXT: store i32 [[TMP11]], i32* [[CONV5]], align 4, !llvm.access.group !4
	// CHECK5-NEXT: [[TMP12:%.]] = load i64, i64 [[G_CASTED]], align 8, !llvm.access.group !4			// CHECK5-NEXT: [[TMP12:%.]] = load i64, i64 [[G_CASTED]], align 8, !llvm.access.group !4
	// CHECK5-NEXT: [[TMP13:%.]] = load i32, i32** [[TMP]], align 8, !llvm.access.group !4			// CHECK5-NEXT: [[TMP13:%.]] = load i32, i32** [[TMP]], align 8, !llvm.access.group !4
	// CHECK5-NEXT: [[TMP14:%.]] = load volatile i32, i32 [[TMP13]], align 4, !llvm.access.group !4			// CHECK5-NEXT: [[TMP14:%.]] = load volatile i32, i32 [[TMP13]], align 4, !llvm.access.group !4
	// CHECK5-NEXT: [[CONV6:%.]] = bitcast i64 [[G1_CASTED]] to i32*			// CHECK5-NEXT: [[CONV6:%.]] = bitcast i64 [[G1_CASTED]] to i32*
	// CHECK5-NEXT: store i32 [[TMP14]], i32* [[CONV6]], align 4, !llvm.access.group !4			// CHECK5-NEXT: store i32 [[TMP14]], i32* [[CONV6]], align 4, !llvm.access.group !4
	// CHECK5-NEXT: [[TMP15:%.]] = load i64, i64 [[G1_CASTED]], align 8, !llvm.access.group !4			// CHECK5-NEXT: [[TMP15:%.]] = load i64, i64 [[G1_CASTED]], align 8, !llvm.access.group !4
	// CHECK5-NEXT: [[TMP16:%.]] = load i32, i32 [[CONV2]], align 4, !llvm.access.group !4			// CHECK5-NEXT: [[TMP16:%.]] = load i32, i32 [[CONV2]], align 8, !llvm.access.group !4
	// CHECK5-NEXT: [[CONV7:%.]] = bitcast i64 [[SIVAR_CASTED]] to i32*			// CHECK5-NEXT: [[CONV7:%.]] = bitcast i64 [[SIVAR_CASTED]] to i32*
	// CHECK5-NEXT: store i32 [[TMP16]], i32* [[CONV7]], align 4, !llvm.access.group !4			// CHECK5-NEXT: store i32 [[TMP16]], i32* [[CONV7]], align 4, !llvm.access.group !4
	// CHECK5-NEXT: [[TMP17:%.]] = load i64, i64 [[SIVAR_CASTED]], align 8, !llvm.access.group !4			// CHECK5-NEXT: [[TMP17:%.]] = load i64, i64 [[SIVAR_CASTED]], align 8, !llvm.access.group !4
	// CHECK5-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i64, i64, i64)* @.omp_outlined..3 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]], i64 [[TMP12]], i64 [[TMP15]], i64 [[TMP17]]), !llvm.access.group !4			// CHECK5-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i64, i64, i64)* @.omp_outlined..3 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]], i64 [[TMP12]], i64 [[TMP15]], i64 [[TMP17]]), !llvm.access.group !4
	// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK5: omp.inner.for.inc:			// CHECK5: omp.inner.for.inc:
	// CHECK5-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !4			// CHECK5-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !4
	// CHECK5-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !4			// CHECK5-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !4
	▲ Show 20 Lines • Show All 76 Lines • ▼ Show 20 Lines
	// CHECK5-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !8			// CHECK5-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !8
	// CHECK5-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK5-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK5-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK5-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK5: omp.inner.for.body:			// CHECK5: omp.inner.for.body:
	// CHECK5-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !8			// CHECK5-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !8
	// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !8			// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !8
	// CHECK5-NEXT: store i32 1, i32* [[CONV]], align 4, !llvm.access.group !8			// CHECK5-NEXT: store i32 1, i32* [[CONV]], align 8, !llvm.access.group !8
	// CHECK5-NEXT: [[TMP10:%.]] = load i32, i32** [[TMP]], align 8, !llvm.access.group !8			// CHECK5-NEXT: [[TMP10:%.]] = load i32, i32** [[TMP]], align 8, !llvm.access.group !8
	// CHECK5-NEXT: store volatile i32 1, i32* [[TMP10]], align 4, !llvm.access.group !8			// CHECK5-NEXT: store volatile i32 1, i32* [[TMP10]], align 4, !llvm.access.group !8
	// CHECK5-NEXT: store i32 2, i32* [[CONV2]], align 4, !llvm.access.group !8			// CHECK5-NEXT: store i32 2, i32* [[CONV2]], align 8, !llvm.access.group !8
	// CHECK5-NEXT: [[TMP11:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 0			// CHECK5-NEXT: [[TMP11:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 0
	// CHECK5-NEXT: store i32* [[CONV]], i32** [[TMP11]], align 8, !llvm.access.group !8			// CHECK5-NEXT: store i32* [[CONV]], i32** [[TMP11]], align 8, !llvm.access.group !8
	// CHECK5-NEXT: [[TMP12:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 1			// CHECK5-NEXT: [[TMP12:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 1
	// CHECK5-NEXT: [[TMP13:%.]] = load i32, i32** [[TMP]], align 8, !llvm.access.group !8			// CHECK5-NEXT: [[TMP13:%.]] = load i32, i32** [[TMP]], align 8, !llvm.access.group !8
	// CHECK5-NEXT: store i32* [[TMP13]], i32** [[TMP12]], align 8, !llvm.access.group !8			// CHECK5-NEXT: store i32* [[TMP13]], i32** [[TMP12]], align 8, !llvm.access.group !8
	// CHECK5-NEXT: [[TMP14:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 2			// CHECK5-NEXT: [[TMP14:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 2
	// CHECK5-NEXT: store i32* [[CONV2]], i32** [[TMP14]], align 8, !llvm.access.group !8			// CHECK5-NEXT: store i32* [[CONV2]], i32** [[TMP14]], align 8, !llvm.access.group !8
	// CHECK5-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(24) [[REF_TMP]]), !llvm.access.group !8			// CHECK5-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(24) [[REF_TMP]]), !llvm.access.group !8
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	// CHECK6-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8			// CHECK6-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8
	// CHECK6-NEXT: store i64 [[G]], i64* [[G_ADDR]], align 8			// CHECK6-NEXT: store i64 [[G]], i64* [[G_ADDR]], align 8
	// CHECK6-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8			// CHECK6-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8
	// CHECK6-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8			// CHECK6-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8
	// CHECK6-NEXT: [[CONV:%.]] = bitcast i64 [[G_ADDR]] to i32*			// CHECK6-NEXT: [[CONV:%.]] = bitcast i64 [[G_ADDR]] to i32*
	// CHECK6-NEXT: [[CONV1:%.]] = bitcast i64 [[G1_ADDR]] to i32*			// CHECK6-NEXT: [[CONV1:%.]] = bitcast i64 [[G1_ADDR]] to i32*
	// CHECK6-NEXT: [[CONV2:%.]] = bitcast i64 [[SIVAR_ADDR]] to i32*			// CHECK6-NEXT: [[CONV2:%.]] = bitcast i64 [[SIVAR_ADDR]] to i32*
	// CHECK6-NEXT: store i32* [[CONV1]], i32** [[TMP]], align 8			// CHECK6-NEXT: store i32* [[CONV1]], i32** [[TMP]], align 8
	// CHECK6-NEXT: [[TMP0:%.]] = load i32, i32 [[CONV]], align 4			// CHECK6-NEXT: [[TMP0:%.]] = load i32, i32 [[CONV]], align 8
	// CHECK6-NEXT: [[CONV3:%.]] = bitcast i64 [[G_CASTED]] to i32*			// CHECK6-NEXT: [[CONV3:%.]] = bitcast i64 [[G_CASTED]] to i32*
	// CHECK6-NEXT: store i32 [[TMP0]], i32* [[CONV3]], align 4			// CHECK6-NEXT: store i32 [[TMP0]], i32* [[CONV3]], align 4
	// CHECK6-NEXT: [[TMP1:%.]] = load i64, i64 [[G_CASTED]], align 8			// CHECK6-NEXT: [[TMP1:%.]] = load i64, i64 [[G_CASTED]], align 8
	// CHECK6-NEXT: [[TMP2:%.]] = load i32, i32** [[TMP]], align 8			// CHECK6-NEXT: [[TMP2:%.]] = load i32, i32** [[TMP]], align 8
	// CHECK6-NEXT: [[TMP3:%.]] = load volatile i32, i32 [[TMP2]], align 4			// CHECK6-NEXT: [[TMP3:%.]] = load volatile i32, i32 [[TMP2]], align 4
	// CHECK6-NEXT: [[CONV4:%.]] = bitcast i64 [[G1_CASTED]] to i32*			// CHECK6-NEXT: [[CONV4:%.]] = bitcast i64 [[G1_CASTED]] to i32*
	// CHECK6-NEXT: store i32 [[TMP3]], i32* [[CONV4]], align 4			// CHECK6-NEXT: store i32 [[TMP3]], i32* [[CONV4]], align 4
	// CHECK6-NEXT: [[TMP4:%.]] = load i64, i64 [[G1_CASTED]], align 8			// CHECK6-NEXT: [[TMP4:%.]] = load i64, i64 [[G1_CASTED]], align 8
	// CHECK6-NEXT: [[TMP5:%.]] = load i32, i32 [[CONV2]], align 4			// CHECK6-NEXT: [[TMP5:%.]] = load i32, i32 [[CONV2]], align 8
	// CHECK6-NEXT: [[CONV5:%.]] = bitcast i64 [[SIVAR_CASTED]] to i32*			// CHECK6-NEXT: [[CONV5:%.]] = bitcast i64 [[SIVAR_CASTED]] to i32*
	// CHECK6-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4			// CHECK6-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4
	// CHECK6-NEXT: [[TMP6:%.]] = load i64, i64 [[SIVAR_CASTED]], align 8			// CHECK6-NEXT: [[TMP6:%.]] = load i64, i64 [[SIVAR_CASTED]], align 8
	// CHECK6-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i64)* @.omp_outlined. to void (i32, i32, ...)*), i64 [[TMP1]], i64 [[TMP4]], i64 [[TMP6]])			// CHECK6-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i64)* @.omp_outlined. to void (i32, i32, ...)*), i64 [[TMP1]], i64 [[TMP4]], i64 [[TMP6]])
	// CHECK6-NEXT: ret void			// CHECK6-NEXT: ret void
	//			//
	//			//
	// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined.			// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined.
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	// CHECK6-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !4			// CHECK6-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !4
	// CHECK6-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK6-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK6-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK6-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK6: omp.inner.for.body:			// CHECK6: omp.inner.for.body:
	// CHECK6-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !4			// CHECK6-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !4
	// CHECK6-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64			// CHECK6-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
	// CHECK6-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !4			// CHECK6-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !4
	// CHECK6-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK6-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK6-NEXT: [[TMP11:%.]] = load i32, i32 [[CONV]], align 4, !llvm.access.group !4			// CHECK6-NEXT: [[TMP11:%.]] = load i32, i32 [[CONV]], align 8, !llvm.access.group !4
	// CHECK6-NEXT: [[CONV5:%.]] = bitcast i64 [[G_CASTED]] to i32*			// CHECK6-NEXT: [[CONV5:%.]] = bitcast i64 [[G_CASTED]] to i32*
	// CHECK6-NEXT: store i32 [[TMP11]], i32* [[CONV5]], align 4, !llvm.access.group !4			// CHECK6-NEXT: store i32 [[TMP11]], i32* [[CONV5]], align 4, !llvm.access.group !4
	// CHECK6-NEXT: [[TMP12:%.]] = load i64, i64 [[G_CASTED]], align 8, !llvm.access.group !4			// CHECK6-NEXT: [[TMP12:%.]] = load i64, i64 [[G_CASTED]], align 8, !llvm.access.group !4
	// CHECK6-NEXT: [[TMP13:%.]] = load i32, i32** [[TMP]], align 8, !llvm.access.group !4			// CHECK6-NEXT: [[TMP13:%.]] = load i32, i32** [[TMP]], align 8, !llvm.access.group !4
	// CHECK6-NEXT: [[TMP14:%.]] = load volatile i32, i32 [[TMP13]], align 4, !llvm.access.group !4			// CHECK6-NEXT: [[TMP14:%.]] = load volatile i32, i32 [[TMP13]], align 4, !llvm.access.group !4
	// CHECK6-NEXT: [[CONV6:%.]] = bitcast i64 [[G1_CASTED]] to i32*			// CHECK6-NEXT: [[CONV6:%.]] = bitcast i64 [[G1_CASTED]] to i32*
	// CHECK6-NEXT: store i32 [[TMP14]], i32* [[CONV6]], align 4, !llvm.access.group !4			// CHECK6-NEXT: store i32 [[TMP14]], i32* [[CONV6]], align 4, !llvm.access.group !4
	// CHECK6-NEXT: [[TMP15:%.]] = load i64, i64 [[G1_CASTED]], align 8, !llvm.access.group !4			// CHECK6-NEXT: [[TMP15:%.]] = load i64, i64 [[G1_CASTED]], align 8, !llvm.access.group !4
	// CHECK6-NEXT: [[TMP16:%.]] = load i32, i32 [[CONV2]], align 4, !llvm.access.group !4			// CHECK6-NEXT: [[TMP16:%.]] = load i32, i32 [[CONV2]], align 8, !llvm.access.group !4
	// CHECK6-NEXT: [[CONV7:%.]] = bitcast i64 [[SIVAR_CASTED]] to i32*			// CHECK6-NEXT: [[CONV7:%.]] = bitcast i64 [[SIVAR_CASTED]] to i32*
	// CHECK6-NEXT: store i32 [[TMP16]], i32* [[CONV7]], align 4, !llvm.access.group !4			// CHECK6-NEXT: store i32 [[TMP16]], i32* [[CONV7]], align 4, !llvm.access.group !4
	// CHECK6-NEXT: [[TMP17:%.]] = load i64, i64 [[SIVAR_CASTED]], align 8, !llvm.access.group !4			// CHECK6-NEXT: [[TMP17:%.]] = load i64, i64 [[SIVAR_CASTED]], align 8, !llvm.access.group !4
	// CHECK6-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i64, i64, i64)* @.omp_outlined..3 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]], i64 [[TMP12]], i64 [[TMP15]], i64 [[TMP17]]), !llvm.access.group !4			// CHECK6-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i64, i64, i64)* @.omp_outlined..3 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]], i64 [[TMP12]], i64 [[TMP15]], i64 [[TMP17]]), !llvm.access.group !4
	// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK6: omp.inner.for.inc:			// CHECK6: omp.inner.for.inc:
	// CHECK6-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !4			// CHECK6-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !4
	// CHECK6-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !4			// CHECK6-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !4
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	// CHECK6-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !8			// CHECK6-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !8
	// CHECK6-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK6-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK6-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK6-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK6: omp.inner.for.body:			// CHECK6: omp.inner.for.body:
	// CHECK6-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !8			// CHECK6-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !8
	// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !8			// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !8
	// CHECK6-NEXT: store i32 1, i32* [[CONV]], align 4, !llvm.access.group !8			// CHECK6-NEXT: store i32 1, i32* [[CONV]], align 8, !llvm.access.group !8
	// CHECK6-NEXT: [[TMP10:%.]] = load i32, i32** [[TMP]], align 8, !llvm.access.group !8			// CHECK6-NEXT: [[TMP10:%.]] = load i32, i32** [[TMP]], align 8, !llvm.access.group !8
	// CHECK6-NEXT: store volatile i32 1, i32* [[TMP10]], align 4, !llvm.access.group !8			// CHECK6-NEXT: store volatile i32 1, i32* [[TMP10]], align 4, !llvm.access.group !8
	// CHECK6-NEXT: store i32 2, i32* [[CONV2]], align 4, !llvm.access.group !8			// CHECK6-NEXT: store i32 2, i32* [[CONV2]], align 8, !llvm.access.group !8
	// CHECK6-NEXT: [[TMP11:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 0			// CHECK6-NEXT: [[TMP11:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 0
	// CHECK6-NEXT: store i32* [[CONV]], i32** [[TMP11]], align 8, !llvm.access.group !8			// CHECK6-NEXT: store i32* [[CONV]], i32** [[TMP11]], align 8, !llvm.access.group !8
	// CHECK6-NEXT: [[TMP12:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 1			// CHECK6-NEXT: [[TMP12:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 1
	// CHECK6-NEXT: [[TMP13:%.]] = load i32, i32** [[TMP]], align 8, !llvm.access.group !8			// CHECK6-NEXT: [[TMP13:%.]] = load i32, i32** [[TMP]], align 8, !llvm.access.group !8
	// CHECK6-NEXT: store i32* [[TMP13]], i32** [[TMP12]], align 8, !llvm.access.group !8			// CHECK6-NEXT: store i32* [[TMP13]], i32** [[TMP12]], align 8, !llvm.access.group !8
	// CHECK6-NEXT: [[TMP14:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 2			// CHECK6-NEXT: [[TMP14:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 2
	// CHECK6-NEXT: store i32* [[CONV2]], i32** [[TMP14]], align 8, !llvm.access.group !8			// CHECK6-NEXT: store i32* [[CONV2]], i32** [[TMP14]], align 8, !llvm.access.group !8
	// CHECK6-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(24) [[REF_TMP]]), !llvm.access.group !8			// CHECK6-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(24) [[REF_TMP]]), !llvm.access.group !8
	▲ Show 20 Lines • Show All 1,614 Lines • ▼ Show 20 Lines
	// CHECK13-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8			// CHECK13-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8
	// CHECK13-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8			// CHECK13-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8
	// CHECK13-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8			// CHECK13-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8
	// CHECK13-NEXT: [[TMP0:%.]] = load [2 x i32], [2 x i32]** [[VEC_ADDR]], align 8			// CHECK13-NEXT: [[TMP0:%.]] = load [2 x i32], [2 x i32]** [[VEC_ADDR]], align 8
	// CHECK13-NEXT: [[CONV:%.]] = bitcast i64 [[T_VAR_ADDR]] to i32*			// CHECK13-NEXT: [[CONV:%.]] = bitcast i64 [[T_VAR_ADDR]] to i32*
	// CHECK13-NEXT: [[TMP1:%.]] = load [2 x %struct.S], [2 x %struct.S]** [[S_ARR_ADDR]], align 8			// CHECK13-NEXT: [[TMP1:%.]] = load [2 x %struct.S], [2 x %struct.S]** [[S_ARR_ADDR]], align 8
	// CHECK13-NEXT: [[TMP2:%.]] = load %struct.S, %struct.S** [[VAR_ADDR]], align 8			// CHECK13-NEXT: [[TMP2:%.]] = load %struct.S, %struct.S** [[VAR_ADDR]], align 8
	// CHECK13-NEXT: [[CONV1:%.]] = bitcast i64 [[SIVAR_ADDR]] to i32*			// CHECK13-NEXT: [[CONV1:%.]] = bitcast i64 [[SIVAR_ADDR]] to i32*
	// CHECK13-NEXT: [[TMP3:%.]] = load i32, i32 [[CONV]], align 4			// CHECK13-NEXT: [[TMP3:%.]] = load i32, i32 [[CONV]], align 8
	// CHECK13-NEXT: [[CONV2:%.]] = bitcast i64 [[T_VAR_CASTED]] to i32*			// CHECK13-NEXT: [[CONV2:%.]] = bitcast i64 [[T_VAR_CASTED]] to i32*
	// CHECK13-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4			// CHECK13-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
	// CHECK13-NEXT: [[TMP4:%.]] = load i64, i64 [[T_VAR_CASTED]], align 8			// CHECK13-NEXT: [[TMP4:%.]] = load i64, i64 [[T_VAR_CASTED]], align 8
	// CHECK13-NEXT: [[TMP5:%.]] = load i32, i32 [[CONV1]], align 4			// CHECK13-NEXT: [[TMP5:%.]] = load i32, i32 [[CONV1]], align 8
	// CHECK13-NEXT: [[CONV3:%.]] = bitcast i64 [[SIVAR_CASTED]] to i32*			// CHECK13-NEXT: [[CONV3:%.]] = bitcast i64 [[SIVAR_CASTED]] to i32*
	// CHECK13-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4			// CHECK13-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4
	// CHECK13-NEXT: [[TMP6:%.]] = load i64, i64 [[SIVAR_CASTED]], align 8			// CHECK13-NEXT: [[TMP6:%.]] = load i64, i64 [[SIVAR_CASTED]], align 8
	// CHECK13-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 5, void (i32, i32, ...)* bitcast (void (i32, i32, [2 x i32], i64, [2 x %struct.S], %struct.S, i64) @.omp_outlined. to void (i32, i32, ...)), [2 x i32] [[TMP0]], i64 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP2]], i64 [[TMP6]])			// CHECK13-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 5, void (i32, i32, ...)* bitcast (void (i32, i32, [2 x i32], i64, [2 x %struct.S], %struct.S, i64) @.omp_outlined. to void (i32, i32, ...)), [2 x i32] [[TMP0]], i64 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP2]], i64 [[TMP6]])
	// CHECK13-NEXT: ret void			// CHECK13-NEXT: ret void
	//			//
	//			//
	// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined.			// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined.
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	// CHECK13-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]			// CHECK13-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]
	// CHECK13: omp.inner.for.cond.cleanup:			// CHECK13: omp.inner.for.cond.cleanup:
	// CHECK13-NEXT: br label [[OMP_INNER_FOR_END:%.*]]			// CHECK13-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
	// CHECK13: omp.inner.for.body:			// CHECK13: omp.inner.for.body:
	// CHECK13-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !6			// CHECK13-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !6
	// CHECK13-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64			// CHECK13-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64
	// CHECK13-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !6			// CHECK13-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !6
	// CHECK13-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64			// CHECK13-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
	// CHECK13-NEXT: [[TMP18:%.]] = load i32, i32 [[CONV]], align 4, !llvm.access.group !6			// CHECK13-NEXT: [[TMP18:%.]] = load i32, i32 [[CONV]], align 8, !llvm.access.group !6
	// CHECK13-NEXT: [[CONV8:%.]] = bitcast i64 [[T_VAR_CASTED]] to i32*			// CHECK13-NEXT: [[CONV8:%.]] = bitcast i64 [[T_VAR_CASTED]] to i32*
	// CHECK13-NEXT: store i32 [[TMP18]], i32* [[CONV8]], align 4, !llvm.access.group !6			// CHECK13-NEXT: store i32 [[TMP18]], i32* [[CONV8]], align 4, !llvm.access.group !6
	// CHECK13-NEXT: [[TMP19:%.]] = load i64, i64 [[T_VAR_CASTED]], align 8, !llvm.access.group !6			// CHECK13-NEXT: [[TMP19:%.]] = load i64, i64 [[T_VAR_CASTED]], align 8, !llvm.access.group !6
	// CHECK13-NEXT: [[TMP20:%.]] = load i32, i32 [[CONV1]], align 4, !llvm.access.group !6			// CHECK13-NEXT: [[TMP20:%.]] = load i32, i32 [[CONV1]], align 8, !llvm.access.group !6
	// CHECK13-NEXT: [[CONV9:%.]] = bitcast i64 [[SIVAR_CASTED]] to i32*			// CHECK13-NEXT: [[CONV9:%.]] = bitcast i64 [[SIVAR_CASTED]] to i32*
	// CHECK13-NEXT: store i32 [[TMP20]], i32* [[CONV9]], align 4, !llvm.access.group !6			// CHECK13-NEXT: store i32 [[TMP20]], i32* [[CONV9]], align 4, !llvm.access.group !6
	// CHECK13-NEXT: [[TMP21:%.]] = load i64, i64 [[SIVAR_CASTED]], align 8, !llvm.access.group !6			// CHECK13-NEXT: [[TMP21:%.]] = load i64, i64 [[SIVAR_CASTED]], align 8, !llvm.access.group !6
	// CHECK13-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, [2 x i32], i64, [2 x %struct.S], %struct.S, i64) @.omp_outlined..1 to void (i32, i32, ...)), i64 [[TMP15]], i64 [[TMP17]], [2 x i32] [[VEC2]], i64 [[TMP19]], [2 x %struct.S]* [[S_ARR3]], %struct.S* [[VAR5]], i64 [[TMP21]]), !llvm.access.group !6			// CHECK13-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, [2 x i32], i64, [2 x %struct.S], %struct.S, i64) @.omp_outlined..1 to void (i32, i32, ...)), i64 [[TMP15]], i64 [[TMP17]], [2 x i32] [[VEC2]], i64 [[TMP19]], [2 x %struct.S]* [[S_ARR3]], %struct.S* [[VAR5]], i64 [[TMP21]]), !llvm.access.group !6
	// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK13: omp.inner.for.inc:			// CHECK13: omp.inner.for.inc:
	// CHECK13-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !6			// CHECK13-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !6
	// CHECK13-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !6			// CHECK13-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !6
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	// CHECK13-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]			// CHECK13-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]
	// CHECK13: omp.inner.for.cond.cleanup:			// CHECK13: omp.inner.for.cond.cleanup:
	// CHECK13-NEXT: br label [[OMP_INNER_FOR_END:%.*]]			// CHECK13-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
	// CHECK13: omp.inner.for.body:			// CHECK13: omp.inner.for.body:
	// CHECK13-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10			// CHECK13-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1			// CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1
	// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK13-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10			// CHECK13-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10
	// CHECK13-NEXT: [[TMP17:%.]] = load i32, i32 [[CONV]], align 4, !llvm.access.group !10			// CHECK13-NEXT: [[TMP17:%.]] = load i32, i32 [[CONV]], align 8, !llvm.access.group !10
	// CHECK13-NEXT: [[TMP18:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !10			// CHECK13-NEXT: [[TMP18:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !10
	// CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP18]] to i64			// CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP18]] to i64
	// CHECK13-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC4]], i64 0, i64 [[IDXPROM]]			// CHECK13-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC4]], i64 0, i64 [[IDXPROM]]
	// CHECK13-NEXT: store i32 [[TMP17]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !10			// CHECK13-NEXT: store i32 [[TMP17]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !10
	// CHECK13-NEXT: [[TMP19:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !10			// CHECK13-NEXT: [[TMP19:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !10
	// CHECK13-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP19]] to i64			// CHECK13-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP19]] to i64
	// CHECK13-NEXT: [[ARRAYIDX11:%.]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S] [[S_ARR5]], i64 0, i64 [[IDXPROM10]]			// CHECK13-NEXT: [[ARRAYIDX11:%.]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S] [[S_ARR5]], i64 0, i64 [[IDXPROM10]]
	// CHECK13-NEXT: [[TMP20:%.]] = bitcast %struct.S [[ARRAYIDX11]] to i8*			// CHECK13-NEXT: [[TMP20:%.]] = bitcast %struct.S [[ARRAYIDX11]] to i8*
	// CHECK13-NEXT: [[TMP21:%.]] = bitcast %struct.S [[VAR7]] to i8*			// CHECK13-NEXT: [[TMP21:%.]] = bitcast %struct.S [[VAR7]] to i8*
	// CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i64 4, i1 false), !llvm.access.group !10			// CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i64 4, i1 false), !llvm.access.group !10
	// CHECK13-NEXT: [[TMP22:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !10			// CHECK13-NEXT: [[TMP22:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !10
	// CHECK13-NEXT: [[TMP23:%.]] = load i32, i32 [[CONV1]], align 4, !llvm.access.group !10			// CHECK13-NEXT: [[TMP23:%.]] = load i32, i32 [[CONV1]], align 8, !llvm.access.group !10
	// CHECK13-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP23]], [[TMP22]]			// CHECK13-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP23]], [[TMP22]]
	// CHECK13-NEXT: store i32 [[ADD12]], i32* [[CONV1]], align 4, !llvm.access.group !10			// CHECK13-NEXT: store i32 [[ADD12]], i32* [[CONV1]], align 8, !llvm.access.group !10
	// CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK13: omp.body.continue:			// CHECK13: omp.body.continue:
	// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK13: omp.inner.for.inc:			// CHECK13: omp.inner.for.inc:
	// CHECK13-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10			// CHECK13-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK13-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP24]], 1			// CHECK13-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP24]], 1
	// CHECK13-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10			// CHECK13-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]			// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]
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	// CHECK13-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8			// CHECK13-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8
	// CHECK13-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8			// CHECK13-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
	// CHECK13-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8			// CHECK13-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8
	// CHECK13-NEXT: [[TMP0:%.]] = load [2 x i32], [2 x i32]** [[VEC_ADDR]], align 8			// CHECK13-NEXT: [[TMP0:%.]] = load [2 x i32], [2 x i32]** [[VEC_ADDR]], align 8
	// CHECK13-NEXT: [[CONV:%.]] = bitcast i64 [[T_VAR_ADDR]] to i32*			// CHECK13-NEXT: [[CONV:%.]] = bitcast i64 [[T_VAR_ADDR]] to i32*
	// CHECK13-NEXT: [[TMP1:%.]] = load [2 x %struct.S.0], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8			// CHECK13-NEXT: [[TMP1:%.]] = load [2 x %struct.S.0], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
	// CHECK13-NEXT: [[TMP2:%.]] = load %struct.S.0, %struct.S.0** [[VAR_ADDR]], align 8			// CHECK13-NEXT: [[TMP2:%.]] = load %struct.S.0, %struct.S.0** [[VAR_ADDR]], align 8
	// CHECK13-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8			// CHECK13-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8
	// CHECK13-NEXT: [[TMP3:%.]] = load i32, i32 [[CONV]], align 4			// CHECK13-NEXT: [[TMP3:%.]] = load i32, i32 [[CONV]], align 8
	// CHECK13-NEXT: [[CONV1:%.]] = bitcast i64 [[T_VAR_CASTED]] to i32*			// CHECK13-NEXT: [[CONV1:%.]] = bitcast i64 [[T_VAR_CASTED]] to i32*
	// CHECK13-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4			// CHECK13-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4
	// CHECK13-NEXT: [[TMP4:%.]] = load i64, i64 [[T_VAR_CASTED]], align 8			// CHECK13-NEXT: [[TMP4:%.]] = load i64, i64 [[T_VAR_CASTED]], align 8
	// CHECK13-NEXT: [[TMP5:%.]] = load %struct.S.0, %struct.S.0** [[TMP]], align 8			// CHECK13-NEXT: [[TMP5:%.]] = load %struct.S.0, %struct.S.0** [[TMP]], align 8
	// CHECK13-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32, i32, ...)* bitcast (void (i32, i32, [2 x i32], i64, [2 x %struct.S.0], %struct.S.0) @.omp_outlined..2 to void (i32, i32, ...)), [2 x i32] [[TMP0]], i64 [[TMP4]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP5]])			// CHECK13-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32, i32, ...)* bitcast (void (i32, i32, [2 x i32], i64, [2 x %struct.S.0], %struct.S.0) @.omp_outlined..2 to void (i32, i32, ...)), [2 x i32] [[TMP0]], i64 [[TMP4]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP5]])
	// CHECK13-NEXT: ret void			// CHECK13-NEXT: ret void
	//			//
	//			//
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	// CHECK13-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]			// CHECK13-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]
	// CHECK13: omp.inner.for.cond.cleanup:			// CHECK13: omp.inner.for.cond.cleanup:
	// CHECK13-NEXT: br label [[OMP_INNER_FOR_END:%.*]]			// CHECK13-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
	// CHECK13: omp.inner.for.body:			// CHECK13: omp.inner.for.body:
	// CHECK13-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !15			// CHECK13-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !15
	// CHECK13-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64			// CHECK13-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64
	// CHECK13-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15			// CHECK13-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15
	// CHECK13-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64			// CHECK13-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
	// CHECK13-NEXT: [[TMP19:%.]] = load i32, i32 [[CONV]], align 4, !llvm.access.group !15			// CHECK13-NEXT: [[TMP19:%.]] = load i32, i32 [[CONV]], align 8, !llvm.access.group !15
	// CHECK13-NEXT: [[CONV9:%.]] = bitcast i64 [[T_VAR_CASTED]] to i32*			// CHECK13-NEXT: [[CONV9:%.]] = bitcast i64 [[T_VAR_CASTED]] to i32*
	// CHECK13-NEXT: store i32 [[TMP19]], i32* [[CONV9]], align 4, !llvm.access.group !15			// CHECK13-NEXT: store i32 [[TMP19]], i32* [[CONV9]], align 4, !llvm.access.group !15
	// CHECK13-NEXT: [[TMP20:%.]] = load i64, i64 [[T_VAR_CASTED]], align 8, !llvm.access.group !15			// CHECK13-NEXT: [[TMP20:%.]] = load i64, i64 [[T_VAR_CASTED]], align 8, !llvm.access.group !15
	// CHECK13-NEXT: [[TMP21:%.]] = load %struct.S.0, %struct.S.0** [[_TMP7]], align 8, !llvm.access.group !15			// CHECK13-NEXT: [[TMP21:%.]] = load %struct.S.0, %struct.S.0** [[_TMP7]], align 8, !llvm.access.group !15
	// CHECK13-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, [2 x i32], i64, [2 x %struct.S.0], %struct.S.0) @.omp_outlined..3 to void (i32, i32, ...)), i64 [[TMP16]], i64 [[TMP18]], [2 x i32] [[VEC2]], i64 [[TMP20]], [2 x %struct.S.0]* [[S_ARR3]], %struct.S.0* [[TMP21]]), !llvm.access.group !15			// CHECK13-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, [2 x i32], i64, [2 x %struct.S.0], %struct.S.0) @.omp_outlined..3 to void (i32, i32, ...)), i64 [[TMP16]], i64 [[TMP18]], [2 x i32] [[VEC2]], i64 [[TMP20]], [2 x %struct.S.0]* [[S_ARR3]], %struct.S.0* [[TMP21]]), !llvm.access.group !15
	// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK13: omp.inner.for.inc:			// CHECK13: omp.inner.for.inc:
	// CHECK13-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15			// CHECK13-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15
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	// CHECK13-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]			// CHECK13-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]
	// CHECK13: omp.inner.for.cond.cleanup:			// CHECK13: omp.inner.for.cond.cleanup:
	// CHECK13-NEXT: br label [[OMP_INNER_FOR_END:%.*]]			// CHECK13-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
	// CHECK13: omp.inner.for.body:			// CHECK13: omp.inner.for.body:
	// CHECK13-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18			// CHECK13-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1			// CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1
	// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK13-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !18			// CHECK13-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !18
	// CHECK13-NEXT: [[TMP18:%.]] = load i32, i32 [[CONV]], align 4, !llvm.access.group !18			// CHECK13-NEXT: [[TMP18:%.]] = load i32, i32 [[CONV]], align 8, !llvm.access.group !18
	// CHECK13-NEXT: [[TMP19:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !18			// CHECK13-NEXT: [[TMP19:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !18
	// CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64			// CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64
	// CHECK13-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC4]], i64 0, i64 [[IDXPROM]]			// CHECK13-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC4]], i64 0, i64 [[IDXPROM]]
	// CHECK13-NEXT: store i32 [[TMP18]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !18			// CHECK13-NEXT: store i32 [[TMP18]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !18
	// CHECK13-NEXT: [[TMP20:%.]] = load %struct.S.0, %struct.S.0** [[_TMP9]], align 8, !llvm.access.group !18			// CHECK13-NEXT: [[TMP20:%.]] = load %struct.S.0, %struct.S.0** [[_TMP9]], align 8, !llvm.access.group !18
	// CHECK13-NEXT: [[TMP21:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !18			// CHECK13-NEXT: [[TMP21:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !18
	// CHECK13-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP21]] to i64			// CHECK13-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP21]] to i64
	// CHECK13-NEXT: [[ARRAYIDX12:%.]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0] [[S_ARR5]], i64 0, i64 [[IDXPROM11]]			// CHECK13-NEXT: [[ARRAYIDX12:%.]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0] [[S_ARR5]], i64 0, i64 [[IDXPROM11]]
	▲ Show 20 Lines • Show All 139 Lines • ▼ Show 20 Lines
	// CHECK14-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8			// CHECK14-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8
	// CHECK14-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8			// CHECK14-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8
	// CHECK14-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8			// CHECK14-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8
	// CHECK14-NEXT: [[TMP0:%.]] = load [2 x i32], [2 x i32]** [[VEC_ADDR]], align 8			// CHECK14-NEXT: [[TMP0:%.]] = load [2 x i32], [2 x i32]** [[VEC_ADDR]], align 8
	// CHECK14-NEXT: [[CONV:%.]] = bitcast i64 [[T_VAR_ADDR]] to i32*			// CHECK14-NEXT: [[CONV:%.]] = bitcast i64 [[T_VAR_ADDR]] to i32*
	// CHECK14-NEXT: [[TMP1:%.]] = load [2 x %struct.S], [2 x %struct.S]** [[S_ARR_ADDR]], align 8			// CHECK14-NEXT: [[TMP1:%.]] = load [2 x %struct.S], [2 x %struct.S]** [[S_ARR_ADDR]], align 8
	// CHECK14-NEXT: [[TMP2:%.]] = load %struct.S, %struct.S** [[VAR_ADDR]], align 8			// CHECK14-NEXT: [[TMP2:%.]] = load %struct.S, %struct.S** [[VAR_ADDR]], align 8
	// CHECK14-NEXT: [[CONV1:%.]] = bitcast i64 [[SIVAR_ADDR]] to i32*			// CHECK14-NEXT: [[CONV1:%.]] = bitcast i64 [[SIVAR_ADDR]] to i32*
	// CHECK14-NEXT: [[TMP3:%.]] = load i32, i32 [[CONV]], align 4			// CHECK14-NEXT: [[TMP3:%.]] = load i32, i32 [[CONV]], align 8
	// CHECK14-NEXT: [[CONV2:%.]] = bitcast i64 [[T_VAR_CASTED]] to i32*			// CHECK14-NEXT: [[CONV2:%.]] = bitcast i64 [[T_VAR_CASTED]] to i32*
	// CHECK14-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4			// CHECK14-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
	// CHECK14-NEXT: [[TMP4:%.]] = load i64, i64 [[T_VAR_CASTED]], align 8			// CHECK14-NEXT: [[TMP4:%.]] = load i64, i64 [[T_VAR_CASTED]], align 8
	// CHECK14-NEXT: [[TMP5:%.]] = load i32, i32 [[CONV1]], align 4			// CHECK14-NEXT: [[TMP5:%.]] = load i32, i32 [[CONV1]], align 8
	// CHECK14-NEXT: [[CONV3:%.]] = bitcast i64 [[SIVAR_CASTED]] to i32*			// CHECK14-NEXT: [[CONV3:%.]] = bitcast i64 [[SIVAR_CASTED]] to i32*
	// CHECK14-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4			// CHECK14-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4
	// CHECK14-NEXT: [[TMP6:%.]] = load i64, i64 [[SIVAR_CASTED]], align 8			// CHECK14-NEXT: [[TMP6:%.]] = load i64, i64 [[SIVAR_CASTED]], align 8
	// CHECK14-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 5, void (i32, i32, ...)* bitcast (void (i32, i32, [2 x i32], i64, [2 x %struct.S], %struct.S, i64) @.omp_outlined. to void (i32, i32, ...)), [2 x i32] [[TMP0]], i64 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP2]], i64 [[TMP6]])			// CHECK14-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 5, void (i32, i32, ...)* bitcast (void (i32, i32, [2 x i32], i64, [2 x %struct.S], %struct.S, i64) @.omp_outlined. to void (i32, i32, ...)), [2 x i32] [[TMP0]], i64 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP2]], i64 [[TMP6]])
	// CHECK14-NEXT: ret void			// CHECK14-NEXT: ret void
	//			//
	//			//
	// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined.			// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined.
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	// CHECK14-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]			// CHECK14-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]
	// CHECK14: omp.inner.for.cond.cleanup:			// CHECK14: omp.inner.for.cond.cleanup:
	// CHECK14-NEXT: br label [[OMP_INNER_FOR_END:%.*]]			// CHECK14-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
	// CHECK14: omp.inner.for.body:			// CHECK14: omp.inner.for.body:
	// CHECK14-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !6			// CHECK14-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !6
	// CHECK14-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64			// CHECK14-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64
	// CHECK14-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !6			// CHECK14-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !6
	// CHECK14-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64			// CHECK14-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
	// CHECK14-NEXT: [[TMP18:%.]] = load i32, i32 [[CONV]], align 4, !llvm.access.group !6			// CHECK14-NEXT: [[TMP18:%.]] = load i32, i32 [[CONV]], align 8, !llvm.access.group !6
	// CHECK14-NEXT: [[CONV8:%.]] = bitcast i64 [[T_VAR_CASTED]] to i32*			// CHECK14-NEXT: [[CONV8:%.]] = bitcast i64 [[T_VAR_CASTED]] to i32*
	// CHECK14-NEXT: store i32 [[TMP18]], i32* [[CONV8]], align 4, !llvm.access.group !6			// CHECK14-NEXT: store i32 [[TMP18]], i32* [[CONV8]], align 4, !llvm.access.group !6
	// CHECK14-NEXT: [[TMP19:%.]] = load i64, i64 [[T_VAR_CASTED]], align 8, !llvm.access.group !6			// CHECK14-NEXT: [[TMP19:%.]] = load i64, i64 [[T_VAR_CASTED]], align 8, !llvm.access.group !6
	// CHECK14-NEXT: [[TMP20:%.]] = load i32, i32 [[CONV1]], align 4, !llvm.access.group !6			// CHECK14-NEXT: [[TMP20:%.]] = load i32, i32 [[CONV1]], align 8, !llvm.access.group !6
	// CHECK14-NEXT: [[CONV9:%.]] = bitcast i64 [[SIVAR_CASTED]] to i32*			// CHECK14-NEXT: [[CONV9:%.]] = bitcast i64 [[SIVAR_CASTED]] to i32*
	// CHECK14-NEXT: store i32 [[TMP20]], i32* [[CONV9]], align 4, !llvm.access.group !6			// CHECK14-NEXT: store i32 [[TMP20]], i32* [[CONV9]], align 4, !llvm.access.group !6
	// CHECK14-NEXT: [[TMP21:%.]] = load i64, i64 [[SIVAR_CASTED]], align 8, !llvm.access.group !6			// CHECK14-NEXT: [[TMP21:%.]] = load i64, i64 [[SIVAR_CASTED]], align 8, !llvm.access.group !6
	// CHECK14-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, [2 x i32], i64, [2 x %struct.S], %struct.S, i64) @.omp_outlined..1 to void (i32, i32, ...)), i64 [[TMP15]], i64 [[TMP17]], [2 x i32] [[VEC2]], i64 [[TMP19]], [2 x %struct.S]* [[S_ARR3]], %struct.S* [[VAR5]], i64 [[TMP21]]), !llvm.access.group !6			// CHECK14-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, [2 x i32], i64, [2 x %struct.S], %struct.S, i64) @.omp_outlined..1 to void (i32, i32, ...)), i64 [[TMP15]], i64 [[TMP17]], [2 x i32] [[VEC2]], i64 [[TMP19]], [2 x %struct.S]* [[S_ARR3]], %struct.S* [[VAR5]], i64 [[TMP21]]), !llvm.access.group !6
	// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK14: omp.inner.for.inc:			// CHECK14: omp.inner.for.inc:
	// CHECK14-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !6			// CHECK14-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !6
	// CHECK14-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !6			// CHECK14-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !6
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	// CHECK14-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]			// CHECK14-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]
	// CHECK14: omp.inner.for.cond.cleanup:			// CHECK14: omp.inner.for.cond.cleanup:
	// CHECK14-NEXT: br label [[OMP_INNER_FOR_END:%.*]]			// CHECK14-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
	// CHECK14: omp.inner.for.body:			// CHECK14: omp.inner.for.body:
	// CHECK14-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10			// CHECK14-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK14-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1			// CHECK14-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1
	// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK14-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10			// CHECK14-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10
	// CHECK14-NEXT: [[TMP17:%.]] = load i32, i32 [[CONV]], align 4, !llvm.access.group !10			// CHECK14-NEXT: [[TMP17:%.]] = load i32, i32 [[CONV]], align 8, !llvm.access.group !10
	// CHECK14-NEXT: [[TMP18:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !10			// CHECK14-NEXT: [[TMP18:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !10
	// CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP18]] to i64			// CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP18]] to i64
	// CHECK14-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC4]], i64 0, i64 [[IDXPROM]]			// CHECK14-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC4]], i64 0, i64 [[IDXPROM]]
	// CHECK14-NEXT: store i32 [[TMP17]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !10			// CHECK14-NEXT: store i32 [[TMP17]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !10
	// CHECK14-NEXT: [[TMP19:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !10			// CHECK14-NEXT: [[TMP19:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !10
	// CHECK14-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP19]] to i64			// CHECK14-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP19]] to i64
	// CHECK14-NEXT: [[ARRAYIDX11:%.]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S] [[S_ARR5]], i64 0, i64 [[IDXPROM10]]			// CHECK14-NEXT: [[ARRAYIDX11:%.]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S] [[S_ARR5]], i64 0, i64 [[IDXPROM10]]
	// CHECK14-NEXT: [[TMP20:%.]] = bitcast %struct.S [[ARRAYIDX11]] to i8*			// CHECK14-NEXT: [[TMP20:%.]] = bitcast %struct.S [[ARRAYIDX11]] to i8*
	// CHECK14-NEXT: [[TMP21:%.]] = bitcast %struct.S [[VAR7]] to i8*			// CHECK14-NEXT: [[TMP21:%.]] = bitcast %struct.S [[VAR7]] to i8*
	// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i64 4, i1 false), !llvm.access.group !10			// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i64 4, i1 false), !llvm.access.group !10
	// CHECK14-NEXT: [[TMP22:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !10			// CHECK14-NEXT: [[TMP22:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !10
	// CHECK14-NEXT: [[TMP23:%.]] = load i32, i32 [[CONV1]], align 4, !llvm.access.group !10			// CHECK14-NEXT: [[TMP23:%.]] = load i32, i32 [[CONV1]], align 8, !llvm.access.group !10
	// CHECK14-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP23]], [[TMP22]]			// CHECK14-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP23]], [[TMP22]]
	// CHECK14-NEXT: store i32 [[ADD12]], i32* [[CONV1]], align 4, !llvm.access.group !10			// CHECK14-NEXT: store i32 [[ADD12]], i32* [[CONV1]], align 8, !llvm.access.group !10
	// CHECK14-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK14-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK14: omp.body.continue:			// CHECK14: omp.body.continue:
	// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK14: omp.inner.for.inc:			// CHECK14: omp.inner.for.inc:
	// CHECK14-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10			// CHECK14-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK14-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP24]], 1			// CHECK14-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP24]], 1
	// CHECK14-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10			// CHECK14-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]			// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]
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	// CHECK14-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8			// CHECK14-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8
	// CHECK14-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8			// CHECK14-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
	// CHECK14-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8			// CHECK14-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8
	// CHECK14-NEXT: [[TMP0:%.]] = load [2 x i32], [2 x i32]** [[VEC_ADDR]], align 8			// CHECK14-NEXT: [[TMP0:%.]] = load [2 x i32], [2 x i32]** [[VEC_ADDR]], align 8
	// CHECK14-NEXT: [[CONV:%.]] = bitcast i64 [[T_VAR_ADDR]] to i32*			// CHECK14-NEXT: [[CONV:%.]] = bitcast i64 [[T_VAR_ADDR]] to i32*
	// CHECK14-NEXT: [[TMP1:%.]] = load [2 x %struct.S.0], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8			// CHECK14-NEXT: [[TMP1:%.]] = load [2 x %struct.S.0], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
	// CHECK14-NEXT: [[TMP2:%.]] = load %struct.S.0, %struct.S.0** [[VAR_ADDR]], align 8			// CHECK14-NEXT: [[TMP2:%.]] = load %struct.S.0, %struct.S.0** [[VAR_ADDR]], align 8
	// CHECK14-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8			// CHECK14-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8
	// CHECK14-NEXT: [[TMP3:%.]] = load i32, i32 [[CONV]], align 4			// CHECK14-NEXT: [[TMP3:%.]] = load i32, i32 [[CONV]], align 8
	// CHECK14-NEXT: [[CONV1:%.]] = bitcast i64 [[T_VAR_CASTED]] to i32*			// CHECK14-NEXT: [[CONV1:%.]] = bitcast i64 [[T_VAR_CASTED]] to i32*
	// CHECK14-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4			// CHECK14-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4
	// CHECK14-NEXT: [[TMP4:%.]] = load i64, i64 [[T_VAR_CASTED]], align 8			// CHECK14-NEXT: [[TMP4:%.]] = load i64, i64 [[T_VAR_CASTED]], align 8
	// CHECK14-NEXT: [[TMP5:%.]] = load %struct.S.0, %struct.S.0** [[TMP]], align 8			// CHECK14-NEXT: [[TMP5:%.]] = load %struct.S.0, %struct.S.0** [[TMP]], align 8
	// CHECK14-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32, i32, ...)* bitcast (void (i32, i32, [2 x i32], i64, [2 x %struct.S.0], %struct.S.0) @.omp_outlined..2 to void (i32, i32, ...)), [2 x i32] [[TMP0]], i64 [[TMP4]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP5]])			// CHECK14-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32, i32, ...)* bitcast (void (i32, i32, [2 x i32], i64, [2 x %struct.S.0], %struct.S.0) @.omp_outlined..2 to void (i32, i32, ...)), [2 x i32] [[TMP0]], i64 [[TMP4]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP5]])
	// CHECK14-NEXT: ret void			// CHECK14-NEXT: ret void
	//			//
	//			//
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	// CHECK14-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]			// CHECK14-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]
	// CHECK14: omp.inner.for.cond.cleanup:			// CHECK14: omp.inner.for.cond.cleanup:
	// CHECK14-NEXT: br label [[OMP_INNER_FOR_END:%.*]]			// CHECK14-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
	// CHECK14: omp.inner.for.body:			// CHECK14: omp.inner.for.body:
	// CHECK14-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !15			// CHECK14-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !15
	// CHECK14-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64			// CHECK14-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64
	// CHECK14-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15			// CHECK14-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15
	// CHECK14-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64			// CHECK14-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
	// CHECK14-NEXT: [[TMP19:%.]] = load i32, i32 [[CONV]], align 4, !llvm.access.group !15			// CHECK14-NEXT: [[TMP19:%.]] = load i32, i32 [[CONV]], align 8, !llvm.access.group !15
	// CHECK14-NEXT: [[CONV9:%.]] = bitcast i64 [[T_VAR_CASTED]] to i32*			// CHECK14-NEXT: [[CONV9:%.]] = bitcast i64 [[T_VAR_CASTED]] to i32*
	// CHECK14-NEXT: store i32 [[TMP19]], i32* [[CONV9]], align 4, !llvm.access.group !15			// CHECK14-NEXT: store i32 [[TMP19]], i32* [[CONV9]], align 4, !llvm.access.group !15
	// CHECK14-NEXT: [[TMP20:%.]] = load i64, i64 [[T_VAR_CASTED]], align 8, !llvm.access.group !15			// CHECK14-NEXT: [[TMP20:%.]] = load i64, i64 [[T_VAR_CASTED]], align 8, !llvm.access.group !15
	// CHECK14-NEXT: [[TMP21:%.]] = load %struct.S.0, %struct.S.0** [[_TMP7]], align 8, !llvm.access.group !15			// CHECK14-NEXT: [[TMP21:%.]] = load %struct.S.0, %struct.S.0** [[_TMP7]], align 8, !llvm.access.group !15
	// CHECK14-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, [2 x i32], i64, [2 x %struct.S.0], %struct.S.0) @.omp_outlined..3 to void (i32, i32, ...)), i64 [[TMP16]], i64 [[TMP18]], [2 x i32] [[VEC2]], i64 [[TMP20]], [2 x %struct.S.0]* [[S_ARR3]], %struct.S.0* [[TMP21]]), !llvm.access.group !15			// CHECK14-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, [2 x i32], i64, [2 x %struct.S.0], %struct.S.0) @.omp_outlined..3 to void (i32, i32, ...)), i64 [[TMP16]], i64 [[TMP18]], [2 x i32] [[VEC2]], i64 [[TMP20]], [2 x %struct.S.0]* [[S_ARR3]], %struct.S.0* [[TMP21]]), !llvm.access.group !15
	// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK14: omp.inner.for.inc:			// CHECK14: omp.inner.for.inc:
	// CHECK14-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15			// CHECK14-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15
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	// CHECK14-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]			// CHECK14-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]
	// CHECK14: omp.inner.for.cond.cleanup:			// CHECK14: omp.inner.for.cond.cleanup:
	// CHECK14-NEXT: br label [[OMP_INNER_FOR_END:%.*]]			// CHECK14-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
	// CHECK14: omp.inner.for.body:			// CHECK14: omp.inner.for.body:
	// CHECK14-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18			// CHECK14-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK14-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1			// CHECK14-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1
	// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK14-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !18			// CHECK14-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !18
	// CHECK14-NEXT: [[TMP18:%.]] = load i32, i32 [[CONV]], align 4, !llvm.access.group !18			// CHECK14-NEXT: [[TMP18:%.]] = load i32, i32 [[CONV]], align 8, !llvm.access.group !18
	// CHECK14-NEXT: [[TMP19:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !18			// CHECK14-NEXT: [[TMP19:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !18
	// CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64			// CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64
	// CHECK14-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC4]], i64 0, i64 [[IDXPROM]]			// CHECK14-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC4]], i64 0, i64 [[IDXPROM]]
	// CHECK14-NEXT: store i32 [[TMP18]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !18			// CHECK14-NEXT: store i32 [[TMP18]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !18
	// CHECK14-NEXT: [[TMP20:%.]] = load %struct.S.0, %struct.S.0** [[_TMP9]], align 8, !llvm.access.group !18			// CHECK14-NEXT: [[TMP20:%.]] = load %struct.S.0, %struct.S.0** [[_TMP9]], align 8, !llvm.access.group !18
	// CHECK14-NEXT: [[TMP21:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !18			// CHECK14-NEXT: [[TMP21:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !18
	// CHECK14-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP21]] to i64			// CHECK14-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP21]] to i64
	// CHECK14-NEXT: [[ARRAYIDX12:%.]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0] [[S_ARR5]], i64 0, i64 [[IDXPROM11]]			// CHECK14-NEXT: [[ARRAYIDX12:%.]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0] [[S_ARR5]], i64 0, i64 [[IDXPROM11]]
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	// CHECK17-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8			// CHECK17-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8
	// CHECK17-NEXT: store i64 [[G]], i64* [[G_ADDR]], align 8			// CHECK17-NEXT: store i64 [[G]], i64* [[G_ADDR]], align 8
	// CHECK17-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8			// CHECK17-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8
	// CHECK17-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8			// CHECK17-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8
	// CHECK17-NEXT: [[CONV:%.]] = bitcast i64 [[G_ADDR]] to i32*			// CHECK17-NEXT: [[CONV:%.]] = bitcast i64 [[G_ADDR]] to i32*
	// CHECK17-NEXT: [[CONV1:%.]] = bitcast i64 [[G1_ADDR]] to i32*			// CHECK17-NEXT: [[CONV1:%.]] = bitcast i64 [[G1_ADDR]] to i32*
	// CHECK17-NEXT: [[CONV2:%.]] = bitcast i64 [[SIVAR_ADDR]] to i32*			// CHECK17-NEXT: [[CONV2:%.]] = bitcast i64 [[SIVAR_ADDR]] to i32*
	// CHECK17-NEXT: store i32* [[CONV1]], i32** [[TMP]], align 8			// CHECK17-NEXT: store i32* [[CONV1]], i32** [[TMP]], align 8
	// CHECK17-NEXT: [[TMP0:%.]] = load i32, i32 [[CONV]], align 4			// CHECK17-NEXT: [[TMP0:%.]] = load i32, i32 [[CONV]], align 8
	// CHECK17-NEXT: [[CONV3:%.]] = bitcast i64 [[G_CASTED]] to i32*			// CHECK17-NEXT: [[CONV3:%.]] = bitcast i64 [[G_CASTED]] to i32*
	// CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV3]], align 4			// CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV3]], align 4
	// CHECK17-NEXT: [[TMP1:%.]] = load i64, i64 [[G_CASTED]], align 8			// CHECK17-NEXT: [[TMP1:%.]] = load i64, i64 [[G_CASTED]], align 8
	// CHECK17-NEXT: [[TMP2:%.]] = load i32, i32** [[TMP]], align 8			// CHECK17-NEXT: [[TMP2:%.]] = load i32, i32** [[TMP]], align 8
	// CHECK17-NEXT: [[TMP3:%.]] = load volatile i32, i32 [[TMP2]], align 4			// CHECK17-NEXT: [[TMP3:%.]] = load volatile i32, i32 [[TMP2]], align 4
	// CHECK17-NEXT: [[CONV4:%.]] = bitcast i64 [[G1_CASTED]] to i32*			// CHECK17-NEXT: [[CONV4:%.]] = bitcast i64 [[G1_CASTED]] to i32*
	// CHECK17-NEXT: store i32 [[TMP3]], i32* [[CONV4]], align 4			// CHECK17-NEXT: store i32 [[TMP3]], i32* [[CONV4]], align 4
	// CHECK17-NEXT: [[TMP4:%.]] = load i64, i64 [[G1_CASTED]], align 8			// CHECK17-NEXT: [[TMP4:%.]] = load i64, i64 [[G1_CASTED]], align 8
	// CHECK17-NEXT: [[TMP5:%.]] = load i32, i32 [[CONV2]], align 4			// CHECK17-NEXT: [[TMP5:%.]] = load i32, i32 [[CONV2]], align 8
	// CHECK17-NEXT: [[CONV5:%.]] = bitcast i64 [[SIVAR_CASTED]] to i32*			// CHECK17-NEXT: [[CONV5:%.]] = bitcast i64 [[SIVAR_CASTED]] to i32*
	// CHECK17-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4			// CHECK17-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4
	// CHECK17-NEXT: [[TMP6:%.]] = load i64, i64 [[SIVAR_CASTED]], align 8			// CHECK17-NEXT: [[TMP6:%.]] = load i64, i64 [[SIVAR_CASTED]], align 8
	// CHECK17-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i64)* @.omp_outlined. to void (i32, i32, ...)*), i64 [[TMP1]], i64 [[TMP4]], i64 [[TMP6]])			// CHECK17-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i64)* @.omp_outlined. to void (i32, i32, ...)*), i64 [[TMP1]], i64 [[TMP4]], i64 [[TMP6]])
	// CHECK17-NEXT: ret void			// CHECK17-NEXT: ret void
	//			//
	//			//
	// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined.			// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined.
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	// CHECK17-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5			// CHECK17-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5
	// CHECK17-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK17-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK17-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK17-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK17: omp.inner.for.body:			// CHECK17: omp.inner.for.body:
	// CHECK17-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !5			// CHECK17-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !5
	// CHECK17-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64			// CHECK17-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
	// CHECK17-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5			// CHECK17-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5
	// CHECK17-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK17-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK17-NEXT: [[TMP11:%.]] = load i32, i32 [[CONV]], align 4, !llvm.access.group !5			// CHECK17-NEXT: [[TMP11:%.]] = load i32, i32 [[CONV]], align 8, !llvm.access.group !5
	// CHECK17-NEXT: [[CONV5:%.]] = bitcast i64 [[G_CASTED]] to i32*			// CHECK17-NEXT: [[CONV5:%.]] = bitcast i64 [[G_CASTED]] to i32*
	// CHECK17-NEXT: store i32 [[TMP11]], i32* [[CONV5]], align 4, !llvm.access.group !5			// CHECK17-NEXT: store i32 [[TMP11]], i32* [[CONV5]], align 4, !llvm.access.group !5
	// CHECK17-NEXT: [[TMP12:%.]] = load i64, i64 [[G_CASTED]], align 8, !llvm.access.group !5			// CHECK17-NEXT: [[TMP12:%.]] = load i64, i64 [[G_CASTED]], align 8, !llvm.access.group !5
	// CHECK17-NEXT: [[TMP13:%.]] = load i32, i32** [[TMP]], align 8, !llvm.access.group !5			// CHECK17-NEXT: [[TMP13:%.]] = load i32, i32** [[TMP]], align 8, !llvm.access.group !5
	// CHECK17-NEXT: [[TMP14:%.]] = load volatile i32, i32 [[TMP13]], align 4, !llvm.access.group !5			// CHECK17-NEXT: [[TMP14:%.]] = load volatile i32, i32 [[TMP13]], align 4, !llvm.access.group !5
	// CHECK17-NEXT: [[CONV6:%.]] = bitcast i64 [[G1_CASTED]] to i32*			// CHECK17-NEXT: [[CONV6:%.]] = bitcast i64 [[G1_CASTED]] to i32*
	// CHECK17-NEXT: store i32 [[TMP14]], i32* [[CONV6]], align 4, !llvm.access.group !5			// CHECK17-NEXT: store i32 [[TMP14]], i32* [[CONV6]], align 4, !llvm.access.group !5
	// CHECK17-NEXT: [[TMP15:%.]] = load i64, i64 [[G1_CASTED]], align 8, !llvm.access.group !5			// CHECK17-NEXT: [[TMP15:%.]] = load i64, i64 [[G1_CASTED]], align 8, !llvm.access.group !5
	// CHECK17-NEXT: [[TMP16:%.]] = load i32, i32 [[CONV2]], align 4, !llvm.access.group !5			// CHECK17-NEXT: [[TMP16:%.]] = load i32, i32 [[CONV2]], align 8, !llvm.access.group !5
	// CHECK17-NEXT: [[CONV7:%.]] = bitcast i64 [[SIVAR_CASTED]] to i32*			// CHECK17-NEXT: [[CONV7:%.]] = bitcast i64 [[SIVAR_CASTED]] to i32*
	// CHECK17-NEXT: store i32 [[TMP16]], i32* [[CONV7]], align 4, !llvm.access.group !5			// CHECK17-NEXT: store i32 [[TMP16]], i32* [[CONV7]], align 4, !llvm.access.group !5
	// CHECK17-NEXT: [[TMP17:%.]] = load i64, i64 [[SIVAR_CASTED]], align 8, !llvm.access.group !5			// CHECK17-NEXT: [[TMP17:%.]] = load i64, i64 [[SIVAR_CASTED]], align 8, !llvm.access.group !5
	// CHECK17-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i64, i64, i64)* @.omp_outlined..1 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]], i64 [[TMP12]], i64 [[TMP15]], i64 [[TMP17]]), !llvm.access.group !5			// CHECK17-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i64, i64, i64)* @.omp_outlined..1 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]], i64 [[TMP12]], i64 [[TMP15]], i64 [[TMP17]]), !llvm.access.group !5
	// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK17: omp.inner.for.inc:			// CHECK17: omp.inner.for.inc:
	// CHECK17-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5			// CHECK17-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK17-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !5			// CHECK17-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !5
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	// CHECK17-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !9			// CHECK17-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !9
	// CHECK17-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK17-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK17-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK17-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK17: omp.inner.for.body:			// CHECK17: omp.inner.for.body:
	// CHECK17-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9			// CHECK17-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK17-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9			// CHECK17-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9
	// CHECK17-NEXT: store i32 1, i32* [[CONV]], align 4, !llvm.access.group !9			// CHECK17-NEXT: store i32 1, i32* [[CONV]], align 8, !llvm.access.group !9
	// CHECK17-NEXT: [[TMP10:%.]] = load i32, i32** [[TMP]], align 8, !llvm.access.group !9			// CHECK17-NEXT: [[TMP10:%.]] = load i32, i32** [[TMP]], align 8, !llvm.access.group !9
	// CHECK17-NEXT: store volatile i32 1, i32* [[TMP10]], align 4, !llvm.access.group !9			// CHECK17-NEXT: store volatile i32 1, i32* [[TMP10]], align 4, !llvm.access.group !9
	// CHECK17-NEXT: store i32 2, i32* [[CONV2]], align 4, !llvm.access.group !9			// CHECK17-NEXT: store i32 2, i32* [[CONV2]], align 8, !llvm.access.group !9
	// CHECK17-NEXT: [[TMP11:%.]] = getelementptr inbounds [[CLASS_ANON]], %class.anon [[REF_TMP]], i32 0, i32 0			// CHECK17-NEXT: [[TMP11:%.]] = getelementptr inbounds [[CLASS_ANON]], %class.anon [[REF_TMP]], i32 0, i32 0
	// CHECK17-NEXT: store i32* [[CONV]], i32** [[TMP11]], align 8, !llvm.access.group !9			// CHECK17-NEXT: store i32* [[CONV]], i32** [[TMP11]], align 8, !llvm.access.group !9
	// CHECK17-NEXT: [[TMP12:%.]] = getelementptr inbounds [[CLASS_ANON]], %class.anon [[REF_TMP]], i32 0, i32 1			// CHECK17-NEXT: [[TMP12:%.]] = getelementptr inbounds [[CLASS_ANON]], %class.anon [[REF_TMP]], i32 0, i32 1
	// CHECK17-NEXT: [[TMP13:%.]] = load i32, i32** [[TMP]], align 8, !llvm.access.group !9			// CHECK17-NEXT: [[TMP13:%.]] = load i32, i32** [[TMP]], align 8, !llvm.access.group !9
	// CHECK17-NEXT: store i32* [[TMP13]], i32** [[TMP12]], align 8, !llvm.access.group !9			// CHECK17-NEXT: store i32* [[TMP13]], i32** [[TMP12]], align 8, !llvm.access.group !9
	// CHECK17-NEXT: [[TMP14:%.]] = getelementptr inbounds [[CLASS_ANON]], %class.anon [[REF_TMP]], i32 0, i32 2			// CHECK17-NEXT: [[TMP14:%.]] = getelementptr inbounds [[CLASS_ANON]], %class.anon [[REF_TMP]], i32 0, i32 2
	// CHECK17-NEXT: store i32* [[CONV2]], i32** [[TMP14]], align 8, !llvm.access.group !9			// CHECK17-NEXT: store i32* [[CONV2]], i32** [[TMP14]], align 8, !llvm.access.group !9
	// CHECK17-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon* nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR3:[0-9]+]], !llvm.access.group !9			// CHECK17-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon* nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR3:[0-9]+]], !llvm.access.group !9
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clang/test/OpenMP/target_teams_distribute_parallel_for_simd_if_codegen.cpp

This file is larger than 256 KB, so syntax highlighting is disabled by default.

	Show First 20 Lines • Show All 151 Lines • ▼ Show 20 Lines
	//			//
	// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l47			// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l47
	// CHECK1-SAME: (i64 [[ARG:%.*]]) #[[ATTR1:[0-9]+]] {			// CHECK1-SAME: (i64 [[ARG:%.*]]) #[[ATTR1:[0-9]+]] {
	// CHECK1-NEXT: entry:			// CHECK1-NEXT: entry:
	// CHECK1-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8			// CHECK1-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8
	// CHECK1-NEXT: [[ARG_CASTED:%.*]] = alloca i64, align 8			// CHECK1-NEXT: [[ARG_CASTED:%.*]] = alloca i64, align 8
	// CHECK1-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8			// CHECK1-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8
	// CHECK1-NEXT: [[CONV:%.]] = bitcast i64 [[ARG_ADDR]] to i32*			// CHECK1-NEXT: [[CONV:%.]] = bitcast i64 [[ARG_ADDR]] to i32*
	// CHECK1-NEXT: [[TMP0:%.]] = load i32, i32 [[CONV]], align 4			// CHECK1-NEXT: [[TMP0:%.]] = load i32, i32 [[CONV]], align 8
	// CHECK1-NEXT: [[CONV1:%.]] = bitcast i64 [[ARG_CASTED]] to i32*			// CHECK1-NEXT: [[CONV1:%.]] = bitcast i64 [[ARG_CASTED]] to i32*
	// CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4			// CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
	// CHECK1-NEXT: [[TMP1:%.]] = load i64, i64 [[ARG_CASTED]], align 8			// CHECK1-NEXT: [[TMP1:%.]] = load i64, i64 [[ARG_CASTED]], align 8
	// CHECK1-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32, i32, ...)* bitcast (void (i32, i32, i64)* @.omp_outlined. to void (i32, i32, ...)*), i64 [[TMP1]])			// CHECK1-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32, i32, ...)* bitcast (void (i32, i32, i64)* @.omp_outlined. to void (i32, i32, ...)*), i64 [[TMP1]])
	// CHECK1-NEXT: ret void			// CHECK1-NEXT: ret void
	//			//
	//			//
	// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined.			// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined.
	Show All 40 Lines
	// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !9			// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !9
	// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK1: omp.inner.for.body:			// CHECK1: omp.inner.for.body:
	// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !9			// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !9
	// CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64			// CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
	// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !9			// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !9
	// CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[CONV]], align 4, !llvm.access.group !9			// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[CONV]], align 8, !llvm.access.group !9
	// CHECK1-NEXT: [[CONV2:%.]] = bitcast i64 [[ARG_CASTED]] to i32*			// CHECK1-NEXT: [[CONV2:%.]] = bitcast i64 [[ARG_CASTED]] to i32*
	// CHECK1-NEXT: store i32 [[TMP11]], i32* [[CONV2]], align 4, !llvm.access.group !9			// CHECK1-NEXT: store i32 [[TMP11]], i32* [[CONV2]], align 4, !llvm.access.group !9
	// CHECK1-NEXT: [[TMP12:%.]] = load i64, i64 [[ARG_CASTED]], align 8, !llvm.access.group !9			// CHECK1-NEXT: [[TMP12:%.]] = load i64, i64 [[ARG_CASTED]], align 8, !llvm.access.group !9
	// CHECK1-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i64)* @.omp_outlined..1 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]], i64 [[TMP12]]), !llvm.access.group !9			// CHECK1-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i64)* @.omp_outlined..1 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]], i64 [[TMP12]]), !llvm.access.group !9
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK1: omp.inner.for.inc:			// CHECK1: omp.inner.for.inc:
	// CHECK1-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9			// CHECK1-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK1-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !9			// CHECK1-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !9
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	// CHECK1-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !13			// CHECK1-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !13
	// CHECK1-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK1-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK1-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK1-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK1: omp.inner.for.body:			// CHECK1: omp.inner.for.body:
	// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13			// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !13			// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !13
	// CHECK1-NEXT: store i32 0, i32* [[CONV]], align 4, !llvm.access.group !13			// CHECK1-NEXT: store i32 0, i32* [[CONV]], align 8, !llvm.access.group !13
	// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK1: omp.body.continue:			// CHECK1: omp.body.continue:
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK1: omp.inner.for.inc:			// CHECK1: omp.inner.for.inc:
	// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13			// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK1-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13			// CHECK1-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]]
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	//			//
	// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92			// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92
	// CHECK1-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {			// CHECK1-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
	// CHECK1-NEXT: entry:			// CHECK1-NEXT: entry:
	// CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8			// CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
	// CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8			// CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
	// CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8			// CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
	// CHECK1-NEXT: [[CONV:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__ADDR]] to i8*			// CHECK1-NEXT: [[CONV:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__ADDR]] to i8*
	// CHECK1-NEXT: [[TMP0:%.]] = load i8, i8 [[CONV]], align 1			// CHECK1-NEXT: [[TMP0:%.]] = load i8, i8 [[CONV]], align 8
	// CHECK1-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP0]] to i1			// CHECK1-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP0]] to i1
	// CHECK1-NEXT: [[CONV1:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED]] to i8*			// CHECK1-NEXT: [[CONV1:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED]] to i8*
	// CHECK1-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8			// CHECK1-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
	// CHECK1-NEXT: store i8 [[FROMBOOL]], i8* [[CONV1]], align 1			// CHECK1-NEXT: store i8 [[FROMBOOL]], i8* [[CONV1]], align 1
	// CHECK1-NEXT: [[TMP1:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED]], align 8			// CHECK1-NEXT: [[TMP1:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED]], align 8
	// CHECK1-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32, i32, ...)* bitcast (void (i32, i32, i64)* @.omp_outlined..8 to void (i32, i32, ...)*), i64 [[TMP1]])			// CHECK1-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32, i32, ...)* bitcast (void (i32, i32, i64)* @.omp_outlined..8 to void (i32, i32, ...)*), i64 [[TMP1]])
	// CHECK1-NEXT: ret void			// CHECK1-NEXT: ret void
	//			//
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	// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !36			// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !36
	// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK1: omp.inner.for.body:			// CHECK1: omp.inner.for.body:
	// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !36			// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !36
	// CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64			// CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
	// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !36			// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !36
	// CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK1-NEXT: [[TMP11:%.]] = load i8, i8 [[CONV]], align 1, !llvm.access.group !36			// CHECK1-NEXT: [[TMP11:%.]] = load i8, i8 [[CONV]], align 8, !llvm.access.group !36
	// CHECK1-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1			// CHECK1-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
	// CHECK1-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE:%.]]			// CHECK1-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE:%.]]
	// CHECK1: omp_if.then:			// CHECK1: omp_if.then:
	// CHECK1-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..9 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !36			// CHECK1-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..9 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !36
	// CHECK1-NEXT: br label [[OMP_IF_END:%.*]]			// CHECK1-NEXT: br label [[OMP_IF_END:%.*]]
	// CHECK1: omp_if.else:			// CHECK1: omp_if.else:
	// CHECK1-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !36			// CHECK1-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !36
	// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !36			// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !36
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	//			//
	// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l70			// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l70
	// CHECK1-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {			// CHECK1-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
	// CHECK1-NEXT: entry:			// CHECK1-NEXT: entry:
	// CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8			// CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
	// CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8			// CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
	// CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8			// CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
	// CHECK1-NEXT: [[CONV:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__ADDR]] to i8*			// CHECK1-NEXT: [[CONV:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__ADDR]] to i8*
	// CHECK1-NEXT: [[TMP0:%.]] = load i8, i8 [[CONV]], align 1			// CHECK1-NEXT: [[TMP0:%.]] = load i8, i8 [[CONV]], align 8
	// CHECK1-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP0]] to i1			// CHECK1-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP0]] to i1
	// CHECK1-NEXT: [[CONV1:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED]] to i8*			// CHECK1-NEXT: [[CONV1:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED]] to i8*
	// CHECK1-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8			// CHECK1-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
	// CHECK1-NEXT: store i8 [[FROMBOOL]], i8* [[CONV1]], align 1			// CHECK1-NEXT: store i8 [[FROMBOOL]], i8* [[CONV1]], align 1
	// CHECK1-NEXT: [[TMP1:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED]], align 8			// CHECK1-NEXT: [[TMP1:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED]], align 8
	// CHECK1-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32, i32, ...)* bitcast (void (i32, i32, i64)* @.omp_outlined..16 to void (i32, i32, ...)*), i64 [[TMP1]])			// CHECK1-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32, i32, ...)* bitcast (void (i32, i32, i64)* @.omp_outlined..16 to void (i32, i32, ...)*), i64 [[TMP1]])
	// CHECK1-NEXT: ret void			// CHECK1-NEXT: ret void
	//			//
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	// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !54			// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !54
	// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK1: omp.inner.for.body:			// CHECK1: omp.inner.for.body:
	// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !54			// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !54
	// CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64			// CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
	// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !54			// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !54
	// CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK1-NEXT: [[TMP11:%.]] = load i8, i8 [[CONV]], align 1, !llvm.access.group !54			// CHECK1-NEXT: [[TMP11:%.]] = load i8, i8 [[CONV]], align 8, !llvm.access.group !54
	// CHECK1-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1			// CHECK1-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
	// CHECK1-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE:%.]]			// CHECK1-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE:%.]]
	// CHECK1: omp_if.then:			// CHECK1: omp_if.then:
	// CHECK1-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..17 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !54			// CHECK1-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..17 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !54
	// CHECK1-NEXT: br label [[OMP_IF_END:%.*]]			// CHECK1-NEXT: br label [[OMP_IF_END:%.*]]
	// CHECK1: omp_if.else:			// CHECK1: omp_if.else:
	// CHECK1-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !54			// CHECK1-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !54
	// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !54			// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !54
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	//			//
	// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l47			// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l47
	// CHECK2-SAME: (i64 [[ARG:%.*]]) #[[ATTR1:[0-9]+]] {			// CHECK2-SAME: (i64 [[ARG:%.*]]) #[[ATTR1:[0-9]+]] {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	// CHECK2-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8			// CHECK2-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8
	// CHECK2-NEXT: [[ARG_CASTED:%.*]] = alloca i64, align 8			// CHECK2-NEXT: [[ARG_CASTED:%.*]] = alloca i64, align 8
	// CHECK2-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8			// CHECK2-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8
	// CHECK2-NEXT: [[CONV:%.]] = bitcast i64 [[ARG_ADDR]] to i32*			// CHECK2-NEXT: [[CONV:%.]] = bitcast i64 [[ARG_ADDR]] to i32*
	// CHECK2-NEXT: [[TMP0:%.]] = load i32, i32 [[CONV]], align 4			// CHECK2-NEXT: [[TMP0:%.]] = load i32, i32 [[CONV]], align 8
	// CHECK2-NEXT: [[CONV1:%.]] = bitcast i64 [[ARG_CASTED]] to i32*			// CHECK2-NEXT: [[CONV1:%.]] = bitcast i64 [[ARG_CASTED]] to i32*
	// CHECK2-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4			// CHECK2-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
	// CHECK2-NEXT: [[TMP1:%.]] = load i64, i64 [[ARG_CASTED]], align 8			// CHECK2-NEXT: [[TMP1:%.]] = load i64, i64 [[ARG_CASTED]], align 8
	// CHECK2-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32, i32, ...)* bitcast (void (i32, i32, i64)* @.omp_outlined. to void (i32, i32, ...)*), i64 [[TMP1]])			// CHECK2-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32, i32, ...)* bitcast (void (i32, i32, i64)* @.omp_outlined. to void (i32, i32, ...)*), i64 [[TMP1]])
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined.			// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined.
	Show All 40 Lines
	// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !9			// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !9
	// CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK2: omp.inner.for.body:			// CHECK2: omp.inner.for.body:
	// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !9			// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !9
	// CHECK2-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64			// CHECK2-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
	// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !9			// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !9
	// CHECK2-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK2-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[CONV]], align 4, !llvm.access.group !9			// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[CONV]], align 8, !llvm.access.group !9
	// CHECK2-NEXT: [[CONV2:%.]] = bitcast i64 [[ARG_CASTED]] to i32*			// CHECK2-NEXT: [[CONV2:%.]] = bitcast i64 [[ARG_CASTED]] to i32*
	// CHECK2-NEXT: store i32 [[TMP11]], i32* [[CONV2]], align 4, !llvm.access.group !9			// CHECK2-NEXT: store i32 [[TMP11]], i32* [[CONV2]], align 4, !llvm.access.group !9
	// CHECK2-NEXT: [[TMP12:%.]] = load i64, i64 [[ARG_CASTED]], align 8, !llvm.access.group !9			// CHECK2-NEXT: [[TMP12:%.]] = load i64, i64 [[ARG_CASTED]], align 8, !llvm.access.group !9
	// CHECK2-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i64)* @.omp_outlined..1 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]], i64 [[TMP12]]), !llvm.access.group !9			// CHECK2-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i64)* @.omp_outlined..1 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]], i64 [[TMP12]]), !llvm.access.group !9
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK2: omp.inner.for.inc:			// CHECK2: omp.inner.for.inc:
	// CHECK2-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9			// CHECK2-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK2-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !9			// CHECK2-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !9
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	// CHECK2-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !13			// CHECK2-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !13
	// CHECK2-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK2-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK2-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK2-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK2: omp.inner.for.body:			// CHECK2: omp.inner.for.body:
	// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13			// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !13			// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !13
	// CHECK2-NEXT: store i32 0, i32* [[CONV]], align 4, !llvm.access.group !13			// CHECK2-NEXT: store i32 0, i32* [[CONV]], align 8, !llvm.access.group !13
	// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK2: omp.body.continue:			// CHECK2: omp.body.continue:
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK2: omp.inner.for.inc:			// CHECK2: omp.inner.for.inc:
	// CHECK2-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13			// CHECK2-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK2-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13			// CHECK2-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]]
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	//			//
	// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92			// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92
	// CHECK2-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {			// CHECK2-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	// CHECK2-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8			// CHECK2-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
	// CHECK2-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8			// CHECK2-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
	// CHECK2-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8			// CHECK2-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
	// CHECK2-NEXT: [[CONV:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__ADDR]] to i8*			// CHECK2-NEXT: [[CONV:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__ADDR]] to i8*
	// CHECK2-NEXT: [[TMP0:%.]] = load i8, i8 [[CONV]], align 1			// CHECK2-NEXT: [[TMP0:%.]] = load i8, i8 [[CONV]], align 8
	// CHECK2-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP0]] to i1			// CHECK2-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP0]] to i1
	// CHECK2-NEXT: [[CONV1:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED]] to i8*			// CHECK2-NEXT: [[CONV1:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED]] to i8*
	// CHECK2-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8			// CHECK2-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
	// CHECK2-NEXT: store i8 [[FROMBOOL]], i8* [[CONV1]], align 1			// CHECK2-NEXT: store i8 [[FROMBOOL]], i8* [[CONV1]], align 1
	// CHECK2-NEXT: [[TMP1:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED]], align 8			// CHECK2-NEXT: [[TMP1:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED]], align 8
	// CHECK2-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32, i32, ...)* bitcast (void (i32, i32, i64)* @.omp_outlined..8 to void (i32, i32, ...)*), i64 [[TMP1]])			// CHECK2-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32, i32, ...)* bitcast (void (i32, i32, i64)* @.omp_outlined..8 to void (i32, i32, ...)*), i64 [[TMP1]])
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	//			//
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	// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !36			// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !36
	// CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK2: omp.inner.for.body:			// CHECK2: omp.inner.for.body:
	// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !36			// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !36
	// CHECK2-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64			// CHECK2-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
	// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !36			// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !36
	// CHECK2-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK2-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK2-NEXT: [[TMP11:%.]] = load i8, i8 [[CONV]], align 1, !llvm.access.group !36			// CHECK2-NEXT: [[TMP11:%.]] = load i8, i8 [[CONV]], align 8, !llvm.access.group !36
	// CHECK2-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1			// CHECK2-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
	// CHECK2-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE:%.]]			// CHECK2-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE:%.]]
	// CHECK2: omp_if.then:			// CHECK2: omp_if.then:
	// CHECK2-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..9 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !36			// CHECK2-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..9 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !36
	// CHECK2-NEXT: br label [[OMP_IF_END:%.*]]			// CHECK2-NEXT: br label [[OMP_IF_END:%.*]]
	// CHECK2: omp_if.else:			// CHECK2: omp_if.else:
	// CHECK2-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !36			// CHECK2-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !36
	// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !36			// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !36
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	//			//
	// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l70			// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l70
	// CHECK2-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {			// CHECK2-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	// CHECK2-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8			// CHECK2-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
	// CHECK2-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8			// CHECK2-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
	// CHECK2-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8			// CHECK2-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
	// CHECK2-NEXT: [[CONV:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__ADDR]] to i8*			// CHECK2-NEXT: [[CONV:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__ADDR]] to i8*
	// CHECK2-NEXT: [[TMP0:%.]] = load i8, i8 [[CONV]], align 1			// CHECK2-NEXT: [[TMP0:%.]] = load i8, i8 [[CONV]], align 8
	// CHECK2-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP0]] to i1			// CHECK2-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP0]] to i1
	// CHECK2-NEXT: [[CONV1:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED]] to i8*			// CHECK2-NEXT: [[CONV1:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED]] to i8*
	// CHECK2-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8			// CHECK2-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
	// CHECK2-NEXT: store i8 [[FROMBOOL]], i8* [[CONV1]], align 1			// CHECK2-NEXT: store i8 [[FROMBOOL]], i8* [[CONV1]], align 1
	// CHECK2-NEXT: [[TMP1:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED]], align 8			// CHECK2-NEXT: [[TMP1:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED]], align 8
	// CHECK2-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32, i32, ...)* bitcast (void (i32, i32, i64)* @.omp_outlined..16 to void (i32, i32, ...)*), i64 [[TMP1]])			// CHECK2-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32, i32, ...)* bitcast (void (i32, i32, i64)* @.omp_outlined..16 to void (i32, i32, ...)*), i64 [[TMP1]])
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	//			//
	▲ Show 20 Lines • Show All 42 Lines • ▼ Show 20 Lines
	// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !54			// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !54
	// CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK2: omp.inner.for.body:			// CHECK2: omp.inner.for.body:
	// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !54			// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !54
	// CHECK2-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64			// CHECK2-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
	// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !54			// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !54
	// CHECK2-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK2-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK2-NEXT: [[TMP11:%.]] = load i8, i8 [[CONV]], align 1, !llvm.access.group !54			// CHECK2-NEXT: [[TMP11:%.]] = load i8, i8 [[CONV]], align 8, !llvm.access.group !54
	// CHECK2-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1			// CHECK2-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
	// CHECK2-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE:%.]]			// CHECK2-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE:%.]]
	// CHECK2: omp_if.then:			// CHECK2: omp_if.then:
	// CHECK2-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..17 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !54			// CHECK2-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..17 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !54
	// CHECK2-NEXT: br label [[OMP_IF_END:%.*]]			// CHECK2-NEXT: br label [[OMP_IF_END:%.*]]
	// CHECK2: omp_if.else:			// CHECK2: omp_if.else:
	// CHECK2-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !54			// CHECK2-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !54
	// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !54			// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !54
	▲ Show 20 Lines • Show All 152 Lines • ▼ Show 20 Lines
	//			//
	// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l45			// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l45
	// CHECK3-SAME: (i64 [[ARG:%.*]]) #[[ATTR1:[0-9]+]] {			// CHECK3-SAME: (i64 [[ARG:%.*]]) #[[ATTR1:[0-9]+]] {
	// CHECK3-NEXT: entry:			// CHECK3-NEXT: entry:
	// CHECK3-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8			// CHECK3-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8
	// CHECK3-NEXT: [[ARG_CASTED:%.*]] = alloca i64, align 8			// CHECK3-NEXT: [[ARG_CASTED:%.*]] = alloca i64, align 8
	// CHECK3-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8			// CHECK3-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8
	// CHECK3-NEXT: [[CONV:%.]] = bitcast i64 [[ARG_ADDR]] to i32*			// CHECK3-NEXT: [[CONV:%.]] = bitcast i64 [[ARG_ADDR]] to i32*
	// CHECK3-NEXT: [[TMP0:%.]] = load i32, i32 [[CONV]], align 4			// CHECK3-NEXT: [[TMP0:%.]] = load i32, i32 [[CONV]], align 8
	// CHECK3-NEXT: [[CONV1:%.]] = bitcast i64 [[ARG_CASTED]] to i32*			// CHECK3-NEXT: [[CONV1:%.]] = bitcast i64 [[ARG_CASTED]] to i32*
	// CHECK3-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4			// CHECK3-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
	// CHECK3-NEXT: [[TMP1:%.]] = load i64, i64 [[ARG_CASTED]], align 8			// CHECK3-NEXT: [[TMP1:%.]] = load i64, i64 [[ARG_CASTED]], align 8
	// CHECK3-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32, i32, ...)* bitcast (void (i32, i32, i64)* @.omp_outlined. to void (i32, i32, ...)*), i64 [[TMP1]])			// CHECK3-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32, i32, ...)* bitcast (void (i32, i32, i64)* @.omp_outlined. to void (i32, i32, ...)*), i64 [[TMP1]])
	// CHECK3-NEXT: ret void			// CHECK3-NEXT: ret void
	//			//
	//			//
	// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined.			// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined.
	Show All 40 Lines
	// CHECK3-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !9			// CHECK3-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !9
	// CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK3: omp.inner.for.body:			// CHECK3: omp.inner.for.body:
	// CHECK3-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !9			// CHECK3-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !9
	// CHECK3-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64			// CHECK3-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
	// CHECK3-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !9			// CHECK3-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !9
	// CHECK3-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK3-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK3-NEXT: [[TMP11:%.]] = load i32, i32 [[CONV]], align 4, !nontemporal !10, !llvm.access.group !9			// CHECK3-NEXT: [[TMP11:%.]] = load i32, i32 [[CONV]], align 8, !nontemporal !10, !llvm.access.group !9
	// CHECK3-NEXT: [[CONV2:%.]] = bitcast i64 [[ARG_CASTED]] to i32*			// CHECK3-NEXT: [[CONV2:%.]] = bitcast i64 [[ARG_CASTED]] to i32*
	// CHECK3-NEXT: store i32 [[TMP11]], i32* [[CONV2]], align 4, !llvm.access.group !9			// CHECK3-NEXT: store i32 [[TMP11]], i32* [[CONV2]], align 4, !llvm.access.group !9
	// CHECK3-NEXT: [[TMP12:%.]] = load i64, i64 [[ARG_CASTED]], align 8, !llvm.access.group !9			// CHECK3-NEXT: [[TMP12:%.]] = load i64, i64 [[ARG_CASTED]], align 8, !llvm.access.group !9
	// CHECK3-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i64)* @.omp_outlined..1 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]], i64 [[TMP12]]), !llvm.access.group !9			// CHECK3-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i64)* @.omp_outlined..1 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]], i64 [[TMP12]]), !llvm.access.group !9
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK3: omp.inner.for.inc:			// CHECK3: omp.inner.for.inc:
	// CHECK3-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9			// CHECK3-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK3-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !9			// CHECK3-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !9
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	// CHECK3-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !14			// CHECK3-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !14
	// CHECK3-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK3-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK3-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK3-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK3: omp.inner.for.body:			// CHECK3: omp.inner.for.body:
	// CHECK3-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14			// CHECK3-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !14			// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !14
	// CHECK3-NEXT: store i32 0, i32* [[CONV]], align 4, !nontemporal !10, !llvm.access.group !14			// CHECK3-NEXT: store i32 0, i32* [[CONV]], align 8, !nontemporal !10, !llvm.access.group !14
	// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK3: omp.body.continue:			// CHECK3: omp.body.continue:
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK3: omp.inner.for.inc:			// CHECK3: omp.inner.for.inc:
	// CHECK3-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14			// CHECK3-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK3-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14			// CHECK3-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]]
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	//			//
	// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92			// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92
	// CHECK3-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {			// CHECK3-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
	// CHECK3-NEXT: entry:			// CHECK3-NEXT: entry:
	// CHECK3-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8			// CHECK3-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
	// CHECK3-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8			// CHECK3-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
	// CHECK3-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8			// CHECK3-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
	// CHECK3-NEXT: [[CONV:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__ADDR]] to i8*			// CHECK3-NEXT: [[CONV:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__ADDR]] to i8*
	// CHECK3-NEXT: [[TMP0:%.]] = load i8, i8 [[CONV]], align 1			// CHECK3-NEXT: [[TMP0:%.]] = load i8, i8 [[CONV]], align 8
	// CHECK3-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP0]] to i1			// CHECK3-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP0]] to i1
	// CHECK3-NEXT: [[CONV1:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED]] to i8*			// CHECK3-NEXT: [[CONV1:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED]] to i8*
	// CHECK3-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8			// CHECK3-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
	// CHECK3-NEXT: store i8 [[FROMBOOL]], i8* [[CONV1]], align 1			// CHECK3-NEXT: store i8 [[FROMBOOL]], i8* [[CONV1]], align 1
	// CHECK3-NEXT: [[TMP1:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED]], align 8			// CHECK3-NEXT: [[TMP1:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED]], align 8
	// CHECK3-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32, i32, ...)* bitcast (void (i32, i32, i64)* @.omp_outlined..8 to void (i32, i32, ...)*), i64 [[TMP1]])			// CHECK3-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32, i32, ...)* bitcast (void (i32, i32, i64)* @.omp_outlined..8 to void (i32, i32, ...)*), i64 [[TMP1]])
	// CHECK3-NEXT: ret void			// CHECK3-NEXT: ret void
	//			//
	Show All 34 Lines
	// CHECK3: cond.false:			// CHECK3: cond.false:
	// CHECK3-NEXT: [[TMP3:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK3-NEXT: [[TMP3:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4
	// CHECK3-NEXT: br label [[COND_END]]			// CHECK3-NEXT: br label [[COND_END]]
	// CHECK3: cond.end:			// CHECK3: cond.end:
	// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]			// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
	// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK3-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK3-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK3-NEXT: [[TMP5:%.]] = load i8, i8 [[CONV]], align 1			// CHECK3-NEXT: [[TMP5:%.]] = load i8, i8 [[CONV]], align 8
	// CHECK3-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP5]] to i1			// CHECK3-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP5]] to i1
	// CHECK3-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE6:%.]]			// CHECK3-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE6:%.]]
	// CHECK3: omp_if.then:			// CHECK3: omp_if.then:
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK3: omp.inner.for.cond:			// CHECK3: omp.inner.for.cond:
	// CHECK3-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !34			// CHECK3-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !34
	// CHECK3-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !34			// CHECK3-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !34
	// CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK3: omp.inner.for.body:			// CHECK3: omp.inner.for.body:
	// CHECK3-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !34			// CHECK3-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !34
	// CHECK3-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64			// CHECK3-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
	// CHECK3-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !34			// CHECK3-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !34
	// CHECK3-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64			// CHECK3-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
	// CHECK3-NEXT: [[TMP12:%.]] = load i8, i8 [[CONV]], align 1, !llvm.access.group !34			// CHECK3-NEXT: [[TMP12:%.]] = load i8, i8 [[CONV]], align 8, !llvm.access.group !34
	// CHECK3-NEXT: [[TOBOOL2:%.*]] = trunc i8 [[TMP12]] to i1			// CHECK3-NEXT: [[TOBOOL2:%.*]] = trunc i8 [[TMP12]] to i1
	// CHECK3-NEXT: [[CONV3:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED]] to i8*			// CHECK3-NEXT: [[CONV3:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED]] to i8*
	// CHECK3-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL2]] to i8			// CHECK3-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL2]] to i8
	// CHECK3-NEXT: store i8 [[FROMBOOL]], i8* [[CONV3]], align 1, !llvm.access.group !34			// CHECK3-NEXT: store i8 [[FROMBOOL]], i8* [[CONV3]], align 1, !llvm.access.group !34
	// CHECK3-NEXT: [[TMP13:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !34			// CHECK3-NEXT: [[TMP13:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !34
	// CHECK3-NEXT: [[TMP14:%.]] = load i8, i8 [[CONV]], align 1, !llvm.access.group !34			// CHECK3-NEXT: [[TMP14:%.]] = load i8, i8 [[CONV]], align 8, !llvm.access.group !34
	// CHECK3-NEXT: [[TOBOOL4:%.*]] = trunc i8 [[TMP14]] to i1			// CHECK3-NEXT: [[TOBOOL4:%.*]] = trunc i8 [[TMP14]] to i1
	// CHECK3-NEXT: br i1 [[TOBOOL4]], label [[OMP_IF_THEN5:%.]], label [[OMP_IF_ELSE:%.]]			// CHECK3-NEXT: br i1 [[TOBOOL4]], label [[OMP_IF_THEN5:%.]], label [[OMP_IF_ELSE:%.]]
	// CHECK3: omp_if.then5:			// CHECK3: omp_if.then5:
	// CHECK3-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i64)* @.omp_outlined..9 to void (i32, i32, ...)*), i64 [[TMP9]], i64 [[TMP11]], i64 [[TMP13]]), !llvm.access.group !34			// CHECK3-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i64)* @.omp_outlined..9 to void (i32, i32, ...)*), i64 [[TMP9]], i64 [[TMP11]], i64 [[TMP13]]), !llvm.access.group !34
	// CHECK3-NEXT: br label [[OMP_IF_END:%.*]]			// CHECK3-NEXT: br label [[OMP_IF_END:%.*]]
	// CHECK3: omp_if.else:			// CHECK3: omp_if.else:
	// CHECK3-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !34			// CHECK3-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !34
	// CHECK3-NEXT: [[TMP15:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !34			// CHECK3-NEXT: [[TMP15:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !34
	Show All 18 Lines
	// CHECK3-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK3-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4
	// CHECK3-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP18]], [[TMP19]]			// CHECK3-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP18]], [[TMP19]]
	// CHECK3-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY9:%.]], label [[OMP_INNER_FOR_END21:%.]]			// CHECK3-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY9:%.]], label [[OMP_INNER_FOR_END21:%.]]
	// CHECK3: omp.inner.for.body9:			// CHECK3: omp.inner.for.body9:
	// CHECK3-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK3-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK3-NEXT: [[TMP21:%.*]] = zext i32 [[TMP20]] to i64			// CHECK3-NEXT: [[TMP21:%.*]] = zext i32 [[TMP20]] to i64
	// CHECK3-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK3-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4
	// CHECK3-NEXT: [[TMP23:%.*]] = zext i32 [[TMP22]] to i64			// CHECK3-NEXT: [[TMP23:%.*]] = zext i32 [[TMP22]] to i64
	// CHECK3-NEXT: [[TMP24:%.]] = load i8, i8 [[CONV]], align 1			// CHECK3-NEXT: [[TMP24:%.]] = load i8, i8 [[CONV]], align 8
	// CHECK3-NEXT: [[TOBOOL10:%.*]] = trunc i8 [[TMP24]] to i1			// CHECK3-NEXT: [[TOBOOL10:%.*]] = trunc i8 [[TMP24]] to i1
	// CHECK3-NEXT: [[CONV12:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED11]] to i8*			// CHECK3-NEXT: [[CONV12:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED11]] to i8*
	// CHECK3-NEXT: [[FROMBOOL13:%.*]] = zext i1 [[TOBOOL10]] to i8			// CHECK3-NEXT: [[FROMBOOL13:%.*]] = zext i1 [[TOBOOL10]] to i8
	// CHECK3-NEXT: store i8 [[FROMBOOL13]], i8* [[CONV12]], align 1			// CHECK3-NEXT: store i8 [[FROMBOOL13]], i8* [[CONV12]], align 1
	// CHECK3-NEXT: [[TMP25:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED11]], align 8			// CHECK3-NEXT: [[TMP25:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED11]], align 8
	// CHECK3-NEXT: [[TMP26:%.]] = load i8, i8 [[CONV]], align 1			// CHECK3-NEXT: [[TMP26:%.]] = load i8, i8 [[CONV]], align 8
	// CHECK3-NEXT: [[TOBOOL14:%.*]] = trunc i8 [[TMP26]] to i1			// CHECK3-NEXT: [[TOBOOL14:%.*]] = trunc i8 [[TMP26]] to i1
	// CHECK3-NEXT: br i1 [[TOBOOL14]], label [[OMP_IF_THEN15:%.]], label [[OMP_IF_ELSE16:%.]]			// CHECK3-NEXT: br i1 [[TOBOOL14]], label [[OMP_IF_THEN15:%.]], label [[OMP_IF_ELSE16:%.]]
	// CHECK3: omp_if.then15:			// CHECK3: omp_if.then15:
	// CHECK3-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i64)* @.omp_outlined..10 to void (i32, i32, ...)*), i64 [[TMP21]], i64 [[TMP23]], i64 [[TMP25]])			// CHECK3-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i64)* @.omp_outlined..10 to void (i32, i32, ...)*), i64 [[TMP21]], i64 [[TMP23]], i64 [[TMP25]])
	// CHECK3-NEXT: br label [[OMP_IF_END18:%.*]]			// CHECK3-NEXT: br label [[OMP_IF_END18:%.*]]
	// CHECK3: omp_if.else16:			// CHECK3: omp_if.else16:
	// CHECK3-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]])			// CHECK3-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]])
	// CHECK3-NEXT: [[TMP27:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK3-NEXT: [[TMP27:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
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	// CHECK3-NEXT: [[TMP0:%.]] = load i64, i64 [[DOTPREVIOUS_LB__ADDR]], align 8			// CHECK3-NEXT: [[TMP0:%.]] = load i64, i64 [[DOTPREVIOUS_LB__ADDR]], align 8
	// CHECK3-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP0]] to i32			// CHECK3-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP0]] to i32
	// CHECK3-NEXT: [[TMP1:%.]] = load i64, i64 [[DOTPREVIOUS_UB__ADDR]], align 8			// CHECK3-NEXT: [[TMP1:%.]] = load i64, i64 [[DOTPREVIOUS_UB__ADDR]], align 8
	// CHECK3-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32			// CHECK3-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32
	// CHECK3-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4			// CHECK3-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4
	// CHECK3-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4			// CHECK3-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4
	// CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4			// CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
	// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4			// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
	// CHECK3-NEXT: [[TMP2:%.]] = load i8, i8 [[CONV]], align 1			// CHECK3-NEXT: [[TMP2:%.]] = load i8, i8 [[CONV]], align 8
	// CHECK3-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1			// CHECK3-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1
	// CHECK3-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE:%.]]			// CHECK3-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE:%.]]
	// CHECK3: omp_if.then:			// CHECK3: omp_if.then:
	// CHECK3-NEXT: [[TMP3:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK3-NEXT: [[TMP3:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK3-NEXT: [[TMP4:%.]] = load i32, i32 [[TMP3]], align 4			// CHECK3-NEXT: [[TMP4:%.]] = load i32, i32 [[TMP3]], align 4
	// CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)			// CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
	// CHECK3-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK3-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 99			// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 99
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	// CHECK3-NEXT: [[TMP0:%.]] = load i64, i64 [[DOTPREVIOUS_LB__ADDR]], align 8			// CHECK3-NEXT: [[TMP0:%.]] = load i64, i64 [[DOTPREVIOUS_LB__ADDR]], align 8
	// CHECK3-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP0]] to i32			// CHECK3-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP0]] to i32
	// CHECK3-NEXT: [[TMP1:%.]] = load i64, i64 [[DOTPREVIOUS_UB__ADDR]], align 8			// CHECK3-NEXT: [[TMP1:%.]] = load i64, i64 [[DOTPREVIOUS_UB__ADDR]], align 8
	// CHECK3-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32			// CHECK3-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32
	// CHECK3-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4			// CHECK3-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4
	// CHECK3-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4			// CHECK3-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4
	// CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4			// CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
	// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4			// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
	// CHECK3-NEXT: [[TMP2:%.]] = load i8, i8 [[CONV]], align 1			// CHECK3-NEXT: [[TMP2:%.]] = load i8, i8 [[CONV]], align 8
	// CHECK3-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1			// CHECK3-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1
	// CHECK3-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE:%.]]			// CHECK3-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE:%.]]
	// CHECK3: omp_if.then:			// CHECK3: omp_if.then:
	// CHECK3-NEXT: [[TMP3:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK3-NEXT: [[TMP3:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK3-NEXT: [[TMP4:%.]] = load i32, i32 [[TMP3]], align 4			// CHECK3-NEXT: [[TMP4:%.]] = load i32, i32 [[TMP3]], align 4
	// CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)			// CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
	// CHECK3-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK3-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 99			// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 99
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	//			//
	// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l70			// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l70
	// CHECK3-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {			// CHECK3-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
	// CHECK3-NEXT: entry:			// CHECK3-NEXT: entry:
	// CHECK3-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8			// CHECK3-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
	// CHECK3-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8			// CHECK3-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
	// CHECK3-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8			// CHECK3-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
	// CHECK3-NEXT: [[CONV:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__ADDR]] to i8*			// CHECK3-NEXT: [[CONV:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__ADDR]] to i8*
	// CHECK3-NEXT: [[TMP0:%.]] = load i8, i8 [[CONV]], align 1			// CHECK3-NEXT: [[TMP0:%.]] = load i8, i8 [[CONV]], align 8
	// CHECK3-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP0]] to i1			// CHECK3-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP0]] to i1
	// CHECK3-NEXT: [[CONV1:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED]] to i8*			// CHECK3-NEXT: [[CONV1:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED]] to i8*
	// CHECK3-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8			// CHECK3-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
	// CHECK3-NEXT: store i8 [[FROMBOOL]], i8* [[CONV1]], align 1			// CHECK3-NEXT: store i8 [[FROMBOOL]], i8* [[CONV1]], align 1
	// CHECK3-NEXT: [[TMP1:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED]], align 8			// CHECK3-NEXT: [[TMP1:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED]], align 8
	// CHECK3-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32, i32, ...)* bitcast (void (i32, i32, i64)* @.omp_outlined..17 to void (i32, i32, ...)*), i64 [[TMP1]])			// CHECK3-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32, i32, ...)* bitcast (void (i32, i32, i64)* @.omp_outlined..17 to void (i32, i32, ...)*), i64 [[TMP1]])
	// CHECK3-NEXT: ret void			// CHECK3-NEXT: ret void
	//			//
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	// CHECK3-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !54			// CHECK3-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !54
	// CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK3: omp.inner.for.body:			// CHECK3: omp.inner.for.body:
	// CHECK3-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !54			// CHECK3-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !54
	// CHECK3-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64			// CHECK3-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
	// CHECK3-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !54			// CHECK3-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !54
	// CHECK3-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK3-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK3-NEXT: [[TMP11:%.]] = load i8, i8 [[CONV]], align 1, !llvm.access.group !54			// CHECK3-NEXT: [[TMP11:%.]] = load i8, i8 [[CONV]], align 8, !llvm.access.group !54
	// CHECK3-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1			// CHECK3-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
	// CHECK3-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE:%.]]			// CHECK3-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE:%.]]
	// CHECK3: omp_if.then:			// CHECK3: omp_if.then:
	// CHECK3-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..18 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !54			// CHECK3-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..18 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !54
	// CHECK3-NEXT: br label [[OMP_IF_END:%.*]]			// CHECK3-NEXT: br label [[OMP_IF_END:%.*]]
	// CHECK3: omp_if.else:			// CHECK3: omp_if.else:
	// CHECK3-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !54			// CHECK3-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !54
	// CHECK3-NEXT: [[TMP12:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !54			// CHECK3-NEXT: [[TMP12:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !54
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	//			//
	// CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l45			// CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l45
	// CHECK4-SAME: (i64 [[ARG:%.*]]) #[[ATTR1:[0-9]+]] {			// CHECK4-SAME: (i64 [[ARG:%.*]]) #[[ATTR1:[0-9]+]] {
	// CHECK4-NEXT: entry:			// CHECK4-NEXT: entry:
	// CHECK4-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8			// CHECK4-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8
	// CHECK4-NEXT: [[ARG_CASTED:%.*]] = alloca i64, align 8			// CHECK4-NEXT: [[ARG_CASTED:%.*]] = alloca i64, align 8
	// CHECK4-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8			// CHECK4-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8
	// CHECK4-NEXT: [[CONV:%.]] = bitcast i64 [[ARG_ADDR]] to i32*			// CHECK4-NEXT: [[CONV:%.]] = bitcast i64 [[ARG_ADDR]] to i32*
	// CHECK4-NEXT: [[TMP0:%.]] = load i32, i32 [[CONV]], align 4			// CHECK4-NEXT: [[TMP0:%.]] = load i32, i32 [[CONV]], align 8
	// CHECK4-NEXT: [[CONV1:%.]] = bitcast i64 [[ARG_CASTED]] to i32*			// CHECK4-NEXT: [[CONV1:%.]] = bitcast i64 [[ARG_CASTED]] to i32*
	// CHECK4-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4			// CHECK4-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
	// CHECK4-NEXT: [[TMP1:%.]] = load i64, i64 [[ARG_CASTED]], align 8			// CHECK4-NEXT: [[TMP1:%.]] = load i64, i64 [[ARG_CASTED]], align 8
	// CHECK4-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32, i32, ...)* bitcast (void (i32, i32, i64)* @.omp_outlined. to void (i32, i32, ...)*), i64 [[TMP1]])			// CHECK4-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32, i32, ...)* bitcast (void (i32, i32, i64)* @.omp_outlined. to void (i32, i32, ...)*), i64 [[TMP1]])
	// CHECK4-NEXT: ret void			// CHECK4-NEXT: ret void
	//			//
	//			//
	// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined.			// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined.
	Show All 40 Lines
	// CHECK4-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !9			// CHECK4-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !9
	// CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK4: omp.inner.for.body:			// CHECK4: omp.inner.for.body:
	// CHECK4-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !9			// CHECK4-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !9
	// CHECK4-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64			// CHECK4-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
	// CHECK4-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !9			// CHECK4-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !9
	// CHECK4-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK4-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK4-NEXT: [[TMP11:%.]] = load i32, i32 [[CONV]], align 4, !nontemporal !10, !llvm.access.group !9			// CHECK4-NEXT: [[TMP11:%.]] = load i32, i32 [[CONV]], align 8, !nontemporal !10, !llvm.access.group !9
	// CHECK4-NEXT: [[CONV2:%.]] = bitcast i64 [[ARG_CASTED]] to i32*			// CHECK4-NEXT: [[CONV2:%.]] = bitcast i64 [[ARG_CASTED]] to i32*
	// CHECK4-NEXT: store i32 [[TMP11]], i32* [[CONV2]], align 4, !llvm.access.group !9			// CHECK4-NEXT: store i32 [[TMP11]], i32* [[CONV2]], align 4, !llvm.access.group !9
	// CHECK4-NEXT: [[TMP12:%.]] = load i64, i64 [[ARG_CASTED]], align 8, !llvm.access.group !9			// CHECK4-NEXT: [[TMP12:%.]] = load i64, i64 [[ARG_CASTED]], align 8, !llvm.access.group !9
	// CHECK4-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i64)* @.omp_outlined..1 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]], i64 [[TMP12]]), !llvm.access.group !9			// CHECK4-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i64)* @.omp_outlined..1 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]], i64 [[TMP12]]), !llvm.access.group !9
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK4: omp.inner.for.inc:			// CHECK4: omp.inner.for.inc:
	// CHECK4-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9			// CHECK4-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK4-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !9			// CHECK4-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !9
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	// CHECK4-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !14			// CHECK4-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !14
	// CHECK4-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK4-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK4-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK4-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK4: omp.inner.for.body:			// CHECK4: omp.inner.for.body:
	// CHECK4-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14			// CHECK4-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !14			// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !14
	// CHECK4-NEXT: store i32 0, i32* [[CONV]], align 4, !nontemporal !10, !llvm.access.group !14			// CHECK4-NEXT: store i32 0, i32* [[CONV]], align 8, !nontemporal !10, !llvm.access.group !14
	// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK4: omp.body.continue:			// CHECK4: omp.body.continue:
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK4: omp.inner.for.inc:			// CHECK4: omp.inner.for.inc:
	// CHECK4-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14			// CHECK4-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK4-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14			// CHECK4-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]]
	▲ Show 20 Lines • Show All 545 Lines • ▼ Show 20 Lines
	//			//
	// CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92			// CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92
	// CHECK4-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {			// CHECK4-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
	// CHECK4-NEXT: entry:			// CHECK4-NEXT: entry:
	// CHECK4-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8			// CHECK4-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
	// CHECK4-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8			// CHECK4-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
	// CHECK4-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8			// CHECK4-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
	// CHECK4-NEXT: [[CONV:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__ADDR]] to i8*			// CHECK4-NEXT: [[CONV:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__ADDR]] to i8*
	// CHECK4-NEXT: [[TMP0:%.]] = load i8, i8 [[CONV]], align 1			// CHECK4-NEXT: [[TMP0:%.]] = load i8, i8 [[CONV]], align 8
	// CHECK4-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP0]] to i1			// CHECK4-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP0]] to i1
	// CHECK4-NEXT: [[CONV1:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED]] to i8*			// CHECK4-NEXT: [[CONV1:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED]] to i8*
	// CHECK4-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8			// CHECK4-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
	// CHECK4-NEXT: store i8 [[FROMBOOL]], i8* [[CONV1]], align 1			// CHECK4-NEXT: store i8 [[FROMBOOL]], i8* [[CONV1]], align 1
	// CHECK4-NEXT: [[TMP1:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED]], align 8			// CHECK4-NEXT: [[TMP1:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED]], align 8
	// CHECK4-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32, i32, ...)* bitcast (void (i32, i32, i64)* @.omp_outlined..8 to void (i32, i32, ...)*), i64 [[TMP1]])			// CHECK4-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32, i32, ...)* bitcast (void (i32, i32, i64)* @.omp_outlined..8 to void (i32, i32, ...)*), i64 [[TMP1]])
	// CHECK4-NEXT: ret void			// CHECK4-NEXT: ret void
	//			//
	Show All 34 Lines
	// CHECK4: cond.false:			// CHECK4: cond.false:
	// CHECK4-NEXT: [[TMP3:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK4-NEXT: [[TMP3:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4
	// CHECK4-NEXT: br label [[COND_END]]			// CHECK4-NEXT: br label [[COND_END]]
	// CHECK4: cond.end:			// CHECK4: cond.end:
	// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]			// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
	// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK4-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK4-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK4-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK4-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK4-NEXT: [[TMP5:%.]] = load i8, i8 [[CONV]], align 1			// CHECK4-NEXT: [[TMP5:%.]] = load i8, i8 [[CONV]], align 8
	// CHECK4-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP5]] to i1			// CHECK4-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP5]] to i1
	// CHECK4-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE6:%.]]			// CHECK4-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE6:%.]]
	// CHECK4: omp_if.then:			// CHECK4: omp_if.then:
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK4: omp.inner.for.cond:			// CHECK4: omp.inner.for.cond:
	// CHECK4-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !34			// CHECK4-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !34
	// CHECK4-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !34			// CHECK4-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !34
	// CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK4: omp.inner.for.body:			// CHECK4: omp.inner.for.body:
	// CHECK4-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !34			// CHECK4-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !34
	// CHECK4-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64			// CHECK4-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
	// CHECK4-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !34			// CHECK4-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !34
	// CHECK4-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64			// CHECK4-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
	// CHECK4-NEXT: [[TMP12:%.]] = load i8, i8 [[CONV]], align 1, !llvm.access.group !34			// CHECK4-NEXT: [[TMP12:%.]] = load i8, i8 [[CONV]], align 8, !llvm.access.group !34
	// CHECK4-NEXT: [[TOBOOL2:%.*]] = trunc i8 [[TMP12]] to i1			// CHECK4-NEXT: [[TOBOOL2:%.*]] = trunc i8 [[TMP12]] to i1
	// CHECK4-NEXT: [[CONV3:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED]] to i8*			// CHECK4-NEXT: [[CONV3:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED]] to i8*
	// CHECK4-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL2]] to i8			// CHECK4-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL2]] to i8
	// CHECK4-NEXT: store i8 [[FROMBOOL]], i8* [[CONV3]], align 1, !llvm.access.group !34			// CHECK4-NEXT: store i8 [[FROMBOOL]], i8* [[CONV3]], align 1, !llvm.access.group !34
	// CHECK4-NEXT: [[TMP13:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !34			// CHECK4-NEXT: [[TMP13:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !34
	// CHECK4-NEXT: [[TMP14:%.]] = load i8, i8 [[CONV]], align 1, !llvm.access.group !34			// CHECK4-NEXT: [[TMP14:%.]] = load i8, i8 [[CONV]], align 8, !llvm.access.group !34
	// CHECK4-NEXT: [[TOBOOL4:%.*]] = trunc i8 [[TMP14]] to i1			// CHECK4-NEXT: [[TOBOOL4:%.*]] = trunc i8 [[TMP14]] to i1
	// CHECK4-NEXT: br i1 [[TOBOOL4]], label [[OMP_IF_THEN5:%.]], label [[OMP_IF_ELSE:%.]]			// CHECK4-NEXT: br i1 [[TOBOOL4]], label [[OMP_IF_THEN5:%.]], label [[OMP_IF_ELSE:%.]]
	// CHECK4: omp_if.then5:			// CHECK4: omp_if.then5:
	// CHECK4-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i64)* @.omp_outlined..9 to void (i32, i32, ...)*), i64 [[TMP9]], i64 [[TMP11]], i64 [[TMP13]]), !llvm.access.group !34			// CHECK4-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i64)* @.omp_outlined..9 to void (i32, i32, ...)*), i64 [[TMP9]], i64 [[TMP11]], i64 [[TMP13]]), !llvm.access.group !34
	// CHECK4-NEXT: br label [[OMP_IF_END:%.*]]			// CHECK4-NEXT: br label [[OMP_IF_END:%.*]]
	// CHECK4: omp_if.else:			// CHECK4: omp_if.else:
	// CHECK4-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !34			// CHECK4-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !34
	// CHECK4-NEXT: [[TMP15:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !34			// CHECK4-NEXT: [[TMP15:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !34
	Show All 18 Lines
	// CHECK4-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK4-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4
	// CHECK4-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP18]], [[TMP19]]			// CHECK4-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP18]], [[TMP19]]
	// CHECK4-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY9:%.]], label [[OMP_INNER_FOR_END21:%.]]			// CHECK4-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY9:%.]], label [[OMP_INNER_FOR_END21:%.]]
	// CHECK4: omp.inner.for.body9:			// CHECK4: omp.inner.for.body9:
	// CHECK4-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK4-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK4-NEXT: [[TMP21:%.*]] = zext i32 [[TMP20]] to i64			// CHECK4-NEXT: [[TMP21:%.*]] = zext i32 [[TMP20]] to i64
	// CHECK4-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK4-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4
	// CHECK4-NEXT: [[TMP23:%.*]] = zext i32 [[TMP22]] to i64			// CHECK4-NEXT: [[TMP23:%.*]] = zext i32 [[TMP22]] to i64
	// CHECK4-NEXT: [[TMP24:%.]] = load i8, i8 [[CONV]], align 1			// CHECK4-NEXT: [[TMP24:%.]] = load i8, i8 [[CONV]], align 8
	// CHECK4-NEXT: [[TOBOOL10:%.*]] = trunc i8 [[TMP24]] to i1			// CHECK4-NEXT: [[TOBOOL10:%.*]] = trunc i8 [[TMP24]] to i1
	// CHECK4-NEXT: [[CONV12:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED11]] to i8*			// CHECK4-NEXT: [[CONV12:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED11]] to i8*
	// CHECK4-NEXT: [[FROMBOOL13:%.*]] = zext i1 [[TOBOOL10]] to i8			// CHECK4-NEXT: [[FROMBOOL13:%.*]] = zext i1 [[TOBOOL10]] to i8
	// CHECK4-NEXT: store i8 [[FROMBOOL13]], i8* [[CONV12]], align 1			// CHECK4-NEXT: store i8 [[FROMBOOL13]], i8* [[CONV12]], align 1
	// CHECK4-NEXT: [[TMP25:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED11]], align 8			// CHECK4-NEXT: [[TMP25:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED11]], align 8
	// CHECK4-NEXT: [[TMP26:%.]] = load i8, i8 [[CONV]], align 1			// CHECK4-NEXT: [[TMP26:%.]] = load i8, i8 [[CONV]], align 8
	// CHECK4-NEXT: [[TOBOOL14:%.*]] = trunc i8 [[TMP26]] to i1			// CHECK4-NEXT: [[TOBOOL14:%.*]] = trunc i8 [[TMP26]] to i1
	// CHECK4-NEXT: br i1 [[TOBOOL14]], label [[OMP_IF_THEN15:%.]], label [[OMP_IF_ELSE16:%.]]			// CHECK4-NEXT: br i1 [[TOBOOL14]], label [[OMP_IF_THEN15:%.]], label [[OMP_IF_ELSE16:%.]]
	// CHECK4: omp_if.then15:			// CHECK4: omp_if.then15:
	// CHECK4-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i64)* @.omp_outlined..10 to void (i32, i32, ...)*), i64 [[TMP21]], i64 [[TMP23]], i64 [[TMP25]])			// CHECK4-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i64)* @.omp_outlined..10 to void (i32, i32, ...)*), i64 [[TMP21]], i64 [[TMP23]], i64 [[TMP25]])
	// CHECK4-NEXT: br label [[OMP_IF_END18:%.*]]			// CHECK4-NEXT: br label [[OMP_IF_END18:%.*]]
	// CHECK4: omp_if.else16:			// CHECK4: omp_if.else16:
	// CHECK4-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]])			// CHECK4-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]])
	// CHECK4-NEXT: [[TMP27:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK4-NEXT: [[TMP27:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
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	// CHECK4-NEXT: [[TMP0:%.]] = load i64, i64 [[DOTPREVIOUS_LB__ADDR]], align 8			// CHECK4-NEXT: [[TMP0:%.]] = load i64, i64 [[DOTPREVIOUS_LB__ADDR]], align 8
	// CHECK4-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP0]] to i32			// CHECK4-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP0]] to i32
	// CHECK4-NEXT: [[TMP1:%.]] = load i64, i64 [[DOTPREVIOUS_UB__ADDR]], align 8			// CHECK4-NEXT: [[TMP1:%.]] = load i64, i64 [[DOTPREVIOUS_UB__ADDR]], align 8
	// CHECK4-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32			// CHECK4-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32
	// CHECK4-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4			// CHECK4-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4
	// CHECK4-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4			// CHECK4-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4
	// CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4			// CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
	// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4			// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
	// CHECK4-NEXT: [[TMP2:%.]] = load i8, i8 [[CONV]], align 1			// CHECK4-NEXT: [[TMP2:%.]] = load i8, i8 [[CONV]], align 8
	// CHECK4-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1			// CHECK4-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1
	// CHECK4-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE:%.]]			// CHECK4-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE:%.]]
	// CHECK4: omp_if.then:			// CHECK4: omp_if.then:
	// CHECK4-NEXT: [[TMP3:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK4-NEXT: [[TMP3:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK4-NEXT: [[TMP4:%.]] = load i32, i32 [[TMP3]], align 4			// CHECK4-NEXT: [[TMP4:%.]] = load i32, i32 [[TMP3]], align 4
	// CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)			// CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
	// CHECK4-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK4-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 99			// CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 99
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	// CHECK4-NEXT: [[TMP0:%.]] = load i64, i64 [[DOTPREVIOUS_LB__ADDR]], align 8			// CHECK4-NEXT: [[TMP0:%.]] = load i64, i64 [[DOTPREVIOUS_LB__ADDR]], align 8
	// CHECK4-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP0]] to i32			// CHECK4-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP0]] to i32
	// CHECK4-NEXT: [[TMP1:%.]] = load i64, i64 [[DOTPREVIOUS_UB__ADDR]], align 8			// CHECK4-NEXT: [[TMP1:%.]] = load i64, i64 [[DOTPREVIOUS_UB__ADDR]], align 8
	// CHECK4-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32			// CHECK4-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32
	// CHECK4-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4			// CHECK4-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4
	// CHECK4-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4			// CHECK4-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4
	// CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4			// CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
	// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4			// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
	// CHECK4-NEXT: [[TMP2:%.]] = load i8, i8 [[CONV]], align 1			// CHECK4-NEXT: [[TMP2:%.]] = load i8, i8 [[CONV]], align 8
	// CHECK4-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1			// CHECK4-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1
	// CHECK4-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE:%.]]			// CHECK4-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE:%.]]
	// CHECK4: omp_if.then:			// CHECK4: omp_if.then:
	// CHECK4-NEXT: [[TMP3:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK4-NEXT: [[TMP3:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK4-NEXT: [[TMP4:%.]] = load i32, i32 [[TMP3]], align 4			// CHECK4-NEXT: [[TMP4:%.]] = load i32, i32 [[TMP3]], align 4
	// CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)			// CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
	// CHECK4-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK4-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 99			// CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 99
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	//			//
	// CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l70			// CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l70
	// CHECK4-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {			// CHECK4-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
	// CHECK4-NEXT: entry:			// CHECK4-NEXT: entry:
	// CHECK4-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8			// CHECK4-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
	// CHECK4-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8			// CHECK4-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
	// CHECK4-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8			// CHECK4-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
	// CHECK4-NEXT: [[CONV:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__ADDR]] to i8*			// CHECK4-NEXT: [[CONV:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__ADDR]] to i8*
	// CHECK4-NEXT: [[TMP0:%.]] = load i8, i8 [[CONV]], align 1			// CHECK4-NEXT: [[TMP0:%.]] = load i8, i8 [[CONV]], align 8
	// CHECK4-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP0]] to i1			// CHECK4-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP0]] to i1
	// CHECK4-NEXT: [[CONV1:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED]] to i8*			// CHECK4-NEXT: [[CONV1:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED]] to i8*
	// CHECK4-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8			// CHECK4-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
	// CHECK4-NEXT: store i8 [[FROMBOOL]], i8* [[CONV1]], align 1			// CHECK4-NEXT: store i8 [[FROMBOOL]], i8* [[CONV1]], align 1
	// CHECK4-NEXT: [[TMP1:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED]], align 8			// CHECK4-NEXT: [[TMP1:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED]], align 8
	// CHECK4-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32, i32, ...)* bitcast (void (i32, i32, i64)* @.omp_outlined..17 to void (i32, i32, ...)*), i64 [[TMP1]])			// CHECK4-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32, i32, ...)* bitcast (void (i32, i32, i64)* @.omp_outlined..17 to void (i32, i32, ...)*), i64 [[TMP1]])
	// CHECK4-NEXT: ret void			// CHECK4-NEXT: ret void
	//			//
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	// CHECK4-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !54			// CHECK4-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !54
	// CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK4: omp.inner.for.body:			// CHECK4: omp.inner.for.body:
	// CHECK4-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !54			// CHECK4-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !54
	// CHECK4-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64			// CHECK4-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
	// CHECK4-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !54			// CHECK4-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !54
	// CHECK4-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK4-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK4-NEXT: [[TMP11:%.]] = load i8, i8 [[CONV]], align 1, !llvm.access.group !54			// CHECK4-NEXT: [[TMP11:%.]] = load i8, i8 [[CONV]], align 8, !llvm.access.group !54
	// CHECK4-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1			// CHECK4-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
	// CHECK4-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE:%.]]			// CHECK4-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE:%.]]
	// CHECK4: omp_if.then:			// CHECK4: omp_if.then:
	// CHECK4-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..18 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !54			// CHECK4-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..18 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !54
	// CHECK4-NEXT: br label [[OMP_IF_END:%.*]]			// CHECK4-NEXT: br label [[OMP_IF_END:%.*]]
	// CHECK4: omp_if.else:			// CHECK4: omp_if.else:
	// CHECK4-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !54			// CHECK4-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !54
	// CHECK4-NEXT: [[TMP12:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !54			// CHECK4-NEXT: [[TMP12:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !54
	▲ Show 20 Lines • Show All 1,338 Lines • ▼ Show 20 Lines
	//			//
	// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l47			// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l47
	// CHECK9-SAME: (i64 [[ARG:%.*]]) #[[ATTR1:[0-9]+]] {			// CHECK9-SAME: (i64 [[ARG:%.*]]) #[[ATTR1:[0-9]+]] {
	// CHECK9-NEXT: entry:			// CHECK9-NEXT: entry:
	// CHECK9-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8			// CHECK9-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8
	// CHECK9-NEXT: [[ARG_CASTED:%.*]] = alloca i64, align 8			// CHECK9-NEXT: [[ARG_CASTED:%.*]] = alloca i64, align 8
	// CHECK9-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8			// CHECK9-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8
	// CHECK9-NEXT: [[CONV:%.]] = bitcast i64 [[ARG_ADDR]] to i32*			// CHECK9-NEXT: [[CONV:%.]] = bitcast i64 [[ARG_ADDR]] to i32*
	// CHECK9-NEXT: [[TMP0:%.]] = load i32, i32 [[CONV]], align 4			// CHECK9-NEXT: [[TMP0:%.]] = load i32, i32 [[CONV]], align 8
	// CHECK9-NEXT: [[CONV1:%.]] = bitcast i64 [[ARG_CASTED]] to i32*			// CHECK9-NEXT: [[CONV1:%.]] = bitcast i64 [[ARG_CASTED]] to i32*
	// CHECK9-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4			// CHECK9-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
	// CHECK9-NEXT: [[TMP1:%.]] = load i64, i64 [[ARG_CASTED]], align 8			// CHECK9-NEXT: [[TMP1:%.]] = load i64, i64 [[ARG_CASTED]], align 8
	// CHECK9-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32, i32, ...)* bitcast (void (i32, i32, i64)* @.omp_outlined. to void (i32, i32, ...)*), i64 [[TMP1]])			// CHECK9-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32, i32, ...)* bitcast (void (i32, i32, i64)* @.omp_outlined. to void (i32, i32, ...)*), i64 [[TMP1]])
	// CHECK9-NEXT: ret void			// CHECK9-NEXT: ret void
	//			//
	//			//
	// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined.			// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined.
	Show All 40 Lines
	// CHECK9-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !13			// CHECK9-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !13
	// CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK9: omp.inner.for.body:			// CHECK9: omp.inner.for.body:
	// CHECK9-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !13			// CHECK9-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !13
	// CHECK9-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64			// CHECK9-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
	// CHECK9-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !13			// CHECK9-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !13
	// CHECK9-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK9-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK9-NEXT: [[TMP11:%.]] = load i32, i32 [[CONV]], align 4, !llvm.access.group !13			// CHECK9-NEXT: [[TMP11:%.]] = load i32, i32 [[CONV]], align 8, !llvm.access.group !13
	// CHECK9-NEXT: [[CONV2:%.]] = bitcast i64 [[ARG_CASTED]] to i32*			// CHECK9-NEXT: [[CONV2:%.]] = bitcast i64 [[ARG_CASTED]] to i32*
	// CHECK9-NEXT: store i32 [[TMP11]], i32* [[CONV2]], align 4, !llvm.access.group !13			// CHECK9-NEXT: store i32 [[TMP11]], i32* [[CONV2]], align 4, !llvm.access.group !13
	// CHECK9-NEXT: [[TMP12:%.]] = load i64, i64 [[ARG_CASTED]], align 8, !llvm.access.group !13			// CHECK9-NEXT: [[TMP12:%.]] = load i64, i64 [[ARG_CASTED]], align 8, !llvm.access.group !13
	// CHECK9-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i64)* @.omp_outlined..1 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]], i64 [[TMP12]]), !llvm.access.group !13			// CHECK9-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i64)* @.omp_outlined..1 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]], i64 [[TMP12]]), !llvm.access.group !13
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK9: omp.inner.for.inc:			// CHECK9: omp.inner.for.inc:
	// CHECK9-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13			// CHECK9-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK9-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !13			// CHECK9-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !13
	▲ Show 20 Lines • Show All 67 Lines • ▼ Show 20 Lines
	// CHECK9-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !17			// CHECK9-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !17
	// CHECK9-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK9-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK9-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK9-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK9: omp.inner.for.body:			// CHECK9: omp.inner.for.body:
	// CHECK9-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !17			// CHECK9-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !17
	// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !17			// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !17
	// CHECK9-NEXT: store i32 0, i32* [[CONV]], align 4, !llvm.access.group !17			// CHECK9-NEXT: store i32 0, i32* [[CONV]], align 8, !llvm.access.group !17
	// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK9: omp.body.continue:			// CHECK9: omp.body.continue:
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK9: omp.inner.for.inc:			// CHECK9: omp.inner.for.inc:
	// CHECK9-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !17			// CHECK9-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !17
	// CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK9-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17			// CHECK9-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]]
	▲ Show 20 Lines • Show All 545 Lines • ▼ Show 20 Lines
	//			//
	// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92			// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92
	// CHECK9-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {			// CHECK9-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
	// CHECK9-NEXT: entry:			// CHECK9-NEXT: entry:
	// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8			// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
	// CHECK9-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8			// CHECK9-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
	// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8			// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
	// CHECK9-NEXT: [[CONV:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__ADDR]] to i8*			// CHECK9-NEXT: [[CONV:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__ADDR]] to i8*
	// CHECK9-NEXT: [[TMP0:%.]] = load i8, i8 [[CONV]], align 1			// CHECK9-NEXT: [[TMP0:%.]] = load i8, i8 [[CONV]], align 8
	// CHECK9-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP0]] to i1			// CHECK9-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP0]] to i1
	// CHECK9-NEXT: [[CONV1:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED]] to i8*			// CHECK9-NEXT: [[CONV1:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED]] to i8*
	// CHECK9-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8			// CHECK9-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
	// CHECK9-NEXT: store i8 [[FROMBOOL]], i8* [[CONV1]], align 1			// CHECK9-NEXT: store i8 [[FROMBOOL]], i8* [[CONV1]], align 1
	// CHECK9-NEXT: [[TMP1:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED]], align 8			// CHECK9-NEXT: [[TMP1:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED]], align 8
	// CHECK9-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32, i32, ...)* bitcast (void (i32, i32, i64)* @.omp_outlined..8 to void (i32, i32, ...)*), i64 [[TMP1]])			// CHECK9-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32, i32, ...)* bitcast (void (i32, i32, i64)* @.omp_outlined..8 to void (i32, i32, ...)*), i64 [[TMP1]])
	// CHECK9-NEXT: ret void			// CHECK9-NEXT: ret void
	//			//
	▲ Show 20 Lines • Show All 42 Lines • ▼ Show 20 Lines
	// CHECK9-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !40			// CHECK9-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !40
	// CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK9: omp.inner.for.body:			// CHECK9: omp.inner.for.body:
	// CHECK9-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !40			// CHECK9-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !40
	// CHECK9-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64			// CHECK9-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
	// CHECK9-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !40			// CHECK9-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !40
	// CHECK9-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK9-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK9-NEXT: [[TMP11:%.]] = load i8, i8 [[CONV]], align 1, !llvm.access.group !40			// CHECK9-NEXT: [[TMP11:%.]] = load i8, i8 [[CONV]], align 8, !llvm.access.group !40
	// CHECK9-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1			// CHECK9-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
	// CHECK9-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE:%.]]			// CHECK9-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE:%.]]
	// CHECK9: omp_if.then:			// CHECK9: omp_if.then:
	// CHECK9-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..9 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !40			// CHECK9-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..9 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !40
	// CHECK9-NEXT: br label [[OMP_IF_END:%.*]]			// CHECK9-NEXT: br label [[OMP_IF_END:%.*]]
	// CHECK9: omp_if.else:			// CHECK9: omp_if.else:
	// CHECK9-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !40			// CHECK9-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !40
	// CHECK9-NEXT: [[TMP12:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !40			// CHECK9-NEXT: [[TMP12:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !40
	▲ Show 20 Lines • Show All 467 Lines • ▼ Show 20 Lines
	//			//
	// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l70			// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l70
	// CHECK9-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {			// CHECK9-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
	// CHECK9-NEXT: entry:			// CHECK9-NEXT: entry:
	// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8			// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
	// CHECK9-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8			// CHECK9-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
	// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8			// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
	// CHECK9-NEXT: [[CONV:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__ADDR]] to i8*			// CHECK9-NEXT: [[CONV:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__ADDR]] to i8*
	// CHECK9-NEXT: [[TMP0:%.]] = load i8, i8 [[CONV]], align 1			// CHECK9-NEXT: [[TMP0:%.]] = load i8, i8 [[CONV]], align 8
	// CHECK9-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP0]] to i1			// CHECK9-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP0]] to i1
	// CHECK9-NEXT: [[CONV1:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED]] to i8*			// CHECK9-NEXT: [[CONV1:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED]] to i8*
	// CHECK9-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8			// CHECK9-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
	// CHECK9-NEXT: store i8 [[FROMBOOL]], i8* [[CONV1]], align 1			// CHECK9-NEXT: store i8 [[FROMBOOL]], i8* [[CONV1]], align 1
	// CHECK9-NEXT: [[TMP1:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED]], align 8			// CHECK9-NEXT: [[TMP1:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED]], align 8
	// CHECK9-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32, i32, ...)* bitcast (void (i32, i32, i64)* @.omp_outlined..16 to void (i32, i32, ...)*), i64 [[TMP1]])			// CHECK9-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32, i32, ...)* bitcast (void (i32, i32, i64)* @.omp_outlined..16 to void (i32, i32, ...)*), i64 [[TMP1]])
	// CHECK9-NEXT: ret void			// CHECK9-NEXT: ret void
	//			//
	▲ Show 20 Lines • Show All 42 Lines • ▼ Show 20 Lines
	// CHECK9-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !58			// CHECK9-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !58
	// CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK9: omp.inner.for.body:			// CHECK9: omp.inner.for.body:
	// CHECK9-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !58			// CHECK9-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !58
	// CHECK9-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64			// CHECK9-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
	// CHECK9-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !58			// CHECK9-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !58
	// CHECK9-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK9-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK9-NEXT: [[TMP11:%.]] = load i8, i8 [[CONV]], align 1, !llvm.access.group !58			// CHECK9-NEXT: [[TMP11:%.]] = load i8, i8 [[CONV]], align 8, !llvm.access.group !58
	// CHECK9-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1			// CHECK9-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
	// CHECK9-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE:%.]]			// CHECK9-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE:%.]]
	// CHECK9: omp_if.then:			// CHECK9: omp_if.then:
	// CHECK9-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..17 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !58			// CHECK9-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..17 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !58
	// CHECK9-NEXT: br label [[OMP_IF_END:%.*]]			// CHECK9-NEXT: br label [[OMP_IF_END:%.*]]
	// CHECK9: omp_if.else:			// CHECK9: omp_if.else:
	// CHECK9-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !58			// CHECK9-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !58
	// CHECK9-NEXT: [[TMP12:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !58			// CHECK9-NEXT: [[TMP12:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !58
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	//			//
	// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l47			// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l47
	// CHECK10-SAME: (i64 [[ARG:%.*]]) #[[ATTR1:[0-9]+]] {			// CHECK10-SAME: (i64 [[ARG:%.*]]) #[[ATTR1:[0-9]+]] {
	// CHECK10-NEXT: entry:			// CHECK10-NEXT: entry:
	// CHECK10-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8			// CHECK10-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8
	// CHECK10-NEXT: [[ARG_CASTED:%.*]] = alloca i64, align 8			// CHECK10-NEXT: [[ARG_CASTED:%.*]] = alloca i64, align 8
	// CHECK10-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8			// CHECK10-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8
	// CHECK10-NEXT: [[CONV:%.]] = bitcast i64 [[ARG_ADDR]] to i32*			// CHECK10-NEXT: [[CONV:%.]] = bitcast i64 [[ARG_ADDR]] to i32*
	// CHECK10-NEXT: [[TMP0:%.]] = load i32, i32 [[CONV]], align 4			// CHECK10-NEXT: [[TMP0:%.]] = load i32, i32 [[CONV]], align 8
	// CHECK10-NEXT: [[CONV1:%.]] = bitcast i64 [[ARG_CASTED]] to i32*			// CHECK10-NEXT: [[CONV1:%.]] = bitcast i64 [[ARG_CASTED]] to i32*
	// CHECK10-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4			// CHECK10-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
	// CHECK10-NEXT: [[TMP1:%.]] = load i64, i64 [[ARG_CASTED]], align 8			// CHECK10-NEXT: [[TMP1:%.]] = load i64, i64 [[ARG_CASTED]], align 8
	// CHECK10-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32, i32, ...)* bitcast (void (i32, i32, i64)* @.omp_outlined. to void (i32, i32, ...)*), i64 [[TMP1]])			// CHECK10-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32, i32, ...)* bitcast (void (i32, i32, i64)* @.omp_outlined. to void (i32, i32, ...)*), i64 [[TMP1]])
	// CHECK10-NEXT: ret void			// CHECK10-NEXT: ret void
	//			//
	//			//
	// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined.			// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined.
	Show All 40 Lines
	// CHECK10-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !13			// CHECK10-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !13
	// CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK10: omp.inner.for.body:			// CHECK10: omp.inner.for.body:
	// CHECK10-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !13			// CHECK10-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !13
	// CHECK10-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64			// CHECK10-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
	// CHECK10-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !13			// CHECK10-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !13
	// CHECK10-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK10-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK10-NEXT: [[TMP11:%.]] = load i32, i32 [[CONV]], align 4, !llvm.access.group !13			// CHECK10-NEXT: [[TMP11:%.]] = load i32, i32 [[CONV]], align 8, !llvm.access.group !13
	// CHECK10-NEXT: [[CONV2:%.]] = bitcast i64 [[ARG_CASTED]] to i32*			// CHECK10-NEXT: [[CONV2:%.]] = bitcast i64 [[ARG_CASTED]] to i32*
	// CHECK10-NEXT: store i32 [[TMP11]], i32* [[CONV2]], align 4, !llvm.access.group !13			// CHECK10-NEXT: store i32 [[TMP11]], i32* [[CONV2]], align 4, !llvm.access.group !13
	// CHECK10-NEXT: [[TMP12:%.]] = load i64, i64 [[ARG_CASTED]], align 8, !llvm.access.group !13			// CHECK10-NEXT: [[TMP12:%.]] = load i64, i64 [[ARG_CASTED]], align 8, !llvm.access.group !13
	// CHECK10-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i64)* @.omp_outlined..1 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]], i64 [[TMP12]]), !llvm.access.group !13			// CHECK10-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i64)* @.omp_outlined..1 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]], i64 [[TMP12]]), !llvm.access.group !13
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK10: omp.inner.for.inc:			// CHECK10: omp.inner.for.inc:
	// CHECK10-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13			// CHECK10-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK10-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !13			// CHECK10-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !13
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	// CHECK10-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !17			// CHECK10-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !17
	// CHECK10-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK10-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK10-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK10-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK10: omp.inner.for.body:			// CHECK10: omp.inner.for.body:
	// CHECK10-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !17			// CHECK10-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !17
	// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !17			// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !17
	// CHECK10-NEXT: store i32 0, i32* [[CONV]], align 4, !llvm.access.group !17			// CHECK10-NEXT: store i32 0, i32* [[CONV]], align 8, !llvm.access.group !17
	// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK10: omp.body.continue:			// CHECK10: omp.body.continue:
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK10: omp.inner.for.inc:			// CHECK10: omp.inner.for.inc:
	// CHECK10-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !17			// CHECK10-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !17
	// CHECK10-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK10-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK10-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17			// CHECK10-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]]
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	//			//
	// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92			// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92
	// CHECK10-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {			// CHECK10-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
	// CHECK10-NEXT: entry:			// CHECK10-NEXT: entry:
	// CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8			// CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
	// CHECK10-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8			// CHECK10-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
	// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8			// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
	// CHECK10-NEXT: [[CONV:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__ADDR]] to i8*			// CHECK10-NEXT: [[CONV:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__ADDR]] to i8*
	// CHECK10-NEXT: [[TMP0:%.]] = load i8, i8 [[CONV]], align 1			// CHECK10-NEXT: [[TMP0:%.]] = load i8, i8 [[CONV]], align 8
	// CHECK10-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP0]] to i1			// CHECK10-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP0]] to i1
	// CHECK10-NEXT: [[CONV1:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED]] to i8*			// CHECK10-NEXT: [[CONV1:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED]] to i8*
	// CHECK10-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8			// CHECK10-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
	// CHECK10-NEXT: store i8 [[FROMBOOL]], i8* [[CONV1]], align 1			// CHECK10-NEXT: store i8 [[FROMBOOL]], i8* [[CONV1]], align 1
	// CHECK10-NEXT: [[TMP1:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED]], align 8			// CHECK10-NEXT: [[TMP1:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED]], align 8
	// CHECK10-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32, i32, ...)* bitcast (void (i32, i32, i64)* @.omp_outlined..8 to void (i32, i32, ...)*), i64 [[TMP1]])			// CHECK10-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32, i32, ...)* bitcast (void (i32, i32, i64)* @.omp_outlined..8 to void (i32, i32, ...)*), i64 [[TMP1]])
	// CHECK10-NEXT: ret void			// CHECK10-NEXT: ret void
	//			//
	▲ Show 20 Lines • Show All 42 Lines • ▼ Show 20 Lines
	// CHECK10-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !40			// CHECK10-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !40
	// CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK10: omp.inner.for.body:			// CHECK10: omp.inner.for.body:
	// CHECK10-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !40			// CHECK10-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !40
	// CHECK10-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64			// CHECK10-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
	// CHECK10-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !40			// CHECK10-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !40
	// CHECK10-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK10-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK10-NEXT: [[TMP11:%.]] = load i8, i8 [[CONV]], align 1, !llvm.access.group !40			// CHECK10-NEXT: [[TMP11:%.]] = load i8, i8 [[CONV]], align 8, !llvm.access.group !40
	// CHECK10-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1			// CHECK10-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
	// CHECK10-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE:%.]]			// CHECK10-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE:%.]]
	// CHECK10: omp_if.then:			// CHECK10: omp_if.then:
	// CHECK10-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..9 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !40			// CHECK10-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..9 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !40
	// CHECK10-NEXT: br label [[OMP_IF_END:%.*]]			// CHECK10-NEXT: br label [[OMP_IF_END:%.*]]
	// CHECK10: omp_if.else:			// CHECK10: omp_if.else:
	// CHECK10-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !40			// CHECK10-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !40
	// CHECK10-NEXT: [[TMP12:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !40			// CHECK10-NEXT: [[TMP12:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !40
	▲ Show 20 Lines • Show All 467 Lines • ▼ Show 20 Lines
	//			//
	// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l70			// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l70
	// CHECK10-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {			// CHECK10-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
	// CHECK10-NEXT: entry:			// CHECK10-NEXT: entry:
	// CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8			// CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
	// CHECK10-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8			// CHECK10-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
	// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8			// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
	// CHECK10-NEXT: [[CONV:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__ADDR]] to i8*			// CHECK10-NEXT: [[CONV:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__ADDR]] to i8*
	// CHECK10-NEXT: [[TMP0:%.]] = load i8, i8 [[CONV]], align 1			// CHECK10-NEXT: [[TMP0:%.]] = load i8, i8 [[CONV]], align 8
	// CHECK10-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP0]] to i1			// CHECK10-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP0]] to i1
	// CHECK10-NEXT: [[CONV1:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED]] to i8*			// CHECK10-NEXT: [[CONV1:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED]] to i8*
	// CHECK10-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8			// CHECK10-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
	// CHECK10-NEXT: store i8 [[FROMBOOL]], i8* [[CONV1]], align 1			// CHECK10-NEXT: store i8 [[FROMBOOL]], i8* [[CONV1]], align 1
	// CHECK10-NEXT: [[TMP1:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED]], align 8			// CHECK10-NEXT: [[TMP1:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED]], align 8
	// CHECK10-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32, i32, ...)* bitcast (void (i32, i32, i64)* @.omp_outlined..16 to void (i32, i32, ...)*), i64 [[TMP1]])			// CHECK10-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32, i32, ...)* bitcast (void (i32, i32, i64)* @.omp_outlined..16 to void (i32, i32, ...)*), i64 [[TMP1]])
	// CHECK10-NEXT: ret void			// CHECK10-NEXT: ret void
	//			//
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	// CHECK10-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !58			// CHECK10-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !58
	// CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK10: omp.inner.for.body:			// CHECK10: omp.inner.for.body:
	// CHECK10-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !58			// CHECK10-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !58
	// CHECK10-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64			// CHECK10-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
	// CHECK10-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !58			// CHECK10-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !58
	// CHECK10-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK10-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK10-NEXT: [[TMP11:%.]] = load i8, i8 [[CONV]], align 1, !llvm.access.group !58			// CHECK10-NEXT: [[TMP11:%.]] = load i8, i8 [[CONV]], align 8, !llvm.access.group !58
	// CHECK10-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1			// CHECK10-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
	// CHECK10-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE:%.]]			// CHECK10-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE:%.]]
	// CHECK10: omp_if.then:			// CHECK10: omp_if.then:
	// CHECK10-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..17 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !58			// CHECK10-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..17 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !58
	// CHECK10-NEXT: br label [[OMP_IF_END:%.*]]			// CHECK10-NEXT: br label [[OMP_IF_END:%.*]]
	// CHECK10: omp_if.else:			// CHECK10: omp_if.else:
	// CHECK10-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !58			// CHECK10-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !58
	// CHECK10-NEXT: [[TMP12:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !58			// CHECK10-NEXT: [[TMP12:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !58
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	//			//
	// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l45			// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l45
	// CHECK11-SAME: (i64 [[ARG:%.*]]) #[[ATTR1:[0-9]+]] {			// CHECK11-SAME: (i64 [[ARG:%.*]]) #[[ATTR1:[0-9]+]] {
	// CHECK11-NEXT: entry:			// CHECK11-NEXT: entry:
	// CHECK11-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8			// CHECK11-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8
	// CHECK11-NEXT: [[ARG_CASTED:%.*]] = alloca i64, align 8			// CHECK11-NEXT: [[ARG_CASTED:%.*]] = alloca i64, align 8
	// CHECK11-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8			// CHECK11-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8
	// CHECK11-NEXT: [[CONV:%.]] = bitcast i64 [[ARG_ADDR]] to i32*			// CHECK11-NEXT: [[CONV:%.]] = bitcast i64 [[ARG_ADDR]] to i32*
	// CHECK11-NEXT: [[TMP0:%.]] = load i32, i32 [[CONV]], align 4			// CHECK11-NEXT: [[TMP0:%.]] = load i32, i32 [[CONV]], align 8
	// CHECK11-NEXT: [[CONV1:%.]] = bitcast i64 [[ARG_CASTED]] to i32*			// CHECK11-NEXT: [[CONV1:%.]] = bitcast i64 [[ARG_CASTED]] to i32*
	// CHECK11-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4			// CHECK11-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
	// CHECK11-NEXT: [[TMP1:%.]] = load i64, i64 [[ARG_CASTED]], align 8			// CHECK11-NEXT: [[TMP1:%.]] = load i64, i64 [[ARG_CASTED]], align 8
	// CHECK11-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32, i32, ...)* bitcast (void (i32, i32, i64)* @.omp_outlined. to void (i32, i32, ...)*), i64 [[TMP1]])			// CHECK11-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32, i32, ...)* bitcast (void (i32, i32, i64)* @.omp_outlined. to void (i32, i32, ...)*), i64 [[TMP1]])
	// CHECK11-NEXT: ret void			// CHECK11-NEXT: ret void
	//			//
	//			//
	// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined.			// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined.
	Show All 40 Lines
	// CHECK11-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !13			// CHECK11-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !13
	// CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK11: omp.inner.for.body:			// CHECK11: omp.inner.for.body:
	// CHECK11-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !13			// CHECK11-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !13
	// CHECK11-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64			// CHECK11-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
	// CHECK11-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !13			// CHECK11-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !13
	// CHECK11-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK11-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK11-NEXT: [[TMP11:%.]] = load i32, i32 [[CONV]], align 4, !nontemporal !14, !llvm.access.group !13			// CHECK11-NEXT: [[TMP11:%.]] = load i32, i32 [[CONV]], align 8, !nontemporal !14, !llvm.access.group !13
	// CHECK11-NEXT: [[CONV2:%.]] = bitcast i64 [[ARG_CASTED]] to i32*			// CHECK11-NEXT: [[CONV2:%.]] = bitcast i64 [[ARG_CASTED]] to i32*
	// CHECK11-NEXT: store i32 [[TMP11]], i32* [[CONV2]], align 4, !llvm.access.group !13			// CHECK11-NEXT: store i32 [[TMP11]], i32* [[CONV2]], align 4, !llvm.access.group !13
	// CHECK11-NEXT: [[TMP12:%.]] = load i64, i64 [[ARG_CASTED]], align 8, !llvm.access.group !13			// CHECK11-NEXT: [[TMP12:%.]] = load i64, i64 [[ARG_CASTED]], align 8, !llvm.access.group !13
	// CHECK11-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i64)* @.omp_outlined..1 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]], i64 [[TMP12]]), !llvm.access.group !13			// CHECK11-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i64)* @.omp_outlined..1 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]], i64 [[TMP12]]), !llvm.access.group !13
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK11: omp.inner.for.inc:			// CHECK11: omp.inner.for.inc:
	// CHECK11-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13			// CHECK11-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK11-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !13			// CHECK11-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !13
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	// CHECK11-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !18			// CHECK11-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !18
	// CHECK11-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK11-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK11-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK11-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK11: omp.inner.for.body:			// CHECK11: omp.inner.for.body:
	// CHECK11-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18			// CHECK11-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !18			// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !18
	// CHECK11-NEXT: store i32 0, i32* [[CONV]], align 4, !nontemporal !14, !llvm.access.group !18			// CHECK11-NEXT: store i32 0, i32* [[CONV]], align 8, !nontemporal !14, !llvm.access.group !18
	// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK11: omp.body.continue:			// CHECK11: omp.body.continue:
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK11: omp.inner.for.inc:			// CHECK11: omp.inner.for.inc:
	// CHECK11-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18			// CHECK11-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK11-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK11-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK11-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18			// CHECK11-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]
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	//			//
	// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92			// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92
	// CHECK11-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {			// CHECK11-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
	// CHECK11-NEXT: entry:			// CHECK11-NEXT: entry:
	// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8			// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
	// CHECK11-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8			// CHECK11-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
	// CHECK11-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8			// CHECK11-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
	// CHECK11-NEXT: [[CONV:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__ADDR]] to i8*			// CHECK11-NEXT: [[CONV:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__ADDR]] to i8*
	// CHECK11-NEXT: [[TMP0:%.]] = load i8, i8 [[CONV]], align 1			// CHECK11-NEXT: [[TMP0:%.]] = load i8, i8 [[CONV]], align 8
	// CHECK11-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP0]] to i1			// CHECK11-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP0]] to i1
	// CHECK11-NEXT: [[CONV1:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED]] to i8*			// CHECK11-NEXT: [[CONV1:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED]] to i8*
	// CHECK11-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8			// CHECK11-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
	// CHECK11-NEXT: store i8 [[FROMBOOL]], i8* [[CONV1]], align 1			// CHECK11-NEXT: store i8 [[FROMBOOL]], i8* [[CONV1]], align 1
	// CHECK11-NEXT: [[TMP1:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED]], align 8			// CHECK11-NEXT: [[TMP1:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED]], align 8
	// CHECK11-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32, i32, ...)* bitcast (void (i32, i32, i64)* @.omp_outlined..8 to void (i32, i32, ...)*), i64 [[TMP1]])			// CHECK11-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32, i32, ...)* bitcast (void (i32, i32, i64)* @.omp_outlined..8 to void (i32, i32, ...)*), i64 [[TMP1]])
	// CHECK11-NEXT: ret void			// CHECK11-NEXT: ret void
	//			//
	Show All 34 Lines
	// CHECK11: cond.false:			// CHECK11: cond.false:
	// CHECK11-NEXT: [[TMP3:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK11-NEXT: [[TMP3:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4
	// CHECK11-NEXT: br label [[COND_END]]			// CHECK11-NEXT: br label [[COND_END]]
	// CHECK11: cond.end:			// CHECK11: cond.end:
	// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]			// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
	// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK11-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK11-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK11-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK11-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK11-NEXT: [[TMP5:%.]] = load i8, i8 [[CONV]], align 1			// CHECK11-NEXT: [[TMP5:%.]] = load i8, i8 [[CONV]], align 8
	// CHECK11-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP5]] to i1			// CHECK11-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP5]] to i1
	// CHECK11-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE6:%.]]			// CHECK11-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE6:%.]]
	// CHECK11: omp_if.then:			// CHECK11: omp_if.then:
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK11: omp.inner.for.cond:			// CHECK11: omp.inner.for.cond:
	// CHECK11-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !38			// CHECK11-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !38
	// CHECK11-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !38			// CHECK11-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !38
	// CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK11: omp.inner.for.body:			// CHECK11: omp.inner.for.body:
	// CHECK11-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !38			// CHECK11-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !38
	// CHECK11-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64			// CHECK11-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
	// CHECK11-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !38			// CHECK11-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !38
	// CHECK11-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64			// CHECK11-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
	// CHECK11-NEXT: [[TMP12:%.]] = load i8, i8 [[CONV]], align 1, !llvm.access.group !38			// CHECK11-NEXT: [[TMP12:%.]] = load i8, i8 [[CONV]], align 8, !llvm.access.group !38
	// CHECK11-NEXT: [[TOBOOL2:%.*]] = trunc i8 [[TMP12]] to i1			// CHECK11-NEXT: [[TOBOOL2:%.*]] = trunc i8 [[TMP12]] to i1
	// CHECK11-NEXT: [[CONV3:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED]] to i8*			// CHECK11-NEXT: [[CONV3:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED]] to i8*
	// CHECK11-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL2]] to i8			// CHECK11-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL2]] to i8
	// CHECK11-NEXT: store i8 [[FROMBOOL]], i8* [[CONV3]], align 1, !llvm.access.group !38			// CHECK11-NEXT: store i8 [[FROMBOOL]], i8* [[CONV3]], align 1, !llvm.access.group !38
	// CHECK11-NEXT: [[TMP13:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !38			// CHECK11-NEXT: [[TMP13:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !38
	// CHECK11-NEXT: [[TMP14:%.]] = load i8, i8 [[CONV]], align 1, !llvm.access.group !38			// CHECK11-NEXT: [[TMP14:%.]] = load i8, i8 [[CONV]], align 8, !llvm.access.group !38
	// CHECK11-NEXT: [[TOBOOL4:%.*]] = trunc i8 [[TMP14]] to i1			// CHECK11-NEXT: [[TOBOOL4:%.*]] = trunc i8 [[TMP14]] to i1
	// CHECK11-NEXT: br i1 [[TOBOOL4]], label [[OMP_IF_THEN5:%.]], label [[OMP_IF_ELSE:%.]]			// CHECK11-NEXT: br i1 [[TOBOOL4]], label [[OMP_IF_THEN5:%.]], label [[OMP_IF_ELSE:%.]]
	// CHECK11: omp_if.then5:			// CHECK11: omp_if.then5:
	// CHECK11-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i64)* @.omp_outlined..9 to void (i32, i32, ...)*), i64 [[TMP9]], i64 [[TMP11]], i64 [[TMP13]]), !llvm.access.group !38			// CHECK11-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i64)* @.omp_outlined..9 to void (i32, i32, ...)*), i64 [[TMP9]], i64 [[TMP11]], i64 [[TMP13]]), !llvm.access.group !38
	// CHECK11-NEXT: br label [[OMP_IF_END:%.*]]			// CHECK11-NEXT: br label [[OMP_IF_END:%.*]]
	// CHECK11: omp_if.else:			// CHECK11: omp_if.else:
	// CHECK11-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !38			// CHECK11-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !38
	// CHECK11-NEXT: [[TMP15:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !38			// CHECK11-NEXT: [[TMP15:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !38
	Show All 18 Lines
	// CHECK11-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK11-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4
	// CHECK11-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP18]], [[TMP19]]			// CHECK11-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP18]], [[TMP19]]
	// CHECK11-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY9:%.]], label [[OMP_INNER_FOR_END21:%.]]			// CHECK11-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY9:%.]], label [[OMP_INNER_FOR_END21:%.]]
	// CHECK11: omp.inner.for.body9:			// CHECK11: omp.inner.for.body9:
	// CHECK11-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK11-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK11-NEXT: [[TMP21:%.*]] = zext i32 [[TMP20]] to i64			// CHECK11-NEXT: [[TMP21:%.*]] = zext i32 [[TMP20]] to i64
	// CHECK11-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK11-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4
	// CHECK11-NEXT: [[TMP23:%.*]] = zext i32 [[TMP22]] to i64			// CHECK11-NEXT: [[TMP23:%.*]] = zext i32 [[TMP22]] to i64
	// CHECK11-NEXT: [[TMP24:%.]] = load i8, i8 [[CONV]], align 1			// CHECK11-NEXT: [[TMP24:%.]] = load i8, i8 [[CONV]], align 8
	// CHECK11-NEXT: [[TOBOOL10:%.*]] = trunc i8 [[TMP24]] to i1			// CHECK11-NEXT: [[TOBOOL10:%.*]] = trunc i8 [[TMP24]] to i1
	// CHECK11-NEXT: [[CONV12:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED11]] to i8*			// CHECK11-NEXT: [[CONV12:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED11]] to i8*
	// CHECK11-NEXT: [[FROMBOOL13:%.*]] = zext i1 [[TOBOOL10]] to i8			// CHECK11-NEXT: [[FROMBOOL13:%.*]] = zext i1 [[TOBOOL10]] to i8
	// CHECK11-NEXT: store i8 [[FROMBOOL13]], i8* [[CONV12]], align 1			// CHECK11-NEXT: store i8 [[FROMBOOL13]], i8* [[CONV12]], align 1
	// CHECK11-NEXT: [[TMP25:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED11]], align 8			// CHECK11-NEXT: [[TMP25:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED11]], align 8
	// CHECK11-NEXT: [[TMP26:%.]] = load i8, i8 [[CONV]], align 1			// CHECK11-NEXT: [[TMP26:%.]] = load i8, i8 [[CONV]], align 8
	// CHECK11-NEXT: [[TOBOOL14:%.*]] = trunc i8 [[TMP26]] to i1			// CHECK11-NEXT: [[TOBOOL14:%.*]] = trunc i8 [[TMP26]] to i1
	// CHECK11-NEXT: br i1 [[TOBOOL14]], label [[OMP_IF_THEN15:%.]], label [[OMP_IF_ELSE16:%.]]			// CHECK11-NEXT: br i1 [[TOBOOL14]], label [[OMP_IF_THEN15:%.]], label [[OMP_IF_ELSE16:%.]]
	// CHECK11: omp_if.then15:			// CHECK11: omp_if.then15:
	// CHECK11-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i64)* @.omp_outlined..10 to void (i32, i32, ...)*), i64 [[TMP21]], i64 [[TMP23]], i64 [[TMP25]])			// CHECK11-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i64)* @.omp_outlined..10 to void (i32, i32, ...)*), i64 [[TMP21]], i64 [[TMP23]], i64 [[TMP25]])
	// CHECK11-NEXT: br label [[OMP_IF_END18:%.*]]			// CHECK11-NEXT: br label [[OMP_IF_END18:%.*]]
	// CHECK11: omp_if.else16:			// CHECK11: omp_if.else16:
	// CHECK11-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]])			// CHECK11-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]])
	// CHECK11-NEXT: [[TMP27:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK11-NEXT: [[TMP27:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
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	// CHECK11-NEXT: [[TMP0:%.]] = load i64, i64 [[DOTPREVIOUS_LB__ADDR]], align 8			// CHECK11-NEXT: [[TMP0:%.]] = load i64, i64 [[DOTPREVIOUS_LB__ADDR]], align 8
	// CHECK11-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP0]] to i32			// CHECK11-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP0]] to i32
	// CHECK11-NEXT: [[TMP1:%.]] = load i64, i64 [[DOTPREVIOUS_UB__ADDR]], align 8			// CHECK11-NEXT: [[TMP1:%.]] = load i64, i64 [[DOTPREVIOUS_UB__ADDR]], align 8
	// CHECK11-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32			// CHECK11-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32
	// CHECK11-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4			// CHECK11-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4
	// CHECK11-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4			// CHECK11-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4
	// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4			// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
	// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4			// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
	// CHECK11-NEXT: [[TMP2:%.]] = load i8, i8 [[CONV]], align 1			// CHECK11-NEXT: [[TMP2:%.]] = load i8, i8 [[CONV]], align 8
	// CHECK11-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1			// CHECK11-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1
	// CHECK11-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE:%.]]			// CHECK11-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE:%.]]
	// CHECK11: omp_if.then:			// CHECK11: omp_if.then:
	// CHECK11-NEXT: [[TMP3:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK11-NEXT: [[TMP3:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK11-NEXT: [[TMP4:%.]] = load i32, i32 [[TMP3]], align 4			// CHECK11-NEXT: [[TMP4:%.]] = load i32, i32 [[TMP3]], align 4
	// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)			// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
	// CHECK11-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK11-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 99			// CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 99
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	// CHECK11-NEXT: [[TMP0:%.]] = load i64, i64 [[DOTPREVIOUS_LB__ADDR]], align 8			// CHECK11-NEXT: [[TMP0:%.]] = load i64, i64 [[DOTPREVIOUS_LB__ADDR]], align 8
	// CHECK11-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP0]] to i32			// CHECK11-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP0]] to i32
	// CHECK11-NEXT: [[TMP1:%.]] = load i64, i64 [[DOTPREVIOUS_UB__ADDR]], align 8			// CHECK11-NEXT: [[TMP1:%.]] = load i64, i64 [[DOTPREVIOUS_UB__ADDR]], align 8
	// CHECK11-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32			// CHECK11-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32
	// CHECK11-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4			// CHECK11-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4
	// CHECK11-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4			// CHECK11-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4
	// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4			// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
	// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4			// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
	// CHECK11-NEXT: [[TMP2:%.]] = load i8, i8 [[CONV]], align 1			// CHECK11-NEXT: [[TMP2:%.]] = load i8, i8 [[CONV]], align 8
	// CHECK11-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1			// CHECK11-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1
	// CHECK11-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE:%.]]			// CHECK11-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE:%.]]
	// CHECK11: omp_if.then:			// CHECK11: omp_if.then:
	// CHECK11-NEXT: [[TMP3:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK11-NEXT: [[TMP3:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK11-NEXT: [[TMP4:%.]] = load i32, i32 [[TMP3]], align 4			// CHECK11-NEXT: [[TMP4:%.]] = load i32, i32 [[TMP3]], align 4
	// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)			// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
	// CHECK11-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK11-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 99			// CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 99
	▲ Show 20 Lines • Show All 451 Lines • ▼ Show 20 Lines
	//			//
	// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l70			// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l70
	// CHECK11-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {			// CHECK11-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
	// CHECK11-NEXT: entry:			// CHECK11-NEXT: entry:
	// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8			// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
	// CHECK11-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8			// CHECK11-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
	// CHECK11-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8			// CHECK11-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
	// CHECK11-NEXT: [[CONV:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__ADDR]] to i8*			// CHECK11-NEXT: [[CONV:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__ADDR]] to i8*
	// CHECK11-NEXT: [[TMP0:%.]] = load i8, i8 [[CONV]], align 1			// CHECK11-NEXT: [[TMP0:%.]] = load i8, i8 [[CONV]], align 8
	// CHECK11-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP0]] to i1			// CHECK11-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP0]] to i1
	// CHECK11-NEXT: [[CONV1:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED]] to i8*			// CHECK11-NEXT: [[CONV1:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED]] to i8*
	// CHECK11-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8			// CHECK11-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
	// CHECK11-NEXT: store i8 [[FROMBOOL]], i8* [[CONV1]], align 1			// CHECK11-NEXT: store i8 [[FROMBOOL]], i8* [[CONV1]], align 1
	// CHECK11-NEXT: [[TMP1:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED]], align 8			// CHECK11-NEXT: [[TMP1:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED]], align 8
	// CHECK11-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32, i32, ...)* bitcast (void (i32, i32, i64)* @.omp_outlined..17 to void (i32, i32, ...)*), i64 [[TMP1]])			// CHECK11-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32, i32, ...)* bitcast (void (i32, i32, i64)* @.omp_outlined..17 to void (i32, i32, ...)*), i64 [[TMP1]])
	// CHECK11-NEXT: ret void			// CHECK11-NEXT: ret void
	//			//
	▲ Show 20 Lines • Show All 42 Lines • ▼ Show 20 Lines
	// CHECK11-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !58			// CHECK11-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !58
	// CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK11: omp.inner.for.body:			// CHECK11: omp.inner.for.body:
	// CHECK11-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !58			// CHECK11-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !58
	// CHECK11-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64			// CHECK11-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
	// CHECK11-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !58			// CHECK11-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !58
	// CHECK11-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK11-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK11-NEXT: [[TMP11:%.]] = load i8, i8 [[CONV]], align 1, !llvm.access.group !58			// CHECK11-NEXT: [[TMP11:%.]] = load i8, i8 [[CONV]], align 8, !llvm.access.group !58
	// CHECK11-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1			// CHECK11-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
	// CHECK11-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE:%.]]			// CHECK11-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE:%.]]
	// CHECK11: omp_if.then:			// CHECK11: omp_if.then:
	// CHECK11-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..18 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !58			// CHECK11-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..18 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !58
	// CHECK11-NEXT: br label [[OMP_IF_END:%.*]]			// CHECK11-NEXT: br label [[OMP_IF_END:%.*]]
	// CHECK11: omp_if.else:			// CHECK11: omp_if.else:
	// CHECK11-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !58			// CHECK11-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !58
	// CHECK11-NEXT: [[TMP12:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !58			// CHECK11-NEXT: [[TMP12:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !58
	▲ Show 20 Lines • Show All 152 Lines • ▼ Show 20 Lines
	//			//
	// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l45			// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l45
	// CHECK12-SAME: (i64 [[ARG:%.*]]) #[[ATTR1:[0-9]+]] {			// CHECK12-SAME: (i64 [[ARG:%.*]]) #[[ATTR1:[0-9]+]] {
	// CHECK12-NEXT: entry:			// CHECK12-NEXT: entry:
	// CHECK12-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8			// CHECK12-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8
	// CHECK12-NEXT: [[ARG_CASTED:%.*]] = alloca i64, align 8			// CHECK12-NEXT: [[ARG_CASTED:%.*]] = alloca i64, align 8
	// CHECK12-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8			// CHECK12-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8
	// CHECK12-NEXT: [[CONV:%.]] = bitcast i64 [[ARG_ADDR]] to i32*			// CHECK12-NEXT: [[CONV:%.]] = bitcast i64 [[ARG_ADDR]] to i32*
	// CHECK12-NEXT: [[TMP0:%.]] = load i32, i32 [[CONV]], align 4			// CHECK12-NEXT: [[TMP0:%.]] = load i32, i32 [[CONV]], align 8
	// CHECK12-NEXT: [[CONV1:%.]] = bitcast i64 [[ARG_CASTED]] to i32*			// CHECK12-NEXT: [[CONV1:%.]] = bitcast i64 [[ARG_CASTED]] to i32*
	// CHECK12-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4			// CHECK12-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
	// CHECK12-NEXT: [[TMP1:%.]] = load i64, i64 [[ARG_CASTED]], align 8			// CHECK12-NEXT: [[TMP1:%.]] = load i64, i64 [[ARG_CASTED]], align 8
	// CHECK12-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32, i32, ...)* bitcast (void (i32, i32, i64)* @.omp_outlined. to void (i32, i32, ...)*), i64 [[TMP1]])			// CHECK12-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32, i32, ...)* bitcast (void (i32, i32, i64)* @.omp_outlined. to void (i32, i32, ...)*), i64 [[TMP1]])
	// CHECK12-NEXT: ret void			// CHECK12-NEXT: ret void
	//			//
	//			//
	// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined.			// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined.
	Show All 40 Lines
	// CHECK12-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !13			// CHECK12-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !13
	// CHECK12-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK12-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK12-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK12-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK12: omp.inner.for.body:			// CHECK12: omp.inner.for.body:
	// CHECK12-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !13			// CHECK12-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !13
	// CHECK12-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64			// CHECK12-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
	// CHECK12-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !13			// CHECK12-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !13
	// CHECK12-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK12-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK12-NEXT: [[TMP11:%.]] = load i32, i32 [[CONV]], align 4, !nontemporal !14, !llvm.access.group !13			// CHECK12-NEXT: [[TMP11:%.]] = load i32, i32 [[CONV]], align 8, !nontemporal !14, !llvm.access.group !13
	// CHECK12-NEXT: [[CONV2:%.]] = bitcast i64 [[ARG_CASTED]] to i32*			// CHECK12-NEXT: [[CONV2:%.]] = bitcast i64 [[ARG_CASTED]] to i32*
	// CHECK12-NEXT: store i32 [[TMP11]], i32* [[CONV2]], align 4, !llvm.access.group !13			// CHECK12-NEXT: store i32 [[TMP11]], i32* [[CONV2]], align 4, !llvm.access.group !13
	// CHECK12-NEXT: [[TMP12:%.]] = load i64, i64 [[ARG_CASTED]], align 8, !llvm.access.group !13			// CHECK12-NEXT: [[TMP12:%.]] = load i64, i64 [[ARG_CASTED]], align 8, !llvm.access.group !13
	// CHECK12-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i64)* @.omp_outlined..1 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]], i64 [[TMP12]]), !llvm.access.group !13			// CHECK12-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i64)* @.omp_outlined..1 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]], i64 [[TMP12]]), !llvm.access.group !13
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK12: omp.inner.for.inc:			// CHECK12: omp.inner.for.inc:
	// CHECK12-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13			// CHECK12-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK12-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !13			// CHECK12-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !13
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	// CHECK12-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !18			// CHECK12-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !18
	// CHECK12-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK12-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK12-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK12-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK12: omp.inner.for.body:			// CHECK12: omp.inner.for.body:
	// CHECK12-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18			// CHECK12-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !18			// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !18
	// CHECK12-NEXT: store i32 0, i32* [[CONV]], align 4, !nontemporal !14, !llvm.access.group !18			// CHECK12-NEXT: store i32 0, i32* [[CONV]], align 8, !nontemporal !14, !llvm.access.group !18
	// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK12: omp.body.continue:			// CHECK12: omp.body.continue:
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK12: omp.inner.for.inc:			// CHECK12: omp.inner.for.inc:
	// CHECK12-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18			// CHECK12-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK12-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK12-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK12-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18			// CHECK12-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]
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	//			//
	// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92			// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92
	// CHECK12-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {			// CHECK12-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
	// CHECK12-NEXT: entry:			// CHECK12-NEXT: entry:
	// CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8			// CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
	// CHECK12-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8			// CHECK12-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
	// CHECK12-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8			// CHECK12-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
	// CHECK12-NEXT: [[CONV:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__ADDR]] to i8*			// CHECK12-NEXT: [[CONV:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__ADDR]] to i8*
	// CHECK12-NEXT: [[TMP0:%.]] = load i8, i8 [[CONV]], align 1			// CHECK12-NEXT: [[TMP0:%.]] = load i8, i8 [[CONV]], align 8
	// CHECK12-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP0]] to i1			// CHECK12-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP0]] to i1
	// CHECK12-NEXT: [[CONV1:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED]] to i8*			// CHECK12-NEXT: [[CONV1:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED]] to i8*
	// CHECK12-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8			// CHECK12-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
	// CHECK12-NEXT: store i8 [[FROMBOOL]], i8* [[CONV1]], align 1			// CHECK12-NEXT: store i8 [[FROMBOOL]], i8* [[CONV1]], align 1
	// CHECK12-NEXT: [[TMP1:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED]], align 8			// CHECK12-NEXT: [[TMP1:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED]], align 8
	// CHECK12-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32, i32, ...)* bitcast (void (i32, i32, i64)* @.omp_outlined..8 to void (i32, i32, ...)*), i64 [[TMP1]])			// CHECK12-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32, i32, ...)* bitcast (void (i32, i32, i64)* @.omp_outlined..8 to void (i32, i32, ...)*), i64 [[TMP1]])
	// CHECK12-NEXT: ret void			// CHECK12-NEXT: ret void
	//			//
	Show All 34 Lines
	// CHECK12: cond.false:			// CHECK12: cond.false:
	// CHECK12-NEXT: [[TMP3:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK12-NEXT: [[TMP3:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4
	// CHECK12-NEXT: br label [[COND_END]]			// CHECK12-NEXT: br label [[COND_END]]
	// CHECK12: cond.end:			// CHECK12: cond.end:
	// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]			// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
	// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK12-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK12-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK12-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK12-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK12-NEXT: [[TMP5:%.]] = load i8, i8 [[CONV]], align 1			// CHECK12-NEXT: [[TMP5:%.]] = load i8, i8 [[CONV]], align 8
	// CHECK12-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP5]] to i1			// CHECK12-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP5]] to i1
	// CHECK12-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE6:%.]]			// CHECK12-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE6:%.]]
	// CHECK12: omp_if.then:			// CHECK12: omp_if.then:
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK12: omp.inner.for.cond:			// CHECK12: omp.inner.for.cond:
	// CHECK12-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !38			// CHECK12-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !38
	// CHECK12-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !38			// CHECK12-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !38
	// CHECK12-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK12-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK12-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK12-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK12: omp.inner.for.body:			// CHECK12: omp.inner.for.body:
	// CHECK12-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !38			// CHECK12-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !38
	// CHECK12-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64			// CHECK12-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
	// CHECK12-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !38			// CHECK12-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !38
	// CHECK12-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64			// CHECK12-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
	// CHECK12-NEXT: [[TMP12:%.]] = load i8, i8 [[CONV]], align 1, !llvm.access.group !38			// CHECK12-NEXT: [[TMP12:%.]] = load i8, i8 [[CONV]], align 8, !llvm.access.group !38
	// CHECK12-NEXT: [[TOBOOL2:%.*]] = trunc i8 [[TMP12]] to i1			// CHECK12-NEXT: [[TOBOOL2:%.*]] = trunc i8 [[TMP12]] to i1
	// CHECK12-NEXT: [[CONV3:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED]] to i8*			// CHECK12-NEXT: [[CONV3:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED]] to i8*
	// CHECK12-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL2]] to i8			// CHECK12-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL2]] to i8
	// CHECK12-NEXT: store i8 [[FROMBOOL]], i8* [[CONV3]], align 1, !llvm.access.group !38			// CHECK12-NEXT: store i8 [[FROMBOOL]], i8* [[CONV3]], align 1, !llvm.access.group !38
	// CHECK12-NEXT: [[TMP13:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !38			// CHECK12-NEXT: [[TMP13:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !38
	// CHECK12-NEXT: [[TMP14:%.]] = load i8, i8 [[CONV]], align 1, !llvm.access.group !38			// CHECK12-NEXT: [[TMP14:%.]] = load i8, i8 [[CONV]], align 8, !llvm.access.group !38
	// CHECK12-NEXT: [[TOBOOL4:%.*]] = trunc i8 [[TMP14]] to i1			// CHECK12-NEXT: [[TOBOOL4:%.*]] = trunc i8 [[TMP14]] to i1
	// CHECK12-NEXT: br i1 [[TOBOOL4]], label [[OMP_IF_THEN5:%.]], label [[OMP_IF_ELSE:%.]]			// CHECK12-NEXT: br i1 [[TOBOOL4]], label [[OMP_IF_THEN5:%.]], label [[OMP_IF_ELSE:%.]]
	// CHECK12: omp_if.then5:			// CHECK12: omp_if.then5:
	// CHECK12-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i64)* @.omp_outlined..9 to void (i32, i32, ...)*), i64 [[TMP9]], i64 [[TMP11]], i64 [[TMP13]]), !llvm.access.group !38			// CHECK12-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i64)* @.omp_outlined..9 to void (i32, i32, ...)*), i64 [[TMP9]], i64 [[TMP11]], i64 [[TMP13]]), !llvm.access.group !38
	// CHECK12-NEXT: br label [[OMP_IF_END:%.*]]			// CHECK12-NEXT: br label [[OMP_IF_END:%.*]]
	// CHECK12: omp_if.else:			// CHECK12: omp_if.else:
	// CHECK12-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !38			// CHECK12-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !38
	// CHECK12-NEXT: [[TMP15:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !38			// CHECK12-NEXT: [[TMP15:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !38
	Show All 18 Lines
	// CHECK12-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK12-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4
	// CHECK12-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP18]], [[TMP19]]			// CHECK12-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP18]], [[TMP19]]
	// CHECK12-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY9:%.]], label [[OMP_INNER_FOR_END21:%.]]			// CHECK12-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY9:%.]], label [[OMP_INNER_FOR_END21:%.]]
	// CHECK12: omp.inner.for.body9:			// CHECK12: omp.inner.for.body9:
	// CHECK12-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK12-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK12-NEXT: [[TMP21:%.*]] = zext i32 [[TMP20]] to i64			// CHECK12-NEXT: [[TMP21:%.*]] = zext i32 [[TMP20]] to i64
	// CHECK12-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK12-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4
	// CHECK12-NEXT: [[TMP23:%.*]] = zext i32 [[TMP22]] to i64			// CHECK12-NEXT: [[TMP23:%.*]] = zext i32 [[TMP22]] to i64
	// CHECK12-NEXT: [[TMP24:%.]] = load i8, i8 [[CONV]], align 1			// CHECK12-NEXT: [[TMP24:%.]] = load i8, i8 [[CONV]], align 8
	// CHECK12-NEXT: [[TOBOOL10:%.*]] = trunc i8 [[TMP24]] to i1			// CHECK12-NEXT: [[TOBOOL10:%.*]] = trunc i8 [[TMP24]] to i1
	// CHECK12-NEXT: [[CONV12:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED11]] to i8*			// CHECK12-NEXT: [[CONV12:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED11]] to i8*
	// CHECK12-NEXT: [[FROMBOOL13:%.*]] = zext i1 [[TOBOOL10]] to i8			// CHECK12-NEXT: [[FROMBOOL13:%.*]] = zext i1 [[TOBOOL10]] to i8
	// CHECK12-NEXT: store i8 [[FROMBOOL13]], i8* [[CONV12]], align 1			// CHECK12-NEXT: store i8 [[FROMBOOL13]], i8* [[CONV12]], align 1
	// CHECK12-NEXT: [[TMP25:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED11]], align 8			// CHECK12-NEXT: [[TMP25:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED11]], align 8
	// CHECK12-NEXT: [[TMP26:%.]] = load i8, i8 [[CONV]], align 1			// CHECK12-NEXT: [[TMP26:%.]] = load i8, i8 [[CONV]], align 8
	// CHECK12-NEXT: [[TOBOOL14:%.*]] = trunc i8 [[TMP26]] to i1			// CHECK12-NEXT: [[TOBOOL14:%.*]] = trunc i8 [[TMP26]] to i1
	// CHECK12-NEXT: br i1 [[TOBOOL14]], label [[OMP_IF_THEN15:%.]], label [[OMP_IF_ELSE16:%.]]			// CHECK12-NEXT: br i1 [[TOBOOL14]], label [[OMP_IF_THEN15:%.]], label [[OMP_IF_ELSE16:%.]]
	// CHECK12: omp_if.then15:			// CHECK12: omp_if.then15:
	// CHECK12-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i64)* @.omp_outlined..10 to void (i32, i32, ...)*), i64 [[TMP21]], i64 [[TMP23]], i64 [[TMP25]])			// CHECK12-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i64)* @.omp_outlined..10 to void (i32, i32, ...)*), i64 [[TMP21]], i64 [[TMP23]], i64 [[TMP25]])
	// CHECK12-NEXT: br label [[OMP_IF_END18:%.*]]			// CHECK12-NEXT: br label [[OMP_IF_END18:%.*]]
	// CHECK12: omp_if.else16:			// CHECK12: omp_if.else16:
	// CHECK12-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]])			// CHECK12-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]])
	// CHECK12-NEXT: [[TMP27:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK12-NEXT: [[TMP27:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	▲ Show 20 Lines • Show All 51 Lines • ▼ Show 20 Lines
	// CHECK12-NEXT: [[TMP0:%.]] = load i64, i64 [[DOTPREVIOUS_LB__ADDR]], align 8			// CHECK12-NEXT: [[TMP0:%.]] = load i64, i64 [[DOTPREVIOUS_LB__ADDR]], align 8
	// CHECK12-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP0]] to i32			// CHECK12-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP0]] to i32
	// CHECK12-NEXT: [[TMP1:%.]] = load i64, i64 [[DOTPREVIOUS_UB__ADDR]], align 8			// CHECK12-NEXT: [[TMP1:%.]] = load i64, i64 [[DOTPREVIOUS_UB__ADDR]], align 8
	// CHECK12-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32			// CHECK12-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32
	// CHECK12-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4			// CHECK12-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4
	// CHECK12-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4			// CHECK12-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4
	// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4			// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
	// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4			// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
	// CHECK12-NEXT: [[TMP2:%.]] = load i8, i8 [[CONV]], align 1			// CHECK12-NEXT: [[TMP2:%.]] = load i8, i8 [[CONV]], align 8
	// CHECK12-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1			// CHECK12-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1
	// CHECK12-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE:%.]]			// CHECK12-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE:%.]]
	// CHECK12: omp_if.then:			// CHECK12: omp_if.then:
	// CHECK12-NEXT: [[TMP3:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK12-NEXT: [[TMP3:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK12-NEXT: [[TMP4:%.]] = load i32, i32 [[TMP3]], align 4			// CHECK12-NEXT: [[TMP4:%.]] = load i32, i32 [[TMP3]], align 4
	// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)			// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
	// CHECK12-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK12-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 99			// CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 99
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	// CHECK12-NEXT: [[TMP0:%.]] = load i64, i64 [[DOTPREVIOUS_LB__ADDR]], align 8			// CHECK12-NEXT: [[TMP0:%.]] = load i64, i64 [[DOTPREVIOUS_LB__ADDR]], align 8
	// CHECK12-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP0]] to i32			// CHECK12-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP0]] to i32
	// CHECK12-NEXT: [[TMP1:%.]] = load i64, i64 [[DOTPREVIOUS_UB__ADDR]], align 8			// CHECK12-NEXT: [[TMP1:%.]] = load i64, i64 [[DOTPREVIOUS_UB__ADDR]], align 8
	// CHECK12-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32			// CHECK12-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32
	// CHECK12-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4			// CHECK12-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4
	// CHECK12-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4			// CHECK12-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4
	// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4			// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
	// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4			// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
	// CHECK12-NEXT: [[TMP2:%.]] = load i8, i8 [[CONV]], align 1			// CHECK12-NEXT: [[TMP2:%.]] = load i8, i8 [[CONV]], align 8
	// CHECK12-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1			// CHECK12-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1
	// CHECK12-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE:%.]]			// CHECK12-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE:%.]]
	// CHECK12: omp_if.then:			// CHECK12: omp_if.then:
	// CHECK12-NEXT: [[TMP3:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK12-NEXT: [[TMP3:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK12-NEXT: [[TMP4:%.]] = load i32, i32 [[TMP3]], align 4			// CHECK12-NEXT: [[TMP4:%.]] = load i32, i32 [[TMP3]], align 4
	// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)			// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
	// CHECK12-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK12-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 99			// CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 99
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	//			//
	// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l70			// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l70
	// CHECK12-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {			// CHECK12-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
	// CHECK12-NEXT: entry:			// CHECK12-NEXT: entry:
	// CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8			// CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
	// CHECK12-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8			// CHECK12-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
	// CHECK12-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8			// CHECK12-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
	// CHECK12-NEXT: [[CONV:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__ADDR]] to i8*			// CHECK12-NEXT: [[CONV:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__ADDR]] to i8*
	// CHECK12-NEXT: [[TMP0:%.]] = load i8, i8 [[CONV]], align 1			// CHECK12-NEXT: [[TMP0:%.]] = load i8, i8 [[CONV]], align 8
	// CHECK12-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP0]] to i1			// CHECK12-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP0]] to i1
	// CHECK12-NEXT: [[CONV1:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED]] to i8*			// CHECK12-NEXT: [[CONV1:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED]] to i8*
	// CHECK12-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8			// CHECK12-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
	// CHECK12-NEXT: store i8 [[FROMBOOL]], i8* [[CONV1]], align 1			// CHECK12-NEXT: store i8 [[FROMBOOL]], i8* [[CONV1]], align 1
	// CHECK12-NEXT: [[TMP1:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED]], align 8			// CHECK12-NEXT: [[TMP1:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED]], align 8
	// CHECK12-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32, i32, ...)* bitcast (void (i32, i32, i64)* @.omp_outlined..17 to void (i32, i32, ...)*), i64 [[TMP1]])			// CHECK12-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32, i32, ...)* bitcast (void (i32, i32, i64)* @.omp_outlined..17 to void (i32, i32, ...)*), i64 [[TMP1]])
	// CHECK12-NEXT: ret void			// CHECK12-NEXT: ret void
	//			//
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	// CHECK12-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !58			// CHECK12-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !58
	// CHECK12-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK12-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK12-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK12-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK12: omp.inner.for.body:			// CHECK12: omp.inner.for.body:
	// CHECK12-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !58			// CHECK12-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !58
	// CHECK12-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64			// CHECK12-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
	// CHECK12-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !58			// CHECK12-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !58
	// CHECK12-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK12-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK12-NEXT: [[TMP11:%.]] = load i8, i8 [[CONV]], align 1, !llvm.access.group !58			// CHECK12-NEXT: [[TMP11:%.]] = load i8, i8 [[CONV]], align 8, !llvm.access.group !58
	// CHECK12-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1			// CHECK12-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
	// CHECK12-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE:%.]]			// CHECK12-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE:%.]]
	// CHECK12: omp_if.then:			// CHECK12: omp_if.then:
	// CHECK12-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..18 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !58			// CHECK12-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..18 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !58
	// CHECK12-NEXT: br label [[OMP_IF_END:%.*]]			// CHECK12-NEXT: br label [[OMP_IF_END:%.*]]
	// CHECK12: omp_if.else:			// CHECK12: omp_if.else:
	// CHECK12-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !58			// CHECK12-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !58
	// CHECK12-NEXT: [[TMP12:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !58			// CHECK12-NEXT: [[TMP12:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !58
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clang/test/OpenMP/target_teams_distribute_parallel_for_simd_proc_bind_codegen.cpp

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	// CHECK1-NEXT: br label [[COND_END]]			// CHECK1-NEXT: br label [[COND_END]]
	// CHECK1: cond.end:			// CHECK1: cond.end:
	// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 999, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]			// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 999, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
	// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK1-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK1-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK1: omp.inner.for.cond:			// CHECK1: omp.inner.for.cond:
	// CHECK1-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !6
	// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !6
	// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK1: omp.inner.for.body:			// CHECK1: omp.inner.for.body:
	// CHECK1-NEXT: call void @__kmpc_push_proc_bind(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 4)			// CHECK1-NEXT: call void @__kmpc_push_proc_bind(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 4), !llvm.access.group !6
	// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !6
	// CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64			// CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
	// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !6
	// CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK1-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..1 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]])			// CHECK1-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..1 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !6
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK1: omp.inner.for.inc:			// CHECK1: omp.inner.for.inc:
	// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !6
	// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !6
	// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]			// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
	// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]
	// CHECK1: omp.inner.for.end:			// CHECK1: omp.inner.for.end:
	// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK1: omp.loop.exit:			// CHECK1: omp.loop.exit:
	// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])			// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
	// CHECK1-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK1-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK1-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0			// CHECK1-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
	// CHECK1-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK1-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK1: .omp.final.then:			// CHECK1: .omp.final.then:
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	// CHECK1-NEXT: br label [[COND_END]]			// CHECK1-NEXT: br label [[COND_END]]
	// CHECK1: cond.end:			// CHECK1: cond.end:
	// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 999, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]			// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 999, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
	// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK1-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK1: omp.inner.for.cond:			// CHECK1: omp.inner.for.cond:
	// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK1-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK1-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !10
	// CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK1: omp.inner.for.body:			// CHECK1: omp.inner.for.body:
	// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10
	// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK1: omp.body.continue:			// CHECK1: omp.body.continue:
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK1: omp.inner.for.inc:			// CHECK1: omp.inner.for.inc:
	// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]
	// CHECK1: omp.inner.for.end:			// CHECK1: omp.inner.for.end:
	// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK1: omp.loop.exit:			// CHECK1: omp.loop.exit:
	// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])			// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
	// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK1-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK1-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK1-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK1-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK1: .omp.final.then:			// CHECK1: .omp.final.then:
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	// CHECK1-NEXT: br label [[COND_END]]			// CHECK1-NEXT: br label [[COND_END]]
	// CHECK1: cond.end:			// CHECK1: cond.end:
	// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 999, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]			// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 999, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
	// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK1-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK1-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK1: omp.inner.for.cond:			// CHECK1: omp.inner.for.cond:
	// CHECK1-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15
	// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK1: omp.inner.for.body:			// CHECK1: omp.inner.for.body:
	// CHECK1-NEXT: call void @__kmpc_push_proc_bind(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 3)			// CHECK1-NEXT: call void @__kmpc_push_proc_bind(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 3), !llvm.access.group !15
	// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !15
	// CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64			// CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
	// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15
	// CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK1-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..3 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]])			// CHECK1-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..3 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !15
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK1: omp.inner.for.inc:			// CHECK1: omp.inner.for.inc:
	// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !15
	// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]			// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
	// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]]
	// CHECK1: omp.inner.for.end:			// CHECK1: omp.inner.for.end:
	// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK1: omp.loop.exit:			// CHECK1: omp.loop.exit:
	// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])			// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
	// CHECK1-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK1-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK1-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0			// CHECK1-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
	// CHECK1-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK1-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK1: .omp.final.then:			// CHECK1: .omp.final.then:
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	// CHECK1-NEXT: br label [[COND_END]]			// CHECK1-NEXT: br label [[COND_END]]
	// CHECK1: cond.end:			// CHECK1: cond.end:
	// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 999, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]			// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 999, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
	// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK1-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK1: omp.inner.for.cond:			// CHECK1: omp.inner.for.cond:
	// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK1-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK1-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !18
	// CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK1: omp.inner.for.body:			// CHECK1: omp.inner.for.body:
	// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !18
	// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK1: omp.body.continue:			// CHECK1: omp.body.continue:
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK1: omp.inner.for.inc:			// CHECK1: omp.inner.for.inc:
	// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]
	// CHECK1: omp.inner.for.end:			// CHECK1: omp.inner.for.end:
	// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK1: omp.loop.exit:			// CHECK1: omp.loop.exit:
	// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])			// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
	// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK1-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK1-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK1-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK1-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK1: .omp.final.then:			// CHECK1: .omp.final.then:
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	// CHECK1-NEXT: br label [[COND_END]]			// CHECK1-NEXT: br label [[COND_END]]
	// CHECK1: cond.end:			// CHECK1: cond.end:
	// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 999, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]			// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 999, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
	// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK1-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK1-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK1: omp.inner.for.cond:			// CHECK1: omp.inner.for.cond:
	// CHECK1-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !21
	// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !21
	// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK1: omp.inner.for.body:			// CHECK1: omp.inner.for.body:
	// CHECK1-NEXT: call void @__kmpc_push_proc_bind(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 2)			// CHECK1-NEXT: call void @__kmpc_push_proc_bind(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 2), !llvm.access.group !21
	// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !21
	// CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64			// CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
	// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !21
	// CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK1-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..5 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]])			// CHECK1-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..5 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !21
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK1: omp.inner.for.inc:			// CHECK1: omp.inner.for.inc:
	// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !21
	// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !21
	// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]			// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
	// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]]
	// CHECK1: omp.inner.for.end:			// CHECK1: omp.inner.for.end:
	// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK1: omp.loop.exit:			// CHECK1: omp.loop.exit:
	// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])			// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
	// CHECK1-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK1-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK1-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0			// CHECK1-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
	// CHECK1-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK1-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK1: .omp.final.then:			// CHECK1: .omp.final.then:
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	// CHECK1-NEXT: br label [[COND_END]]			// CHECK1-NEXT: br label [[COND_END]]
	// CHECK1: cond.end:			// CHECK1: cond.end:
	// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 999, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]			// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 999, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
	// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK1-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK1: omp.inner.for.cond:			// CHECK1: omp.inner.for.cond:
	// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !24
	// CHECK1-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK1-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !24
	// CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK1: omp.inner.for.body:			// CHECK1: omp.inner.for.body:
	// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !24
	// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !24
	// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK1: omp.body.continue:			// CHECK1: omp.body.continue:
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK1: omp.inner.for.inc:			// CHECK1: omp.inner.for.inc:
	// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !24
	// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]]
	// CHECK1: omp.inner.for.end:			// CHECK1: omp.inner.for.end:
	// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK1: omp.loop.exit:			// CHECK1: omp.loop.exit:
	// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])			// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
	// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK1-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK1-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK1-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK1-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK1: .omp.final.then:			// CHECK1: .omp.final.then:
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	// CHECK2-NEXT: br label [[COND_END]]			// CHECK2-NEXT: br label [[COND_END]]
	// CHECK2: cond.end:			// CHECK2: cond.end:
	// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 999, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]			// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 999, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
	// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK2-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK2-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK2-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK2: omp.inner.for.cond:			// CHECK2: omp.inner.for.cond:
	// CHECK2-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !6
	// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !6
	// CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK2: omp.inner.for.body:			// CHECK2: omp.inner.for.body:
	// CHECK2-NEXT: call void @__kmpc_push_proc_bind(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 4)			// CHECK2-NEXT: call void @__kmpc_push_proc_bind(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 4), !llvm.access.group !6
	// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !6
	// CHECK2-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64			// CHECK2-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
	// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !6
	// CHECK2-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK2-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK2-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..1 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]])			// CHECK2-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..1 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !6
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK2: omp.inner.for.inc:			// CHECK2: omp.inner.for.inc:
	// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !6
	// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !6
	// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]			// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
	// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]
	// CHECK2: omp.inner.for.end:			// CHECK2: omp.inner.for.end:
	// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK2: omp.loop.exit:			// CHECK2: omp.loop.exit:
	// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])			// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
	// CHECK2-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK2-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK2-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0			// CHECK2-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
	// CHECK2-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK2-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK2: .omp.final.then:			// CHECK2: .omp.final.then:
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	// CHECK2-NEXT: br label [[COND_END]]			// CHECK2-NEXT: br label [[COND_END]]
	// CHECK2: cond.end:			// CHECK2: cond.end:
	// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 999, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]			// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 999, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
	// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK2-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK2: omp.inner.for.cond:			// CHECK2: omp.inner.for.cond:
	// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK2-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK2-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !10
	// CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK2: omp.inner.for.body:			// CHECK2: omp.inner.for.body:
	// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10
	// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK2: omp.body.continue:			// CHECK2: omp.body.continue:
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK2: omp.inner.for.inc:			// CHECK2: omp.inner.for.inc:
	// CHECK2-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]
	// CHECK2: omp.inner.for.end:			// CHECK2: omp.inner.for.end:
	// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK2: omp.loop.exit:			// CHECK2: omp.loop.exit:
	// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])			// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
	// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK2-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK2-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK2-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK2-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK2: .omp.final.then:			// CHECK2: .omp.final.then:
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	// CHECK2-NEXT: br label [[COND_END]]			// CHECK2-NEXT: br label [[COND_END]]
	// CHECK2: cond.end:			// CHECK2: cond.end:
	// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 999, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]			// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 999, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
	// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK2-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK2-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK2-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK2: omp.inner.for.cond:			// CHECK2: omp.inner.for.cond:
	// CHECK2-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15
	// CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK2: omp.inner.for.body:			// CHECK2: omp.inner.for.body:
	// CHECK2-NEXT: call void @__kmpc_push_proc_bind(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 3)			// CHECK2-NEXT: call void @__kmpc_push_proc_bind(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 3), !llvm.access.group !15
	// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !15
	// CHECK2-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64			// CHECK2-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
	// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15
	// CHECK2-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK2-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK2-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..3 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]])			// CHECK2-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..3 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !15
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK2: omp.inner.for.inc:			// CHECK2: omp.inner.for.inc:
	// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !15
	// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]			// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
	// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]]
	// CHECK2: omp.inner.for.end:			// CHECK2: omp.inner.for.end:
	// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK2: omp.loop.exit:			// CHECK2: omp.loop.exit:
	// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])			// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
	// CHECK2-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK2-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK2-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0			// CHECK2-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
	// CHECK2-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK2-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK2: .omp.final.then:			// CHECK2: .omp.final.then:
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	// CHECK2-NEXT: br label [[COND_END]]			// CHECK2-NEXT: br label [[COND_END]]
	// CHECK2: cond.end:			// CHECK2: cond.end:
	// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 999, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]			// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 999, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
	// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK2-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK2: omp.inner.for.cond:			// CHECK2: omp.inner.for.cond:
	// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK2-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK2-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !18
	// CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK2: omp.inner.for.body:			// CHECK2: omp.inner.for.body:
	// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !18
	// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK2: omp.body.continue:			// CHECK2: omp.body.continue:
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK2: omp.inner.for.inc:			// CHECK2: omp.inner.for.inc:
	// CHECK2-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]
	// CHECK2: omp.inner.for.end:			// CHECK2: omp.inner.for.end:
	// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK2: omp.loop.exit:			// CHECK2: omp.loop.exit:
	// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])			// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
	// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK2-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK2-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK2-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK2-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK2: .omp.final.then:			// CHECK2: .omp.final.then:
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	// CHECK2-NEXT: br label [[COND_END]]			// CHECK2-NEXT: br label [[COND_END]]
	// CHECK2: cond.end:			// CHECK2: cond.end:
	// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 999, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]			// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 999, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
	// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK2-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK2-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK2-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK2: omp.inner.for.cond:			// CHECK2: omp.inner.for.cond:
	// CHECK2-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !21
	// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !21
	// CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK2: omp.inner.for.body:			// CHECK2: omp.inner.for.body:
	// CHECK2-NEXT: call void @__kmpc_push_proc_bind(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 2)			// CHECK2-NEXT: call void @__kmpc_push_proc_bind(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 2), !llvm.access.group !21
	// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !21
	// CHECK2-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64			// CHECK2-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
	// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !21
	// CHECK2-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK2-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK2-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..5 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]])			// CHECK2-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..5 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !21
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK2: omp.inner.for.inc:			// CHECK2: omp.inner.for.inc:
	// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !21
	// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !21
	// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]			// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
	// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]]
	// CHECK2: omp.inner.for.end:			// CHECK2: omp.inner.for.end:
	// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK2: omp.loop.exit:			// CHECK2: omp.loop.exit:
	// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])			// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
	// CHECK2-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK2-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK2-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0			// CHECK2-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
	// CHECK2-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK2-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK2: .omp.final.then:			// CHECK2: .omp.final.then:
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	// CHECK2-NEXT: br label [[COND_END]]			// CHECK2-NEXT: br label [[COND_END]]
	// CHECK2: cond.end:			// CHECK2: cond.end:
	// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 999, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]			// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 999, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
	// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK2-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK2: omp.inner.for.cond:			// CHECK2: omp.inner.for.cond:
	// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !24
	// CHECK2-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK2-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !24
	// CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK2: omp.inner.for.body:			// CHECK2: omp.inner.for.body:
	// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !24
	// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !24
	// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK2: omp.body.continue:			// CHECK2: omp.body.continue:
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK2: omp.inner.for.inc:			// CHECK2: omp.inner.for.inc:
	// CHECK2-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !24
	// CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]]
	// CHECK2: omp.inner.for.end:			// CHECK2: omp.inner.for.end:
	// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK2: omp.loop.exit:			// CHECK2: omp.loop.exit:
	// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])			// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
	// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK2-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK2-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK2-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK2-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK2: .omp.final.then:			// CHECK2: .omp.final.then:
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clang/test/OpenMP/target_teams_distribute_parallel_for_simd_reduction_codegen.cpp

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	// CHECK1-NEXT: br label [[COND_END]]			// CHECK1-NEXT: br label [[COND_END]]
	// CHECK1: cond.end:			// CHECK1: cond.end:
	// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]			// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
	// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK1-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK1-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK1-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK1: omp.inner.for.cond:			// CHECK1: omp.inner.for.cond:
	// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5
	// CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK1: omp.inner.for.body:			// CHECK1: omp.inner.for.body:
	// CHECK1-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK1-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !5
	// CHECK1-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64			// CHECK1-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
	// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5
	// CHECK1-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64			// CHECK1-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
	// CHECK1-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i32) @.omp_outlined..1 to void (i32, i32, ...)), i64 [[TMP9]], i64 [[TMP11]], i32 [[SIVAR1]])			// CHECK1-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i32) @.omp_outlined..1 to void (i32, i32, ...)), i64 [[TMP9]], i64 [[TMP11]], i32 [[SIVAR1]]), !llvm.access.group !5
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK1: omp.inner.for.inc:			// CHECK1: omp.inner.for.inc:
	// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK1-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK1-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !5
	// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]			// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]
	// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]
	// CHECK1: omp.inner.for.end:			// CHECK1: omp.inner.for.end:
	// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK1: omp.loop.exit:			// CHECK1: omp.loop.exit:
	// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])			// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
	// CHECK1-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK1-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK1-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0			// CHECK1-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0
	// CHECK1-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK1-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK1: .omp.final.then:			// CHECK1: .omp.final.then:
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	// CHECK1-NEXT: br label [[COND_END]]			// CHECK1-NEXT: br label [[COND_END]]
	// CHECK1: cond.end:			// CHECK1: cond.end:
	// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ]			// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ]
	// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK1-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK1: omp.inner.for.cond:			// CHECK1: omp.inner.for.cond:
	// CHECK1-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !9
	// CHECK1-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]			// CHECK1-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
	// CHECK1-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK1-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK1: omp.inner.for.body:			// CHECK1: omp.inner.for.body:
	// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1			// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
	// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9
	// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4			// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !9
	// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32 [[SIVAR2]], align 4			// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32 [[SIVAR2]], align 4, !llvm.access.group !9
	// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], [[TMP11]]			// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], [[TMP11]]
	// CHECK1-NEXT: store i32 [[ADD4]], i32* [[SIVAR2]], align 4			// CHECK1-NEXT: store i32 [[ADD4]], i32* [[SIVAR2]], align 4, !llvm.access.group !9
	// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK1: omp.body.continue:			// CHECK1: omp.body.continue:
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK1: omp.inner.for.inc:			// CHECK1: omp.inner.for.inc:
	// CHECK1-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP13]], 1			// CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP13]], 1
	// CHECK1-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]
	// CHECK1: omp.inner.for.end:			// CHECK1: omp.inner.for.end:
	// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK1: omp.loop.exit:			// CHECK1: omp.loop.exit:
	// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]])			// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]])
	// CHECK1-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK1-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK1-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0			// CHECK1-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0
	// CHECK1-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK1-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK1: .omp.final.then:			// CHECK1: .omp.final.then:
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	// CHECK1-NEXT: br label [[COND_END]]			// CHECK1-NEXT: br label [[COND_END]]
	// CHECK1: cond.end:			// CHECK1: cond.end:
	// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]			// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
	// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK1-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK1-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK1-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK1: omp.inner.for.cond:			// CHECK1: omp.inner.for.cond:
	// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !14
	// CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK1: omp.inner.for.body:			// CHECK1: omp.inner.for.body:
	// CHECK1-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK1-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !14
	// CHECK1-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64			// CHECK1-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
	// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !14
	// CHECK1-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64			// CHECK1-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
	// CHECK1-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i32) @.omp_outlined..4 to void (i32, i32, ...)), i64 [[TMP9]], i64 [[TMP11]], i32 [[T_VAR1]])			// CHECK1-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i32) @.omp_outlined..4 to void (i32, i32, ...)), i64 [[TMP9]], i64 [[TMP11]], i32 [[T_VAR1]]), !llvm.access.group !14
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK1: omp.inner.for.inc:			// CHECK1: omp.inner.for.inc:
	// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK1-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK1-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !14
	// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]			// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]
	// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]]
	// CHECK1: omp.inner.for.end:			// CHECK1: omp.inner.for.end:
	// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK1: omp.loop.exit:			// CHECK1: omp.loop.exit:
	// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])			// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
	// CHECK1-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK1-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK1-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0			// CHECK1-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0
	// CHECK1-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK1-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK1: .omp.final.then:			// CHECK1: .omp.final.then:
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	// CHECK1-NEXT: br label [[COND_END]]			// CHECK1-NEXT: br label [[COND_END]]
	// CHECK1: cond.end:			// CHECK1: cond.end:
	// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ]			// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ]
	// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK1-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK1: omp.inner.for.cond:			// CHECK1: omp.inner.for.cond:
	// CHECK1-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !17
	// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !17
	// CHECK1-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]			// CHECK1-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
	// CHECK1-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK1-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK1: omp.inner.for.body:			// CHECK1: omp.inner.for.body:
	// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !17
	// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1			// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
	// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !17
	// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4			// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !17
	// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32 [[T_VAR2]], align 4			// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32 [[T_VAR2]], align 4, !llvm.access.group !17
	// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], [[TMP11]]			// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], [[TMP11]]
	// CHECK1-NEXT: store i32 [[ADD4]], i32* [[T_VAR2]], align 4			// CHECK1-NEXT: store i32 [[ADD4]], i32* [[T_VAR2]], align 4, !llvm.access.group !17
	// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK1: omp.body.continue:			// CHECK1: omp.body.continue:
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK1: omp.inner.for.inc:			// CHECK1: omp.inner.for.inc:
	// CHECK1-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !17
	// CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP13]], 1			// CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP13]], 1
	// CHECK1-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]]
	// CHECK1: omp.inner.for.end:			// CHECK1: omp.inner.for.end:
	// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK1: omp.loop.exit:			// CHECK1: omp.loop.exit:
	// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]])			// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]])
	// CHECK1-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK1-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK1-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0			// CHECK1-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0
	// CHECK1-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK1-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK1: .omp.final.then:			// CHECK1: .omp.final.then:
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	// CHECK2-NEXT: br label [[COND_END]]			// CHECK2-NEXT: br label [[COND_END]]
	// CHECK2: cond.end:			// CHECK2: cond.end:
	// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]			// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
	// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK2-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK2-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK2-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK2: omp.inner.for.cond:			// CHECK2: omp.inner.for.cond:
	// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5
	// CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK2: omp.inner.for.body:			// CHECK2: omp.inner.for.body:
	// CHECK2-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK2-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !5
	// CHECK2-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64			// CHECK2-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
	// CHECK2-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK2-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5
	// CHECK2-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64			// CHECK2-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
	// CHECK2-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i32) @.omp_outlined..1 to void (i32, i32, ...)), i64 [[TMP9]], i64 [[TMP11]], i32 [[SIVAR1]])			// CHECK2-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i32) @.omp_outlined..1 to void (i32, i32, ...)), i64 [[TMP9]], i64 [[TMP11]], i32 [[SIVAR1]]), !llvm.access.group !5
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK2: omp.inner.for.inc:			// CHECK2: omp.inner.for.inc:
	// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK2-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK2-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !5
	// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]			// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]
	// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]
	// CHECK2: omp.inner.for.end:			// CHECK2: omp.inner.for.end:
	// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK2: omp.loop.exit:			// CHECK2: omp.loop.exit:
	// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])			// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
	// CHECK2-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK2-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK2-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0			// CHECK2-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0
	// CHECK2-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK2-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK2: .omp.final.then:			// CHECK2: .omp.final.then:
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	// CHECK2-NEXT: br label [[COND_END]]			// CHECK2-NEXT: br label [[COND_END]]
	// CHECK2: cond.end:			// CHECK2: cond.end:
	// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ]			// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ]
	// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK2-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK2: omp.inner.for.cond:			// CHECK2: omp.inner.for.cond:
	// CHECK2-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !9
	// CHECK2-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]			// CHECK2-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
	// CHECK2-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK2-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK2: omp.inner.for.body:			// CHECK2: omp.inner.for.body:
	// CHECK2-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1			// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
	// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9
	// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4			// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !9
	// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32 [[SIVAR2]], align 4			// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32 [[SIVAR2]], align 4, !llvm.access.group !9
	// CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], [[TMP11]]			// CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], [[TMP11]]
	// CHECK2-NEXT: store i32 [[ADD4]], i32* [[SIVAR2]], align 4			// CHECK2-NEXT: store i32 [[ADD4]], i32* [[SIVAR2]], align 4, !llvm.access.group !9
	// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK2: omp.body.continue:			// CHECK2: omp.body.continue:
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK2: omp.inner.for.inc:			// CHECK2: omp.inner.for.inc:
	// CHECK2-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK2-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP13]], 1			// CHECK2-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP13]], 1
	// CHECK2-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]
	// CHECK2: omp.inner.for.end:			// CHECK2: omp.inner.for.end:
	// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK2: omp.loop.exit:			// CHECK2: omp.loop.exit:
	// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]])			// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]])
	// CHECK2-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK2-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK2-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0			// CHECK2-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0
	// CHECK2-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK2-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK2: .omp.final.then:			// CHECK2: .omp.final.then:
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	// CHECK2-NEXT: br label [[COND_END]]			// CHECK2-NEXT: br label [[COND_END]]
	// CHECK2: cond.end:			// CHECK2: cond.end:
	// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]			// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
	// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK2-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK2-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK2-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK2: omp.inner.for.cond:			// CHECK2: omp.inner.for.cond:
	// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !14
	// CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK2: omp.inner.for.body:			// CHECK2: omp.inner.for.body:
	// CHECK2-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK2-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !14
	// CHECK2-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64			// CHECK2-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
	// CHECK2-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK2-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !14
	// CHECK2-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64			// CHECK2-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
	// CHECK2-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i32) @.omp_outlined..4 to void (i32, i32, ...)), i64 [[TMP9]], i64 [[TMP11]], i32 [[T_VAR1]])			// CHECK2-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i32) @.omp_outlined..4 to void (i32, i32, ...)), i64 [[TMP9]], i64 [[TMP11]], i32 [[T_VAR1]]), !llvm.access.group !14
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK2: omp.inner.for.inc:			// CHECK2: omp.inner.for.inc:
	// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK2-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK2-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !14
	// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]			// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]
	// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]]
	// CHECK2: omp.inner.for.end:			// CHECK2: omp.inner.for.end:
	// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK2: omp.loop.exit:			// CHECK2: omp.loop.exit:
	// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])			// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
	// CHECK2-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK2-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK2-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0			// CHECK2-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0
	// CHECK2-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK2-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK2: .omp.final.then:			// CHECK2: .omp.final.then:
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	// CHECK2-NEXT: br label [[COND_END]]			// CHECK2-NEXT: br label [[COND_END]]
	// CHECK2: cond.end:			// CHECK2: cond.end:
	// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ]			// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ]
	// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK2-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK2: omp.inner.for.cond:			// CHECK2: omp.inner.for.cond:
	// CHECK2-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !17
	// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !17
	// CHECK2-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]			// CHECK2-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
	// CHECK2-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK2-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK2: omp.inner.for.body:			// CHECK2: omp.inner.for.body:
	// CHECK2-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !17
	// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1			// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
	// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !17
	// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4			// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !17
	// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32 [[T_VAR2]], align 4			// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32 [[T_VAR2]], align 4, !llvm.access.group !17
	// CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], [[TMP11]]			// CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], [[TMP11]]
	// CHECK2-NEXT: store i32 [[ADD4]], i32* [[T_VAR2]], align 4			// CHECK2-NEXT: store i32 [[ADD4]], i32* [[T_VAR2]], align 4, !llvm.access.group !17
	// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK2: omp.body.continue:			// CHECK2: omp.body.continue:
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK2: omp.inner.for.inc:			// CHECK2: omp.inner.for.inc:
	// CHECK2-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !17
	// CHECK2-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP13]], 1			// CHECK2-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP13]], 1
	// CHECK2-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]]
	// CHECK2: omp.inner.for.end:			// CHECK2: omp.inner.for.end:
	// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK2: omp.loop.exit:			// CHECK2: omp.loop.exit:
	// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]])			// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]])
	// CHECK2-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK2-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK2-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0			// CHECK2-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0
	// CHECK2-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK2-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK2: .omp.final.then:			// CHECK2: .omp.final.then:
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	// CHECK3-NEXT: br label [[COND_END]]			// CHECK3-NEXT: br label [[COND_END]]
	// CHECK3: cond.end:			// CHECK3: cond.end:
	// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]			// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
	// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK3-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK3-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK3-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK3-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK3: omp.inner.for.cond:			// CHECK3: omp.inner.for.cond:
	// CHECK3-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK3-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !6
	// CHECK3-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK3-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !6
	// CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK3: omp.inner.for.body:			// CHECK3: omp.inner.for.body:
	// CHECK3-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK3-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !6
	// CHECK3-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK3-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !6
	// CHECK3-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i32, i32, i32) @.omp_outlined..1 to void (i32, i32, ...)), i32 [[TMP8]], i32 [[TMP9]], i32 [[SIVAR1]])			// CHECK3-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i32, i32, i32) @.omp_outlined..1 to void (i32, i32, ...)), i32 [[TMP8]], i32 [[TMP9]], i32 [[SIVAR1]]), !llvm.access.group !6
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK3: omp.inner.for.inc:			// CHECK3: omp.inner.for.inc:
	// CHECK3-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK3-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !6
	// CHECK3-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK3-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !6
	// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP10]], [[TMP11]]			// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP10]], [[TMP11]]
	// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]
	// CHECK3: omp.inner.for.end:			// CHECK3: omp.inner.for.end:
	// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK3: omp.loop.exit:			// CHECK3: omp.loop.exit:
	// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])			// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
	// CHECK3-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK3-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK3-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0			// CHECK3-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0
	// CHECK3-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK3-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK3: .omp.final.then:			// CHECK3: .omp.final.then:
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	// CHECK3-NEXT: br label [[COND_END]]			// CHECK3-NEXT: br label [[COND_END]]
	// CHECK3: cond.end:			// CHECK3: cond.end:
	// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ]			// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ]
	// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK3-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK3-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK3-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4			// CHECK3-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK3: omp.inner.for.cond:			// CHECK3: omp.inner.for.cond:
	// CHECK3-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK3-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK3-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK3-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !10
	// CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]			// CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
	// CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK3: omp.inner.for.body:			// CHECK3: omp.inner.for.body:
	// CHECK3-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK3-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1			// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
	// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10
	// CHECK3-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4			// CHECK3-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !10
	// CHECK3-NEXT: [[TMP12:%.]] = load i32, i32 [[SIVAR1]], align 4			// CHECK3-NEXT: [[TMP12:%.]] = load i32, i32 [[SIVAR1]], align 4, !llvm.access.group !10
	// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], [[TMP11]]			// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], [[TMP11]]
	// CHECK3-NEXT: store i32 [[ADD3]], i32* [[SIVAR1]], align 4			// CHECK3-NEXT: store i32 [[ADD3]], i32* [[SIVAR1]], align 4, !llvm.access.group !10
	// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK3: omp.body.continue:			// CHECK3: omp.body.continue:
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK3: omp.inner.for.inc:			// CHECK3: omp.inner.for.inc:
	// CHECK3-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK3-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], 1			// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], 1
	// CHECK3-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4			// CHECK3-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]
	// CHECK3: omp.inner.for.end:			// CHECK3: omp.inner.for.end:
	// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK3: omp.loop.exit:			// CHECK3: omp.loop.exit:
	// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]])			// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]])
	// CHECK3-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK3-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK3-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0			// CHECK3-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0
	// CHECK3-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK3-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK3: .omp.final.then:			// CHECK3: .omp.final.then:
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	// CHECK3-NEXT: br label [[COND_END]]			// CHECK3-NEXT: br label [[COND_END]]
	// CHECK3: cond.end:			// CHECK3: cond.end:
	// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]			// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
	// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK3-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK3-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK3-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK3-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK3: omp.inner.for.cond:			// CHECK3: omp.inner.for.cond:
	// CHECK3-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK3-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK3-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK3-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15
	// CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK3: omp.inner.for.body:			// CHECK3: omp.inner.for.body:
	// CHECK3-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK3-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !15
	// CHECK3-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK3-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15
	// CHECK3-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i32, i32, i32) @.omp_outlined..4 to void (i32, i32, ...)), i32 [[TMP8]], i32 [[TMP9]], i32 [[T_VAR1]])			// CHECK3-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i32, i32, i32) @.omp_outlined..4 to void (i32, i32, ...)), i32 [[TMP8]], i32 [[TMP9]], i32 [[T_VAR1]]), !llvm.access.group !15
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK3: omp.inner.for.inc:			// CHECK3: omp.inner.for.inc:
	// CHECK3-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK3-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK3-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK3-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !15
	// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP10]], [[TMP11]]			// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP10]], [[TMP11]]
	// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]]
	// CHECK3: omp.inner.for.end:			// CHECK3: omp.inner.for.end:
	// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK3: omp.loop.exit:			// CHECK3: omp.loop.exit:
	// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])			// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
	// CHECK3-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK3-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK3-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0			// CHECK3-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0
	// CHECK3-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK3-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK3: .omp.final.then:			// CHECK3: .omp.final.then:
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	// CHECK3-NEXT: br label [[COND_END]]			// CHECK3-NEXT: br label [[COND_END]]
	// CHECK3: cond.end:			// CHECK3: cond.end:
	// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ]			// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ]
	// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK3-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK3-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK3-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4			// CHECK3-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK3: omp.inner.for.cond:			// CHECK3: omp.inner.for.cond:
	// CHECK3-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK3-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK3-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK3-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !18
	// CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]			// CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
	// CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK3: omp.inner.for.body:			// CHECK3: omp.inner.for.body:
	// CHECK3-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK3-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1			// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
	// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !18
	// CHECK3-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4			// CHECK3-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !18
	// CHECK3-NEXT: [[TMP12:%.]] = load i32, i32 [[T_VAR1]], align 4			// CHECK3-NEXT: [[TMP12:%.]] = load i32, i32 [[T_VAR1]], align 4, !llvm.access.group !18
	// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], [[TMP11]]			// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], [[TMP11]]
	// CHECK3-NEXT: store i32 [[ADD3]], i32* [[T_VAR1]], align 4			// CHECK3-NEXT: store i32 [[ADD3]], i32* [[T_VAR1]], align 4, !llvm.access.group !18
	// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK3: omp.body.continue:			// CHECK3: omp.body.continue:
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK3: omp.inner.for.inc:			// CHECK3: omp.inner.for.inc:
	// CHECK3-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK3-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], 1			// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], 1
	// CHECK3-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4			// CHECK3-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]
	// CHECK3: omp.inner.for.end:			// CHECK3: omp.inner.for.end:
	// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK3: omp.loop.exit:			// CHECK3: omp.loop.exit:
	// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]])			// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]])
	// CHECK3-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK3-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK3-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0			// CHECK3-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0
	// CHECK3-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK3-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK3: .omp.final.then:			// CHECK3: .omp.final.then:
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	// CHECK4-NEXT: br label [[COND_END]]			// CHECK4-NEXT: br label [[COND_END]]
	// CHECK4: cond.end:			// CHECK4: cond.end:
	// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]			// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
	// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK4-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK4-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK4-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK4-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK4: omp.inner.for.cond:			// CHECK4: omp.inner.for.cond:
	// CHECK4-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK4-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !6
	// CHECK4-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK4-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !6
	// CHECK4-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK4-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK4-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK4-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK4: omp.inner.for.body:			// CHECK4: omp.inner.for.body:
	// CHECK4-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK4-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !6
	// CHECK4-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK4-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !6
	// CHECK4-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i32, i32, i32) @.omp_outlined..1 to void (i32, i32, ...)), i32 [[TMP8]], i32 [[TMP9]], i32 [[SIVAR1]])			// CHECK4-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i32, i32, i32) @.omp_outlined..1 to void (i32, i32, ...)), i32 [[TMP8]], i32 [[TMP9]], i32 [[SIVAR1]]), !llvm.access.group !6
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK4: omp.inner.for.inc:			// CHECK4: omp.inner.for.inc:
	// CHECK4-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK4-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !6
	// CHECK4-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK4-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !6
	// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP10]], [[TMP11]]			// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP10]], [[TMP11]]
	// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]
	// CHECK4: omp.inner.for.end:			// CHECK4: omp.inner.for.end:
	// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK4: omp.loop.exit:			// CHECK4: omp.loop.exit:
	// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])			// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
	// CHECK4-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK4-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK4-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0			// CHECK4-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0
	// CHECK4-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK4-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK4: .omp.final.then:			// CHECK4: .omp.final.then:
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	// CHECK4-NEXT: br label [[COND_END]]			// CHECK4-NEXT: br label [[COND_END]]
	// CHECK4: cond.end:			// CHECK4: cond.end:
	// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ]			// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ]
	// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK4-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK4-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK4-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4			// CHECK4-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK4: omp.inner.for.cond:			// CHECK4: omp.inner.for.cond:
	// CHECK4-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK4-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK4-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK4-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !10
	// CHECK4-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]			// CHECK4-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
	// CHECK4-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK4-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK4: omp.inner.for.body:			// CHECK4: omp.inner.for.body:
	// CHECK4-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK4-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1			// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
	// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10
	// CHECK4-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4			// CHECK4-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !10
	// CHECK4-NEXT: [[TMP12:%.]] = load i32, i32 [[SIVAR1]], align 4			// CHECK4-NEXT: [[TMP12:%.]] = load i32, i32 [[SIVAR1]], align 4, !llvm.access.group !10
	// CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], [[TMP11]]			// CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], [[TMP11]]
	// CHECK4-NEXT: store i32 [[ADD3]], i32* [[SIVAR1]], align 4			// CHECK4-NEXT: store i32 [[ADD3]], i32* [[SIVAR1]], align 4, !llvm.access.group !10
	// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK4: omp.body.continue:			// CHECK4: omp.body.continue:
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK4: omp.inner.for.inc:			// CHECK4: omp.inner.for.inc:
	// CHECK4-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK4-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], 1			// CHECK4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], 1
	// CHECK4-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4			// CHECK4-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]
	// CHECK4: omp.inner.for.end:			// CHECK4: omp.inner.for.end:
	// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK4: omp.loop.exit:			// CHECK4: omp.loop.exit:
	// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]])			// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]])
	// CHECK4-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK4-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK4-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0			// CHECK4-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0
	// CHECK4-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK4-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK4: .omp.final.then:			// CHECK4: .omp.final.then:
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	// CHECK4-NEXT: br label [[COND_END]]			// CHECK4-NEXT: br label [[COND_END]]
	// CHECK4: cond.end:			// CHECK4: cond.end:
	// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]			// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
	// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK4-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK4-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK4-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK4-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK4: omp.inner.for.cond:			// CHECK4: omp.inner.for.cond:
	// CHECK4-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK4-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK4-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK4-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15
	// CHECK4-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK4-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK4-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK4-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK4: omp.inner.for.body:			// CHECK4: omp.inner.for.body:
	// CHECK4-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK4-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !15
	// CHECK4-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK4-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15
	// CHECK4-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i32, i32, i32) @.omp_outlined..4 to void (i32, i32, ...)), i32 [[TMP8]], i32 [[TMP9]], i32 [[T_VAR1]])			// CHECK4-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i32, i32, i32) @.omp_outlined..4 to void (i32, i32, ...)), i32 [[TMP8]], i32 [[TMP9]], i32 [[T_VAR1]]), !llvm.access.group !15
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK4: omp.inner.for.inc:			// CHECK4: omp.inner.for.inc:
	// CHECK4-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK4-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK4-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK4-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !15
	// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP10]], [[TMP11]]			// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP10]], [[TMP11]]
	// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]]
	// CHECK4: omp.inner.for.end:			// CHECK4: omp.inner.for.end:
	// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK4: omp.loop.exit:			// CHECK4: omp.loop.exit:
	// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])			// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
	// CHECK4-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK4-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK4-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0			// CHECK4-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0
	// CHECK4-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK4-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK4: .omp.final.then:			// CHECK4: .omp.final.then:
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	// CHECK4-NEXT: br label [[COND_END]]			// CHECK4-NEXT: br label [[COND_END]]
	// CHECK4: cond.end:			// CHECK4: cond.end:
	// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ]			// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ]
	// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK4-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK4-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK4-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4			// CHECK4-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK4: omp.inner.for.cond:			// CHECK4: omp.inner.for.cond:
	// CHECK4-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK4-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK4-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK4-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !18
	// CHECK4-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]			// CHECK4-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
	// CHECK4-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK4-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK4: omp.inner.for.body:			// CHECK4: omp.inner.for.body:
	// CHECK4-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK4-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1			// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
	// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !18
	// CHECK4-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4			// CHECK4-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !18
	// CHECK4-NEXT: [[TMP12:%.]] = load i32, i32 [[T_VAR1]], align 4			// CHECK4-NEXT: [[TMP12:%.]] = load i32, i32 [[T_VAR1]], align 4, !llvm.access.group !18
	// CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], [[TMP11]]			// CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], [[TMP11]]
	// CHECK4-NEXT: store i32 [[ADD3]], i32* [[T_VAR1]], align 4			// CHECK4-NEXT: store i32 [[ADD3]], i32* [[T_VAR1]], align 4, !llvm.access.group !18
	// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK4: omp.body.continue:			// CHECK4: omp.body.continue:
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK4: omp.inner.for.inc:			// CHECK4: omp.inner.for.inc:
	// CHECK4-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK4-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], 1			// CHECK4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], 1
	// CHECK4-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4			// CHECK4-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]
	// CHECK4: omp.inner.for.end:			// CHECK4: omp.inner.for.end:
	// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK4: omp.loop.exit:			// CHECK4: omp.loop.exit:
	// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]])			// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]])
	// CHECK4-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK4-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK4-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0			// CHECK4-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0
	// CHECK4-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK4-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK4: .omp.final.then:			// CHECK4: .omp.final.then:
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	// CHECK5-NEXT: br label [[COND_END]]			// CHECK5-NEXT: br label [[COND_END]]
	// CHECK5: cond.end:			// CHECK5: cond.end:
	// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]			// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
	// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK5-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK5-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK5-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK5-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK5: omp.inner.for.cond:			// CHECK5: omp.inner.for.cond:
	// CHECK5-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK5-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !4
	// CHECK5-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK5-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !4
	// CHECK5-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK5-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK5: omp.inner.for.body:			// CHECK5: omp.inner.for.body:
	// CHECK5-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK5-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !4
	// CHECK5-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64			// CHECK5-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
	// CHECK5-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK5-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !4
	// CHECK5-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64			// CHECK5-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
	// CHECK5-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i32) @.omp_outlined..1 to void (i32, i32, ...)), i64 [[TMP9]], i64 [[TMP11]], i32 [[SIVAR1]])			// CHECK5-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i32) @.omp_outlined..1 to void (i32, i32, ...)), i64 [[TMP9]], i64 [[TMP11]], i32 [[SIVAR1]]), !llvm.access.group !4
	// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK5: omp.inner.for.inc:			// CHECK5: omp.inner.for.inc:
	// CHECK5-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK5-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !4
	// CHECK5-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK5-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !4
	// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]			// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]
	// CHECK5-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK5-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4
	// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]			// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]
	// CHECK5: omp.inner.for.end:			// CHECK5: omp.inner.for.end:
	// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK5: omp.loop.exit:			// CHECK5: omp.loop.exit:
	// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])			// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
	// CHECK5-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK5-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK5-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0			// CHECK5-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0
	// CHECK5-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK5-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK5: .omp.final.then:			// CHECK5: .omp.final.then:
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	// CHECK5-NEXT: br label [[COND_END]]			// CHECK5-NEXT: br label [[COND_END]]
	// CHECK5: cond.end:			// CHECK5: cond.end:
	// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ]			// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ]
	// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK5-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK5-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK5-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4			// CHECK5-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4
	// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK5: omp.inner.for.cond:			// CHECK5: omp.inner.for.cond:
	// CHECK5-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK5-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !8
	// CHECK5-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK5-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !8
	// CHECK5-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]			// CHECK5-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
	// CHECK5-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK5-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK5: omp.inner.for.body:			// CHECK5: omp.inner.for.body:
	// CHECK5-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK5-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !8
	// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1			// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
	// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !8
	// CHECK5-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4			// CHECK5-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !8
	// CHECK5-NEXT: [[TMP12:%.]] = load i32, i32 [[SIVAR2]], align 4			// CHECK5-NEXT: [[TMP12:%.]] = load i32, i32 [[SIVAR2]], align 4, !llvm.access.group !8
	// CHECK5-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], [[TMP11]]			// CHECK5-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], [[TMP11]]
	// CHECK5-NEXT: store i32 [[ADD4]], i32* [[SIVAR2]], align 4			// CHECK5-NEXT: store i32 [[ADD4]], i32* [[SIVAR2]], align 4, !llvm.access.group !8
	// CHECK5-NEXT: [[TMP13:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 0			// CHECK5-NEXT: [[TMP13:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 0
	// CHECK5-NEXT: store i32* [[SIVAR2]], i32** [[TMP13]], align 8			// CHECK5-NEXT: store i32* [[SIVAR2]], i32** [[TMP13]], align 8, !llvm.access.group !8
	// CHECK5-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(8) [[REF_TMP]])			// CHECK5-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(8) [[REF_TMP]]), !llvm.access.group !8
	// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK5: omp.body.continue:			// CHECK5: omp.body.continue:
	// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK5: omp.inner.for.inc:			// CHECK5: omp.inner.for.inc:
	// CHECK5-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK5-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !8
	// CHECK5-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP14]], 1			// CHECK5-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP14]], 1
	// CHECK5-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4			// CHECK5-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8
	// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]			// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]
	// CHECK5: omp.inner.for.end:			// CHECK5: omp.inner.for.end:
	// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK5: omp.loop.exit:			// CHECK5: omp.loop.exit:
	// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]])			// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]])
	// CHECK5-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK5-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK5-NEXT: [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0			// CHECK5-NEXT: [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0
	// CHECK5-NEXT: br i1 [[TMP16]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK5-NEXT: br i1 [[TMP16]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK5: .omp.final.then:			// CHECK5: .omp.final.then:
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	// CHECK6-NEXT: br label [[COND_END]]			// CHECK6-NEXT: br label [[COND_END]]
	// CHECK6: cond.end:			// CHECK6: cond.end:
	// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]			// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
	// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK6-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK6-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK6-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK6-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK6: omp.inner.for.cond:			// CHECK6: omp.inner.for.cond:
	// CHECK6-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK6-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !4
	// CHECK6-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK6-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !4
	// CHECK6-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK6-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK6-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK6-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK6: omp.inner.for.body:			// CHECK6: omp.inner.for.body:
	// CHECK6-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK6-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !4
	// CHECK6-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64			// CHECK6-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
	// CHECK6-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK6-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !4
	// CHECK6-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64			// CHECK6-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
	// CHECK6-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i32) @.omp_outlined..1 to void (i32, i32, ...)), i64 [[TMP9]], i64 [[TMP11]], i32 [[SIVAR1]])			// CHECK6-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i32) @.omp_outlined..1 to void (i32, i32, ...)), i64 [[TMP9]], i64 [[TMP11]], i32 [[SIVAR1]]), !llvm.access.group !4
	// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK6: omp.inner.for.inc:			// CHECK6: omp.inner.for.inc:
	// CHECK6-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK6-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !4
	// CHECK6-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK6-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !4
	// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]			// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]
	// CHECK6-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK6-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4
	// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]			// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]
	// CHECK6: omp.inner.for.end:			// CHECK6: omp.inner.for.end:
	// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK6: omp.loop.exit:			// CHECK6: omp.loop.exit:
	// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])			// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
	// CHECK6-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK6-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK6-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0			// CHECK6-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0
	// CHECK6-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK6-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK6: .omp.final.then:			// CHECK6: .omp.final.then:
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	// CHECK6-NEXT: br label [[COND_END]]			// CHECK6-NEXT: br label [[COND_END]]
	// CHECK6: cond.end:			// CHECK6: cond.end:
	// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ]			// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ]
	// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK6-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK6-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK6-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4			// CHECK6-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4
	// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK6: omp.inner.for.cond:			// CHECK6: omp.inner.for.cond:
	// CHECK6-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK6-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !8
	// CHECK6-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK6-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !8
	// CHECK6-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]			// CHECK6-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
	// CHECK6-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK6-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK6: omp.inner.for.body:			// CHECK6: omp.inner.for.body:
	// CHECK6-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK6-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !8
	// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1			// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
	// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !8
	// CHECK6-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4			// CHECK6-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !8
	// CHECK6-NEXT: [[TMP12:%.]] = load i32, i32 [[SIVAR2]], align 4			// CHECK6-NEXT: [[TMP12:%.]] = load i32, i32 [[SIVAR2]], align 4, !llvm.access.group !8
	// CHECK6-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], [[TMP11]]			// CHECK6-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], [[TMP11]]
	// CHECK6-NEXT: store i32 [[ADD4]], i32* [[SIVAR2]], align 4			// CHECK6-NEXT: store i32 [[ADD4]], i32* [[SIVAR2]], align 4, !llvm.access.group !8
	// CHECK6-NEXT: [[TMP13:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 0			// CHECK6-NEXT: [[TMP13:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 0
	// CHECK6-NEXT: store i32* [[SIVAR2]], i32** [[TMP13]], align 8			// CHECK6-NEXT: store i32* [[SIVAR2]], i32** [[TMP13]], align 8, !llvm.access.group !8
	// CHECK6-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(8) [[REF_TMP]])			// CHECK6-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(8) [[REF_TMP]]), !llvm.access.group !8
	// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK6: omp.body.continue:			// CHECK6: omp.body.continue:
	// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK6: omp.inner.for.inc:			// CHECK6: omp.inner.for.inc:
	// CHECK6-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK6-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !8
	// CHECK6-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP14]], 1			// CHECK6-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP14]], 1
	// CHECK6-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4			// CHECK6-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8
	// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]			// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]
	// CHECK6: omp.inner.for.end:			// CHECK6: omp.inner.for.end:
	// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK6: omp.loop.exit:			// CHECK6: omp.loop.exit:
	// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]])			// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]])
	// CHECK6-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK6-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK6-NEXT: [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0			// CHECK6-NEXT: [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0
	// CHECK6-NEXT: br i1 [[TMP16]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK6-NEXT: br i1 [[TMP16]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK6: .omp.final.then:			// CHECK6: .omp.final.then:
	▲ Show 20 Lines • Show All 501 Lines • Show Last 20 Lines

clang/test/OpenMP/target_teams_distribute_reduction_codegen.cpp

	Show First 20 Lines • Show All 1,657 Lines • ▼ Show 20 Lines
	//			//
	//			//
	// CHECK10-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg			// CHECK10-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
	// CHECK10-SAME: () #[[ATTR6:[0-9]+]] {			// CHECK10-SAME: () #[[ATTR6:[0-9]+]] {
	// CHECK10-NEXT: entry:			// CHECK10-NEXT: entry:
	// CHECK10-NEXT: call void @__tgt_register_requires(i64 1)			// CHECK10-NEXT: call void @__tgt_register_requires(i64 1)
	// CHECK10-NEXT: ret void			// CHECK10-NEXT: ret void
	//			//
	//
	No newline at end of file

clang/test/OpenMP/taskgroup_codegen.cpp

	Show First 20 Lines • Show All 202 Lines • ▼ Show 20 Lines
	// CHECK2-NEXT: [[EXN:%.]] = load i8, i8** [[EXN_SLOT]], align 8			// CHECK2-NEXT: [[EXN:%.]] = load i8, i8** [[EXN_SLOT]], align 8
	// CHECK2-NEXT: call void @__clang_call_terminate(i8* [[EXN]]) #[[ATTR8]]			// CHECK2-NEXT: call void @__clang_call_terminate(i8* [[EXN]]) #[[ATTR8]]
	// CHECK2-NEXT: unreachable			// CHECK2-NEXT: unreachable
	//			//
	//			//
	// DEBUG1-LABEL: define {{[^@]+}}@_Z3foov			// DEBUG1-LABEL: define {{[^@]+}}@_Z3foov
	// DEBUG1-SAME: () #[[ATTR0:[0-9]+]] !dbg [[DBG6:![0-9]+]] {			// DEBUG1-SAME: () #[[ATTR0:[0-9]+]] !dbg [[DBG6:![0-9]+]] {
	// DEBUG1-NEXT: entry:			// DEBUG1-NEXT: entry:
	// DEBUG1-NEXT: call void @_Z8mayThrowv(), !dbg [[DBG9:![0-9]+]]			// DEBUG1-NEXT: call void @_Z8mayThrowv(), !dbg [[DBG10:![0-9]+]]
	// DEBUG1-NEXT: ret void, !dbg [[DBG10:![0-9]+]]			// DEBUG1-NEXT: ret void, !dbg [[DBG11:![0-9]+]]
	//			//
	//			//
	// DEBUG1-LABEL: define {{[^@]+}}@main			// DEBUG1-LABEL: define {{[^@]+}}@main
	// DEBUG1-SAME: () #[[ATTR2:[0-9]+]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) !dbg [[DBG11:![0-9]+]] {			// DEBUG1-SAME: () #[[ATTR2:[0-9]+]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) !dbg [[DBG12:![0-9]+]] {
	// DEBUG1-NEXT: entry:			// DEBUG1-NEXT: entry:
	// DEBUG1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4			// DEBUG1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
	// DEBUG1-NEXT: [[A:%.*]] = alloca i8, align 1			// DEBUG1-NEXT: [[A:%.*]] = alloca i8, align 1
	// DEBUG1-NEXT: [[EXN_SLOT:%.]] = alloca i8, align 8			// DEBUG1-NEXT: [[EXN_SLOT:%.]] = alloca i8, align 8
	// DEBUG1-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4			// DEBUG1-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4
	// DEBUG1-NEXT: [[TMP0:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB1:[0-9]+]])			// DEBUG1-NEXT: [[TMP0:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB1:[0-9]+]])
	// DEBUG1-NEXT: store i32 0, i32* [[RETVAL]], align 4			// DEBUG1-NEXT: store i32 0, i32* [[RETVAL]], align 4
	// DEBUG1-NEXT: call void @__kmpc_taskgroup(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]), !dbg [[DBG12:![0-9]+]]			// DEBUG1-NEXT: call void @__kmpc_taskgroup(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]), !dbg [[DBG13:![0-9]+]]
	// DEBUG1-NEXT: store i8 2, i8* [[A]], align 1, !dbg [[DBG13:![0-9]+]]			// DEBUG1-NEXT: store i8 2, i8* [[A]], align 1, !dbg [[DBG14:![0-9]+]]
	// DEBUG1-NEXT: call void @__kmpc_end_taskgroup(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]), !dbg [[DBG14:![0-9]+]]			// DEBUG1-NEXT: call void @__kmpc_end_taskgroup(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]), !dbg [[DBG15:![0-9]+]]
	// DEBUG1-NEXT: call void @__kmpc_taskgroup(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP0]]), !dbg [[DBG15:![0-9]+]]			// DEBUG1-NEXT: call void @__kmpc_taskgroup(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP0]]), !dbg [[DBG16:![0-9]+]]
	// DEBUG1-NEXT: invoke void @_Z3foov()			// DEBUG1-NEXT: invoke void @_Z3foov()
	// DEBUG1-NEXT: to label [[INVOKE_CONT:%.]] unwind label [[LPAD:%.]], !dbg [[DBG16:![0-9]+]]			// DEBUG1-NEXT: to label [[INVOKE_CONT:%.]] unwind label [[LPAD:%.]], !dbg [[DBG17:![0-9]+]]
	// DEBUG1: invoke.cont:			// DEBUG1: invoke.cont:
	// DEBUG1-NEXT: call void @__kmpc_end_taskgroup(%struct.ident_t* @[[GLOB3]], i32 [[TMP0]]), !dbg [[DBG16]]			// DEBUG1-NEXT: call void @__kmpc_end_taskgroup(%struct.ident_t* @[[GLOB3]], i32 [[TMP0]]), !dbg [[DBG17]]
	// DEBUG1-NEXT: [[TMP1:%.]] = load i8, i8 [[A]], align 1, !dbg [[DBG17:![0-9]+]]			// DEBUG1-NEXT: [[TMP1:%.]] = load i8, i8 [[A]], align 1, !dbg [[DBG18:![0-9]+]]
	// DEBUG1-NEXT: [[CONV:%.*]] = sext i8 [[TMP1]] to i32, !dbg [[DBG17]]			// DEBUG1-NEXT: [[CONV:%.*]] = sext i8 [[TMP1]] to i32, !dbg [[DBG18]]
	// DEBUG1-NEXT: ret i32 [[CONV]], !dbg [[DBG18:![0-9]+]]			// DEBUG1-NEXT: ret i32 [[CONV]], !dbg [[DBG19:![0-9]+]]
	// DEBUG1: lpad:			// DEBUG1: lpad:
	// DEBUG1-NEXT: [[TMP2:%.]] = landingpad { i8, i32 }			// DEBUG1-NEXT: [[TMP2:%.]] = landingpad { i8, i32 }
	// DEBUG1-NEXT: catch i8* null, !dbg [[DBG19:![0-9]+]]			// DEBUG1-NEXT: catch i8* null, !dbg [[DBG20:![0-9]+]]
	// DEBUG1-NEXT: [[TMP3:%.]] = extractvalue { i8, i32 } [[TMP2]], 0, !dbg [[DBG19]]			// DEBUG1-NEXT: [[TMP3:%.]] = extractvalue { i8, i32 } [[TMP2]], 0, !dbg [[DBG20]]
	// DEBUG1-NEXT: store i8* [[TMP3]], i8** [[EXN_SLOT]], align 8, !dbg [[DBG19]]			// DEBUG1-NEXT: store i8* [[TMP3]], i8** [[EXN_SLOT]], align 8, !dbg [[DBG20]]
	// DEBUG1-NEXT: [[TMP4:%.]] = extractvalue { i8, i32 } [[TMP2]], 1, !dbg [[DBG19]]			// DEBUG1-NEXT: [[TMP4:%.]] = extractvalue { i8, i32 } [[TMP2]], 1, !dbg [[DBG20]]
	// DEBUG1-NEXT: store i32 [[TMP4]], i32* [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG19]]			// DEBUG1-NEXT: store i32 [[TMP4]], i32* [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG20]]
	// DEBUG1-NEXT: call void @__kmpc_end_taskgroup(%struct.ident_t* @[[GLOB3]], i32 [[TMP0]]), !dbg [[DBG16]]			// DEBUG1-NEXT: call void @__kmpc_end_taskgroup(%struct.ident_t* @[[GLOB3]], i32 [[TMP0]]), !dbg [[DBG17]]
	// DEBUG1-NEXT: br label [[TERMINATE_HANDLER:%.*]], !dbg [[DBG16]]			// DEBUG1-NEXT: br label [[TERMINATE_HANDLER:%.*]], !dbg [[DBG17]]
	// DEBUG1: terminate.handler:			// DEBUG1: terminate.handler:
	// DEBUG1-NEXT: [[EXN:%.]] = load i8, i8** [[EXN_SLOT]], align 8, !dbg [[DBG16]]			// DEBUG1-NEXT: [[EXN:%.]] = load i8, i8** [[EXN_SLOT]], align 8, !dbg [[DBG17]]
	// DEBUG1-NEXT: call void @__clang_call_terminate(i8* [[EXN]]) #[[ATTR8:[0-9]+]], !dbg [[DBG16]]			// DEBUG1-NEXT: call void @__clang_call_terminate(i8* [[EXN]]) #[[ATTR8:[0-9]+]], !dbg [[DBG17]]
	// DEBUG1-NEXT: unreachable, !dbg [[DBG16]]			// DEBUG1-NEXT: unreachable, !dbg [[DBG17]]
	//			//
	//			//
	// DEBUG1-LABEL: define {{[^@]+}}@__clang_call_terminate			// DEBUG1-LABEL: define {{[^@]+}}@__clang_call_terminate
	// DEBUG1-SAME: (i8* [[TMP0:%.*]]) #[[ATTR5:[0-9]+]] {			// DEBUG1-SAME: (i8* [[TMP0:%.*]]) #[[ATTR5:[0-9]+]] {
	// DEBUG1-NEXT: [[TMP2:%.]] = call i8 @__cxa_begin_catch(i8* [[TMP0]]) #[[ATTR3:[0-9]+]]			// DEBUG1-NEXT: [[TMP2:%.]] = call i8 @__cxa_begin_catch(i8* [[TMP0]]) #[[ATTR3:[0-9]+]]
	// DEBUG1-NEXT: call void @_ZSt9terminatev() #[[ATTR8]]			// DEBUG1-NEXT: call void @_ZSt9terminatev() #[[ATTR8]]
	// DEBUG1-NEXT: unreachable			// DEBUG1-NEXT: unreachable
	//			//
	//			//
	// DEBUG1-LABEL: define {{[^@]+}}@_Z18parallel_taskgroupv			// DEBUG1-LABEL: define {{[^@]+}}@_Z18parallel_taskgroupv
	// DEBUG1-SAME: () #[[ATTR6:[0-9]+]] !dbg [[DBG20:![0-9]+]] {			// DEBUG1-SAME: () #[[ATTR6:[0-9]+]] !dbg [[DBG21:![0-9]+]] {
	// DEBUG1-NEXT: entry:			// DEBUG1-NEXT: entry:
	// DEBUG1-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB7:[0-9]+]], i32 0, void (i32, i32, ...)* bitcast (void (i32, i32)* @.omp_outlined. to void (i32, i32, ...)*)), !dbg [[DBG21:![0-9]+]]			// DEBUG1-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB7:[0-9]+]], i32 0, void (i32, i32, ...)* bitcast (void (i32, i32)* @.omp_outlined. to void (i32, i32, ...)*)), !dbg [[DBG22:![0-9]+]]
	// DEBUG1-NEXT: ret void, !dbg [[DBG22:![0-9]+]]			// DEBUG1-NEXT: ret void, !dbg [[DBG23:![0-9]+]]
	//			//
	//			//
	// DEBUG1-LABEL: define {{[^@]+}}@.omp_outlined.			// DEBUG1-LABEL: define {{[^@]+}}@.omp_outlined.
	// DEBUG1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]]) #[[ATTR7:[0-9]+]] personality i8 bitcast (i32 (...)* @__gxx_personality_v0 to i8*) !dbg [[DBG23:![0-9]+]] {			// DEBUG1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]]) #[[ATTR7:[0-9]+]] personality i8 bitcast (i32 (...)* @__gxx_personality_v0 to i8*) !dbg [[DBG24:![0-9]+]] {
	// DEBUG1-NEXT: entry:			// DEBUG1-NEXT: entry:
	// DEBUG1-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8			// DEBUG1-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8
	// DEBUG1-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8			// DEBUG1-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8
	// DEBUG1-NEXT: [[EXN_SLOT:%.]] = alloca i8, align 8			// DEBUG1-NEXT: [[EXN_SLOT:%.]] = alloca i8, align 8
	// DEBUG1-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4			// DEBUG1-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4
	// DEBUG1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8			// DEBUG1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// DEBUG1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8			// DEBUG1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
	// DEBUG1-NEXT: [[TMP0:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG24:![0-9]+]]			// DEBUG1-NEXT: [[TMP0:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG25:![0-9]+]]
	// DEBUG1-NEXT: [[TMP1:%.]] = load i32, i32 [[TMP0]], align 4, !dbg [[DBG24]]			// DEBUG1-NEXT: [[TMP1:%.]] = load i32, i32 [[TMP0]], align 4, !dbg [[DBG25]]
	// DEBUG1-NEXT: call void @__kmpc_taskgroup(%struct.ident_t* @[[GLOB5:[0-9]+]], i32 [[TMP1]]), !dbg [[DBG24]]			// DEBUG1-NEXT: call void @__kmpc_taskgroup(%struct.ident_t* @[[GLOB5:[0-9]+]], i32 [[TMP1]]), !dbg [[DBG25]]
	// DEBUG1-NEXT: invoke void @_Z3foov()			// DEBUG1-NEXT: invoke void @_Z3foov()
	// DEBUG1-NEXT: to label [[INVOKE_CONT:%.]] unwind label [[LPAD:%.]], !dbg [[DBG25:![0-9]+]]			// DEBUG1-NEXT: to label [[INVOKE_CONT:%.]] unwind label [[LPAD:%.]], !dbg [[DBG26:![0-9]+]]
	// DEBUG1: invoke.cont:			// DEBUG1: invoke.cont:
	// DEBUG1-NEXT: call void @__kmpc_end_taskgroup(%struct.ident_t* @[[GLOB5]], i32 [[TMP1]]), !dbg [[DBG25]]			// DEBUG1-NEXT: call void @__kmpc_end_taskgroup(%struct.ident_t* @[[GLOB5]], i32 [[TMP1]]), !dbg [[DBG26]]
	// DEBUG1-NEXT: ret void, !dbg [[DBG26:![0-9]+]]			// DEBUG1-NEXT: ret void, !dbg [[DBG27:![0-9]+]]
	// DEBUG1: lpad:			// DEBUG1: lpad:
	// DEBUG1-NEXT: [[TMP2:%.]] = landingpad { i8, i32 }			// DEBUG1-NEXT: [[TMP2:%.]] = landingpad { i8, i32 }
	// DEBUG1-NEXT: catch i8* null, !dbg [[DBG27:![0-9]+]]			// DEBUG1-NEXT: catch i8* null, !dbg [[DBG28:![0-9]+]]
	// DEBUG1-NEXT: [[TMP3:%.]] = extractvalue { i8, i32 } [[TMP2]], 0, !dbg [[DBG27]]			// DEBUG1-NEXT: [[TMP3:%.]] = extractvalue { i8, i32 } [[TMP2]], 0, !dbg [[DBG28]]
	// DEBUG1-NEXT: store i8* [[TMP3]], i8** [[EXN_SLOT]], align 8, !dbg [[DBG27]]			// DEBUG1-NEXT: store i8* [[TMP3]], i8** [[EXN_SLOT]], align 8, !dbg [[DBG28]]
	// DEBUG1-NEXT: [[TMP4:%.]] = extractvalue { i8, i32 } [[TMP2]], 1, !dbg [[DBG27]]			// DEBUG1-NEXT: [[TMP4:%.]] = extractvalue { i8, i32 } [[TMP2]], 1, !dbg [[DBG28]]
	// DEBUG1-NEXT: store i32 [[TMP4]], i32* [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG27]]			// DEBUG1-NEXT: store i32 [[TMP4]], i32* [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG28]]
	// DEBUG1-NEXT: call void @__kmpc_end_taskgroup(%struct.ident_t* @[[GLOB5]], i32 [[TMP1]]), !dbg [[DBG25]]			// DEBUG1-NEXT: call void @__kmpc_end_taskgroup(%struct.ident_t* @[[GLOB5]], i32 [[TMP1]]), !dbg [[DBG26]]
	// DEBUG1-NEXT: br label [[TERMINATE_HANDLER:%.*]], !dbg [[DBG25]]			// DEBUG1-NEXT: br label [[TERMINATE_HANDLER:%.*]], !dbg [[DBG26]]
	// DEBUG1: terminate.handler:			// DEBUG1: terminate.handler:
	// DEBUG1-NEXT: [[EXN:%.]] = load i8, i8** [[EXN_SLOT]], align 8, !dbg [[DBG25]]			// DEBUG1-NEXT: [[EXN:%.]] = load i8, i8** [[EXN_SLOT]], align 8, !dbg [[DBG26]]
	// DEBUG1-NEXT: call void @__clang_call_terminate(i8* [[EXN]]) #[[ATTR8]], !dbg [[DBG25]]			// DEBUG1-NEXT: call void @__clang_call_terminate(i8* [[EXN]]) #[[ATTR8]], !dbg [[DBG26]]
	// DEBUG1-NEXT: unreachable, !dbg [[DBG25]]			// DEBUG1-NEXT: unreachable, !dbg [[DBG26]]
	//			//

clang/test/OpenMP/teams_distribute_collapse_codegen.cpp

	Show First 20 Lines • Show All 2,380 Lines • ▼ Show 20 Lines
	//			//
	//			//
	// CHECK12-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg			// CHECK12-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
	// CHECK12-SAME: () #[[ATTR5:[0-9]+]] {			// CHECK12-SAME: () #[[ATTR5:[0-9]+]] {
	// CHECK12-NEXT: entry:			// CHECK12-NEXT: entry:
	// CHECK12-NEXT: call void @__tgt_register_requires(i64 1)			// CHECK12-NEXT: call void @__tgt_register_requires(i64 1)
	// CHECK12-NEXT: ret void			// CHECK12-NEXT: ret void
	//			//
	//
	No newline at end of file

clang/test/OpenMP/teams_distribute_lastprivate_codegen.cpp

This file is larger than 256 KB, so syntax highlighting is disabled by default.

	Show First 20 Lines • Show All 3,542 Lines • ▼ Show 20 Lines
	//			//
	//			//
	// CHECK12-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg			// CHECK12-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
	// CHECK12-SAME: () #[[ATTR6:[0-9]+]] {			// CHECK12-SAME: () #[[ATTR6:[0-9]+]] {
	// CHECK12-NEXT: entry:			// CHECK12-NEXT: entry:
	// CHECK12-NEXT: call void @__tgt_register_requires(i64 1)			// CHECK12-NEXT: call void @__tgt_register_requires(i64 1)
	// CHECK12-NEXT: ret void			// CHECK12-NEXT: ret void
	//			//
	//
	No newline at end of file

clang/test/OpenMP/teams_distribute_parallel_for_collapse_codegen.cpp

	Show First 20 Lines • Show All 3,457 Lines • ▼ Show 20 Lines
	//			//
	//			//
	// CHECK12-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg			// CHECK12-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
	// CHECK12-SAME: () #[[ATTR5:[0-9]+]] {			// CHECK12-SAME: () #[[ATTR5:[0-9]+]] {
	// CHECK12-NEXT: entry:			// CHECK12-NEXT: entry:
	// CHECK12-NEXT: call void @__tgt_register_requires(i64 1)			// CHECK12-NEXT: call void @__tgt_register_requires(i64 1)
	// CHECK12-NEXT: ret void			// CHECK12-NEXT: ret void
	//			//
	//
	No newline at end of file

clang/test/OpenMP/teams_distribute_parallel_for_copyin_codegen.cpp

	Show First 20 Lines • Show All 2,119 Lines • ▼ Show 20 Lines
	//			//
	//			//
	// CHECK10-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg			// CHECK10-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
	// CHECK10-SAME: () #[[ATTR5:[0-9]+]] {			// CHECK10-SAME: () #[[ATTR5:[0-9]+]] {
	// CHECK10-NEXT: entry:			// CHECK10-NEXT: entry:
	// CHECK10-NEXT: call void @__tgt_register_requires(i64 1)			// CHECK10-NEXT: call void @__tgt_register_requires(i64 1)
	// CHECK10-NEXT: ret void			// CHECK10-NEXT: ret void
	//			//
	//
	No newline at end of file

clang/test/OpenMP/teams_distribute_parallel_for_lastprivate_codegen.cpp

This file is larger than 256 KB, so syntax highlighting is disabled by default.

	Show First 20 Lines • Show All 5,200 Lines • ▼ Show 20 Lines
	//			//
	//			//
	// CHECK12-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg			// CHECK12-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
	// CHECK12-SAME: () #[[ATTR6:[0-9]+]] {			// CHECK12-SAME: () #[[ATTR6:[0-9]+]] {
	// CHECK12-NEXT: entry:			// CHECK12-NEXT: entry:
	// CHECK12-NEXT: call void @__tgt_register_requires(i64 1)			// CHECK12-NEXT: call void @__tgt_register_requires(i64 1)
	// CHECK12-NEXT: ret void			// CHECK12-NEXT: ret void
	//			//
	//
	No newline at end of file

clang/test/OpenMP/teams_distribute_parallel_for_proc_bind_codegen.cpp

	Show First 20 Lines • Show All 969 Lines • ▼ Show 20 Lines
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg			// CHECK2-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
	// CHECK2-SAME: () #[[ATTR4:[0-9]+]] {			// CHECK2-SAME: () #[[ATTR4:[0-9]+]] {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	// CHECK2-NEXT: call void @__tgt_register_requires(i64 1)			// CHECK2-NEXT: call void @__tgt_register_requires(i64 1)
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	//			//
	//
	No newline at end of file

clang/test/OpenMP/teams_distribute_parallel_for_reduction_codegen.cpp

	Show First 20 Lines • Show All 2,888 Lines • ▼ Show 20 Lines
	//			//
	//			//
	// CHECK10-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg			// CHECK10-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
	// CHECK10-SAME: () #[[ATTR6:[0-9]+]] {			// CHECK10-SAME: () #[[ATTR6:[0-9]+]] {
	// CHECK10-NEXT: entry:			// CHECK10-NEXT: entry:
	// CHECK10-NEXT: call void @__tgt_register_requires(i64 1)			// CHECK10-NEXT: call void @__tgt_register_requires(i64 1)
	// CHECK10-NEXT: ret void			// CHECK10-NEXT: ret void
	//			//
	//
	No newline at end of file

clang/test/OpenMP/teams_distribute_parallel_for_simd_collapse_codegen.cpp

This file is larger than 256 KB, so syntax highlighting is disabled by default.

	Show First 20 Lines • Show All 197 Lines • ▼ Show 20 Lines
	// CHECK1-NEXT: br label [[COND_END]]			// CHECK1-NEXT: br label [[COND_END]]
	// CHECK1: cond.end:			// CHECK1: cond.end:
	// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 56087, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]			// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 56087, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
	// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK1-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK1-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK1-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK1: omp.inner.for.cond:			// CHECK1: omp.inner.for.cond:
	// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !4
	// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !4
	// CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK1: omp.inner.for.body:			// CHECK1: omp.inner.for.body:
	// CHECK1-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK1-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !4
	// CHECK1-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64			// CHECK1-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
	// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !4
	// CHECK1-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64			// CHECK1-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
	// CHECK1-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, %struct.SS) @.omp_outlined..1 to void (i32, i32, ...)), i64 [[TMP9]], i64 [[TMP11]], %struct.SS [[TMP0]])			// CHECK1-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, %struct.SS) @.omp_outlined..1 to void (i32, i32, ...)), i64 [[TMP9]], i64 [[TMP11]], %struct.SS [[TMP0]]), !llvm.access.group !4
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK1: omp.inner.for.inc:			// CHECK1: omp.inner.for.inc:
	// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !4
	// CHECK1-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK1-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !4
	// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]			// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]
	// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]
	// CHECK1: omp.inner.for.end:			// CHECK1: omp.inner.for.end:
	// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK1: omp.loop.exit:			// CHECK1: omp.loop.exit:
	// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])			// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
	// CHECK1-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK1-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK1-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0			// CHECK1-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0
	// CHECK1-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK1-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK1: .omp.final.then:			// CHECK1: .omp.final.then:
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	// CHECK1-NEXT: br label [[COND_END]]			// CHECK1-NEXT: br label [[COND_END]]
	// CHECK1: cond.end:			// CHECK1: cond.end:
	// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 56087, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ]			// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 56087, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ]
	// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK1-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK1: omp.inner.for.cond:			// CHECK1: omp.inner.for.cond:
	// CHECK1-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !8
	// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !8
	// CHECK1-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]			// CHECK1-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
	// CHECK1-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK1-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK1: omp.inner.for.body:			// CHECK1: omp.inner.for.body:
	// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !8
	// CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 456			// CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 456
	// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1			// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1
	// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !8
	// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !8
	// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !8
	// CHECK1-NEXT: [[DIV4:%.*]] = sdiv i32 [[TMP12]], 456			// CHECK1-NEXT: [[DIV4:%.*]] = sdiv i32 [[TMP12]], 456
	// CHECK1-NEXT: [[MUL5:%.*]] = mul nsw i32 [[DIV4]], 456			// CHECK1-NEXT: [[MUL5:%.*]] = mul nsw i32 [[DIV4]], 456
	// CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP11]], [[MUL5]]			// CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP11]], [[MUL5]]
	// CHECK1-NEXT: [[MUL6:%.*]] = mul nsw i32 [[SUB]], 1			// CHECK1-NEXT: [[MUL6:%.*]] = mul nsw i32 [[SUB]], 1
	// CHECK1-NEXT: [[ADD7:%.*]] = add nsw i32 0, [[MUL6]]			// CHECK1-NEXT: [[ADD7:%.*]] = add nsw i32 0, [[MUL6]]
	// CHECK1-NEXT: store i32 [[ADD7]], i32* [[J]], align 4			// CHECK1-NEXT: store i32 [[ADD7]], i32* [[J]], align 4, !llvm.access.group !8
	// CHECK1-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 0			// CHECK1-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 0
	// CHECK1-NEXT: [[TMP13:%.]] = load i32, i32 [[I]], align 4			// CHECK1-NEXT: [[TMP13:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !8
	// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64			// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64
	// CHECK1-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]] [[A]], i64 0, i64 [[IDXPROM]]			// CHECK1-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]] [[A]], i64 0, i64 [[IDXPROM]]
	// CHECK1-NEXT: [[TMP14:%.]] = load i32, i32 [[J]], align 4			// CHECK1-NEXT: [[TMP14:%.]] = load i32, i32 [[J]], align 4, !llvm.access.group !8
	// CHECK1-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP14]] to i64			// CHECK1-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP14]] to i64
	// CHECK1-NEXT: [[ARRAYIDX9:%.]] = getelementptr inbounds [456 x i32], [456 x i32] [[ARRAYIDX]], i64 0, i64 [[IDXPROM8]]			// CHECK1-NEXT: [[ARRAYIDX9:%.]] = getelementptr inbounds [456 x i32], [456 x i32] [[ARRAYIDX]], i64 0, i64 [[IDXPROM8]]
	// CHECK1-NEXT: store i32 0, i32* [[ARRAYIDX9]], align 4			// CHECK1-NEXT: store i32 0, i32* [[ARRAYIDX9]], align 4, !llvm.access.group !8
	// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK1: omp.body.continue:			// CHECK1: omp.body.continue:
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK1: omp.inner.for.inc:			// CHECK1: omp.inner.for.inc:
	// CHECK1-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !8
	// CHECK1-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP15]], 1			// CHECK1-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP15]], 1
	// CHECK1-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]
	// CHECK1: omp.inner.for.end:			// CHECK1: omp.inner.for.end:
	// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK1: omp.loop.exit:			// CHECK1: omp.loop.exit:
	// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]])			// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]])
	// CHECK1-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK1-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK1-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0			// CHECK1-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0
	// CHECK1-NEXT: br i1 [[TMP17]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK1-NEXT: br i1 [[TMP17]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK1: .omp.final.then:			// CHECK1: .omp.final.then:
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	// CHECK2-NEXT: br label [[COND_END]]			// CHECK2-NEXT: br label [[COND_END]]
	// CHECK2: cond.end:			// CHECK2: cond.end:
	// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 56087, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]			// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 56087, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
	// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK2-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK2-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK2-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK2: omp.inner.for.cond:			// CHECK2: omp.inner.for.cond:
	// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !4
	// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !4
	// CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK2: omp.inner.for.body:			// CHECK2: omp.inner.for.body:
	// CHECK2-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK2-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !4
	// CHECK2-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64			// CHECK2-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
	// CHECK2-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK2-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !4
	// CHECK2-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64			// CHECK2-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
	// CHECK2-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, %struct.SS) @.omp_outlined..1 to void (i32, i32, ...)), i64 [[TMP9]], i64 [[TMP11]], %struct.SS [[TMP0]])			// CHECK2-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, %struct.SS) @.omp_outlined..1 to void (i32, i32, ...)), i64 [[TMP9]], i64 [[TMP11]], %struct.SS [[TMP0]]), !llvm.access.group !4
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK2: omp.inner.for.inc:			// CHECK2: omp.inner.for.inc:
	// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !4
	// CHECK2-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK2-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !4
	// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]			// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]
	// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]
	// CHECK2: omp.inner.for.end:			// CHECK2: omp.inner.for.end:
	// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK2: omp.loop.exit:			// CHECK2: omp.loop.exit:
	// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])			// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
	// CHECK2-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK2-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK2-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0			// CHECK2-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0
	// CHECK2-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK2-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK2: .omp.final.then:			// CHECK2: .omp.final.then:
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	// CHECK2-NEXT: br label [[COND_END]]			// CHECK2-NEXT: br label [[COND_END]]
	// CHECK2: cond.end:			// CHECK2: cond.end:
	// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 56087, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ]			// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 56087, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ]
	// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK2-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK2: omp.inner.for.cond:			// CHECK2: omp.inner.for.cond:
	// CHECK2-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !8
	// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !8
	// CHECK2-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]			// CHECK2-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
	// CHECK2-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK2-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK2: omp.inner.for.body:			// CHECK2: omp.inner.for.body:
	// CHECK2-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !8
	// CHECK2-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 456			// CHECK2-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 456
	// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1			// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1
	// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !8
	// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !8
	// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !8
	// CHECK2-NEXT: [[DIV4:%.*]] = sdiv i32 [[TMP12]], 456			// CHECK2-NEXT: [[DIV4:%.*]] = sdiv i32 [[TMP12]], 456
	// CHECK2-NEXT: [[MUL5:%.*]] = mul nsw i32 [[DIV4]], 456			// CHECK2-NEXT: [[MUL5:%.*]] = mul nsw i32 [[DIV4]], 456
	// CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP11]], [[MUL5]]			// CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP11]], [[MUL5]]
	// CHECK2-NEXT: [[MUL6:%.*]] = mul nsw i32 [[SUB]], 1			// CHECK2-NEXT: [[MUL6:%.*]] = mul nsw i32 [[SUB]], 1
	// CHECK2-NEXT: [[ADD7:%.*]] = add nsw i32 0, [[MUL6]]			// CHECK2-NEXT: [[ADD7:%.*]] = add nsw i32 0, [[MUL6]]
	// CHECK2-NEXT: store i32 [[ADD7]], i32* [[J]], align 4			// CHECK2-NEXT: store i32 [[ADD7]], i32* [[J]], align 4, !llvm.access.group !8
	// CHECK2-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 0			// CHECK2-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 0
	// CHECK2-NEXT: [[TMP13:%.]] = load i32, i32 [[I]], align 4			// CHECK2-NEXT: [[TMP13:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !8
	// CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64			// CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64
	// CHECK2-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]] [[A]], i64 0, i64 [[IDXPROM]]			// CHECK2-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]] [[A]], i64 0, i64 [[IDXPROM]]
	// CHECK2-NEXT: [[TMP14:%.]] = load i32, i32 [[J]], align 4			// CHECK2-NEXT: [[TMP14:%.]] = load i32, i32 [[J]], align 4, !llvm.access.group !8
	// CHECK2-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP14]] to i64			// CHECK2-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP14]] to i64
	// CHECK2-NEXT: [[ARRAYIDX9:%.]] = getelementptr inbounds [456 x i32], [456 x i32] [[ARRAYIDX]], i64 0, i64 [[IDXPROM8]]			// CHECK2-NEXT: [[ARRAYIDX9:%.]] = getelementptr inbounds [456 x i32], [456 x i32] [[ARRAYIDX]], i64 0, i64 [[IDXPROM8]]
	// CHECK2-NEXT: store i32 0, i32* [[ARRAYIDX9]], align 4			// CHECK2-NEXT: store i32 0, i32* [[ARRAYIDX9]], align 4, !llvm.access.group !8
	// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK2: omp.body.continue:			// CHECK2: omp.body.continue:
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK2: omp.inner.for.inc:			// CHECK2: omp.inner.for.inc:
	// CHECK2-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !8
	// CHECK2-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP15]], 1			// CHECK2-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP15]], 1
	// CHECK2-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]
	// CHECK2: omp.inner.for.end:			// CHECK2: omp.inner.for.end:
	// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK2: omp.loop.exit:			// CHECK2: omp.loop.exit:
	// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]])			// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]])
	// CHECK2-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK2-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK2-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0			// CHECK2-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0
	// CHECK2-NEXT: br i1 [[TMP17]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK2-NEXT: br i1 [[TMP17]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK2: .omp.final.then:			// CHECK2: .omp.final.then:
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	// CHECK3-NEXT: br label [[COND_END]]			// CHECK3-NEXT: br label [[COND_END]]
	// CHECK3: cond.end:			// CHECK3: cond.end:
	// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 56087, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]			// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 56087, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
	// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK3-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK3-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK3-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK3-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK3: omp.inner.for.cond:			// CHECK3: omp.inner.for.cond:
	// CHECK3-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK3-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK3-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK3-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5
	// CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK3: omp.inner.for.body:			// CHECK3: omp.inner.for.body:
	// CHECK3-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK3-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !5
	// CHECK3-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK3-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5
	// CHECK3-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i32, i32, %struct.SS) @.omp_outlined..1 to void (i32, i32, ...)), i32 [[TMP8]], i32 [[TMP9]], %struct.SS [[TMP0]])			// CHECK3-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i32, i32, %struct.SS) @.omp_outlined..1 to void (i32, i32, ...)), i32 [[TMP8]], i32 [[TMP9]], %struct.SS [[TMP0]]), !llvm.access.group !5
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK3: omp.inner.for.inc:			// CHECK3: omp.inner.for.inc:
	// CHECK3-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK3-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK3-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK3-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !5
	// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP10]], [[TMP11]]			// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP10]], [[TMP11]]
	// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]
	// CHECK3: omp.inner.for.end:			// CHECK3: omp.inner.for.end:
	// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK3: omp.loop.exit:			// CHECK3: omp.loop.exit:
	// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])			// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
	// CHECK3-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK3-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK3-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0			// CHECK3-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0
	// CHECK3-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK3-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK3: .omp.final.then:			// CHECK3: .omp.final.then:
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	// CHECK3-NEXT: br label [[COND_END]]			// CHECK3-NEXT: br label [[COND_END]]
	// CHECK3: cond.end:			// CHECK3: cond.end:
	// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 56087, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ]			// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 56087, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ]
	// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK3-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK3-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK3-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4			// CHECK3-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK3: omp.inner.for.cond:			// CHECK3: omp.inner.for.cond:
	// CHECK3-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK3-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK3-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK3-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !9
	// CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]			// CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
	// CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK3: omp.inner.for.body:			// CHECK3: omp.inner.for.body:
	// CHECK3-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK3-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK3-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 456			// CHECK3-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 456
	// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1			// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1
	// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9
	// CHECK3-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK3-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK3-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK3-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK3-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP12]], 456			// CHECK3-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP12]], 456
	// CHECK3-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 456			// CHECK3-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 456
	// CHECK3-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP11]], [[MUL4]]			// CHECK3-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP11]], [[MUL4]]
	// CHECK3-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1			// CHECK3-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1
	// CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]]			// CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]]
	// CHECK3-NEXT: store i32 [[ADD6]], i32* [[J]], align 4			// CHECK3-NEXT: store i32 [[ADD6]], i32* [[J]], align 4, !llvm.access.group !9
	// CHECK3-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 0			// CHECK3-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 0
	// CHECK3-NEXT: [[TMP13:%.]] = load i32, i32 [[I]], align 4			// CHECK3-NEXT: [[TMP13:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !9
	// CHECK3-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]] [[A]], i32 0, i32 [[TMP13]]			// CHECK3-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]] [[A]], i32 0, i32 [[TMP13]]
	// CHECK3-NEXT: [[TMP14:%.]] = load i32, i32 [[J]], align 4			// CHECK3-NEXT: [[TMP14:%.]] = load i32, i32 [[J]], align 4, !llvm.access.group !9
	// CHECK3-NEXT: [[ARRAYIDX7:%.]] = getelementptr inbounds [456 x i32], [456 x i32] [[ARRAYIDX]], i32 0, i32 [[TMP14]]			// CHECK3-NEXT: [[ARRAYIDX7:%.]] = getelementptr inbounds [456 x i32], [456 x i32] [[ARRAYIDX]], i32 0, i32 [[TMP14]]
	// CHECK3-NEXT: store i32 0, i32* [[ARRAYIDX7]], align 4			// CHECK3-NEXT: store i32 0, i32* [[ARRAYIDX7]], align 4, !llvm.access.group !9
	// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK3: omp.body.continue:			// CHECK3: omp.body.continue:
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK3: omp.inner.for.inc:			// CHECK3: omp.inner.for.inc:
	// CHECK3-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK3-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK3-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP15]], 1			// CHECK3-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP15]], 1
	// CHECK3-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4			// CHECK3-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]
	// CHECK3: omp.inner.for.end:			// CHECK3: omp.inner.for.end:
	// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK3: omp.loop.exit:			// CHECK3: omp.loop.exit:
	// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]])			// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]])
	// CHECK3-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK3-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK3-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0			// CHECK3-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0
	// CHECK3-NEXT: br i1 [[TMP17]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK3-NEXT: br i1 [[TMP17]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK3: .omp.final.then:			// CHECK3: .omp.final.then:
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	// CHECK4-NEXT: br label [[COND_END]]			// CHECK4-NEXT: br label [[COND_END]]
	// CHECK4: cond.end:			// CHECK4: cond.end:
	// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 56087, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]			// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 56087, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
	// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK4-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK4-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK4-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK4-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK4: omp.inner.for.cond:			// CHECK4: omp.inner.for.cond:
	// CHECK4-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK4-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK4-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK4-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5
	// CHECK4-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK4-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK4-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK4-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK4: omp.inner.for.body:			// CHECK4: omp.inner.for.body:
	// CHECK4-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK4-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !5
	// CHECK4-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK4-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5
	// CHECK4-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i32, i32, %struct.SS) @.omp_outlined..1 to void (i32, i32, ...)), i32 [[TMP8]], i32 [[TMP9]], %struct.SS [[TMP0]])			// CHECK4-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i32, i32, %struct.SS) @.omp_outlined..1 to void (i32, i32, ...)), i32 [[TMP8]], i32 [[TMP9]], %struct.SS [[TMP0]]), !llvm.access.group !5
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK4: omp.inner.for.inc:			// CHECK4: omp.inner.for.inc:
	// CHECK4-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK4-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK4-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK4-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !5
	// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP10]], [[TMP11]]			// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP10]], [[TMP11]]
	// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]
	// CHECK4: omp.inner.for.end:			// CHECK4: omp.inner.for.end:
	// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK4: omp.loop.exit:			// CHECK4: omp.loop.exit:
	// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])			// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
	// CHECK4-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK4-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK4-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0			// CHECK4-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0
	// CHECK4-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK4-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK4: .omp.final.then:			// CHECK4: .omp.final.then:
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	// CHECK4-NEXT: br label [[COND_END]]			// CHECK4-NEXT: br label [[COND_END]]
	// CHECK4: cond.end:			// CHECK4: cond.end:
	// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 56087, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ]			// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 56087, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ]
	// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK4-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK4-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK4-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4			// CHECK4-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK4: omp.inner.for.cond:			// CHECK4: omp.inner.for.cond:
	// CHECK4-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK4-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK4-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK4-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !9
	// CHECK4-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]			// CHECK4-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
	// CHECK4-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK4-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK4: omp.inner.for.body:			// CHECK4: omp.inner.for.body:
	// CHECK4-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK4-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK4-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 456			// CHECK4-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 456
	// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1			// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1
	// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9
	// CHECK4-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK4-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK4-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK4-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK4-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP12]], 456			// CHECK4-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP12]], 456
	// CHECK4-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 456			// CHECK4-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 456
	// CHECK4-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP11]], [[MUL4]]			// CHECK4-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP11]], [[MUL4]]
	// CHECK4-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1			// CHECK4-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1
	// CHECK4-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]]			// CHECK4-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]]
	// CHECK4-NEXT: store i32 [[ADD6]], i32* [[J]], align 4			// CHECK4-NEXT: store i32 [[ADD6]], i32* [[J]], align 4, !llvm.access.group !9
	// CHECK4-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 0			// CHECK4-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 0
	// CHECK4-NEXT: [[TMP13:%.]] = load i32, i32 [[I]], align 4			// CHECK4-NEXT: [[TMP13:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !9
	// CHECK4-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]] [[A]], i32 0, i32 [[TMP13]]			// CHECK4-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]] [[A]], i32 0, i32 [[TMP13]]
	// CHECK4-NEXT: [[TMP14:%.]] = load i32, i32 [[J]], align 4			// CHECK4-NEXT: [[TMP14:%.]] = load i32, i32 [[J]], align 4, !llvm.access.group !9
	// CHECK4-NEXT: [[ARRAYIDX7:%.]] = getelementptr inbounds [456 x i32], [456 x i32] [[ARRAYIDX]], i32 0, i32 [[TMP14]]			// CHECK4-NEXT: [[ARRAYIDX7:%.]] = getelementptr inbounds [456 x i32], [456 x i32] [[ARRAYIDX]], i32 0, i32 [[TMP14]]
	// CHECK4-NEXT: store i32 0, i32* [[ARRAYIDX7]], align 4			// CHECK4-NEXT: store i32 0, i32* [[ARRAYIDX7]], align 4, !llvm.access.group !9
	// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK4: omp.body.continue:			// CHECK4: omp.body.continue:
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK4: omp.inner.for.inc:			// CHECK4: omp.inner.for.inc:
	// CHECK4-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK4-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK4-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP15]], 1			// CHECK4-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP15]], 1
	// CHECK4-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4			// CHECK4-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]
	// CHECK4: omp.inner.for.end:			// CHECK4: omp.inner.for.end:
	// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK4: omp.loop.exit:			// CHECK4: omp.loop.exit:
	// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]])			// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]])
	// CHECK4-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK4-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK4-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0			// CHECK4-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0
	// CHECK4-NEXT: br i1 [[TMP17]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK4-NEXT: br i1 [[TMP17]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK4: .omp.final.then:			// CHECK4: .omp.final.then:
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	// CHECK9-NEXT: br label [[COND_END]]			// CHECK9-NEXT: br label [[COND_END]]
	// CHECK9: cond.end:			// CHECK9: cond.end:
	// CHECK9-NEXT: [[COND:%.*]] = phi i64 [ [[TMP16]], [[COND_TRUE]] ], [ [[TMP17]], [[COND_FALSE]] ]			// CHECK9-NEXT: [[COND:%.*]] = phi i64 [ [[TMP16]], [[COND_TRUE]] ], [ [[TMP17]], [[COND_FALSE]] ]
	// CHECK9-NEXT: store i64 [[COND]], i64* [[DOTOMP_COMB_UB]], align 8			// CHECK9-NEXT: store i64 [[COND]], i64* [[DOTOMP_COMB_UB]], align 8
	// CHECK9-NEXT: [[TMP18:%.]] = load i64, i64 [[DOTOMP_COMB_LB]], align 8			// CHECK9-NEXT: [[TMP18:%.]] = load i64, i64 [[DOTOMP_COMB_LB]], align 8
	// CHECK9-NEXT: store i64 [[TMP18]], i64* [[DOTOMP_IV]], align 8			// CHECK9-NEXT: store i64 [[TMP18]], i64* [[DOTOMP_IV]], align 8
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK9: omp.inner.for.cond:			// CHECK9: omp.inner.for.cond:
	// CHECK9-NEXT: [[TMP19:%.]] = load i64, i64 [[DOTOMP_IV]], align 8			// CHECK9-NEXT: [[TMP19:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !5
	// CHECK9-NEXT: [[TMP20:%.]] = load i64, i64 [[DOTOMP_COMB_UB]], align 8			// CHECK9-NEXT: [[TMP20:%.]] = load i64, i64 [[DOTOMP_COMB_UB]], align 8, !llvm.access.group !5
	// CHECK9-NEXT: [[CMP14:%.*]] = icmp sle i64 [[TMP19]], [[TMP20]]			// CHECK9-NEXT: [[CMP14:%.*]] = icmp sle i64 [[TMP19]], [[TMP20]]
	// CHECK9-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK9-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK9: omp.inner.for.body:			// CHECK9: omp.inner.for.body:
	// CHECK9-NEXT: [[TMP21:%.]] = load i64, i64 [[DOTOMP_COMB_LB]], align 8			// CHECK9-NEXT: [[TMP21:%.]] = load i64, i64 [[DOTOMP_COMB_LB]], align 8, !llvm.access.group !5
	// CHECK9-NEXT: [[TMP22:%.]] = load i64, i64 [[DOTOMP_COMB_UB]], align 8			// CHECK9-NEXT: [[TMP22:%.]] = load i64, i64 [[DOTOMP_COMB_UB]], align 8, !llvm.access.group !5
	// CHECK9-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i32, i32, i64, i64, i32) @.omp_outlined..1 to void (i32, i32, ...)), i64 [[TMP21]], i64 [[TMP22]], i32 [[TMP0]], i32* [[TMP1]], i64 [[TMP2]], i64 [[TMP3]], i32* [[TMP4]])			// CHECK9-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i32, i32, i64, i64, i32) @.omp_outlined..1 to void (i32, i32, ...)), i64 [[TMP21]], i64 [[TMP22]], i32 [[TMP0]], i32* [[TMP1]], i64 [[TMP2]], i64 [[TMP3]], i32* [[TMP4]]), !llvm.access.group !5
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK9: omp.inner.for.inc:			// CHECK9: omp.inner.for.inc:
	// CHECK9-NEXT: [[TMP23:%.]] = load i64, i64 [[DOTOMP_IV]], align 8			// CHECK9-NEXT: [[TMP23:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !5
	// CHECK9-NEXT: [[TMP24:%.]] = load i64, i64 [[DOTOMP_STRIDE]], align 8			// CHECK9-NEXT: [[TMP24:%.]] = load i64, i64 [[DOTOMP_STRIDE]], align 8, !llvm.access.group !5
	// CHECK9-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP23]], [[TMP24]]			// CHECK9-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP23]], [[TMP24]]
	// CHECK9-NEXT: store i64 [[ADD]], i64* [[DOTOMP_IV]], align 8			// CHECK9-NEXT: store i64 [[ADD]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !5
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]
	// CHECK9: omp.inner.for.end:			// CHECK9: omp.inner.for.end:
	// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK9: omp.loop.exit:			// CHECK9: omp.loop.exit:
	// CHECK9-NEXT: [[TMP25:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK9-NEXT: [[TMP25:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK9-NEXT: [[TMP26:%.]] = load i32, i32 [[TMP25]], align 4			// CHECK9-NEXT: [[TMP26:%.]] = load i32, i32 [[TMP25]], align 4
	// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]])			// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]])
	// CHECK9-NEXT: [[TMP27:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK9-NEXT: [[TMP27:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK9-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0			// CHECK9-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0
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	// CHECK9-NEXT: br label [[COND_END]]			// CHECK9-NEXT: br label [[COND_END]]
	// CHECK9: cond.end:			// CHECK9: cond.end:
	// CHECK9-NEXT: [[COND:%.*]] = phi i64 [ [[TMP18]], [[COND_TRUE]] ], [ [[TMP19]], [[COND_FALSE]] ]			// CHECK9-NEXT: [[COND:%.*]] = phi i64 [ [[TMP18]], [[COND_TRUE]] ], [ [[TMP19]], [[COND_FALSE]] ]
	// CHECK9-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8			// CHECK9-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
	// CHECK9-NEXT: [[TMP20:%.]] = load i64, i64 [[DOTOMP_LB]], align 8			// CHECK9-NEXT: [[TMP20:%.]] = load i64, i64 [[DOTOMP_LB]], align 8
	// CHECK9-NEXT: store i64 [[TMP20]], i64* [[DOTOMP_IV]], align 8			// CHECK9-NEXT: store i64 [[TMP20]], i64* [[DOTOMP_IV]], align 8
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK9: omp.inner.for.cond:			// CHECK9: omp.inner.for.cond:
	// CHECK9-NEXT: [[TMP21:%.]] = load i64, i64 [[DOTOMP_IV]], align 8			// CHECK9-NEXT: [[TMP21:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !9
	// CHECK9-NEXT: [[TMP22:%.]] = load i64, i64 [[DOTOMP_UB]], align 8			// CHECK9-NEXT: [[TMP22:%.]] = load i64, i64 [[DOTOMP_UB]], align 8, !llvm.access.group !9
	// CHECK9-NEXT: [[CMP14:%.*]] = icmp sle i64 [[TMP21]], [[TMP22]]			// CHECK9-NEXT: [[CMP14:%.*]] = icmp sle i64 [[TMP21]], [[TMP22]]
	// CHECK9-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK9-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK9: omp.inner.for.body:			// CHECK9: omp.inner.for.body:
	// CHECK9-NEXT: [[TMP23:%.]] = load i64, i64 [[DOTOMP_IV]], align 8			// CHECK9-NEXT: [[TMP23:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !9
	// CHECK9-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_4]], align 4			// CHECK9-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_4]], align 4, !llvm.access.group !9
	// CHECK9-NEXT: [[SUB15:%.*]] = sub nsw i32 [[TMP24]], 0			// CHECK9-NEXT: [[SUB15:%.*]] = sub nsw i32 [[TMP24]], 0
	// CHECK9-NEXT: [[DIV16:%.*]] = sdiv i32 [[SUB15]], 1			// CHECK9-NEXT: [[DIV16:%.*]] = sdiv i32 [[SUB15]], 1
	// CHECK9-NEXT: [[MUL17:%.*]] = mul nsw i32 1, [[DIV16]]			// CHECK9-NEXT: [[MUL17:%.*]] = mul nsw i32 1, [[DIV16]]
	// CHECK9-NEXT: [[CONV18:%.*]] = sext i32 [[MUL17]] to i64			// CHECK9-NEXT: [[CONV18:%.*]] = sext i32 [[MUL17]] to i64
	// CHECK9-NEXT: [[DIV19:%.*]] = sdiv i64 [[TMP23]], [[CONV18]]			// CHECK9-NEXT: [[DIV19:%.*]] = sdiv i64 [[TMP23]], [[CONV18]]
	// CHECK9-NEXT: [[MUL20:%.*]] = mul nsw i64 [[DIV19]], 1			// CHECK9-NEXT: [[MUL20:%.*]] = mul nsw i64 [[DIV19]], 1
	// CHECK9-NEXT: [[ADD:%.*]] = add nsw i64 0, [[MUL20]]			// CHECK9-NEXT: [[ADD:%.*]] = add nsw i64 0, [[MUL20]]
	// CHECK9-NEXT: [[CONV21:%.*]] = trunc i64 [[ADD]] to i32			// CHECK9-NEXT: [[CONV21:%.*]] = trunc i64 [[ADD]] to i32
	// CHECK9-NEXT: store i32 [[CONV21]], i32* [[I11]], align 4			// CHECK9-NEXT: store i32 [[CONV21]], i32* [[I11]], align 4, !llvm.access.group !9
	// CHECK9-NEXT: [[TMP25:%.]] = load i64, i64 [[DOTOMP_IV]], align 8			// CHECK9-NEXT: [[TMP25:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !9
	// CHECK9-NEXT: [[TMP26:%.]] = load i64, i64 [[DOTOMP_IV]], align 8			// CHECK9-NEXT: [[TMP26:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !9
	// CHECK9-NEXT: [[TMP27:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_4]], align 4			// CHECK9-NEXT: [[TMP27:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_4]], align 4, !llvm.access.group !9
	// CHECK9-NEXT: [[SUB22:%.*]] = sub nsw i32 [[TMP27]], 0			// CHECK9-NEXT: [[SUB22:%.*]] = sub nsw i32 [[TMP27]], 0
	// CHECK9-NEXT: [[DIV23:%.*]] = sdiv i32 [[SUB22]], 1			// CHECK9-NEXT: [[DIV23:%.*]] = sdiv i32 [[SUB22]], 1
	// CHECK9-NEXT: [[MUL24:%.*]] = mul nsw i32 1, [[DIV23]]			// CHECK9-NEXT: [[MUL24:%.*]] = mul nsw i32 1, [[DIV23]]
	// CHECK9-NEXT: [[CONV25:%.*]] = sext i32 [[MUL24]] to i64			// CHECK9-NEXT: [[CONV25:%.*]] = sext i32 [[MUL24]] to i64
	// CHECK9-NEXT: [[DIV26:%.*]] = sdiv i64 [[TMP26]], [[CONV25]]			// CHECK9-NEXT: [[DIV26:%.*]] = sdiv i64 [[TMP26]], [[CONV25]]
	// CHECK9-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_4]], align 4			// CHECK9-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_4]], align 4, !llvm.access.group !9
	// CHECK9-NEXT: [[SUB27:%.*]] = sub nsw i32 [[TMP28]], 0			// CHECK9-NEXT: [[SUB27:%.*]] = sub nsw i32 [[TMP28]], 0
	// CHECK9-NEXT: [[DIV28:%.*]] = sdiv i32 [[SUB27]], 1			// CHECK9-NEXT: [[DIV28:%.*]] = sdiv i32 [[SUB27]], 1
	// CHECK9-NEXT: [[MUL29:%.*]] = mul nsw i32 1, [[DIV28]]			// CHECK9-NEXT: [[MUL29:%.*]] = mul nsw i32 1, [[DIV28]]
	// CHECK9-NEXT: [[CONV30:%.*]] = sext i32 [[MUL29]] to i64			// CHECK9-NEXT: [[CONV30:%.*]] = sext i32 [[MUL29]] to i64
	// CHECK9-NEXT: [[MUL31:%.*]] = mul nsw i64 [[DIV26]], [[CONV30]]			// CHECK9-NEXT: [[MUL31:%.*]] = mul nsw i64 [[DIV26]], [[CONV30]]
	// CHECK9-NEXT: [[SUB32:%.*]] = sub nsw i64 [[TMP25]], [[MUL31]]			// CHECK9-NEXT: [[SUB32:%.*]] = sub nsw i64 [[TMP25]], [[MUL31]]
	// CHECK9-NEXT: [[MUL33:%.*]] = mul nsw i64 [[SUB32]], 1			// CHECK9-NEXT: [[MUL33:%.*]] = mul nsw i64 [[SUB32]], 1
	// CHECK9-NEXT: [[ADD34:%.*]] = add nsw i64 0, [[MUL33]]			// CHECK9-NEXT: [[ADD34:%.*]] = add nsw i64 0, [[MUL33]]
	// CHECK9-NEXT: [[CONV35:%.*]] = trunc i64 [[ADD34]] to i32			// CHECK9-NEXT: [[CONV35:%.*]] = trunc i64 [[ADD34]] to i32
	// CHECK9-NEXT: store i32 [[CONV35]], i32* [[J12]], align 4			// CHECK9-NEXT: store i32 [[CONV35]], i32* [[J12]], align 4, !llvm.access.group !9
	// CHECK9-NEXT: [[TMP29:%.]] = load i32, i32 [[I11]], align 4			// CHECK9-NEXT: [[TMP29:%.]] = load i32, i32 [[I11]], align 4, !llvm.access.group !9
	// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP29]] to i64			// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP29]] to i64
	// CHECK9-NEXT: [[TMP30:%.*]] = mul nsw i64 [[IDXPROM]], [[TMP3]]			// CHECK9-NEXT: [[TMP30:%.*]] = mul nsw i64 [[IDXPROM]], [[TMP3]]
	// CHECK9-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP4]], i64 [[TMP30]]			// CHECK9-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP4]], i64 [[TMP30]]
	// CHECK9-NEXT: [[TMP31:%.]] = load i32, i32 [[J12]], align 4			// CHECK9-NEXT: [[TMP31:%.]] = load i32, i32 [[J12]], align 4, !llvm.access.group !9
	// CHECK9-NEXT: [[IDXPROM36:%.*]] = sext i32 [[TMP31]] to i64			// CHECK9-NEXT: [[IDXPROM36:%.*]] = sext i32 [[TMP31]] to i64
	// CHECK9-NEXT: [[ARRAYIDX37:%.]] = getelementptr inbounds i32, i32 [[ARRAYIDX]], i64 [[IDXPROM36]]			// CHECK9-NEXT: [[ARRAYIDX37:%.]] = getelementptr inbounds i32, i32 [[ARRAYIDX]], i64 [[IDXPROM36]]
	// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX37]], align 4			// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX37]], align 4, !llvm.access.group !9
	// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK9: omp.body.continue:			// CHECK9: omp.body.continue:
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK9: omp.inner.for.inc:			// CHECK9: omp.inner.for.inc:
	// CHECK9-NEXT: [[TMP32:%.]] = load i64, i64 [[DOTOMP_IV]], align 8			// CHECK9-NEXT: [[TMP32:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !9
	// CHECK9-NEXT: [[ADD38:%.*]] = add nsw i64 [[TMP32]], 1			// CHECK9-NEXT: [[ADD38:%.*]] = add nsw i64 [[TMP32]], 1
	// CHECK9-NEXT: store i64 [[ADD38]], i64* [[DOTOMP_IV]], align 8			// CHECK9-NEXT: store i64 [[ADD38]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !9
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]
	// CHECK9: omp.inner.for.end:			// CHECK9: omp.inner.for.end:
	// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK9: omp.loop.exit:			// CHECK9: omp.loop.exit:
	// CHECK9-NEXT: [[TMP33:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK9-NEXT: [[TMP33:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK9-NEXT: [[TMP34:%.]] = load i32, i32 [[TMP33]], align 4			// CHECK9-NEXT: [[TMP34:%.]] = load i32, i32 [[TMP33]], align 4
	// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP34]])			// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP34]])
	// CHECK9-NEXT: [[TMP35:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK9-NEXT: [[TMP35:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK9-NEXT: [[TMP36:%.*]] = icmp ne i32 [[TMP35]], 0			// CHECK9-NEXT: [[TMP36:%.*]] = icmp ne i32 [[TMP35]], 0
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	// CHECK9-NEXT: br label [[COND_END]]			// CHECK9-NEXT: br label [[COND_END]]
	// CHECK9: cond.end:			// CHECK9: cond.end:
	// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 19, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]			// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 19, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
	// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK9-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK9-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK9: omp.inner.for.cond:			// CHECK9: omp.inner.for.cond:
	// CHECK9-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK9-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK9-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !14
	// CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK9: omp.inner.for.body:			// CHECK9: omp.inner.for.body:
	// CHECK9-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK9-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !14
	// CHECK9-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64			// CHECK9-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
	// CHECK9-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK9-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !14
	// CHECK9-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64			// CHECK9-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
	// CHECK9-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, [10 x [2 x i32]]) @.omp_outlined..3 to void (i32, i32, ...)), i64 [[TMP9]], i64 [[TMP11]], [10 x [2 x i32]] [[TMP0]])			// CHECK9-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, [10 x [2 x i32]]) @.omp_outlined..3 to void (i32, i32, ...)), i64 [[TMP9]], i64 [[TMP11]], [10 x [2 x i32]] [[TMP0]]), !llvm.access.group !14
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK9: omp.inner.for.inc:			// CHECK9: omp.inner.for.inc:
	// CHECK9-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK9-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK9-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !14
	// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]			// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]
	// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]]
	// CHECK9: omp.inner.for.end:			// CHECK9: omp.inner.for.end:
	// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK9: omp.loop.exit:			// CHECK9: omp.loop.exit:
	// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])			// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
	// CHECK9-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK9-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK9-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0			// CHECK9-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0
	// CHECK9-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK9-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK9: .omp.final.then:			// CHECK9: .omp.final.then:
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	// CHECK9-NEXT: br label [[COND_END]]			// CHECK9-NEXT: br label [[COND_END]]
	// CHECK9: cond.end:			// CHECK9: cond.end:
	// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 19, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ]			// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 19, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ]
	// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK9-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK9-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK9-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4			// CHECK9-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK9: omp.inner.for.cond:			// CHECK9: omp.inner.for.cond:
	// CHECK9-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !17
	// CHECK9-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK9-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !17
	// CHECK9-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]			// CHECK9-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
	// CHECK9-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK9-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK9: omp.inner.for.body:			// CHECK9: omp.inner.for.body:
	// CHECK9-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !17
	// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 2			// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 2
	// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1			// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1
	// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !17
	// CHECK9-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !17
	// CHECK9-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !17
	// CHECK9-NEXT: [[DIV4:%.*]] = sdiv i32 [[TMP12]], 2			// CHECK9-NEXT: [[DIV4:%.*]] = sdiv i32 [[TMP12]], 2
	// CHECK9-NEXT: [[MUL5:%.*]] = mul nsw i32 [[DIV4]], 2			// CHECK9-NEXT: [[MUL5:%.*]] = mul nsw i32 [[DIV4]], 2
	// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP11]], [[MUL5]]			// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP11]], [[MUL5]]
	// CHECK9-NEXT: [[MUL6:%.*]] = mul nsw i32 [[SUB]], 1			// CHECK9-NEXT: [[MUL6:%.*]] = mul nsw i32 [[SUB]], 1
	// CHECK9-NEXT: [[ADD7:%.*]] = add nsw i32 0, [[MUL6]]			// CHECK9-NEXT: [[ADD7:%.*]] = add nsw i32 0, [[MUL6]]
	// CHECK9-NEXT: store i32 [[ADD7]], i32* [[J]], align 4			// CHECK9-NEXT: store i32 [[ADD7]], i32* [[J]], align 4, !llvm.access.group !17
	// CHECK9-NEXT: [[TMP13:%.]] = load i32, i32 [[I]], align 4			// CHECK9-NEXT: [[TMP13:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !17
	// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64			// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64
	// CHECK9-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]] [[TMP0]], i64 0, i64 [[IDXPROM]]			// CHECK9-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]] [[TMP0]], i64 0, i64 [[IDXPROM]]
	// CHECK9-NEXT: [[TMP14:%.]] = load i32, i32 [[J]], align 4			// CHECK9-NEXT: [[TMP14:%.]] = load i32, i32 [[J]], align 4, !llvm.access.group !17
	// CHECK9-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP14]] to i64			// CHECK9-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP14]] to i64
	// CHECK9-NEXT: [[ARRAYIDX9:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[ARRAYIDX]], i64 0, i64 [[IDXPROM8]]			// CHECK9-NEXT: [[ARRAYIDX9:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[ARRAYIDX]], i64 0, i64 [[IDXPROM8]]
	// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX9]], align 4			// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX9]], align 4, !llvm.access.group !17
	// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK9: omp.body.continue:			// CHECK9: omp.body.continue:
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK9: omp.inner.for.inc:			// CHECK9: omp.inner.for.inc:
	// CHECK9-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !17
	// CHECK9-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP15]], 1			// CHECK9-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP15]], 1
	// CHECK9-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4			// CHECK9-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]]
	// CHECK9: omp.inner.for.end:			// CHECK9: omp.inner.for.end:
	// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK9: omp.loop.exit:			// CHECK9: omp.loop.exit:
	// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]])			// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]])
	// CHECK9-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK9-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK9-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0			// CHECK9-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0
	// CHECK9-NEXT: br i1 [[TMP17]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK9-NEXT: br i1 [[TMP17]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK9: .omp.final.then:			// CHECK9: .omp.final.then:
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	// CHECK10-NEXT: br label [[COND_END]]			// CHECK10-NEXT: br label [[COND_END]]
	// CHECK10: cond.end:			// CHECK10: cond.end:
	// CHECK10-NEXT: [[COND:%.*]] = phi i64 [ [[TMP16]], [[COND_TRUE]] ], [ [[TMP17]], [[COND_FALSE]] ]			// CHECK10-NEXT: [[COND:%.*]] = phi i64 [ [[TMP16]], [[COND_TRUE]] ], [ [[TMP17]], [[COND_FALSE]] ]
	// CHECK10-NEXT: store i64 [[COND]], i64* [[DOTOMP_COMB_UB]], align 8			// CHECK10-NEXT: store i64 [[COND]], i64* [[DOTOMP_COMB_UB]], align 8
	// CHECK10-NEXT: [[TMP18:%.]] = load i64, i64 [[DOTOMP_COMB_LB]], align 8			// CHECK10-NEXT: [[TMP18:%.]] = load i64, i64 [[DOTOMP_COMB_LB]], align 8
	// CHECK10-NEXT: store i64 [[TMP18]], i64* [[DOTOMP_IV]], align 8			// CHECK10-NEXT: store i64 [[TMP18]], i64* [[DOTOMP_IV]], align 8
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK10: omp.inner.for.cond:			// CHECK10: omp.inner.for.cond:
	// CHECK10-NEXT: [[TMP19:%.]] = load i64, i64 [[DOTOMP_IV]], align 8			// CHECK10-NEXT: [[TMP19:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !5
	// CHECK10-NEXT: [[TMP20:%.]] = load i64, i64 [[DOTOMP_COMB_UB]], align 8			// CHECK10-NEXT: [[TMP20:%.]] = load i64, i64 [[DOTOMP_COMB_UB]], align 8, !llvm.access.group !5
	// CHECK10-NEXT: [[CMP14:%.*]] = icmp sle i64 [[TMP19]], [[TMP20]]			// CHECK10-NEXT: [[CMP14:%.*]] = icmp sle i64 [[TMP19]], [[TMP20]]
	// CHECK10-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK10-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK10: omp.inner.for.body:			// CHECK10: omp.inner.for.body:
	// CHECK10-NEXT: [[TMP21:%.]] = load i64, i64 [[DOTOMP_COMB_LB]], align 8			// CHECK10-NEXT: [[TMP21:%.]] = load i64, i64 [[DOTOMP_COMB_LB]], align 8, !llvm.access.group !5
	// CHECK10-NEXT: [[TMP22:%.]] = load i64, i64 [[DOTOMP_COMB_UB]], align 8			// CHECK10-NEXT: [[TMP22:%.]] = load i64, i64 [[DOTOMP_COMB_UB]], align 8, !llvm.access.group !5
	// CHECK10-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i32, i32, i64, i64, i32) @.omp_outlined..1 to void (i32, i32, ...)), i64 [[TMP21]], i64 [[TMP22]], i32 [[TMP0]], i32* [[TMP1]], i64 [[TMP2]], i64 [[TMP3]], i32* [[TMP4]])			// CHECK10-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i32, i32, i64, i64, i32) @.omp_outlined..1 to void (i32, i32, ...)), i64 [[TMP21]], i64 [[TMP22]], i32 [[TMP0]], i32* [[TMP1]], i64 [[TMP2]], i64 [[TMP3]], i32* [[TMP4]]), !llvm.access.group !5
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK10: omp.inner.for.inc:			// CHECK10: omp.inner.for.inc:
	// CHECK10-NEXT: [[TMP23:%.]] = load i64, i64 [[DOTOMP_IV]], align 8			// CHECK10-NEXT: [[TMP23:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !5
	// CHECK10-NEXT: [[TMP24:%.]] = load i64, i64 [[DOTOMP_STRIDE]], align 8			// CHECK10-NEXT: [[TMP24:%.]] = load i64, i64 [[DOTOMP_STRIDE]], align 8, !llvm.access.group !5
	// CHECK10-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP23]], [[TMP24]]			// CHECK10-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP23]], [[TMP24]]
	// CHECK10-NEXT: store i64 [[ADD]], i64* [[DOTOMP_IV]], align 8			// CHECK10-NEXT: store i64 [[ADD]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !5
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]
	// CHECK10: omp.inner.for.end:			// CHECK10: omp.inner.for.end:
	// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK10: omp.loop.exit:			// CHECK10: omp.loop.exit:
	// CHECK10-NEXT: [[TMP25:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK10-NEXT: [[TMP25:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK10-NEXT: [[TMP26:%.]] = load i32, i32 [[TMP25]], align 4			// CHECK10-NEXT: [[TMP26:%.]] = load i32, i32 [[TMP25]], align 4
	// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]])			// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]])
	// CHECK10-NEXT: [[TMP27:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK10-NEXT: [[TMP27:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK10-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0			// CHECK10-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0
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	// CHECK10-NEXT: br label [[COND_END]]			// CHECK10-NEXT: br label [[COND_END]]
	// CHECK10: cond.end:			// CHECK10: cond.end:
	// CHECK10-NEXT: [[COND:%.*]] = phi i64 [ [[TMP18]], [[COND_TRUE]] ], [ [[TMP19]], [[COND_FALSE]] ]			// CHECK10-NEXT: [[COND:%.*]] = phi i64 [ [[TMP18]], [[COND_TRUE]] ], [ [[TMP19]], [[COND_FALSE]] ]
	// CHECK10-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8			// CHECK10-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
	// CHECK10-NEXT: [[TMP20:%.]] = load i64, i64 [[DOTOMP_LB]], align 8			// CHECK10-NEXT: [[TMP20:%.]] = load i64, i64 [[DOTOMP_LB]], align 8
	// CHECK10-NEXT: store i64 [[TMP20]], i64* [[DOTOMP_IV]], align 8			// CHECK10-NEXT: store i64 [[TMP20]], i64* [[DOTOMP_IV]], align 8
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK10: omp.inner.for.cond:			// CHECK10: omp.inner.for.cond:
	// CHECK10-NEXT: [[TMP21:%.]] = load i64, i64 [[DOTOMP_IV]], align 8			// CHECK10-NEXT: [[TMP21:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !9
	// CHECK10-NEXT: [[TMP22:%.]] = load i64, i64 [[DOTOMP_UB]], align 8			// CHECK10-NEXT: [[TMP22:%.]] = load i64, i64 [[DOTOMP_UB]], align 8, !llvm.access.group !9
	// CHECK10-NEXT: [[CMP14:%.*]] = icmp sle i64 [[TMP21]], [[TMP22]]			// CHECK10-NEXT: [[CMP14:%.*]] = icmp sle i64 [[TMP21]], [[TMP22]]
	// CHECK10-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK10-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK10: omp.inner.for.body:			// CHECK10: omp.inner.for.body:
	// CHECK10-NEXT: [[TMP23:%.]] = load i64, i64 [[DOTOMP_IV]], align 8			// CHECK10-NEXT: [[TMP23:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !9
	// CHECK10-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_4]], align 4			// CHECK10-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_4]], align 4, !llvm.access.group !9
	// CHECK10-NEXT: [[SUB15:%.*]] = sub nsw i32 [[TMP24]], 0			// CHECK10-NEXT: [[SUB15:%.*]] = sub nsw i32 [[TMP24]], 0
	// CHECK10-NEXT: [[DIV16:%.*]] = sdiv i32 [[SUB15]], 1			// CHECK10-NEXT: [[DIV16:%.*]] = sdiv i32 [[SUB15]], 1
	// CHECK10-NEXT: [[MUL17:%.*]] = mul nsw i32 1, [[DIV16]]			// CHECK10-NEXT: [[MUL17:%.*]] = mul nsw i32 1, [[DIV16]]
	// CHECK10-NEXT: [[CONV18:%.*]] = sext i32 [[MUL17]] to i64			// CHECK10-NEXT: [[CONV18:%.*]] = sext i32 [[MUL17]] to i64
	// CHECK10-NEXT: [[DIV19:%.*]] = sdiv i64 [[TMP23]], [[CONV18]]			// CHECK10-NEXT: [[DIV19:%.*]] = sdiv i64 [[TMP23]], [[CONV18]]
	// CHECK10-NEXT: [[MUL20:%.*]] = mul nsw i64 [[DIV19]], 1			// CHECK10-NEXT: [[MUL20:%.*]] = mul nsw i64 [[DIV19]], 1
	// CHECK10-NEXT: [[ADD:%.*]] = add nsw i64 0, [[MUL20]]			// CHECK10-NEXT: [[ADD:%.*]] = add nsw i64 0, [[MUL20]]
	// CHECK10-NEXT: [[CONV21:%.*]] = trunc i64 [[ADD]] to i32			// CHECK10-NEXT: [[CONV21:%.*]] = trunc i64 [[ADD]] to i32
	// CHECK10-NEXT: store i32 [[CONV21]], i32* [[I11]], align 4			// CHECK10-NEXT: store i32 [[CONV21]], i32* [[I11]], align 4, !llvm.access.group !9
	// CHECK10-NEXT: [[TMP25:%.]] = load i64, i64 [[DOTOMP_IV]], align 8			// CHECK10-NEXT: [[TMP25:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !9
	// CHECK10-NEXT: [[TMP26:%.]] = load i64, i64 [[DOTOMP_IV]], align 8			// CHECK10-NEXT: [[TMP26:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !9
	// CHECK10-NEXT: [[TMP27:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_4]], align 4			// CHECK10-NEXT: [[TMP27:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_4]], align 4, !llvm.access.group !9
	// CHECK10-NEXT: [[SUB22:%.*]] = sub nsw i32 [[TMP27]], 0			// CHECK10-NEXT: [[SUB22:%.*]] = sub nsw i32 [[TMP27]], 0
	// CHECK10-NEXT: [[DIV23:%.*]] = sdiv i32 [[SUB22]], 1			// CHECK10-NEXT: [[DIV23:%.*]] = sdiv i32 [[SUB22]], 1
	// CHECK10-NEXT: [[MUL24:%.*]] = mul nsw i32 1, [[DIV23]]			// CHECK10-NEXT: [[MUL24:%.*]] = mul nsw i32 1, [[DIV23]]
	// CHECK10-NEXT: [[CONV25:%.*]] = sext i32 [[MUL24]] to i64			// CHECK10-NEXT: [[CONV25:%.*]] = sext i32 [[MUL24]] to i64
	// CHECK10-NEXT: [[DIV26:%.*]] = sdiv i64 [[TMP26]], [[CONV25]]			// CHECK10-NEXT: [[DIV26:%.*]] = sdiv i64 [[TMP26]], [[CONV25]]
	// CHECK10-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_4]], align 4			// CHECK10-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_4]], align 4, !llvm.access.group !9
	// CHECK10-NEXT: [[SUB27:%.*]] = sub nsw i32 [[TMP28]], 0			// CHECK10-NEXT: [[SUB27:%.*]] = sub nsw i32 [[TMP28]], 0
	// CHECK10-NEXT: [[DIV28:%.*]] = sdiv i32 [[SUB27]], 1			// CHECK10-NEXT: [[DIV28:%.*]] = sdiv i32 [[SUB27]], 1
	// CHECK10-NEXT: [[MUL29:%.*]] = mul nsw i32 1, [[DIV28]]			// CHECK10-NEXT: [[MUL29:%.*]] = mul nsw i32 1, [[DIV28]]
	// CHECK10-NEXT: [[CONV30:%.*]] = sext i32 [[MUL29]] to i64			// CHECK10-NEXT: [[CONV30:%.*]] = sext i32 [[MUL29]] to i64
	// CHECK10-NEXT: [[MUL31:%.*]] = mul nsw i64 [[DIV26]], [[CONV30]]			// CHECK10-NEXT: [[MUL31:%.*]] = mul nsw i64 [[DIV26]], [[CONV30]]
	// CHECK10-NEXT: [[SUB32:%.*]] = sub nsw i64 [[TMP25]], [[MUL31]]			// CHECK10-NEXT: [[SUB32:%.*]] = sub nsw i64 [[TMP25]], [[MUL31]]
	// CHECK10-NEXT: [[MUL33:%.*]] = mul nsw i64 [[SUB32]], 1			// CHECK10-NEXT: [[MUL33:%.*]] = mul nsw i64 [[SUB32]], 1
	// CHECK10-NEXT: [[ADD34:%.*]] = add nsw i64 0, [[MUL33]]			// CHECK10-NEXT: [[ADD34:%.*]] = add nsw i64 0, [[MUL33]]
	// CHECK10-NEXT: [[CONV35:%.*]] = trunc i64 [[ADD34]] to i32			// CHECK10-NEXT: [[CONV35:%.*]] = trunc i64 [[ADD34]] to i32
	// CHECK10-NEXT: store i32 [[CONV35]], i32* [[J12]], align 4			// CHECK10-NEXT: store i32 [[CONV35]], i32* [[J12]], align 4, !llvm.access.group !9
	// CHECK10-NEXT: [[TMP29:%.]] = load i32, i32 [[I11]], align 4			// CHECK10-NEXT: [[TMP29:%.]] = load i32, i32 [[I11]], align 4, !llvm.access.group !9
	// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP29]] to i64			// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP29]] to i64
	// CHECK10-NEXT: [[TMP30:%.*]] = mul nsw i64 [[IDXPROM]], [[TMP3]]			// CHECK10-NEXT: [[TMP30:%.*]] = mul nsw i64 [[IDXPROM]], [[TMP3]]
	// CHECK10-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP4]], i64 [[TMP30]]			// CHECK10-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP4]], i64 [[TMP30]]
	// CHECK10-NEXT: [[TMP31:%.]] = load i32, i32 [[J12]], align 4			// CHECK10-NEXT: [[TMP31:%.]] = load i32, i32 [[J12]], align 4, !llvm.access.group !9
	// CHECK10-NEXT: [[IDXPROM36:%.*]] = sext i32 [[TMP31]] to i64			// CHECK10-NEXT: [[IDXPROM36:%.*]] = sext i32 [[TMP31]] to i64
	// CHECK10-NEXT: [[ARRAYIDX37:%.]] = getelementptr inbounds i32, i32 [[ARRAYIDX]], i64 [[IDXPROM36]]			// CHECK10-NEXT: [[ARRAYIDX37:%.]] = getelementptr inbounds i32, i32 [[ARRAYIDX]], i64 [[IDXPROM36]]
	// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX37]], align 4			// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX37]], align 4, !llvm.access.group !9
	// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK10: omp.body.continue:			// CHECK10: omp.body.continue:
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK10: omp.inner.for.inc:			// CHECK10: omp.inner.for.inc:
	// CHECK10-NEXT: [[TMP32:%.]] = load i64, i64 [[DOTOMP_IV]], align 8			// CHECK10-NEXT: [[TMP32:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !9
	// CHECK10-NEXT: [[ADD38:%.*]] = add nsw i64 [[TMP32]], 1			// CHECK10-NEXT: [[ADD38:%.*]] = add nsw i64 [[TMP32]], 1
	// CHECK10-NEXT: store i64 [[ADD38]], i64* [[DOTOMP_IV]], align 8			// CHECK10-NEXT: store i64 [[ADD38]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !9
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]
	// CHECK10: omp.inner.for.end:			// CHECK10: omp.inner.for.end:
	// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK10: omp.loop.exit:			// CHECK10: omp.loop.exit:
	// CHECK10-NEXT: [[TMP33:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK10-NEXT: [[TMP33:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK10-NEXT: [[TMP34:%.]] = load i32, i32 [[TMP33]], align 4			// CHECK10-NEXT: [[TMP34:%.]] = load i32, i32 [[TMP33]], align 4
	// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP34]])			// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP34]])
	// CHECK10-NEXT: [[TMP35:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK10-NEXT: [[TMP35:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK10-NEXT: [[TMP36:%.*]] = icmp ne i32 [[TMP35]], 0			// CHECK10-NEXT: [[TMP36:%.*]] = icmp ne i32 [[TMP35]], 0
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	// CHECK10-NEXT: br label [[COND_END]]			// CHECK10-NEXT: br label [[COND_END]]
	// CHECK10: cond.end:			// CHECK10: cond.end:
	// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 19, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]			// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 19, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
	// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK10-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK10-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK10-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK10-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK10: omp.inner.for.cond:			// CHECK10: omp.inner.for.cond:
	// CHECK10-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK10-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK10-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !14
	// CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK10: omp.inner.for.body:			// CHECK10: omp.inner.for.body:
	// CHECK10-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK10-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !14
	// CHECK10-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64			// CHECK10-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
	// CHECK10-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK10-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !14
	// CHECK10-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64			// CHECK10-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
	// CHECK10-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, [10 x [2 x i32]]) @.omp_outlined..3 to void (i32, i32, ...)), i64 [[TMP9]], i64 [[TMP11]], [10 x [2 x i32]] [[TMP0]])			// CHECK10-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, [10 x [2 x i32]]) @.omp_outlined..3 to void (i32, i32, ...)), i64 [[TMP9]], i64 [[TMP11]], [10 x [2 x i32]] [[TMP0]]), !llvm.access.group !14
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK10: omp.inner.for.inc:			// CHECK10: omp.inner.for.inc:
	// CHECK10-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK10-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK10-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !14
	// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]			// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]
	// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]]
	// CHECK10: omp.inner.for.end:			// CHECK10: omp.inner.for.end:
	// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK10: omp.loop.exit:			// CHECK10: omp.loop.exit:
	// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])			// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
	// CHECK10-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK10-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK10-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0			// CHECK10-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0
	// CHECK10-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK10-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK10: .omp.final.then:			// CHECK10: .omp.final.then:
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	// CHECK10-NEXT: br label [[COND_END]]			// CHECK10-NEXT: br label [[COND_END]]
	// CHECK10: cond.end:			// CHECK10: cond.end:
	// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 19, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ]			// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 19, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ]
	// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK10-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK10-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK10-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4			// CHECK10-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK10: omp.inner.for.cond:			// CHECK10: omp.inner.for.cond:
	// CHECK10-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !17
	// CHECK10-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK10-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !17
	// CHECK10-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]			// CHECK10-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
	// CHECK10-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK10-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK10: omp.inner.for.body:			// CHECK10: omp.inner.for.body:
	// CHECK10-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !17
	// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 2			// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 2
	// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1			// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1
	// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !17
	// CHECK10-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !17
	// CHECK10-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !17
	// CHECK10-NEXT: [[DIV4:%.*]] = sdiv i32 [[TMP12]], 2			// CHECK10-NEXT: [[DIV4:%.*]] = sdiv i32 [[TMP12]], 2
	// CHECK10-NEXT: [[MUL5:%.*]] = mul nsw i32 [[DIV4]], 2			// CHECK10-NEXT: [[MUL5:%.*]] = mul nsw i32 [[DIV4]], 2
	// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP11]], [[MUL5]]			// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP11]], [[MUL5]]
	// CHECK10-NEXT: [[MUL6:%.*]] = mul nsw i32 [[SUB]], 1			// CHECK10-NEXT: [[MUL6:%.*]] = mul nsw i32 [[SUB]], 1
	// CHECK10-NEXT: [[ADD7:%.*]] = add nsw i32 0, [[MUL6]]			// CHECK10-NEXT: [[ADD7:%.*]] = add nsw i32 0, [[MUL6]]
	// CHECK10-NEXT: store i32 [[ADD7]], i32* [[J]], align 4			// CHECK10-NEXT: store i32 [[ADD7]], i32* [[J]], align 4, !llvm.access.group !17
	// CHECK10-NEXT: [[TMP13:%.]] = load i32, i32 [[I]], align 4			// CHECK10-NEXT: [[TMP13:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !17
	// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64			// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64
	// CHECK10-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]] [[TMP0]], i64 0, i64 [[IDXPROM]]			// CHECK10-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]] [[TMP0]], i64 0, i64 [[IDXPROM]]
	// CHECK10-NEXT: [[TMP14:%.]] = load i32, i32 [[J]], align 4			// CHECK10-NEXT: [[TMP14:%.]] = load i32, i32 [[J]], align 4, !llvm.access.group !17
	// CHECK10-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP14]] to i64			// CHECK10-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP14]] to i64
	// CHECK10-NEXT: [[ARRAYIDX9:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[ARRAYIDX]], i64 0, i64 [[IDXPROM8]]			// CHECK10-NEXT: [[ARRAYIDX9:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[ARRAYIDX]], i64 0, i64 [[IDXPROM8]]
	// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX9]], align 4			// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX9]], align 4, !llvm.access.group !17
	// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK10: omp.body.continue:			// CHECK10: omp.body.continue:
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK10: omp.inner.for.inc:			// CHECK10: omp.inner.for.inc:
	// CHECK10-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !17
	// CHECK10-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP15]], 1			// CHECK10-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP15]], 1
	// CHECK10-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4			// CHECK10-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]]
	// CHECK10: omp.inner.for.end:			// CHECK10: omp.inner.for.end:
	// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK10: omp.loop.exit:			// CHECK10: omp.loop.exit:
	// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]])			// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]])
	// CHECK10-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK10-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK10-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0			// CHECK10-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0
	// CHECK10-NEXT: br i1 [[TMP17]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK10-NEXT: br i1 [[TMP17]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK10: .omp.final.then:			// CHECK10: .omp.final.then:
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	// CHECK11-NEXT: br label [[COND_END]]			// CHECK11-NEXT: br label [[COND_END]]
	// CHECK11: cond.end:			// CHECK11: cond.end:
	// CHECK11-NEXT: [[COND:%.*]] = phi i64 [ [[TMP16]], [[COND_TRUE]] ], [ [[TMP17]], [[COND_FALSE]] ]			// CHECK11-NEXT: [[COND:%.*]] = phi i64 [ [[TMP16]], [[COND_TRUE]] ], [ [[TMP17]], [[COND_FALSE]] ]
	// CHECK11-NEXT: store i64 [[COND]], i64* [[DOTOMP_COMB_UB]], align 8			// CHECK11-NEXT: store i64 [[COND]], i64* [[DOTOMP_COMB_UB]], align 8
	// CHECK11-NEXT: [[TMP18:%.]] = load i64, i64 [[DOTOMP_COMB_LB]], align 8			// CHECK11-NEXT: [[TMP18:%.]] = load i64, i64 [[DOTOMP_COMB_LB]], align 8
	// CHECK11-NEXT: store i64 [[TMP18]], i64* [[DOTOMP_IV]], align 8			// CHECK11-NEXT: store i64 [[TMP18]], i64* [[DOTOMP_IV]], align 8
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK11: omp.inner.for.cond:			// CHECK11: omp.inner.for.cond:
	// CHECK11-NEXT: [[TMP19:%.]] = load i64, i64 [[DOTOMP_IV]], align 8			// CHECK11-NEXT: [[TMP19:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !6
	// CHECK11-NEXT: [[TMP20:%.]] = load i64, i64 [[DOTOMP_COMB_UB]], align 8			// CHECK11-NEXT: [[TMP20:%.]] = load i64, i64 [[DOTOMP_COMB_UB]], align 8, !llvm.access.group !6
	// CHECK11-NEXT: [[CMP14:%.*]] = icmp sle i64 [[TMP19]], [[TMP20]]			// CHECK11-NEXT: [[CMP14:%.*]] = icmp sle i64 [[TMP19]], [[TMP20]]
	// CHECK11-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK11-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK11: omp.inner.for.body:			// CHECK11: omp.inner.for.body:
	// CHECK11-NEXT: [[TMP21:%.]] = load i64, i64 [[DOTOMP_COMB_LB]], align 8			// CHECK11-NEXT: [[TMP21:%.]] = load i64, i64 [[DOTOMP_COMB_LB]], align 8, !llvm.access.group !6
	// CHECK11-NEXT: [[TMP22:%.*]] = trunc i64 [[TMP21]] to i32			// CHECK11-NEXT: [[TMP22:%.*]] = trunc i64 [[TMP21]] to i32
	// CHECK11-NEXT: [[TMP23:%.]] = load i64, i64 [[DOTOMP_COMB_UB]], align 8			// CHECK11-NEXT: [[TMP23:%.]] = load i64, i64 [[DOTOMP_COMB_UB]], align 8, !llvm.access.group !6
	// CHECK11-NEXT: [[TMP24:%.*]] = trunc i64 [[TMP23]] to i32			// CHECK11-NEXT: [[TMP24:%.*]] = trunc i64 [[TMP23]] to i32
	// CHECK11-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32, i32, ...)* bitcast (void (i32, i32, i32, i32, i32, i32, i32, i32, i32) @.omp_outlined..1 to void (i32, i32, ...)), i32 [[TMP22]], i32 [[TMP24]], i32 [[TMP0]], i32* [[TMP1]], i32 [[TMP2]], i32 [[TMP3]], i32* [[TMP4]])			// CHECK11-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32, i32, ...)* bitcast (void (i32, i32, i32, i32, i32, i32, i32, i32, i32) @.omp_outlined..1 to void (i32, i32, ...)), i32 [[TMP22]], i32 [[TMP24]], i32 [[TMP0]], i32* [[TMP1]], i32 [[TMP2]], i32 [[TMP3]], i32* [[TMP4]]), !llvm.access.group !6
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK11: omp.inner.for.inc:			// CHECK11: omp.inner.for.inc:
	// CHECK11-NEXT: [[TMP25:%.]] = load i64, i64 [[DOTOMP_IV]], align 8			// CHECK11-NEXT: [[TMP25:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !6
	// CHECK11-NEXT: [[TMP26:%.]] = load i64, i64 [[DOTOMP_STRIDE]], align 8			// CHECK11-NEXT: [[TMP26:%.]] = load i64, i64 [[DOTOMP_STRIDE]], align 8, !llvm.access.group !6
	// CHECK11-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP25]], [[TMP26]]			// CHECK11-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP25]], [[TMP26]]
	// CHECK11-NEXT: store i64 [[ADD]], i64* [[DOTOMP_IV]], align 8			// CHECK11-NEXT: store i64 [[ADD]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !6
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]
	// CHECK11: omp.inner.for.end:			// CHECK11: omp.inner.for.end:
	// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK11: omp.loop.exit:			// CHECK11: omp.loop.exit:
	// CHECK11-NEXT: [[TMP27:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4			// CHECK11-NEXT: [[TMP27:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4
	// CHECK11-NEXT: [[TMP28:%.]] = load i32, i32 [[TMP27]], align 4			// CHECK11-NEXT: [[TMP28:%.]] = load i32, i32 [[TMP27]], align 4
	// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP28]])			// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP28]])
	// CHECK11-NEXT: [[TMP29:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK11-NEXT: [[TMP29:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK11-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0			// CHECK11-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0
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	// CHECK11-NEXT: br label [[COND_END]]			// CHECK11-NEXT: br label [[COND_END]]
	// CHECK11: cond.end:			// CHECK11: cond.end:
	// CHECK11-NEXT: [[COND:%.*]] = phi i64 [ [[TMP18]], [[COND_TRUE]] ], [ [[TMP19]], [[COND_FALSE]] ]			// CHECK11-NEXT: [[COND:%.*]] = phi i64 [ [[TMP18]], [[COND_TRUE]] ], [ [[TMP19]], [[COND_FALSE]] ]
	// CHECK11-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8			// CHECK11-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
	// CHECK11-NEXT: [[TMP20:%.]] = load i64, i64 [[DOTOMP_LB]], align 8			// CHECK11-NEXT: [[TMP20:%.]] = load i64, i64 [[DOTOMP_LB]], align 8
	// CHECK11-NEXT: store i64 [[TMP20]], i64* [[DOTOMP_IV]], align 8			// CHECK11-NEXT: store i64 [[TMP20]], i64* [[DOTOMP_IV]], align 8
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK11: omp.inner.for.cond:			// CHECK11: omp.inner.for.cond:
	// CHECK11-NEXT: [[TMP21:%.]] = load i64, i64 [[DOTOMP_IV]], align 8			// CHECK11-NEXT: [[TMP21:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !10
	// CHECK11-NEXT: [[TMP22:%.]] = load i64, i64 [[DOTOMP_UB]], align 8			// CHECK11-NEXT: [[TMP22:%.]] = load i64, i64 [[DOTOMP_UB]], align 8, !llvm.access.group !10
	// CHECK11-NEXT: [[CMP16:%.*]] = icmp sle i64 [[TMP21]], [[TMP22]]			// CHECK11-NEXT: [[CMP16:%.*]] = icmp sle i64 [[TMP21]], [[TMP22]]
	// CHECK11-NEXT: br i1 [[CMP16]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK11-NEXT: br i1 [[CMP16]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK11: omp.inner.for.body:			// CHECK11: omp.inner.for.body:
	// CHECK11-NEXT: [[TMP23:%.]] = load i64, i64 [[DOTOMP_IV]], align 8			// CHECK11-NEXT: [[TMP23:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !10
	// CHECK11-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_4]], align 4			// CHECK11-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_4]], align 4, !llvm.access.group !10
	// CHECK11-NEXT: [[SUB17:%.*]] = sub nsw i32 [[TMP24]], 0			// CHECK11-NEXT: [[SUB17:%.*]] = sub nsw i32 [[TMP24]], 0
	// CHECK11-NEXT: [[DIV18:%.*]] = sdiv i32 [[SUB17]], 1			// CHECK11-NEXT: [[DIV18:%.*]] = sdiv i32 [[SUB17]], 1
	// CHECK11-NEXT: [[MUL19:%.*]] = mul nsw i32 1, [[DIV18]]			// CHECK11-NEXT: [[MUL19:%.*]] = mul nsw i32 1, [[DIV18]]
	// CHECK11-NEXT: [[CONV20:%.*]] = sext i32 [[MUL19]] to i64			// CHECK11-NEXT: [[CONV20:%.*]] = sext i32 [[MUL19]] to i64
	// CHECK11-NEXT: [[DIV21:%.*]] = sdiv i64 [[TMP23]], [[CONV20]]			// CHECK11-NEXT: [[DIV21:%.*]] = sdiv i64 [[TMP23]], [[CONV20]]
	// CHECK11-NEXT: [[MUL22:%.*]] = mul nsw i64 [[DIV21]], 1			// CHECK11-NEXT: [[MUL22:%.*]] = mul nsw i64 [[DIV21]], 1
	// CHECK11-NEXT: [[ADD:%.*]] = add nsw i64 0, [[MUL22]]			// CHECK11-NEXT: [[ADD:%.*]] = add nsw i64 0, [[MUL22]]
	// CHECK11-NEXT: [[CONV23:%.*]] = trunc i64 [[ADD]] to i32			// CHECK11-NEXT: [[CONV23:%.*]] = trunc i64 [[ADD]] to i32
	// CHECK11-NEXT: store i32 [[CONV23]], i32* [[I13]], align 4			// CHECK11-NEXT: store i32 [[CONV23]], i32* [[I13]], align 4, !llvm.access.group !10
	// CHECK11-NEXT: [[TMP25:%.]] = load i64, i64 [[DOTOMP_IV]], align 8			// CHECK11-NEXT: [[TMP25:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !10
	// CHECK11-NEXT: [[TMP26:%.]] = load i64, i64 [[DOTOMP_IV]], align 8			// CHECK11-NEXT: [[TMP26:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !10
	// CHECK11-NEXT: [[TMP27:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_4]], align 4			// CHECK11-NEXT: [[TMP27:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_4]], align 4, !llvm.access.group !10
	// CHECK11-NEXT: [[SUB24:%.*]] = sub nsw i32 [[TMP27]], 0			// CHECK11-NEXT: [[SUB24:%.*]] = sub nsw i32 [[TMP27]], 0
	// CHECK11-NEXT: [[DIV25:%.*]] = sdiv i32 [[SUB24]], 1			// CHECK11-NEXT: [[DIV25:%.*]] = sdiv i32 [[SUB24]], 1
	// CHECK11-NEXT: [[MUL26:%.*]] = mul nsw i32 1, [[DIV25]]			// CHECK11-NEXT: [[MUL26:%.*]] = mul nsw i32 1, [[DIV25]]
	// CHECK11-NEXT: [[CONV27:%.*]] = sext i32 [[MUL26]] to i64			// CHECK11-NEXT: [[CONV27:%.*]] = sext i32 [[MUL26]] to i64
	// CHECK11-NEXT: [[DIV28:%.*]] = sdiv i64 [[TMP26]], [[CONV27]]			// CHECK11-NEXT: [[DIV28:%.*]] = sdiv i64 [[TMP26]], [[CONV27]]
	// CHECK11-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_4]], align 4			// CHECK11-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_4]], align 4, !llvm.access.group !10
	// CHECK11-NEXT: [[SUB29:%.*]] = sub nsw i32 [[TMP28]], 0			// CHECK11-NEXT: [[SUB29:%.*]] = sub nsw i32 [[TMP28]], 0
	// CHECK11-NEXT: [[DIV30:%.*]] = sdiv i32 [[SUB29]], 1			// CHECK11-NEXT: [[DIV30:%.*]] = sdiv i32 [[SUB29]], 1
	// CHECK11-NEXT: [[MUL31:%.*]] = mul nsw i32 1, [[DIV30]]			// CHECK11-NEXT: [[MUL31:%.*]] = mul nsw i32 1, [[DIV30]]
	// CHECK11-NEXT: [[CONV32:%.*]] = sext i32 [[MUL31]] to i64			// CHECK11-NEXT: [[CONV32:%.*]] = sext i32 [[MUL31]] to i64
	// CHECK11-NEXT: [[MUL33:%.*]] = mul nsw i64 [[DIV28]], [[CONV32]]			// CHECK11-NEXT: [[MUL33:%.*]] = mul nsw i64 [[DIV28]], [[CONV32]]
	// CHECK11-NEXT: [[SUB34:%.*]] = sub nsw i64 [[TMP25]], [[MUL33]]			// CHECK11-NEXT: [[SUB34:%.*]] = sub nsw i64 [[TMP25]], [[MUL33]]
	// CHECK11-NEXT: [[MUL35:%.*]] = mul nsw i64 [[SUB34]], 1			// CHECK11-NEXT: [[MUL35:%.*]] = mul nsw i64 [[SUB34]], 1
	// CHECK11-NEXT: [[ADD36:%.*]] = add nsw i64 0, [[MUL35]]			// CHECK11-NEXT: [[ADD36:%.*]] = add nsw i64 0, [[MUL35]]
	// CHECK11-NEXT: [[CONV37:%.*]] = trunc i64 [[ADD36]] to i32			// CHECK11-NEXT: [[CONV37:%.*]] = trunc i64 [[ADD36]] to i32
	// CHECK11-NEXT: store i32 [[CONV37]], i32* [[J14]], align 4			// CHECK11-NEXT: store i32 [[CONV37]], i32* [[J14]], align 4, !llvm.access.group !10
	// CHECK11-NEXT: [[TMP29:%.]] = load i32, i32 [[I13]], align 4			// CHECK11-NEXT: [[TMP29:%.]] = load i32, i32 [[I13]], align 4, !llvm.access.group !10
	// CHECK11-NEXT: [[TMP30:%.*]] = mul nsw i32 [[TMP29]], [[TMP3]]			// CHECK11-NEXT: [[TMP30:%.*]] = mul nsw i32 [[TMP29]], [[TMP3]]
	// CHECK11-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP4]], i32 [[TMP30]]			// CHECK11-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP4]], i32 [[TMP30]]
	// CHECK11-NEXT: [[TMP31:%.]] = load i32, i32 [[J14]], align 4			// CHECK11-NEXT: [[TMP31:%.]] = load i32, i32 [[J14]], align 4, !llvm.access.group !10
	// CHECK11-NEXT: [[ARRAYIDX38:%.]] = getelementptr inbounds i32, i32 [[ARRAYIDX]], i32 [[TMP31]]			// CHECK11-NEXT: [[ARRAYIDX38:%.]] = getelementptr inbounds i32, i32 [[ARRAYIDX]], i32 [[TMP31]]
	// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX38]], align 4			// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX38]], align 4, !llvm.access.group !10
	// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK11: omp.body.continue:			// CHECK11: omp.body.continue:
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK11: omp.inner.for.inc:			// CHECK11: omp.inner.for.inc:
	// CHECK11-NEXT: [[TMP32:%.]] = load i64, i64 [[DOTOMP_IV]], align 8			// CHECK11-NEXT: [[TMP32:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !10
	// CHECK11-NEXT: [[ADD39:%.*]] = add nsw i64 [[TMP32]], 1			// CHECK11-NEXT: [[ADD39:%.*]] = add nsw i64 [[TMP32]], 1
	// CHECK11-NEXT: store i64 [[ADD39]], i64* [[DOTOMP_IV]], align 8			// CHECK11-NEXT: store i64 [[ADD39]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !10
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]
	// CHECK11: omp.inner.for.end:			// CHECK11: omp.inner.for.end:
	// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK11: omp.loop.exit:			// CHECK11: omp.loop.exit:
	// CHECK11-NEXT: [[TMP33:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4			// CHECK11-NEXT: [[TMP33:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4
	// CHECK11-NEXT: [[TMP34:%.]] = load i32, i32 [[TMP33]], align 4			// CHECK11-NEXT: [[TMP34:%.]] = load i32, i32 [[TMP33]], align 4
	// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP34]])			// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP34]])
	// CHECK11-NEXT: [[TMP35:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK11-NEXT: [[TMP35:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK11-NEXT: [[TMP36:%.*]] = icmp ne i32 [[TMP35]], 0			// CHECK11-NEXT: [[TMP36:%.*]] = icmp ne i32 [[TMP35]], 0
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	// CHECK11-NEXT: br label [[COND_END]]			// CHECK11-NEXT: br label [[COND_END]]
	// CHECK11: cond.end:			// CHECK11: cond.end:
	// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 19, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]			// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 19, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
	// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK11-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK11-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK11-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK11-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK11: omp.inner.for.cond:			// CHECK11: omp.inner.for.cond:
	// CHECK11-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK11-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK11-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK11-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15
	// CHECK11-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK11-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK11-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK11-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK11: omp.inner.for.body:			// CHECK11: omp.inner.for.body:
	// CHECK11-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK11-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !15
	// CHECK11-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK11-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15
	// CHECK11-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i32, i32, [10 x [2 x i32]]) @.omp_outlined..3 to void (i32, i32, ...)), i32 [[TMP8]], i32 [[TMP9]], [10 x [2 x i32]] [[TMP0]])			// CHECK11-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i32, i32, [10 x [2 x i32]]) @.omp_outlined..3 to void (i32, i32, ...)), i32 [[TMP8]], i32 [[TMP9]], [10 x [2 x i32]] [[TMP0]]), !llvm.access.group !15
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK11: omp.inner.for.inc:			// CHECK11: omp.inner.for.inc:
	// CHECK11-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK11-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK11-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK11-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !15
	// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP10]], [[TMP11]]			// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP10]], [[TMP11]]
	// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]]
	// CHECK11: omp.inner.for.end:			// CHECK11: omp.inner.for.end:
	// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK11: omp.loop.exit:			// CHECK11: omp.loop.exit:
	// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])			// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
	// CHECK11-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK11-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK11-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0			// CHECK11-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0
	// CHECK11-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK11-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK11: .omp.final.then:			// CHECK11: .omp.final.then:
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	// CHECK11-NEXT: br label [[COND_END]]			// CHECK11-NEXT: br label [[COND_END]]
	// CHECK11: cond.end:			// CHECK11: cond.end:
	// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 19, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ]			// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 19, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ]
	// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK11-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK11-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK11-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4			// CHECK11-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK11: omp.inner.for.cond:			// CHECK11: omp.inner.for.cond:
	// CHECK11-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK11-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK11-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK11-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !18
	// CHECK11-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]			// CHECK11-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
	// CHECK11-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK11-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK11: omp.inner.for.body:			// CHECK11: omp.inner.for.body:
	// CHECK11-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK11-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 2			// CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 2
	// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1			// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1
	// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !18
	// CHECK11-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK11-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK11-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK11-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK11-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP12]], 2			// CHECK11-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP12]], 2
	// CHECK11-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 2			// CHECK11-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 2
	// CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP11]], [[MUL4]]			// CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP11]], [[MUL4]]
	// CHECK11-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1			// CHECK11-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1
	// CHECK11-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]]			// CHECK11-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]]
	// CHECK11-NEXT: store i32 [[ADD6]], i32* [[J]], align 4			// CHECK11-NEXT: store i32 [[ADD6]], i32* [[J]], align 4, !llvm.access.group !18
	// CHECK11-NEXT: [[TMP13:%.]] = load i32, i32 [[I]], align 4			// CHECK11-NEXT: [[TMP13:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !18
	// CHECK11-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]] [[TMP0]], i32 0, i32 [[TMP13]]			// CHECK11-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]] [[TMP0]], i32 0, i32 [[TMP13]]
	// CHECK11-NEXT: [[TMP14:%.]] = load i32, i32 [[J]], align 4			// CHECK11-NEXT: [[TMP14:%.]] = load i32, i32 [[J]], align 4, !llvm.access.group !18
	// CHECK11-NEXT: [[ARRAYIDX7:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[ARRAYIDX]], i32 0, i32 [[TMP14]]			// CHECK11-NEXT: [[ARRAYIDX7:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[ARRAYIDX]], i32 0, i32 [[TMP14]]
	// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX7]], align 4			// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX7]], align 4, !llvm.access.group !18
	// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK11: omp.body.continue:			// CHECK11: omp.body.continue:
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK11: omp.inner.for.inc:			// CHECK11: omp.inner.for.inc:
	// CHECK11-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK11-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK11-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP15]], 1			// CHECK11-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP15]], 1
	// CHECK11-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4			// CHECK11-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]
	// CHECK11: omp.inner.for.end:			// CHECK11: omp.inner.for.end:
	// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK11: omp.loop.exit:			// CHECK11: omp.loop.exit:
	// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]])			// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]])
	// CHECK11-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK11-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK11-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0			// CHECK11-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0
	// CHECK11-NEXT: br i1 [[TMP17]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK11-NEXT: br i1 [[TMP17]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK11: .omp.final.then:			// CHECK11: .omp.final.then:
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	// CHECK12-NEXT: br label [[COND_END]]			// CHECK12-NEXT: br label [[COND_END]]
	// CHECK12: cond.end:			// CHECK12: cond.end:
	// CHECK12-NEXT: [[COND:%.*]] = phi i64 [ [[TMP16]], [[COND_TRUE]] ], [ [[TMP17]], [[COND_FALSE]] ]			// CHECK12-NEXT: [[COND:%.*]] = phi i64 [ [[TMP16]], [[COND_TRUE]] ], [ [[TMP17]], [[COND_FALSE]] ]
	// CHECK12-NEXT: store i64 [[COND]], i64* [[DOTOMP_COMB_UB]], align 8			// CHECK12-NEXT: store i64 [[COND]], i64* [[DOTOMP_COMB_UB]], align 8
	// CHECK12-NEXT: [[TMP18:%.]] = load i64, i64 [[DOTOMP_COMB_LB]], align 8			// CHECK12-NEXT: [[TMP18:%.]] = load i64, i64 [[DOTOMP_COMB_LB]], align 8
	// CHECK12-NEXT: store i64 [[TMP18]], i64* [[DOTOMP_IV]], align 8			// CHECK12-NEXT: store i64 [[TMP18]], i64* [[DOTOMP_IV]], align 8
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK12: omp.inner.for.cond:			// CHECK12: omp.inner.for.cond:
	// CHECK12-NEXT: [[TMP19:%.]] = load i64, i64 [[DOTOMP_IV]], align 8			// CHECK12-NEXT: [[TMP19:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !6
	// CHECK12-NEXT: [[TMP20:%.]] = load i64, i64 [[DOTOMP_COMB_UB]], align 8			// CHECK12-NEXT: [[TMP20:%.]] = load i64, i64 [[DOTOMP_COMB_UB]], align 8, !llvm.access.group !6
	// CHECK12-NEXT: [[CMP14:%.*]] = icmp sle i64 [[TMP19]], [[TMP20]]			// CHECK12-NEXT: [[CMP14:%.*]] = icmp sle i64 [[TMP19]], [[TMP20]]
	// CHECK12-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK12-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK12: omp.inner.for.body:			// CHECK12: omp.inner.for.body:
	// CHECK12-NEXT: [[TMP21:%.]] = load i64, i64 [[DOTOMP_COMB_LB]], align 8			// CHECK12-NEXT: [[TMP21:%.]] = load i64, i64 [[DOTOMP_COMB_LB]], align 8, !llvm.access.group !6
	// CHECK12-NEXT: [[TMP22:%.*]] = trunc i64 [[TMP21]] to i32			// CHECK12-NEXT: [[TMP22:%.*]] = trunc i64 [[TMP21]] to i32
	// CHECK12-NEXT: [[TMP23:%.]] = load i64, i64 [[DOTOMP_COMB_UB]], align 8			// CHECK12-NEXT: [[TMP23:%.]] = load i64, i64 [[DOTOMP_COMB_UB]], align 8, !llvm.access.group !6
	// CHECK12-NEXT: [[TMP24:%.*]] = trunc i64 [[TMP23]] to i32			// CHECK12-NEXT: [[TMP24:%.*]] = trunc i64 [[TMP23]] to i32
	// CHECK12-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32, i32, ...)* bitcast (void (i32, i32, i32, i32, i32, i32, i32, i32, i32) @.omp_outlined..1 to void (i32, i32, ...)), i32 [[TMP22]], i32 [[TMP24]], i32 [[TMP0]], i32* [[TMP1]], i32 [[TMP2]], i32 [[TMP3]], i32* [[TMP4]])			// CHECK12-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32, i32, ...)* bitcast (void (i32, i32, i32, i32, i32, i32, i32, i32, i32) @.omp_outlined..1 to void (i32, i32, ...)), i32 [[TMP22]], i32 [[TMP24]], i32 [[TMP0]], i32* [[TMP1]], i32 [[TMP2]], i32 [[TMP3]], i32* [[TMP4]]), !llvm.access.group !6
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK12: omp.inner.for.inc:			// CHECK12: omp.inner.for.inc:
	// CHECK12-NEXT: [[TMP25:%.]] = load i64, i64 [[DOTOMP_IV]], align 8			// CHECK12-NEXT: [[TMP25:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !6
	// CHECK12-NEXT: [[TMP26:%.]] = load i64, i64 [[DOTOMP_STRIDE]], align 8			// CHECK12-NEXT: [[TMP26:%.]] = load i64, i64 [[DOTOMP_STRIDE]], align 8, !llvm.access.group !6
	// CHECK12-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP25]], [[TMP26]]			// CHECK12-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP25]], [[TMP26]]
	// CHECK12-NEXT: store i64 [[ADD]], i64* [[DOTOMP_IV]], align 8			// CHECK12-NEXT: store i64 [[ADD]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !6
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]
	// CHECK12: omp.inner.for.end:			// CHECK12: omp.inner.for.end:
	// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK12: omp.loop.exit:			// CHECK12: omp.loop.exit:
	// CHECK12-NEXT: [[TMP27:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4			// CHECK12-NEXT: [[TMP27:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4
	// CHECK12-NEXT: [[TMP28:%.]] = load i32, i32 [[TMP27]], align 4			// CHECK12-NEXT: [[TMP28:%.]] = load i32, i32 [[TMP27]], align 4
	// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP28]])			// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP28]])
	// CHECK12-NEXT: [[TMP29:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK12-NEXT: [[TMP29:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK12-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0			// CHECK12-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0
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	// CHECK12-NEXT: br label [[COND_END]]			// CHECK12-NEXT: br label [[COND_END]]
	// CHECK12: cond.end:			// CHECK12: cond.end:
	// CHECK12-NEXT: [[COND:%.*]] = phi i64 [ [[TMP18]], [[COND_TRUE]] ], [ [[TMP19]], [[COND_FALSE]] ]			// CHECK12-NEXT: [[COND:%.*]] = phi i64 [ [[TMP18]], [[COND_TRUE]] ], [ [[TMP19]], [[COND_FALSE]] ]
	// CHECK12-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8			// CHECK12-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
	// CHECK12-NEXT: [[TMP20:%.]] = load i64, i64 [[DOTOMP_LB]], align 8			// CHECK12-NEXT: [[TMP20:%.]] = load i64, i64 [[DOTOMP_LB]], align 8
	// CHECK12-NEXT: store i64 [[TMP20]], i64* [[DOTOMP_IV]], align 8			// CHECK12-NEXT: store i64 [[TMP20]], i64* [[DOTOMP_IV]], align 8
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK12: omp.inner.for.cond:			// CHECK12: omp.inner.for.cond:
	// CHECK12-NEXT: [[TMP21:%.]] = load i64, i64 [[DOTOMP_IV]], align 8			// CHECK12-NEXT: [[TMP21:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !10
	// CHECK12-NEXT: [[TMP22:%.]] = load i64, i64 [[DOTOMP_UB]], align 8			// CHECK12-NEXT: [[TMP22:%.]] = load i64, i64 [[DOTOMP_UB]], align 8, !llvm.access.group !10
	// CHECK12-NEXT: [[CMP16:%.*]] = icmp sle i64 [[TMP21]], [[TMP22]]			// CHECK12-NEXT: [[CMP16:%.*]] = icmp sle i64 [[TMP21]], [[TMP22]]
	// CHECK12-NEXT: br i1 [[CMP16]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK12-NEXT: br i1 [[CMP16]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK12: omp.inner.for.body:			// CHECK12: omp.inner.for.body:
	// CHECK12-NEXT: [[TMP23:%.]] = load i64, i64 [[DOTOMP_IV]], align 8			// CHECK12-NEXT: [[TMP23:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !10
	// CHECK12-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_4]], align 4			// CHECK12-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_4]], align 4, !llvm.access.group !10
	// CHECK12-NEXT: [[SUB17:%.*]] = sub nsw i32 [[TMP24]], 0			// CHECK12-NEXT: [[SUB17:%.*]] = sub nsw i32 [[TMP24]], 0
	// CHECK12-NEXT: [[DIV18:%.*]] = sdiv i32 [[SUB17]], 1			// CHECK12-NEXT: [[DIV18:%.*]] = sdiv i32 [[SUB17]], 1
	// CHECK12-NEXT: [[MUL19:%.*]] = mul nsw i32 1, [[DIV18]]			// CHECK12-NEXT: [[MUL19:%.*]] = mul nsw i32 1, [[DIV18]]
	// CHECK12-NEXT: [[CONV20:%.*]] = sext i32 [[MUL19]] to i64			// CHECK12-NEXT: [[CONV20:%.*]] = sext i32 [[MUL19]] to i64
	// CHECK12-NEXT: [[DIV21:%.*]] = sdiv i64 [[TMP23]], [[CONV20]]			// CHECK12-NEXT: [[DIV21:%.*]] = sdiv i64 [[TMP23]], [[CONV20]]
	// CHECK12-NEXT: [[MUL22:%.*]] = mul nsw i64 [[DIV21]], 1			// CHECK12-NEXT: [[MUL22:%.*]] = mul nsw i64 [[DIV21]], 1
	// CHECK12-NEXT: [[ADD:%.*]] = add nsw i64 0, [[MUL22]]			// CHECK12-NEXT: [[ADD:%.*]] = add nsw i64 0, [[MUL22]]
	// CHECK12-NEXT: [[CONV23:%.*]] = trunc i64 [[ADD]] to i32			// CHECK12-NEXT: [[CONV23:%.*]] = trunc i64 [[ADD]] to i32
	// CHECK12-NEXT: store i32 [[CONV23]], i32* [[I13]], align 4			// CHECK12-NEXT: store i32 [[CONV23]], i32* [[I13]], align 4, !llvm.access.group !10
	// CHECK12-NEXT: [[TMP25:%.]] = load i64, i64 [[DOTOMP_IV]], align 8			// CHECK12-NEXT: [[TMP25:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !10
	// CHECK12-NEXT: [[TMP26:%.]] = load i64, i64 [[DOTOMP_IV]], align 8			// CHECK12-NEXT: [[TMP26:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !10
	// CHECK12-NEXT: [[TMP27:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_4]], align 4			// CHECK12-NEXT: [[TMP27:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_4]], align 4, !llvm.access.group !10
	// CHECK12-NEXT: [[SUB24:%.*]] = sub nsw i32 [[TMP27]], 0			// CHECK12-NEXT: [[SUB24:%.*]] = sub nsw i32 [[TMP27]], 0
	// CHECK12-NEXT: [[DIV25:%.*]] = sdiv i32 [[SUB24]], 1			// CHECK12-NEXT: [[DIV25:%.*]] = sdiv i32 [[SUB24]], 1
	// CHECK12-NEXT: [[MUL26:%.*]] = mul nsw i32 1, [[DIV25]]			// CHECK12-NEXT: [[MUL26:%.*]] = mul nsw i32 1, [[DIV25]]
	// CHECK12-NEXT: [[CONV27:%.*]] = sext i32 [[MUL26]] to i64			// CHECK12-NEXT: [[CONV27:%.*]] = sext i32 [[MUL26]] to i64
	// CHECK12-NEXT: [[DIV28:%.*]] = sdiv i64 [[TMP26]], [[CONV27]]			// CHECK12-NEXT: [[DIV28:%.*]] = sdiv i64 [[TMP26]], [[CONV27]]
	// CHECK12-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_4]], align 4			// CHECK12-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_4]], align 4, !llvm.access.group !10
	// CHECK12-NEXT: [[SUB29:%.*]] = sub nsw i32 [[TMP28]], 0			// CHECK12-NEXT: [[SUB29:%.*]] = sub nsw i32 [[TMP28]], 0
	// CHECK12-NEXT: [[DIV30:%.*]] = sdiv i32 [[SUB29]], 1			// CHECK12-NEXT: [[DIV30:%.*]] = sdiv i32 [[SUB29]], 1
	// CHECK12-NEXT: [[MUL31:%.*]] = mul nsw i32 1, [[DIV30]]			// CHECK12-NEXT: [[MUL31:%.*]] = mul nsw i32 1, [[DIV30]]
	// CHECK12-NEXT: [[CONV32:%.*]] = sext i32 [[MUL31]] to i64			// CHECK12-NEXT: [[CONV32:%.*]] = sext i32 [[MUL31]] to i64
	// CHECK12-NEXT: [[MUL33:%.*]] = mul nsw i64 [[DIV28]], [[CONV32]]			// CHECK12-NEXT: [[MUL33:%.*]] = mul nsw i64 [[DIV28]], [[CONV32]]
	// CHECK12-NEXT: [[SUB34:%.*]] = sub nsw i64 [[TMP25]], [[MUL33]]			// CHECK12-NEXT: [[SUB34:%.*]] = sub nsw i64 [[TMP25]], [[MUL33]]
	// CHECK12-NEXT: [[MUL35:%.*]] = mul nsw i64 [[SUB34]], 1			// CHECK12-NEXT: [[MUL35:%.*]] = mul nsw i64 [[SUB34]], 1
	// CHECK12-NEXT: [[ADD36:%.*]] = add nsw i64 0, [[MUL35]]			// CHECK12-NEXT: [[ADD36:%.*]] = add nsw i64 0, [[MUL35]]
	// CHECK12-NEXT: [[CONV37:%.*]] = trunc i64 [[ADD36]] to i32			// CHECK12-NEXT: [[CONV37:%.*]] = trunc i64 [[ADD36]] to i32
	// CHECK12-NEXT: store i32 [[CONV37]], i32* [[J14]], align 4			// CHECK12-NEXT: store i32 [[CONV37]], i32* [[J14]], align 4, !llvm.access.group !10
	// CHECK12-NEXT: [[TMP29:%.]] = load i32, i32 [[I13]], align 4			// CHECK12-NEXT: [[TMP29:%.]] = load i32, i32 [[I13]], align 4, !llvm.access.group !10
	// CHECK12-NEXT: [[TMP30:%.*]] = mul nsw i32 [[TMP29]], [[TMP3]]			// CHECK12-NEXT: [[TMP30:%.*]] = mul nsw i32 [[TMP29]], [[TMP3]]
	// CHECK12-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP4]], i32 [[TMP30]]			// CHECK12-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP4]], i32 [[TMP30]]
	// CHECK12-NEXT: [[TMP31:%.]] = load i32, i32 [[J14]], align 4			// CHECK12-NEXT: [[TMP31:%.]] = load i32, i32 [[J14]], align 4, !llvm.access.group !10
	// CHECK12-NEXT: [[ARRAYIDX38:%.]] = getelementptr inbounds i32, i32 [[ARRAYIDX]], i32 [[TMP31]]			// CHECK12-NEXT: [[ARRAYIDX38:%.]] = getelementptr inbounds i32, i32 [[ARRAYIDX]], i32 [[TMP31]]
	// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX38]], align 4			// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX38]], align 4, !llvm.access.group !10
	// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK12: omp.body.continue:			// CHECK12: omp.body.continue:
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK12: omp.inner.for.inc:			// CHECK12: omp.inner.for.inc:
	// CHECK12-NEXT: [[TMP32:%.]] = load i64, i64 [[DOTOMP_IV]], align 8			// CHECK12-NEXT: [[TMP32:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !10
	// CHECK12-NEXT: [[ADD39:%.*]] = add nsw i64 [[TMP32]], 1			// CHECK12-NEXT: [[ADD39:%.*]] = add nsw i64 [[TMP32]], 1
	// CHECK12-NEXT: store i64 [[ADD39]], i64* [[DOTOMP_IV]], align 8			// CHECK12-NEXT: store i64 [[ADD39]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !10
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]
	// CHECK12: omp.inner.for.end:			// CHECK12: omp.inner.for.end:
	// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK12: omp.loop.exit:			// CHECK12: omp.loop.exit:
	// CHECK12-NEXT: [[TMP33:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4			// CHECK12-NEXT: [[TMP33:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4
	// CHECK12-NEXT: [[TMP34:%.]] = load i32, i32 [[TMP33]], align 4			// CHECK12-NEXT: [[TMP34:%.]] = load i32, i32 [[TMP33]], align 4
	// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP34]])			// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP34]])
	// CHECK12-NEXT: [[TMP35:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK12-NEXT: [[TMP35:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK12-NEXT: [[TMP36:%.*]] = icmp ne i32 [[TMP35]], 0			// CHECK12-NEXT: [[TMP36:%.*]] = icmp ne i32 [[TMP35]], 0
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	// CHECK12-NEXT: br label [[COND_END]]			// CHECK12-NEXT: br label [[COND_END]]
	// CHECK12: cond.end:			// CHECK12: cond.end:
	// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 19, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]			// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 19, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
	// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK12-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK12-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK12-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK12-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK12: omp.inner.for.cond:			// CHECK12: omp.inner.for.cond:
	// CHECK12-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK12-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK12-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK12-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15
	// CHECK12-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK12-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK12-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK12-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK12: omp.inner.for.body:			// CHECK12: omp.inner.for.body:
	// CHECK12-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK12-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !15
	// CHECK12-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK12-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15
	// CHECK12-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i32, i32, [10 x [2 x i32]]) @.omp_outlined..3 to void (i32, i32, ...)), i32 [[TMP8]], i32 [[TMP9]], [10 x [2 x i32]] [[TMP0]])			// CHECK12-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i32, i32, [10 x [2 x i32]]) @.omp_outlined..3 to void (i32, i32, ...)), i32 [[TMP8]], i32 [[TMP9]], [10 x [2 x i32]] [[TMP0]]), !llvm.access.group !15
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK12: omp.inner.for.inc:			// CHECK12: omp.inner.for.inc:
	// CHECK12-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK12-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK12-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK12-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !15
	// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP10]], [[TMP11]]			// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP10]], [[TMP11]]
	// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]]
	// CHECK12: omp.inner.for.end:			// CHECK12: omp.inner.for.end:
	// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK12: omp.loop.exit:			// CHECK12: omp.loop.exit:
	// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])			// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
	// CHECK12-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK12-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK12-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0			// CHECK12-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0
	// CHECK12-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK12-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK12: .omp.final.then:			// CHECK12: .omp.final.then:
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	// CHECK12-NEXT: br label [[COND_END]]			// CHECK12-NEXT: br label [[COND_END]]
	// CHECK12: cond.end:			// CHECK12: cond.end:
	// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 19, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ]			// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 19, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ]
	// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK12-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK12-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK12-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4			// CHECK12-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK12: omp.inner.for.cond:			// CHECK12: omp.inner.for.cond:
	// CHECK12-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK12-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK12-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK12-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !18
	// CHECK12-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]			// CHECK12-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
	// CHECK12-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK12-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK12: omp.inner.for.body:			// CHECK12: omp.inner.for.body:
	// CHECK12-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK12-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 2			// CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 2
	// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1			// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1
	// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !18
	// CHECK12-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK12-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK12-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK12-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK12-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP12]], 2			// CHECK12-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP12]], 2
	// CHECK12-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 2			// CHECK12-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 2
	// CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP11]], [[MUL4]]			// CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP11]], [[MUL4]]
	// CHECK12-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1			// CHECK12-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1
	// CHECK12-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]]			// CHECK12-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]]
	// CHECK12-NEXT: store i32 [[ADD6]], i32* [[J]], align 4			// CHECK12-NEXT: store i32 [[ADD6]], i32* [[J]], align 4, !llvm.access.group !18
	// CHECK12-NEXT: [[TMP13:%.]] = load i32, i32 [[I]], align 4			// CHECK12-NEXT: [[TMP13:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !18
	// CHECK12-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]] [[TMP0]], i32 0, i32 [[TMP13]]			// CHECK12-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]] [[TMP0]], i32 0, i32 [[TMP13]]
	// CHECK12-NEXT: [[TMP14:%.]] = load i32, i32 [[J]], align 4			// CHECK12-NEXT: [[TMP14:%.]] = load i32, i32 [[J]], align 4, !llvm.access.group !18
	// CHECK12-NEXT: [[ARRAYIDX7:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[ARRAYIDX]], i32 0, i32 [[TMP14]]			// CHECK12-NEXT: [[ARRAYIDX7:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[ARRAYIDX]], i32 0, i32 [[TMP14]]
	// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX7]], align 4			// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX7]], align 4, !llvm.access.group !18
	// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK12: omp.body.continue:			// CHECK12: omp.body.continue:
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK12: omp.inner.for.inc:			// CHECK12: omp.inner.for.inc:
	// CHECK12-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK12-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK12-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP15]], 1			// CHECK12-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP15]], 1
	// CHECK12-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4			// CHECK12-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]
	// CHECK12: omp.inner.for.end:			// CHECK12: omp.inner.for.end:
	// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK12: omp.loop.exit:			// CHECK12: omp.loop.exit:
	// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]])			// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]])
	// CHECK12-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK12-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK12-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0			// CHECK12-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0
	// CHECK12-NEXT: br i1 [[TMP17]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK12-NEXT: br i1 [[TMP17]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK12: .omp.final.then:			// CHECK12: .omp.final.then:
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clang/test/OpenMP/teams_distribute_parallel_for_simd_dist_schedule_codegen.cpp

This file is larger than 256 KB, so syntax highlighting is disabled by default.

	Show First 20 Lines • Show All 3,774 Lines • ▼ Show 20 Lines
	// CHECK9-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8			// CHECK9-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8
	// CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8			// CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
	// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8			// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
	// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8			// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
	// CHECK9-NEXT: [[CONV:%.]] = bitcast i64 [[M_ADDR]] to i32*			// CHECK9-NEXT: [[CONV:%.]] = bitcast i64 [[M_ADDR]] to i32*
	// CHECK9-NEXT: [[CONV1:%.]] = bitcast i64 [[N_ADDR]] to i32*			// CHECK9-NEXT: [[CONV1:%.]] = bitcast i64 [[N_ADDR]] to i32*
	// CHECK9-NEXT: [[TMP0:%.]] = load i64, i64 [[VLA_ADDR]], align 8			// CHECK9-NEXT: [[TMP0:%.]] = load i64, i64 [[VLA_ADDR]], align 8
	// CHECK9-NEXT: [[TMP1:%.]] = load i32, i32** [[A_ADDR]], align 8			// CHECK9-NEXT: [[TMP1:%.]] = load i32, i32** [[A_ADDR]], align 8
	// CHECK9-NEXT: [[TMP2:%.]] = load i32, i32 [[CONV]], align 4			// CHECK9-NEXT: [[TMP2:%.]] = load i32, i32 [[CONV]], align 8
	// CHECK9-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4			// CHECK9-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
	// CHECK9-NEXT: [[TMP3:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4			// CHECK9-NEXT: [[TMP3:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4
	// CHECK9-NEXT: [[CONV2:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED]] to i32*			// CHECK9-NEXT: [[CONV2:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED]] to i32*
	// CHECK9-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4			// CHECK9-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
	// CHECK9-NEXT: [[TMP4:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED]], align 8			// CHECK9-NEXT: [[TMP4:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED]], align 8
	// CHECK9-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32, i32, ...)* bitcast (void (i32, i32, i32, i64, i32, i64)* @.omp_outlined..5 to void (i32, i32, ...)), i32 [[CONV1]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP4]])			// CHECK9-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32, i32, ...)* bitcast (void (i32, i32, i32, i64, i32, i64)* @.omp_outlined..5 to void (i32, i32, ...)), i32 [[CONV1]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP4]])
	// CHECK9-NEXT: ret void			// CHECK9-NEXT: ret void
	//			//
	Show All 40 Lines
	// CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]]			// CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]]
	// CHECK9-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.]], label [[OMP_PRECOND_END:%.]]			// CHECK9-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.]], label [[OMP_PRECOND_END:%.]]
	// CHECK9: omp.precond.then:			// CHECK9: omp.precond.then:
	// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4			// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
	// CHECK9-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2]], align 4			// CHECK9-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2]], align 4
	// CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4			// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
	// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4			// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
	// CHECK9-NEXT: [[TMP7:%.]] = load i32, i32 [[CONV]], align 4			// CHECK9-NEXT: [[TMP7:%.]] = load i32, i32 [[CONV]], align 8
	// CHECK9-NEXT: [[TMP8:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK9-NEXT: [[TMP8:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK9-NEXT: [[TMP9:%.]] = load i32, i32 [[TMP8]], align 4			// CHECK9-NEXT: [[TMP9:%.]] = load i32, i32 [[TMP8]], align 4
	// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP7]])			// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP7]])
	// CHECK9-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK9-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4
	// CHECK9-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2]], align 4			// CHECK9-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2]], align 4
	// CHECK9-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]]			// CHECK9-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]]
	// CHECK9-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.]], label [[COND_FALSE:%.]]			// CHECK9-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.]], label [[COND_FALSE:%.]]
	// CHECK9: cond.true:			// CHECK9: cond.true:
	Show All 14 Lines
	// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP16]], 1			// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP16]], 1
	// CHECK9-NEXT: [[CMP6:%.*]] = icmp slt i32 [[TMP15]], [[ADD]]			// CHECK9-NEXT: [[CMP6:%.*]] = icmp slt i32 [[TMP15]], [[ADD]]
	// CHECK9-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK9-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK9: omp.inner.for.body:			// CHECK9: omp.inner.for.body:
	// CHECK9-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !24			// CHECK9-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !24
	// CHECK9-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64			// CHECK9-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
	// CHECK9-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !24			// CHECK9-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !24
	// CHECK9-NEXT: [[TMP20:%.*]] = zext i32 [[TMP19]] to i64			// CHECK9-NEXT: [[TMP20:%.*]] = zext i32 [[TMP19]] to i64
	// CHECK9-NEXT: [[TMP21:%.]] = load i32, i32 [[CONV]], align 4, !llvm.access.group !24			// CHECK9-NEXT: [[TMP21:%.]] = load i32, i32 [[CONV]], align 8, !llvm.access.group !24
	// CHECK9-NEXT: [[CONV7:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED]] to i32*			// CHECK9-NEXT: [[CONV7:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED]] to i32*
	// CHECK9-NEXT: store i32 [[TMP21]], i32* [[CONV7]], align 4, !llvm.access.group !24			// CHECK9-NEXT: store i32 [[TMP21]], i32* [[CONV7]], align 4, !llvm.access.group !24
	// CHECK9-NEXT: [[TMP22:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !24			// CHECK9-NEXT: [[TMP22:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !24
	// CHECK9-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i32, i64, i32, i64)* @.omp_outlined..6 to void (i32, i32, ...)), i64 [[TMP18]], i64 [[TMP20]], i32 [[TMP0]], i64 [[TMP1]], i32* [[TMP2]], i64 [[TMP22]]), !llvm.access.group !24			// CHECK9-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i32, i64, i32, i64)* @.omp_outlined..6 to void (i32, i32, ...)), i64 [[TMP18]], i64 [[TMP20]], i32 [[TMP0]], i64 [[TMP1]], i32* [[TMP2]], i64 [[TMP22]]), !llvm.access.group !24
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK9: omp.inner.for.inc:			// CHECK9: omp.inner.for.inc:
	// CHECK9-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !24			// CHECK9-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !24
	// CHECK9-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !24			// CHECK9-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !24
	▲ Show 20 Lines • Show All 590 Lines • ▼ Show 20 Lines
	// CHECK9-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8			// CHECK9-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8
	// CHECK9-NEXT: [[A_ADDR:%.]] = alloca [10 x i32], align 8			// CHECK9-NEXT: [[A_ADDR:%.]] = alloca [10 x i32], align 8
	// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4			// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
	// CHECK9-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8			// CHECK9-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
	// CHECK9-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8			// CHECK9-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8
	// CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8			// CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8
	// CHECK9-NEXT: [[CONV:%.]] = bitcast i64 [[M_ADDR]] to i32*			// CHECK9-NEXT: [[CONV:%.]] = bitcast i64 [[M_ADDR]] to i32*
	// CHECK9-NEXT: [[TMP0:%.]] = load [10 x i32], [10 x i32]** [[A_ADDR]], align 8			// CHECK9-NEXT: [[TMP0:%.]] = load [10 x i32], [10 x i32]** [[A_ADDR]], align 8
	// CHECK9-NEXT: [[TMP1:%.]] = load i32, i32 [[CONV]], align 4			// CHECK9-NEXT: [[TMP1:%.]] = load i32, i32 [[CONV]], align 8
	// CHECK9-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4			// CHECK9-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
	// CHECK9-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4			// CHECK9-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4
	// CHECK9-NEXT: [[CONV1:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED]] to i32*			// CHECK9-NEXT: [[CONV1:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED]] to i32*
	// CHECK9-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4			// CHECK9-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4
	// CHECK9-NEXT: [[TMP3:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED]], align 8			// CHECK9-NEXT: [[TMP3:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED]], align 8
	// CHECK9-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, [10 x i32], i64) @.omp_outlined..15 to void (i32, i32, ...)), [10 x i32] [[TMP0]], i64 [[TMP3]])			// CHECK9-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, [10 x i32], i64) @.omp_outlined..15 to void (i32, i32, ...)), [10 x i32] [[TMP0]], i64 [[TMP3]])
	// CHECK9-NEXT: ret void			// CHECK9-NEXT: ret void
	//			//
	Show All 18 Lines
	// CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8			// CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8
	// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8			// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
	// CHECK9-NEXT: [[TMP0:%.]] = load [10 x i32], [10 x i32]** [[A_ADDR]], align 8			// CHECK9-NEXT: [[TMP0:%.]] = load [10 x i32], [10 x i32]** [[A_ADDR]], align 8
	// CHECK9-NEXT: [[CONV:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__ADDR]] to i32*			// CHECK9-NEXT: [[CONV:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__ADDR]] to i32*
	// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4			// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
	// CHECK9-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4			// CHECK9-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4			// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
	// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4			// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
	// CHECK9-NEXT: [[TMP1:%.]] = load i32, i32 [[CONV]], align 4			// CHECK9-NEXT: [[TMP1:%.]] = load i32, i32 [[CONV]], align 8
	// CHECK9-NEXT: [[TMP2:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK9-NEXT: [[TMP2:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK9-NEXT: [[TMP3:%.]] = load i32, i32 [[TMP2]], align 4			// CHECK9-NEXT: [[TMP3:%.]] = load i32, i32 [[TMP2]], align 4
	// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP1]])			// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP1]])
	// CHECK9-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK9-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4
	// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 9			// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 9
	// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.]], label [[COND_FALSE:%.]]			// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.]], label [[COND_FALSE:%.]]
	// CHECK9: cond.true:			// CHECK9: cond.true:
	// CHECK9-NEXT: br label [[COND_END:%.*]]			// CHECK9-NEXT: br label [[COND_END:%.*]]
	Show All 10 Lines
	// CHECK9-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !42			// CHECK9-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !42
	// CHECK9-NEXT: [[CMP1:%.*]] = icmp slt i32 [[TMP7]], 10			// CHECK9-NEXT: [[CMP1:%.*]] = icmp slt i32 [[TMP7]], 10
	// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK9: omp.inner.for.body:			// CHECK9: omp.inner.for.body:
	// CHECK9-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !42			// CHECK9-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !42
	// CHECK9-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64			// CHECK9-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
	// CHECK9-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !42			// CHECK9-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !42
	// CHECK9-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64			// CHECK9-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
	// CHECK9-NEXT: [[TMP12:%.]] = load i32, i32 [[CONV]], align 4, !llvm.access.group !42			// CHECK9-NEXT: [[TMP12:%.]] = load i32, i32 [[CONV]], align 8, !llvm.access.group !42
	// CHECK9-NEXT: [[CONV2:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED]] to i32*			// CHECK9-NEXT: [[CONV2:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED]] to i32*
	// CHECK9-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4, !llvm.access.group !42			// CHECK9-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4, !llvm.access.group !42
	// CHECK9-NEXT: [[TMP13:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !42			// CHECK9-NEXT: [[TMP13:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !42
	// CHECK9-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, [10 x i32], i64) @.omp_outlined..16 to void (i32, i32, ...)), i64 [[TMP9]], i64 [[TMP11]], [10 x i32] [[TMP0]], i64 [[TMP13]]), !llvm.access.group !42			// CHECK9-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, [10 x i32], i64) @.omp_outlined..16 to void (i32, i32, ...)), i64 [[TMP9]], i64 [[TMP11]], [10 x i32] [[TMP0]], i64 [[TMP13]]), !llvm.access.group !42
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK9: omp.inner.for.inc:			// CHECK9: omp.inner.for.inc:
	// CHECK9-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !42			// CHECK9-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !42
	// CHECK9-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !42			// CHECK9-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !42
	▲ Show 20 Lines • Show All 850 Lines • ▼ Show 20 Lines
	// CHECK10-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8			// CHECK10-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8
	// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8			// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
	// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8			// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
	// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8			// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
	// CHECK10-NEXT: [[CONV:%.]] = bitcast i64 [[M_ADDR]] to i32*			// CHECK10-NEXT: [[CONV:%.]] = bitcast i64 [[M_ADDR]] to i32*
	// CHECK10-NEXT: [[CONV1:%.]] = bitcast i64 [[N_ADDR]] to i32*			// CHECK10-NEXT: [[CONV1:%.]] = bitcast i64 [[N_ADDR]] to i32*
	// CHECK10-NEXT: [[TMP0:%.]] = load i64, i64 [[VLA_ADDR]], align 8			// CHECK10-NEXT: [[TMP0:%.]] = load i64, i64 [[VLA_ADDR]], align 8
	// CHECK10-NEXT: [[TMP1:%.]] = load i32, i32** [[A_ADDR]], align 8			// CHECK10-NEXT: [[TMP1:%.]] = load i32, i32** [[A_ADDR]], align 8
	// CHECK10-NEXT: [[TMP2:%.]] = load i32, i32 [[CONV]], align 4			// CHECK10-NEXT: [[TMP2:%.]] = load i32, i32 [[CONV]], align 8
	// CHECK10-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4			// CHECK10-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
	// CHECK10-NEXT: [[TMP3:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4			// CHECK10-NEXT: [[TMP3:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4
	// CHECK10-NEXT: [[CONV2:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED]] to i32*			// CHECK10-NEXT: [[CONV2:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED]] to i32*
	// CHECK10-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4			// CHECK10-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
	// CHECK10-NEXT: [[TMP4:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED]], align 8			// CHECK10-NEXT: [[TMP4:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED]], align 8
	// CHECK10-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32, i32, ...)* bitcast (void (i32, i32, i32, i64, i32, i64)* @.omp_outlined..5 to void (i32, i32, ...)), i32 [[CONV1]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP4]])			// CHECK10-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32, i32, ...)* bitcast (void (i32, i32, i32, i64, i32, i64)* @.omp_outlined..5 to void (i32, i32, ...)), i32 [[CONV1]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP4]])
	// CHECK10-NEXT: ret void			// CHECK10-NEXT: ret void
	//			//
	Show All 40 Lines
	// CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]]			// CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]]
	// CHECK10-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.]], label [[OMP_PRECOND_END:%.]]			// CHECK10-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.]], label [[OMP_PRECOND_END:%.]]
	// CHECK10: omp.precond.then:			// CHECK10: omp.precond.then:
	// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4			// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
	// CHECK10-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2]], align 4			// CHECK10-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2]], align 4
	// CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4			// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
	// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4			// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
	// CHECK10-NEXT: [[TMP7:%.]] = load i32, i32 [[CONV]], align 4			// CHECK10-NEXT: [[TMP7:%.]] = load i32, i32 [[CONV]], align 8
	// CHECK10-NEXT: [[TMP8:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK10-NEXT: [[TMP8:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK10-NEXT: [[TMP9:%.]] = load i32, i32 [[TMP8]], align 4			// CHECK10-NEXT: [[TMP9:%.]] = load i32, i32 [[TMP8]], align 4
	// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP7]])			// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP7]])
	// CHECK10-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK10-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4
	// CHECK10-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2]], align 4			// CHECK10-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2]], align 4
	// CHECK10-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]]			// CHECK10-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]]
	// CHECK10-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.]], label [[COND_FALSE:%.]]			// CHECK10-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.]], label [[COND_FALSE:%.]]
	// CHECK10: cond.true:			// CHECK10: cond.true:
	Show All 14 Lines
	// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP16]], 1			// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP16]], 1
	// CHECK10-NEXT: [[CMP6:%.*]] = icmp slt i32 [[TMP15]], [[ADD]]			// CHECK10-NEXT: [[CMP6:%.*]] = icmp slt i32 [[TMP15]], [[ADD]]
	// CHECK10-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK10-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK10: omp.inner.for.body:			// CHECK10: omp.inner.for.body:
	// CHECK10-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !24			// CHECK10-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !24
	// CHECK10-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64			// CHECK10-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
	// CHECK10-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !24			// CHECK10-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !24
	// CHECK10-NEXT: [[TMP20:%.*]] = zext i32 [[TMP19]] to i64			// CHECK10-NEXT: [[TMP20:%.*]] = zext i32 [[TMP19]] to i64
	// CHECK10-NEXT: [[TMP21:%.]] = load i32, i32 [[CONV]], align 4, !llvm.access.group !24			// CHECK10-NEXT: [[TMP21:%.]] = load i32, i32 [[CONV]], align 8, !llvm.access.group !24
	// CHECK10-NEXT: [[CONV7:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED]] to i32*			// CHECK10-NEXT: [[CONV7:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED]] to i32*
	// CHECK10-NEXT: store i32 [[TMP21]], i32* [[CONV7]], align 4, !llvm.access.group !24			// CHECK10-NEXT: store i32 [[TMP21]], i32* [[CONV7]], align 4, !llvm.access.group !24
	// CHECK10-NEXT: [[TMP22:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !24			// CHECK10-NEXT: [[TMP22:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !24
	// CHECK10-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i32, i64, i32, i64)* @.omp_outlined..6 to void (i32, i32, ...)), i64 [[TMP18]], i64 [[TMP20]], i32 [[TMP0]], i64 [[TMP1]], i32* [[TMP2]], i64 [[TMP22]]), !llvm.access.group !24			// CHECK10-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i32, i64, i32, i64)* @.omp_outlined..6 to void (i32, i32, ...)), i64 [[TMP18]], i64 [[TMP20]], i32 [[TMP0]], i64 [[TMP1]], i32* [[TMP2]], i64 [[TMP22]]), !llvm.access.group !24
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK10: omp.inner.for.inc:			// CHECK10: omp.inner.for.inc:
	// CHECK10-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !24			// CHECK10-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !24
	// CHECK10-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !24			// CHECK10-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !24
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	// CHECK10-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8			// CHECK10-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8
	// CHECK10-NEXT: [[A_ADDR:%.]] = alloca [10 x i32], align 8			// CHECK10-NEXT: [[A_ADDR:%.]] = alloca [10 x i32], align 8
	// CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4			// CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
	// CHECK10-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8			// CHECK10-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
	// CHECK10-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8			// CHECK10-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8
	// CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8			// CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8
	// CHECK10-NEXT: [[CONV:%.]] = bitcast i64 [[M_ADDR]] to i32*			// CHECK10-NEXT: [[CONV:%.]] = bitcast i64 [[M_ADDR]] to i32*
	// CHECK10-NEXT: [[TMP0:%.]] = load [10 x i32], [10 x i32]** [[A_ADDR]], align 8			// CHECK10-NEXT: [[TMP0:%.]] = load [10 x i32], [10 x i32]** [[A_ADDR]], align 8
	// CHECK10-NEXT: [[TMP1:%.]] = load i32, i32 [[CONV]], align 4			// CHECK10-NEXT: [[TMP1:%.]] = load i32, i32 [[CONV]], align 8
	// CHECK10-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4			// CHECK10-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
	// CHECK10-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4			// CHECK10-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4
	// CHECK10-NEXT: [[CONV1:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED]] to i32*			// CHECK10-NEXT: [[CONV1:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED]] to i32*
	// CHECK10-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4			// CHECK10-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4
	// CHECK10-NEXT: [[TMP3:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED]], align 8			// CHECK10-NEXT: [[TMP3:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED]], align 8
	// CHECK10-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, [10 x i32], i64) @.omp_outlined..15 to void (i32, i32, ...)), [10 x i32] [[TMP0]], i64 [[TMP3]])			// CHECK10-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, [10 x i32], i64) @.omp_outlined..15 to void (i32, i32, ...)), [10 x i32] [[TMP0]], i64 [[TMP3]])
	// CHECK10-NEXT: ret void			// CHECK10-NEXT: ret void
	//			//
	Show All 18 Lines
	// CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8			// CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8
	// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8			// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
	// CHECK10-NEXT: [[TMP0:%.]] = load [10 x i32], [10 x i32]** [[A_ADDR]], align 8			// CHECK10-NEXT: [[TMP0:%.]] = load [10 x i32], [10 x i32]** [[A_ADDR]], align 8
	// CHECK10-NEXT: [[CONV:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__ADDR]] to i32*			// CHECK10-NEXT: [[CONV:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__ADDR]] to i32*
	// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4			// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
	// CHECK10-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4			// CHECK10-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4			// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
	// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4			// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
	// CHECK10-NEXT: [[TMP1:%.]] = load i32, i32 [[CONV]], align 4			// CHECK10-NEXT: [[TMP1:%.]] = load i32, i32 [[CONV]], align 8
	// CHECK10-NEXT: [[TMP2:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK10-NEXT: [[TMP2:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK10-NEXT: [[TMP3:%.]] = load i32, i32 [[TMP2]], align 4			// CHECK10-NEXT: [[TMP3:%.]] = load i32, i32 [[TMP2]], align 4
	// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP1]])			// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP1]])
	// CHECK10-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK10-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4
	// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 9			// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 9
	// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.]], label [[COND_FALSE:%.]]			// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.]], label [[COND_FALSE:%.]]
	// CHECK10: cond.true:			// CHECK10: cond.true:
	// CHECK10-NEXT: br label [[COND_END:%.*]]			// CHECK10-NEXT: br label [[COND_END:%.*]]
	Show All 10 Lines
	// CHECK10-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !42			// CHECK10-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !42
	// CHECK10-NEXT: [[CMP1:%.*]] = icmp slt i32 [[TMP7]], 10			// CHECK10-NEXT: [[CMP1:%.*]] = icmp slt i32 [[TMP7]], 10
	// CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK10: omp.inner.for.body:			// CHECK10: omp.inner.for.body:
	// CHECK10-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !42			// CHECK10-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !42
	// CHECK10-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64			// CHECK10-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
	// CHECK10-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !42			// CHECK10-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !42
	// CHECK10-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64			// CHECK10-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
	// CHECK10-NEXT: [[TMP12:%.]] = load i32, i32 [[CONV]], align 4, !llvm.access.group !42			// CHECK10-NEXT: [[TMP12:%.]] = load i32, i32 [[CONV]], align 8, !llvm.access.group !42
	// CHECK10-NEXT: [[CONV2:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED]] to i32*			// CHECK10-NEXT: [[CONV2:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED]] to i32*
	// CHECK10-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4, !llvm.access.group !42			// CHECK10-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4, !llvm.access.group !42
	// CHECK10-NEXT: [[TMP13:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !42			// CHECK10-NEXT: [[TMP13:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !42
	// CHECK10-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, [10 x i32], i64) @.omp_outlined..16 to void (i32, i32, ...)), i64 [[TMP9]], i64 [[TMP11]], [10 x i32] [[TMP0]], i64 [[TMP13]]), !llvm.access.group !42			// CHECK10-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, [10 x i32], i64) @.omp_outlined..16 to void (i32, i32, ...)), i64 [[TMP9]], i64 [[TMP11]], [10 x i32] [[TMP0]], i64 [[TMP13]]), !llvm.access.group !42
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK10: omp.inner.for.inc:			// CHECK10: omp.inner.for.inc:
	// CHECK10-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !42			// CHECK10-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !42
	// CHECK10-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !42			// CHECK10-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !42
	▲ Show 20 Lines • Show All 4,553 Lines • Show Last 20 Lines

clang/test/OpenMP/teams_distribute_parallel_for_simd_firstprivate_codegen.cpp

This file is larger than 256 KB, so syntax highlighting is disabled by default.

	Show First 20 Lines • Show All 379 Lines • ▼ Show 20 Lines
	// CHECK1-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8			// CHECK1-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8
	// CHECK1-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8			// CHECK1-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8
	// CHECK1-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8			// CHECK1-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8
	// CHECK1-NEXT: [[CONV:%.]] = bitcast i64 [[T_VAR_ADDR]] to i32*			// CHECK1-NEXT: [[CONV:%.]] = bitcast i64 [[T_VAR_ADDR]] to i32*
	// CHECK1-NEXT: [[TMP0:%.]] = load [2 x i32], [2 x i32]** [[VEC_ADDR]], align 8			// CHECK1-NEXT: [[TMP0:%.]] = load [2 x i32], [2 x i32]** [[VEC_ADDR]], align 8
	// CHECK1-NEXT: [[TMP1:%.]] = load [2 x %struct.S], [2 x %struct.S]** [[S_ARR_ADDR]], align 8			// CHECK1-NEXT: [[TMP1:%.]] = load [2 x %struct.S], [2 x %struct.S]** [[S_ARR_ADDR]], align 8
	// CHECK1-NEXT: [[TMP2:%.]] = load %struct.S, %struct.S** [[VAR_ADDR]], align 8			// CHECK1-NEXT: [[TMP2:%.]] = load %struct.S, %struct.S** [[VAR_ADDR]], align 8
	// CHECK1-NEXT: [[CONV1:%.]] = bitcast i64 [[SIVAR_ADDR]] to i32*			// CHECK1-NEXT: [[CONV1:%.]] = bitcast i64 [[SIVAR_ADDR]] to i32*
	// CHECK1-NEXT: [[TMP3:%.]] = load i32, i32 [[CONV]], align 4			// CHECK1-NEXT: [[TMP3:%.]] = load i32, i32 [[CONV]], align 8
	// CHECK1-NEXT: [[CONV2:%.]] = bitcast i64 [[T_VAR_CASTED]] to i32*			// CHECK1-NEXT: [[CONV2:%.]] = bitcast i64 [[T_VAR_CASTED]] to i32*
	// CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4			// CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
	// CHECK1-NEXT: [[TMP4:%.]] = load i64, i64 [[T_VAR_CASTED]], align 8			// CHECK1-NEXT: [[TMP4:%.]] = load i64, i64 [[T_VAR_CASTED]], align 8
	// CHECK1-NEXT: [[TMP5:%.]] = load i32, i32 [[CONV1]], align 4			// CHECK1-NEXT: [[TMP5:%.]] = load i32, i32 [[CONV1]], align 8
	// CHECK1-NEXT: [[CONV3:%.]] = bitcast i64 [[SIVAR_CASTED]] to i32*			// CHECK1-NEXT: [[CONV3:%.]] = bitcast i64 [[SIVAR_CASTED]] to i32*
	// CHECK1-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4			// CHECK1-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4
	// CHECK1-NEXT: [[TMP6:%.]] = load i64, i64 [[SIVAR_CASTED]], align 8			// CHECK1-NEXT: [[TMP6:%.]] = load i64, i64 [[SIVAR_CASTED]], align 8
	// CHECK1-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32, i32, ...)* bitcast (void (i32, i32, [2 x i32], i64, [2 x %struct.S], %struct.S, i64) @.omp_outlined. to void (i32, i32, ...)), [2 x i32] [[TMP0]], i64 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP2]], i64 [[TMP6]])			// CHECK1-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32, i32, ...)* bitcast (void (i32, i32, [2 x i32], i64, [2 x %struct.S], %struct.S, i64) @.omp_outlined. to void (i32, i32, ...)), [2 x i32] [[TMP0]], i64 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP2]], i64 [[TMP6]])
	// CHECK1-NEXT: ret void			// CHECK1-NEXT: ret void
	//			//
	//			//
	// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined.			// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined.
	▲ Show 20 Lines • Show All 82 Lines • ▼ Show 20 Lines
	// CHECK1-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]			// CHECK1-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]
	// CHECK1: omp.inner.for.cond.cleanup:			// CHECK1: omp.inner.for.cond.cleanup:
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
	// CHECK1: omp.inner.for.body:			// CHECK1: omp.inner.for.body:
	// CHECK1-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !5			// CHECK1-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !5
	// CHECK1-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64			// CHECK1-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64
	// CHECK1-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5			// CHECK1-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5
	// CHECK1-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64			// CHECK1-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
	// CHECK1-NEXT: [[TMP18:%.]] = load i32, i32 [[CONV]], align 4, !llvm.access.group !5			// CHECK1-NEXT: [[TMP18:%.]] = load i32, i32 [[CONV]], align 8, !llvm.access.group !5
	// CHECK1-NEXT: [[CONV8:%.]] = bitcast i64 [[T_VAR_CASTED]] to i32*			// CHECK1-NEXT: [[CONV8:%.]] = bitcast i64 [[T_VAR_CASTED]] to i32*
	// CHECK1-NEXT: store i32 [[TMP18]], i32* [[CONV8]], align 4, !llvm.access.group !5			// CHECK1-NEXT: store i32 [[TMP18]], i32* [[CONV8]], align 4, !llvm.access.group !5
	// CHECK1-NEXT: [[TMP19:%.]] = load i64, i64 [[T_VAR_CASTED]], align 8, !llvm.access.group !5			// CHECK1-NEXT: [[TMP19:%.]] = load i64, i64 [[T_VAR_CASTED]], align 8, !llvm.access.group !5
	// CHECK1-NEXT: [[TMP20:%.]] = load i32, i32 [[CONV1]], align 4, !llvm.access.group !5			// CHECK1-NEXT: [[TMP20:%.]] = load i32, i32 [[CONV1]], align 8, !llvm.access.group !5
	// CHECK1-NEXT: [[CONV9:%.]] = bitcast i64 [[SIVAR_CASTED]] to i32*			// CHECK1-NEXT: [[CONV9:%.]] = bitcast i64 [[SIVAR_CASTED]] to i32*
	// CHECK1-NEXT: store i32 [[TMP20]], i32* [[CONV9]], align 4, !llvm.access.group !5			// CHECK1-NEXT: store i32 [[TMP20]], i32* [[CONV9]], align 4, !llvm.access.group !5
	// CHECK1-NEXT: [[TMP21:%.]] = load i64, i64 [[SIVAR_CASTED]], align 8, !llvm.access.group !5			// CHECK1-NEXT: [[TMP21:%.]] = load i64, i64 [[SIVAR_CASTED]], align 8, !llvm.access.group !5
	// CHECK1-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, [2 x i32], i64, [2 x %struct.S], %struct.S, i64) @.omp_outlined..3 to void (i32, i32, ...)), i64 [[TMP15]], i64 [[TMP17]], [2 x i32] [[VEC2]], i64 [[TMP19]], [2 x %struct.S]* [[S_ARR3]], %struct.S* [[VAR5]], i64 [[TMP21]]), !llvm.access.group !5			// CHECK1-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, [2 x i32], i64, [2 x %struct.S], %struct.S, i64) @.omp_outlined..3 to void (i32, i32, ...)), i64 [[TMP15]], i64 [[TMP17]], [2 x i32] [[VEC2]], i64 [[TMP19]], [2 x %struct.S]* [[S_ARR3]], %struct.S* [[VAR5]], i64 [[TMP21]]), !llvm.access.group !5
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK1: omp.inner.for.inc:			// CHECK1: omp.inner.for.inc:
	// CHECK1-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5			// CHECK1-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK1-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !5			// CHECK1-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !5
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	// CHECK1-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]			// CHECK1-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]
	// CHECK1: omp.inner.for.cond.cleanup:			// CHECK1: omp.inner.for.cond.cleanup:
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
	// CHECK1: omp.inner.for.body:			// CHECK1: omp.inner.for.body:
	// CHECK1-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9			// CHECK1-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1			// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1
	// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9			// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9
	// CHECK1-NEXT: [[TMP17:%.]] = load i32, i32 [[CONV]], align 4, !llvm.access.group !9			// CHECK1-NEXT: [[TMP17:%.]] = load i32, i32 [[CONV]], align 8, !llvm.access.group !9
	// CHECK1-NEXT: [[TMP18:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !9			// CHECK1-NEXT: [[TMP18:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !9
	// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP18]] to i64			// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP18]] to i64
	// CHECK1-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC4]], i64 0, i64 [[IDXPROM]]			// CHECK1-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC4]], i64 0, i64 [[IDXPROM]]
	// CHECK1-NEXT: store i32 [[TMP17]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !9			// CHECK1-NEXT: store i32 [[TMP17]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !9
	// CHECK1-NEXT: [[TMP19:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !9			// CHECK1-NEXT: [[TMP19:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !9
	// CHECK1-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP19]] to i64			// CHECK1-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP19]] to i64
	// CHECK1-NEXT: [[ARRAYIDX11:%.]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S] [[S_ARR5]], i64 0, i64 [[IDXPROM10]]			// CHECK1-NEXT: [[ARRAYIDX11:%.]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S] [[S_ARR5]], i64 0, i64 [[IDXPROM10]]
	// CHECK1-NEXT: [[TMP20:%.]] = bitcast %struct.S [[ARRAYIDX11]] to i8*			// CHECK1-NEXT: [[TMP20:%.]] = bitcast %struct.S [[ARRAYIDX11]] to i8*
	// CHECK1-NEXT: [[TMP21:%.]] = bitcast %struct.S [[VAR7]] to i8*			// CHECK1-NEXT: [[TMP21:%.]] = bitcast %struct.S [[VAR7]] to i8*
	// CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i64 4, i1 false), !llvm.access.group !9			// CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i64 4, i1 false), !llvm.access.group !9
	// CHECK1-NEXT: [[TMP22:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !9			// CHECK1-NEXT: [[TMP22:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !9
	// CHECK1-NEXT: [[TMP23:%.]] = load i32, i32 [[CONV1]], align 4, !llvm.access.group !9			// CHECK1-NEXT: [[TMP23:%.]] = load i32, i32 [[CONV1]], align 8, !llvm.access.group !9
	// CHECK1-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP23]], [[TMP22]]			// CHECK1-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP23]], [[TMP22]]
	// CHECK1-NEXT: store i32 [[ADD12]], i32* [[CONV1]], align 4, !llvm.access.group !9			// CHECK1-NEXT: store i32 [[ADD12]], i32* [[CONV1]], align 8, !llvm.access.group !9
	// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK1: omp.body.continue:			// CHECK1: omp.body.continue:
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK1: omp.inner.for.inc:			// CHECK1: omp.inner.for.inc:
	// CHECK1-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9			// CHECK1-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK1-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP24]], 1			// CHECK1-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP24]], 1
	// CHECK1-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9			// CHECK1-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]
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	// CHECK1-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8			// CHECK1-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8
	// CHECK1-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8			// CHECK1-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
	// CHECK1-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8			// CHECK1-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8
	// CHECK1-NEXT: [[CONV:%.]] = bitcast i64 [[T_VAR_ADDR]] to i32*			// CHECK1-NEXT: [[CONV:%.]] = bitcast i64 [[T_VAR_ADDR]] to i32*
	// CHECK1-NEXT: [[TMP0:%.]] = load [2 x i32], [2 x i32]** [[VEC_ADDR]], align 8			// CHECK1-NEXT: [[TMP0:%.]] = load [2 x i32], [2 x i32]** [[VEC_ADDR]], align 8
	// CHECK1-NEXT: [[TMP1:%.]] = load [2 x %struct.S.0], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8			// CHECK1-NEXT: [[TMP1:%.]] = load [2 x %struct.S.0], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
	// CHECK1-NEXT: [[TMP2:%.]] = load %struct.S.0, %struct.S.0** [[VAR_ADDR]], align 8			// CHECK1-NEXT: [[TMP2:%.]] = load %struct.S.0, %struct.S.0** [[VAR_ADDR]], align 8
	// CHECK1-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8			// CHECK1-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8
	// CHECK1-NEXT: [[TMP3:%.]] = load i32, i32 [[CONV]], align 4			// CHECK1-NEXT: [[TMP3:%.]] = load i32, i32 [[CONV]], align 8
	// CHECK1-NEXT: [[CONV1:%.]] = bitcast i64 [[T_VAR_CASTED]] to i32*			// CHECK1-NEXT: [[CONV1:%.]] = bitcast i64 [[T_VAR_CASTED]] to i32*
	// CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4			// CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4
	// CHECK1-NEXT: [[TMP4:%.]] = load i64, i64 [[T_VAR_CASTED]], align 8			// CHECK1-NEXT: [[TMP4:%.]] = load i64, i64 [[T_VAR_CASTED]], align 8
	// CHECK1-NEXT: [[TMP5:%.]] = load %struct.S.0, %struct.S.0** [[TMP]], align 8			// CHECK1-NEXT: [[TMP5:%.]] = load %struct.S.0, %struct.S.0** [[TMP]], align 8
	// CHECK1-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32, i32, ...)* bitcast (void (i32, i32, [2 x i32], i64, [2 x %struct.S.0], %struct.S.0) @.omp_outlined..4 to void (i32, i32, ...)), [2 x i32] [[TMP0]], i64 [[TMP4]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP5]])			// CHECK1-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32, i32, ...)* bitcast (void (i32, i32, [2 x i32], i64, [2 x %struct.S.0], %struct.S.0) @.omp_outlined..4 to void (i32, i32, ...)), [2 x i32] [[TMP0]], i64 [[TMP4]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP5]])
	// CHECK1-NEXT: ret void			// CHECK1-NEXT: ret void
	//			//
	//			//
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	// CHECK1-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]			// CHECK1-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]
	// CHECK1: omp.inner.for.cond.cleanup:			// CHECK1: omp.inner.for.cond.cleanup:
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
	// CHECK1: omp.inner.for.body:			// CHECK1: omp.inner.for.body:
	// CHECK1-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !14			// CHECK1-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !14
	// CHECK1-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64			// CHECK1-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64
	// CHECK1-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !14			// CHECK1-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !14
	// CHECK1-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64			// CHECK1-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
	// CHECK1-NEXT: [[TMP19:%.]] = load i32, i32 [[CONV]], align 4, !llvm.access.group !14			// CHECK1-NEXT: [[TMP19:%.]] = load i32, i32 [[CONV]], align 8, !llvm.access.group !14
	// CHECK1-NEXT: [[CONV9:%.]] = bitcast i64 [[T_VAR_CASTED]] to i32*			// CHECK1-NEXT: [[CONV9:%.]] = bitcast i64 [[T_VAR_CASTED]] to i32*
	// CHECK1-NEXT: store i32 [[TMP19]], i32* [[CONV9]], align 4, !llvm.access.group !14			// CHECK1-NEXT: store i32 [[TMP19]], i32* [[CONV9]], align 4, !llvm.access.group !14
	// CHECK1-NEXT: [[TMP20:%.]] = load i64, i64 [[T_VAR_CASTED]], align 8, !llvm.access.group !14			// CHECK1-NEXT: [[TMP20:%.]] = load i64, i64 [[T_VAR_CASTED]], align 8, !llvm.access.group !14
	// CHECK1-NEXT: [[TMP21:%.]] = load %struct.S.0, %struct.S.0** [[_TMP7]], align 8, !llvm.access.group !14			// CHECK1-NEXT: [[TMP21:%.]] = load %struct.S.0, %struct.S.0** [[_TMP7]], align 8, !llvm.access.group !14
	// CHECK1-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, [2 x i32], i64, [2 x %struct.S.0], %struct.S.0) @.omp_outlined..5 to void (i32, i32, ...)), i64 [[TMP16]], i64 [[TMP18]], [2 x i32] [[VEC2]], i64 [[TMP20]], [2 x %struct.S.0]* [[S_ARR3]], %struct.S.0* [[TMP21]]), !llvm.access.group !14			// CHECK1-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, [2 x i32], i64, [2 x %struct.S.0], %struct.S.0) @.omp_outlined..5 to void (i32, i32, ...)), i64 [[TMP16]], i64 [[TMP18]], [2 x i32] [[VEC2]], i64 [[TMP20]], [2 x %struct.S.0]* [[S_ARR3]], %struct.S.0* [[TMP21]]), !llvm.access.group !14
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK1: omp.inner.for.inc:			// CHECK1: omp.inner.for.inc:
	// CHECK1-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14			// CHECK1-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14
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	// CHECK1-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]			// CHECK1-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]
	// CHECK1: omp.inner.for.cond.cleanup:			// CHECK1: omp.inner.for.cond.cleanup:
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
	// CHECK1: omp.inner.for.body:			// CHECK1: omp.inner.for.body:
	// CHECK1-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !17			// CHECK1-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !17
	// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1			// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1
	// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !17			// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !17
	// CHECK1-NEXT: [[TMP18:%.]] = load i32, i32 [[CONV]], align 4, !llvm.access.group !17			// CHECK1-NEXT: [[TMP18:%.]] = load i32, i32 [[CONV]], align 8, !llvm.access.group !17
	// CHECK1-NEXT: [[TMP19:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !17			// CHECK1-NEXT: [[TMP19:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !17
	// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64			// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64
	// CHECK1-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC4]], i64 0, i64 [[IDXPROM]]			// CHECK1-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC4]], i64 0, i64 [[IDXPROM]]
	// CHECK1-NEXT: store i32 [[TMP18]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !17			// CHECK1-NEXT: store i32 [[TMP18]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !17
	// CHECK1-NEXT: [[TMP20:%.]] = load %struct.S.0, %struct.S.0** [[_TMP9]], align 8, !llvm.access.group !17			// CHECK1-NEXT: [[TMP20:%.]] = load %struct.S.0, %struct.S.0** [[_TMP9]], align 8, !llvm.access.group !17
	// CHECK1-NEXT: [[TMP21:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !17			// CHECK1-NEXT: [[TMP21:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !17
	// CHECK1-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP21]] to i64			// CHECK1-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP21]] to i64
	// CHECK1-NEXT: [[ARRAYIDX12:%.]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0] [[S_ARR5]], i64 0, i64 [[IDXPROM11]]			// CHECK1-NEXT: [[ARRAYIDX12:%.]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0] [[S_ARR5]], i64 0, i64 [[IDXPROM11]]
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	// CHECK2-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8			// CHECK2-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8
	// CHECK2-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8			// CHECK2-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8
	// CHECK2-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8			// CHECK2-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8
	// CHECK2-NEXT: [[CONV:%.]] = bitcast i64 [[T_VAR_ADDR]] to i32*			// CHECK2-NEXT: [[CONV:%.]] = bitcast i64 [[T_VAR_ADDR]] to i32*
	// CHECK2-NEXT: [[TMP0:%.]] = load [2 x i32], [2 x i32]** [[VEC_ADDR]], align 8			// CHECK2-NEXT: [[TMP0:%.]] = load [2 x i32], [2 x i32]** [[VEC_ADDR]], align 8
	// CHECK2-NEXT: [[TMP1:%.]] = load [2 x %struct.S], [2 x %struct.S]** [[S_ARR_ADDR]], align 8			// CHECK2-NEXT: [[TMP1:%.]] = load [2 x %struct.S], [2 x %struct.S]** [[S_ARR_ADDR]], align 8
	// CHECK2-NEXT: [[TMP2:%.]] = load %struct.S, %struct.S** [[VAR_ADDR]], align 8			// CHECK2-NEXT: [[TMP2:%.]] = load %struct.S, %struct.S** [[VAR_ADDR]], align 8
	// CHECK2-NEXT: [[CONV1:%.]] = bitcast i64 [[SIVAR_ADDR]] to i32*			// CHECK2-NEXT: [[CONV1:%.]] = bitcast i64 [[SIVAR_ADDR]] to i32*
	// CHECK2-NEXT: [[TMP3:%.]] = load i32, i32 [[CONV]], align 4			// CHECK2-NEXT: [[TMP3:%.]] = load i32, i32 [[CONV]], align 8
	// CHECK2-NEXT: [[CONV2:%.]] = bitcast i64 [[T_VAR_CASTED]] to i32*			// CHECK2-NEXT: [[CONV2:%.]] = bitcast i64 [[T_VAR_CASTED]] to i32*
	// CHECK2-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4			// CHECK2-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
	// CHECK2-NEXT: [[TMP4:%.]] = load i64, i64 [[T_VAR_CASTED]], align 8			// CHECK2-NEXT: [[TMP4:%.]] = load i64, i64 [[T_VAR_CASTED]], align 8
	// CHECK2-NEXT: [[TMP5:%.]] = load i32, i32 [[CONV1]], align 4			// CHECK2-NEXT: [[TMP5:%.]] = load i32, i32 [[CONV1]], align 8
	// CHECK2-NEXT: [[CONV3:%.]] = bitcast i64 [[SIVAR_CASTED]] to i32*			// CHECK2-NEXT: [[CONV3:%.]] = bitcast i64 [[SIVAR_CASTED]] to i32*
	// CHECK2-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4			// CHECK2-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4
	// CHECK2-NEXT: [[TMP6:%.]] = load i64, i64 [[SIVAR_CASTED]], align 8			// CHECK2-NEXT: [[TMP6:%.]] = load i64, i64 [[SIVAR_CASTED]], align 8
	// CHECK2-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32, i32, ...)* bitcast (void (i32, i32, [2 x i32], i64, [2 x %struct.S], %struct.S, i64) @.omp_outlined. to void (i32, i32, ...)), [2 x i32] [[TMP0]], i64 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP2]], i64 [[TMP6]])			// CHECK2-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32, i32, ...)* bitcast (void (i32, i32, [2 x i32], i64, [2 x %struct.S], %struct.S, i64) @.omp_outlined. to void (i32, i32, ...)), [2 x i32] [[TMP0]], i64 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP2]], i64 [[TMP6]])
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined.			// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined.
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	// CHECK2-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]			// CHECK2-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]
	// CHECK2: omp.inner.for.cond.cleanup:			// CHECK2: omp.inner.for.cond.cleanup:
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_END:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
	// CHECK2: omp.inner.for.body:			// CHECK2: omp.inner.for.body:
	// CHECK2-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !5			// CHECK2-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !5
	// CHECK2-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64			// CHECK2-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64
	// CHECK2-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5			// CHECK2-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5
	// CHECK2-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64			// CHECK2-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
	// CHECK2-NEXT: [[TMP18:%.]] = load i32, i32 [[CONV]], align 4, !llvm.access.group !5			// CHECK2-NEXT: [[TMP18:%.]] = load i32, i32 [[CONV]], align 8, !llvm.access.group !5
	// CHECK2-NEXT: [[CONV8:%.]] = bitcast i64 [[T_VAR_CASTED]] to i32*			// CHECK2-NEXT: [[CONV8:%.]] = bitcast i64 [[T_VAR_CASTED]] to i32*
	// CHECK2-NEXT: store i32 [[TMP18]], i32* [[CONV8]], align 4, !llvm.access.group !5			// CHECK2-NEXT: store i32 [[TMP18]], i32* [[CONV8]], align 4, !llvm.access.group !5
	// CHECK2-NEXT: [[TMP19:%.]] = load i64, i64 [[T_VAR_CASTED]], align 8, !llvm.access.group !5			// CHECK2-NEXT: [[TMP19:%.]] = load i64, i64 [[T_VAR_CASTED]], align 8, !llvm.access.group !5
	// CHECK2-NEXT: [[TMP20:%.]] = load i32, i32 [[CONV1]], align 4, !llvm.access.group !5			// CHECK2-NEXT: [[TMP20:%.]] = load i32, i32 [[CONV1]], align 8, !llvm.access.group !5
	// CHECK2-NEXT: [[CONV9:%.]] = bitcast i64 [[SIVAR_CASTED]] to i32*			// CHECK2-NEXT: [[CONV9:%.]] = bitcast i64 [[SIVAR_CASTED]] to i32*
	// CHECK2-NEXT: store i32 [[TMP20]], i32* [[CONV9]], align 4, !llvm.access.group !5			// CHECK2-NEXT: store i32 [[TMP20]], i32* [[CONV9]], align 4, !llvm.access.group !5
	// CHECK2-NEXT: [[TMP21:%.]] = load i64, i64 [[SIVAR_CASTED]], align 8, !llvm.access.group !5			// CHECK2-NEXT: [[TMP21:%.]] = load i64, i64 [[SIVAR_CASTED]], align 8, !llvm.access.group !5
	// CHECK2-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, [2 x i32], i64, [2 x %struct.S], %struct.S, i64) @.omp_outlined..3 to void (i32, i32, ...)), i64 [[TMP15]], i64 [[TMP17]], [2 x i32] [[VEC2]], i64 [[TMP19]], [2 x %struct.S]* [[S_ARR3]], %struct.S* [[VAR5]], i64 [[TMP21]]), !llvm.access.group !5			// CHECK2-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, [2 x i32], i64, [2 x %struct.S], %struct.S, i64) @.omp_outlined..3 to void (i32, i32, ...)), i64 [[TMP15]], i64 [[TMP17]], [2 x i32] [[VEC2]], i64 [[TMP19]], [2 x %struct.S]* [[S_ARR3]], %struct.S* [[VAR5]], i64 [[TMP21]]), !llvm.access.group !5
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK2: omp.inner.for.inc:			// CHECK2: omp.inner.for.inc:
	// CHECK2-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5			// CHECK2-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK2-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !5			// CHECK2-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !5
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	// CHECK2-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]			// CHECK2-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]
	// CHECK2: omp.inner.for.cond.cleanup:			// CHECK2: omp.inner.for.cond.cleanup:
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_END:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
	// CHECK2: omp.inner.for.body:			// CHECK2: omp.inner.for.body:
	// CHECK2-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9			// CHECK2-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1			// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1
	// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9			// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9
	// CHECK2-NEXT: [[TMP17:%.]] = load i32, i32 [[CONV]], align 4, !llvm.access.group !9			// CHECK2-NEXT: [[TMP17:%.]] = load i32, i32 [[CONV]], align 8, !llvm.access.group !9
	// CHECK2-NEXT: [[TMP18:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !9			// CHECK2-NEXT: [[TMP18:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !9
	// CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP18]] to i64			// CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP18]] to i64
	// CHECK2-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC4]], i64 0, i64 [[IDXPROM]]			// CHECK2-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC4]], i64 0, i64 [[IDXPROM]]
	// CHECK2-NEXT: store i32 [[TMP17]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !9			// CHECK2-NEXT: store i32 [[TMP17]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !9
	// CHECK2-NEXT: [[TMP19:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !9			// CHECK2-NEXT: [[TMP19:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !9
	// CHECK2-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP19]] to i64			// CHECK2-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP19]] to i64
	// CHECK2-NEXT: [[ARRAYIDX11:%.]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S] [[S_ARR5]], i64 0, i64 [[IDXPROM10]]			// CHECK2-NEXT: [[ARRAYIDX11:%.]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S] [[S_ARR5]], i64 0, i64 [[IDXPROM10]]
	// CHECK2-NEXT: [[TMP20:%.]] = bitcast %struct.S [[ARRAYIDX11]] to i8*			// CHECK2-NEXT: [[TMP20:%.]] = bitcast %struct.S [[ARRAYIDX11]] to i8*
	// CHECK2-NEXT: [[TMP21:%.]] = bitcast %struct.S [[VAR7]] to i8*			// CHECK2-NEXT: [[TMP21:%.]] = bitcast %struct.S [[VAR7]] to i8*
	// CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i64 4, i1 false), !llvm.access.group !9			// CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i64 4, i1 false), !llvm.access.group !9
	// CHECK2-NEXT: [[TMP22:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !9			// CHECK2-NEXT: [[TMP22:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !9
	// CHECK2-NEXT: [[TMP23:%.]] = load i32, i32 [[CONV1]], align 4, !llvm.access.group !9			// CHECK2-NEXT: [[TMP23:%.]] = load i32, i32 [[CONV1]], align 8, !llvm.access.group !9
	// CHECK2-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP23]], [[TMP22]]			// CHECK2-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP23]], [[TMP22]]
	// CHECK2-NEXT: store i32 [[ADD12]], i32* [[CONV1]], align 4, !llvm.access.group !9			// CHECK2-NEXT: store i32 [[ADD12]], i32* [[CONV1]], align 8, !llvm.access.group !9
	// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK2: omp.body.continue:			// CHECK2: omp.body.continue:
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK2: omp.inner.for.inc:			// CHECK2: omp.inner.for.inc:
	// CHECK2-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9			// CHECK2-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK2-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP24]], 1			// CHECK2-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP24]], 1
	// CHECK2-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9			// CHECK2-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]
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	// CHECK2-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8			// CHECK2-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8
	// CHECK2-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8			// CHECK2-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
	// CHECK2-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8			// CHECK2-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8
	// CHECK2-NEXT: [[CONV:%.]] = bitcast i64 [[T_VAR_ADDR]] to i32*			// CHECK2-NEXT: [[CONV:%.]] = bitcast i64 [[T_VAR_ADDR]] to i32*
	// CHECK2-NEXT: [[TMP0:%.]] = load [2 x i32], [2 x i32]** [[VEC_ADDR]], align 8			// CHECK2-NEXT: [[TMP0:%.]] = load [2 x i32], [2 x i32]** [[VEC_ADDR]], align 8
	// CHECK2-NEXT: [[TMP1:%.]] = load [2 x %struct.S.0], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8			// CHECK2-NEXT: [[TMP1:%.]] = load [2 x %struct.S.0], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
	// CHECK2-NEXT: [[TMP2:%.]] = load %struct.S.0, %struct.S.0** [[VAR_ADDR]], align 8			// CHECK2-NEXT: [[TMP2:%.]] = load %struct.S.0, %struct.S.0** [[VAR_ADDR]], align 8
	// CHECK2-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8			// CHECK2-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8
	// CHECK2-NEXT: [[TMP3:%.]] = load i32, i32 [[CONV]], align 4			// CHECK2-NEXT: [[TMP3:%.]] = load i32, i32 [[CONV]], align 8
	// CHECK2-NEXT: [[CONV1:%.]] = bitcast i64 [[T_VAR_CASTED]] to i32*			// CHECK2-NEXT: [[CONV1:%.]] = bitcast i64 [[T_VAR_CASTED]] to i32*
	// CHECK2-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4			// CHECK2-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4
	// CHECK2-NEXT: [[TMP4:%.]] = load i64, i64 [[T_VAR_CASTED]], align 8			// CHECK2-NEXT: [[TMP4:%.]] = load i64, i64 [[T_VAR_CASTED]], align 8
	// CHECK2-NEXT: [[TMP5:%.]] = load %struct.S.0, %struct.S.0** [[TMP]], align 8			// CHECK2-NEXT: [[TMP5:%.]] = load %struct.S.0, %struct.S.0** [[TMP]], align 8
	// CHECK2-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32, i32, ...)* bitcast (void (i32, i32, [2 x i32], i64, [2 x %struct.S.0], %struct.S.0) @.omp_outlined..4 to void (i32, i32, ...)), [2 x i32] [[TMP0]], i64 [[TMP4]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP5]])			// CHECK2-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32, i32, ...)* bitcast (void (i32, i32, [2 x i32], i64, [2 x %struct.S.0], %struct.S.0) @.omp_outlined..4 to void (i32, i32, ...)), [2 x i32] [[TMP0]], i64 [[TMP4]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP5]])
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	//			//
	//			//
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	// CHECK2-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]			// CHECK2-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]
	// CHECK2: omp.inner.for.cond.cleanup:			// CHECK2: omp.inner.for.cond.cleanup:
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_END:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
	// CHECK2: omp.inner.for.body:			// CHECK2: omp.inner.for.body:
	// CHECK2-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !14			// CHECK2-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !14
	// CHECK2-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64			// CHECK2-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64
	// CHECK2-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !14			// CHECK2-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !14
	// CHECK2-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64			// CHECK2-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
	// CHECK2-NEXT: [[TMP19:%.]] = load i32, i32 [[CONV]], align 4, !llvm.access.group !14			// CHECK2-NEXT: [[TMP19:%.]] = load i32, i32 [[CONV]], align 8, !llvm.access.group !14
	// CHECK2-NEXT: [[CONV9:%.]] = bitcast i64 [[T_VAR_CASTED]] to i32*			// CHECK2-NEXT: [[CONV9:%.]] = bitcast i64 [[T_VAR_CASTED]] to i32*
	// CHECK2-NEXT: store i32 [[TMP19]], i32* [[CONV9]], align 4, !llvm.access.group !14			// CHECK2-NEXT: store i32 [[TMP19]], i32* [[CONV9]], align 4, !llvm.access.group !14
	// CHECK2-NEXT: [[TMP20:%.]] = load i64, i64 [[T_VAR_CASTED]], align 8, !llvm.access.group !14			// CHECK2-NEXT: [[TMP20:%.]] = load i64, i64 [[T_VAR_CASTED]], align 8, !llvm.access.group !14
	// CHECK2-NEXT: [[TMP21:%.]] = load %struct.S.0, %struct.S.0** [[_TMP7]], align 8, !llvm.access.group !14			// CHECK2-NEXT: [[TMP21:%.]] = load %struct.S.0, %struct.S.0** [[_TMP7]], align 8, !llvm.access.group !14
	// CHECK2-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, [2 x i32], i64, [2 x %struct.S.0], %struct.S.0) @.omp_outlined..5 to void (i32, i32, ...)), i64 [[TMP16]], i64 [[TMP18]], [2 x i32] [[VEC2]], i64 [[TMP20]], [2 x %struct.S.0]* [[S_ARR3]], %struct.S.0* [[TMP21]]), !llvm.access.group !14			// CHECK2-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, [2 x i32], i64, [2 x %struct.S.0], %struct.S.0) @.omp_outlined..5 to void (i32, i32, ...)), i64 [[TMP16]], i64 [[TMP18]], [2 x i32] [[VEC2]], i64 [[TMP20]], [2 x %struct.S.0]* [[S_ARR3]], %struct.S.0* [[TMP21]]), !llvm.access.group !14
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK2: omp.inner.for.inc:			// CHECK2: omp.inner.for.inc:
	// CHECK2-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14			// CHECK2-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14
	▲ Show 20 Lines • Show All 137 Lines • ▼ Show 20 Lines
	// CHECK2-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]			// CHECK2-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]
	// CHECK2: omp.inner.for.cond.cleanup:			// CHECK2: omp.inner.for.cond.cleanup:
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_END:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
	// CHECK2: omp.inner.for.body:			// CHECK2: omp.inner.for.body:
	// CHECK2-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !17			// CHECK2-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !17
	// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1			// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1
	// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !17			// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !17
	// CHECK2-NEXT: [[TMP18:%.]] = load i32, i32 [[CONV]], align 4, !llvm.access.group !17			// CHECK2-NEXT: [[TMP18:%.]] = load i32, i32 [[CONV]], align 8, !llvm.access.group !17
	// CHECK2-NEXT: [[TMP19:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !17			// CHECK2-NEXT: [[TMP19:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !17
	// CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64			// CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64
	// CHECK2-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC4]], i64 0, i64 [[IDXPROM]]			// CHECK2-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC4]], i64 0, i64 [[IDXPROM]]
	// CHECK2-NEXT: store i32 [[TMP18]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !17			// CHECK2-NEXT: store i32 [[TMP18]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !17
	// CHECK2-NEXT: [[TMP20:%.]] = load %struct.S.0, %struct.S.0** [[_TMP9]], align 8, !llvm.access.group !17			// CHECK2-NEXT: [[TMP20:%.]] = load %struct.S.0, %struct.S.0** [[_TMP9]], align 8, !llvm.access.group !17
	// CHECK2-NEXT: [[TMP21:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !17			// CHECK2-NEXT: [[TMP21:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !17
	// CHECK2-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP21]] to i64			// CHECK2-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP21]] to i64
	// CHECK2-NEXT: [[ARRAYIDX12:%.]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0] [[S_ARR5]], i64 0, i64 [[IDXPROM11]]			// CHECK2-NEXT: [[ARRAYIDX12:%.]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0] [[S_ARR5]], i64 0, i64 [[IDXPROM11]]
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	// CHECK9-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8			// CHECK9-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8
	// CHECK9-NEXT: store i64 [[G]], i64* [[G_ADDR]], align 8			// CHECK9-NEXT: store i64 [[G]], i64* [[G_ADDR]], align 8
	// CHECK9-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8			// CHECK9-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8
	// CHECK9-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8			// CHECK9-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8
	// CHECK9-NEXT: [[CONV:%.]] = bitcast i64 [[G_ADDR]] to i32*			// CHECK9-NEXT: [[CONV:%.]] = bitcast i64 [[G_ADDR]] to i32*
	// CHECK9-NEXT: [[CONV1:%.]] = bitcast i64 [[SIVAR_ADDR]] to i32*			// CHECK9-NEXT: [[CONV1:%.]] = bitcast i64 [[SIVAR_ADDR]] to i32*
	// CHECK9-NEXT: [[CONV2:%.]] = bitcast i64 [[G1_ADDR]] to i32*			// CHECK9-NEXT: [[CONV2:%.]] = bitcast i64 [[G1_ADDR]] to i32*
	// CHECK9-NEXT: store i32* [[CONV2]], i32** [[TMP]], align 8			// CHECK9-NEXT: store i32* [[CONV2]], i32** [[TMP]], align 8
	// CHECK9-NEXT: [[TMP0:%.]] = load i32, i32 [[CONV]], align 4			// CHECK9-NEXT: [[TMP0:%.]] = load i32, i32 [[CONV]], align 8
	// CHECK9-NEXT: [[CONV3:%.]] = bitcast i64 [[G_CASTED]] to i32*			// CHECK9-NEXT: [[CONV3:%.]] = bitcast i64 [[G_CASTED]] to i32*
	// CHECK9-NEXT: store i32 [[TMP0]], i32* [[CONV3]], align 4			// CHECK9-NEXT: store i32 [[TMP0]], i32* [[CONV3]], align 4
	// CHECK9-NEXT: [[TMP1:%.]] = load i64, i64 [[G_CASTED]], align 8			// CHECK9-NEXT: [[TMP1:%.]] = load i64, i64 [[G_CASTED]], align 8
	// CHECK9-NEXT: [[TMP2:%.]] = load i32, i32** [[TMP]], align 8			// CHECK9-NEXT: [[TMP2:%.]] = load i32, i32** [[TMP]], align 8
	// CHECK9-NEXT: [[TMP3:%.]] = load volatile i32, i32 [[TMP2]], align 4			// CHECK9-NEXT: [[TMP3:%.]] = load volatile i32, i32 [[TMP2]], align 4
	// CHECK9-NEXT: [[CONV4:%.]] = bitcast i64 [[G1_CASTED]] to i32*			// CHECK9-NEXT: [[CONV4:%.]] = bitcast i64 [[G1_CASTED]] to i32*
	// CHECK9-NEXT: store i32 [[TMP3]], i32* [[CONV4]], align 4			// CHECK9-NEXT: store i32 [[TMP3]], i32* [[CONV4]], align 4
	// CHECK9-NEXT: [[TMP4:%.]] = load i64, i64 [[G1_CASTED]], align 8			// CHECK9-NEXT: [[TMP4:%.]] = load i64, i64 [[G1_CASTED]], align 8
	// CHECK9-NEXT: [[TMP5:%.]] = load i32, i32 [[CONV1]], align 4			// CHECK9-NEXT: [[TMP5:%.]] = load i32, i32 [[CONV1]], align 8
	// CHECK9-NEXT: [[CONV5:%.]] = bitcast i64 [[SIVAR_CASTED]] to i32*			// CHECK9-NEXT: [[CONV5:%.]] = bitcast i64 [[SIVAR_CASTED]] to i32*
	// CHECK9-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4			// CHECK9-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4
	// CHECK9-NEXT: [[TMP6:%.]] = load i64, i64 [[SIVAR_CASTED]], align 8			// CHECK9-NEXT: [[TMP6:%.]] = load i64, i64 [[SIVAR_CASTED]], align 8
	// CHECK9-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i64)* @.omp_outlined. to void (i32, i32, ...)*), i64 [[TMP1]], i64 [[TMP4]], i64 [[TMP6]])			// CHECK9-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i64)* @.omp_outlined. to void (i32, i32, ...)*), i64 [[TMP1]], i64 [[TMP4]], i64 [[TMP6]])
	// CHECK9-NEXT: ret void			// CHECK9-NEXT: ret void
	//			//
	//			//
	// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined.			// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined.
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	// CHECK9-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !4			// CHECK9-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !4
	// CHECK9-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK9-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK9-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK9-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK9: omp.inner.for.body:			// CHECK9: omp.inner.for.body:
	// CHECK9-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !4			// CHECK9-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !4
	// CHECK9-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64			// CHECK9-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
	// CHECK9-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !4			// CHECK9-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !4
	// CHECK9-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK9-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK9-NEXT: [[TMP11:%.]] = load i32, i32 [[CONV]], align 4, !llvm.access.group !4			// CHECK9-NEXT: [[TMP11:%.]] = load i32, i32 [[CONV]], align 8, !llvm.access.group !4
	// CHECK9-NEXT: [[CONV5:%.]] = bitcast i64 [[G_CASTED]] to i32*			// CHECK9-NEXT: [[CONV5:%.]] = bitcast i64 [[G_CASTED]] to i32*
	// CHECK9-NEXT: store i32 [[TMP11]], i32* [[CONV5]], align 4, !llvm.access.group !4			// CHECK9-NEXT: store i32 [[TMP11]], i32* [[CONV5]], align 4, !llvm.access.group !4
	// CHECK9-NEXT: [[TMP12:%.]] = load i64, i64 [[G_CASTED]], align 8, !llvm.access.group !4			// CHECK9-NEXT: [[TMP12:%.]] = load i64, i64 [[G_CASTED]], align 8, !llvm.access.group !4
	// CHECK9-NEXT: [[TMP13:%.]] = load i32, i32** [[TMP]], align 8, !llvm.access.group !4			// CHECK9-NEXT: [[TMP13:%.]] = load i32, i32** [[TMP]], align 8, !llvm.access.group !4
	// CHECK9-NEXT: [[TMP14:%.]] = load volatile i32, i32 [[TMP13]], align 4, !llvm.access.group !4			// CHECK9-NEXT: [[TMP14:%.]] = load volatile i32, i32 [[TMP13]], align 4, !llvm.access.group !4
	// CHECK9-NEXT: [[CONV6:%.]] = bitcast i64 [[G1_CASTED]] to i32*			// CHECK9-NEXT: [[CONV6:%.]] = bitcast i64 [[G1_CASTED]] to i32*
	// CHECK9-NEXT: store i32 [[TMP14]], i32* [[CONV6]], align 4, !llvm.access.group !4			// CHECK9-NEXT: store i32 [[TMP14]], i32* [[CONV6]], align 4, !llvm.access.group !4
	// CHECK9-NEXT: [[TMP15:%.]] = load i64, i64 [[G1_CASTED]], align 8, !llvm.access.group !4			// CHECK9-NEXT: [[TMP15:%.]] = load i64, i64 [[G1_CASTED]], align 8, !llvm.access.group !4
	// CHECK9-NEXT: [[TMP16:%.]] = load i32, i32 [[CONV2]], align 4, !llvm.access.group !4			// CHECK9-NEXT: [[TMP16:%.]] = load i32, i32 [[CONV2]], align 8, !llvm.access.group !4
	// CHECK9-NEXT: [[CONV7:%.]] = bitcast i64 [[SIVAR_CASTED]] to i32*			// CHECK9-NEXT: [[CONV7:%.]] = bitcast i64 [[SIVAR_CASTED]] to i32*
	// CHECK9-NEXT: store i32 [[TMP16]], i32* [[CONV7]], align 4, !llvm.access.group !4			// CHECK9-NEXT: store i32 [[TMP16]], i32* [[CONV7]], align 4, !llvm.access.group !4
	// CHECK9-NEXT: [[TMP17:%.]] = load i64, i64 [[SIVAR_CASTED]], align 8, !llvm.access.group !4			// CHECK9-NEXT: [[TMP17:%.]] = load i64, i64 [[SIVAR_CASTED]], align 8, !llvm.access.group !4
	// CHECK9-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i64, i64, i64)* @.omp_outlined..3 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]], i64 [[TMP12]], i64 [[TMP15]], i64 [[TMP17]]), !llvm.access.group !4			// CHECK9-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i64, i64, i64)* @.omp_outlined..3 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]], i64 [[TMP12]], i64 [[TMP15]], i64 [[TMP17]]), !llvm.access.group !4
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK9: omp.inner.for.inc:			// CHECK9: omp.inner.for.inc:
	// CHECK9-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !4			// CHECK9-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !4
	// CHECK9-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !4			// CHECK9-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !4
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	// CHECK9-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !8			// CHECK9-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !8
	// CHECK9-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK9-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK9-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK9-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK9: omp.inner.for.body:			// CHECK9: omp.inner.for.body:
	// CHECK9-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !8			// CHECK9-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !8
	// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !8			// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !8
	// CHECK9-NEXT: store i32 1, i32* [[CONV]], align 4, !llvm.access.group !8			// CHECK9-NEXT: store i32 1, i32* [[CONV]], align 8, !llvm.access.group !8
	// CHECK9-NEXT: [[TMP10:%.]] = load i32, i32** [[TMP]], align 8, !llvm.access.group !8			// CHECK9-NEXT: [[TMP10:%.]] = load i32, i32** [[TMP]], align 8, !llvm.access.group !8
	// CHECK9-NEXT: store volatile i32 1, i32* [[TMP10]], align 4, !llvm.access.group !8			// CHECK9-NEXT: store volatile i32 1, i32* [[TMP10]], align 4, !llvm.access.group !8
	// CHECK9-NEXT: store i32 2, i32* [[CONV2]], align 4, !llvm.access.group !8			// CHECK9-NEXT: store i32 2, i32* [[CONV2]], align 8, !llvm.access.group !8
	// CHECK9-NEXT: [[TMP11:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 0			// CHECK9-NEXT: [[TMP11:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 0
	// CHECK9-NEXT: store i32* [[CONV]], i32** [[TMP11]], align 8, !llvm.access.group !8			// CHECK9-NEXT: store i32* [[CONV]], i32** [[TMP11]], align 8, !llvm.access.group !8
	// CHECK9-NEXT: [[TMP12:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 1			// CHECK9-NEXT: [[TMP12:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 1
	// CHECK9-NEXT: [[TMP13:%.]] = load i32, i32** [[TMP]], align 8, !llvm.access.group !8			// CHECK9-NEXT: [[TMP13:%.]] = load i32, i32** [[TMP]], align 8, !llvm.access.group !8
	// CHECK9-NEXT: store i32* [[TMP13]], i32** [[TMP12]], align 8, !llvm.access.group !8			// CHECK9-NEXT: store i32* [[TMP13]], i32** [[TMP12]], align 8, !llvm.access.group !8
	// CHECK9-NEXT: [[TMP14:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 2			// CHECK9-NEXT: [[TMP14:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 2
	// CHECK9-NEXT: store i32* [[CONV2]], i32** [[TMP14]], align 8, !llvm.access.group !8			// CHECK9-NEXT: store i32* [[CONV2]], i32** [[TMP14]], align 8, !llvm.access.group !8
	// CHECK9-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(24) [[REF_TMP]]), !llvm.access.group !8			// CHECK9-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(24) [[REF_TMP]]), !llvm.access.group !8
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	// CHECK10-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8			// CHECK10-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8
	// CHECK10-NEXT: store i64 [[G]], i64* [[G_ADDR]], align 8			// CHECK10-NEXT: store i64 [[G]], i64* [[G_ADDR]], align 8
	// CHECK10-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8			// CHECK10-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8
	// CHECK10-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8			// CHECK10-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8
	// CHECK10-NEXT: [[CONV:%.]] = bitcast i64 [[G_ADDR]] to i32*			// CHECK10-NEXT: [[CONV:%.]] = bitcast i64 [[G_ADDR]] to i32*
	// CHECK10-NEXT: [[CONV1:%.]] = bitcast i64 [[SIVAR_ADDR]] to i32*			// CHECK10-NEXT: [[CONV1:%.]] = bitcast i64 [[SIVAR_ADDR]] to i32*
	// CHECK10-NEXT: [[CONV2:%.]] = bitcast i64 [[G1_ADDR]] to i32*			// CHECK10-NEXT: [[CONV2:%.]] = bitcast i64 [[G1_ADDR]] to i32*
	// CHECK10-NEXT: store i32* [[CONV2]], i32** [[TMP]], align 8			// CHECK10-NEXT: store i32* [[CONV2]], i32** [[TMP]], align 8
	// CHECK10-NEXT: [[TMP0:%.]] = load i32, i32 [[CONV]], align 4			// CHECK10-NEXT: [[TMP0:%.]] = load i32, i32 [[CONV]], align 8
	// CHECK10-NEXT: [[CONV3:%.]] = bitcast i64 [[G_CASTED]] to i32*			// CHECK10-NEXT: [[CONV3:%.]] = bitcast i64 [[G_CASTED]] to i32*
	// CHECK10-NEXT: store i32 [[TMP0]], i32* [[CONV3]], align 4			// CHECK10-NEXT: store i32 [[TMP0]], i32* [[CONV3]], align 4
	// CHECK10-NEXT: [[TMP1:%.]] = load i64, i64 [[G_CASTED]], align 8			// CHECK10-NEXT: [[TMP1:%.]] = load i64, i64 [[G_CASTED]], align 8
	// CHECK10-NEXT: [[TMP2:%.]] = load i32, i32** [[TMP]], align 8			// CHECK10-NEXT: [[TMP2:%.]] = load i32, i32** [[TMP]], align 8
	// CHECK10-NEXT: [[TMP3:%.]] = load volatile i32, i32 [[TMP2]], align 4			// CHECK10-NEXT: [[TMP3:%.]] = load volatile i32, i32 [[TMP2]], align 4
	// CHECK10-NEXT: [[CONV4:%.]] = bitcast i64 [[G1_CASTED]] to i32*			// CHECK10-NEXT: [[CONV4:%.]] = bitcast i64 [[G1_CASTED]] to i32*
	// CHECK10-NEXT: store i32 [[TMP3]], i32* [[CONV4]], align 4			// CHECK10-NEXT: store i32 [[TMP3]], i32* [[CONV4]], align 4
	// CHECK10-NEXT: [[TMP4:%.]] = load i64, i64 [[G1_CASTED]], align 8			// CHECK10-NEXT: [[TMP4:%.]] = load i64, i64 [[G1_CASTED]], align 8
	// CHECK10-NEXT: [[TMP5:%.]] = load i32, i32 [[CONV1]], align 4			// CHECK10-NEXT: [[TMP5:%.]] = load i32, i32 [[CONV1]], align 8
	// CHECK10-NEXT: [[CONV5:%.]] = bitcast i64 [[SIVAR_CASTED]] to i32*			// CHECK10-NEXT: [[CONV5:%.]] = bitcast i64 [[SIVAR_CASTED]] to i32*
	// CHECK10-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4			// CHECK10-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4
	// CHECK10-NEXT: [[TMP6:%.]] = load i64, i64 [[SIVAR_CASTED]], align 8			// CHECK10-NEXT: [[TMP6:%.]] = load i64, i64 [[SIVAR_CASTED]], align 8
	// CHECK10-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i64)* @.omp_outlined. to void (i32, i32, ...)*), i64 [[TMP1]], i64 [[TMP4]], i64 [[TMP6]])			// CHECK10-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i64)* @.omp_outlined. to void (i32, i32, ...)*), i64 [[TMP1]], i64 [[TMP4]], i64 [[TMP6]])
	// CHECK10-NEXT: ret void			// CHECK10-NEXT: ret void
	//			//
	//			//
	// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined.			// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined.
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	// CHECK10-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !4			// CHECK10-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !4
	// CHECK10-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK10-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK10-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK10-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK10: omp.inner.for.body:			// CHECK10: omp.inner.for.body:
	// CHECK10-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !4			// CHECK10-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !4
	// CHECK10-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64			// CHECK10-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
	// CHECK10-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !4			// CHECK10-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !4
	// CHECK10-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK10-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK10-NEXT: [[TMP11:%.]] = load i32, i32 [[CONV]], align 4, !llvm.access.group !4			// CHECK10-NEXT: [[TMP11:%.]] = load i32, i32 [[CONV]], align 8, !llvm.access.group !4
	// CHECK10-NEXT: [[CONV5:%.]] = bitcast i64 [[G_CASTED]] to i32*			// CHECK10-NEXT: [[CONV5:%.]] = bitcast i64 [[G_CASTED]] to i32*
	// CHECK10-NEXT: store i32 [[TMP11]], i32* [[CONV5]], align 4, !llvm.access.group !4			// CHECK10-NEXT: store i32 [[TMP11]], i32* [[CONV5]], align 4, !llvm.access.group !4
	// CHECK10-NEXT: [[TMP12:%.]] = load i64, i64 [[G_CASTED]], align 8, !llvm.access.group !4			// CHECK10-NEXT: [[TMP12:%.]] = load i64, i64 [[G_CASTED]], align 8, !llvm.access.group !4
	// CHECK10-NEXT: [[TMP13:%.]] = load i32, i32** [[TMP]], align 8, !llvm.access.group !4			// CHECK10-NEXT: [[TMP13:%.]] = load i32, i32** [[TMP]], align 8, !llvm.access.group !4
	// CHECK10-NEXT: [[TMP14:%.]] = load volatile i32, i32 [[TMP13]], align 4, !llvm.access.group !4			// CHECK10-NEXT: [[TMP14:%.]] = load volatile i32, i32 [[TMP13]], align 4, !llvm.access.group !4
	// CHECK10-NEXT: [[CONV6:%.]] = bitcast i64 [[G1_CASTED]] to i32*			// CHECK10-NEXT: [[CONV6:%.]] = bitcast i64 [[G1_CASTED]] to i32*
	// CHECK10-NEXT: store i32 [[TMP14]], i32* [[CONV6]], align 4, !llvm.access.group !4			// CHECK10-NEXT: store i32 [[TMP14]], i32* [[CONV6]], align 4, !llvm.access.group !4
	// CHECK10-NEXT: [[TMP15:%.]] = load i64, i64 [[G1_CASTED]], align 8, !llvm.access.group !4			// CHECK10-NEXT: [[TMP15:%.]] = load i64, i64 [[G1_CASTED]], align 8, !llvm.access.group !4
	// CHECK10-NEXT: [[TMP16:%.]] = load i32, i32 [[CONV2]], align 4, !llvm.access.group !4			// CHECK10-NEXT: [[TMP16:%.]] = load i32, i32 [[CONV2]], align 8, !llvm.access.group !4
	// CHECK10-NEXT: [[CONV7:%.]] = bitcast i64 [[SIVAR_CASTED]] to i32*			// CHECK10-NEXT: [[CONV7:%.]] = bitcast i64 [[SIVAR_CASTED]] to i32*
	// CHECK10-NEXT: store i32 [[TMP16]], i32* [[CONV7]], align 4, !llvm.access.group !4			// CHECK10-NEXT: store i32 [[TMP16]], i32* [[CONV7]], align 4, !llvm.access.group !4
	// CHECK10-NEXT: [[TMP17:%.]] = load i64, i64 [[SIVAR_CASTED]], align 8, !llvm.access.group !4			// CHECK10-NEXT: [[TMP17:%.]] = load i64, i64 [[SIVAR_CASTED]], align 8, !llvm.access.group !4
	// CHECK10-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i64, i64, i64)* @.omp_outlined..3 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]], i64 [[TMP12]], i64 [[TMP15]], i64 [[TMP17]]), !llvm.access.group !4			// CHECK10-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i64, i64, i64)* @.omp_outlined..3 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]], i64 [[TMP12]], i64 [[TMP15]], i64 [[TMP17]]), !llvm.access.group !4
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK10: omp.inner.for.inc:			// CHECK10: omp.inner.for.inc:
	// CHECK10-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !4			// CHECK10-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !4
	// CHECK10-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !4			// CHECK10-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !4
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	// CHECK10-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !8			// CHECK10-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !8
	// CHECK10-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK10-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK10-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK10-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK10: omp.inner.for.body:			// CHECK10: omp.inner.for.body:
	// CHECK10-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !8			// CHECK10-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !8
	// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !8			// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !8
	// CHECK10-NEXT: store i32 1, i32* [[CONV]], align 4, !llvm.access.group !8			// CHECK10-NEXT: store i32 1, i32* [[CONV]], align 8, !llvm.access.group !8
	// CHECK10-NEXT: [[TMP10:%.]] = load i32, i32** [[TMP]], align 8, !llvm.access.group !8			// CHECK10-NEXT: [[TMP10:%.]] = load i32, i32** [[TMP]], align 8, !llvm.access.group !8
	// CHECK10-NEXT: store volatile i32 1, i32* [[TMP10]], align 4, !llvm.access.group !8			// CHECK10-NEXT: store volatile i32 1, i32* [[TMP10]], align 4, !llvm.access.group !8
	// CHECK10-NEXT: store i32 2, i32* [[CONV2]], align 4, !llvm.access.group !8			// CHECK10-NEXT: store i32 2, i32* [[CONV2]], align 8, !llvm.access.group !8
	// CHECK10-NEXT: [[TMP11:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 0			// CHECK10-NEXT: [[TMP11:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 0
	// CHECK10-NEXT: store i32* [[CONV]], i32** [[TMP11]], align 8, !llvm.access.group !8			// CHECK10-NEXT: store i32* [[CONV]], i32** [[TMP11]], align 8, !llvm.access.group !8
	// CHECK10-NEXT: [[TMP12:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 1			// CHECK10-NEXT: [[TMP12:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 1
	// CHECK10-NEXT: [[TMP13:%.]] = load i32, i32** [[TMP]], align 8, !llvm.access.group !8			// CHECK10-NEXT: [[TMP13:%.]] = load i32, i32** [[TMP]], align 8, !llvm.access.group !8
	// CHECK10-NEXT: store i32* [[TMP13]], i32** [[TMP12]], align 8, !llvm.access.group !8			// CHECK10-NEXT: store i32* [[TMP13]], i32** [[TMP12]], align 8, !llvm.access.group !8
	// CHECK10-NEXT: [[TMP14:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 2			// CHECK10-NEXT: [[TMP14:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 2
	// CHECK10-NEXT: store i32* [[CONV2]], i32** [[TMP14]], align 8, !llvm.access.group !8			// CHECK10-NEXT: store i32* [[CONV2]], i32** [[TMP14]], align 8, !llvm.access.group !8
	// CHECK10-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(24) [[REF_TMP]]), !llvm.access.group !8			// CHECK10-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(24) [[REF_TMP]]), !llvm.access.group !8
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clang/test/OpenMP/teams_distribute_parallel_for_simd_if_codegen.cpp

This file is larger than 256 KB, so syntax highlighting is disabled by default.

	Show First 20 Lines • Show All 816 Lines • ▼ Show 20 Lines
	// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92			// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92
	// CHECK1-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] {			// CHECK1-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] {
	// CHECK1-NEXT: entry:			// CHECK1-NEXT: entry:
	// CHECK1-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8			// CHECK1-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8
	// CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1			// CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
	// CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8			// CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
	// CHECK1-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8			// CHECK1-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8
	// CHECK1-NEXT: [[CONV:%.]] = bitcast i64 [[ARG_ADDR]] to i32*			// CHECK1-NEXT: [[CONV:%.]] = bitcast i64 [[ARG_ADDR]] to i32*
	// CHECK1-NEXT: [[TMP0:%.]] = load i32, i32 [[CONV]], align 4			// CHECK1-NEXT: [[TMP0:%.]] = load i32, i32 [[CONV]], align 8
	// CHECK1-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0			// CHECK1-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0
	// CHECK1-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8			// CHECK1-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
	// CHECK1-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1			// CHECK1-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
	// CHECK1-NEXT: [[TMP1:%.]] = load i8, i8 [[DOTCAPTURE_EXPR_]], align 1			// CHECK1-NEXT: [[TMP1:%.]] = load i8, i8 [[DOTCAPTURE_EXPR_]], align 1
	// CHECK1-NEXT: [[TOBOOL1:%.*]] = trunc i8 [[TMP1]] to i1			// CHECK1-NEXT: [[TOBOOL1:%.*]] = trunc i8 [[TMP1]] to i1
	// CHECK1-NEXT: [[CONV2:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED]] to i8*			// CHECK1-NEXT: [[CONV2:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED]] to i8*
	// CHECK1-NEXT: [[FROMBOOL3:%.*]] = zext i1 [[TOBOOL1]] to i8			// CHECK1-NEXT: [[FROMBOOL3:%.*]] = zext i1 [[TOBOOL1]] to i8
	// CHECK1-NEXT: store i8 [[FROMBOOL3]], i8* [[CONV2]], align 1			// CHECK1-NEXT: store i8 [[FROMBOOL3]], i8* [[CONV2]], align 1
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	// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !38			// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !38
	// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK1: omp.inner.for.body:			// CHECK1: omp.inner.for.body:
	// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !38			// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !38
	// CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64			// CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
	// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !38			// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !38
	// CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK1-NEXT: [[TMP11:%.]] = load i8, i8 [[CONV]], align 1, !llvm.access.group !38			// CHECK1-NEXT: [[TMP11:%.]] = load i8, i8 [[CONV]], align 8, !llvm.access.group !38
	// CHECK1-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1			// CHECK1-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
	// CHECK1-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE:%.]]			// CHECK1-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE:%.]]
	// CHECK1: omp_if.then:			// CHECK1: omp_if.then:
	// CHECK1-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..9 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !38			// CHECK1-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..9 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !38
	// CHECK1-NEXT: br label [[OMP_IF_END:%.*]]			// CHECK1-NEXT: br label [[OMP_IF_END:%.*]]
	// CHECK1: omp_if.else:			// CHECK1: omp_if.else:
	// CHECK1-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !38			// CHECK1-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !38
	// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !38			// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !38
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	// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l67			// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l67
	// CHECK1-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] {			// CHECK1-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] {
	// CHECK1-NEXT: entry:			// CHECK1-NEXT: entry:
	// CHECK1-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8			// CHECK1-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8
	// CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1			// CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
	// CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8			// CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
	// CHECK1-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8			// CHECK1-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8
	// CHECK1-NEXT: [[CONV:%.]] = bitcast i64 [[ARG_ADDR]] to i32*			// CHECK1-NEXT: [[CONV:%.]] = bitcast i64 [[ARG_ADDR]] to i32*
	// CHECK1-NEXT: [[TMP0:%.]] = load i32, i32 [[CONV]], align 4			// CHECK1-NEXT: [[TMP0:%.]] = load i32, i32 [[CONV]], align 8
	// CHECK1-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0			// CHECK1-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0
	// CHECK1-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8			// CHECK1-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
	// CHECK1-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1			// CHECK1-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
	// CHECK1-NEXT: [[TMP1:%.]] = load i8, i8 [[DOTCAPTURE_EXPR_]], align 1			// CHECK1-NEXT: [[TMP1:%.]] = load i8, i8 [[DOTCAPTURE_EXPR_]], align 1
	// CHECK1-NEXT: [[TOBOOL1:%.*]] = trunc i8 [[TMP1]] to i1			// CHECK1-NEXT: [[TOBOOL1:%.*]] = trunc i8 [[TMP1]] to i1
	// CHECK1-NEXT: [[CONV2:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED]] to i8*			// CHECK1-NEXT: [[CONV2:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED]] to i8*
	// CHECK1-NEXT: [[FROMBOOL3:%.*]] = zext i1 [[TOBOOL1]] to i8			// CHECK1-NEXT: [[FROMBOOL3:%.*]] = zext i1 [[TOBOOL1]] to i8
	// CHECK1-NEXT: store i8 [[FROMBOOL3]], i8* [[CONV2]], align 1			// CHECK1-NEXT: store i8 [[FROMBOOL3]], i8* [[CONV2]], align 1
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	// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !56			// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !56
	// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK1: omp.inner.for.body:			// CHECK1: omp.inner.for.body:
	// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !56			// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !56
	// CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64			// CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
	// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !56			// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !56
	// CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK1-NEXT: [[TMP11:%.]] = load i8, i8 [[CONV]], align 1, !llvm.access.group !56			// CHECK1-NEXT: [[TMP11:%.]] = load i8, i8 [[CONV]], align 8, !llvm.access.group !56
	// CHECK1-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1			// CHECK1-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
	// CHECK1-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE:%.]]			// CHECK1-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE:%.]]
	// CHECK1: omp_if.then:			// CHECK1: omp_if.then:
	// CHECK1-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..15 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !56			// CHECK1-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..15 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !56
	// CHECK1-NEXT: br label [[OMP_IF_END:%.*]]			// CHECK1-NEXT: br label [[OMP_IF_END:%.*]]
	// CHECK1: omp_if.else:			// CHECK1: omp_if.else:
	// CHECK1-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !56			// CHECK1-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !56
	// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !56			// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !56
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	// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92			// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92
	// CHECK2-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] {			// CHECK2-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	// CHECK2-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8			// CHECK2-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8
	// CHECK2-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1			// CHECK2-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
	// CHECK2-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8			// CHECK2-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
	// CHECK2-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8			// CHECK2-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8
	// CHECK2-NEXT: [[CONV:%.]] = bitcast i64 [[ARG_ADDR]] to i32*			// CHECK2-NEXT: [[CONV:%.]] = bitcast i64 [[ARG_ADDR]] to i32*
	// CHECK2-NEXT: [[TMP0:%.]] = load i32, i32 [[CONV]], align 4			// CHECK2-NEXT: [[TMP0:%.]] = load i32, i32 [[CONV]], align 8
	// CHECK2-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0			// CHECK2-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0
	// CHECK2-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8			// CHECK2-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
	// CHECK2-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1			// CHECK2-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
	// CHECK2-NEXT: [[TMP1:%.]] = load i8, i8 [[DOTCAPTURE_EXPR_]], align 1			// CHECK2-NEXT: [[TMP1:%.]] = load i8, i8 [[DOTCAPTURE_EXPR_]], align 1
	// CHECK2-NEXT: [[TOBOOL1:%.*]] = trunc i8 [[TMP1]] to i1			// CHECK2-NEXT: [[TOBOOL1:%.*]] = trunc i8 [[TMP1]] to i1
	// CHECK2-NEXT: [[CONV2:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED]] to i8*			// CHECK2-NEXT: [[CONV2:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED]] to i8*
	// CHECK2-NEXT: [[FROMBOOL3:%.*]] = zext i1 [[TOBOOL1]] to i8			// CHECK2-NEXT: [[FROMBOOL3:%.*]] = zext i1 [[TOBOOL1]] to i8
	// CHECK2-NEXT: store i8 [[FROMBOOL3]], i8* [[CONV2]], align 1			// CHECK2-NEXT: store i8 [[FROMBOOL3]], i8* [[CONV2]], align 1
	▲ Show 20 Lines • Show All 46 Lines • ▼ Show 20 Lines
	// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !38			// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !38
	// CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK2: omp.inner.for.body:			// CHECK2: omp.inner.for.body:
	// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !38			// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !38
	// CHECK2-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64			// CHECK2-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
	// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !38			// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !38
	// CHECK2-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK2-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK2-NEXT: [[TMP11:%.]] = load i8, i8 [[CONV]], align 1, !llvm.access.group !38			// CHECK2-NEXT: [[TMP11:%.]] = load i8, i8 [[CONV]], align 8, !llvm.access.group !38
	// CHECK2-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1			// CHECK2-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
	// CHECK2-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE:%.]]			// CHECK2-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE:%.]]
	// CHECK2: omp_if.then:			// CHECK2: omp_if.then:
	// CHECK2-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..9 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !38			// CHECK2-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..9 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !38
	// CHECK2-NEXT: br label [[OMP_IF_END:%.*]]			// CHECK2-NEXT: br label [[OMP_IF_END:%.*]]
	// CHECK2: omp_if.else:			// CHECK2: omp_if.else:
	// CHECK2-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !38			// CHECK2-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !38
	// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !38			// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !38
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	// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l67			// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l67
	// CHECK2-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] {			// CHECK2-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	// CHECK2-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8			// CHECK2-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8
	// CHECK2-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1			// CHECK2-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
	// CHECK2-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8			// CHECK2-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
	// CHECK2-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8			// CHECK2-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8
	// CHECK2-NEXT: [[CONV:%.]] = bitcast i64 [[ARG_ADDR]] to i32*			// CHECK2-NEXT: [[CONV:%.]] = bitcast i64 [[ARG_ADDR]] to i32*
	// CHECK2-NEXT: [[TMP0:%.]] = load i32, i32 [[CONV]], align 4			// CHECK2-NEXT: [[TMP0:%.]] = load i32, i32 [[CONV]], align 8
	// CHECK2-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0			// CHECK2-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0
	// CHECK2-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8			// CHECK2-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
	// CHECK2-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1			// CHECK2-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
	// CHECK2-NEXT: [[TMP1:%.]] = load i8, i8 [[DOTCAPTURE_EXPR_]], align 1			// CHECK2-NEXT: [[TMP1:%.]] = load i8, i8 [[DOTCAPTURE_EXPR_]], align 1
	// CHECK2-NEXT: [[TOBOOL1:%.*]] = trunc i8 [[TMP1]] to i1			// CHECK2-NEXT: [[TOBOOL1:%.*]] = trunc i8 [[TMP1]] to i1
	// CHECK2-NEXT: [[CONV2:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED]] to i8*			// CHECK2-NEXT: [[CONV2:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED]] to i8*
	// CHECK2-NEXT: [[FROMBOOL3:%.*]] = zext i1 [[TOBOOL1]] to i8			// CHECK2-NEXT: [[FROMBOOL3:%.*]] = zext i1 [[TOBOOL1]] to i8
	// CHECK2-NEXT: store i8 [[FROMBOOL3]], i8* [[CONV2]], align 1			// CHECK2-NEXT: store i8 [[FROMBOOL3]], i8* [[CONV2]], align 1
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	// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !56			// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !56
	// CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK2: omp.inner.for.body:			// CHECK2: omp.inner.for.body:
	// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !56			// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !56
	// CHECK2-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64			// CHECK2-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
	// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !56			// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !56
	// CHECK2-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK2-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK2-NEXT: [[TMP11:%.]] = load i8, i8 [[CONV]], align 1, !llvm.access.group !56			// CHECK2-NEXT: [[TMP11:%.]] = load i8, i8 [[CONV]], align 8, !llvm.access.group !56
	// CHECK2-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1			// CHECK2-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
	// CHECK2-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE:%.]]			// CHECK2-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE:%.]]
	// CHECK2: omp_if.then:			// CHECK2: omp_if.then:
	// CHECK2-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..15 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !56			// CHECK2-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..15 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !56
	// CHECK2-NEXT: br label [[OMP_IF_END:%.*]]			// CHECK2-NEXT: br label [[OMP_IF_END:%.*]]
	// CHECK2: omp_if.else:			// CHECK2: omp_if.else:
	// CHECK2-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !56			// CHECK2-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !56
	// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !56			// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !56
	▲ Show 20 Lines • Show All 815 Lines • ▼ Show 20 Lines
	// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92			// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92
	// CHECK3-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] {			// CHECK3-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] {
	// CHECK3-NEXT: entry:			// CHECK3-NEXT: entry:
	// CHECK3-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8			// CHECK3-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8
	// CHECK3-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1			// CHECK3-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
	// CHECK3-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8			// CHECK3-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
	// CHECK3-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8			// CHECK3-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8
	// CHECK3-NEXT: [[CONV:%.]] = bitcast i64 [[ARG_ADDR]] to i32*			// CHECK3-NEXT: [[CONV:%.]] = bitcast i64 [[ARG_ADDR]] to i32*
	// CHECK3-NEXT: [[TMP0:%.]] = load i32, i32 [[CONV]], align 4			// CHECK3-NEXT: [[TMP0:%.]] = load i32, i32 [[CONV]], align 8
	// CHECK3-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0			// CHECK3-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0
	// CHECK3-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8			// CHECK3-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
	// CHECK3-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1			// CHECK3-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
	// CHECK3-NEXT: [[TMP1:%.]] = load i8, i8 [[DOTCAPTURE_EXPR_]], align 1			// CHECK3-NEXT: [[TMP1:%.]] = load i8, i8 [[DOTCAPTURE_EXPR_]], align 1
	// CHECK3-NEXT: [[TOBOOL1:%.*]] = trunc i8 [[TMP1]] to i1			// CHECK3-NEXT: [[TOBOOL1:%.*]] = trunc i8 [[TMP1]] to i1
	// CHECK3-NEXT: [[CONV2:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED]] to i8*			// CHECK3-NEXT: [[CONV2:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED]] to i8*
	// CHECK3-NEXT: [[FROMBOOL3:%.*]] = zext i1 [[TOBOOL1]] to i8			// CHECK3-NEXT: [[FROMBOOL3:%.*]] = zext i1 [[TOBOOL1]] to i8
	// CHECK3-NEXT: store i8 [[FROMBOOL3]], i8* [[CONV2]], align 1			// CHECK3-NEXT: store i8 [[FROMBOOL3]], i8* [[CONV2]], align 1
	Show All 38 Lines
	// CHECK3: cond.false:			// CHECK3: cond.false:
	// CHECK3-NEXT: [[TMP3:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK3-NEXT: [[TMP3:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4
	// CHECK3-NEXT: br label [[COND_END]]			// CHECK3-NEXT: br label [[COND_END]]
	// CHECK3: cond.end:			// CHECK3: cond.end:
	// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]			// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
	// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK3-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK3-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK3-NEXT: [[TMP5:%.]] = load i8, i8 [[CONV]], align 1			// CHECK3-NEXT: [[TMP5:%.]] = load i8, i8 [[CONV]], align 8
	// CHECK3-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP5]] to i1			// CHECK3-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP5]] to i1
	// CHECK3-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE6:%.]]			// CHECK3-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE6:%.]]
	// CHECK3: omp_if.then:			// CHECK3: omp_if.then:
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK3: omp.inner.for.cond:			// CHECK3: omp.inner.for.cond:
	// CHECK3-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !35			// CHECK3-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !35
	// CHECK3-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !35			// CHECK3-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !35
	// CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK3: omp.inner.for.body:			// CHECK3: omp.inner.for.body:
	// CHECK3-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !35			// CHECK3-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !35
	// CHECK3-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64			// CHECK3-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
	// CHECK3-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !35			// CHECK3-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !35
	// CHECK3-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64			// CHECK3-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
	// CHECK3-NEXT: [[TMP12:%.]] = load i8, i8 [[CONV]], align 1, !llvm.access.group !35			// CHECK3-NEXT: [[TMP12:%.]] = load i8, i8 [[CONV]], align 8, !llvm.access.group !35
	// CHECK3-NEXT: [[TOBOOL2:%.*]] = trunc i8 [[TMP12]] to i1			// CHECK3-NEXT: [[TOBOOL2:%.*]] = trunc i8 [[TMP12]] to i1
	// CHECK3-NEXT: [[CONV3:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED]] to i8*			// CHECK3-NEXT: [[CONV3:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED]] to i8*
	// CHECK3-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL2]] to i8			// CHECK3-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL2]] to i8
	// CHECK3-NEXT: store i8 [[FROMBOOL]], i8* [[CONV3]], align 1, !llvm.access.group !35			// CHECK3-NEXT: store i8 [[FROMBOOL]], i8* [[CONV3]], align 1, !llvm.access.group !35
	// CHECK3-NEXT: [[TMP13:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !35			// CHECK3-NEXT: [[TMP13:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !35
	// CHECK3-NEXT: [[TMP14:%.]] = load i8, i8 [[CONV]], align 1, !llvm.access.group !35			// CHECK3-NEXT: [[TMP14:%.]] = load i8, i8 [[CONV]], align 8, !llvm.access.group !35
	// CHECK3-NEXT: [[TOBOOL4:%.*]] = trunc i8 [[TMP14]] to i1			// CHECK3-NEXT: [[TOBOOL4:%.*]] = trunc i8 [[TMP14]] to i1
	// CHECK3-NEXT: br i1 [[TOBOOL4]], label [[OMP_IF_THEN5:%.]], label [[OMP_IF_ELSE:%.]]			// CHECK3-NEXT: br i1 [[TOBOOL4]], label [[OMP_IF_THEN5:%.]], label [[OMP_IF_ELSE:%.]]
	// CHECK3: omp_if.then5:			// CHECK3: omp_if.then5:
	// CHECK3-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i64)* @.omp_outlined..9 to void (i32, i32, ...)*), i64 [[TMP9]], i64 [[TMP11]], i64 [[TMP13]]), !llvm.access.group !35			// CHECK3-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i64)* @.omp_outlined..9 to void (i32, i32, ...)*), i64 [[TMP9]], i64 [[TMP11]], i64 [[TMP13]]), !llvm.access.group !35
	// CHECK3-NEXT: br label [[OMP_IF_END:%.*]]			// CHECK3-NEXT: br label [[OMP_IF_END:%.*]]
	// CHECK3: omp_if.else:			// CHECK3: omp_if.else:
	// CHECK3-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !35			// CHECK3-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !35
	// CHECK3-NEXT: [[TMP15:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !35			// CHECK3-NEXT: [[TMP15:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !35
	Show All 18 Lines
	// CHECK3-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK3-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4
	// CHECK3-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP18]], [[TMP19]]			// CHECK3-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP18]], [[TMP19]]
	// CHECK3-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY9:%.]], label [[OMP_INNER_FOR_END21:%.]]			// CHECK3-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY9:%.]], label [[OMP_INNER_FOR_END21:%.]]
	// CHECK3: omp.inner.for.body9:			// CHECK3: omp.inner.for.body9:
	// CHECK3-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK3-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK3-NEXT: [[TMP21:%.*]] = zext i32 [[TMP20]] to i64			// CHECK3-NEXT: [[TMP21:%.*]] = zext i32 [[TMP20]] to i64
	// CHECK3-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK3-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4
	// CHECK3-NEXT: [[TMP23:%.*]] = zext i32 [[TMP22]] to i64			// CHECK3-NEXT: [[TMP23:%.*]] = zext i32 [[TMP22]] to i64
	// CHECK3-NEXT: [[TMP24:%.]] = load i8, i8 [[CONV]], align 1			// CHECK3-NEXT: [[TMP24:%.]] = load i8, i8 [[CONV]], align 8
	// CHECK3-NEXT: [[TOBOOL10:%.*]] = trunc i8 [[TMP24]] to i1			// CHECK3-NEXT: [[TOBOOL10:%.*]] = trunc i8 [[TMP24]] to i1
	// CHECK3-NEXT: [[CONV12:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED11]] to i8*			// CHECK3-NEXT: [[CONV12:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED11]] to i8*
	// CHECK3-NEXT: [[FROMBOOL13:%.*]] = zext i1 [[TOBOOL10]] to i8			// CHECK3-NEXT: [[FROMBOOL13:%.*]] = zext i1 [[TOBOOL10]] to i8
	// CHECK3-NEXT: store i8 [[FROMBOOL13]], i8* [[CONV12]], align 1			// CHECK3-NEXT: store i8 [[FROMBOOL13]], i8* [[CONV12]], align 1
	// CHECK3-NEXT: [[TMP25:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED11]], align 8			// CHECK3-NEXT: [[TMP25:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED11]], align 8
	// CHECK3-NEXT: [[TMP26:%.]] = load i8, i8 [[CONV]], align 1			// CHECK3-NEXT: [[TMP26:%.]] = load i8, i8 [[CONV]], align 8
	// CHECK3-NEXT: [[TOBOOL14:%.*]] = trunc i8 [[TMP26]] to i1			// CHECK3-NEXT: [[TOBOOL14:%.*]] = trunc i8 [[TMP26]] to i1
	// CHECK3-NEXT: br i1 [[TOBOOL14]], label [[OMP_IF_THEN15:%.]], label [[OMP_IF_ELSE16:%.]]			// CHECK3-NEXT: br i1 [[TOBOOL14]], label [[OMP_IF_THEN15:%.]], label [[OMP_IF_ELSE16:%.]]
	// CHECK3: omp_if.then15:			// CHECK3: omp_if.then15:
	// CHECK3-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i64)* @.omp_outlined..10 to void (i32, i32, ...)*), i64 [[TMP21]], i64 [[TMP23]], i64 [[TMP25]])			// CHECK3-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i64)* @.omp_outlined..10 to void (i32, i32, ...)*), i64 [[TMP21]], i64 [[TMP23]], i64 [[TMP25]])
	// CHECK3-NEXT: br label [[OMP_IF_END18:%.*]]			// CHECK3-NEXT: br label [[OMP_IF_END18:%.*]]
	// CHECK3: omp_if.else16:			// CHECK3: omp_if.else16:
	// CHECK3-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]])			// CHECK3-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]])
	// CHECK3-NEXT: [[TMP27:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK3-NEXT: [[TMP27:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
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	// CHECK3-NEXT: [[TMP0:%.]] = load i64, i64 [[DOTPREVIOUS_LB__ADDR]], align 8			// CHECK3-NEXT: [[TMP0:%.]] = load i64, i64 [[DOTPREVIOUS_LB__ADDR]], align 8
	// CHECK3-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP0]] to i32			// CHECK3-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP0]] to i32
	// CHECK3-NEXT: [[TMP1:%.]] = load i64, i64 [[DOTPREVIOUS_UB__ADDR]], align 8			// CHECK3-NEXT: [[TMP1:%.]] = load i64, i64 [[DOTPREVIOUS_UB__ADDR]], align 8
	// CHECK3-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32			// CHECK3-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32
	// CHECK3-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4			// CHECK3-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4
	// CHECK3-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4			// CHECK3-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4
	// CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4			// CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
	// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4			// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
	// CHECK3-NEXT: [[TMP2:%.]] = load i8, i8 [[CONV]], align 1			// CHECK3-NEXT: [[TMP2:%.]] = load i8, i8 [[CONV]], align 8
	// CHECK3-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1			// CHECK3-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1
	// CHECK3-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE:%.]]			// CHECK3-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE:%.]]
	// CHECK3: omp_if.then:			// CHECK3: omp_if.then:
	// CHECK3-NEXT: [[TMP3:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK3-NEXT: [[TMP3:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK3-NEXT: [[TMP4:%.]] = load i32, i32 [[TMP3]], align 4			// CHECK3-NEXT: [[TMP4:%.]] = load i32, i32 [[TMP3]], align 4
	// CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)			// CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
	// CHECK3-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK3-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 99			// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 99
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	// CHECK3-NEXT: [[TMP0:%.]] = load i64, i64 [[DOTPREVIOUS_LB__ADDR]], align 8			// CHECK3-NEXT: [[TMP0:%.]] = load i64, i64 [[DOTPREVIOUS_LB__ADDR]], align 8
	// CHECK3-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP0]] to i32			// CHECK3-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP0]] to i32
	// CHECK3-NEXT: [[TMP1:%.]] = load i64, i64 [[DOTPREVIOUS_UB__ADDR]], align 8			// CHECK3-NEXT: [[TMP1:%.]] = load i64, i64 [[DOTPREVIOUS_UB__ADDR]], align 8
	// CHECK3-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32			// CHECK3-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32
	// CHECK3-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4			// CHECK3-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4
	// CHECK3-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4			// CHECK3-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4
	// CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4			// CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
	// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4			// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
	// CHECK3-NEXT: [[TMP2:%.]] = load i8, i8 [[CONV]], align 1			// CHECK3-NEXT: [[TMP2:%.]] = load i8, i8 [[CONV]], align 8
	// CHECK3-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1			// CHECK3-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1
	// CHECK3-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE:%.]]			// CHECK3-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE:%.]]
	// CHECK3: omp_if.then:			// CHECK3: omp_if.then:
	// CHECK3-NEXT: [[TMP3:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK3-NEXT: [[TMP3:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK3-NEXT: [[TMP4:%.]] = load i32, i32 [[TMP3]], align 4			// CHECK3-NEXT: [[TMP4:%.]] = load i32, i32 [[TMP3]], align 4
	// CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)			// CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
	// CHECK3-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK3-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 99			// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 99
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	// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l67			// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l67
	// CHECK3-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] {			// CHECK3-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] {
	// CHECK3-NEXT: entry:			// CHECK3-NEXT: entry:
	// CHECK3-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8			// CHECK3-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8
	// CHECK3-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1			// CHECK3-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
	// CHECK3-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8			// CHECK3-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
	// CHECK3-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8			// CHECK3-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8
	// CHECK3-NEXT: [[CONV:%.]] = bitcast i64 [[ARG_ADDR]] to i32*			// CHECK3-NEXT: [[CONV:%.]] = bitcast i64 [[ARG_ADDR]] to i32*
	// CHECK3-NEXT: [[TMP0:%.]] = load i32, i32 [[CONV]], align 4			// CHECK3-NEXT: [[TMP0:%.]] = load i32, i32 [[CONV]], align 8
	// CHECK3-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0			// CHECK3-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0
	// CHECK3-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8			// CHECK3-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
	// CHECK3-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1			// CHECK3-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
	// CHECK3-NEXT: [[TMP1:%.]] = load i8, i8 [[DOTCAPTURE_EXPR_]], align 1			// CHECK3-NEXT: [[TMP1:%.]] = load i8, i8 [[DOTCAPTURE_EXPR_]], align 1
	// CHECK3-NEXT: [[TOBOOL1:%.*]] = trunc i8 [[TMP1]] to i1			// CHECK3-NEXT: [[TOBOOL1:%.*]] = trunc i8 [[TMP1]] to i1
	// CHECK3-NEXT: [[CONV2:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED]] to i8*			// CHECK3-NEXT: [[CONV2:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED]] to i8*
	// CHECK3-NEXT: [[FROMBOOL3:%.*]] = zext i1 [[TOBOOL1]] to i8			// CHECK3-NEXT: [[FROMBOOL3:%.*]] = zext i1 [[TOBOOL1]] to i8
	// CHECK3-NEXT: store i8 [[FROMBOOL3]], i8* [[CONV2]], align 1			// CHECK3-NEXT: store i8 [[FROMBOOL3]], i8* [[CONV2]], align 1
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	// CHECK3-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !55			// CHECK3-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !55
	// CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK3: omp.inner.for.body:			// CHECK3: omp.inner.for.body:
	// CHECK3-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !55			// CHECK3-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !55
	// CHECK3-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64			// CHECK3-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
	// CHECK3-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !55			// CHECK3-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !55
	// CHECK3-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK3-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK3-NEXT: [[TMP11:%.]] = load i8, i8 [[CONV]], align 1, !llvm.access.group !55			// CHECK3-NEXT: [[TMP11:%.]] = load i8, i8 [[CONV]], align 8, !llvm.access.group !55
	// CHECK3-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1			// CHECK3-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
	// CHECK3-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE:%.]]			// CHECK3-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE:%.]]
	// CHECK3: omp_if.then:			// CHECK3: omp_if.then:
	// CHECK3-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..16 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !55			// CHECK3-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..16 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !55
	// CHECK3-NEXT: br label [[OMP_IF_END:%.*]]			// CHECK3-NEXT: br label [[OMP_IF_END:%.*]]
	// CHECK3: omp_if.else:			// CHECK3: omp_if.else:
	// CHECK3-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !55			// CHECK3-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !55
	// CHECK3-NEXT: [[TMP12:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !55			// CHECK3-NEXT: [[TMP12:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !55
	▲ Show 20 Lines • Show All 815 Lines • ▼ Show 20 Lines
	// CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92			// CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92
	// CHECK4-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] {			// CHECK4-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] {
	// CHECK4-NEXT: entry:			// CHECK4-NEXT: entry:
	// CHECK4-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8			// CHECK4-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8
	// CHECK4-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1			// CHECK4-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
	// CHECK4-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8			// CHECK4-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
	// CHECK4-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8			// CHECK4-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8
	// CHECK4-NEXT: [[CONV:%.]] = bitcast i64 [[ARG_ADDR]] to i32*			// CHECK4-NEXT: [[CONV:%.]] = bitcast i64 [[ARG_ADDR]] to i32*
	// CHECK4-NEXT: [[TMP0:%.]] = load i32, i32 [[CONV]], align 4			// CHECK4-NEXT: [[TMP0:%.]] = load i32, i32 [[CONV]], align 8
	// CHECK4-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0			// CHECK4-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0
	// CHECK4-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8			// CHECK4-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
	// CHECK4-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1			// CHECK4-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
	// CHECK4-NEXT: [[TMP1:%.]] = load i8, i8 [[DOTCAPTURE_EXPR_]], align 1			// CHECK4-NEXT: [[TMP1:%.]] = load i8, i8 [[DOTCAPTURE_EXPR_]], align 1
	// CHECK4-NEXT: [[TOBOOL1:%.*]] = trunc i8 [[TMP1]] to i1			// CHECK4-NEXT: [[TOBOOL1:%.*]] = trunc i8 [[TMP1]] to i1
	// CHECK4-NEXT: [[CONV2:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED]] to i8*			// CHECK4-NEXT: [[CONV2:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED]] to i8*
	// CHECK4-NEXT: [[FROMBOOL3:%.*]] = zext i1 [[TOBOOL1]] to i8			// CHECK4-NEXT: [[FROMBOOL3:%.*]] = zext i1 [[TOBOOL1]] to i8
	// CHECK4-NEXT: store i8 [[FROMBOOL3]], i8* [[CONV2]], align 1			// CHECK4-NEXT: store i8 [[FROMBOOL3]], i8* [[CONV2]], align 1
	Show All 38 Lines
	// CHECK4: cond.false:			// CHECK4: cond.false:
	// CHECK4-NEXT: [[TMP3:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK4-NEXT: [[TMP3:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4
	// CHECK4-NEXT: br label [[COND_END]]			// CHECK4-NEXT: br label [[COND_END]]
	// CHECK4: cond.end:			// CHECK4: cond.end:
	// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]			// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
	// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK4-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK4-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK4-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK4-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK4-NEXT: [[TMP5:%.]] = load i8, i8 [[CONV]], align 1			// CHECK4-NEXT: [[TMP5:%.]] = load i8, i8 [[CONV]], align 8
	// CHECK4-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP5]] to i1			// CHECK4-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP5]] to i1
	// CHECK4-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE6:%.]]			// CHECK4-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE6:%.]]
	// CHECK4: omp_if.then:			// CHECK4: omp_if.then:
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK4: omp.inner.for.cond:			// CHECK4: omp.inner.for.cond:
	// CHECK4-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !35			// CHECK4-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !35
	// CHECK4-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !35			// CHECK4-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !35
	// CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK4: omp.inner.for.body:			// CHECK4: omp.inner.for.body:
	// CHECK4-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !35			// CHECK4-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !35
	// CHECK4-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64			// CHECK4-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
	// CHECK4-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !35			// CHECK4-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !35
	// CHECK4-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64			// CHECK4-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
	// CHECK4-NEXT: [[TMP12:%.]] = load i8, i8 [[CONV]], align 1, !llvm.access.group !35			// CHECK4-NEXT: [[TMP12:%.]] = load i8, i8 [[CONV]], align 8, !llvm.access.group !35
	// CHECK4-NEXT: [[TOBOOL2:%.*]] = trunc i8 [[TMP12]] to i1			// CHECK4-NEXT: [[TOBOOL2:%.*]] = trunc i8 [[TMP12]] to i1
	// CHECK4-NEXT: [[CONV3:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED]] to i8*			// CHECK4-NEXT: [[CONV3:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED]] to i8*
	// CHECK4-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL2]] to i8			// CHECK4-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL2]] to i8
	// CHECK4-NEXT: store i8 [[FROMBOOL]], i8* [[CONV3]], align 1, !llvm.access.group !35			// CHECK4-NEXT: store i8 [[FROMBOOL]], i8* [[CONV3]], align 1, !llvm.access.group !35
	// CHECK4-NEXT: [[TMP13:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !35			// CHECK4-NEXT: [[TMP13:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !35
	// CHECK4-NEXT: [[TMP14:%.]] = load i8, i8 [[CONV]], align 1, !llvm.access.group !35			// CHECK4-NEXT: [[TMP14:%.]] = load i8, i8 [[CONV]], align 8, !llvm.access.group !35
	// CHECK4-NEXT: [[TOBOOL4:%.*]] = trunc i8 [[TMP14]] to i1			// CHECK4-NEXT: [[TOBOOL4:%.*]] = trunc i8 [[TMP14]] to i1
	// CHECK4-NEXT: br i1 [[TOBOOL4]], label [[OMP_IF_THEN5:%.]], label [[OMP_IF_ELSE:%.]]			// CHECK4-NEXT: br i1 [[TOBOOL4]], label [[OMP_IF_THEN5:%.]], label [[OMP_IF_ELSE:%.]]
	// CHECK4: omp_if.then5:			// CHECK4: omp_if.then5:
	// CHECK4-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i64)* @.omp_outlined..9 to void (i32, i32, ...)*), i64 [[TMP9]], i64 [[TMP11]], i64 [[TMP13]]), !llvm.access.group !35			// CHECK4-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i64)* @.omp_outlined..9 to void (i32, i32, ...)*), i64 [[TMP9]], i64 [[TMP11]], i64 [[TMP13]]), !llvm.access.group !35
	// CHECK4-NEXT: br label [[OMP_IF_END:%.*]]			// CHECK4-NEXT: br label [[OMP_IF_END:%.*]]
	// CHECK4: omp_if.else:			// CHECK4: omp_if.else:
	// CHECK4-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !35			// CHECK4-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !35
	// CHECK4-NEXT: [[TMP15:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !35			// CHECK4-NEXT: [[TMP15:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !35
	Show All 18 Lines
	// CHECK4-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK4-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4
	// CHECK4-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP18]], [[TMP19]]			// CHECK4-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP18]], [[TMP19]]
	// CHECK4-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY9:%.]], label [[OMP_INNER_FOR_END21:%.]]			// CHECK4-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY9:%.]], label [[OMP_INNER_FOR_END21:%.]]
	// CHECK4: omp.inner.for.body9:			// CHECK4: omp.inner.for.body9:
	// CHECK4-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK4-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK4-NEXT: [[TMP21:%.*]] = zext i32 [[TMP20]] to i64			// CHECK4-NEXT: [[TMP21:%.*]] = zext i32 [[TMP20]] to i64
	// CHECK4-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK4-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4
	// CHECK4-NEXT: [[TMP23:%.*]] = zext i32 [[TMP22]] to i64			// CHECK4-NEXT: [[TMP23:%.*]] = zext i32 [[TMP22]] to i64
	// CHECK4-NEXT: [[TMP24:%.]] = load i8, i8 [[CONV]], align 1			// CHECK4-NEXT: [[TMP24:%.]] = load i8, i8 [[CONV]], align 8
	// CHECK4-NEXT: [[TOBOOL10:%.*]] = trunc i8 [[TMP24]] to i1			// CHECK4-NEXT: [[TOBOOL10:%.*]] = trunc i8 [[TMP24]] to i1
	// CHECK4-NEXT: [[CONV12:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED11]] to i8*			// CHECK4-NEXT: [[CONV12:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED11]] to i8*
	// CHECK4-NEXT: [[FROMBOOL13:%.*]] = zext i1 [[TOBOOL10]] to i8			// CHECK4-NEXT: [[FROMBOOL13:%.*]] = zext i1 [[TOBOOL10]] to i8
	// CHECK4-NEXT: store i8 [[FROMBOOL13]], i8* [[CONV12]], align 1			// CHECK4-NEXT: store i8 [[FROMBOOL13]], i8* [[CONV12]], align 1
	// CHECK4-NEXT: [[TMP25:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED11]], align 8			// CHECK4-NEXT: [[TMP25:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED11]], align 8
	// CHECK4-NEXT: [[TMP26:%.]] = load i8, i8 [[CONV]], align 1			// CHECK4-NEXT: [[TMP26:%.]] = load i8, i8 [[CONV]], align 8
	// CHECK4-NEXT: [[TOBOOL14:%.*]] = trunc i8 [[TMP26]] to i1			// CHECK4-NEXT: [[TOBOOL14:%.*]] = trunc i8 [[TMP26]] to i1
	// CHECK4-NEXT: br i1 [[TOBOOL14]], label [[OMP_IF_THEN15:%.]], label [[OMP_IF_ELSE16:%.]]			// CHECK4-NEXT: br i1 [[TOBOOL14]], label [[OMP_IF_THEN15:%.]], label [[OMP_IF_ELSE16:%.]]
	// CHECK4: omp_if.then15:			// CHECK4: omp_if.then15:
	// CHECK4-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i64)* @.omp_outlined..10 to void (i32, i32, ...)*), i64 [[TMP21]], i64 [[TMP23]], i64 [[TMP25]])			// CHECK4-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i64)* @.omp_outlined..10 to void (i32, i32, ...)*), i64 [[TMP21]], i64 [[TMP23]], i64 [[TMP25]])
	// CHECK4-NEXT: br label [[OMP_IF_END18:%.*]]			// CHECK4-NEXT: br label [[OMP_IF_END18:%.*]]
	// CHECK4: omp_if.else16:			// CHECK4: omp_if.else16:
	// CHECK4-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]])			// CHECK4-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]])
	// CHECK4-NEXT: [[TMP27:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK4-NEXT: [[TMP27:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
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	// CHECK4-NEXT: [[TMP0:%.]] = load i64, i64 [[DOTPREVIOUS_LB__ADDR]], align 8			// CHECK4-NEXT: [[TMP0:%.]] = load i64, i64 [[DOTPREVIOUS_LB__ADDR]], align 8
	// CHECK4-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP0]] to i32			// CHECK4-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP0]] to i32
	// CHECK4-NEXT: [[TMP1:%.]] = load i64, i64 [[DOTPREVIOUS_UB__ADDR]], align 8			// CHECK4-NEXT: [[TMP1:%.]] = load i64, i64 [[DOTPREVIOUS_UB__ADDR]], align 8
	// CHECK4-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32			// CHECK4-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32
	// CHECK4-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4			// CHECK4-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4
	// CHECK4-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4			// CHECK4-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4
	// CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4			// CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
	// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4			// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
	// CHECK4-NEXT: [[TMP2:%.]] = load i8, i8 [[CONV]], align 1			// CHECK4-NEXT: [[TMP2:%.]] = load i8, i8 [[CONV]], align 8
	// CHECK4-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1			// CHECK4-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1
	// CHECK4-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE:%.]]			// CHECK4-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE:%.]]
	// CHECK4: omp_if.then:			// CHECK4: omp_if.then:
	// CHECK4-NEXT: [[TMP3:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK4-NEXT: [[TMP3:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK4-NEXT: [[TMP4:%.]] = load i32, i32 [[TMP3]], align 4			// CHECK4-NEXT: [[TMP4:%.]] = load i32, i32 [[TMP3]], align 4
	// CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)			// CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
	// CHECK4-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK4-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 99			// CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 99
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	// CHECK4-NEXT: [[TMP0:%.]] = load i64, i64 [[DOTPREVIOUS_LB__ADDR]], align 8			// CHECK4-NEXT: [[TMP0:%.]] = load i64, i64 [[DOTPREVIOUS_LB__ADDR]], align 8
	// CHECK4-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP0]] to i32			// CHECK4-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP0]] to i32
	// CHECK4-NEXT: [[TMP1:%.]] = load i64, i64 [[DOTPREVIOUS_UB__ADDR]], align 8			// CHECK4-NEXT: [[TMP1:%.]] = load i64, i64 [[DOTPREVIOUS_UB__ADDR]], align 8
	// CHECK4-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32			// CHECK4-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32
	// CHECK4-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4			// CHECK4-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4
	// CHECK4-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4			// CHECK4-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4
	// CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4			// CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
	// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4			// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
	// CHECK4-NEXT: [[TMP2:%.]] = load i8, i8 [[CONV]], align 1			// CHECK4-NEXT: [[TMP2:%.]] = load i8, i8 [[CONV]], align 8
	// CHECK4-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1			// CHECK4-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1
	// CHECK4-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE:%.]]			// CHECK4-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE:%.]]
	// CHECK4: omp_if.then:			// CHECK4: omp_if.then:
	// CHECK4-NEXT: [[TMP3:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK4-NEXT: [[TMP3:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK4-NEXT: [[TMP4:%.]] = load i32, i32 [[TMP3]], align 4			// CHECK4-NEXT: [[TMP4:%.]] = load i32, i32 [[TMP3]], align 4
	// CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)			// CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
	// CHECK4-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK4-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 99			// CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 99
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	// CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l67			// CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l67
	// CHECK4-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] {			// CHECK4-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] {
	// CHECK4-NEXT: entry:			// CHECK4-NEXT: entry:
	// CHECK4-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8			// CHECK4-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8
	// CHECK4-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1			// CHECK4-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
	// CHECK4-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8			// CHECK4-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
	// CHECK4-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8			// CHECK4-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8
	// CHECK4-NEXT: [[CONV:%.]] = bitcast i64 [[ARG_ADDR]] to i32*			// CHECK4-NEXT: [[CONV:%.]] = bitcast i64 [[ARG_ADDR]] to i32*
	// CHECK4-NEXT: [[TMP0:%.]] = load i32, i32 [[CONV]], align 4			// CHECK4-NEXT: [[TMP0:%.]] = load i32, i32 [[CONV]], align 8
	// CHECK4-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0			// CHECK4-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0
	// CHECK4-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8			// CHECK4-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
	// CHECK4-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1			// CHECK4-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
	// CHECK4-NEXT: [[TMP1:%.]] = load i8, i8 [[DOTCAPTURE_EXPR_]], align 1			// CHECK4-NEXT: [[TMP1:%.]] = load i8, i8 [[DOTCAPTURE_EXPR_]], align 1
	// CHECK4-NEXT: [[TOBOOL1:%.*]] = trunc i8 [[TMP1]] to i1			// CHECK4-NEXT: [[TOBOOL1:%.*]] = trunc i8 [[TMP1]] to i1
	// CHECK4-NEXT: [[CONV2:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED]] to i8*			// CHECK4-NEXT: [[CONV2:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED]] to i8*
	// CHECK4-NEXT: [[FROMBOOL3:%.*]] = zext i1 [[TOBOOL1]] to i8			// CHECK4-NEXT: [[FROMBOOL3:%.*]] = zext i1 [[TOBOOL1]] to i8
	// CHECK4-NEXT: store i8 [[FROMBOOL3]], i8* [[CONV2]], align 1			// CHECK4-NEXT: store i8 [[FROMBOOL3]], i8* [[CONV2]], align 1
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	// CHECK4-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !55			// CHECK4-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !55
	// CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK4: omp.inner.for.body:			// CHECK4: omp.inner.for.body:
	// CHECK4-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !55			// CHECK4-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !55
	// CHECK4-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64			// CHECK4-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
	// CHECK4-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !55			// CHECK4-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !55
	// CHECK4-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK4-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK4-NEXT: [[TMP11:%.]] = load i8, i8 [[CONV]], align 1, !llvm.access.group !55			// CHECK4-NEXT: [[TMP11:%.]] = load i8, i8 [[CONV]], align 8, !llvm.access.group !55
	// CHECK4-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1			// CHECK4-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
	// CHECK4-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE:%.]]			// CHECK4-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE:%.]]
	// CHECK4: omp_if.then:			// CHECK4: omp_if.then:
	// CHECK4-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..16 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !55			// CHECK4-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..16 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !55
	// CHECK4-NEXT: br label [[OMP_IF_END:%.*]]			// CHECK4-NEXT: br label [[OMP_IF_END:%.*]]
	// CHECK4: omp_if.else:			// CHECK4: omp_if.else:
	// CHECK4-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !55			// CHECK4-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !55
	// CHECK4-NEXT: [[TMP12:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !55			// CHECK4-NEXT: [[TMP12:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !55
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	// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92			// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92
	// CHECK9-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] {			// CHECK9-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] {
	// CHECK9-NEXT: entry:			// CHECK9-NEXT: entry:
	// CHECK9-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8			// CHECK9-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8
	// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1			// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
	// CHECK9-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8			// CHECK9-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
	// CHECK9-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8			// CHECK9-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8
	// CHECK9-NEXT: [[CONV:%.]] = bitcast i64 [[ARG_ADDR]] to i32*			// CHECK9-NEXT: [[CONV:%.]] = bitcast i64 [[ARG_ADDR]] to i32*
	// CHECK9-NEXT: [[TMP0:%.]] = load i32, i32 [[CONV]], align 4			// CHECK9-NEXT: [[TMP0:%.]] = load i32, i32 [[CONV]], align 8
	// CHECK9-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0			// CHECK9-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0
	// CHECK9-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8			// CHECK9-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
	// CHECK9-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1			// CHECK9-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
	// CHECK9-NEXT: [[TMP1:%.]] = load i8, i8 [[DOTCAPTURE_EXPR_]], align 1			// CHECK9-NEXT: [[TMP1:%.]] = load i8, i8 [[DOTCAPTURE_EXPR_]], align 1
	// CHECK9-NEXT: [[TOBOOL1:%.*]] = trunc i8 [[TMP1]] to i1			// CHECK9-NEXT: [[TOBOOL1:%.*]] = trunc i8 [[TMP1]] to i1
	// CHECK9-NEXT: [[CONV2:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED]] to i8*			// CHECK9-NEXT: [[CONV2:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED]] to i8*
	// CHECK9-NEXT: [[FROMBOOL3:%.*]] = zext i1 [[TOBOOL1]] to i8			// CHECK9-NEXT: [[FROMBOOL3:%.*]] = zext i1 [[TOBOOL1]] to i8
	// CHECK9-NEXT: store i8 [[FROMBOOL3]], i8* [[CONV2]], align 1			// CHECK9-NEXT: store i8 [[FROMBOOL3]], i8* [[CONV2]], align 1
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	// CHECK9-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !42			// CHECK9-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !42
	// CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK9: omp.inner.for.body:			// CHECK9: omp.inner.for.body:
	// CHECK9-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !42			// CHECK9-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !42
	// CHECK9-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64			// CHECK9-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
	// CHECK9-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !42			// CHECK9-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !42
	// CHECK9-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK9-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK9-NEXT: [[TMP11:%.]] = load i8, i8 [[CONV]], align 1, !llvm.access.group !42			// CHECK9-NEXT: [[TMP11:%.]] = load i8, i8 [[CONV]], align 8, !llvm.access.group !42
	// CHECK9-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1			// CHECK9-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
	// CHECK9-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE:%.]]			// CHECK9-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE:%.]]
	// CHECK9: omp_if.then:			// CHECK9: omp_if.then:
	// CHECK9-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..9 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !42			// CHECK9-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..9 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !42
	// CHECK9-NEXT: br label [[OMP_IF_END:%.*]]			// CHECK9-NEXT: br label [[OMP_IF_END:%.*]]
	// CHECK9: omp_if.else:			// CHECK9: omp_if.else:
	// CHECK9-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !42			// CHECK9-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !42
	// CHECK9-NEXT: [[TMP12:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !42			// CHECK9-NEXT: [[TMP12:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !42
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	// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l67			// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l67
	// CHECK9-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] {			// CHECK9-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] {
	// CHECK9-NEXT: entry:			// CHECK9-NEXT: entry:
	// CHECK9-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8			// CHECK9-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8
	// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1			// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
	// CHECK9-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8			// CHECK9-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
	// CHECK9-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8			// CHECK9-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8
	// CHECK9-NEXT: [[CONV:%.]] = bitcast i64 [[ARG_ADDR]] to i32*			// CHECK9-NEXT: [[CONV:%.]] = bitcast i64 [[ARG_ADDR]] to i32*
	// CHECK9-NEXT: [[TMP0:%.]] = load i32, i32 [[CONV]], align 4			// CHECK9-NEXT: [[TMP0:%.]] = load i32, i32 [[CONV]], align 8
	// CHECK9-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0			// CHECK9-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0
	// CHECK9-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8			// CHECK9-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
	// CHECK9-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1			// CHECK9-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
	// CHECK9-NEXT: [[TMP1:%.]] = load i8, i8 [[DOTCAPTURE_EXPR_]], align 1			// CHECK9-NEXT: [[TMP1:%.]] = load i8, i8 [[DOTCAPTURE_EXPR_]], align 1
	// CHECK9-NEXT: [[TOBOOL1:%.*]] = trunc i8 [[TMP1]] to i1			// CHECK9-NEXT: [[TOBOOL1:%.*]] = trunc i8 [[TMP1]] to i1
	// CHECK9-NEXT: [[CONV2:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED]] to i8*			// CHECK9-NEXT: [[CONV2:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED]] to i8*
	// CHECK9-NEXT: [[FROMBOOL3:%.*]] = zext i1 [[TOBOOL1]] to i8			// CHECK9-NEXT: [[FROMBOOL3:%.*]] = zext i1 [[TOBOOL1]] to i8
	// CHECK9-NEXT: store i8 [[FROMBOOL3]], i8* [[CONV2]], align 1			// CHECK9-NEXT: store i8 [[FROMBOOL3]], i8* [[CONV2]], align 1
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	// CHECK9-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !60			// CHECK9-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !60
	// CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK9: omp.inner.for.body:			// CHECK9: omp.inner.for.body:
	// CHECK9-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !60			// CHECK9-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !60
	// CHECK9-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64			// CHECK9-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
	// CHECK9-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !60			// CHECK9-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !60
	// CHECK9-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK9-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK9-NEXT: [[TMP11:%.]] = load i8, i8 [[CONV]], align 1, !llvm.access.group !60			// CHECK9-NEXT: [[TMP11:%.]] = load i8, i8 [[CONV]], align 8, !llvm.access.group !60
	// CHECK9-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1			// CHECK9-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
	// CHECK9-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE:%.]]			// CHECK9-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE:%.]]
	// CHECK9: omp_if.then:			// CHECK9: omp_if.then:
	// CHECK9-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..15 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !60			// CHECK9-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..15 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !60
	// CHECK9-NEXT: br label [[OMP_IF_END:%.*]]			// CHECK9-NEXT: br label [[OMP_IF_END:%.*]]
	// CHECK9: omp_if.else:			// CHECK9: omp_if.else:
	// CHECK9-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !60			// CHECK9-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !60
	// CHECK9-NEXT: [[TMP12:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !60			// CHECK9-NEXT: [[TMP12:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !60
	▲ Show 20 Lines • Show All 815 Lines • ▼ Show 20 Lines
	// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92			// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92
	// CHECK10-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] {			// CHECK10-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] {
	// CHECK10-NEXT: entry:			// CHECK10-NEXT: entry:
	// CHECK10-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8			// CHECK10-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8
	// CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1			// CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
	// CHECK10-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8			// CHECK10-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
	// CHECK10-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8			// CHECK10-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8
	// CHECK10-NEXT: [[CONV:%.]] = bitcast i64 [[ARG_ADDR]] to i32*			// CHECK10-NEXT: [[CONV:%.]] = bitcast i64 [[ARG_ADDR]] to i32*
	// CHECK10-NEXT: [[TMP0:%.]] = load i32, i32 [[CONV]], align 4			// CHECK10-NEXT: [[TMP0:%.]] = load i32, i32 [[CONV]], align 8
	// CHECK10-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0			// CHECK10-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0
	// CHECK10-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8			// CHECK10-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
	// CHECK10-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1			// CHECK10-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
	// CHECK10-NEXT: [[TMP1:%.]] = load i8, i8 [[DOTCAPTURE_EXPR_]], align 1			// CHECK10-NEXT: [[TMP1:%.]] = load i8, i8 [[DOTCAPTURE_EXPR_]], align 1
	// CHECK10-NEXT: [[TOBOOL1:%.*]] = trunc i8 [[TMP1]] to i1			// CHECK10-NEXT: [[TOBOOL1:%.*]] = trunc i8 [[TMP1]] to i1
	// CHECK10-NEXT: [[CONV2:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED]] to i8*			// CHECK10-NEXT: [[CONV2:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED]] to i8*
	// CHECK10-NEXT: [[FROMBOOL3:%.*]] = zext i1 [[TOBOOL1]] to i8			// CHECK10-NEXT: [[FROMBOOL3:%.*]] = zext i1 [[TOBOOL1]] to i8
	// CHECK10-NEXT: store i8 [[FROMBOOL3]], i8* [[CONV2]], align 1			// CHECK10-NEXT: store i8 [[FROMBOOL3]], i8* [[CONV2]], align 1
	▲ Show 20 Lines • Show All 46 Lines • ▼ Show 20 Lines
	// CHECK10-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !42			// CHECK10-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !42
	// CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK10: omp.inner.for.body:			// CHECK10: omp.inner.for.body:
	// CHECK10-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !42			// CHECK10-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !42
	// CHECK10-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64			// CHECK10-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
	// CHECK10-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !42			// CHECK10-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !42
	// CHECK10-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK10-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK10-NEXT: [[TMP11:%.]] = load i8, i8 [[CONV]], align 1, !llvm.access.group !42			// CHECK10-NEXT: [[TMP11:%.]] = load i8, i8 [[CONV]], align 8, !llvm.access.group !42
	// CHECK10-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1			// CHECK10-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
	// CHECK10-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE:%.]]			// CHECK10-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE:%.]]
	// CHECK10: omp_if.then:			// CHECK10: omp_if.then:
	// CHECK10-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..9 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !42			// CHECK10-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..9 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !42
	// CHECK10-NEXT: br label [[OMP_IF_END:%.*]]			// CHECK10-NEXT: br label [[OMP_IF_END:%.*]]
	// CHECK10: omp_if.else:			// CHECK10: omp_if.else:
	// CHECK10-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !42			// CHECK10-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !42
	// CHECK10-NEXT: [[TMP12:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !42			// CHECK10-NEXT: [[TMP12:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !42
	▲ Show 20 Lines • Show All 474 Lines • ▼ Show 20 Lines
	// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l67			// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l67
	// CHECK10-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] {			// CHECK10-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] {
	// CHECK10-NEXT: entry:			// CHECK10-NEXT: entry:
	// CHECK10-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8			// CHECK10-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8
	// CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1			// CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
	// CHECK10-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8			// CHECK10-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
	// CHECK10-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8			// CHECK10-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8
	// CHECK10-NEXT: [[CONV:%.]] = bitcast i64 [[ARG_ADDR]] to i32*			// CHECK10-NEXT: [[CONV:%.]] = bitcast i64 [[ARG_ADDR]] to i32*
	// CHECK10-NEXT: [[TMP0:%.]] = load i32, i32 [[CONV]], align 4			// CHECK10-NEXT: [[TMP0:%.]] = load i32, i32 [[CONV]], align 8
	// CHECK10-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0			// CHECK10-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0
	// CHECK10-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8			// CHECK10-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
	// CHECK10-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1			// CHECK10-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
	// CHECK10-NEXT: [[TMP1:%.]] = load i8, i8 [[DOTCAPTURE_EXPR_]], align 1			// CHECK10-NEXT: [[TMP1:%.]] = load i8, i8 [[DOTCAPTURE_EXPR_]], align 1
	// CHECK10-NEXT: [[TOBOOL1:%.*]] = trunc i8 [[TMP1]] to i1			// CHECK10-NEXT: [[TOBOOL1:%.*]] = trunc i8 [[TMP1]] to i1
	// CHECK10-NEXT: [[CONV2:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED]] to i8*			// CHECK10-NEXT: [[CONV2:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED]] to i8*
	// CHECK10-NEXT: [[FROMBOOL3:%.*]] = zext i1 [[TOBOOL1]] to i8			// CHECK10-NEXT: [[FROMBOOL3:%.*]] = zext i1 [[TOBOOL1]] to i8
	// CHECK10-NEXT: store i8 [[FROMBOOL3]], i8* [[CONV2]], align 1			// CHECK10-NEXT: store i8 [[FROMBOOL3]], i8* [[CONV2]], align 1
	▲ Show 20 Lines • Show All 46 Lines • ▼ Show 20 Lines
	// CHECK10-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !60			// CHECK10-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !60
	// CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK10: omp.inner.for.body:			// CHECK10: omp.inner.for.body:
	// CHECK10-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !60			// CHECK10-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !60
	// CHECK10-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64			// CHECK10-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
	// CHECK10-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !60			// CHECK10-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !60
	// CHECK10-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK10-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK10-NEXT: [[TMP11:%.]] = load i8, i8 [[CONV]], align 1, !llvm.access.group !60			// CHECK10-NEXT: [[TMP11:%.]] = load i8, i8 [[CONV]], align 8, !llvm.access.group !60
	// CHECK10-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1			// CHECK10-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
	// CHECK10-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE:%.]]			// CHECK10-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE:%.]]
	// CHECK10: omp_if.then:			// CHECK10: omp_if.then:
	// CHECK10-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..15 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !60			// CHECK10-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..15 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !60
	// CHECK10-NEXT: br label [[OMP_IF_END:%.*]]			// CHECK10-NEXT: br label [[OMP_IF_END:%.*]]
	// CHECK10: omp_if.else:			// CHECK10: omp_if.else:
	// CHECK10-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !60			// CHECK10-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !60
	// CHECK10-NEXT: [[TMP12:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !60			// CHECK10-NEXT: [[TMP12:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !60
	▲ Show 20 Lines • Show All 815 Lines • ▼ Show 20 Lines
	// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92			// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92
	// CHECK11-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] {			// CHECK11-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] {
	// CHECK11-NEXT: entry:			// CHECK11-NEXT: entry:
	// CHECK11-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8			// CHECK11-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8
	// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1			// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
	// CHECK11-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8			// CHECK11-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
	// CHECK11-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8			// CHECK11-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8
	// CHECK11-NEXT: [[CONV:%.]] = bitcast i64 [[ARG_ADDR]] to i32*			// CHECK11-NEXT: [[CONV:%.]] = bitcast i64 [[ARG_ADDR]] to i32*
	// CHECK11-NEXT: [[TMP0:%.]] = load i32, i32 [[CONV]], align 4			// CHECK11-NEXT: [[TMP0:%.]] = load i32, i32 [[CONV]], align 8
	// CHECK11-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0			// CHECK11-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0
	// CHECK11-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8			// CHECK11-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
	// CHECK11-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1			// CHECK11-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
	// CHECK11-NEXT: [[TMP1:%.]] = load i8, i8 [[DOTCAPTURE_EXPR_]], align 1			// CHECK11-NEXT: [[TMP1:%.]] = load i8, i8 [[DOTCAPTURE_EXPR_]], align 1
	// CHECK11-NEXT: [[TOBOOL1:%.*]] = trunc i8 [[TMP1]] to i1			// CHECK11-NEXT: [[TOBOOL1:%.*]] = trunc i8 [[TMP1]] to i1
	// CHECK11-NEXT: [[CONV2:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED]] to i8*			// CHECK11-NEXT: [[CONV2:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED]] to i8*
	// CHECK11-NEXT: [[FROMBOOL3:%.*]] = zext i1 [[TOBOOL1]] to i8			// CHECK11-NEXT: [[FROMBOOL3:%.*]] = zext i1 [[TOBOOL1]] to i8
	// CHECK11-NEXT: store i8 [[FROMBOOL3]], i8* [[CONV2]], align 1			// CHECK11-NEXT: store i8 [[FROMBOOL3]], i8* [[CONV2]], align 1
	Show All 38 Lines
	// CHECK11: cond.false:			// CHECK11: cond.false:
	// CHECK11-NEXT: [[TMP3:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK11-NEXT: [[TMP3:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4
	// CHECK11-NEXT: br label [[COND_END]]			// CHECK11-NEXT: br label [[COND_END]]
	// CHECK11: cond.end:			// CHECK11: cond.end:
	// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]			// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
	// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK11-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK11-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK11-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK11-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK11-NEXT: [[TMP5:%.]] = load i8, i8 [[CONV]], align 1			// CHECK11-NEXT: [[TMP5:%.]] = load i8, i8 [[CONV]], align 8
	// CHECK11-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP5]] to i1			// CHECK11-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP5]] to i1
	// CHECK11-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE6:%.]]			// CHECK11-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE6:%.]]
	// CHECK11: omp_if.then:			// CHECK11: omp_if.then:
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK11: omp.inner.for.cond:			// CHECK11: omp.inner.for.cond:
	// CHECK11-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !39			// CHECK11-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !39
	// CHECK11-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !39			// CHECK11-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !39
	// CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK11: omp.inner.for.body:			// CHECK11: omp.inner.for.body:
	// CHECK11-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !39			// CHECK11-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !39
	// CHECK11-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64			// CHECK11-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
	// CHECK11-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !39			// CHECK11-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !39
	// CHECK11-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64			// CHECK11-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
	// CHECK11-NEXT: [[TMP12:%.]] = load i8, i8 [[CONV]], align 1, !llvm.access.group !39			// CHECK11-NEXT: [[TMP12:%.]] = load i8, i8 [[CONV]], align 8, !llvm.access.group !39
	// CHECK11-NEXT: [[TOBOOL2:%.*]] = trunc i8 [[TMP12]] to i1			// CHECK11-NEXT: [[TOBOOL2:%.*]] = trunc i8 [[TMP12]] to i1
	// CHECK11-NEXT: [[CONV3:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED]] to i8*			// CHECK11-NEXT: [[CONV3:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED]] to i8*
	// CHECK11-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL2]] to i8			// CHECK11-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL2]] to i8
	// CHECK11-NEXT: store i8 [[FROMBOOL]], i8* [[CONV3]], align 1, !llvm.access.group !39			// CHECK11-NEXT: store i8 [[FROMBOOL]], i8* [[CONV3]], align 1, !llvm.access.group !39
	// CHECK11-NEXT: [[TMP13:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !39			// CHECK11-NEXT: [[TMP13:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !39
	// CHECK11-NEXT: [[TMP14:%.]] = load i8, i8 [[CONV]], align 1, !llvm.access.group !39			// CHECK11-NEXT: [[TMP14:%.]] = load i8, i8 [[CONV]], align 8, !llvm.access.group !39
	// CHECK11-NEXT: [[TOBOOL4:%.*]] = trunc i8 [[TMP14]] to i1			// CHECK11-NEXT: [[TOBOOL4:%.*]] = trunc i8 [[TMP14]] to i1
	// CHECK11-NEXT: br i1 [[TOBOOL4]], label [[OMP_IF_THEN5:%.]], label [[OMP_IF_ELSE:%.]]			// CHECK11-NEXT: br i1 [[TOBOOL4]], label [[OMP_IF_THEN5:%.]], label [[OMP_IF_ELSE:%.]]
	// CHECK11: omp_if.then5:			// CHECK11: omp_if.then5:
	// CHECK11-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i64)* @.omp_outlined..9 to void (i32, i32, ...)*), i64 [[TMP9]], i64 [[TMP11]], i64 [[TMP13]]), !llvm.access.group !39			// CHECK11-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i64)* @.omp_outlined..9 to void (i32, i32, ...)*), i64 [[TMP9]], i64 [[TMP11]], i64 [[TMP13]]), !llvm.access.group !39
	// CHECK11-NEXT: br label [[OMP_IF_END:%.*]]			// CHECK11-NEXT: br label [[OMP_IF_END:%.*]]
	// CHECK11: omp_if.else:			// CHECK11: omp_if.else:
	// CHECK11-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !39			// CHECK11-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !39
	// CHECK11-NEXT: [[TMP15:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !39			// CHECK11-NEXT: [[TMP15:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !39
	Show All 18 Lines
	// CHECK11-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK11-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4
	// CHECK11-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP18]], [[TMP19]]			// CHECK11-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP18]], [[TMP19]]
	// CHECK11-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY9:%.]], label [[OMP_INNER_FOR_END21:%.]]			// CHECK11-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY9:%.]], label [[OMP_INNER_FOR_END21:%.]]
	// CHECK11: omp.inner.for.body9:			// CHECK11: omp.inner.for.body9:
	// CHECK11-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK11-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK11-NEXT: [[TMP21:%.*]] = zext i32 [[TMP20]] to i64			// CHECK11-NEXT: [[TMP21:%.*]] = zext i32 [[TMP20]] to i64
	// CHECK11-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK11-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4
	// CHECK11-NEXT: [[TMP23:%.*]] = zext i32 [[TMP22]] to i64			// CHECK11-NEXT: [[TMP23:%.*]] = zext i32 [[TMP22]] to i64
	// CHECK11-NEXT: [[TMP24:%.]] = load i8, i8 [[CONV]], align 1			// CHECK11-NEXT: [[TMP24:%.]] = load i8, i8 [[CONV]], align 8
	// CHECK11-NEXT: [[TOBOOL10:%.*]] = trunc i8 [[TMP24]] to i1			// CHECK11-NEXT: [[TOBOOL10:%.*]] = trunc i8 [[TMP24]] to i1
	// CHECK11-NEXT: [[CONV12:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED11]] to i8*			// CHECK11-NEXT: [[CONV12:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED11]] to i8*
	// CHECK11-NEXT: [[FROMBOOL13:%.*]] = zext i1 [[TOBOOL10]] to i8			// CHECK11-NEXT: [[FROMBOOL13:%.*]] = zext i1 [[TOBOOL10]] to i8
	// CHECK11-NEXT: store i8 [[FROMBOOL13]], i8* [[CONV12]], align 1			// CHECK11-NEXT: store i8 [[FROMBOOL13]], i8* [[CONV12]], align 1
	// CHECK11-NEXT: [[TMP25:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED11]], align 8			// CHECK11-NEXT: [[TMP25:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED11]], align 8
	// CHECK11-NEXT: [[TMP26:%.]] = load i8, i8 [[CONV]], align 1			// CHECK11-NEXT: [[TMP26:%.]] = load i8, i8 [[CONV]], align 8
	// CHECK11-NEXT: [[TOBOOL14:%.*]] = trunc i8 [[TMP26]] to i1			// CHECK11-NEXT: [[TOBOOL14:%.*]] = trunc i8 [[TMP26]] to i1
	// CHECK11-NEXT: br i1 [[TOBOOL14]], label [[OMP_IF_THEN15:%.]], label [[OMP_IF_ELSE16:%.]]			// CHECK11-NEXT: br i1 [[TOBOOL14]], label [[OMP_IF_THEN15:%.]], label [[OMP_IF_ELSE16:%.]]
	// CHECK11: omp_if.then15:			// CHECK11: omp_if.then15:
	// CHECK11-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i64)* @.omp_outlined..10 to void (i32, i32, ...)*), i64 [[TMP21]], i64 [[TMP23]], i64 [[TMP25]])			// CHECK11-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i64)* @.omp_outlined..10 to void (i32, i32, ...)*), i64 [[TMP21]], i64 [[TMP23]], i64 [[TMP25]])
	// CHECK11-NEXT: br label [[OMP_IF_END18:%.*]]			// CHECK11-NEXT: br label [[OMP_IF_END18:%.*]]
	// CHECK11: omp_if.else16:			// CHECK11: omp_if.else16:
	// CHECK11-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]])			// CHECK11-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]])
	// CHECK11-NEXT: [[TMP27:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK11-NEXT: [[TMP27:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	▲ Show 20 Lines • Show All 51 Lines • ▼ Show 20 Lines
	// CHECK11-NEXT: [[TMP0:%.]] = load i64, i64 [[DOTPREVIOUS_LB__ADDR]], align 8			// CHECK11-NEXT: [[TMP0:%.]] = load i64, i64 [[DOTPREVIOUS_LB__ADDR]], align 8
	// CHECK11-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP0]] to i32			// CHECK11-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP0]] to i32
	// CHECK11-NEXT: [[TMP1:%.]] = load i64, i64 [[DOTPREVIOUS_UB__ADDR]], align 8			// CHECK11-NEXT: [[TMP1:%.]] = load i64, i64 [[DOTPREVIOUS_UB__ADDR]], align 8
	// CHECK11-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32			// CHECK11-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32
	// CHECK11-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4			// CHECK11-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4
	// CHECK11-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4			// CHECK11-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4
	// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4			// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
	// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4			// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
	// CHECK11-NEXT: [[TMP2:%.]] = load i8, i8 [[CONV]], align 1			// CHECK11-NEXT: [[TMP2:%.]] = load i8, i8 [[CONV]], align 8
	// CHECK11-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1			// CHECK11-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1
	// CHECK11-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE:%.]]			// CHECK11-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE:%.]]
	// CHECK11: omp_if.then:			// CHECK11: omp_if.then:
	// CHECK11-NEXT: [[TMP3:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK11-NEXT: [[TMP3:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK11-NEXT: [[TMP4:%.]] = load i32, i32 [[TMP3]], align 4			// CHECK11-NEXT: [[TMP4:%.]] = load i32, i32 [[TMP3]], align 4
	// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)			// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
	// CHECK11-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK11-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 99			// CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 99
	▲ Show 20 Lines • Show All 111 Lines • ▼ Show 20 Lines
	// CHECK11-NEXT: [[TMP0:%.]] = load i64, i64 [[DOTPREVIOUS_LB__ADDR]], align 8			// CHECK11-NEXT: [[TMP0:%.]] = load i64, i64 [[DOTPREVIOUS_LB__ADDR]], align 8
	// CHECK11-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP0]] to i32			// CHECK11-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP0]] to i32
	// CHECK11-NEXT: [[TMP1:%.]] = load i64, i64 [[DOTPREVIOUS_UB__ADDR]], align 8			// CHECK11-NEXT: [[TMP1:%.]] = load i64, i64 [[DOTPREVIOUS_UB__ADDR]], align 8
	// CHECK11-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32			// CHECK11-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32
	// CHECK11-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4			// CHECK11-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4
	// CHECK11-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4			// CHECK11-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4
	// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4			// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
	// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4			// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
	// CHECK11-NEXT: [[TMP2:%.]] = load i8, i8 [[CONV]], align 1			// CHECK11-NEXT: [[TMP2:%.]] = load i8, i8 [[CONV]], align 8
	// CHECK11-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1			// CHECK11-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1
	// CHECK11-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE:%.]]			// CHECK11-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE:%.]]
	// CHECK11: omp_if.then:			// CHECK11: omp_if.then:
	// CHECK11-NEXT: [[TMP3:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK11-NEXT: [[TMP3:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK11-NEXT: [[TMP4:%.]] = load i32, i32 [[TMP3]], align 4			// CHECK11-NEXT: [[TMP4:%.]] = load i32, i32 [[TMP3]], align 4
	// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)			// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
	// CHECK11-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK11-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 99			// CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 99
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	// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l67			// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l67
	// CHECK11-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] {			// CHECK11-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] {
	// CHECK11-NEXT: entry:			// CHECK11-NEXT: entry:
	// CHECK11-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8			// CHECK11-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8
	// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1			// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
	// CHECK11-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8			// CHECK11-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
	// CHECK11-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8			// CHECK11-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8
	// CHECK11-NEXT: [[CONV:%.]] = bitcast i64 [[ARG_ADDR]] to i32*			// CHECK11-NEXT: [[CONV:%.]] = bitcast i64 [[ARG_ADDR]] to i32*
	// CHECK11-NEXT: [[TMP0:%.]] = load i32, i32 [[CONV]], align 4			// CHECK11-NEXT: [[TMP0:%.]] = load i32, i32 [[CONV]], align 8
	// CHECK11-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0			// CHECK11-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0
	// CHECK11-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8			// CHECK11-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
	// CHECK11-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1			// CHECK11-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
	// CHECK11-NEXT: [[TMP1:%.]] = load i8, i8 [[DOTCAPTURE_EXPR_]], align 1			// CHECK11-NEXT: [[TMP1:%.]] = load i8, i8 [[DOTCAPTURE_EXPR_]], align 1
	// CHECK11-NEXT: [[TOBOOL1:%.*]] = trunc i8 [[TMP1]] to i1			// CHECK11-NEXT: [[TOBOOL1:%.*]] = trunc i8 [[TMP1]] to i1
	// CHECK11-NEXT: [[CONV2:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED]] to i8*			// CHECK11-NEXT: [[CONV2:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED]] to i8*
	// CHECK11-NEXT: [[FROMBOOL3:%.*]] = zext i1 [[TOBOOL1]] to i8			// CHECK11-NEXT: [[FROMBOOL3:%.*]] = zext i1 [[TOBOOL1]] to i8
	// CHECK11-NEXT: store i8 [[FROMBOOL3]], i8* [[CONV2]], align 1			// CHECK11-NEXT: store i8 [[FROMBOOL3]], i8* [[CONV2]], align 1
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	// CHECK11-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !59			// CHECK11-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !59
	// CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK11: omp.inner.for.body:			// CHECK11: omp.inner.for.body:
	// CHECK11-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !59			// CHECK11-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !59
	// CHECK11-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64			// CHECK11-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
	// CHECK11-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !59			// CHECK11-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !59
	// CHECK11-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK11-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK11-NEXT: [[TMP11:%.]] = load i8, i8 [[CONV]], align 1, !llvm.access.group !59			// CHECK11-NEXT: [[TMP11:%.]] = load i8, i8 [[CONV]], align 8, !llvm.access.group !59
	// CHECK11-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1			// CHECK11-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
	// CHECK11-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE:%.]]			// CHECK11-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE:%.]]
	// CHECK11: omp_if.then:			// CHECK11: omp_if.then:
	// CHECK11-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..16 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !59			// CHECK11-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..16 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !59
	// CHECK11-NEXT: br label [[OMP_IF_END:%.*]]			// CHECK11-NEXT: br label [[OMP_IF_END:%.*]]
	// CHECK11: omp_if.else:			// CHECK11: omp_if.else:
	// CHECK11-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !59			// CHECK11-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !59
	// CHECK11-NEXT: [[TMP12:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !59			// CHECK11-NEXT: [[TMP12:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !59
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	// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92			// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92
	// CHECK12-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] {			// CHECK12-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] {
	// CHECK12-NEXT: entry:			// CHECK12-NEXT: entry:
	// CHECK12-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8			// CHECK12-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8
	// CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1			// CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
	// CHECK12-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8			// CHECK12-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
	// CHECK12-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8			// CHECK12-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8
	// CHECK12-NEXT: [[CONV:%.]] = bitcast i64 [[ARG_ADDR]] to i32*			// CHECK12-NEXT: [[CONV:%.]] = bitcast i64 [[ARG_ADDR]] to i32*
	// CHECK12-NEXT: [[TMP0:%.]] = load i32, i32 [[CONV]], align 4			// CHECK12-NEXT: [[TMP0:%.]] = load i32, i32 [[CONV]], align 8
	// CHECK12-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0			// CHECK12-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0
	// CHECK12-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8			// CHECK12-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
	// CHECK12-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1			// CHECK12-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
	// CHECK12-NEXT: [[TMP1:%.]] = load i8, i8 [[DOTCAPTURE_EXPR_]], align 1			// CHECK12-NEXT: [[TMP1:%.]] = load i8, i8 [[DOTCAPTURE_EXPR_]], align 1
	// CHECK12-NEXT: [[TOBOOL1:%.*]] = trunc i8 [[TMP1]] to i1			// CHECK12-NEXT: [[TOBOOL1:%.*]] = trunc i8 [[TMP1]] to i1
	// CHECK12-NEXT: [[CONV2:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED]] to i8*			// CHECK12-NEXT: [[CONV2:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED]] to i8*
	// CHECK12-NEXT: [[FROMBOOL3:%.*]] = zext i1 [[TOBOOL1]] to i8			// CHECK12-NEXT: [[FROMBOOL3:%.*]] = zext i1 [[TOBOOL1]] to i8
	// CHECK12-NEXT: store i8 [[FROMBOOL3]], i8* [[CONV2]], align 1			// CHECK12-NEXT: store i8 [[FROMBOOL3]], i8* [[CONV2]], align 1
	Show All 38 Lines
	// CHECK12: cond.false:			// CHECK12: cond.false:
	// CHECK12-NEXT: [[TMP3:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK12-NEXT: [[TMP3:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4
	// CHECK12-NEXT: br label [[COND_END]]			// CHECK12-NEXT: br label [[COND_END]]
	// CHECK12: cond.end:			// CHECK12: cond.end:
	// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]			// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
	// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK12-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK12-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK12-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK12-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK12-NEXT: [[TMP5:%.]] = load i8, i8 [[CONV]], align 1			// CHECK12-NEXT: [[TMP5:%.]] = load i8, i8 [[CONV]], align 8
	// CHECK12-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP5]] to i1			// CHECK12-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP5]] to i1
	// CHECK12-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE6:%.]]			// CHECK12-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE6:%.]]
	// CHECK12: omp_if.then:			// CHECK12: omp_if.then:
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK12: omp.inner.for.cond:			// CHECK12: omp.inner.for.cond:
	// CHECK12-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !39			// CHECK12-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !39
	// CHECK12-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !39			// CHECK12-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !39
	// CHECK12-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK12-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK12-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK12-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK12: omp.inner.for.body:			// CHECK12: omp.inner.for.body:
	// CHECK12-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !39			// CHECK12-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !39
	// CHECK12-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64			// CHECK12-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
	// CHECK12-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !39			// CHECK12-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !39
	// CHECK12-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64			// CHECK12-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
	// CHECK12-NEXT: [[TMP12:%.]] = load i8, i8 [[CONV]], align 1, !llvm.access.group !39			// CHECK12-NEXT: [[TMP12:%.]] = load i8, i8 [[CONV]], align 8, !llvm.access.group !39
	// CHECK12-NEXT: [[TOBOOL2:%.*]] = trunc i8 [[TMP12]] to i1			// CHECK12-NEXT: [[TOBOOL2:%.*]] = trunc i8 [[TMP12]] to i1
	// CHECK12-NEXT: [[CONV3:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED]] to i8*			// CHECK12-NEXT: [[CONV3:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED]] to i8*
	// CHECK12-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL2]] to i8			// CHECK12-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL2]] to i8
	// CHECK12-NEXT: store i8 [[FROMBOOL]], i8* [[CONV3]], align 1, !llvm.access.group !39			// CHECK12-NEXT: store i8 [[FROMBOOL]], i8* [[CONV3]], align 1, !llvm.access.group !39
	// CHECK12-NEXT: [[TMP13:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !39			// CHECK12-NEXT: [[TMP13:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !39
	// CHECK12-NEXT: [[TMP14:%.]] = load i8, i8 [[CONV]], align 1, !llvm.access.group !39			// CHECK12-NEXT: [[TMP14:%.]] = load i8, i8 [[CONV]], align 8, !llvm.access.group !39
	// CHECK12-NEXT: [[TOBOOL4:%.*]] = trunc i8 [[TMP14]] to i1			// CHECK12-NEXT: [[TOBOOL4:%.*]] = trunc i8 [[TMP14]] to i1
	// CHECK12-NEXT: br i1 [[TOBOOL4]], label [[OMP_IF_THEN5:%.]], label [[OMP_IF_ELSE:%.]]			// CHECK12-NEXT: br i1 [[TOBOOL4]], label [[OMP_IF_THEN5:%.]], label [[OMP_IF_ELSE:%.]]
	// CHECK12: omp_if.then5:			// CHECK12: omp_if.then5:
	// CHECK12-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i64)* @.omp_outlined..9 to void (i32, i32, ...)*), i64 [[TMP9]], i64 [[TMP11]], i64 [[TMP13]]), !llvm.access.group !39			// CHECK12-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i64)* @.omp_outlined..9 to void (i32, i32, ...)*), i64 [[TMP9]], i64 [[TMP11]], i64 [[TMP13]]), !llvm.access.group !39
	// CHECK12-NEXT: br label [[OMP_IF_END:%.*]]			// CHECK12-NEXT: br label [[OMP_IF_END:%.*]]
	// CHECK12: omp_if.else:			// CHECK12: omp_if.else:
	// CHECK12-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !39			// CHECK12-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !39
	// CHECK12-NEXT: [[TMP15:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !39			// CHECK12-NEXT: [[TMP15:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !39
	Show All 18 Lines
	// CHECK12-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK12-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4
	// CHECK12-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP18]], [[TMP19]]			// CHECK12-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP18]], [[TMP19]]
	// CHECK12-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY9:%.]], label [[OMP_INNER_FOR_END21:%.]]			// CHECK12-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY9:%.]], label [[OMP_INNER_FOR_END21:%.]]
	// CHECK12: omp.inner.for.body9:			// CHECK12: omp.inner.for.body9:
	// CHECK12-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK12-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK12-NEXT: [[TMP21:%.*]] = zext i32 [[TMP20]] to i64			// CHECK12-NEXT: [[TMP21:%.*]] = zext i32 [[TMP20]] to i64
	// CHECK12-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK12-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4
	// CHECK12-NEXT: [[TMP23:%.*]] = zext i32 [[TMP22]] to i64			// CHECK12-NEXT: [[TMP23:%.*]] = zext i32 [[TMP22]] to i64
	// CHECK12-NEXT: [[TMP24:%.]] = load i8, i8 [[CONV]], align 1			// CHECK12-NEXT: [[TMP24:%.]] = load i8, i8 [[CONV]], align 8
	// CHECK12-NEXT: [[TOBOOL10:%.*]] = trunc i8 [[TMP24]] to i1			// CHECK12-NEXT: [[TOBOOL10:%.*]] = trunc i8 [[TMP24]] to i1
	// CHECK12-NEXT: [[CONV12:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED11]] to i8*			// CHECK12-NEXT: [[CONV12:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED11]] to i8*
	// CHECK12-NEXT: [[FROMBOOL13:%.*]] = zext i1 [[TOBOOL10]] to i8			// CHECK12-NEXT: [[FROMBOOL13:%.*]] = zext i1 [[TOBOOL10]] to i8
	// CHECK12-NEXT: store i8 [[FROMBOOL13]], i8* [[CONV12]], align 1			// CHECK12-NEXT: store i8 [[FROMBOOL13]], i8* [[CONV12]], align 1
	// CHECK12-NEXT: [[TMP25:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED11]], align 8			// CHECK12-NEXT: [[TMP25:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED11]], align 8
	// CHECK12-NEXT: [[TMP26:%.]] = load i8, i8 [[CONV]], align 1			// CHECK12-NEXT: [[TMP26:%.]] = load i8, i8 [[CONV]], align 8
	// CHECK12-NEXT: [[TOBOOL14:%.*]] = trunc i8 [[TMP26]] to i1			// CHECK12-NEXT: [[TOBOOL14:%.*]] = trunc i8 [[TMP26]] to i1
	// CHECK12-NEXT: br i1 [[TOBOOL14]], label [[OMP_IF_THEN15:%.]], label [[OMP_IF_ELSE16:%.]]			// CHECK12-NEXT: br i1 [[TOBOOL14]], label [[OMP_IF_THEN15:%.]], label [[OMP_IF_ELSE16:%.]]
	// CHECK12: omp_if.then15:			// CHECK12: omp_if.then15:
	// CHECK12-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i64)* @.omp_outlined..10 to void (i32, i32, ...)*), i64 [[TMP21]], i64 [[TMP23]], i64 [[TMP25]])			// CHECK12-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i64)* @.omp_outlined..10 to void (i32, i32, ...)*), i64 [[TMP21]], i64 [[TMP23]], i64 [[TMP25]])
	// CHECK12-NEXT: br label [[OMP_IF_END18:%.*]]			// CHECK12-NEXT: br label [[OMP_IF_END18:%.*]]
	// CHECK12: omp_if.else16:			// CHECK12: omp_if.else16:
	// CHECK12-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]])			// CHECK12-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]])
	// CHECK12-NEXT: [[TMP27:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK12-NEXT: [[TMP27:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	▲ Show 20 Lines • Show All 51 Lines • ▼ Show 20 Lines
	// CHECK12-NEXT: [[TMP0:%.]] = load i64, i64 [[DOTPREVIOUS_LB__ADDR]], align 8			// CHECK12-NEXT: [[TMP0:%.]] = load i64, i64 [[DOTPREVIOUS_LB__ADDR]], align 8
	// CHECK12-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP0]] to i32			// CHECK12-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP0]] to i32
	// CHECK12-NEXT: [[TMP1:%.]] = load i64, i64 [[DOTPREVIOUS_UB__ADDR]], align 8			// CHECK12-NEXT: [[TMP1:%.]] = load i64, i64 [[DOTPREVIOUS_UB__ADDR]], align 8
	// CHECK12-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32			// CHECK12-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32
	// CHECK12-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4			// CHECK12-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4
	// CHECK12-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4			// CHECK12-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4
	// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4			// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
	// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4			// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
	// CHECK12-NEXT: [[TMP2:%.]] = load i8, i8 [[CONV]], align 1			// CHECK12-NEXT: [[TMP2:%.]] = load i8, i8 [[CONV]], align 8
	// CHECK12-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1			// CHECK12-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1
	// CHECK12-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE:%.]]			// CHECK12-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE:%.]]
	// CHECK12: omp_if.then:			// CHECK12: omp_if.then:
	// CHECK12-NEXT: [[TMP3:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK12-NEXT: [[TMP3:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK12-NEXT: [[TMP4:%.]] = load i32, i32 [[TMP3]], align 4			// CHECK12-NEXT: [[TMP4:%.]] = load i32, i32 [[TMP3]], align 4
	// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)			// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
	// CHECK12-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK12-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 99			// CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 99
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	// CHECK12-NEXT: [[TMP0:%.]] = load i64, i64 [[DOTPREVIOUS_LB__ADDR]], align 8			// CHECK12-NEXT: [[TMP0:%.]] = load i64, i64 [[DOTPREVIOUS_LB__ADDR]], align 8
	// CHECK12-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP0]] to i32			// CHECK12-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP0]] to i32
	// CHECK12-NEXT: [[TMP1:%.]] = load i64, i64 [[DOTPREVIOUS_UB__ADDR]], align 8			// CHECK12-NEXT: [[TMP1:%.]] = load i64, i64 [[DOTPREVIOUS_UB__ADDR]], align 8
	// CHECK12-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32			// CHECK12-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32
	// CHECK12-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4			// CHECK12-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4
	// CHECK12-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4			// CHECK12-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4
	// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4			// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
	// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4			// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
	// CHECK12-NEXT: [[TMP2:%.]] = load i8, i8 [[CONV]], align 1			// CHECK12-NEXT: [[TMP2:%.]] = load i8, i8 [[CONV]], align 8
	// CHECK12-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1			// CHECK12-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1
	// CHECK12-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE:%.]]			// CHECK12-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE:%.]]
	// CHECK12: omp_if.then:			// CHECK12: omp_if.then:
	// CHECK12-NEXT: [[TMP3:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK12-NEXT: [[TMP3:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK12-NEXT: [[TMP4:%.]] = load i32, i32 [[TMP3]], align 4			// CHECK12-NEXT: [[TMP4:%.]] = load i32, i32 [[TMP3]], align 4
	// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)			// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
	// CHECK12-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK12-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 99			// CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 99
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	// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l67			// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l67
	// CHECK12-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] {			// CHECK12-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] {
	// CHECK12-NEXT: entry:			// CHECK12-NEXT: entry:
	// CHECK12-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8			// CHECK12-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8
	// CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1			// CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
	// CHECK12-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8			// CHECK12-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
	// CHECK12-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8			// CHECK12-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8
	// CHECK12-NEXT: [[CONV:%.]] = bitcast i64 [[ARG_ADDR]] to i32*			// CHECK12-NEXT: [[CONV:%.]] = bitcast i64 [[ARG_ADDR]] to i32*
	// CHECK12-NEXT: [[TMP0:%.]] = load i32, i32 [[CONV]], align 4			// CHECK12-NEXT: [[TMP0:%.]] = load i32, i32 [[CONV]], align 8
	// CHECK12-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0			// CHECK12-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0
	// CHECK12-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8			// CHECK12-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
	// CHECK12-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1			// CHECK12-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
	// CHECK12-NEXT: [[TMP1:%.]] = load i8, i8 [[DOTCAPTURE_EXPR_]], align 1			// CHECK12-NEXT: [[TMP1:%.]] = load i8, i8 [[DOTCAPTURE_EXPR_]], align 1
	// CHECK12-NEXT: [[TOBOOL1:%.*]] = trunc i8 [[TMP1]] to i1			// CHECK12-NEXT: [[TOBOOL1:%.*]] = trunc i8 [[TMP1]] to i1
	// CHECK12-NEXT: [[CONV2:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED]] to i8*			// CHECK12-NEXT: [[CONV2:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED]] to i8*
	// CHECK12-NEXT: [[FROMBOOL3:%.*]] = zext i1 [[TOBOOL1]] to i8			// CHECK12-NEXT: [[FROMBOOL3:%.*]] = zext i1 [[TOBOOL1]] to i8
	// CHECK12-NEXT: store i8 [[FROMBOOL3]], i8* [[CONV2]], align 1			// CHECK12-NEXT: store i8 [[FROMBOOL3]], i8* [[CONV2]], align 1
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	// CHECK12-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !59			// CHECK12-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !59
	// CHECK12-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK12-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK12-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK12-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK12: omp.inner.for.body:			// CHECK12: omp.inner.for.body:
	// CHECK12-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !59			// CHECK12-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !59
	// CHECK12-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64			// CHECK12-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
	// CHECK12-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !59			// CHECK12-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !59
	// CHECK12-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK12-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK12-NEXT: [[TMP11:%.]] = load i8, i8 [[CONV]], align 1, !llvm.access.group !59			// CHECK12-NEXT: [[TMP11:%.]] = load i8, i8 [[CONV]], align 8, !llvm.access.group !59
	// CHECK12-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1			// CHECK12-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
	// CHECK12-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE:%.]]			// CHECK12-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE:%.]]
	// CHECK12: omp_if.then:			// CHECK12: omp_if.then:
	// CHECK12-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..16 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !59			// CHECK12-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..16 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !59
	// CHECK12-NEXT: br label [[OMP_IF_END:%.*]]			// CHECK12-NEXT: br label [[OMP_IF_END:%.*]]
	// CHECK12: omp_if.else:			// CHECK12: omp_if.else:
	// CHECK12-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !59			// CHECK12-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !59
	// CHECK12-NEXT: [[TMP12:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !59			// CHECK12-NEXT: [[TMP12:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !59
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clang/test/OpenMP/teams_distribute_parallel_for_simd_lastprivate_codegen.cpp

This file is larger than 256 KB, so syntax highlighting is disabled by default.

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	// CHECK1-NEXT: br label [[COND_END]]			// CHECK1-NEXT: br label [[COND_END]]
	// CHECK1: cond.end:			// CHECK1: cond.end:
	// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ]			// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ]
	// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK1-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK1: omp.inner.for.cond:			// CHECK1: omp.inner.for.cond:
	// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !4
	// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !4
	// CHECK1-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]			// CHECK1-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]
	// CHECK1-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK1-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK1: omp.inner.for.body:			// CHECK1: omp.inner.for.body:
	// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !4
	// CHECK1-NEXT: [[TMP13:%.*]] = zext i32 [[TMP12]] to i64			// CHECK1-NEXT: [[TMP13:%.*]] = zext i32 [[TMP12]] to i64
	// CHECK1-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK1-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !4
	// CHECK1-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64			// CHECK1-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64
	// CHECK1-NEXT: [[TMP16:%.]] = load double, double** [[_TMP4]], align 8			// CHECK1-NEXT: [[TMP16:%.]] = load double, double** [[_TMP4]], align 8, !llvm.access.group !4
	// CHECK1-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, double, double, i32, float)* @.omp_outlined..1 to void (i32, i32, ...)), i64 [[TMP13]], i64 [[TMP15]], double [[G2]], double* [[TMP16]], i32* [[SVAR5]], float* [[SFVAR6]])			// CHECK1-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, double, double, i32, float)* @.omp_outlined..1 to void (i32, i32, ...)), i64 [[TMP13]], i64 [[TMP15]], double [[G2]], double* [[TMP16]], i32* [[SVAR5]], float* [[SFVAR6]]), !llvm.access.group !4
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK1: omp.inner.for.inc:			// CHECK1: omp.inner.for.inc:
	// CHECK1-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !4
	// CHECK1-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK1-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !4
	// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP17]], [[TMP18]]			// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP17]], [[TMP18]]
	// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]
	// CHECK1: omp.inner.for.end:			// CHECK1: omp.inner.for.end:
	// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK1: omp.loop.exit:			// CHECK1: omp.loop.exit:
	// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]])			// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]])
	// CHECK1-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK1-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK1-NEXT: [[TMP20:%.*]] = icmp ne i32 [[TMP19]], 0			// CHECK1-NEXT: [[TMP20:%.*]] = icmp ne i32 [[TMP19]], 0
	// CHECK1-NEXT: br i1 [[TMP20]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK1-NEXT: br i1 [[TMP20]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK1: .omp.final.then:			// CHECK1: .omp.final.then:
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	// CHECK1-NEXT: br label [[COND_END]]			// CHECK1-NEXT: br label [[COND_END]]
	// CHECK1: cond.end:			// CHECK1: cond.end:
	// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ]			// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ]
	// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK1-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK1: omp.inner.for.cond:			// CHECK1: omp.inner.for.cond:
	// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !8
	// CHECK1-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK1-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !8
	// CHECK1-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]]			// CHECK1-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]]
	// CHECK1-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK1-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK1: omp.inner.for.body:			// CHECK1: omp.inner.for.body:
	// CHECK1-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !8
	// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1			// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1
	// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !8
	// CHECK1-NEXT: store double 1.000000e+00, double* [[G3]], align 8			// CHECK1-NEXT: store double 1.000000e+00, double* [[G3]], align 8, !llvm.access.group !8
	// CHECK1-NEXT: [[TMP15:%.]] = load double, double** [[_TMP5]], align 8			// CHECK1-NEXT: [[TMP15:%.]] = load double, double** [[_TMP5]], align 8, !llvm.access.group !8
	// CHECK1-NEXT: store volatile double 1.000000e+00, double* [[TMP15]], align 8			// CHECK1-NEXT: store volatile double 1.000000e+00, double* [[TMP15]], align 8, !llvm.access.group !8
	// CHECK1-NEXT: store i32 3, i32* [[SVAR6]], align 4			// CHECK1-NEXT: store i32 3, i32* [[SVAR6]], align 4, !llvm.access.group !8
	// CHECK1-NEXT: store float 4.000000e+00, float* [[SFVAR7]], align 4			// CHECK1-NEXT: store float 4.000000e+00, float* [[SFVAR7]], align 4, !llvm.access.group !8
	// CHECK1-NEXT: [[TMP16:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 0			// CHECK1-NEXT: [[TMP16:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 0
	// CHECK1-NEXT: store double* [[G3]], double** [[TMP16]], align 8			// CHECK1-NEXT: store double* [[G3]], double** [[TMP16]], align 8, !llvm.access.group !8
	// CHECK1-NEXT: [[TMP17:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 1			// CHECK1-NEXT: [[TMP17:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 1
	// CHECK1-NEXT: [[TMP18:%.]] = load double, double** [[_TMP5]], align 8			// CHECK1-NEXT: [[TMP18:%.]] = load double, double** [[_TMP5]], align 8, !llvm.access.group !8
	// CHECK1-NEXT: store double* [[TMP18]], double** [[TMP17]], align 8			// CHECK1-NEXT: store double* [[TMP18]], double** [[TMP17]], align 8, !llvm.access.group !8
	// CHECK1-NEXT: [[TMP19:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 2			// CHECK1-NEXT: [[TMP19:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 2
	// CHECK1-NEXT: store i32* [[SVAR6]], i32** [[TMP19]], align 8			// CHECK1-NEXT: store i32* [[SVAR6]], i32** [[TMP19]], align 8, !llvm.access.group !8
	// CHECK1-NEXT: [[TMP20:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 3			// CHECK1-NEXT: [[TMP20:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 3
	// CHECK1-NEXT: store float* [[SFVAR7]], float** [[TMP20]], align 8			// CHECK1-NEXT: store float* [[SFVAR7]], float** [[TMP20]], align 8, !llvm.access.group !8
	// CHECK1-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(32) [[REF_TMP]])			// CHECK1-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(32) [[REF_TMP]]), !llvm.access.group !8
	// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK1: omp.body.continue:			// CHECK1: omp.body.continue:
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK1: omp.inner.for.inc:			// CHECK1: omp.inner.for.inc:
	// CHECK1-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !8
	// CHECK1-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP21]], 1			// CHECK1-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP21]], 1
	// CHECK1-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]
	// CHECK1: omp.inner.for.end:			// CHECK1: omp.inner.for.end:
	// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK1: omp.loop.exit:			// CHECK1: omp.loop.exit:
	// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]])			// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]])
	// CHECK1-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK1-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK1-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0			// CHECK1-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0
	// CHECK1-NEXT: br i1 [[TMP23]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK1-NEXT: br i1 [[TMP23]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK1: .omp.final.then:			// CHECK1: .omp.final.then:
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	// CHECK2-NEXT: br label [[COND_END]]			// CHECK2-NEXT: br label [[COND_END]]
	// CHECK2: cond.end:			// CHECK2: cond.end:
	// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ]			// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ]
	// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK2-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK2: omp.inner.for.cond:			// CHECK2: omp.inner.for.cond:
	// CHECK2-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !4
	// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !4
	// CHECK2-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]			// CHECK2-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]
	// CHECK2-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK2-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK2: omp.inner.for.body:			// CHECK2: omp.inner.for.body:
	// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !4
	// CHECK2-NEXT: [[TMP13:%.*]] = zext i32 [[TMP12]] to i64			// CHECK2-NEXT: [[TMP13:%.*]] = zext i32 [[TMP12]] to i64
	// CHECK2-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK2-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !4
	// CHECK2-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64			// CHECK2-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64
	// CHECK2-NEXT: [[TMP16:%.]] = load double, double** [[_TMP4]], align 8			// CHECK2-NEXT: [[TMP16:%.]] = load double, double** [[_TMP4]], align 8, !llvm.access.group !4
	// CHECK2-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, double, double, i32, float)* @.omp_outlined..1 to void (i32, i32, ...)), i64 [[TMP13]], i64 [[TMP15]], double [[G2]], double* [[TMP16]], i32* [[SVAR5]], float* [[SFVAR6]])			// CHECK2-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, double, double, i32, float)* @.omp_outlined..1 to void (i32, i32, ...)), i64 [[TMP13]], i64 [[TMP15]], double [[G2]], double* [[TMP16]], i32* [[SVAR5]], float* [[SFVAR6]]), !llvm.access.group !4
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK2: omp.inner.for.inc:			// CHECK2: omp.inner.for.inc:
	// CHECK2-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !4
	// CHECK2-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK2-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !4
	// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP17]], [[TMP18]]			// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP17]], [[TMP18]]
	// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]
	// CHECK2: omp.inner.for.end:			// CHECK2: omp.inner.for.end:
	// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK2: omp.loop.exit:			// CHECK2: omp.loop.exit:
	// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]])			// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]])
	// CHECK2-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK2-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK2-NEXT: [[TMP20:%.*]] = icmp ne i32 [[TMP19]], 0			// CHECK2-NEXT: [[TMP20:%.*]] = icmp ne i32 [[TMP19]], 0
	// CHECK2-NEXT: br i1 [[TMP20]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK2-NEXT: br i1 [[TMP20]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK2: .omp.final.then:			// CHECK2: .omp.final.then:
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	// CHECK2-NEXT: br label [[COND_END]]			// CHECK2-NEXT: br label [[COND_END]]
	// CHECK2: cond.end:			// CHECK2: cond.end:
	// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ]			// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ]
	// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK2-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK2: omp.inner.for.cond:			// CHECK2: omp.inner.for.cond:
	// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !8
	// CHECK2-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK2-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !8
	// CHECK2-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]]			// CHECK2-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]]
	// CHECK2-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK2-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK2: omp.inner.for.body:			// CHECK2: omp.inner.for.body:
	// CHECK2-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !8
	// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1			// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1
	// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !8
	// CHECK2-NEXT: store double 1.000000e+00, double* [[G3]], align 8			// CHECK2-NEXT: store double 1.000000e+00, double* [[G3]], align 8, !llvm.access.group !8
	// CHECK2-NEXT: [[TMP15:%.]] = load double, double** [[_TMP5]], align 8			// CHECK2-NEXT: [[TMP15:%.]] = load double, double** [[_TMP5]], align 8, !llvm.access.group !8
	// CHECK2-NEXT: store volatile double 1.000000e+00, double* [[TMP15]], align 8			// CHECK2-NEXT: store volatile double 1.000000e+00, double* [[TMP15]], align 8, !llvm.access.group !8
	// CHECK2-NEXT: store i32 3, i32* [[SVAR6]], align 4			// CHECK2-NEXT: store i32 3, i32* [[SVAR6]], align 4, !llvm.access.group !8
	// CHECK2-NEXT: store float 4.000000e+00, float* [[SFVAR7]], align 4			// CHECK2-NEXT: store float 4.000000e+00, float* [[SFVAR7]], align 4, !llvm.access.group !8
	// CHECK2-NEXT: [[TMP16:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 0			// CHECK2-NEXT: [[TMP16:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 0
	// CHECK2-NEXT: store double* [[G3]], double** [[TMP16]], align 8			// CHECK2-NEXT: store double* [[G3]], double** [[TMP16]], align 8, !llvm.access.group !8
	// CHECK2-NEXT: [[TMP17:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 1			// CHECK2-NEXT: [[TMP17:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 1
	// CHECK2-NEXT: [[TMP18:%.]] = load double, double** [[_TMP5]], align 8			// CHECK2-NEXT: [[TMP18:%.]] = load double, double** [[_TMP5]], align 8, !llvm.access.group !8
	// CHECK2-NEXT: store double* [[TMP18]], double** [[TMP17]], align 8			// CHECK2-NEXT: store double* [[TMP18]], double** [[TMP17]], align 8, !llvm.access.group !8
	// CHECK2-NEXT: [[TMP19:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 2			// CHECK2-NEXT: [[TMP19:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 2
	// CHECK2-NEXT: store i32* [[SVAR6]], i32** [[TMP19]], align 8			// CHECK2-NEXT: store i32* [[SVAR6]], i32** [[TMP19]], align 8, !llvm.access.group !8
	// CHECK2-NEXT: [[TMP20:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 3			// CHECK2-NEXT: [[TMP20:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 3
	// CHECK2-NEXT: store float* [[SFVAR7]], float** [[TMP20]], align 8			// CHECK2-NEXT: store float* [[SFVAR7]], float** [[TMP20]], align 8, !llvm.access.group !8
	// CHECK2-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(32) [[REF_TMP]])			// CHECK2-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(32) [[REF_TMP]]), !llvm.access.group !8
	// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK2: omp.body.continue:			// CHECK2: omp.body.continue:
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK2: omp.inner.for.inc:			// CHECK2: omp.inner.for.inc:
	// CHECK2-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !8
	// CHECK2-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP21]], 1			// CHECK2-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP21]], 1
	// CHECK2-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]
	// CHECK2: omp.inner.for.end:			// CHECK2: omp.inner.for.end:
	// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK2: omp.loop.exit:			// CHECK2: omp.loop.exit:
	// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]])			// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]])
	// CHECK2-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK2-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK2-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0			// CHECK2-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0
	// CHECK2-NEXT: br i1 [[TMP23]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK2-NEXT: br i1 [[TMP23]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK2: .omp.final.then:			// CHECK2: .omp.final.then:
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	// CHECK3-NEXT: br label [[COND_END]]			// CHECK3-NEXT: br label [[COND_END]]
	// CHECK3: cond.end:			// CHECK3: cond.end:
	// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ]			// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ]
	// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK3-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK3-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK3-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4			// CHECK3-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK3: omp.inner.for.cond:			// CHECK3: omp.inner.for.cond:
	// CHECK3-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK3-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK3-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK3-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5
	// CHECK3-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]			// CHECK3-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]
	// CHECK3-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK3-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK3: omp.inner.for.body:			// CHECK3: omp.inner.for.body:
	// CHECK3-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK3-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !5
	// CHECK3-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK3-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5
	// CHECK3-NEXT: [[TMP14:%.]] = load double, double** [[_TMP4]], align 4			// CHECK3-NEXT: [[TMP14:%.]] = load double, double** [[_TMP4]], align 4, !llvm.access.group !5
	// CHECK3-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32, i32, ...)* bitcast (void (i32, i32, i32, i32, double, double, i32, float)* @.omp_outlined..1 to void (i32, i32, ...)), i32 [[TMP12]], i32 [[TMP13]], double [[G2]], double* [[TMP14]], i32* [[SVAR5]], float* [[SFVAR6]])			// CHECK3-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32, i32, ...)* bitcast (void (i32, i32, i32, i32, double, double, i32, float)* @.omp_outlined..1 to void (i32, i32, ...)), i32 [[TMP12]], i32 [[TMP13]], double [[G2]], double* [[TMP14]], i32* [[SVAR5]], float* [[SFVAR6]]), !llvm.access.group !5
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK3: omp.inner.for.inc:			// CHECK3: omp.inner.for.inc:
	// CHECK3-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK3-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK3-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK3-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !5
	// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP15]], [[TMP16]]			// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP15]], [[TMP16]]
	// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]
	// CHECK3: omp.inner.for.end:			// CHECK3: omp.inner.for.end:
	// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK3: omp.loop.exit:			// CHECK3: omp.loop.exit:
	// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]])			// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]])
	// CHECK3-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK3-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK3-NEXT: [[TMP18:%.*]] = icmp ne i32 [[TMP17]], 0			// CHECK3-NEXT: [[TMP18:%.*]] = icmp ne i32 [[TMP17]], 0
	// CHECK3-NEXT: br i1 [[TMP18]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK3-NEXT: br i1 [[TMP18]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK3: .omp.final.then:			// CHECK3: .omp.final.then:
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	// CHECK3-NEXT: br label [[COND_END]]			// CHECK3-NEXT: br label [[COND_END]]
	// CHECK3: cond.end:			// CHECK3: cond.end:
	// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ]			// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ]
	// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK3-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK3-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK3-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4			// CHECK3-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK3: omp.inner.for.cond:			// CHECK3: omp.inner.for.cond:
	// CHECK3-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK3-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK3-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK3-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !9
	// CHECK3-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]]			// CHECK3-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]]
	// CHECK3-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK3-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK3: omp.inner.for.body:			// CHECK3: omp.inner.for.body:
	// CHECK3-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK3-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1			// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1
	// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9
	// CHECK3-NEXT: store double 1.000000e+00, double* [[G2]], align 8			// CHECK3-NEXT: store double 1.000000e+00, double* [[G2]], align 8, !llvm.access.group !9
	// CHECK3-NEXT: [[TMP15:%.]] = load double, double** [[_TMP4]], align 4			// CHECK3-NEXT: [[TMP15:%.]] = load double, double** [[_TMP4]], align 4, !llvm.access.group !9
	// CHECK3-NEXT: store volatile double 1.000000e+00, double* [[TMP15]], align 4			// CHECK3-NEXT: store volatile double 1.000000e+00, double* [[TMP15]], align 4, !llvm.access.group !9
	// CHECK3-NEXT: store i32 3, i32* [[SVAR5]], align 4			// CHECK3-NEXT: store i32 3, i32* [[SVAR5]], align 4, !llvm.access.group !9
	// CHECK3-NEXT: store float 4.000000e+00, float* [[SFVAR6]], align 4			// CHECK3-NEXT: store float 4.000000e+00, float* [[SFVAR6]], align 4, !llvm.access.group !9
	// CHECK3-NEXT: [[TMP16:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 0			// CHECK3-NEXT: [[TMP16:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 0
	// CHECK3-NEXT: store double* [[G2]], double** [[TMP16]], align 4			// CHECK3-NEXT: store double* [[G2]], double** [[TMP16]], align 4, !llvm.access.group !9
	// CHECK3-NEXT: [[TMP17:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 1			// CHECK3-NEXT: [[TMP17:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 1
	// CHECK3-NEXT: [[TMP18:%.]] = load double, double** [[_TMP4]], align 4			// CHECK3-NEXT: [[TMP18:%.]] = load double, double** [[_TMP4]], align 4, !llvm.access.group !9
	// CHECK3-NEXT: store double* [[TMP18]], double** [[TMP17]], align 4			// CHECK3-NEXT: store double* [[TMP18]], double** [[TMP17]], align 4, !llvm.access.group !9
	// CHECK3-NEXT: [[TMP19:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 2			// CHECK3-NEXT: [[TMP19:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 2
	// CHECK3-NEXT: store i32* [[SVAR5]], i32** [[TMP19]], align 4			// CHECK3-NEXT: store i32* [[SVAR5]], i32** [[TMP19]], align 4, !llvm.access.group !9
	// CHECK3-NEXT: [[TMP20:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 3			// CHECK3-NEXT: [[TMP20:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 3
	// CHECK3-NEXT: store float* [[SFVAR6]], float** [[TMP20]], align 4			// CHECK3-NEXT: store float* [[SFVAR6]], float** [[TMP20]], align 4, !llvm.access.group !9
	// CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 4 dereferenceable(16) [[REF_TMP]])			// CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 4 dereferenceable(16) [[REF_TMP]]), !llvm.access.group !9
	// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK3: omp.body.continue:			// CHECK3: omp.body.continue:
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK3: omp.inner.for.inc:			// CHECK3: omp.inner.for.inc:
	// CHECK3-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK3-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK3-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP21]], 1			// CHECK3-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP21]], 1
	// CHECK3-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4			// CHECK3-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]
	// CHECK3: omp.inner.for.end:			// CHECK3: omp.inner.for.end:
	// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK3: omp.loop.exit:			// CHECK3: omp.loop.exit:
	// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]])			// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]])
	// CHECK3-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK3-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK3-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0			// CHECK3-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0
	// CHECK3-NEXT: br i1 [[TMP23]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK3-NEXT: br i1 [[TMP23]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK3: .omp.final.then:			// CHECK3: .omp.final.then:
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	// CHECK4-NEXT: br label [[COND_END]]			// CHECK4-NEXT: br label [[COND_END]]
	// CHECK4: cond.end:			// CHECK4: cond.end:
	// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ]			// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ]
	// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK4-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK4-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK4-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4			// CHECK4-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK4: omp.inner.for.cond:			// CHECK4: omp.inner.for.cond:
	// CHECK4-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK4-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK4-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK4-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5
	// CHECK4-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]			// CHECK4-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]
	// CHECK4-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK4-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK4: omp.inner.for.body:			// CHECK4: omp.inner.for.body:
	// CHECK4-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK4-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !5
	// CHECK4-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK4-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5
	// CHECK4-NEXT: [[TMP14:%.]] = load double, double** [[_TMP4]], align 4			// CHECK4-NEXT: [[TMP14:%.]] = load double, double** [[_TMP4]], align 4, !llvm.access.group !5
	// CHECK4-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32, i32, ...)* bitcast (void (i32, i32, i32, i32, double, double, i32, float)* @.omp_outlined..1 to void (i32, i32, ...)), i32 [[TMP12]], i32 [[TMP13]], double [[G2]], double* [[TMP14]], i32* [[SVAR5]], float* [[SFVAR6]])			// CHECK4-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32, i32, ...)* bitcast (void (i32, i32, i32, i32, double, double, i32, float)* @.omp_outlined..1 to void (i32, i32, ...)), i32 [[TMP12]], i32 [[TMP13]], double [[G2]], double* [[TMP14]], i32* [[SVAR5]], float* [[SFVAR6]]), !llvm.access.group !5
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK4: omp.inner.for.inc:			// CHECK4: omp.inner.for.inc:
	// CHECK4-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK4-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK4-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK4-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !5
	// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP15]], [[TMP16]]			// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP15]], [[TMP16]]
	// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]
	// CHECK4: omp.inner.for.end:			// CHECK4: omp.inner.for.end:
	// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK4: omp.loop.exit:			// CHECK4: omp.loop.exit:
	// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]])			// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]])
	// CHECK4-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK4-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK4-NEXT: [[TMP18:%.*]] = icmp ne i32 [[TMP17]], 0			// CHECK4-NEXT: [[TMP18:%.*]] = icmp ne i32 [[TMP17]], 0
	// CHECK4-NEXT: br i1 [[TMP18]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK4-NEXT: br i1 [[TMP18]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK4: .omp.final.then:			// CHECK4: .omp.final.then:
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	// CHECK4-NEXT: br label [[COND_END]]			// CHECK4-NEXT: br label [[COND_END]]
	// CHECK4: cond.end:			// CHECK4: cond.end:
	// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ]			// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ]
	// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK4-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK4-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK4-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4			// CHECK4-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK4: omp.inner.for.cond:			// CHECK4: omp.inner.for.cond:
	// CHECK4-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK4-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK4-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK4-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !9
	// CHECK4-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]]			// CHECK4-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]]
	// CHECK4-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK4-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK4: omp.inner.for.body:			// CHECK4: omp.inner.for.body:
	// CHECK4-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK4-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1			// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1
	// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9
	// CHECK4-NEXT: store double 1.000000e+00, double* [[G2]], align 8			// CHECK4-NEXT: store double 1.000000e+00, double* [[G2]], align 8, !llvm.access.group !9
	// CHECK4-NEXT: [[TMP15:%.]] = load double, double** [[_TMP4]], align 4			// CHECK4-NEXT: [[TMP15:%.]] = load double, double** [[_TMP4]], align 4, !llvm.access.group !9
	// CHECK4-NEXT: store volatile double 1.000000e+00, double* [[TMP15]], align 4			// CHECK4-NEXT: store volatile double 1.000000e+00, double* [[TMP15]], align 4, !llvm.access.group !9
	// CHECK4-NEXT: store i32 3, i32* [[SVAR5]], align 4			// CHECK4-NEXT: store i32 3, i32* [[SVAR5]], align 4, !llvm.access.group !9
	// CHECK4-NEXT: store float 4.000000e+00, float* [[SFVAR6]], align 4			// CHECK4-NEXT: store float 4.000000e+00, float* [[SFVAR6]], align 4, !llvm.access.group !9
	// CHECK4-NEXT: [[TMP16:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 0			// CHECK4-NEXT: [[TMP16:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 0
	// CHECK4-NEXT: store double* [[G2]], double** [[TMP16]], align 4			// CHECK4-NEXT: store double* [[G2]], double** [[TMP16]], align 4, !llvm.access.group !9
	// CHECK4-NEXT: [[TMP17:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 1			// CHECK4-NEXT: [[TMP17:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 1
	// CHECK4-NEXT: [[TMP18:%.]] = load double, double** [[_TMP4]], align 4			// CHECK4-NEXT: [[TMP18:%.]] = load double, double** [[_TMP4]], align 4, !llvm.access.group !9
	// CHECK4-NEXT: store double* [[TMP18]], double** [[TMP17]], align 4			// CHECK4-NEXT: store double* [[TMP18]], double** [[TMP17]], align 4, !llvm.access.group !9
	// CHECK4-NEXT: [[TMP19:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 2			// CHECK4-NEXT: [[TMP19:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 2
	// CHECK4-NEXT: store i32* [[SVAR5]], i32** [[TMP19]], align 4			// CHECK4-NEXT: store i32* [[SVAR5]], i32** [[TMP19]], align 4, !llvm.access.group !9
	// CHECK4-NEXT: [[TMP20:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 3			// CHECK4-NEXT: [[TMP20:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 3
	// CHECK4-NEXT: store float* [[SFVAR6]], float** [[TMP20]], align 4			// CHECK4-NEXT: store float* [[SFVAR6]], float** [[TMP20]], align 4, !llvm.access.group !9
	// CHECK4-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 4 dereferenceable(16) [[REF_TMP]])			// CHECK4-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 4 dereferenceable(16) [[REF_TMP]]), !llvm.access.group !9
	// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK4: omp.body.continue:			// CHECK4: omp.body.continue:
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK4: omp.inner.for.inc:			// CHECK4: omp.inner.for.inc:
	// CHECK4-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK4-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK4-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP21]], 1			// CHECK4-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP21]], 1
	// CHECK4-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4			// CHECK4-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]
	// CHECK4: omp.inner.for.end:			// CHECK4: omp.inner.for.end:
	// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK4: omp.loop.exit:			// CHECK4: omp.loop.exit:
	// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]])			// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]])
	// CHECK4-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK4-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK4-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0			// CHECK4-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0
	// CHECK4-NEXT: br i1 [[TMP23]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK4-NEXT: br i1 [[TMP23]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK4: .omp.final.then:			// CHECK4: .omp.final.then:
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	// CHECK9-NEXT: br label [[COND_END]]			// CHECK9-NEXT: br label [[COND_END]]
	// CHECK9: cond.end:			// CHECK9: cond.end:
	// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ]			// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ]
	// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK9-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK9-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK9-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4			// CHECK9-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK9: omp.inner.for.cond:			// CHECK9: omp.inner.for.cond:
	// CHECK9-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK9-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK9-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5
	// CHECK9-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]]			// CHECK9-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]]
	// CHECK9-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]			// CHECK9-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]
	// CHECK9: omp.inner.for.cond.cleanup:			// CHECK9: omp.inner.for.cond.cleanup:
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_END:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
	// CHECK9: omp.inner.for.body:			// CHECK9: omp.inner.for.body:
	// CHECK9-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK9-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !5
	// CHECK9-NEXT: [[TMP14:%.*]] = zext i32 [[TMP13]] to i64			// CHECK9-NEXT: [[TMP14:%.*]] = zext i32 [[TMP13]] to i64
	// CHECK9-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK9-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5
	// CHECK9-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64			// CHECK9-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64
	// CHECK9-NEXT: [[TMP17:%.]] = load %struct.S, %struct.S** [[_TMP6]], align 8			// CHECK9-NEXT: [[TMP17:%.]] = load %struct.S, %struct.S** [[_TMP6]], align 8, !llvm.access.group !5
	// CHECK9-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, [2 x i32], i32, [2 x %struct.S], %struct.S, i32) @.omp_outlined..1 to void (i32, i32, ...)), i64 [[TMP14]], i64 [[TMP16]], [2 x i32] [[VEC3]], i32* [[T_VAR2]], [2 x %struct.S]* [[S_ARR4]], %struct.S* [[TMP17]], i32* [[SVAR7]])			// CHECK9-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, [2 x i32], i32, [2 x %struct.S], %struct.S, i32) @.omp_outlined..1 to void (i32, i32, ...)), i64 [[TMP14]], i64 [[TMP16]], [2 x i32] [[VEC3]], i32* [[T_VAR2]], [2 x %struct.S]* [[S_ARR4]], %struct.S* [[TMP17]], i32* [[SVAR7]]), !llvm.access.group !5
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK9: omp.inner.for.inc:			// CHECK9: omp.inner.for.inc:
	// CHECK9-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK9-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK9-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !5
	// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], [[TMP19]]			// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], [[TMP19]]
	// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]
	// CHECK9: omp.inner.for.end:			// CHECK9: omp.inner.for.end:
	// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK9: omp.loop.exit:			// CHECK9: omp.loop.exit:
	// CHECK9-NEXT: [[TMP20:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK9-NEXT: [[TMP20:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK9-NEXT: [[TMP21:%.]] = load i32, i32 [[TMP20]], align 4			// CHECK9-NEXT: [[TMP21:%.]] = load i32, i32 [[TMP20]], align 4
	// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP21]])			// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP21]])
	// CHECK9-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK9-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK9-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0			// CHECK9-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0
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	// CHECK9-NEXT: br label [[COND_END]]			// CHECK9-NEXT: br label [[COND_END]]
	// CHECK9: cond.end:			// CHECK9: cond.end:
	// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ]			// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ]
	// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK9-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK9-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK9-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4			// CHECK9-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK9: omp.inner.for.cond:			// CHECK9: omp.inner.for.cond:
	// CHECK9-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK9-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK9-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !9
	// CHECK9-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]			// CHECK9-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
	// CHECK9-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]			// CHECK9-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]
	// CHECK9: omp.inner.for.cond.cleanup:			// CHECK9: omp.inner.for.cond.cleanup:
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_END:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
	// CHECK9: omp.inner.for.body:			// CHECK9: omp.inner.for.body:
	// CHECK9-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1			// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1
	// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9
	// CHECK9-NEXT: [[TMP16:%.]] = load i32, i32 [[T_VAR3]], align 4			// CHECK9-NEXT: [[TMP16:%.]] = load i32, i32 [[T_VAR3]], align 4, !llvm.access.group !9
	// CHECK9-NEXT: [[TMP17:%.]] = load i32, i32 [[I]], align 4			// CHECK9-NEXT: [[TMP17:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !9
	// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64			// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64
	// CHECK9-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC4]], i64 0, i64 [[IDXPROM]]			// CHECK9-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC4]], i64 0, i64 [[IDXPROM]]
	// CHECK9-NEXT: store i32 [[TMP16]], i32* [[ARRAYIDX]], align 4			// CHECK9-NEXT: store i32 [[TMP16]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !9
	// CHECK9-NEXT: [[TMP18:%.]] = load %struct.S, %struct.S** [[_TMP7]], align 8			// CHECK9-NEXT: [[TMP18:%.]] = load %struct.S, %struct.S** [[_TMP7]], align 8, !llvm.access.group !9
	// CHECK9-NEXT: [[TMP19:%.]] = load i32, i32 [[I]], align 4			// CHECK9-NEXT: [[TMP19:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !9
	// CHECK9-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP19]] to i64			// CHECK9-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP19]] to i64
	// CHECK9-NEXT: [[ARRAYIDX11:%.]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S] [[S_ARR5]], i64 0, i64 [[IDXPROM10]]			// CHECK9-NEXT: [[ARRAYIDX11:%.]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S] [[S_ARR5]], i64 0, i64 [[IDXPROM10]]
	// CHECK9-NEXT: [[TMP20:%.]] = bitcast %struct.S [[ARRAYIDX11]] to i8*			// CHECK9-NEXT: [[TMP20:%.]] = bitcast %struct.S [[ARRAYIDX11]] to i8*
	// CHECK9-NEXT: [[TMP21:%.]] = bitcast %struct.S [[TMP18]] to i8*			// CHECK9-NEXT: [[TMP21:%.]] = bitcast %struct.S [[TMP18]] to i8*
	// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i64 4, i1 false)			// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i64 4, i1 false), !llvm.access.group !9
	// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK9: omp.body.continue:			// CHECK9: omp.body.continue:
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK9: omp.inner.for.inc:			// CHECK9: omp.inner.for.inc:
	// CHECK9-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK9-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP22]], 1			// CHECK9-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP22]], 1
	// CHECK9-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4			// CHECK9-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]
	// CHECK9: omp.inner.for.end:			// CHECK9: omp.inner.for.end:
	// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK9: omp.loop.exit:			// CHECK9: omp.loop.exit:
	// CHECK9-NEXT: [[TMP23:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK9-NEXT: [[TMP23:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK9-NEXT: [[TMP24:%.]] = load i32, i32 [[TMP23]], align 4			// CHECK9-NEXT: [[TMP24:%.]] = load i32, i32 [[TMP23]], align 4
	// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]])			// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]])
	// CHECK9-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK9-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK9-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0			// CHECK9-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0
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	// CHECK9-NEXT: br label [[COND_END]]			// CHECK9-NEXT: br label [[COND_END]]
	// CHECK9: cond.end:			// CHECK9: cond.end:
	// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ]			// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ]
	// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK9-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK9-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK9-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4			// CHECK9-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK9: omp.inner.for.cond:			// CHECK9: omp.inner.for.cond:
	// CHECK9-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK9-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK9-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !14
	// CHECK9-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]			// CHECK9-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]
	// CHECK9-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]			// CHECK9-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]
	// CHECK9: omp.inner.for.cond.cleanup:			// CHECK9: omp.inner.for.cond.cleanup:
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_END:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
	// CHECK9: omp.inner.for.body:			// CHECK9: omp.inner.for.body:
	// CHECK9-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK9-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !14
	// CHECK9-NEXT: [[TMP13:%.*]] = zext i32 [[TMP12]] to i64			// CHECK9-NEXT: [[TMP13:%.*]] = zext i32 [[TMP12]] to i64
	// CHECK9-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK9-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !14
	// CHECK9-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64			// CHECK9-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64
	// CHECK9-NEXT: [[TMP16:%.]] = load %struct.S.0, %struct.S.0** [[_TMP6]], align 8			// CHECK9-NEXT: [[TMP16:%.]] = load %struct.S.0, %struct.S.0** [[_TMP6]], align 8, !llvm.access.group !14
	// CHECK9-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, [2 x i32], i32, [2 x %struct.S.0], %struct.S.0)* @.omp_outlined..3 to void (i32, i32, ...)), i64 [[TMP13]], i64 [[TMP15]], [2 x i32] [[VEC3]], i32* [[T_VAR2]], [2 x %struct.S.0]* [[S_ARR4]], %struct.S.0* [[TMP16]])			// CHECK9-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, [2 x i32], i32, [2 x %struct.S.0], %struct.S.0)* @.omp_outlined..3 to void (i32, i32, ...)), i64 [[TMP13]], i64 [[TMP15]], [2 x i32] [[VEC3]], i32* [[T_VAR2]], [2 x %struct.S.0]* [[S_ARR4]], %struct.S.0* [[TMP16]]), !llvm.access.group !14
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK9: omp.inner.for.inc:			// CHECK9: omp.inner.for.inc:
	// CHECK9-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK9-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK9-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !14
	// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP17]], [[TMP18]]			// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP17]], [[TMP18]]
	// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]]
	// CHECK9: omp.inner.for.end:			// CHECK9: omp.inner.for.end:
	// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK9: omp.loop.exit:			// CHECK9: omp.loop.exit:
	// CHECK9-NEXT: [[TMP19:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK9-NEXT: [[TMP19:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK9-NEXT: [[TMP20:%.]] = load i32, i32 [[TMP19]], align 4			// CHECK9-NEXT: [[TMP20:%.]] = load i32, i32 [[TMP19]], align 4
	// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]])			// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]])
	// CHECK9-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK9-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK9-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0			// CHECK9-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0
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	// CHECK9-NEXT: br label [[COND_END]]			// CHECK9-NEXT: br label [[COND_END]]
	// CHECK9: cond.end:			// CHECK9: cond.end:
	// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ]			// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ]
	// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK9-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK9-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK9-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4			// CHECK9-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK9: omp.inner.for.cond:			// CHECK9: omp.inner.for.cond:
	// CHECK9-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !17
	// CHECK9-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK9-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !17
	// CHECK9-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]]			// CHECK9-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]]
	// CHECK9-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]			// CHECK9-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]
	// CHECK9: omp.inner.for.cond.cleanup:			// CHECK9: omp.inner.for.cond.cleanup:
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_END:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
	// CHECK9: omp.inner.for.body:			// CHECK9: omp.inner.for.body:
	// CHECK9-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !17
	// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1			// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1
	// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !17
	// CHECK9-NEXT: [[TMP15:%.]] = load i32, i32 [[T_VAR3]], align 4			// CHECK9-NEXT: [[TMP15:%.]] = load i32, i32 [[T_VAR3]], align 4, !llvm.access.group !17
	// CHECK9-NEXT: [[TMP16:%.]] = load i32, i32 [[I]], align 4			// CHECK9-NEXT: [[TMP16:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !17
	// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64			// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64
	// CHECK9-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC4]], i64 0, i64 [[IDXPROM]]			// CHECK9-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC4]], i64 0, i64 [[IDXPROM]]
	// CHECK9-NEXT: store i32 [[TMP15]], i32* [[ARRAYIDX]], align 4			// CHECK9-NEXT: store i32 [[TMP15]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !17
	// CHECK9-NEXT: [[TMP17:%.]] = load %struct.S.0, %struct.S.0** [[_TMP7]], align 8			// CHECK9-NEXT: [[TMP17:%.]] = load %struct.S.0, %struct.S.0** [[_TMP7]], align 8, !llvm.access.group !17
	// CHECK9-NEXT: [[TMP18:%.]] = load i32, i32 [[I]], align 4			// CHECK9-NEXT: [[TMP18:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !17
	// CHECK9-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP18]] to i64			// CHECK9-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP18]] to i64
	// CHECK9-NEXT: [[ARRAYIDX10:%.]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0] [[S_ARR5]], i64 0, i64 [[IDXPROM9]]			// CHECK9-NEXT: [[ARRAYIDX10:%.]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0] [[S_ARR5]], i64 0, i64 [[IDXPROM9]]
	// CHECK9-NEXT: [[TMP19:%.]] = bitcast %struct.S.0 [[ARRAYIDX10]] to i8*			// CHECK9-NEXT: [[TMP19:%.]] = bitcast %struct.S.0 [[ARRAYIDX10]] to i8*
	// CHECK9-NEXT: [[TMP20:%.]] = bitcast %struct.S.0 [[TMP17]] to i8*			// CHECK9-NEXT: [[TMP20:%.]] = bitcast %struct.S.0 [[TMP17]] to i8*
	// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP19]], i8* align 4 [[TMP20]], i64 4, i1 false)			// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP19]], i8* align 4 [[TMP20]], i64 4, i1 false), !llvm.access.group !17
	// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK9: omp.body.continue:			// CHECK9: omp.body.continue:
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK9: omp.inner.for.inc:			// CHECK9: omp.inner.for.inc:
	// CHECK9-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !17
	// CHECK9-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP21]], 1			// CHECK9-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP21]], 1
	// CHECK9-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4			// CHECK9-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]]
	// CHECK9: omp.inner.for.end:			// CHECK9: omp.inner.for.end:
	// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK9: omp.loop.exit:			// CHECK9: omp.loop.exit:
	// CHECK9-NEXT: [[TMP22:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK9-NEXT: [[TMP22:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK9-NEXT: [[TMP23:%.]] = load i32, i32 [[TMP22]], align 4			// CHECK9-NEXT: [[TMP23:%.]] = load i32, i32 [[TMP22]], align 4
	// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]])			// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]])
	// CHECK9-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK9-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK9-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0			// CHECK9-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0
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	// CHECK10-NEXT: br label [[COND_END]]			// CHECK10-NEXT: br label [[COND_END]]
	// CHECK10: cond.end:			// CHECK10: cond.end:
	// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ]			// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ]
	// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK10-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK10-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK10-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4			// CHECK10-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK10: omp.inner.for.cond:			// CHECK10: omp.inner.for.cond:
	// CHECK10-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK10-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK10-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5
	// CHECK10-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]]			// CHECK10-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]]
	// CHECK10-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]			// CHECK10-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]
	// CHECK10: omp.inner.for.cond.cleanup:			// CHECK10: omp.inner.for.cond.cleanup:
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_END:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
	// CHECK10: omp.inner.for.body:			// CHECK10: omp.inner.for.body:
	// CHECK10-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK10-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !5
	// CHECK10-NEXT: [[TMP14:%.*]] = zext i32 [[TMP13]] to i64			// CHECK10-NEXT: [[TMP14:%.*]] = zext i32 [[TMP13]] to i64
	// CHECK10-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK10-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5
	// CHECK10-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64			// CHECK10-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64
	// CHECK10-NEXT: [[TMP17:%.]] = load %struct.S, %struct.S** [[_TMP6]], align 8			// CHECK10-NEXT: [[TMP17:%.]] = load %struct.S, %struct.S** [[_TMP6]], align 8, !llvm.access.group !5
	// CHECK10-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, [2 x i32], i32, [2 x %struct.S], %struct.S, i32) @.omp_outlined..1 to void (i32, i32, ...)), i64 [[TMP14]], i64 [[TMP16]], [2 x i32] [[VEC3]], i32* [[T_VAR2]], [2 x %struct.S]* [[S_ARR4]], %struct.S* [[TMP17]], i32* [[SVAR7]])			// CHECK10-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, [2 x i32], i32, [2 x %struct.S], %struct.S, i32) @.omp_outlined..1 to void (i32, i32, ...)), i64 [[TMP14]], i64 [[TMP16]], [2 x i32] [[VEC3]], i32* [[T_VAR2]], [2 x %struct.S]* [[S_ARR4]], %struct.S* [[TMP17]], i32* [[SVAR7]]), !llvm.access.group !5
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK10: omp.inner.for.inc:			// CHECK10: omp.inner.for.inc:
	// CHECK10-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK10-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK10-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !5
	// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], [[TMP19]]			// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], [[TMP19]]
	// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]
	// CHECK10: omp.inner.for.end:			// CHECK10: omp.inner.for.end:
	// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK10: omp.loop.exit:			// CHECK10: omp.loop.exit:
	// CHECK10-NEXT: [[TMP20:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK10-NEXT: [[TMP20:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK10-NEXT: [[TMP21:%.]] = load i32, i32 [[TMP20]], align 4			// CHECK10-NEXT: [[TMP21:%.]] = load i32, i32 [[TMP20]], align 4
	// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP21]])			// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP21]])
	// CHECK10-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK10-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK10-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0			// CHECK10-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0
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	// CHECK10-NEXT: br label [[COND_END]]			// CHECK10-NEXT: br label [[COND_END]]
	// CHECK10: cond.end:			// CHECK10: cond.end:
	// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ]			// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ]
	// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK10-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK10-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK10-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4			// CHECK10-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK10: omp.inner.for.cond:			// CHECK10: omp.inner.for.cond:
	// CHECK10-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK10-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK10-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !9
	// CHECK10-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]			// CHECK10-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
	// CHECK10-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]			// CHECK10-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]
	// CHECK10: omp.inner.for.cond.cleanup:			// CHECK10: omp.inner.for.cond.cleanup:
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_END:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
	// CHECK10: omp.inner.for.body:			// CHECK10: omp.inner.for.body:
	// CHECK10-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1			// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1
	// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9
	// CHECK10-NEXT: [[TMP16:%.]] = load i32, i32 [[T_VAR3]], align 4			// CHECK10-NEXT: [[TMP16:%.]] = load i32, i32 [[T_VAR3]], align 4, !llvm.access.group !9
	// CHECK10-NEXT: [[TMP17:%.]] = load i32, i32 [[I]], align 4			// CHECK10-NEXT: [[TMP17:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !9
	// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64			// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64
	// CHECK10-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC4]], i64 0, i64 [[IDXPROM]]			// CHECK10-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC4]], i64 0, i64 [[IDXPROM]]
	// CHECK10-NEXT: store i32 [[TMP16]], i32* [[ARRAYIDX]], align 4			// CHECK10-NEXT: store i32 [[TMP16]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !9
	// CHECK10-NEXT: [[TMP18:%.]] = load %struct.S, %struct.S** [[_TMP7]], align 8			// CHECK10-NEXT: [[TMP18:%.]] = load %struct.S, %struct.S** [[_TMP7]], align 8, !llvm.access.group !9
	// CHECK10-NEXT: [[TMP19:%.]] = load i32, i32 [[I]], align 4			// CHECK10-NEXT: [[TMP19:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !9
	// CHECK10-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP19]] to i64			// CHECK10-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP19]] to i64
	// CHECK10-NEXT: [[ARRAYIDX11:%.]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S] [[S_ARR5]], i64 0, i64 [[IDXPROM10]]			// CHECK10-NEXT: [[ARRAYIDX11:%.]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S] [[S_ARR5]], i64 0, i64 [[IDXPROM10]]
	// CHECK10-NEXT: [[TMP20:%.]] = bitcast %struct.S [[ARRAYIDX11]] to i8*			// CHECK10-NEXT: [[TMP20:%.]] = bitcast %struct.S [[ARRAYIDX11]] to i8*
	// CHECK10-NEXT: [[TMP21:%.]] = bitcast %struct.S [[TMP18]] to i8*			// CHECK10-NEXT: [[TMP21:%.]] = bitcast %struct.S [[TMP18]] to i8*
	// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i64 4, i1 false)			// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i64 4, i1 false), !llvm.access.group !9
	// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK10: omp.body.continue:			// CHECK10: omp.body.continue:
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK10: omp.inner.for.inc:			// CHECK10: omp.inner.for.inc:
	// CHECK10-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK10-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP22]], 1			// CHECK10-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP22]], 1
	// CHECK10-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4			// CHECK10-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]
	// CHECK10: omp.inner.for.end:			// CHECK10: omp.inner.for.end:
	// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK10: omp.loop.exit:			// CHECK10: omp.loop.exit:
	// CHECK10-NEXT: [[TMP23:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK10-NEXT: [[TMP23:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK10-NEXT: [[TMP24:%.]] = load i32, i32 [[TMP23]], align 4			// CHECK10-NEXT: [[TMP24:%.]] = load i32, i32 [[TMP23]], align 4
	// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]])			// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]])
	// CHECK10-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK10-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK10-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0			// CHECK10-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0
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	// CHECK10-NEXT: br label [[COND_END]]			// CHECK10-NEXT: br label [[COND_END]]
	// CHECK10: cond.end:			// CHECK10: cond.end:
	// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ]			// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ]
	// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK10-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK10-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK10-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4			// CHECK10-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK10: omp.inner.for.cond:			// CHECK10: omp.inner.for.cond:
	// CHECK10-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK10-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK10-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !14
	// CHECK10-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]			// CHECK10-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]
	// CHECK10-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]			// CHECK10-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]
	// CHECK10: omp.inner.for.cond.cleanup:			// CHECK10: omp.inner.for.cond.cleanup:
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_END:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
	// CHECK10: omp.inner.for.body:			// CHECK10: omp.inner.for.body:
	// CHECK10-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK10-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !14
	// CHECK10-NEXT: [[TMP13:%.*]] = zext i32 [[TMP12]] to i64			// CHECK10-NEXT: [[TMP13:%.*]] = zext i32 [[TMP12]] to i64
	// CHECK10-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK10-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !14
	// CHECK10-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64			// CHECK10-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64
	// CHECK10-NEXT: [[TMP16:%.]] = load %struct.S.0, %struct.S.0** [[_TMP6]], align 8			// CHECK10-NEXT: [[TMP16:%.]] = load %struct.S.0, %struct.S.0** [[_TMP6]], align 8, !llvm.access.group !14
	// CHECK10-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, [2 x i32], i32, [2 x %struct.S.0], %struct.S.0)* @.omp_outlined..3 to void (i32, i32, ...)), i64 [[TMP13]], i64 [[TMP15]], [2 x i32] [[VEC3]], i32* [[T_VAR2]], [2 x %struct.S.0]* [[S_ARR4]], %struct.S.0* [[TMP16]])			// CHECK10-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, [2 x i32], i32, [2 x %struct.S.0], %struct.S.0)* @.omp_outlined..3 to void (i32, i32, ...)), i64 [[TMP13]], i64 [[TMP15]], [2 x i32] [[VEC3]], i32* [[T_VAR2]], [2 x %struct.S.0]* [[S_ARR4]], %struct.S.0* [[TMP16]]), !llvm.access.group !14
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK10: omp.inner.for.inc:			// CHECK10: omp.inner.for.inc:
	// CHECK10-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK10-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK10-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !14
	// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP17]], [[TMP18]]			// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP17]], [[TMP18]]
	// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]]
	// CHECK10: omp.inner.for.end:			// CHECK10: omp.inner.for.end:
	// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK10: omp.loop.exit:			// CHECK10: omp.loop.exit:
	// CHECK10-NEXT: [[TMP19:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK10-NEXT: [[TMP19:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK10-NEXT: [[TMP20:%.]] = load i32, i32 [[TMP19]], align 4			// CHECK10-NEXT: [[TMP20:%.]] = load i32, i32 [[TMP19]], align 4
	// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]])			// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]])
	// CHECK10-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK10-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK10-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0			// CHECK10-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0
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	// CHECK10-NEXT: br label [[COND_END]]			// CHECK10-NEXT: br label [[COND_END]]
	// CHECK10: cond.end:			// CHECK10: cond.end:
	// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ]			// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ]
	// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK10-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK10-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK10-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4			// CHECK10-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK10: omp.inner.for.cond:			// CHECK10: omp.inner.for.cond:
	// CHECK10-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !17
	// CHECK10-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK10-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !17
	// CHECK10-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]]			// CHECK10-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]]
	// CHECK10-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]			// CHECK10-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]
	// CHECK10: omp.inner.for.cond.cleanup:			// CHECK10: omp.inner.for.cond.cleanup:
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_END:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
	// CHECK10: omp.inner.for.body:			// CHECK10: omp.inner.for.body:
	// CHECK10-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !17
	// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1			// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1
	// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !17
	// CHECK10-NEXT: [[TMP15:%.]] = load i32, i32 [[T_VAR3]], align 4			// CHECK10-NEXT: [[TMP15:%.]] = load i32, i32 [[T_VAR3]], align 4, !llvm.access.group !17
	// CHECK10-NEXT: [[TMP16:%.]] = load i32, i32 [[I]], align 4			// CHECK10-NEXT: [[TMP16:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !17
	// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64			// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64
	// CHECK10-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC4]], i64 0, i64 [[IDXPROM]]			// CHECK10-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC4]], i64 0, i64 [[IDXPROM]]
	// CHECK10-NEXT: store i32 [[TMP15]], i32* [[ARRAYIDX]], align 4			// CHECK10-NEXT: store i32 [[TMP15]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !17
	// CHECK10-NEXT: [[TMP17:%.]] = load %struct.S.0, %struct.S.0** [[_TMP7]], align 8			// CHECK10-NEXT: [[TMP17:%.]] = load %struct.S.0, %struct.S.0** [[_TMP7]], align 8, !llvm.access.group !17
	// CHECK10-NEXT: [[TMP18:%.]] = load i32, i32 [[I]], align 4			// CHECK10-NEXT: [[TMP18:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !17
	// CHECK10-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP18]] to i64			// CHECK10-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP18]] to i64
	// CHECK10-NEXT: [[ARRAYIDX10:%.]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0] [[S_ARR5]], i64 0, i64 [[IDXPROM9]]			// CHECK10-NEXT: [[ARRAYIDX10:%.]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0] [[S_ARR5]], i64 0, i64 [[IDXPROM9]]
	// CHECK10-NEXT: [[TMP19:%.]] = bitcast %struct.S.0 [[ARRAYIDX10]] to i8*			// CHECK10-NEXT: [[TMP19:%.]] = bitcast %struct.S.0 [[ARRAYIDX10]] to i8*
	// CHECK10-NEXT: [[TMP20:%.]] = bitcast %struct.S.0 [[TMP17]] to i8*			// CHECK10-NEXT: [[TMP20:%.]] = bitcast %struct.S.0 [[TMP17]] to i8*
	// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP19]], i8* align 4 [[TMP20]], i64 4, i1 false)			// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP19]], i8* align 4 [[TMP20]], i64 4, i1 false), !llvm.access.group !17
	// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK10: omp.body.continue:			// CHECK10: omp.body.continue:
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK10: omp.inner.for.inc:			// CHECK10: omp.inner.for.inc:
	// CHECK10-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !17
	// CHECK10-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP21]], 1			// CHECK10-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP21]], 1
	// CHECK10-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4			// CHECK10-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]]
	// CHECK10: omp.inner.for.end:			// CHECK10: omp.inner.for.end:
	// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK10: omp.loop.exit:			// CHECK10: omp.loop.exit:
	// CHECK10-NEXT: [[TMP22:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK10-NEXT: [[TMP22:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK10-NEXT: [[TMP23:%.]] = load i32, i32 [[TMP22]], align 4			// CHECK10-NEXT: [[TMP23:%.]] = load i32, i32 [[TMP22]], align 4
	// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]])			// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]])
	// CHECK10-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK10-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK10-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0			// CHECK10-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0
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	// CHECK11-NEXT: br label [[COND_END]]			// CHECK11-NEXT: br label [[COND_END]]
	// CHECK11: cond.end:			// CHECK11: cond.end:
	// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ]			// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ]
	// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK11-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK11-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK11-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4			// CHECK11-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK11: omp.inner.for.cond:			// CHECK11: omp.inner.for.cond:
	// CHECK11-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK11-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !6
	// CHECK11-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK11-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !6
	// CHECK11-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]]			// CHECK11-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]]
	// CHECK11-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]			// CHECK11-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]
	// CHECK11: omp.inner.for.cond.cleanup:			// CHECK11: omp.inner.for.cond.cleanup:
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_END:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
	// CHECK11: omp.inner.for.body:			// CHECK11: omp.inner.for.body:
	// CHECK11-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK11-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !6
	// CHECK11-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK11-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !6
	// CHECK11-NEXT: [[TMP15:%.]] = load %struct.S, %struct.S** [[_TMP6]], align 4			// CHECK11-NEXT: [[TMP15:%.]] = load %struct.S, %struct.S** [[_TMP6]], align 4, !llvm.access.group !6
	// CHECK11-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32, i32, ...)* bitcast (void (i32, i32, i32, i32, [2 x i32], i32, [2 x %struct.S], %struct.S, i32) @.omp_outlined..1 to void (i32, i32, ...)), i32 [[TMP13]], i32 [[TMP14]], [2 x i32] [[VEC3]], i32* [[T_VAR2]], [2 x %struct.S]* [[S_ARR4]], %struct.S* [[TMP15]], i32* [[SVAR7]])			// CHECK11-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32, i32, ...)* bitcast (void (i32, i32, i32, i32, [2 x i32], i32, [2 x %struct.S], %struct.S, i32) @.omp_outlined..1 to void (i32, i32, ...)), i32 [[TMP13]], i32 [[TMP14]], [2 x i32] [[VEC3]], i32* [[T_VAR2]], [2 x %struct.S]* [[S_ARR4]], %struct.S* [[TMP15]], i32* [[SVAR7]]), !llvm.access.group !6
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK11: omp.inner.for.inc:			// CHECK11: omp.inner.for.inc:
	// CHECK11-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK11-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !6
	// CHECK11-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK11-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !6
	// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP16]], [[TMP17]]			// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP16]], [[TMP17]]
	// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]
	// CHECK11: omp.inner.for.end:			// CHECK11: omp.inner.for.end:
	// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK11: omp.loop.exit:			// CHECK11: omp.loop.exit:
	// CHECK11-NEXT: [[TMP18:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4			// CHECK11-NEXT: [[TMP18:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4
	// CHECK11-NEXT: [[TMP19:%.]] = load i32, i32 [[TMP18]], align 4			// CHECK11-NEXT: [[TMP19:%.]] = load i32, i32 [[TMP18]], align 4
	// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP19]])			// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP19]])
	// CHECK11-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK11-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK11-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0			// CHECK11-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0
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	// CHECK11-NEXT: br label [[COND_END]]			// CHECK11-NEXT: br label [[COND_END]]
	// CHECK11: cond.end:			// CHECK11: cond.end:
	// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ]			// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ]
	// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK11-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK11-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK11-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4			// CHECK11-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK11: omp.inner.for.cond:			// CHECK11: omp.inner.for.cond:
	// CHECK11-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK11-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK11-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK11-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !10
	// CHECK11-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]			// CHECK11-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
	// CHECK11-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]			// CHECK11-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]
	// CHECK11: omp.inner.for.cond.cleanup:			// CHECK11: omp.inner.for.cond.cleanup:
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_END:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
	// CHECK11: omp.inner.for.body:			// CHECK11: omp.inner.for.body:
	// CHECK11-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK11-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1			// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1
	// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10
	// CHECK11-NEXT: [[TMP16:%.]] = load i32, i32 [[T_VAR2]], align 4			// CHECK11-NEXT: [[TMP16:%.]] = load i32, i32 [[T_VAR2]], align 4, !llvm.access.group !10
	// CHECK11-NEXT: [[TMP17:%.]] = load i32, i32 [[I]], align 4			// CHECK11-NEXT: [[TMP17:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !10
	// CHECK11-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC3]], i32 0, i32 [[TMP17]]			// CHECK11-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC3]], i32 0, i32 [[TMP17]]
	// CHECK11-NEXT: store i32 [[TMP16]], i32* [[ARRAYIDX]], align 4			// CHECK11-NEXT: store i32 [[TMP16]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !10
	// CHECK11-NEXT: [[TMP18:%.]] = load %struct.S, %struct.S** [[_TMP6]], align 4			// CHECK11-NEXT: [[TMP18:%.]] = load %struct.S, %struct.S** [[_TMP6]], align 4, !llvm.access.group !10
	// CHECK11-NEXT: [[TMP19:%.]] = load i32, i32 [[I]], align 4			// CHECK11-NEXT: [[TMP19:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !10
	// CHECK11-NEXT: [[ARRAYIDX9:%.]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S] [[S_ARR4]], i32 0, i32 [[TMP19]]			// CHECK11-NEXT: [[ARRAYIDX9:%.]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S] [[S_ARR4]], i32 0, i32 [[TMP19]]
	// CHECK11-NEXT: [[TMP20:%.]] = bitcast %struct.S [[ARRAYIDX9]] to i8*			// CHECK11-NEXT: [[TMP20:%.]] = bitcast %struct.S [[ARRAYIDX9]] to i8*
	// CHECK11-NEXT: [[TMP21:%.]] = bitcast %struct.S [[TMP18]] to i8*			// CHECK11-NEXT: [[TMP21:%.]] = bitcast %struct.S [[TMP18]] to i8*
	// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i32 4, i1 false)			// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i32 4, i1 false), !llvm.access.group !10
	// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK11: omp.body.continue:			// CHECK11: omp.body.continue:
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK11: omp.inner.for.inc:			// CHECK11: omp.inner.for.inc:
	// CHECK11-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK11-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK11-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP22]], 1			// CHECK11-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP22]], 1
	// CHECK11-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4			// CHECK11-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]
	// CHECK11: omp.inner.for.end:			// CHECK11: omp.inner.for.end:
	// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK11: omp.loop.exit:			// CHECK11: omp.loop.exit:
	// CHECK11-NEXT: [[TMP23:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4			// CHECK11-NEXT: [[TMP23:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4
	// CHECK11-NEXT: [[TMP24:%.]] = load i32, i32 [[TMP23]], align 4			// CHECK11-NEXT: [[TMP24:%.]] = load i32, i32 [[TMP23]], align 4
	// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]])			// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]])
	// CHECK11-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK11-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK11-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0			// CHECK11-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0
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	// CHECK11-NEXT: br label [[COND_END]]			// CHECK11-NEXT: br label [[COND_END]]
	// CHECK11: cond.end:			// CHECK11: cond.end:
	// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ]			// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ]
	// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK11-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK11-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK11-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4			// CHECK11-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK11: omp.inner.for.cond:			// CHECK11: omp.inner.for.cond:
	// CHECK11-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK11-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK11-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK11-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15
	// CHECK11-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]			// CHECK11-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]
	// CHECK11-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]			// CHECK11-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]
	// CHECK11: omp.inner.for.cond.cleanup:			// CHECK11: omp.inner.for.cond.cleanup:
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_END:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
	// CHECK11: omp.inner.for.body:			// CHECK11: omp.inner.for.body:
	// CHECK11-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK11-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !15
	// CHECK11-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK11-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15
	// CHECK11-NEXT: [[TMP14:%.]] = load %struct.S.0, %struct.S.0** [[_TMP6]], align 4			// CHECK11-NEXT: [[TMP14:%.]] = load %struct.S.0, %struct.S.0** [[_TMP6]], align 4, !llvm.access.group !15
	// CHECK11-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32, i32, ...)* bitcast (void (i32, i32, i32, i32, [2 x i32], i32, [2 x %struct.S.0], %struct.S.0)* @.omp_outlined..3 to void (i32, i32, ...)), i32 [[TMP12]], i32 [[TMP13]], [2 x i32] [[VEC3]], i32* [[T_VAR2]], [2 x %struct.S.0]* [[S_ARR4]], %struct.S.0* [[TMP14]])			// CHECK11-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32, i32, ...)* bitcast (void (i32, i32, i32, i32, [2 x i32], i32, [2 x %struct.S.0], %struct.S.0)* @.omp_outlined..3 to void (i32, i32, ...)), i32 [[TMP12]], i32 [[TMP13]], [2 x i32] [[VEC3]], i32* [[T_VAR2]], [2 x %struct.S.0]* [[S_ARR4]], %struct.S.0* [[TMP14]]), !llvm.access.group !15
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK11: omp.inner.for.inc:			// CHECK11: omp.inner.for.inc:
	// CHECK11-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK11-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK11-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK11-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !15
	// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP15]], [[TMP16]]			// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP15]], [[TMP16]]
	// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]]
	// CHECK11: omp.inner.for.end:			// CHECK11: omp.inner.for.end:
	// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK11: omp.loop.exit:			// CHECK11: omp.loop.exit:
	// CHECK11-NEXT: [[TMP17:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4			// CHECK11-NEXT: [[TMP17:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4
	// CHECK11-NEXT: [[TMP18:%.]] = load i32, i32 [[TMP17]], align 4			// CHECK11-NEXT: [[TMP18:%.]] = load i32, i32 [[TMP17]], align 4
	// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP18]])			// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP18]])
	// CHECK11-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK11-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK11-NEXT: [[TMP20:%.*]] = icmp ne i32 [[TMP19]], 0			// CHECK11-NEXT: [[TMP20:%.*]] = icmp ne i32 [[TMP19]], 0
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	// CHECK11-NEXT: br label [[COND_END]]			// CHECK11-NEXT: br label [[COND_END]]
	// CHECK11: cond.end:			// CHECK11: cond.end:
	// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ]			// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ]
	// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK11-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK11-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK11-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4			// CHECK11-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK11: omp.inner.for.cond:			// CHECK11: omp.inner.for.cond:
	// CHECK11-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK11-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK11-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK11-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !18
	// CHECK11-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]]			// CHECK11-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]]
	// CHECK11-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]			// CHECK11-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]
	// CHECK11: omp.inner.for.cond.cleanup:			// CHECK11: omp.inner.for.cond.cleanup:
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_END:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
	// CHECK11: omp.inner.for.body:			// CHECK11: omp.inner.for.body:
	// CHECK11-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK11-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1			// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1
	// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !18
	// CHECK11-NEXT: [[TMP15:%.]] = load i32, i32 [[T_VAR2]], align 4			// CHECK11-NEXT: [[TMP15:%.]] = load i32, i32 [[T_VAR2]], align 4, !llvm.access.group !18
	// CHECK11-NEXT: [[TMP16:%.]] = load i32, i32 [[I]], align 4			// CHECK11-NEXT: [[TMP16:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !18
	// CHECK11-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC3]], i32 0, i32 [[TMP16]]			// CHECK11-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC3]], i32 0, i32 [[TMP16]]
	// CHECK11-NEXT: store i32 [[TMP15]], i32* [[ARRAYIDX]], align 4			// CHECK11-NEXT: store i32 [[TMP15]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !18
	// CHECK11-NEXT: [[TMP17:%.]] = load %struct.S.0, %struct.S.0** [[_TMP6]], align 4			// CHECK11-NEXT: [[TMP17:%.]] = load %struct.S.0, %struct.S.0** [[_TMP6]], align 4, !llvm.access.group !18
	// CHECK11-NEXT: [[TMP18:%.]] = load i32, i32 [[I]], align 4			// CHECK11-NEXT: [[TMP18:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !18
	// CHECK11-NEXT: [[ARRAYIDX8:%.]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0] [[S_ARR4]], i32 0, i32 [[TMP18]]			// CHECK11-NEXT: [[ARRAYIDX8:%.]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0] [[S_ARR4]], i32 0, i32 [[TMP18]]
	// CHECK11-NEXT: [[TMP19:%.]] = bitcast %struct.S.0 [[ARRAYIDX8]] to i8*			// CHECK11-NEXT: [[TMP19:%.]] = bitcast %struct.S.0 [[ARRAYIDX8]] to i8*
	// CHECK11-NEXT: [[TMP20:%.]] = bitcast %struct.S.0 [[TMP17]] to i8*			// CHECK11-NEXT: [[TMP20:%.]] = bitcast %struct.S.0 [[TMP17]] to i8*
	// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP19]], i8* align 4 [[TMP20]], i32 4, i1 false)			// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP19]], i8* align 4 [[TMP20]], i32 4, i1 false), !llvm.access.group !18
	// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK11: omp.body.continue:			// CHECK11: omp.body.continue:
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK11: omp.inner.for.inc:			// CHECK11: omp.inner.for.inc:
	// CHECK11-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK11-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK11-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP21]], 1			// CHECK11-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP21]], 1
	// CHECK11-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4			// CHECK11-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]
	// CHECK11: omp.inner.for.end:			// CHECK11: omp.inner.for.end:
	// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK11: omp.loop.exit:			// CHECK11: omp.loop.exit:
	// CHECK11-NEXT: [[TMP22:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4			// CHECK11-NEXT: [[TMP22:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4
	// CHECK11-NEXT: [[TMP23:%.]] = load i32, i32 [[TMP22]], align 4			// CHECK11-NEXT: [[TMP23:%.]] = load i32, i32 [[TMP22]], align 4
	// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]])			// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]])
	// CHECK11-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK11-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK11-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0			// CHECK11-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0
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	// CHECK12-NEXT: br label [[COND_END]]			// CHECK12-NEXT: br label [[COND_END]]
	// CHECK12: cond.end:			// CHECK12: cond.end:
	// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ]			// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ]
	// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK12-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK12-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK12-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4			// CHECK12-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK12: omp.inner.for.cond:			// CHECK12: omp.inner.for.cond:
	// CHECK12-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK12-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !6
	// CHECK12-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK12-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !6
	// CHECK12-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]]			// CHECK12-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]]
	// CHECK12-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]			// CHECK12-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]
	// CHECK12: omp.inner.for.cond.cleanup:			// CHECK12: omp.inner.for.cond.cleanup:
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_END:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
	// CHECK12: omp.inner.for.body:			// CHECK12: omp.inner.for.body:
	// CHECK12-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK12-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !6
	// CHECK12-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK12-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !6
	// CHECK12-NEXT: [[TMP15:%.]] = load %struct.S, %struct.S** [[_TMP6]], align 4			// CHECK12-NEXT: [[TMP15:%.]] = load %struct.S, %struct.S** [[_TMP6]], align 4, !llvm.access.group !6
	// CHECK12-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32, i32, ...)* bitcast (void (i32, i32, i32, i32, [2 x i32], i32, [2 x %struct.S], %struct.S, i32) @.omp_outlined..1 to void (i32, i32, ...)), i32 [[TMP13]], i32 [[TMP14]], [2 x i32] [[VEC3]], i32* [[T_VAR2]], [2 x %struct.S]* [[S_ARR4]], %struct.S* [[TMP15]], i32* [[SVAR7]])			// CHECK12-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32, i32, ...)* bitcast (void (i32, i32, i32, i32, [2 x i32], i32, [2 x %struct.S], %struct.S, i32) @.omp_outlined..1 to void (i32, i32, ...)), i32 [[TMP13]], i32 [[TMP14]], [2 x i32] [[VEC3]], i32* [[T_VAR2]], [2 x %struct.S]* [[S_ARR4]], %struct.S* [[TMP15]], i32* [[SVAR7]]), !llvm.access.group !6
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK12: omp.inner.for.inc:			// CHECK12: omp.inner.for.inc:
	// CHECK12-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK12-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !6
	// CHECK12-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK12-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !6
	// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP16]], [[TMP17]]			// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP16]], [[TMP17]]
	// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]
	// CHECK12: omp.inner.for.end:			// CHECK12: omp.inner.for.end:
	// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK12: omp.loop.exit:			// CHECK12: omp.loop.exit:
	// CHECK12-NEXT: [[TMP18:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4			// CHECK12-NEXT: [[TMP18:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4
	// CHECK12-NEXT: [[TMP19:%.]] = load i32, i32 [[TMP18]], align 4			// CHECK12-NEXT: [[TMP19:%.]] = load i32, i32 [[TMP18]], align 4
	// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP19]])			// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP19]])
	// CHECK12-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK12-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK12-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0			// CHECK12-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0
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	// CHECK12-NEXT: br label [[COND_END]]			// CHECK12-NEXT: br label [[COND_END]]
	// CHECK12: cond.end:			// CHECK12: cond.end:
	// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ]			// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ]
	// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK12-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK12-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK12-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4			// CHECK12-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK12: omp.inner.for.cond:			// CHECK12: omp.inner.for.cond:
	// CHECK12-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK12-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK12-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK12-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !10
	// CHECK12-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]			// CHECK12-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
	// CHECK12-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]			// CHECK12-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]
	// CHECK12: omp.inner.for.cond.cleanup:			// CHECK12: omp.inner.for.cond.cleanup:
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_END:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
	// CHECK12: omp.inner.for.body:			// CHECK12: omp.inner.for.body:
	// CHECK12-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK12-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1			// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1
	// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10
	// CHECK12-NEXT: [[TMP16:%.]] = load i32, i32 [[T_VAR2]], align 4			// CHECK12-NEXT: [[TMP16:%.]] = load i32, i32 [[T_VAR2]], align 4, !llvm.access.group !10
	// CHECK12-NEXT: [[TMP17:%.]] = load i32, i32 [[I]], align 4			// CHECK12-NEXT: [[TMP17:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !10
	// CHECK12-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC3]], i32 0, i32 [[TMP17]]			// CHECK12-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC3]], i32 0, i32 [[TMP17]]
	// CHECK12-NEXT: store i32 [[TMP16]], i32* [[ARRAYIDX]], align 4			// CHECK12-NEXT: store i32 [[TMP16]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !10
	// CHECK12-NEXT: [[TMP18:%.]] = load %struct.S, %struct.S** [[_TMP6]], align 4			// CHECK12-NEXT: [[TMP18:%.]] = load %struct.S, %struct.S** [[_TMP6]], align 4, !llvm.access.group !10
	// CHECK12-NEXT: [[TMP19:%.]] = load i32, i32 [[I]], align 4			// CHECK12-NEXT: [[TMP19:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !10
	// CHECK12-NEXT: [[ARRAYIDX9:%.]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S] [[S_ARR4]], i32 0, i32 [[TMP19]]			// CHECK12-NEXT: [[ARRAYIDX9:%.]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S] [[S_ARR4]], i32 0, i32 [[TMP19]]
	// CHECK12-NEXT: [[TMP20:%.]] = bitcast %struct.S [[ARRAYIDX9]] to i8*			// CHECK12-NEXT: [[TMP20:%.]] = bitcast %struct.S [[ARRAYIDX9]] to i8*
	// CHECK12-NEXT: [[TMP21:%.]] = bitcast %struct.S [[TMP18]] to i8*			// CHECK12-NEXT: [[TMP21:%.]] = bitcast %struct.S [[TMP18]] to i8*
	// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i32 4, i1 false)			// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i32 4, i1 false), !llvm.access.group !10
	// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK12: omp.body.continue:			// CHECK12: omp.body.continue:
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK12: omp.inner.for.inc:			// CHECK12: omp.inner.for.inc:
	// CHECK12-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK12-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK12-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP22]], 1			// CHECK12-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP22]], 1
	// CHECK12-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4			// CHECK12-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]
	// CHECK12: omp.inner.for.end:			// CHECK12: omp.inner.for.end:
	// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK12: omp.loop.exit:			// CHECK12: omp.loop.exit:
	// CHECK12-NEXT: [[TMP23:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4			// CHECK12-NEXT: [[TMP23:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4
	// CHECK12-NEXT: [[TMP24:%.]] = load i32, i32 [[TMP23]], align 4			// CHECK12-NEXT: [[TMP24:%.]] = load i32, i32 [[TMP23]], align 4
	// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]])			// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]])
	// CHECK12-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK12-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK12-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0			// CHECK12-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0
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	// CHECK12-NEXT: br label [[COND_END]]			// CHECK12-NEXT: br label [[COND_END]]
	// CHECK12: cond.end:			// CHECK12: cond.end:
	// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ]			// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ]
	// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK12-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK12-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK12-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4			// CHECK12-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK12: omp.inner.for.cond:			// CHECK12: omp.inner.for.cond:
	// CHECK12-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK12-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK12-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK12-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15
	// CHECK12-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]			// CHECK12-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]
	// CHECK12-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]			// CHECK12-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]
	// CHECK12: omp.inner.for.cond.cleanup:			// CHECK12: omp.inner.for.cond.cleanup:
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_END:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
	// CHECK12: omp.inner.for.body:			// CHECK12: omp.inner.for.body:
	// CHECK12-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK12-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !15
	// CHECK12-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK12-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15
	// CHECK12-NEXT: [[TMP14:%.]] = load %struct.S.0, %struct.S.0** [[_TMP6]], align 4			// CHECK12-NEXT: [[TMP14:%.]] = load %struct.S.0, %struct.S.0** [[_TMP6]], align 4, !llvm.access.group !15
	// CHECK12-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32, i32, ...)* bitcast (void (i32, i32, i32, i32, [2 x i32], i32, [2 x %struct.S.0], %struct.S.0)* @.omp_outlined..3 to void (i32, i32, ...)), i32 [[TMP12]], i32 [[TMP13]], [2 x i32] [[VEC3]], i32* [[T_VAR2]], [2 x %struct.S.0]* [[S_ARR4]], %struct.S.0* [[TMP14]])			// CHECK12-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32, i32, ...)* bitcast (void (i32, i32, i32, i32, [2 x i32], i32, [2 x %struct.S.0], %struct.S.0)* @.omp_outlined..3 to void (i32, i32, ...)), i32 [[TMP12]], i32 [[TMP13]], [2 x i32] [[VEC3]], i32* [[T_VAR2]], [2 x %struct.S.0]* [[S_ARR4]], %struct.S.0* [[TMP14]]), !llvm.access.group !15
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK12: omp.inner.for.inc:			// CHECK12: omp.inner.for.inc:
	// CHECK12-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK12-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK12-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK12-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !15
	// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP15]], [[TMP16]]			// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP15]], [[TMP16]]
	// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]]
	// CHECK12: omp.inner.for.end:			// CHECK12: omp.inner.for.end:
	// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK12: omp.loop.exit:			// CHECK12: omp.loop.exit:
	// CHECK12-NEXT: [[TMP17:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4			// CHECK12-NEXT: [[TMP17:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4
	// CHECK12-NEXT: [[TMP18:%.]] = load i32, i32 [[TMP17]], align 4			// CHECK12-NEXT: [[TMP18:%.]] = load i32, i32 [[TMP17]], align 4
	// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP18]])			// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP18]])
	// CHECK12-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK12-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK12-NEXT: [[TMP20:%.*]] = icmp ne i32 [[TMP19]], 0			// CHECK12-NEXT: [[TMP20:%.*]] = icmp ne i32 [[TMP19]], 0
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	// CHECK12-NEXT: br label [[COND_END]]			// CHECK12-NEXT: br label [[COND_END]]
	// CHECK12: cond.end:			// CHECK12: cond.end:
	// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ]			// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ]
	// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK12-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK12-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK12-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4			// CHECK12-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK12: omp.inner.for.cond:			// CHECK12: omp.inner.for.cond:
	// CHECK12-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK12-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK12-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK12-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !18
	// CHECK12-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]]			// CHECK12-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]]
	// CHECK12-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]			// CHECK12-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]
	// CHECK12: omp.inner.for.cond.cleanup:			// CHECK12: omp.inner.for.cond.cleanup:
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_END:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
	// CHECK12: omp.inner.for.body:			// CHECK12: omp.inner.for.body:
	// CHECK12-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK12-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1			// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1
	// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !18
	// CHECK12-NEXT: [[TMP15:%.]] = load i32, i32 [[T_VAR2]], align 4			// CHECK12-NEXT: [[TMP15:%.]] = load i32, i32 [[T_VAR2]], align 4, !llvm.access.group !18
	// CHECK12-NEXT: [[TMP16:%.]] = load i32, i32 [[I]], align 4			// CHECK12-NEXT: [[TMP16:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !18
	// CHECK12-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC3]], i32 0, i32 [[TMP16]]			// CHECK12-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC3]], i32 0, i32 [[TMP16]]
	// CHECK12-NEXT: store i32 [[TMP15]], i32* [[ARRAYIDX]], align 4			// CHECK12-NEXT: store i32 [[TMP15]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !18
	// CHECK12-NEXT: [[TMP17:%.]] = load %struct.S.0, %struct.S.0** [[_TMP6]], align 4			// CHECK12-NEXT: [[TMP17:%.]] = load %struct.S.0, %struct.S.0** [[_TMP6]], align 4, !llvm.access.group !18
	// CHECK12-NEXT: [[TMP18:%.]] = load i32, i32 [[I]], align 4			// CHECK12-NEXT: [[TMP18:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !18
	// CHECK12-NEXT: [[ARRAYIDX8:%.]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0] [[S_ARR4]], i32 0, i32 [[TMP18]]			// CHECK12-NEXT: [[ARRAYIDX8:%.]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0] [[S_ARR4]], i32 0, i32 [[TMP18]]
	// CHECK12-NEXT: [[TMP19:%.]] = bitcast %struct.S.0 [[ARRAYIDX8]] to i8*			// CHECK12-NEXT: [[TMP19:%.]] = bitcast %struct.S.0 [[ARRAYIDX8]] to i8*
	// CHECK12-NEXT: [[TMP20:%.]] = bitcast %struct.S.0 [[TMP17]] to i8*			// CHECK12-NEXT: [[TMP20:%.]] = bitcast %struct.S.0 [[TMP17]] to i8*
	// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP19]], i8* align 4 [[TMP20]], i32 4, i1 false)			// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP19]], i8* align 4 [[TMP20]], i32 4, i1 false), !llvm.access.group !18
	// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK12: omp.body.continue:			// CHECK12: omp.body.continue:
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK12: omp.inner.for.inc:			// CHECK12: omp.inner.for.inc:
	// CHECK12-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK12-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK12-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP21]], 1			// CHECK12-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP21]], 1
	// CHECK12-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4			// CHECK12-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]
	// CHECK12: omp.inner.for.end:			// CHECK12: omp.inner.for.end:
	// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK12: omp.loop.exit:			// CHECK12: omp.loop.exit:
	// CHECK12-NEXT: [[TMP22:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4			// CHECK12-NEXT: [[TMP22:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4
	// CHECK12-NEXT: [[TMP23:%.]] = load i32, i32 [[TMP22]], align 4			// CHECK12-NEXT: [[TMP23:%.]] = load i32, i32 [[TMP22]], align 4
	// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]])			// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]])
	// CHECK12-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK12-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK12-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0			// CHECK12-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0
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clang/test/OpenMP/teams_distribute_parallel_for_simd_num_threads_codegen.cpp

This file is larger than 256 KB, so syntax highlighting is disabled by default.

	Show First 20 Lines • Show All 356 Lines • ▼ Show 20 Lines
	// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l55			// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l55
	// CHECK1-SAME: (i64 [[A:%.*]]) #[[ATTR3]] {			// CHECK1-SAME: (i64 [[A:%.*]]) #[[ATTR3]] {
	// CHECK1-NEXT: entry:			// CHECK1-NEXT: entry:
	// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8			// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
	// CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1			// CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
	// CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8			// CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
	// CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8			// CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
	// CHECK1-NEXT: [[CONV:%.]] = bitcast i64 [[A_ADDR]] to i8*			// CHECK1-NEXT: [[CONV:%.]] = bitcast i64 [[A_ADDR]] to i8*
	// CHECK1-NEXT: [[TMP0:%.]] = load i8, i8 [[CONV]], align 1			// CHECK1-NEXT: [[TMP0:%.]] = load i8, i8 [[CONV]], align 8
	// CHECK1-NEXT: store i8 [[TMP0]], i8* [[DOTCAPTURE_EXPR_]], align 1			// CHECK1-NEXT: store i8 [[TMP0]], i8* [[DOTCAPTURE_EXPR_]], align 1
	// CHECK1-NEXT: [[TMP1:%.]] = load i8, i8 [[DOTCAPTURE_EXPR_]], align 1			// CHECK1-NEXT: [[TMP1:%.]] = load i8, i8 [[DOTCAPTURE_EXPR_]], align 1
	// CHECK1-NEXT: [[CONV1:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED]] to i8*			// CHECK1-NEXT: [[CONV1:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED]] to i8*
	// CHECK1-NEXT: store i8 [[TMP1]], i8* [[CONV1]], align 1			// CHECK1-NEXT: store i8 [[TMP1]], i8* [[CONV1]], align 1
	// CHECK1-NEXT: [[TMP2:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED]], align 8			// CHECK1-NEXT: [[TMP2:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED]], align 8
	// CHECK1-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32, i32, ...)* bitcast (void (i32, i32, i64)* @.omp_outlined..2 to void (i32, i32, ...)*), i64 [[TMP2]])			// CHECK1-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32, i32, ...)* bitcast (void (i32, i32, i64)* @.omp_outlined..2 to void (i32, i32, ...)*), i64 [[TMP2]])
	// CHECK1-NEXT: ret void			// CHECK1-NEXT: ret void
	//			//
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	// CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK1: omp.inner.for.cond:			// CHECK1: omp.inner.for.cond:
	// CHECK1-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18			// CHECK1-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !18			// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !18
	// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK1: omp.inner.for.body:			// CHECK1: omp.inner.for.body:
	// CHECK1-NEXT: [[TMP7:%.]] = load i8, i8 [[CONV]], align 1, !llvm.access.group !18			// CHECK1-NEXT: [[TMP7:%.]] = load i8, i8 [[CONV]], align 8, !llvm.access.group !18
	// CHECK1-NEXT: [[TMP8:%.*]] = sext i8 [[TMP7]] to i32			// CHECK1-NEXT: [[TMP8:%.*]] = sext i8 [[TMP7]] to i32
	// CHECK1-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 [[TMP8]]), !llvm.access.group !18			// CHECK1-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 [[TMP8]]), !llvm.access.group !18
	// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !18			// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !18
	// CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !18			// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !18
	// CHECK1-NEXT: [[TMP12:%.*]] = zext i32 [[TMP11]] to i64			// CHECK1-NEXT: [[TMP12:%.*]] = zext i32 [[TMP11]] to i64
	// CHECK1-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..3 to void (i32, i32, ...)*), i64 [[TMP10]], i64 [[TMP12]]), !llvm.access.group !18			// CHECK1-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..3 to void (i32, i32, ...)*), i64 [[TMP10]], i64 [[TMP12]]), !llvm.access.group !18
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
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	// CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK1: omp.inner.for.cond:			// CHECK1: omp.inner.for.cond:
	// CHECK1-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !42			// CHECK1-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !42
	// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !42			// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !42
	// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK1: omp.inner.for.body:			// CHECK1: omp.inner.for.body:
	// CHECK1-NEXT: [[TMP7:%.]] = load i8, i8 [[CONV]], align 1, !llvm.access.group !42			// CHECK1-NEXT: [[TMP7:%.]] = load i8, i8 [[CONV]], align 8, !llvm.access.group !42
	// CHECK1-NEXT: [[TMP8:%.*]] = sext i8 [[TMP7]] to i32			// CHECK1-NEXT: [[TMP8:%.*]] = sext i8 [[TMP7]] to i32
	// CHECK1-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 [[TMP8]]), !llvm.access.group !42			// CHECK1-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 [[TMP8]]), !llvm.access.group !42
	// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !42			// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !42
	// CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !42			// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !42
	// CHECK1-NEXT: [[TMP12:%.*]] = zext i32 [[TMP11]] to i64			// CHECK1-NEXT: [[TMP12:%.*]] = zext i32 [[TMP11]] to i64
	// CHECK1-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..11 to void (i32, i32, ...)*), i64 [[TMP10]], i64 [[TMP12]]), !llvm.access.group !42			// CHECK1-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..11 to void (i32, i32, ...)*), i64 [[TMP10]], i64 [[TMP12]]), !llvm.access.group !42
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
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	// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l55			// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l55
	// CHECK2-SAME: (i64 [[A:%.*]]) #[[ATTR3]] {			// CHECK2-SAME: (i64 [[A:%.*]]) #[[ATTR3]] {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	// CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8			// CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
	// CHECK2-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1			// CHECK2-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
	// CHECK2-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8			// CHECK2-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
	// CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8			// CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
	// CHECK2-NEXT: [[CONV:%.]] = bitcast i64 [[A_ADDR]] to i8*			// CHECK2-NEXT: [[CONV:%.]] = bitcast i64 [[A_ADDR]] to i8*
	// CHECK2-NEXT: [[TMP0:%.]] = load i8, i8 [[CONV]], align 1			// CHECK2-NEXT: [[TMP0:%.]] = load i8, i8 [[CONV]], align 8
	// CHECK2-NEXT: store i8 [[TMP0]], i8* [[DOTCAPTURE_EXPR_]], align 1			// CHECK2-NEXT: store i8 [[TMP0]], i8* [[DOTCAPTURE_EXPR_]], align 1
	// CHECK2-NEXT: [[TMP1:%.]] = load i8, i8 [[DOTCAPTURE_EXPR_]], align 1			// CHECK2-NEXT: [[TMP1:%.]] = load i8, i8 [[DOTCAPTURE_EXPR_]], align 1
	// CHECK2-NEXT: [[CONV1:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED]] to i8*			// CHECK2-NEXT: [[CONV1:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED]] to i8*
	// CHECK2-NEXT: store i8 [[TMP1]], i8* [[CONV1]], align 1			// CHECK2-NEXT: store i8 [[TMP1]], i8* [[CONV1]], align 1
	// CHECK2-NEXT: [[TMP2:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED]], align 8			// CHECK2-NEXT: [[TMP2:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED]], align 8
	// CHECK2-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32, i32, ...)* bitcast (void (i32, i32, i64)* @.omp_outlined..2 to void (i32, i32, ...)*), i64 [[TMP2]])			// CHECK2-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32, i32, ...)* bitcast (void (i32, i32, i64)* @.omp_outlined..2 to void (i32, i32, ...)*), i64 [[TMP2]])
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	//			//
	Show All 37 Lines
	// CHECK2-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK2: omp.inner.for.cond:			// CHECK2: omp.inner.for.cond:
	// CHECK2-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18			// CHECK2-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !18			// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !18
	// CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK2: omp.inner.for.body:			// CHECK2: omp.inner.for.body:
	// CHECK2-NEXT: [[TMP7:%.]] = load i8, i8 [[CONV]], align 1, !llvm.access.group !18			// CHECK2-NEXT: [[TMP7:%.]] = load i8, i8 [[CONV]], align 8, !llvm.access.group !18
	// CHECK2-NEXT: [[TMP8:%.*]] = sext i8 [[TMP7]] to i32			// CHECK2-NEXT: [[TMP8:%.*]] = sext i8 [[TMP7]] to i32
	// CHECK2-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 [[TMP8]]), !llvm.access.group !18			// CHECK2-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 [[TMP8]]), !llvm.access.group !18
	// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !18			// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !18
	// CHECK2-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK2-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !18			// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !18
	// CHECK2-NEXT: [[TMP12:%.*]] = zext i32 [[TMP11]] to i64			// CHECK2-NEXT: [[TMP12:%.*]] = zext i32 [[TMP11]] to i64
	// CHECK2-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..3 to void (i32, i32, ...)*), i64 [[TMP10]], i64 [[TMP12]]), !llvm.access.group !18			// CHECK2-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..3 to void (i32, i32, ...)*), i64 [[TMP10]], i64 [[TMP12]]), !llvm.access.group !18
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	▲ Show 20 Lines • Show All 756 Lines • ▼ Show 20 Lines
	// CHECK2-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK2: omp.inner.for.cond:			// CHECK2: omp.inner.for.cond:
	// CHECK2-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !42			// CHECK2-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !42
	// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !42			// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !42
	// CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK2: omp.inner.for.body:			// CHECK2: omp.inner.for.body:
	// CHECK2-NEXT: [[TMP7:%.]] = load i8, i8 [[CONV]], align 1, !llvm.access.group !42			// CHECK2-NEXT: [[TMP7:%.]] = load i8, i8 [[CONV]], align 8, !llvm.access.group !42
	// CHECK2-NEXT: [[TMP8:%.*]] = sext i8 [[TMP7]] to i32			// CHECK2-NEXT: [[TMP8:%.*]] = sext i8 [[TMP7]] to i32
	// CHECK2-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 [[TMP8]]), !llvm.access.group !42			// CHECK2-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 [[TMP8]]), !llvm.access.group !42
	// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !42			// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !42
	// CHECK2-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK2-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !42			// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !42
	// CHECK2-NEXT: [[TMP12:%.*]] = zext i32 [[TMP11]] to i64			// CHECK2-NEXT: [[TMP12:%.*]] = zext i32 [[TMP11]] to i64
	// CHECK2-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..11 to void (i32, i32, ...)*), i64 [[TMP10]], i64 [[TMP12]]), !llvm.access.group !42			// CHECK2-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..11 to void (i32, i32, ...)*), i64 [[TMP10]], i64 [[TMP12]]), !llvm.access.group !42
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	▲ Show 20 Lines • Show All 1,090 Lines • ▼ Show 20 Lines
	// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l55			// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l55
	// CHECK5-SAME: (i64 [[A:%.*]]) #[[ATTR3]] {			// CHECK5-SAME: (i64 [[A:%.*]]) #[[ATTR3]] {
	// CHECK5-NEXT: entry:			// CHECK5-NEXT: entry:
	// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8			// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
	// CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1			// CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
	// CHECK5-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8			// CHECK5-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
	// CHECK5-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8			// CHECK5-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
	// CHECK5-NEXT: [[CONV:%.]] = bitcast i64 [[A_ADDR]] to i8*			// CHECK5-NEXT: [[CONV:%.]] = bitcast i64 [[A_ADDR]] to i8*
	// CHECK5-NEXT: [[TMP0:%.]] = load i8, i8 [[CONV]], align 1			// CHECK5-NEXT: [[TMP0:%.]] = load i8, i8 [[CONV]], align 8
	// CHECK5-NEXT: store i8 [[TMP0]], i8* [[DOTCAPTURE_EXPR_]], align 1			// CHECK5-NEXT: store i8 [[TMP0]], i8* [[DOTCAPTURE_EXPR_]], align 1
	// CHECK5-NEXT: [[TMP1:%.]] = load i8, i8 [[DOTCAPTURE_EXPR_]], align 1			// CHECK5-NEXT: [[TMP1:%.]] = load i8, i8 [[DOTCAPTURE_EXPR_]], align 1
	// CHECK5-NEXT: [[CONV1:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED]] to i8*			// CHECK5-NEXT: [[CONV1:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED]] to i8*
	// CHECK5-NEXT: store i8 [[TMP1]], i8* [[CONV1]], align 1			// CHECK5-NEXT: store i8 [[TMP1]], i8* [[CONV1]], align 1
	// CHECK5-NEXT: [[TMP2:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED]], align 8			// CHECK5-NEXT: [[TMP2:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED]], align 8
	// CHECK5-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32, i32, ...)* bitcast (void (i32, i32, i64)* @.omp_outlined..2 to void (i32, i32, ...)*), i64 [[TMP2]])			// CHECK5-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32, i32, ...)* bitcast (void (i32, i32, i64)* @.omp_outlined..2 to void (i32, i32, ...)*), i64 [[TMP2]])
	// CHECK5-NEXT: ret void			// CHECK5-NEXT: ret void
	//			//
	Show All 37 Lines
	// CHECK5-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK5-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK5: omp.inner.for.cond:			// CHECK5: omp.inner.for.cond:
	// CHECK5-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18			// CHECK5-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK5-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !18			// CHECK5-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !18
	// CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK5: omp.inner.for.body:			// CHECK5: omp.inner.for.body:
	// CHECK5-NEXT: [[TMP7:%.]] = load i8, i8 [[CONV]], align 1, !llvm.access.group !18			// CHECK5-NEXT: [[TMP7:%.]] = load i8, i8 [[CONV]], align 8, !llvm.access.group !18
	// CHECK5-NEXT: [[TMP8:%.*]] = sext i8 [[TMP7]] to i32			// CHECK5-NEXT: [[TMP8:%.*]] = sext i8 [[TMP7]] to i32
	// CHECK5-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 [[TMP8]]), !llvm.access.group !18			// CHECK5-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 [[TMP8]]), !llvm.access.group !18
	// CHECK5-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !18			// CHECK5-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !18
	// CHECK5-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK5-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK5-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !18			// CHECK5-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !18
	// CHECK5-NEXT: [[TMP12:%.*]] = zext i32 [[TMP11]] to i64			// CHECK5-NEXT: [[TMP12:%.*]] = zext i32 [[TMP11]] to i64
	// CHECK5-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..3 to void (i32, i32, ...)*), i64 [[TMP10]], i64 [[TMP12]]), !llvm.access.group !18			// CHECK5-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..3 to void (i32, i32, ...)*), i64 [[TMP10]], i64 [[TMP12]]), !llvm.access.group !18
	// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	▲ Show 20 Lines • Show All 747 Lines • ▼ Show 20 Lines
	// CHECK5-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK5-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK5: omp.inner.for.cond:			// CHECK5: omp.inner.for.cond:
	// CHECK5-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !42			// CHECK5-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !42
	// CHECK5-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !42			// CHECK5-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !42
	// CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK5: omp.inner.for.body:			// CHECK5: omp.inner.for.body:
	// CHECK5-NEXT: [[TMP7:%.]] = load i8, i8 [[CONV]], align 1, !llvm.access.group !42			// CHECK5-NEXT: [[TMP7:%.]] = load i8, i8 [[CONV]], align 8, !llvm.access.group !42
	// CHECK5-NEXT: [[TMP8:%.*]] = sext i8 [[TMP7]] to i32			// CHECK5-NEXT: [[TMP8:%.*]] = sext i8 [[TMP7]] to i32
	// CHECK5-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 [[TMP8]]), !llvm.access.group !42			// CHECK5-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 [[TMP8]]), !llvm.access.group !42
	// CHECK5-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !42			// CHECK5-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !42
	// CHECK5-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK5-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK5-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !42			// CHECK5-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !42
	// CHECK5-NEXT: [[TMP12:%.*]] = zext i32 [[TMP11]] to i64			// CHECK5-NEXT: [[TMP12:%.*]] = zext i32 [[TMP11]] to i64
	// CHECK5-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..11 to void (i32, i32, ...)*), i64 [[TMP10]], i64 [[TMP12]]), !llvm.access.group !42			// CHECK5-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..11 to void (i32, i32, ...)*), i64 [[TMP10]], i64 [[TMP12]]), !llvm.access.group !42
	// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	▲ Show 20 Lines • Show All 401 Lines • ▼ Show 20 Lines
	// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l55			// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l55
	// CHECK6-SAME: (i64 [[A:%.*]]) #[[ATTR3]] {			// CHECK6-SAME: (i64 [[A:%.*]]) #[[ATTR3]] {
	// CHECK6-NEXT: entry:			// CHECK6-NEXT: entry:
	// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8			// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
	// CHECK6-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1			// CHECK6-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
	// CHECK6-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8			// CHECK6-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
	// CHECK6-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8			// CHECK6-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
	// CHECK6-NEXT: [[CONV:%.]] = bitcast i64 [[A_ADDR]] to i8*			// CHECK6-NEXT: [[CONV:%.]] = bitcast i64 [[A_ADDR]] to i8*
	// CHECK6-NEXT: [[TMP0:%.]] = load i8, i8 [[CONV]], align 1			// CHECK6-NEXT: [[TMP0:%.]] = load i8, i8 [[CONV]], align 8
	// CHECK6-NEXT: store i8 [[TMP0]], i8* [[DOTCAPTURE_EXPR_]], align 1			// CHECK6-NEXT: store i8 [[TMP0]], i8* [[DOTCAPTURE_EXPR_]], align 1
	// CHECK6-NEXT: [[TMP1:%.]] = load i8, i8 [[DOTCAPTURE_EXPR_]], align 1			// CHECK6-NEXT: [[TMP1:%.]] = load i8, i8 [[DOTCAPTURE_EXPR_]], align 1
	// CHECK6-NEXT: [[CONV1:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED]] to i8*			// CHECK6-NEXT: [[CONV1:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED]] to i8*
	// CHECK6-NEXT: store i8 [[TMP1]], i8* [[CONV1]], align 1			// CHECK6-NEXT: store i8 [[TMP1]], i8* [[CONV1]], align 1
	// CHECK6-NEXT: [[TMP2:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED]], align 8			// CHECK6-NEXT: [[TMP2:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED]], align 8
	// CHECK6-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32, i32, ...)* bitcast (void (i32, i32, i64)* @.omp_outlined..2 to void (i32, i32, ...)*), i64 [[TMP2]])			// CHECK6-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32, i32, ...)* bitcast (void (i32, i32, i64)* @.omp_outlined..2 to void (i32, i32, ...)*), i64 [[TMP2]])
	// CHECK6-NEXT: ret void			// CHECK6-NEXT: ret void
	//			//
	Show All 37 Lines
	// CHECK6-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK6-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK6: omp.inner.for.cond:			// CHECK6: omp.inner.for.cond:
	// CHECK6-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18			// CHECK6-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK6-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !18			// CHECK6-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !18
	// CHECK6-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK6-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK6-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK6-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK6: omp.inner.for.body:			// CHECK6: omp.inner.for.body:
	// CHECK6-NEXT: [[TMP7:%.]] = load i8, i8 [[CONV]], align 1, !llvm.access.group !18			// CHECK6-NEXT: [[TMP7:%.]] = load i8, i8 [[CONV]], align 8, !llvm.access.group !18
	// CHECK6-NEXT: [[TMP8:%.*]] = sext i8 [[TMP7]] to i32			// CHECK6-NEXT: [[TMP8:%.*]] = sext i8 [[TMP7]] to i32
	// CHECK6-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 [[TMP8]]), !llvm.access.group !18			// CHECK6-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 [[TMP8]]), !llvm.access.group !18
	// CHECK6-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !18			// CHECK6-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !18
	// CHECK6-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK6-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK6-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !18			// CHECK6-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !18
	// CHECK6-NEXT: [[TMP12:%.*]] = zext i32 [[TMP11]] to i64			// CHECK6-NEXT: [[TMP12:%.*]] = zext i32 [[TMP11]] to i64
	// CHECK6-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..3 to void (i32, i32, ...)*), i64 [[TMP10]], i64 [[TMP12]]), !llvm.access.group !18			// CHECK6-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..3 to void (i32, i32, ...)*), i64 [[TMP10]], i64 [[TMP12]]), !llvm.access.group !18
	// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
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	// CHECK6-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK6-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK6: omp.inner.for.cond:			// CHECK6: omp.inner.for.cond:
	// CHECK6-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !42			// CHECK6-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !42
	// CHECK6-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !42			// CHECK6-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !42
	// CHECK6-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK6-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK6-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK6-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK6: omp.inner.for.body:			// CHECK6: omp.inner.for.body:
	// CHECK6-NEXT: [[TMP7:%.]] = load i8, i8 [[CONV]], align 1, !llvm.access.group !42			// CHECK6-NEXT: [[TMP7:%.]] = load i8, i8 [[CONV]], align 8, !llvm.access.group !42
	// CHECK6-NEXT: [[TMP8:%.*]] = sext i8 [[TMP7]] to i32			// CHECK6-NEXT: [[TMP8:%.*]] = sext i8 [[TMP7]] to i32
	// CHECK6-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 [[TMP8]]), !llvm.access.group !42			// CHECK6-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 [[TMP8]]), !llvm.access.group !42
	// CHECK6-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !42			// CHECK6-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !42
	// CHECK6-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK6-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK6-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !42			// CHECK6-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !42
	// CHECK6-NEXT: [[TMP12:%.*]] = zext i32 [[TMP11]] to i64			// CHECK6-NEXT: [[TMP12:%.*]] = zext i32 [[TMP11]] to i64
	// CHECK6-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..11 to void (i32, i32, ...)*), i64 [[TMP10]], i64 [[TMP12]]), !llvm.access.group !42			// CHECK6-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..11 to void (i32, i32, ...)*), i64 [[TMP10]], i64 [[TMP12]]), !llvm.access.group !42
	// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
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clang/test/OpenMP/teams_distribute_parallel_for_simd_proc_bind_codegen.cpp

	Show First 20 Lines • Show All 116 Lines • ▼ Show 20 Lines
	// CHECK1-NEXT: br label [[COND_END]]			// CHECK1-NEXT: br label [[COND_END]]
	// CHECK1: cond.end:			// CHECK1: cond.end:
	// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 999, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]			// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 999, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
	// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK1-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK1-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK1: omp.inner.for.cond:			// CHECK1: omp.inner.for.cond:
	// CHECK1-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !6
	// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !6
	// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK1: omp.inner.for.body:			// CHECK1: omp.inner.for.body:
	// CHECK1-NEXT: call void @__kmpc_push_proc_bind(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 4)			// CHECK1-NEXT: call void @__kmpc_push_proc_bind(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 4), !llvm.access.group !6
	// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !6
	// CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64			// CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
	// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !6
	// CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK1-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..1 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]])			// CHECK1-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..1 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !6
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK1: omp.inner.for.inc:			// CHECK1: omp.inner.for.inc:
	// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !6
	// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !6
	// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]			// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
	// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]
	// CHECK1: omp.inner.for.end:			// CHECK1: omp.inner.for.end:
	// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK1: omp.loop.exit:			// CHECK1: omp.loop.exit:
	// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])			// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
	// CHECK1-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK1-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK1-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0			// CHECK1-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
	// CHECK1-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK1-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK1: .omp.final.then:			// CHECK1: .omp.final.then:
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	// CHECK1-NEXT: br label [[COND_END]]			// CHECK1-NEXT: br label [[COND_END]]
	// CHECK1: cond.end:			// CHECK1: cond.end:
	// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 999, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]			// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 999, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
	// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK1-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK1: omp.inner.for.cond:			// CHECK1: omp.inner.for.cond:
	// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK1-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK1-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !10
	// CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK1: omp.inner.for.body:			// CHECK1: omp.inner.for.body:
	// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10
	// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK1: omp.body.continue:			// CHECK1: omp.body.continue:
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK1: omp.inner.for.inc:			// CHECK1: omp.inner.for.inc:
	// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]
	// CHECK1: omp.inner.for.end:			// CHECK1: omp.inner.for.end:
	// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK1: omp.loop.exit:			// CHECK1: omp.loop.exit:
	// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])			// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
	// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK1-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK1-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK1-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK1-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK1: .omp.final.then:			// CHECK1: .omp.final.then:
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	// CHECK1-NEXT: br label [[COND_END]]			// CHECK1-NEXT: br label [[COND_END]]
	// CHECK1: cond.end:			// CHECK1: cond.end:
	// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 999, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]			// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 999, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
	// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK1-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK1-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK1: omp.inner.for.cond:			// CHECK1: omp.inner.for.cond:
	// CHECK1-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15
	// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK1: omp.inner.for.body:			// CHECK1: omp.inner.for.body:
	// CHECK1-NEXT: call void @__kmpc_push_proc_bind(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 3)			// CHECK1-NEXT: call void @__kmpc_push_proc_bind(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 3), !llvm.access.group !15
	// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !15
	// CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64			// CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
	// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15
	// CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK1-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..3 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]])			// CHECK1-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..3 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !15
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK1: omp.inner.for.inc:			// CHECK1: omp.inner.for.inc:
	// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !15
	// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]			// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
	// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]]
	// CHECK1: omp.inner.for.end:			// CHECK1: omp.inner.for.end:
	// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK1: omp.loop.exit:			// CHECK1: omp.loop.exit:
	// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])			// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
	// CHECK1-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK1-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK1-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0			// CHECK1-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
	// CHECK1-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK1-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK1: .omp.final.then:			// CHECK1: .omp.final.then:
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	// CHECK1-NEXT: br label [[COND_END]]			// CHECK1-NEXT: br label [[COND_END]]
	// CHECK1: cond.end:			// CHECK1: cond.end:
	// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 999, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]			// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 999, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
	// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK1-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK1: omp.inner.for.cond:			// CHECK1: omp.inner.for.cond:
	// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK1-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK1-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !18
	// CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK1: omp.inner.for.body:			// CHECK1: omp.inner.for.body:
	// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !18
	// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK1: omp.body.continue:			// CHECK1: omp.body.continue:
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK1: omp.inner.for.inc:			// CHECK1: omp.inner.for.inc:
	// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]
	// CHECK1: omp.inner.for.end:			// CHECK1: omp.inner.for.end:
	// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK1: omp.loop.exit:			// CHECK1: omp.loop.exit:
	// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])			// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
	// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK1-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK1-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK1-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK1-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK1: .omp.final.then:			// CHECK1: .omp.final.then:
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	// CHECK1-NEXT: br label [[COND_END]]			// CHECK1-NEXT: br label [[COND_END]]
	// CHECK1: cond.end:			// CHECK1: cond.end:
	// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 999, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]			// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 999, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
	// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK1-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK1-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK1: omp.inner.for.cond:			// CHECK1: omp.inner.for.cond:
	// CHECK1-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !21
	// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !21
	// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK1: omp.inner.for.body:			// CHECK1: omp.inner.for.body:
	// CHECK1-NEXT: call void @__kmpc_push_proc_bind(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 2)			// CHECK1-NEXT: call void @__kmpc_push_proc_bind(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 2), !llvm.access.group !21
	// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !21
	// CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64			// CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
	// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !21
	// CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK1-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..5 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]])			// CHECK1-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..5 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !21
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK1: omp.inner.for.inc:			// CHECK1: omp.inner.for.inc:
	// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !21
	// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !21
	// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]			// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
	// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]]
	// CHECK1: omp.inner.for.end:			// CHECK1: omp.inner.for.end:
	// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK1: omp.loop.exit:			// CHECK1: omp.loop.exit:
	// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])			// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
	// CHECK1-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK1-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK1-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0			// CHECK1-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
	// CHECK1-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK1-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK1: .omp.final.then:			// CHECK1: .omp.final.then:
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	// CHECK1-NEXT: br label [[COND_END]]			// CHECK1-NEXT: br label [[COND_END]]
	// CHECK1: cond.end:			// CHECK1: cond.end:
	// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 999, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]			// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 999, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
	// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK1-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK1: omp.inner.for.cond:			// CHECK1: omp.inner.for.cond:
	// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !24
	// CHECK1-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK1-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !24
	// CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK1: omp.inner.for.body:			// CHECK1: omp.inner.for.body:
	// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !24
	// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !24
	// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK1: omp.body.continue:			// CHECK1: omp.body.continue:
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK1: omp.inner.for.inc:			// CHECK1: omp.inner.for.inc:
	// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !24
	// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]]
	// CHECK1: omp.inner.for.end:			// CHECK1: omp.inner.for.end:
	// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK1: omp.loop.exit:			// CHECK1: omp.loop.exit:
	// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])			// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
	// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK1-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK1-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK1-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK1-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK1: .omp.final.then:			// CHECK1: .omp.final.then:
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	// CHECK2-NEXT: br label [[COND_END]]			// CHECK2-NEXT: br label [[COND_END]]
	// CHECK2: cond.end:			// CHECK2: cond.end:
	// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 999, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]			// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 999, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
	// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK2-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK2-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK2-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK2: omp.inner.for.cond:			// CHECK2: omp.inner.for.cond:
	// CHECK2-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !6
	// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !6
	// CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK2: omp.inner.for.body:			// CHECK2: omp.inner.for.body:
	// CHECK2-NEXT: call void @__kmpc_push_proc_bind(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 4)			// CHECK2-NEXT: call void @__kmpc_push_proc_bind(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 4), !llvm.access.group !6
	// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !6
	// CHECK2-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64			// CHECK2-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
	// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !6
	// CHECK2-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK2-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK2-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..1 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]])			// CHECK2-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..1 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !6
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK2: omp.inner.for.inc:			// CHECK2: omp.inner.for.inc:
	// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !6
	// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !6
	// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]			// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
	// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]
	// CHECK2: omp.inner.for.end:			// CHECK2: omp.inner.for.end:
	// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK2: omp.loop.exit:			// CHECK2: omp.loop.exit:
	// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])			// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
	// CHECK2-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK2-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK2-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0			// CHECK2-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
	// CHECK2-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK2-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK2: .omp.final.then:			// CHECK2: .omp.final.then:
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	// CHECK2-NEXT: br label [[COND_END]]			// CHECK2-NEXT: br label [[COND_END]]
	// CHECK2: cond.end:			// CHECK2: cond.end:
	// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 999, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]			// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 999, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
	// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK2-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK2: omp.inner.for.cond:			// CHECK2: omp.inner.for.cond:
	// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK2-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK2-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !10
	// CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK2: omp.inner.for.body:			// CHECK2: omp.inner.for.body:
	// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10
	// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK2: omp.body.continue:			// CHECK2: omp.body.continue:
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK2: omp.inner.for.inc:			// CHECK2: omp.inner.for.inc:
	// CHECK2-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]
	// CHECK2: omp.inner.for.end:			// CHECK2: omp.inner.for.end:
	// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK2: omp.loop.exit:			// CHECK2: omp.loop.exit:
	// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])			// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
	// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK2-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK2-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK2-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK2-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK2: .omp.final.then:			// CHECK2: .omp.final.then:
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	// CHECK2-NEXT: br label [[COND_END]]			// CHECK2-NEXT: br label [[COND_END]]
	// CHECK2: cond.end:			// CHECK2: cond.end:
	// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 999, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]			// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 999, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
	// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK2-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK2-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK2-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK2: omp.inner.for.cond:			// CHECK2: omp.inner.for.cond:
	// CHECK2-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15
	// CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK2: omp.inner.for.body:			// CHECK2: omp.inner.for.body:
	// CHECK2-NEXT: call void @__kmpc_push_proc_bind(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 3)			// CHECK2-NEXT: call void @__kmpc_push_proc_bind(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 3), !llvm.access.group !15
	// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !15
	// CHECK2-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64			// CHECK2-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
	// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15
	// CHECK2-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK2-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK2-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..3 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]])			// CHECK2-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..3 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !15
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK2: omp.inner.for.inc:			// CHECK2: omp.inner.for.inc:
	// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !15
	// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]			// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
	// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]]
	// CHECK2: omp.inner.for.end:			// CHECK2: omp.inner.for.end:
	// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK2: omp.loop.exit:			// CHECK2: omp.loop.exit:
	// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])			// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
	// CHECK2-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK2-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK2-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0			// CHECK2-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
	// CHECK2-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK2-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK2: .omp.final.then:			// CHECK2: .omp.final.then:
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	// CHECK2-NEXT: br label [[COND_END]]			// CHECK2-NEXT: br label [[COND_END]]
	// CHECK2: cond.end:			// CHECK2: cond.end:
	// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 999, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]			// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 999, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
	// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK2-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK2: omp.inner.for.cond:			// CHECK2: omp.inner.for.cond:
	// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK2-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK2-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !18
	// CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK2: omp.inner.for.body:			// CHECK2: omp.inner.for.body:
	// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !18
	// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK2: omp.body.continue:			// CHECK2: omp.body.continue:
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK2: omp.inner.for.inc:			// CHECK2: omp.inner.for.inc:
	// CHECK2-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]
	// CHECK2: omp.inner.for.end:			// CHECK2: omp.inner.for.end:
	// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK2: omp.loop.exit:			// CHECK2: omp.loop.exit:
	// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])			// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
	// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK2-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK2-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK2-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK2-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK2: .omp.final.then:			// CHECK2: .omp.final.then:
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	// CHECK2-NEXT: br label [[COND_END]]			// CHECK2-NEXT: br label [[COND_END]]
	// CHECK2: cond.end:			// CHECK2: cond.end:
	// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 999, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]			// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 999, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
	// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK2-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK2-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK2-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK2: omp.inner.for.cond:			// CHECK2: omp.inner.for.cond:
	// CHECK2-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !21
	// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !21
	// CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK2: omp.inner.for.body:			// CHECK2: omp.inner.for.body:
	// CHECK2-NEXT: call void @__kmpc_push_proc_bind(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 2)			// CHECK2-NEXT: call void @__kmpc_push_proc_bind(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 2), !llvm.access.group !21
	// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !21
	// CHECK2-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64			// CHECK2-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
	// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !21
	// CHECK2-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK2-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK2-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..5 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]])			// CHECK2-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..5 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !21
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK2: omp.inner.for.inc:			// CHECK2: omp.inner.for.inc:
	// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !21
	// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !21
	// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]			// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
	// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]]
	// CHECK2: omp.inner.for.end:			// CHECK2: omp.inner.for.end:
	// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK2: omp.loop.exit:			// CHECK2: omp.loop.exit:
	// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])			// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
	// CHECK2-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK2-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK2-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0			// CHECK2-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
	// CHECK2-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK2-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK2: .omp.final.then:			// CHECK2: .omp.final.then:
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	// CHECK2-NEXT: br label [[COND_END]]			// CHECK2-NEXT: br label [[COND_END]]
	// CHECK2: cond.end:			// CHECK2: cond.end:
	// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 999, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]			// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 999, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
	// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK2-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK2: omp.inner.for.cond:			// CHECK2: omp.inner.for.cond:
	// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !24
	// CHECK2-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK2-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !24
	// CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK2: omp.inner.for.body:			// CHECK2: omp.inner.for.body:
	// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !24
	// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !24
	// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK2: omp.body.continue:			// CHECK2: omp.body.continue:
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK2: omp.inner.for.inc:			// CHECK2: omp.inner.for.inc:
	// CHECK2-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !24
	// CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]]
	// CHECK2: omp.inner.for.end:			// CHECK2: omp.inner.for.end:
	// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK2: omp.loop.exit:			// CHECK2: omp.loop.exit:
	// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])			// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
	// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK2-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK2-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK2-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK2-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK2: .omp.final.then:			// CHECK2: .omp.final.then:
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clang/test/OpenMP/teams_distribute_parallel_for_simd_reduction_codegen.cpp

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	// CHECK1-NEXT: br label [[COND_END]]			// CHECK1-NEXT: br label [[COND_END]]
	// CHECK1: cond.end:			// CHECK1: cond.end:
	// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]			// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
	// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK1-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK1-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK1-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK1: omp.inner.for.cond:			// CHECK1: omp.inner.for.cond:
	// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5
	// CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK1: omp.inner.for.body:			// CHECK1: omp.inner.for.body:
	// CHECK1-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK1-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !5
	// CHECK1-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64			// CHECK1-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
	// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5
	// CHECK1-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64			// CHECK1-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
	// CHECK1-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i32) @.omp_outlined..1 to void (i32, i32, ...)), i64 [[TMP9]], i64 [[TMP11]], i32 [[SIVAR1]])			// CHECK1-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i32) @.omp_outlined..1 to void (i32, i32, ...)), i64 [[TMP9]], i64 [[TMP11]], i32 [[SIVAR1]]), !llvm.access.group !5
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK1: omp.inner.for.inc:			// CHECK1: omp.inner.for.inc:
	// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK1-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK1-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !5
	// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]			// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]
	// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]
	// CHECK1: omp.inner.for.end:			// CHECK1: omp.inner.for.end:
	// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK1: omp.loop.exit:			// CHECK1: omp.loop.exit:
	// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])			// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
	// CHECK1-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK1-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK1-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0			// CHECK1-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0
	// CHECK1-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK1-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK1: .omp.final.then:			// CHECK1: .omp.final.then:
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	// CHECK1-NEXT: br label [[COND_END]]			// CHECK1-NEXT: br label [[COND_END]]
	// CHECK1: cond.end:			// CHECK1: cond.end:
	// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ]			// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ]
	// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK1-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK1: omp.inner.for.cond:			// CHECK1: omp.inner.for.cond:
	// CHECK1-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !9
	// CHECK1-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]			// CHECK1-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
	// CHECK1-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK1-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK1: omp.inner.for.body:			// CHECK1: omp.inner.for.body:
	// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1			// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
	// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9
	// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4			// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !9
	// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32 [[SIVAR2]], align 4			// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32 [[SIVAR2]], align 4, !llvm.access.group !9
	// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], [[TMP11]]			// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], [[TMP11]]
	// CHECK1-NEXT: store i32 [[ADD4]], i32* [[SIVAR2]], align 4			// CHECK1-NEXT: store i32 [[ADD4]], i32* [[SIVAR2]], align 4, !llvm.access.group !9
	// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK1: omp.body.continue:			// CHECK1: omp.body.continue:
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK1: omp.inner.for.inc:			// CHECK1: omp.inner.for.inc:
	// CHECK1-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP13]], 1			// CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP13]], 1
	// CHECK1-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]
	// CHECK1: omp.inner.for.end:			// CHECK1: omp.inner.for.end:
	// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK1: omp.loop.exit:			// CHECK1: omp.loop.exit:
	// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]])			// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]])
	// CHECK1-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK1-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK1-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0			// CHECK1-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0
	// CHECK1-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK1-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK1: .omp.final.then:			// CHECK1: .omp.final.then:
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	// CHECK1-NEXT: br label [[COND_END]]			// CHECK1-NEXT: br label [[COND_END]]
	// CHECK1: cond.end:			// CHECK1: cond.end:
	// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]			// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
	// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK1-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK1-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK1-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK1: omp.inner.for.cond:			// CHECK1: omp.inner.for.cond:
	// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !14
	// CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK1: omp.inner.for.body:			// CHECK1: omp.inner.for.body:
	// CHECK1-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK1-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !14
	// CHECK1-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64			// CHECK1-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
	// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !14
	// CHECK1-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64			// CHECK1-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
	// CHECK1-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i32) @.omp_outlined..4 to void (i32, i32, ...)), i64 [[TMP9]], i64 [[TMP11]], i32 [[T_VAR1]])			// CHECK1-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i32) @.omp_outlined..4 to void (i32, i32, ...)), i64 [[TMP9]], i64 [[TMP11]], i32 [[T_VAR1]]), !llvm.access.group !14
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK1: omp.inner.for.inc:			// CHECK1: omp.inner.for.inc:
	// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK1-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK1-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !14
	// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]			// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]
	// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]]
	// CHECK1: omp.inner.for.end:			// CHECK1: omp.inner.for.end:
	// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK1: omp.loop.exit:			// CHECK1: omp.loop.exit:
	// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])			// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
	// CHECK1-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK1-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK1-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0			// CHECK1-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0
	// CHECK1-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK1-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK1: .omp.final.then:			// CHECK1: .omp.final.then:
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	// CHECK1-NEXT: br label [[COND_END]]			// CHECK1-NEXT: br label [[COND_END]]
	// CHECK1: cond.end:			// CHECK1: cond.end:
	// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ]			// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ]
	// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK1-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK1: omp.inner.for.cond:			// CHECK1: omp.inner.for.cond:
	// CHECK1-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !17
	// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !17
	// CHECK1-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]			// CHECK1-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
	// CHECK1-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK1-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK1: omp.inner.for.body:			// CHECK1: omp.inner.for.body:
	// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !17
	// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1			// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
	// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !17
	// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4			// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !17
	// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32 [[T_VAR2]], align 4			// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32 [[T_VAR2]], align 4, !llvm.access.group !17
	// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], [[TMP11]]			// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], [[TMP11]]
	// CHECK1-NEXT: store i32 [[ADD4]], i32* [[T_VAR2]], align 4			// CHECK1-NEXT: store i32 [[ADD4]], i32* [[T_VAR2]], align 4, !llvm.access.group !17
	// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK1: omp.body.continue:			// CHECK1: omp.body.continue:
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK1: omp.inner.for.inc:			// CHECK1: omp.inner.for.inc:
	// CHECK1-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !17
	// CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP13]], 1			// CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP13]], 1
	// CHECK1-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]]
	// CHECK1: omp.inner.for.end:			// CHECK1: omp.inner.for.end:
	// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK1: omp.loop.exit:			// CHECK1: omp.loop.exit:
	// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]])			// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]])
	// CHECK1-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK1-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK1-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0			// CHECK1-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0
	// CHECK1-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK1-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK1: .omp.final.then:			// CHECK1: .omp.final.then:
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	// CHECK2-NEXT: br label [[COND_END]]			// CHECK2-NEXT: br label [[COND_END]]
	// CHECK2: cond.end:			// CHECK2: cond.end:
	// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]			// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
	// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK2-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK2-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK2-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK2: omp.inner.for.cond:			// CHECK2: omp.inner.for.cond:
	// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5
	// CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK2: omp.inner.for.body:			// CHECK2: omp.inner.for.body:
	// CHECK2-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK2-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !5
	// CHECK2-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64			// CHECK2-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
	// CHECK2-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK2-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5
	// CHECK2-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64			// CHECK2-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
	// CHECK2-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i32) @.omp_outlined..1 to void (i32, i32, ...)), i64 [[TMP9]], i64 [[TMP11]], i32 [[SIVAR1]])			// CHECK2-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i32) @.omp_outlined..1 to void (i32, i32, ...)), i64 [[TMP9]], i64 [[TMP11]], i32 [[SIVAR1]]), !llvm.access.group !5
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK2: omp.inner.for.inc:			// CHECK2: omp.inner.for.inc:
	// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK2-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK2-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !5
	// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]			// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]
	// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]
	// CHECK2: omp.inner.for.end:			// CHECK2: omp.inner.for.end:
	// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK2: omp.loop.exit:			// CHECK2: omp.loop.exit:
	// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])			// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
	// CHECK2-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK2-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK2-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0			// CHECK2-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0
	// CHECK2-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK2-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK2: .omp.final.then:			// CHECK2: .omp.final.then:
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	// CHECK2-NEXT: br label [[COND_END]]			// CHECK2-NEXT: br label [[COND_END]]
	// CHECK2: cond.end:			// CHECK2: cond.end:
	// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ]			// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ]
	// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK2-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK2: omp.inner.for.cond:			// CHECK2: omp.inner.for.cond:
	// CHECK2-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !9
	// CHECK2-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]			// CHECK2-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
	// CHECK2-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK2-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK2: omp.inner.for.body:			// CHECK2: omp.inner.for.body:
	// CHECK2-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1			// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
	// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9
	// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4			// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !9
	// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32 [[SIVAR2]], align 4			// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32 [[SIVAR2]], align 4, !llvm.access.group !9
	// CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], [[TMP11]]			// CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], [[TMP11]]
	// CHECK2-NEXT: store i32 [[ADD4]], i32* [[SIVAR2]], align 4			// CHECK2-NEXT: store i32 [[ADD4]], i32* [[SIVAR2]], align 4, !llvm.access.group !9
	// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK2: omp.body.continue:			// CHECK2: omp.body.continue:
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK2: omp.inner.for.inc:			// CHECK2: omp.inner.for.inc:
	// CHECK2-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK2-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP13]], 1			// CHECK2-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP13]], 1
	// CHECK2-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]
	// CHECK2: omp.inner.for.end:			// CHECK2: omp.inner.for.end:
	// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK2: omp.loop.exit:			// CHECK2: omp.loop.exit:
	// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]])			// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]])
	// CHECK2-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK2-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK2-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0			// CHECK2-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0
	// CHECK2-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK2-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK2: .omp.final.then:			// CHECK2: .omp.final.then:
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	// CHECK2-NEXT: br label [[COND_END]]			// CHECK2-NEXT: br label [[COND_END]]
	// CHECK2: cond.end:			// CHECK2: cond.end:
	// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]			// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
	// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK2-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK2-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK2-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK2: omp.inner.for.cond:			// CHECK2: omp.inner.for.cond:
	// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !14
	// CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK2: omp.inner.for.body:			// CHECK2: omp.inner.for.body:
	// CHECK2-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK2-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !14
	// CHECK2-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64			// CHECK2-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
	// CHECK2-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK2-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !14
	// CHECK2-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64			// CHECK2-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
	// CHECK2-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i32) @.omp_outlined..4 to void (i32, i32, ...)), i64 [[TMP9]], i64 [[TMP11]], i32 [[T_VAR1]])			// CHECK2-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i32) @.omp_outlined..4 to void (i32, i32, ...)), i64 [[TMP9]], i64 [[TMP11]], i32 [[T_VAR1]]), !llvm.access.group !14
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK2: omp.inner.for.inc:			// CHECK2: omp.inner.for.inc:
	// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK2-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK2-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !14
	// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]			// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]
	// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]]
	// CHECK2: omp.inner.for.end:			// CHECK2: omp.inner.for.end:
	// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK2: omp.loop.exit:			// CHECK2: omp.loop.exit:
	// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])			// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
	// CHECK2-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK2-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK2-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0			// CHECK2-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0
	// CHECK2-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK2-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK2: .omp.final.then:			// CHECK2: .omp.final.then:
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	// CHECK2-NEXT: br label [[COND_END]]			// CHECK2-NEXT: br label [[COND_END]]
	// CHECK2: cond.end:			// CHECK2: cond.end:
	// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ]			// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ]
	// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK2-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK2: omp.inner.for.cond:			// CHECK2: omp.inner.for.cond:
	// CHECK2-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !17
	// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !17
	// CHECK2-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]			// CHECK2-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
	// CHECK2-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK2-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK2: omp.inner.for.body:			// CHECK2: omp.inner.for.body:
	// CHECK2-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !17
	// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1			// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
	// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !17
	// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4			// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !17
	// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32 [[T_VAR2]], align 4			// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32 [[T_VAR2]], align 4, !llvm.access.group !17
	// CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], [[TMP11]]			// CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], [[TMP11]]
	// CHECK2-NEXT: store i32 [[ADD4]], i32* [[T_VAR2]], align 4			// CHECK2-NEXT: store i32 [[ADD4]], i32* [[T_VAR2]], align 4, !llvm.access.group !17
	// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK2: omp.body.continue:			// CHECK2: omp.body.continue:
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK2: omp.inner.for.inc:			// CHECK2: omp.inner.for.inc:
	// CHECK2-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !17
	// CHECK2-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP13]], 1			// CHECK2-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP13]], 1
	// CHECK2-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]]
	// CHECK2: omp.inner.for.end:			// CHECK2: omp.inner.for.end:
	// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK2: omp.loop.exit:			// CHECK2: omp.loop.exit:
	// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]])			// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]])
	// CHECK2-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK2-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK2-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0			// CHECK2-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0
	// CHECK2-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK2-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK2: .omp.final.then:			// CHECK2: .omp.final.then:
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	// CHECK3-NEXT: br label [[COND_END]]			// CHECK3-NEXT: br label [[COND_END]]
	// CHECK3: cond.end:			// CHECK3: cond.end:
	// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]			// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
	// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK3-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK3-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK3-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK3-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK3: omp.inner.for.cond:			// CHECK3: omp.inner.for.cond:
	// CHECK3-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK3-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !6
	// CHECK3-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK3-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !6
	// CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK3: omp.inner.for.body:			// CHECK3: omp.inner.for.body:
	// CHECK3-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK3-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !6
	// CHECK3-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK3-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !6
	// CHECK3-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i32, i32, i32) @.omp_outlined..1 to void (i32, i32, ...)), i32 [[TMP8]], i32 [[TMP9]], i32 [[SIVAR1]])			// CHECK3-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i32, i32, i32) @.omp_outlined..1 to void (i32, i32, ...)), i32 [[TMP8]], i32 [[TMP9]], i32 [[SIVAR1]]), !llvm.access.group !6
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK3: omp.inner.for.inc:			// CHECK3: omp.inner.for.inc:
	// CHECK3-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK3-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !6
	// CHECK3-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK3-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !6
	// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP10]], [[TMP11]]			// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP10]], [[TMP11]]
	// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]
	// CHECK3: omp.inner.for.end:			// CHECK3: omp.inner.for.end:
	// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK3: omp.loop.exit:			// CHECK3: omp.loop.exit:
	// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])			// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
	// CHECK3-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK3-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK3-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0			// CHECK3-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0
	// CHECK3-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK3-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK3: .omp.final.then:			// CHECK3: .omp.final.then:
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	// CHECK3-NEXT: br label [[COND_END]]			// CHECK3-NEXT: br label [[COND_END]]
	// CHECK3: cond.end:			// CHECK3: cond.end:
	// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ]			// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ]
	// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK3-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK3-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK3-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4			// CHECK3-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK3: omp.inner.for.cond:			// CHECK3: omp.inner.for.cond:
	// CHECK3-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK3-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK3-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK3-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !10
	// CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]			// CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
	// CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK3: omp.inner.for.body:			// CHECK3: omp.inner.for.body:
	// CHECK3-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK3-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1			// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
	// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10
	// CHECK3-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4			// CHECK3-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !10
	// CHECK3-NEXT: [[TMP12:%.]] = load i32, i32 [[SIVAR1]], align 4			// CHECK3-NEXT: [[TMP12:%.]] = load i32, i32 [[SIVAR1]], align 4, !llvm.access.group !10
	// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], [[TMP11]]			// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], [[TMP11]]
	// CHECK3-NEXT: store i32 [[ADD3]], i32* [[SIVAR1]], align 4			// CHECK3-NEXT: store i32 [[ADD3]], i32* [[SIVAR1]], align 4, !llvm.access.group !10
	// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK3: omp.body.continue:			// CHECK3: omp.body.continue:
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK3: omp.inner.for.inc:			// CHECK3: omp.inner.for.inc:
	// CHECK3-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK3-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], 1			// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], 1
	// CHECK3-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4			// CHECK3-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]
	// CHECK3: omp.inner.for.end:			// CHECK3: omp.inner.for.end:
	// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK3: omp.loop.exit:			// CHECK3: omp.loop.exit:
	// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]])			// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]])
	// CHECK3-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK3-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK3-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0			// CHECK3-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0
	// CHECK3-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK3-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK3: .omp.final.then:			// CHECK3: .omp.final.then:
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	// CHECK3-NEXT: br label [[COND_END]]			// CHECK3-NEXT: br label [[COND_END]]
	// CHECK3: cond.end:			// CHECK3: cond.end:
	// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]			// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
	// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK3-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK3-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK3-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK3-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK3: omp.inner.for.cond:			// CHECK3: omp.inner.for.cond:
	// CHECK3-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK3-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK3-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK3-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15
	// CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK3: omp.inner.for.body:			// CHECK3: omp.inner.for.body:
	// CHECK3-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK3-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !15
	// CHECK3-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK3-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15
	// CHECK3-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i32, i32, i32) @.omp_outlined..4 to void (i32, i32, ...)), i32 [[TMP8]], i32 [[TMP9]], i32 [[T_VAR1]])			// CHECK3-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i32, i32, i32) @.omp_outlined..4 to void (i32, i32, ...)), i32 [[TMP8]], i32 [[TMP9]], i32 [[T_VAR1]]), !llvm.access.group !15
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK3: omp.inner.for.inc:			// CHECK3: omp.inner.for.inc:
	// CHECK3-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK3-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK3-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK3-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !15
	// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP10]], [[TMP11]]			// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP10]], [[TMP11]]
	// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]]
	// CHECK3: omp.inner.for.end:			// CHECK3: omp.inner.for.end:
	// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK3: omp.loop.exit:			// CHECK3: omp.loop.exit:
	// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])			// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
	// CHECK3-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK3-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK3-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0			// CHECK3-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0
	// CHECK3-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK3-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK3: .omp.final.then:			// CHECK3: .omp.final.then:
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	// CHECK3-NEXT: br label [[COND_END]]			// CHECK3-NEXT: br label [[COND_END]]
	// CHECK3: cond.end:			// CHECK3: cond.end:
	// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ]			// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ]
	// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK3-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK3-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK3-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4			// CHECK3-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK3: omp.inner.for.cond:			// CHECK3: omp.inner.for.cond:
	// CHECK3-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK3-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK3-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK3-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !18
	// CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]			// CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
	// CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK3: omp.inner.for.body:			// CHECK3: omp.inner.for.body:
	// CHECK3-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK3-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1			// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
	// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !18
	// CHECK3-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4			// CHECK3-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !18
	// CHECK3-NEXT: [[TMP12:%.]] = load i32, i32 [[T_VAR1]], align 4			// CHECK3-NEXT: [[TMP12:%.]] = load i32, i32 [[T_VAR1]], align 4, !llvm.access.group !18
	// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], [[TMP11]]			// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], [[TMP11]]
	// CHECK3-NEXT: store i32 [[ADD3]], i32* [[T_VAR1]], align 4			// CHECK3-NEXT: store i32 [[ADD3]], i32* [[T_VAR1]], align 4, !llvm.access.group !18
	// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK3: omp.body.continue:			// CHECK3: omp.body.continue:
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK3: omp.inner.for.inc:			// CHECK3: omp.inner.for.inc:
	// CHECK3-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK3-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], 1			// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], 1
	// CHECK3-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4			// CHECK3-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]
	// CHECK3: omp.inner.for.end:			// CHECK3: omp.inner.for.end:
	// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK3: omp.loop.exit:			// CHECK3: omp.loop.exit:
	// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]])			// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]])
	// CHECK3-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK3-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK3-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0			// CHECK3-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0
	// CHECK3-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK3-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK3: .omp.final.then:			// CHECK3: .omp.final.then:
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	// CHECK4-NEXT: br label [[COND_END]]			// CHECK4-NEXT: br label [[COND_END]]
	// CHECK4: cond.end:			// CHECK4: cond.end:
	// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]			// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
	// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK4-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK4-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK4-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK4-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK4: omp.inner.for.cond:			// CHECK4: omp.inner.for.cond:
	// CHECK4-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK4-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !6
	// CHECK4-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK4-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !6
	// CHECK4-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK4-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK4-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK4-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK4: omp.inner.for.body:			// CHECK4: omp.inner.for.body:
	// CHECK4-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK4-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !6
	// CHECK4-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK4-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !6
	// CHECK4-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i32, i32, i32) @.omp_outlined..1 to void (i32, i32, ...)), i32 [[TMP8]], i32 [[TMP9]], i32 [[SIVAR1]])			// CHECK4-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i32, i32, i32) @.omp_outlined..1 to void (i32, i32, ...)), i32 [[TMP8]], i32 [[TMP9]], i32 [[SIVAR1]]), !llvm.access.group !6
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK4: omp.inner.for.inc:			// CHECK4: omp.inner.for.inc:
	// CHECK4-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK4-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !6
	// CHECK4-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK4-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !6
	// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP10]], [[TMP11]]			// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP10]], [[TMP11]]
	// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]
	// CHECK4: omp.inner.for.end:			// CHECK4: omp.inner.for.end:
	// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK4: omp.loop.exit:			// CHECK4: omp.loop.exit:
	// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])			// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
	// CHECK4-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK4-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK4-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0			// CHECK4-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0
	// CHECK4-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK4-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK4: .omp.final.then:			// CHECK4: .omp.final.then:
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	// CHECK4-NEXT: br label [[COND_END]]			// CHECK4-NEXT: br label [[COND_END]]
	// CHECK4: cond.end:			// CHECK4: cond.end:
	// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ]			// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ]
	// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK4-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK4-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK4-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4			// CHECK4-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK4: omp.inner.for.cond:			// CHECK4: omp.inner.for.cond:
	// CHECK4-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK4-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK4-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK4-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !10
	// CHECK4-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]			// CHECK4-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
	// CHECK4-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK4-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK4: omp.inner.for.body:			// CHECK4: omp.inner.for.body:
	// CHECK4-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK4-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1			// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
	// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10
	// CHECK4-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4			// CHECK4-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !10
	// CHECK4-NEXT: [[TMP12:%.]] = load i32, i32 [[SIVAR1]], align 4			// CHECK4-NEXT: [[TMP12:%.]] = load i32, i32 [[SIVAR1]], align 4, !llvm.access.group !10
	// CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], [[TMP11]]			// CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], [[TMP11]]
	// CHECK4-NEXT: store i32 [[ADD3]], i32* [[SIVAR1]], align 4			// CHECK4-NEXT: store i32 [[ADD3]], i32* [[SIVAR1]], align 4, !llvm.access.group !10
	// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK4: omp.body.continue:			// CHECK4: omp.body.continue:
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK4: omp.inner.for.inc:			// CHECK4: omp.inner.for.inc:
	// CHECK4-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK4-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], 1			// CHECK4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], 1
	// CHECK4-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4			// CHECK4-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]
	// CHECK4: omp.inner.for.end:			// CHECK4: omp.inner.for.end:
	// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK4: omp.loop.exit:			// CHECK4: omp.loop.exit:
	// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]])			// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]])
	// CHECK4-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK4-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK4-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0			// CHECK4-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0
	// CHECK4-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK4-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK4: .omp.final.then:			// CHECK4: .omp.final.then:
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	// CHECK4-NEXT: br label [[COND_END]]			// CHECK4-NEXT: br label [[COND_END]]
	// CHECK4: cond.end:			// CHECK4: cond.end:
	// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]			// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
	// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK4-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK4-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK4-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK4-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK4: omp.inner.for.cond:			// CHECK4: omp.inner.for.cond:
	// CHECK4-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK4-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK4-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK4-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15
	// CHECK4-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK4-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK4-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK4-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK4: omp.inner.for.body:			// CHECK4: omp.inner.for.body:
	// CHECK4-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK4-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !15
	// CHECK4-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK4-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15
	// CHECK4-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i32, i32, i32) @.omp_outlined..4 to void (i32, i32, ...)), i32 [[TMP8]], i32 [[TMP9]], i32 [[T_VAR1]])			// CHECK4-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i32, i32, i32) @.omp_outlined..4 to void (i32, i32, ...)), i32 [[TMP8]], i32 [[TMP9]], i32 [[T_VAR1]]), !llvm.access.group !15
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK4: omp.inner.for.inc:			// CHECK4: omp.inner.for.inc:
	// CHECK4-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK4-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK4-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK4-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !15
	// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP10]], [[TMP11]]			// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP10]], [[TMP11]]
	// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]]
	// CHECK4: omp.inner.for.end:			// CHECK4: omp.inner.for.end:
	// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK4: omp.loop.exit:			// CHECK4: omp.loop.exit:
	// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])			// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
	// CHECK4-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK4-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK4-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0			// CHECK4-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0
	// CHECK4-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK4-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK4: .omp.final.then:			// CHECK4: .omp.final.then:
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	// CHECK4-NEXT: br label [[COND_END]]			// CHECK4-NEXT: br label [[COND_END]]
	// CHECK4: cond.end:			// CHECK4: cond.end:
	// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ]			// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ]
	// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK4-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK4-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK4-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4			// CHECK4-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK4: omp.inner.for.cond:			// CHECK4: omp.inner.for.cond:
	// CHECK4-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK4-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK4-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK4-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !18
	// CHECK4-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]			// CHECK4-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
	// CHECK4-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK4-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK4: omp.inner.for.body:			// CHECK4: omp.inner.for.body:
	// CHECK4-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK4-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1			// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
	// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !18
	// CHECK4-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4			// CHECK4-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !18
	// CHECK4-NEXT: [[TMP12:%.]] = load i32, i32 [[T_VAR1]], align 4			// CHECK4-NEXT: [[TMP12:%.]] = load i32, i32 [[T_VAR1]], align 4, !llvm.access.group !18
	// CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], [[TMP11]]			// CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], [[TMP11]]
	// CHECK4-NEXT: store i32 [[ADD3]], i32* [[T_VAR1]], align 4			// CHECK4-NEXT: store i32 [[ADD3]], i32* [[T_VAR1]], align 4, !llvm.access.group !18
	// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK4: omp.body.continue:			// CHECK4: omp.body.continue:
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK4: omp.inner.for.inc:			// CHECK4: omp.inner.for.inc:
	// CHECK4-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK4-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], 1			// CHECK4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], 1
	// CHECK4-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4			// CHECK4-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]
	// CHECK4: omp.inner.for.end:			// CHECK4: omp.inner.for.end:
	// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK4: omp.loop.exit:			// CHECK4: omp.loop.exit:
	// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]])			// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]])
	// CHECK4-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK4-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK4-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0			// CHECK4-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0
	// CHECK4-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK4-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK4: .omp.final.then:			// CHECK4: .omp.final.then:
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	// CHECK9-NEXT: br label [[COND_END]]			// CHECK9-NEXT: br label [[COND_END]]
	// CHECK9: cond.end:			// CHECK9: cond.end:
	// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]			// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
	// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK9-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK9-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK9: omp.inner.for.cond:			// CHECK9: omp.inner.for.cond:
	// CHECK9-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !4
	// CHECK9-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK9-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !4
	// CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK9: omp.inner.for.body:			// CHECK9: omp.inner.for.body:
	// CHECK9-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK9-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !4
	// CHECK9-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64			// CHECK9-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
	// CHECK9-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK9-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !4
	// CHECK9-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64			// CHECK9-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
	// CHECK9-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i32) @.omp_outlined..1 to void (i32, i32, ...)), i64 [[TMP9]], i64 [[TMP11]], i32 [[SIVAR1]])			// CHECK9-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i32) @.omp_outlined..1 to void (i32, i32, ...)), i64 [[TMP9]], i64 [[TMP11]], i32 [[SIVAR1]]), !llvm.access.group !4
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK9: omp.inner.for.inc:			// CHECK9: omp.inner.for.inc:
	// CHECK9-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !4
	// CHECK9-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK9-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !4
	// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]			// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]
	// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]
	// CHECK9: omp.inner.for.end:			// CHECK9: omp.inner.for.end:
	// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK9: omp.loop.exit:			// CHECK9: omp.loop.exit:
	// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])			// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
	// CHECK9-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK9-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK9-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0			// CHECK9-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0
	// CHECK9-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK9-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK9: .omp.final.then:			// CHECK9: .omp.final.then:
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	// CHECK9-NEXT: br label [[COND_END]]			// CHECK9-NEXT: br label [[COND_END]]
	// CHECK9: cond.end:			// CHECK9: cond.end:
	// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ]			// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ]
	// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK9-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK9-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK9-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4			// CHECK9-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK9: omp.inner.for.cond:			// CHECK9: omp.inner.for.cond:
	// CHECK9-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !8
	// CHECK9-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK9-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !8
	// CHECK9-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]			// CHECK9-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
	// CHECK9-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK9-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK9: omp.inner.for.body:			// CHECK9: omp.inner.for.body:
	// CHECK9-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !8
	// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1			// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
	// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !8
	// CHECK9-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4			// CHECK9-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !8
	// CHECK9-NEXT: [[TMP12:%.]] = load i32, i32 [[SIVAR2]], align 4			// CHECK9-NEXT: [[TMP12:%.]] = load i32, i32 [[SIVAR2]], align 4, !llvm.access.group !8
	// CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], [[TMP11]]			// CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], [[TMP11]]
	// CHECK9-NEXT: store i32 [[ADD4]], i32* [[SIVAR2]], align 4			// CHECK9-NEXT: store i32 [[ADD4]], i32* [[SIVAR2]], align 4, !llvm.access.group !8
	// CHECK9-NEXT: [[TMP13:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 0			// CHECK9-NEXT: [[TMP13:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 0
	// CHECK9-NEXT: store i32* [[SIVAR2]], i32** [[TMP13]], align 8			// CHECK9-NEXT: store i32* [[SIVAR2]], i32** [[TMP13]], align 8, !llvm.access.group !8
	// CHECK9-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(8) [[REF_TMP]])			// CHECK9-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(8) [[REF_TMP]]), !llvm.access.group !8
	// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK9: omp.body.continue:			// CHECK9: omp.body.continue:
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK9: omp.inner.for.inc:			// CHECK9: omp.inner.for.inc:
	// CHECK9-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !8
	// CHECK9-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP14]], 1			// CHECK9-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP14]], 1
	// CHECK9-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4			// CHECK9-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]
	// CHECK9: omp.inner.for.end:			// CHECK9: omp.inner.for.end:
	// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK9: omp.loop.exit:			// CHECK9: omp.loop.exit:
	// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]])			// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]])
	// CHECK9-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK9-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK9-NEXT: [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0			// CHECK9-NEXT: [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0
	// CHECK9-NEXT: br i1 [[TMP16]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK9-NEXT: br i1 [[TMP16]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK9: .omp.final.then:			// CHECK9: .omp.final.then:
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	// CHECK10-NEXT: br label [[COND_END]]			// CHECK10-NEXT: br label [[COND_END]]
	// CHECK10: cond.end:			// CHECK10: cond.end:
	// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]			// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
	// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK10-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK10-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK10-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK10-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK10: omp.inner.for.cond:			// CHECK10: omp.inner.for.cond:
	// CHECK10-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !4
	// CHECK10-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK10-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !4
	// CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK10: omp.inner.for.body:			// CHECK10: omp.inner.for.body:
	// CHECK10-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK10-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !4
	// CHECK10-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64			// CHECK10-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
	// CHECK10-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK10-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !4
	// CHECK10-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64			// CHECK10-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
	// CHECK10-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i32) @.omp_outlined..1 to void (i32, i32, ...)), i64 [[TMP9]], i64 [[TMP11]], i32 [[SIVAR1]])			// CHECK10-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i32) @.omp_outlined..1 to void (i32, i32, ...)), i64 [[TMP9]], i64 [[TMP11]], i32 [[SIVAR1]]), !llvm.access.group !4
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK10: omp.inner.for.inc:			// CHECK10: omp.inner.for.inc:
	// CHECK10-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !4
	// CHECK10-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK10-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !4
	// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]			// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]
	// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]
	// CHECK10: omp.inner.for.end:			// CHECK10: omp.inner.for.end:
	// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK10: omp.loop.exit:			// CHECK10: omp.loop.exit:
	// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])			// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
	// CHECK10-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK10-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK10-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0			// CHECK10-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0
	// CHECK10-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK10-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK10: .omp.final.then:			// CHECK10: .omp.final.then:
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	// CHECK10-NEXT: br label [[COND_END]]			// CHECK10-NEXT: br label [[COND_END]]
	// CHECK10: cond.end:			// CHECK10: cond.end:
	// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ]			// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ]
	// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK10-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK10-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK10-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4			// CHECK10-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK10: omp.inner.for.cond:			// CHECK10: omp.inner.for.cond:
	// CHECK10-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !8
	// CHECK10-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK10-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !8
	// CHECK10-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]			// CHECK10-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
	// CHECK10-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK10-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK10: omp.inner.for.body:			// CHECK10: omp.inner.for.body:
	// CHECK10-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !8
	// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1			// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
	// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !8
	// CHECK10-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4			// CHECK10-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !8
	// CHECK10-NEXT: [[TMP12:%.]] = load i32, i32 [[SIVAR2]], align 4			// CHECK10-NEXT: [[TMP12:%.]] = load i32, i32 [[SIVAR2]], align 4, !llvm.access.group !8
	// CHECK10-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], [[TMP11]]			// CHECK10-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], [[TMP11]]
	// CHECK10-NEXT: store i32 [[ADD4]], i32* [[SIVAR2]], align 4			// CHECK10-NEXT: store i32 [[ADD4]], i32* [[SIVAR2]], align 4, !llvm.access.group !8
	// CHECK10-NEXT: [[TMP13:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 0			// CHECK10-NEXT: [[TMP13:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 0
	// CHECK10-NEXT: store i32* [[SIVAR2]], i32** [[TMP13]], align 8			// CHECK10-NEXT: store i32* [[SIVAR2]], i32** [[TMP13]], align 8, !llvm.access.group !8
	// CHECK10-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(8) [[REF_TMP]])			// CHECK10-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(8) [[REF_TMP]]), !llvm.access.group !8
	// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK10: omp.body.continue:			// CHECK10: omp.body.continue:
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK10: omp.inner.for.inc:			// CHECK10: omp.inner.for.inc:
	// CHECK10-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !8
	// CHECK10-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP14]], 1			// CHECK10-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP14]], 1
	// CHECK10-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4			// CHECK10-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]
	// CHECK10: omp.inner.for.end:			// CHECK10: omp.inner.for.end:
	// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK10: omp.loop.exit:			// CHECK10: omp.loop.exit:
	// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]])			// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]])
	// CHECK10-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK10-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK10-NEXT: [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0			// CHECK10-NEXT: [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0
	// CHECK10-NEXT: br i1 [[TMP16]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK10-NEXT: br i1 [[TMP16]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK10: .omp.final.then:			// CHECK10: .omp.final.then:
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clang/test/OpenMP/teams_distribute_reduction_codegen.cpp

	Show First 20 Lines • Show All 1,693 Lines • ▼ Show 20 Lines
	//			//
	//			//
	// CHECK10-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg			// CHECK10-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
	// CHECK10-SAME: () #[[ATTR6:[0-9]+]] {			// CHECK10-SAME: () #[[ATTR6:[0-9]+]] {
	// CHECK10-NEXT: entry:			// CHECK10-NEXT: entry:
	// CHECK10-NEXT: call void @__tgt_register_requires(i64 1)			// CHECK10-NEXT: call void @__tgt_register_requires(i64 1)
	// CHECK10-NEXT: ret void			// CHECK10-NEXT: ret void
	//			//
	//
	No newline at end of file

clang/test/OpenMP/teams_distribute_simd_collapse_codegen.cpp

	Show First 20 Lines • Show All 188 Lines • ▼ Show 20 Lines
	// CHECK1-NEXT: br label [[COND_END]]			// CHECK1-NEXT: br label [[COND_END]]
	// CHECK1: cond.end:			// CHECK1: cond.end:
	// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 56087, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]			// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 56087, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
	// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK1-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK1-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK1-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK1: omp.inner.for.cond:			// CHECK1: omp.inner.for.cond:
	// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !4
	// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !4
	// CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK1: omp.inner.for.body:			// CHECK1: omp.inner.for.body:
	// CHECK1-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !4
	// CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP8]], 456			// CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP8]], 456
	// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1			// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1
	// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !4
	// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !4
	// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !4
	// CHECK1-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP10]], 456			// CHECK1-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP10]], 456
	// CHECK1-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 456			// CHECK1-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 456
	// CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP9]], [[MUL4]]			// CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP9]], [[MUL4]]
	// CHECK1-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1			// CHECK1-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1
	// CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]]			// CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]]
	// CHECK1-NEXT: store i32 [[ADD6]], i32* [[J]], align 4			// CHECK1-NEXT: store i32 [[ADD6]], i32* [[J]], align 4, !llvm.access.group !4
	// CHECK1-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 0			// CHECK1-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 0
	// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4			// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !4
	// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64			// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64
	// CHECK1-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]] [[A]], i64 0, i64 [[IDXPROM]]			// CHECK1-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]] [[A]], i64 0, i64 [[IDXPROM]]
	// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32 [[J]], align 4			// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32 [[J]], align 4, !llvm.access.group !4
	// CHECK1-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP12]] to i64			// CHECK1-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP12]] to i64
	// CHECK1-NEXT: [[ARRAYIDX8:%.]] = getelementptr inbounds [456 x i32], [456 x i32] [[ARRAYIDX]], i64 0, i64 [[IDXPROM7]]			// CHECK1-NEXT: [[ARRAYIDX8:%.]] = getelementptr inbounds [456 x i32], [456 x i32] [[ARRAYIDX]], i64 0, i64 [[IDXPROM7]]
	// CHECK1-NEXT: store i32 0, i32* [[ARRAYIDX8]], align 4			// CHECK1-NEXT: store i32 0, i32* [[ARRAYIDX8]], align 4, !llvm.access.group !4
	// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK1: omp.body.continue:			// CHECK1: omp.body.continue:
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK1: omp.inner.for.inc:			// CHECK1: omp.inner.for.inc:
	// CHECK1-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !4
	// CHECK1-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP13]], 1			// CHECK1-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP13]], 1
	// CHECK1-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]
	// CHECK1: omp.inner.for.end:			// CHECK1: omp.inner.for.end:
	// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK1: omp.loop.exit:			// CHECK1: omp.loop.exit:
	// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])			// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
	// CHECK1-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK1-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK1-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0			// CHECK1-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0
	// CHECK1-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK1-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK1: .omp.final.then:			// CHECK1: .omp.final.then:
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	// CHECK2-NEXT: br label [[COND_END]]			// CHECK2-NEXT: br label [[COND_END]]
	// CHECK2: cond.end:			// CHECK2: cond.end:
	// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 56087, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]			// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 56087, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
	// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK2-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK2-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK2-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK2: omp.inner.for.cond:			// CHECK2: omp.inner.for.cond:
	// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !4
	// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !4
	// CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK2: omp.inner.for.body:			// CHECK2: omp.inner.for.body:
	// CHECK2-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !4
	// CHECK2-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP8]], 456			// CHECK2-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP8]], 456
	// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1			// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1
	// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !4
	// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !4
	// CHECK2-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !4
	// CHECK2-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP10]], 456			// CHECK2-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP10]], 456
	// CHECK2-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 456			// CHECK2-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 456
	// CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP9]], [[MUL4]]			// CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP9]], [[MUL4]]
	// CHECK2-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1			// CHECK2-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1
	// CHECK2-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]]			// CHECK2-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]]
	// CHECK2-NEXT: store i32 [[ADD6]], i32* [[J]], align 4			// CHECK2-NEXT: store i32 [[ADD6]], i32* [[J]], align 4, !llvm.access.group !4
	// CHECK2-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 0			// CHECK2-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 0
	// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4			// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !4
	// CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64			// CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64
	// CHECK2-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]] [[A]], i64 0, i64 [[IDXPROM]]			// CHECK2-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]] [[A]], i64 0, i64 [[IDXPROM]]
	// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32 [[J]], align 4			// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32 [[J]], align 4, !llvm.access.group !4
	// CHECK2-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP12]] to i64			// CHECK2-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP12]] to i64
	// CHECK2-NEXT: [[ARRAYIDX8:%.]] = getelementptr inbounds [456 x i32], [456 x i32] [[ARRAYIDX]], i64 0, i64 [[IDXPROM7]]			// CHECK2-NEXT: [[ARRAYIDX8:%.]] = getelementptr inbounds [456 x i32], [456 x i32] [[ARRAYIDX]], i64 0, i64 [[IDXPROM7]]
	// CHECK2-NEXT: store i32 0, i32* [[ARRAYIDX8]], align 4			// CHECK2-NEXT: store i32 0, i32* [[ARRAYIDX8]], align 4, !llvm.access.group !4
	// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK2: omp.body.continue:			// CHECK2: omp.body.continue:
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK2: omp.inner.for.inc:			// CHECK2: omp.inner.for.inc:
	// CHECK2-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !4
	// CHECK2-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP13]], 1			// CHECK2-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP13]], 1
	// CHECK2-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]
	// CHECK2: omp.inner.for.end:			// CHECK2: omp.inner.for.end:
	// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK2: omp.loop.exit:			// CHECK2: omp.loop.exit:
	// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])			// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
	// CHECK2-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK2-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK2-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0			// CHECK2-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0
	// CHECK2-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK2-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK2: .omp.final.then:			// CHECK2: .omp.final.then:
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	// CHECK3-NEXT: br label [[COND_END]]			// CHECK3-NEXT: br label [[COND_END]]
	// CHECK3: cond.end:			// CHECK3: cond.end:
	// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 56087, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]			// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 56087, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
	// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK3-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK3-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK3-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK3-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK3: omp.inner.for.cond:			// CHECK3: omp.inner.for.cond:
	// CHECK3-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK3-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK3-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK3-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !5
	// CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK3: omp.inner.for.body:			// CHECK3: omp.inner.for.body:
	// CHECK3-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK3-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK3-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP8]], 456			// CHECK3-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP8]], 456
	// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1			// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1
	// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !5
	// CHECK3-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK3-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK3-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK3-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK3-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP10]], 456			// CHECK3-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP10]], 456
	// CHECK3-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 456			// CHECK3-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 456
	// CHECK3-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP9]], [[MUL4]]			// CHECK3-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP9]], [[MUL4]]
	// CHECK3-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1			// CHECK3-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1
	// CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]]			// CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]]
	// CHECK3-NEXT: store i32 [[ADD6]], i32* [[J]], align 4			// CHECK3-NEXT: store i32 [[ADD6]], i32* [[J]], align 4, !llvm.access.group !5
	// CHECK3-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 0			// CHECK3-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 0
	// CHECK3-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4			// CHECK3-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !5
	// CHECK3-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]] [[A]], i32 0, i32 [[TMP11]]			// CHECK3-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]] [[A]], i32 0, i32 [[TMP11]]
	// CHECK3-NEXT: [[TMP12:%.]] = load i32, i32 [[J]], align 4			// CHECK3-NEXT: [[TMP12:%.]] = load i32, i32 [[J]], align 4, !llvm.access.group !5
	// CHECK3-NEXT: [[ARRAYIDX7:%.]] = getelementptr inbounds [456 x i32], [456 x i32] [[ARRAYIDX]], i32 0, i32 [[TMP12]]			// CHECK3-NEXT: [[ARRAYIDX7:%.]] = getelementptr inbounds [456 x i32], [456 x i32] [[ARRAYIDX]], i32 0, i32 [[TMP12]]
	// CHECK3-NEXT: store i32 0, i32* [[ARRAYIDX7]], align 4			// CHECK3-NEXT: store i32 0, i32* [[ARRAYIDX7]], align 4, !llvm.access.group !5
	// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK3: omp.body.continue:			// CHECK3: omp.body.continue:
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK3: omp.inner.for.inc:			// CHECK3: omp.inner.for.inc:
	// CHECK3-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK3-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK3-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP13]], 1			// CHECK3-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP13]], 1
	// CHECK3-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4			// CHECK3-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]
	// CHECK3: omp.inner.for.end:			// CHECK3: omp.inner.for.end:
	// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK3: omp.loop.exit:			// CHECK3: omp.loop.exit:
	// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])			// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
	// CHECK3-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK3-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK3-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0			// CHECK3-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0
	// CHECK3-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK3-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK3: .omp.final.then:			// CHECK3: .omp.final.then:
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	// CHECK4-NEXT: br label [[COND_END]]			// CHECK4-NEXT: br label [[COND_END]]
	// CHECK4: cond.end:			// CHECK4: cond.end:
	// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 56087, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]			// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 56087, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
	// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK4-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK4-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK4-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK4-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK4: omp.inner.for.cond:			// CHECK4: omp.inner.for.cond:
	// CHECK4-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK4-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK4-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK4-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !5
	// CHECK4-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK4-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK4-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK4-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK4: omp.inner.for.body:			// CHECK4: omp.inner.for.body:
	// CHECK4-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK4-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK4-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP8]], 456			// CHECK4-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP8]], 456
	// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1			// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1
	// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !5
	// CHECK4-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK4-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK4-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK4-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK4-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP10]], 456			// CHECK4-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP10]], 456
	// CHECK4-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 456			// CHECK4-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 456
	// CHECK4-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP9]], [[MUL4]]			// CHECK4-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP9]], [[MUL4]]
	// CHECK4-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1			// CHECK4-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1
	// CHECK4-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]]			// CHECK4-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]]
	// CHECK4-NEXT: store i32 [[ADD6]], i32* [[J]], align 4			// CHECK4-NEXT: store i32 [[ADD6]], i32* [[J]], align 4, !llvm.access.group !5
	// CHECK4-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 0			// CHECK4-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 0
	// CHECK4-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4			// CHECK4-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !5
	// CHECK4-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]] [[A]], i32 0, i32 [[TMP11]]			// CHECK4-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]] [[A]], i32 0, i32 [[TMP11]]
	// CHECK4-NEXT: [[TMP12:%.]] = load i32, i32 [[J]], align 4			// CHECK4-NEXT: [[TMP12:%.]] = load i32, i32 [[J]], align 4, !llvm.access.group !5
	// CHECK4-NEXT: [[ARRAYIDX7:%.]] = getelementptr inbounds [456 x i32], [456 x i32] [[ARRAYIDX]], i32 0, i32 [[TMP12]]			// CHECK4-NEXT: [[ARRAYIDX7:%.]] = getelementptr inbounds [456 x i32], [456 x i32] [[ARRAYIDX]], i32 0, i32 [[TMP12]]
	// CHECK4-NEXT: store i32 0, i32* [[ARRAYIDX7]], align 4			// CHECK4-NEXT: store i32 0, i32* [[ARRAYIDX7]], align 4, !llvm.access.group !5
	// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK4: omp.body.continue:			// CHECK4: omp.body.continue:
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK4: omp.inner.for.inc:			// CHECK4: omp.inner.for.inc:
	// CHECK4-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK4-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK4-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP13]], 1			// CHECK4-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP13]], 1
	// CHECK4-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4			// CHECK4-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]
	// CHECK4: omp.inner.for.end:			// CHECK4: omp.inner.for.end:
	// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK4: omp.loop.exit:			// CHECK4: omp.loop.exit:
	// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])			// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
	// CHECK4-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK4-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK4-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0			// CHECK4-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0
	// CHECK4-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK4-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK4: .omp.final.then:			// CHECK4: .omp.final.then:
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	// CHECK9-NEXT: br label [[COND_END]]			// CHECK9-NEXT: br label [[COND_END]]
	// CHECK9: cond.end:			// CHECK9: cond.end:
	// CHECK9-NEXT: [[COND:%.*]] = phi i64 [ [[TMP16]], [[COND_TRUE]] ], [ [[TMP17]], [[COND_FALSE]] ]			// CHECK9-NEXT: [[COND:%.*]] = phi i64 [ [[TMP16]], [[COND_TRUE]] ], [ [[TMP17]], [[COND_FALSE]] ]
	// CHECK9-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8			// CHECK9-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
	// CHECK9-NEXT: [[TMP18:%.]] = load i64, i64 [[DOTOMP_LB]], align 8			// CHECK9-NEXT: [[TMP18:%.]] = load i64, i64 [[DOTOMP_LB]], align 8
	// CHECK9-NEXT: store i64 [[TMP18]], i64* [[DOTOMP_IV]], align 8			// CHECK9-NEXT: store i64 [[TMP18]], i64* [[DOTOMP_IV]], align 8
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK9: omp.inner.for.cond:			// CHECK9: omp.inner.for.cond:
	// CHECK9-NEXT: [[TMP19:%.]] = load i64, i64 [[DOTOMP_IV]], align 8			// CHECK9-NEXT: [[TMP19:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !5
	// CHECK9-NEXT: [[TMP20:%.]] = load i64, i64 [[DOTOMP_UB]], align 8			// CHECK9-NEXT: [[TMP20:%.]] = load i64, i64 [[DOTOMP_UB]], align 8, !llvm.access.group !5
	// CHECK9-NEXT: [[CMP14:%.*]] = icmp sle i64 [[TMP19]], [[TMP20]]			// CHECK9-NEXT: [[CMP14:%.*]] = icmp sle i64 [[TMP19]], [[TMP20]]
	// CHECK9-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK9-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK9: omp.inner.for.body:			// CHECK9: omp.inner.for.body:
	// CHECK9-NEXT: [[TMP21:%.]] = load i64, i64 [[DOTOMP_IV]], align 8			// CHECK9-NEXT: [[TMP21:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !5
	// CHECK9-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_4]], align 4			// CHECK9-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_4]], align 4, !llvm.access.group !5
	// CHECK9-NEXT: [[SUB15:%.*]] = sub nsw i32 [[TMP22]], 0			// CHECK9-NEXT: [[SUB15:%.*]] = sub nsw i32 [[TMP22]], 0
	// CHECK9-NEXT: [[DIV16:%.*]] = sdiv i32 [[SUB15]], 1			// CHECK9-NEXT: [[DIV16:%.*]] = sdiv i32 [[SUB15]], 1
	// CHECK9-NEXT: [[MUL17:%.*]] = mul nsw i32 1, [[DIV16]]			// CHECK9-NEXT: [[MUL17:%.*]] = mul nsw i32 1, [[DIV16]]
	// CHECK9-NEXT: [[CONV18:%.*]] = sext i32 [[MUL17]] to i64			// CHECK9-NEXT: [[CONV18:%.*]] = sext i32 [[MUL17]] to i64
	// CHECK9-NEXT: [[DIV19:%.*]] = sdiv i64 [[TMP21]], [[CONV18]]			// CHECK9-NEXT: [[DIV19:%.*]] = sdiv i64 [[TMP21]], [[CONV18]]
	// CHECK9-NEXT: [[MUL20:%.*]] = mul nsw i64 [[DIV19]], 1			// CHECK9-NEXT: [[MUL20:%.*]] = mul nsw i64 [[DIV19]], 1
	// CHECK9-NEXT: [[ADD:%.*]] = add nsw i64 0, [[MUL20]]			// CHECK9-NEXT: [[ADD:%.*]] = add nsw i64 0, [[MUL20]]
	// CHECK9-NEXT: [[CONV21:%.*]] = trunc i64 [[ADD]] to i32			// CHECK9-NEXT: [[CONV21:%.*]] = trunc i64 [[ADD]] to i32
	// CHECK9-NEXT: store i32 [[CONV21]], i32* [[I11]], align 4			// CHECK9-NEXT: store i32 [[CONV21]], i32* [[I11]], align 4, !llvm.access.group !5
	// CHECK9-NEXT: [[TMP23:%.]] = load i64, i64 [[DOTOMP_IV]], align 8			// CHECK9-NEXT: [[TMP23:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !5
	// CHECK9-NEXT: [[TMP24:%.]] = load i64, i64 [[DOTOMP_IV]], align 8			// CHECK9-NEXT: [[TMP24:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !5
	// CHECK9-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_4]], align 4			// CHECK9-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_4]], align 4, !llvm.access.group !5
	// CHECK9-NEXT: [[SUB22:%.*]] = sub nsw i32 [[TMP25]], 0			// CHECK9-NEXT: [[SUB22:%.*]] = sub nsw i32 [[TMP25]], 0
	// CHECK9-NEXT: [[DIV23:%.*]] = sdiv i32 [[SUB22]], 1			// CHECK9-NEXT: [[DIV23:%.*]] = sdiv i32 [[SUB22]], 1
	// CHECK9-NEXT: [[MUL24:%.*]] = mul nsw i32 1, [[DIV23]]			// CHECK9-NEXT: [[MUL24:%.*]] = mul nsw i32 1, [[DIV23]]
	// CHECK9-NEXT: [[CONV25:%.*]] = sext i32 [[MUL24]] to i64			// CHECK9-NEXT: [[CONV25:%.*]] = sext i32 [[MUL24]] to i64
	// CHECK9-NEXT: [[DIV26:%.*]] = sdiv i64 [[TMP24]], [[CONV25]]			// CHECK9-NEXT: [[DIV26:%.*]] = sdiv i64 [[TMP24]], [[CONV25]]
	// CHECK9-NEXT: [[TMP26:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_4]], align 4			// CHECK9-NEXT: [[TMP26:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_4]], align 4, !llvm.access.group !5
	// CHECK9-NEXT: [[SUB27:%.*]] = sub nsw i32 [[TMP26]], 0			// CHECK9-NEXT: [[SUB27:%.*]] = sub nsw i32 [[TMP26]], 0
	// CHECK9-NEXT: [[DIV28:%.*]] = sdiv i32 [[SUB27]], 1			// CHECK9-NEXT: [[DIV28:%.*]] = sdiv i32 [[SUB27]], 1
	// CHECK9-NEXT: [[MUL29:%.*]] = mul nsw i32 1, [[DIV28]]			// CHECK9-NEXT: [[MUL29:%.*]] = mul nsw i32 1, [[DIV28]]
	// CHECK9-NEXT: [[CONV30:%.*]] = sext i32 [[MUL29]] to i64			// CHECK9-NEXT: [[CONV30:%.*]] = sext i32 [[MUL29]] to i64
	// CHECK9-NEXT: [[MUL31:%.*]] = mul nsw i64 [[DIV26]], [[CONV30]]			// CHECK9-NEXT: [[MUL31:%.*]] = mul nsw i64 [[DIV26]], [[CONV30]]
	// CHECK9-NEXT: [[SUB32:%.*]] = sub nsw i64 [[TMP23]], [[MUL31]]			// CHECK9-NEXT: [[SUB32:%.*]] = sub nsw i64 [[TMP23]], [[MUL31]]
	// CHECK9-NEXT: [[MUL33:%.*]] = mul nsw i64 [[SUB32]], 1			// CHECK9-NEXT: [[MUL33:%.*]] = mul nsw i64 [[SUB32]], 1
	// CHECK9-NEXT: [[ADD34:%.*]] = add nsw i64 0, [[MUL33]]			// CHECK9-NEXT: [[ADD34:%.*]] = add nsw i64 0, [[MUL33]]
	// CHECK9-NEXT: [[CONV35:%.*]] = trunc i64 [[ADD34]] to i32			// CHECK9-NEXT: [[CONV35:%.*]] = trunc i64 [[ADD34]] to i32
	// CHECK9-NEXT: store i32 [[CONV35]], i32* [[J12]], align 4			// CHECK9-NEXT: store i32 [[CONV35]], i32* [[J12]], align 4, !llvm.access.group !5
	// CHECK9-NEXT: [[TMP27:%.]] = load i32, i32 [[I11]], align 4			// CHECK9-NEXT: [[TMP27:%.]] = load i32, i32 [[I11]], align 4, !llvm.access.group !5
	// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP27]] to i64			// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP27]] to i64
	// CHECK9-NEXT: [[TMP28:%.*]] = mul nsw i64 [[IDXPROM]], [[TMP3]]			// CHECK9-NEXT: [[TMP28:%.*]] = mul nsw i64 [[IDXPROM]], [[TMP3]]
	// CHECK9-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP4]], i64 [[TMP28]]			// CHECK9-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP4]], i64 [[TMP28]]
	// CHECK9-NEXT: [[TMP29:%.]] = load i32, i32 [[J12]], align 4			// CHECK9-NEXT: [[TMP29:%.]] = load i32, i32 [[J12]], align 4, !llvm.access.group !5
	// CHECK9-NEXT: [[IDXPROM36:%.*]] = sext i32 [[TMP29]] to i64			// CHECK9-NEXT: [[IDXPROM36:%.*]] = sext i32 [[TMP29]] to i64
	// CHECK9-NEXT: [[ARRAYIDX37:%.]] = getelementptr inbounds i32, i32 [[ARRAYIDX]], i64 [[IDXPROM36]]			// CHECK9-NEXT: [[ARRAYIDX37:%.]] = getelementptr inbounds i32, i32 [[ARRAYIDX]], i64 [[IDXPROM36]]
	// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX37]], align 4			// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX37]], align 4, !llvm.access.group !5
	// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK9: omp.body.continue:			// CHECK9: omp.body.continue:
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK9: omp.inner.for.inc:			// CHECK9: omp.inner.for.inc:
	// CHECK9-NEXT: [[TMP30:%.]] = load i64, i64 [[DOTOMP_IV]], align 8			// CHECK9-NEXT: [[TMP30:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !5
	// CHECK9-NEXT: [[ADD38:%.*]] = add nsw i64 [[TMP30]], 1			// CHECK9-NEXT: [[ADD38:%.*]] = add nsw i64 [[TMP30]], 1
	// CHECK9-NEXT: store i64 [[ADD38]], i64* [[DOTOMP_IV]], align 8			// CHECK9-NEXT: store i64 [[ADD38]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !5
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]
	// CHECK9: omp.inner.for.end:			// CHECK9: omp.inner.for.end:
	// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK9: omp.loop.exit:			// CHECK9: omp.loop.exit:
	// CHECK9-NEXT: [[TMP31:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK9-NEXT: [[TMP31:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK9-NEXT: [[TMP32:%.]] = load i32, i32 [[TMP31]], align 4			// CHECK9-NEXT: [[TMP32:%.]] = load i32, i32 [[TMP31]], align 4
	// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP32]])			// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP32]])
	// CHECK9-NEXT: [[TMP33:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK9-NEXT: [[TMP33:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK9-NEXT: [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 0			// CHECK9-NEXT: [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 0
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	// CHECK9-NEXT: br label [[COND_END]]			// CHECK9-NEXT: br label [[COND_END]]
	// CHECK9: cond.end:			// CHECK9: cond.end:
	// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 19, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]			// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 19, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
	// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK9-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK9-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK9: omp.inner.for.cond:			// CHECK9: omp.inner.for.cond:
	// CHECK9-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11
	// CHECK9-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK9-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !11
	// CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK9: omp.inner.for.body:			// CHECK9: omp.inner.for.body:
	// CHECK9-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11
	// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP8]], 2			// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP8]], 2
	// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1			// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1
	// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11
	// CHECK9-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11
	// CHECK9-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11
	// CHECK9-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP10]], 2			// CHECK9-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP10]], 2
	// CHECK9-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 2			// CHECK9-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 2
	// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP9]], [[MUL4]]			// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP9]], [[MUL4]]
	// CHECK9-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1			// CHECK9-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1
	// CHECK9-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]]			// CHECK9-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]]
	// CHECK9-NEXT: store i32 [[ADD6]], i32* [[J]], align 4			// CHECK9-NEXT: store i32 [[ADD6]], i32* [[J]], align 4, !llvm.access.group !11
	// CHECK9-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4			// CHECK9-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !11
	// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64			// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64
	// CHECK9-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]] [[TMP0]], i64 0, i64 [[IDXPROM]]			// CHECK9-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]] [[TMP0]], i64 0, i64 [[IDXPROM]]
	// CHECK9-NEXT: [[TMP12:%.]] = load i32, i32 [[J]], align 4			// CHECK9-NEXT: [[TMP12:%.]] = load i32, i32 [[J]], align 4, !llvm.access.group !11
	// CHECK9-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP12]] to i64			// CHECK9-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP12]] to i64
	// CHECK9-NEXT: [[ARRAYIDX8:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[ARRAYIDX]], i64 0, i64 [[IDXPROM7]]			// CHECK9-NEXT: [[ARRAYIDX8:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[ARRAYIDX]], i64 0, i64 [[IDXPROM7]]
	// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX8]], align 4			// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX8]], align 4, !llvm.access.group !11
	// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK9: omp.body.continue:			// CHECK9: omp.body.continue:
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK9: omp.inner.for.inc:			// CHECK9: omp.inner.for.inc:
	// CHECK9-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11
	// CHECK9-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP13]], 1			// CHECK9-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP13]], 1
	// CHECK9-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4			// CHECK9-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]
	// CHECK9: omp.inner.for.end:			// CHECK9: omp.inner.for.end:
	// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK9: omp.loop.exit:			// CHECK9: omp.loop.exit:
	// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])			// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
	// CHECK9-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK9-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK9-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0			// CHECK9-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0
	// CHECK9-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK9-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK9: .omp.final.then:			// CHECK9: .omp.final.then:
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	// CHECK10-NEXT: br label [[COND_END]]			// CHECK10-NEXT: br label [[COND_END]]
	// CHECK10: cond.end:			// CHECK10: cond.end:
	// CHECK10-NEXT: [[COND:%.*]] = phi i64 [ [[TMP16]], [[COND_TRUE]] ], [ [[TMP17]], [[COND_FALSE]] ]			// CHECK10-NEXT: [[COND:%.*]] = phi i64 [ [[TMP16]], [[COND_TRUE]] ], [ [[TMP17]], [[COND_FALSE]] ]
	// CHECK10-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8			// CHECK10-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
	// CHECK10-NEXT: [[TMP18:%.]] = load i64, i64 [[DOTOMP_LB]], align 8			// CHECK10-NEXT: [[TMP18:%.]] = load i64, i64 [[DOTOMP_LB]], align 8
	// CHECK10-NEXT: store i64 [[TMP18]], i64* [[DOTOMP_IV]], align 8			// CHECK10-NEXT: store i64 [[TMP18]], i64* [[DOTOMP_IV]], align 8
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK10: omp.inner.for.cond:			// CHECK10: omp.inner.for.cond:
	// CHECK10-NEXT: [[TMP19:%.]] = load i64, i64 [[DOTOMP_IV]], align 8			// CHECK10-NEXT: [[TMP19:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !5
	// CHECK10-NEXT: [[TMP20:%.]] = load i64, i64 [[DOTOMP_UB]], align 8			// CHECK10-NEXT: [[TMP20:%.]] = load i64, i64 [[DOTOMP_UB]], align 8, !llvm.access.group !5
	// CHECK10-NEXT: [[CMP14:%.*]] = icmp sle i64 [[TMP19]], [[TMP20]]			// CHECK10-NEXT: [[CMP14:%.*]] = icmp sle i64 [[TMP19]], [[TMP20]]
	// CHECK10-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK10-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK10: omp.inner.for.body:			// CHECK10: omp.inner.for.body:
	// CHECK10-NEXT: [[TMP21:%.]] = load i64, i64 [[DOTOMP_IV]], align 8			// CHECK10-NEXT: [[TMP21:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !5
	// CHECK10-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_4]], align 4			// CHECK10-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_4]], align 4, !llvm.access.group !5
	// CHECK10-NEXT: [[SUB15:%.*]] = sub nsw i32 [[TMP22]], 0			// CHECK10-NEXT: [[SUB15:%.*]] = sub nsw i32 [[TMP22]], 0
	// CHECK10-NEXT: [[DIV16:%.*]] = sdiv i32 [[SUB15]], 1			// CHECK10-NEXT: [[DIV16:%.*]] = sdiv i32 [[SUB15]], 1
	// CHECK10-NEXT: [[MUL17:%.*]] = mul nsw i32 1, [[DIV16]]			// CHECK10-NEXT: [[MUL17:%.*]] = mul nsw i32 1, [[DIV16]]
	// CHECK10-NEXT: [[CONV18:%.*]] = sext i32 [[MUL17]] to i64			// CHECK10-NEXT: [[CONV18:%.*]] = sext i32 [[MUL17]] to i64
	// CHECK10-NEXT: [[DIV19:%.*]] = sdiv i64 [[TMP21]], [[CONV18]]			// CHECK10-NEXT: [[DIV19:%.*]] = sdiv i64 [[TMP21]], [[CONV18]]
	// CHECK10-NEXT: [[MUL20:%.*]] = mul nsw i64 [[DIV19]], 1			// CHECK10-NEXT: [[MUL20:%.*]] = mul nsw i64 [[DIV19]], 1
	// CHECK10-NEXT: [[ADD:%.*]] = add nsw i64 0, [[MUL20]]			// CHECK10-NEXT: [[ADD:%.*]] = add nsw i64 0, [[MUL20]]
	// CHECK10-NEXT: [[CONV21:%.*]] = trunc i64 [[ADD]] to i32			// CHECK10-NEXT: [[CONV21:%.*]] = trunc i64 [[ADD]] to i32
	// CHECK10-NEXT: store i32 [[CONV21]], i32* [[I11]], align 4			// CHECK10-NEXT: store i32 [[CONV21]], i32* [[I11]], align 4, !llvm.access.group !5
	// CHECK10-NEXT: [[TMP23:%.]] = load i64, i64 [[DOTOMP_IV]], align 8			// CHECK10-NEXT: [[TMP23:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !5
	// CHECK10-NEXT: [[TMP24:%.]] = load i64, i64 [[DOTOMP_IV]], align 8			// CHECK10-NEXT: [[TMP24:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !5
	// CHECK10-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_4]], align 4			// CHECK10-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_4]], align 4, !llvm.access.group !5
	// CHECK10-NEXT: [[SUB22:%.*]] = sub nsw i32 [[TMP25]], 0			// CHECK10-NEXT: [[SUB22:%.*]] = sub nsw i32 [[TMP25]], 0
	// CHECK10-NEXT: [[DIV23:%.*]] = sdiv i32 [[SUB22]], 1			// CHECK10-NEXT: [[DIV23:%.*]] = sdiv i32 [[SUB22]], 1
	// CHECK10-NEXT: [[MUL24:%.*]] = mul nsw i32 1, [[DIV23]]			// CHECK10-NEXT: [[MUL24:%.*]] = mul nsw i32 1, [[DIV23]]
	// CHECK10-NEXT: [[CONV25:%.*]] = sext i32 [[MUL24]] to i64			// CHECK10-NEXT: [[CONV25:%.*]] = sext i32 [[MUL24]] to i64
	// CHECK10-NEXT: [[DIV26:%.*]] = sdiv i64 [[TMP24]], [[CONV25]]			// CHECK10-NEXT: [[DIV26:%.*]] = sdiv i64 [[TMP24]], [[CONV25]]
	// CHECK10-NEXT: [[TMP26:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_4]], align 4			// CHECK10-NEXT: [[TMP26:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_4]], align 4, !llvm.access.group !5
	// CHECK10-NEXT: [[SUB27:%.*]] = sub nsw i32 [[TMP26]], 0			// CHECK10-NEXT: [[SUB27:%.*]] = sub nsw i32 [[TMP26]], 0
	// CHECK10-NEXT: [[DIV28:%.*]] = sdiv i32 [[SUB27]], 1			// CHECK10-NEXT: [[DIV28:%.*]] = sdiv i32 [[SUB27]], 1
	// CHECK10-NEXT: [[MUL29:%.*]] = mul nsw i32 1, [[DIV28]]			// CHECK10-NEXT: [[MUL29:%.*]] = mul nsw i32 1, [[DIV28]]
	// CHECK10-NEXT: [[CONV30:%.*]] = sext i32 [[MUL29]] to i64			// CHECK10-NEXT: [[CONV30:%.*]] = sext i32 [[MUL29]] to i64
	// CHECK10-NEXT: [[MUL31:%.*]] = mul nsw i64 [[DIV26]], [[CONV30]]			// CHECK10-NEXT: [[MUL31:%.*]] = mul nsw i64 [[DIV26]], [[CONV30]]
	// CHECK10-NEXT: [[SUB32:%.*]] = sub nsw i64 [[TMP23]], [[MUL31]]			// CHECK10-NEXT: [[SUB32:%.*]] = sub nsw i64 [[TMP23]], [[MUL31]]
	// CHECK10-NEXT: [[MUL33:%.*]] = mul nsw i64 [[SUB32]], 1			// CHECK10-NEXT: [[MUL33:%.*]] = mul nsw i64 [[SUB32]], 1
	// CHECK10-NEXT: [[ADD34:%.*]] = add nsw i64 0, [[MUL33]]			// CHECK10-NEXT: [[ADD34:%.*]] = add nsw i64 0, [[MUL33]]
	// CHECK10-NEXT: [[CONV35:%.*]] = trunc i64 [[ADD34]] to i32			// CHECK10-NEXT: [[CONV35:%.*]] = trunc i64 [[ADD34]] to i32
	// CHECK10-NEXT: store i32 [[CONV35]], i32* [[J12]], align 4			// CHECK10-NEXT: store i32 [[CONV35]], i32* [[J12]], align 4, !llvm.access.group !5
	// CHECK10-NEXT: [[TMP27:%.]] = load i32, i32 [[I11]], align 4			// CHECK10-NEXT: [[TMP27:%.]] = load i32, i32 [[I11]], align 4, !llvm.access.group !5
	// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP27]] to i64			// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP27]] to i64
	// CHECK10-NEXT: [[TMP28:%.*]] = mul nsw i64 [[IDXPROM]], [[TMP3]]			// CHECK10-NEXT: [[TMP28:%.*]] = mul nsw i64 [[IDXPROM]], [[TMP3]]
	// CHECK10-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP4]], i64 [[TMP28]]			// CHECK10-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP4]], i64 [[TMP28]]
	// CHECK10-NEXT: [[TMP29:%.]] = load i32, i32 [[J12]], align 4			// CHECK10-NEXT: [[TMP29:%.]] = load i32, i32 [[J12]], align 4, !llvm.access.group !5
	// CHECK10-NEXT: [[IDXPROM36:%.*]] = sext i32 [[TMP29]] to i64			// CHECK10-NEXT: [[IDXPROM36:%.*]] = sext i32 [[TMP29]] to i64
	// CHECK10-NEXT: [[ARRAYIDX37:%.]] = getelementptr inbounds i32, i32 [[ARRAYIDX]], i64 [[IDXPROM36]]			// CHECK10-NEXT: [[ARRAYIDX37:%.]] = getelementptr inbounds i32, i32 [[ARRAYIDX]], i64 [[IDXPROM36]]
	// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX37]], align 4			// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX37]], align 4, !llvm.access.group !5
	// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK10: omp.body.continue:			// CHECK10: omp.body.continue:
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK10: omp.inner.for.inc:			// CHECK10: omp.inner.for.inc:
	// CHECK10-NEXT: [[TMP30:%.]] = load i64, i64 [[DOTOMP_IV]], align 8			// CHECK10-NEXT: [[TMP30:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !5
	// CHECK10-NEXT: [[ADD38:%.*]] = add nsw i64 [[TMP30]], 1			// CHECK10-NEXT: [[ADD38:%.*]] = add nsw i64 [[TMP30]], 1
	// CHECK10-NEXT: store i64 [[ADD38]], i64* [[DOTOMP_IV]], align 8			// CHECK10-NEXT: store i64 [[ADD38]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !5
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]
	// CHECK10: omp.inner.for.end:			// CHECK10: omp.inner.for.end:
	// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK10: omp.loop.exit:			// CHECK10: omp.loop.exit:
	// CHECK10-NEXT: [[TMP31:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK10-NEXT: [[TMP31:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK10-NEXT: [[TMP32:%.]] = load i32, i32 [[TMP31]], align 4			// CHECK10-NEXT: [[TMP32:%.]] = load i32, i32 [[TMP31]], align 4
	// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP32]])			// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP32]])
	// CHECK10-NEXT: [[TMP33:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK10-NEXT: [[TMP33:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK10-NEXT: [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 0			// CHECK10-NEXT: [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 0
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	// CHECK10-NEXT: br label [[COND_END]]			// CHECK10-NEXT: br label [[COND_END]]
	// CHECK10: cond.end:			// CHECK10: cond.end:
	// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 19, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]			// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 19, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
	// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK10-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK10-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK10-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK10-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK10: omp.inner.for.cond:			// CHECK10: omp.inner.for.cond:
	// CHECK10-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11
	// CHECK10-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK10-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !11
	// CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK10: omp.inner.for.body:			// CHECK10: omp.inner.for.body:
	// CHECK10-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11
	// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP8]], 2			// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP8]], 2
	// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1			// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1
	// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11
	// CHECK10-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11
	// CHECK10-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11
	// CHECK10-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP10]], 2			// CHECK10-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP10]], 2
	// CHECK10-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 2			// CHECK10-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 2
	// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP9]], [[MUL4]]			// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP9]], [[MUL4]]
	// CHECK10-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1			// CHECK10-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1
	// CHECK10-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]]			// CHECK10-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]]
	// CHECK10-NEXT: store i32 [[ADD6]], i32* [[J]], align 4			// CHECK10-NEXT: store i32 [[ADD6]], i32* [[J]], align 4, !llvm.access.group !11
	// CHECK10-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4			// CHECK10-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !11
	// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64			// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64
	// CHECK10-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]] [[TMP0]], i64 0, i64 [[IDXPROM]]			// CHECK10-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]] [[TMP0]], i64 0, i64 [[IDXPROM]]
	// CHECK10-NEXT: [[TMP12:%.]] = load i32, i32 [[J]], align 4			// CHECK10-NEXT: [[TMP12:%.]] = load i32, i32 [[J]], align 4, !llvm.access.group !11
	// CHECK10-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP12]] to i64			// CHECK10-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP12]] to i64
	// CHECK10-NEXT: [[ARRAYIDX8:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[ARRAYIDX]], i64 0, i64 [[IDXPROM7]]			// CHECK10-NEXT: [[ARRAYIDX8:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[ARRAYIDX]], i64 0, i64 [[IDXPROM7]]
	// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX8]], align 4			// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX8]], align 4, !llvm.access.group !11
	// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK10: omp.body.continue:			// CHECK10: omp.body.continue:
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK10: omp.inner.for.inc:			// CHECK10: omp.inner.for.inc:
	// CHECK10-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11
	// CHECK10-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP13]], 1			// CHECK10-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP13]], 1
	// CHECK10-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4			// CHECK10-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]
	// CHECK10: omp.inner.for.end:			// CHECK10: omp.inner.for.end:
	// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK10: omp.loop.exit:			// CHECK10: omp.loop.exit:
	// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])			// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
	// CHECK10-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK10-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK10-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0			// CHECK10-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0
	// CHECK10-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK10-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK10: .omp.final.then:			// CHECK10: .omp.final.then:
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	// CHECK11-NEXT: br label [[COND_END]]			// CHECK11-NEXT: br label [[COND_END]]
	// CHECK11: cond.end:			// CHECK11: cond.end:
	// CHECK11-NEXT: [[COND:%.*]] = phi i64 [ [[TMP16]], [[COND_TRUE]] ], [ [[TMP17]], [[COND_FALSE]] ]			// CHECK11-NEXT: [[COND:%.*]] = phi i64 [ [[TMP16]], [[COND_TRUE]] ], [ [[TMP17]], [[COND_FALSE]] ]
	// CHECK11-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8			// CHECK11-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
	// CHECK11-NEXT: [[TMP18:%.]] = load i64, i64 [[DOTOMP_LB]], align 8			// CHECK11-NEXT: [[TMP18:%.]] = load i64, i64 [[DOTOMP_LB]], align 8
	// CHECK11-NEXT: store i64 [[TMP18]], i64* [[DOTOMP_IV]], align 8			// CHECK11-NEXT: store i64 [[TMP18]], i64* [[DOTOMP_IV]], align 8
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK11: omp.inner.for.cond:			// CHECK11: omp.inner.for.cond:
	// CHECK11-NEXT: [[TMP19:%.]] = load i64, i64 [[DOTOMP_IV]], align 8			// CHECK11-NEXT: [[TMP19:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !6
	// CHECK11-NEXT: [[TMP20:%.]] = load i64, i64 [[DOTOMP_UB]], align 8			// CHECK11-NEXT: [[TMP20:%.]] = load i64, i64 [[DOTOMP_UB]], align 8, !llvm.access.group !6
	// CHECK11-NEXT: [[CMP14:%.*]] = icmp sle i64 [[TMP19]], [[TMP20]]			// CHECK11-NEXT: [[CMP14:%.*]] = icmp sle i64 [[TMP19]], [[TMP20]]
	// CHECK11-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK11-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK11: omp.inner.for.body:			// CHECK11: omp.inner.for.body:
	// CHECK11-NEXT: [[TMP21:%.]] = load i64, i64 [[DOTOMP_IV]], align 8			// CHECK11-NEXT: [[TMP21:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !6
	// CHECK11-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_4]], align 4			// CHECK11-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_4]], align 4, !llvm.access.group !6
	// CHECK11-NEXT: [[SUB15:%.*]] = sub nsw i32 [[TMP22]], 0			// CHECK11-NEXT: [[SUB15:%.*]] = sub nsw i32 [[TMP22]], 0
	// CHECK11-NEXT: [[DIV16:%.*]] = sdiv i32 [[SUB15]], 1			// CHECK11-NEXT: [[DIV16:%.*]] = sdiv i32 [[SUB15]], 1
	// CHECK11-NEXT: [[MUL17:%.*]] = mul nsw i32 1, [[DIV16]]			// CHECK11-NEXT: [[MUL17:%.*]] = mul nsw i32 1, [[DIV16]]
	// CHECK11-NEXT: [[CONV18:%.*]] = sext i32 [[MUL17]] to i64			// CHECK11-NEXT: [[CONV18:%.*]] = sext i32 [[MUL17]] to i64
	// CHECK11-NEXT: [[DIV19:%.*]] = sdiv i64 [[TMP21]], [[CONV18]]			// CHECK11-NEXT: [[DIV19:%.*]] = sdiv i64 [[TMP21]], [[CONV18]]
	// CHECK11-NEXT: [[MUL20:%.*]] = mul nsw i64 [[DIV19]], 1			// CHECK11-NEXT: [[MUL20:%.*]] = mul nsw i64 [[DIV19]], 1
	// CHECK11-NEXT: [[ADD:%.*]] = add nsw i64 0, [[MUL20]]			// CHECK11-NEXT: [[ADD:%.*]] = add nsw i64 0, [[MUL20]]
	// CHECK11-NEXT: [[CONV21:%.*]] = trunc i64 [[ADD]] to i32			// CHECK11-NEXT: [[CONV21:%.*]] = trunc i64 [[ADD]] to i32
	// CHECK11-NEXT: store i32 [[CONV21]], i32* [[I11]], align 4			// CHECK11-NEXT: store i32 [[CONV21]], i32* [[I11]], align 4, !llvm.access.group !6
	// CHECK11-NEXT: [[TMP23:%.]] = load i64, i64 [[DOTOMP_IV]], align 8			// CHECK11-NEXT: [[TMP23:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !6
	// CHECK11-NEXT: [[TMP24:%.]] = load i64, i64 [[DOTOMP_IV]], align 8			// CHECK11-NEXT: [[TMP24:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !6
	// CHECK11-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_4]], align 4			// CHECK11-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_4]], align 4, !llvm.access.group !6
	// CHECK11-NEXT: [[SUB22:%.*]] = sub nsw i32 [[TMP25]], 0			// CHECK11-NEXT: [[SUB22:%.*]] = sub nsw i32 [[TMP25]], 0
	// CHECK11-NEXT: [[DIV23:%.*]] = sdiv i32 [[SUB22]], 1			// CHECK11-NEXT: [[DIV23:%.*]] = sdiv i32 [[SUB22]], 1
	// CHECK11-NEXT: [[MUL24:%.*]] = mul nsw i32 1, [[DIV23]]			// CHECK11-NEXT: [[MUL24:%.*]] = mul nsw i32 1, [[DIV23]]
	// CHECK11-NEXT: [[CONV25:%.*]] = sext i32 [[MUL24]] to i64			// CHECK11-NEXT: [[CONV25:%.*]] = sext i32 [[MUL24]] to i64
	// CHECK11-NEXT: [[DIV26:%.*]] = sdiv i64 [[TMP24]], [[CONV25]]			// CHECK11-NEXT: [[DIV26:%.*]] = sdiv i64 [[TMP24]], [[CONV25]]
	// CHECK11-NEXT: [[TMP26:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_4]], align 4			// CHECK11-NEXT: [[TMP26:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_4]], align 4, !llvm.access.group !6
	// CHECK11-NEXT: [[SUB27:%.*]] = sub nsw i32 [[TMP26]], 0			// CHECK11-NEXT: [[SUB27:%.*]] = sub nsw i32 [[TMP26]], 0
	// CHECK11-NEXT: [[DIV28:%.*]] = sdiv i32 [[SUB27]], 1			// CHECK11-NEXT: [[DIV28:%.*]] = sdiv i32 [[SUB27]], 1
	// CHECK11-NEXT: [[MUL29:%.*]] = mul nsw i32 1, [[DIV28]]			// CHECK11-NEXT: [[MUL29:%.*]] = mul nsw i32 1, [[DIV28]]
	// CHECK11-NEXT: [[CONV30:%.*]] = sext i32 [[MUL29]] to i64			// CHECK11-NEXT: [[CONV30:%.*]] = sext i32 [[MUL29]] to i64
	// CHECK11-NEXT: [[MUL31:%.*]] = mul nsw i64 [[DIV26]], [[CONV30]]			// CHECK11-NEXT: [[MUL31:%.*]] = mul nsw i64 [[DIV26]], [[CONV30]]
	// CHECK11-NEXT: [[SUB32:%.*]] = sub nsw i64 [[TMP23]], [[MUL31]]			// CHECK11-NEXT: [[SUB32:%.*]] = sub nsw i64 [[TMP23]], [[MUL31]]
	// CHECK11-NEXT: [[MUL33:%.*]] = mul nsw i64 [[SUB32]], 1			// CHECK11-NEXT: [[MUL33:%.*]] = mul nsw i64 [[SUB32]], 1
	// CHECK11-NEXT: [[ADD34:%.*]] = add nsw i64 0, [[MUL33]]			// CHECK11-NEXT: [[ADD34:%.*]] = add nsw i64 0, [[MUL33]]
	// CHECK11-NEXT: [[CONV35:%.*]] = trunc i64 [[ADD34]] to i32			// CHECK11-NEXT: [[CONV35:%.*]] = trunc i64 [[ADD34]] to i32
	// CHECK11-NEXT: store i32 [[CONV35]], i32* [[J12]], align 4			// CHECK11-NEXT: store i32 [[CONV35]], i32* [[J12]], align 4, !llvm.access.group !6
	// CHECK11-NEXT: [[TMP27:%.]] = load i32, i32 [[I11]], align 4			// CHECK11-NEXT: [[TMP27:%.]] = load i32, i32 [[I11]], align 4, !llvm.access.group !6
	// CHECK11-NEXT: [[TMP28:%.*]] = mul nsw i32 [[TMP27]], [[TMP3]]			// CHECK11-NEXT: [[TMP28:%.*]] = mul nsw i32 [[TMP27]], [[TMP3]]
	// CHECK11-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP4]], i32 [[TMP28]]			// CHECK11-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP4]], i32 [[TMP28]]
	// CHECK11-NEXT: [[TMP29:%.]] = load i32, i32 [[J12]], align 4			// CHECK11-NEXT: [[TMP29:%.]] = load i32, i32 [[J12]], align 4, !llvm.access.group !6
	// CHECK11-NEXT: [[ARRAYIDX36:%.]] = getelementptr inbounds i32, i32 [[ARRAYIDX]], i32 [[TMP29]]			// CHECK11-NEXT: [[ARRAYIDX36:%.]] = getelementptr inbounds i32, i32 [[ARRAYIDX]], i32 [[TMP29]]
	// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX36]], align 4			// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX36]], align 4, !llvm.access.group !6
	// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK11: omp.body.continue:			// CHECK11: omp.body.continue:
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK11: omp.inner.for.inc:			// CHECK11: omp.inner.for.inc:
	// CHECK11-NEXT: [[TMP30:%.]] = load i64, i64 [[DOTOMP_IV]], align 8			// CHECK11-NEXT: [[TMP30:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !6
	// CHECK11-NEXT: [[ADD37:%.*]] = add nsw i64 [[TMP30]], 1			// CHECK11-NEXT: [[ADD37:%.*]] = add nsw i64 [[TMP30]], 1
	// CHECK11-NEXT: store i64 [[ADD37]], i64* [[DOTOMP_IV]], align 8			// CHECK11-NEXT: store i64 [[ADD37]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !6
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]
	// CHECK11: omp.inner.for.end:			// CHECK11: omp.inner.for.end:
	// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK11: omp.loop.exit:			// CHECK11: omp.loop.exit:
	// CHECK11-NEXT: [[TMP31:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4			// CHECK11-NEXT: [[TMP31:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4
	// CHECK11-NEXT: [[TMP32:%.]] = load i32, i32 [[TMP31]], align 4			// CHECK11-NEXT: [[TMP32:%.]] = load i32, i32 [[TMP31]], align 4
	// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP32]])			// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP32]])
	// CHECK11-NEXT: [[TMP33:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK11-NEXT: [[TMP33:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK11-NEXT: [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 0			// CHECK11-NEXT: [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 0
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	// CHECK11-NEXT: br label [[COND_END]]			// CHECK11-NEXT: br label [[COND_END]]
	// CHECK11: cond.end:			// CHECK11: cond.end:
	// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 19, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]			// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 19, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
	// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK11-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK11-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK11-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK11-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK11: omp.inner.for.cond:			// CHECK11: omp.inner.for.cond:
	// CHECK11-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK11-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12
	// CHECK11-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK11-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !12
	// CHECK11-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK11-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK11-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK11-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK11: omp.inner.for.body:			// CHECK11: omp.inner.for.body:
	// CHECK11-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK11-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12
	// CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP8]], 2			// CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP8]], 2
	// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1			// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1
	// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !12
	// CHECK11-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK11-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12
	// CHECK11-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK11-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12
	// CHECK11-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP10]], 2			// CHECK11-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP10]], 2
	// CHECK11-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 2			// CHECK11-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 2
	// CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP9]], [[MUL4]]			// CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP9]], [[MUL4]]
	// CHECK11-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1			// CHECK11-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1
	// CHECK11-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]]			// CHECK11-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]]
	// CHECK11-NEXT: store i32 [[ADD6]], i32* [[J]], align 4			// CHECK11-NEXT: store i32 [[ADD6]], i32* [[J]], align 4, !llvm.access.group !12
	// CHECK11-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4			// CHECK11-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !12
	// CHECK11-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]] [[TMP0]], i32 0, i32 [[TMP11]]			// CHECK11-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]] [[TMP0]], i32 0, i32 [[TMP11]]
	// CHECK11-NEXT: [[TMP12:%.]] = load i32, i32 [[J]], align 4			// CHECK11-NEXT: [[TMP12:%.]] = load i32, i32 [[J]], align 4, !llvm.access.group !12
	// CHECK11-NEXT: [[ARRAYIDX7:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[ARRAYIDX]], i32 0, i32 [[TMP12]]			// CHECK11-NEXT: [[ARRAYIDX7:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[ARRAYIDX]], i32 0, i32 [[TMP12]]
	// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX7]], align 4			// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX7]], align 4, !llvm.access.group !12
	// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK11: omp.body.continue:			// CHECK11: omp.body.continue:
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK11: omp.inner.for.inc:			// CHECK11: omp.inner.for.inc:
	// CHECK11-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK11-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12
	// CHECK11-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP13]], 1			// CHECK11-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP13]], 1
	// CHECK11-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4			// CHECK11-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]
	// CHECK11: omp.inner.for.end:			// CHECK11: omp.inner.for.end:
	// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK11: omp.loop.exit:			// CHECK11: omp.loop.exit:
	// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])			// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
	// CHECK11-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK11-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK11-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0			// CHECK11-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0
	// CHECK11-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK11-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK11: .omp.final.then:			// CHECK11: .omp.final.then:
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	// CHECK12-NEXT: br label [[COND_END]]			// CHECK12-NEXT: br label [[COND_END]]
	// CHECK12: cond.end:			// CHECK12: cond.end:
	// CHECK12-NEXT: [[COND:%.*]] = phi i64 [ [[TMP16]], [[COND_TRUE]] ], [ [[TMP17]], [[COND_FALSE]] ]			// CHECK12-NEXT: [[COND:%.*]] = phi i64 [ [[TMP16]], [[COND_TRUE]] ], [ [[TMP17]], [[COND_FALSE]] ]
	// CHECK12-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8			// CHECK12-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
	// CHECK12-NEXT: [[TMP18:%.]] = load i64, i64 [[DOTOMP_LB]], align 8			// CHECK12-NEXT: [[TMP18:%.]] = load i64, i64 [[DOTOMP_LB]], align 8
	// CHECK12-NEXT: store i64 [[TMP18]], i64* [[DOTOMP_IV]], align 8			// CHECK12-NEXT: store i64 [[TMP18]], i64* [[DOTOMP_IV]], align 8
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK12: omp.inner.for.cond:			// CHECK12: omp.inner.for.cond:
	// CHECK12-NEXT: [[TMP19:%.]] = load i64, i64 [[DOTOMP_IV]], align 8			// CHECK12-NEXT: [[TMP19:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !6
	// CHECK12-NEXT: [[TMP20:%.]] = load i64, i64 [[DOTOMP_UB]], align 8			// CHECK12-NEXT: [[TMP20:%.]] = load i64, i64 [[DOTOMP_UB]], align 8, !llvm.access.group !6
	// CHECK12-NEXT: [[CMP14:%.*]] = icmp sle i64 [[TMP19]], [[TMP20]]			// CHECK12-NEXT: [[CMP14:%.*]] = icmp sle i64 [[TMP19]], [[TMP20]]
	// CHECK12-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK12-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK12: omp.inner.for.body:			// CHECK12: omp.inner.for.body:
	// CHECK12-NEXT: [[TMP21:%.]] = load i64, i64 [[DOTOMP_IV]], align 8			// CHECK12-NEXT: [[TMP21:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !6
	// CHECK12-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_4]], align 4			// CHECK12-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_4]], align 4, !llvm.access.group !6
	// CHECK12-NEXT: [[SUB15:%.*]] = sub nsw i32 [[TMP22]], 0			// CHECK12-NEXT: [[SUB15:%.*]] = sub nsw i32 [[TMP22]], 0
	// CHECK12-NEXT: [[DIV16:%.*]] = sdiv i32 [[SUB15]], 1			// CHECK12-NEXT: [[DIV16:%.*]] = sdiv i32 [[SUB15]], 1
	// CHECK12-NEXT: [[MUL17:%.*]] = mul nsw i32 1, [[DIV16]]			// CHECK12-NEXT: [[MUL17:%.*]] = mul nsw i32 1, [[DIV16]]
	// CHECK12-NEXT: [[CONV18:%.*]] = sext i32 [[MUL17]] to i64			// CHECK12-NEXT: [[CONV18:%.*]] = sext i32 [[MUL17]] to i64
	// CHECK12-NEXT: [[DIV19:%.*]] = sdiv i64 [[TMP21]], [[CONV18]]			// CHECK12-NEXT: [[DIV19:%.*]] = sdiv i64 [[TMP21]], [[CONV18]]
	// CHECK12-NEXT: [[MUL20:%.*]] = mul nsw i64 [[DIV19]], 1			// CHECK12-NEXT: [[MUL20:%.*]] = mul nsw i64 [[DIV19]], 1
	// CHECK12-NEXT: [[ADD:%.*]] = add nsw i64 0, [[MUL20]]			// CHECK12-NEXT: [[ADD:%.*]] = add nsw i64 0, [[MUL20]]
	// CHECK12-NEXT: [[CONV21:%.*]] = trunc i64 [[ADD]] to i32			// CHECK12-NEXT: [[CONV21:%.*]] = trunc i64 [[ADD]] to i32
	// CHECK12-NEXT: store i32 [[CONV21]], i32* [[I11]], align 4			// CHECK12-NEXT: store i32 [[CONV21]], i32* [[I11]], align 4, !llvm.access.group !6
	// CHECK12-NEXT: [[TMP23:%.]] = load i64, i64 [[DOTOMP_IV]], align 8			// CHECK12-NEXT: [[TMP23:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !6
	// CHECK12-NEXT: [[TMP24:%.]] = load i64, i64 [[DOTOMP_IV]], align 8			// CHECK12-NEXT: [[TMP24:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !6
	// CHECK12-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_4]], align 4			// CHECK12-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_4]], align 4, !llvm.access.group !6
	// CHECK12-NEXT: [[SUB22:%.*]] = sub nsw i32 [[TMP25]], 0			// CHECK12-NEXT: [[SUB22:%.*]] = sub nsw i32 [[TMP25]], 0
	// CHECK12-NEXT: [[DIV23:%.*]] = sdiv i32 [[SUB22]], 1			// CHECK12-NEXT: [[DIV23:%.*]] = sdiv i32 [[SUB22]], 1
	// CHECK12-NEXT: [[MUL24:%.*]] = mul nsw i32 1, [[DIV23]]			// CHECK12-NEXT: [[MUL24:%.*]] = mul nsw i32 1, [[DIV23]]
	// CHECK12-NEXT: [[CONV25:%.*]] = sext i32 [[MUL24]] to i64			// CHECK12-NEXT: [[CONV25:%.*]] = sext i32 [[MUL24]] to i64
	// CHECK12-NEXT: [[DIV26:%.*]] = sdiv i64 [[TMP24]], [[CONV25]]			// CHECK12-NEXT: [[DIV26:%.*]] = sdiv i64 [[TMP24]], [[CONV25]]
	// CHECK12-NEXT: [[TMP26:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_4]], align 4			// CHECK12-NEXT: [[TMP26:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_4]], align 4, !llvm.access.group !6
	// CHECK12-NEXT: [[SUB27:%.*]] = sub nsw i32 [[TMP26]], 0			// CHECK12-NEXT: [[SUB27:%.*]] = sub nsw i32 [[TMP26]], 0
	// CHECK12-NEXT: [[DIV28:%.*]] = sdiv i32 [[SUB27]], 1			// CHECK12-NEXT: [[DIV28:%.*]] = sdiv i32 [[SUB27]], 1
	// CHECK12-NEXT: [[MUL29:%.*]] = mul nsw i32 1, [[DIV28]]			// CHECK12-NEXT: [[MUL29:%.*]] = mul nsw i32 1, [[DIV28]]
	// CHECK12-NEXT: [[CONV30:%.*]] = sext i32 [[MUL29]] to i64			// CHECK12-NEXT: [[CONV30:%.*]] = sext i32 [[MUL29]] to i64
	// CHECK12-NEXT: [[MUL31:%.*]] = mul nsw i64 [[DIV26]], [[CONV30]]			// CHECK12-NEXT: [[MUL31:%.*]] = mul nsw i64 [[DIV26]], [[CONV30]]
	// CHECK12-NEXT: [[SUB32:%.*]] = sub nsw i64 [[TMP23]], [[MUL31]]			// CHECK12-NEXT: [[SUB32:%.*]] = sub nsw i64 [[TMP23]], [[MUL31]]
	// CHECK12-NEXT: [[MUL33:%.*]] = mul nsw i64 [[SUB32]], 1			// CHECK12-NEXT: [[MUL33:%.*]] = mul nsw i64 [[SUB32]], 1
	// CHECK12-NEXT: [[ADD34:%.*]] = add nsw i64 0, [[MUL33]]			// CHECK12-NEXT: [[ADD34:%.*]] = add nsw i64 0, [[MUL33]]
	// CHECK12-NEXT: [[CONV35:%.*]] = trunc i64 [[ADD34]] to i32			// CHECK12-NEXT: [[CONV35:%.*]] = trunc i64 [[ADD34]] to i32
	// CHECK12-NEXT: store i32 [[CONV35]], i32* [[J12]], align 4			// CHECK12-NEXT: store i32 [[CONV35]], i32* [[J12]], align 4, !llvm.access.group !6
	// CHECK12-NEXT: [[TMP27:%.]] = load i32, i32 [[I11]], align 4			// CHECK12-NEXT: [[TMP27:%.]] = load i32, i32 [[I11]], align 4, !llvm.access.group !6
	// CHECK12-NEXT: [[TMP28:%.*]] = mul nsw i32 [[TMP27]], [[TMP3]]			// CHECK12-NEXT: [[TMP28:%.*]] = mul nsw i32 [[TMP27]], [[TMP3]]
	// CHECK12-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP4]], i32 [[TMP28]]			// CHECK12-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP4]], i32 [[TMP28]]
	// CHECK12-NEXT: [[TMP29:%.]] = load i32, i32 [[J12]], align 4			// CHECK12-NEXT: [[TMP29:%.]] = load i32, i32 [[J12]], align 4, !llvm.access.group !6
	// CHECK12-NEXT: [[ARRAYIDX36:%.]] = getelementptr inbounds i32, i32 [[ARRAYIDX]], i32 [[TMP29]]			// CHECK12-NEXT: [[ARRAYIDX36:%.]] = getelementptr inbounds i32, i32 [[ARRAYIDX]], i32 [[TMP29]]
	// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX36]], align 4			// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX36]], align 4, !llvm.access.group !6
	// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK12: omp.body.continue:			// CHECK12: omp.body.continue:
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK12: omp.inner.for.inc:			// CHECK12: omp.inner.for.inc:
	// CHECK12-NEXT: [[TMP30:%.]] = load i64, i64 [[DOTOMP_IV]], align 8			// CHECK12-NEXT: [[TMP30:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !6
	// CHECK12-NEXT: [[ADD37:%.*]] = add nsw i64 [[TMP30]], 1			// CHECK12-NEXT: [[ADD37:%.*]] = add nsw i64 [[TMP30]], 1
	// CHECK12-NEXT: store i64 [[ADD37]], i64* [[DOTOMP_IV]], align 8			// CHECK12-NEXT: store i64 [[ADD37]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !6
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]
	// CHECK12: omp.inner.for.end:			// CHECK12: omp.inner.for.end:
	// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK12: omp.loop.exit:			// CHECK12: omp.loop.exit:
	// CHECK12-NEXT: [[TMP31:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4			// CHECK12-NEXT: [[TMP31:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4
	// CHECK12-NEXT: [[TMP32:%.]] = load i32, i32 [[TMP31]], align 4			// CHECK12-NEXT: [[TMP32:%.]] = load i32, i32 [[TMP31]], align 4
	// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP32]])			// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP32]])
	// CHECK12-NEXT: [[TMP33:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK12-NEXT: [[TMP33:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK12-NEXT: [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 0			// CHECK12-NEXT: [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 0
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	// CHECK12-NEXT: br label [[COND_END]]			// CHECK12-NEXT: br label [[COND_END]]
	// CHECK12: cond.end:			// CHECK12: cond.end:
	// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 19, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]			// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 19, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
	// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK12-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK12-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK12-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK12-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK12: omp.inner.for.cond:			// CHECK12: omp.inner.for.cond:
	// CHECK12-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK12-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12
	// CHECK12-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK12-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !12
	// CHECK12-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK12-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK12-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK12-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK12: omp.inner.for.body:			// CHECK12: omp.inner.for.body:
	// CHECK12-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK12-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12
	// CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP8]], 2			// CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP8]], 2
	// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1			// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1
	// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !12
	// CHECK12-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK12-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12
	// CHECK12-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK12-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12
	// CHECK12-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP10]], 2			// CHECK12-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP10]], 2
	// CHECK12-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 2			// CHECK12-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 2
	// CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP9]], [[MUL4]]			// CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP9]], [[MUL4]]
	// CHECK12-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1			// CHECK12-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1
	// CHECK12-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]]			// CHECK12-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]]
	// CHECK12-NEXT: store i32 [[ADD6]], i32* [[J]], align 4			// CHECK12-NEXT: store i32 [[ADD6]], i32* [[J]], align 4, !llvm.access.group !12
	// CHECK12-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4			// CHECK12-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !12
	// CHECK12-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]] [[TMP0]], i32 0, i32 [[TMP11]]			// CHECK12-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]] [[TMP0]], i32 0, i32 [[TMP11]]
	// CHECK12-NEXT: [[TMP12:%.]] = load i32, i32 [[J]], align 4			// CHECK12-NEXT: [[TMP12:%.]] = load i32, i32 [[J]], align 4, !llvm.access.group !12
	// CHECK12-NEXT: [[ARRAYIDX7:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[ARRAYIDX]], i32 0, i32 [[TMP12]]			// CHECK12-NEXT: [[ARRAYIDX7:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[ARRAYIDX]], i32 0, i32 [[TMP12]]
	// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX7]], align 4			// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX7]], align 4, !llvm.access.group !12
	// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK12: omp.body.continue:			// CHECK12: omp.body.continue:
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK12: omp.inner.for.inc:			// CHECK12: omp.inner.for.inc:
	// CHECK12-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK12-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12
	// CHECK12-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP13]], 1			// CHECK12-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP13]], 1
	// CHECK12-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4			// CHECK12-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]
	// CHECK12: omp.inner.for.end:			// CHECK12: omp.inner.for.end:
	// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK12: omp.loop.exit:			// CHECK12: omp.loop.exit:
	// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])			// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
	// CHECK12-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK12-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK12-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0			// CHECK12-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0
	// CHECK12-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK12-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK12: .omp.final.then:			// CHECK12: .omp.final.then:
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clang/test/OpenMP/teams_distribute_simd_firstprivate_codegen.cpp

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	// CHECK1-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8			// CHECK1-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8
	// CHECK1-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8			// CHECK1-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8
	// CHECK1-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8			// CHECK1-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8
	// CHECK1-NEXT: [[CONV:%.]] = bitcast i64 [[T_VAR_ADDR]] to i32*			// CHECK1-NEXT: [[CONV:%.]] = bitcast i64 [[T_VAR_ADDR]] to i32*
	// CHECK1-NEXT: [[TMP0:%.]] = load [2 x i32], [2 x i32]** [[VEC_ADDR]], align 8			// CHECK1-NEXT: [[TMP0:%.]] = load [2 x i32], [2 x i32]** [[VEC_ADDR]], align 8
	// CHECK1-NEXT: [[TMP1:%.]] = load [2 x %struct.S], [2 x %struct.S]** [[S_ARR_ADDR]], align 8			// CHECK1-NEXT: [[TMP1:%.]] = load [2 x %struct.S], [2 x %struct.S]** [[S_ARR_ADDR]], align 8
	// CHECK1-NEXT: [[TMP2:%.]] = load %struct.S, %struct.S** [[VAR_ADDR]], align 8			// CHECK1-NEXT: [[TMP2:%.]] = load %struct.S, %struct.S** [[VAR_ADDR]], align 8
	// CHECK1-NEXT: [[CONV1:%.]] = bitcast i64 [[SIVAR_ADDR]] to i32*			// CHECK1-NEXT: [[CONV1:%.]] = bitcast i64 [[SIVAR_ADDR]] to i32*
	// CHECK1-NEXT: [[TMP3:%.]] = load i32, i32 [[CONV]], align 4			// CHECK1-NEXT: [[TMP3:%.]] = load i32, i32 [[CONV]], align 8
	// CHECK1-NEXT: [[CONV2:%.]] = bitcast i64 [[T_VAR_CASTED]] to i32*			// CHECK1-NEXT: [[CONV2:%.]] = bitcast i64 [[T_VAR_CASTED]] to i32*
	// CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4			// CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
	// CHECK1-NEXT: [[TMP4:%.]] = load i64, i64 [[T_VAR_CASTED]], align 8			// CHECK1-NEXT: [[TMP4:%.]] = load i64, i64 [[T_VAR_CASTED]], align 8
	// CHECK1-NEXT: [[TMP5:%.]] = load i32, i32 [[CONV1]], align 4			// CHECK1-NEXT: [[TMP5:%.]] = load i32, i32 [[CONV1]], align 8
	// CHECK1-NEXT: [[CONV3:%.]] = bitcast i64 [[SIVAR_CASTED]] to i32*			// CHECK1-NEXT: [[CONV3:%.]] = bitcast i64 [[SIVAR_CASTED]] to i32*
	// CHECK1-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4			// CHECK1-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4
	// CHECK1-NEXT: [[TMP6:%.]] = load i64, i64 [[SIVAR_CASTED]], align 8			// CHECK1-NEXT: [[TMP6:%.]] = load i64, i64 [[SIVAR_CASTED]], align 8
	// CHECK1-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32, i32, ...)* bitcast (void (i32, i32, [2 x i32], i64, [2 x %struct.S], %struct.S, i64) @.omp_outlined. to void (i32, i32, ...)), [2 x i32] [[TMP0]], i64 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP2]], i64 [[TMP6]])			// CHECK1-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32, i32, ...)* bitcast (void (i32, i32, [2 x i32], i64, [2 x %struct.S], %struct.S, i64) @.omp_outlined. to void (i32, i32, ...)), [2 x i32] [[TMP0]], i64 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP2]], i64 [[TMP6]])
	// CHECK1-NEXT: ret void			// CHECK1-NEXT: ret void
	//			//
	//			//
	// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined.			// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined.
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	// CHECK1-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]			// CHECK1-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]
	// CHECK1: omp.inner.for.cond.cleanup:			// CHECK1: omp.inner.for.cond.cleanup:
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
	// CHECK1: omp.inner.for.body:			// CHECK1: omp.inner.for.body:
	// CHECK1-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5			// CHECK1-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1			// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1
	// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !5			// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !5
	// CHECK1-NEXT: [[TMP15:%.]] = load i32, i32 [[CONV]], align 4, !llvm.access.group !5			// CHECK1-NEXT: [[TMP15:%.]] = load i32, i32 [[CONV]], align 8, !llvm.access.group !5
	// CHECK1-NEXT: [[TMP16:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !5			// CHECK1-NEXT: [[TMP16:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !5
	// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64			// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64
	// CHECK1-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC2]], i64 0, i64 [[IDXPROM]]			// CHECK1-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC2]], i64 0, i64 [[IDXPROM]]
	// CHECK1-NEXT: store i32 [[TMP15]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !5			// CHECK1-NEXT: store i32 [[TMP15]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !5
	// CHECK1-NEXT: [[TMP17:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !5			// CHECK1-NEXT: [[TMP17:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !5
	// CHECK1-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP17]] to i64			// CHECK1-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP17]] to i64
	// CHECK1-NEXT: [[ARRAYIDX9:%.]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S] [[S_ARR3]], i64 0, i64 [[IDXPROM8]]			// CHECK1-NEXT: [[ARRAYIDX9:%.]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S] [[S_ARR3]], i64 0, i64 [[IDXPROM8]]
	// CHECK1-NEXT: [[TMP18:%.]] = bitcast %struct.S [[ARRAYIDX9]] to i8*			// CHECK1-NEXT: [[TMP18:%.]] = bitcast %struct.S [[ARRAYIDX9]] to i8*
	// CHECK1-NEXT: [[TMP19:%.]] = bitcast %struct.S [[VAR5]] to i8*			// CHECK1-NEXT: [[TMP19:%.]] = bitcast %struct.S [[VAR5]] to i8*
	// CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP18]], i8* align 4 [[TMP19]], i64 4, i1 false), !llvm.access.group !5			// CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP18]], i8* align 4 [[TMP19]], i64 4, i1 false), !llvm.access.group !5
	// CHECK1-NEXT: [[TMP20:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !5			// CHECK1-NEXT: [[TMP20:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !5
	// CHECK1-NEXT: [[TMP21:%.]] = load i32, i32 [[CONV1]], align 4, !llvm.access.group !5			// CHECK1-NEXT: [[TMP21:%.]] = load i32, i32 [[CONV1]], align 8, !llvm.access.group !5
	// CHECK1-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP21]], [[TMP20]]			// CHECK1-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP21]], [[TMP20]]
	// CHECK1-NEXT: store i32 [[ADD10]], i32* [[CONV1]], align 4, !llvm.access.group !5			// CHECK1-NEXT: store i32 [[ADD10]], i32* [[CONV1]], align 8, !llvm.access.group !5
	// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK1: omp.body.continue:			// CHECK1: omp.body.continue:
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK1: omp.inner.for.inc:			// CHECK1: omp.inner.for.inc:
	// CHECK1-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5			// CHECK1-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK1-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP22]], 1			// CHECK1-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP22]], 1
	// CHECK1-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5			// CHECK1-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]
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	// CHECK1-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8			// CHECK1-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8
	// CHECK1-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8			// CHECK1-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
	// CHECK1-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8			// CHECK1-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8
	// CHECK1-NEXT: [[CONV:%.]] = bitcast i64 [[T_VAR_ADDR]] to i32*			// CHECK1-NEXT: [[CONV:%.]] = bitcast i64 [[T_VAR_ADDR]] to i32*
	// CHECK1-NEXT: [[TMP0:%.]] = load [2 x i32], [2 x i32]** [[VEC_ADDR]], align 8			// CHECK1-NEXT: [[TMP0:%.]] = load [2 x i32], [2 x i32]** [[VEC_ADDR]], align 8
	// CHECK1-NEXT: [[TMP1:%.]] = load [2 x %struct.S.0], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8			// CHECK1-NEXT: [[TMP1:%.]] = load [2 x %struct.S.0], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
	// CHECK1-NEXT: [[TMP2:%.]] = load %struct.S.0, %struct.S.0** [[VAR_ADDR]], align 8			// CHECK1-NEXT: [[TMP2:%.]] = load %struct.S.0, %struct.S.0** [[VAR_ADDR]], align 8
	// CHECK1-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8			// CHECK1-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8
	// CHECK1-NEXT: [[TMP3:%.]] = load i32, i32 [[CONV]], align 4			// CHECK1-NEXT: [[TMP3:%.]] = load i32, i32 [[CONV]], align 8
	// CHECK1-NEXT: [[CONV1:%.]] = bitcast i64 [[T_VAR_CASTED]] to i32*			// CHECK1-NEXT: [[CONV1:%.]] = bitcast i64 [[T_VAR_CASTED]] to i32*
	// CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4			// CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4
	// CHECK1-NEXT: [[TMP4:%.]] = load i64, i64 [[T_VAR_CASTED]], align 8			// CHECK1-NEXT: [[TMP4:%.]] = load i64, i64 [[T_VAR_CASTED]], align 8
	// CHECK1-NEXT: [[TMP5:%.]] = load %struct.S.0, %struct.S.0** [[TMP]], align 8			// CHECK1-NEXT: [[TMP5:%.]] = load %struct.S.0, %struct.S.0** [[TMP]], align 8
	// CHECK1-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32, i32, ...)* bitcast (void (i32, i32, [2 x i32], i64, [2 x %struct.S.0], %struct.S.0) @.omp_outlined..3 to void (i32, i32, ...)), [2 x i32] [[TMP0]], i64 [[TMP4]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP5]])			// CHECK1-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32, i32, ...)* bitcast (void (i32, i32, [2 x i32], i64, [2 x %struct.S.0], %struct.S.0) @.omp_outlined..3 to void (i32, i32, ...)), [2 x i32] [[TMP0]], i64 [[TMP4]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP5]])
	// CHECK1-NEXT: ret void			// CHECK1-NEXT: ret void
	//			//
	//			//
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	// CHECK1-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]			// CHECK1-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]
	// CHECK1: omp.inner.for.cond.cleanup:			// CHECK1: omp.inner.for.cond.cleanup:
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
	// CHECK1: omp.inner.for.body:			// CHECK1: omp.inner.for.body:
	// CHECK1-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11			// CHECK1-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11
	// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1			// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1
	// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11			// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11
	// CHECK1-NEXT: [[TMP16:%.]] = load i32, i32 [[CONV]], align 4, !llvm.access.group !11			// CHECK1-NEXT: [[TMP16:%.]] = load i32, i32 [[CONV]], align 8, !llvm.access.group !11
	// CHECK1-NEXT: [[TMP17:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !11			// CHECK1-NEXT: [[TMP17:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !11
	// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64			// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64
	// CHECK1-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC2]], i64 0, i64 [[IDXPROM]]			// CHECK1-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC2]], i64 0, i64 [[IDXPROM]]
	// CHECK1-NEXT: store i32 [[TMP16]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !11			// CHECK1-NEXT: store i32 [[TMP16]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !11
	// CHECK1-NEXT: [[TMP18:%.]] = load %struct.S.0, %struct.S.0** [[_TMP7]], align 8, !llvm.access.group !11			// CHECK1-NEXT: [[TMP18:%.]] = load %struct.S.0, %struct.S.0** [[_TMP7]], align 8, !llvm.access.group !11
	// CHECK1-NEXT: [[TMP19:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !11			// CHECK1-NEXT: [[TMP19:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !11
	// CHECK1-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP19]] to i64			// CHECK1-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP19]] to i64
	// CHECK1-NEXT: [[ARRAYIDX10:%.]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0] [[S_ARR3]], i64 0, i64 [[IDXPROM9]]			// CHECK1-NEXT: [[ARRAYIDX10:%.]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0] [[S_ARR3]], i64 0, i64 [[IDXPROM9]]
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	// CHECK2-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8			// CHECK2-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8
	// CHECK2-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8			// CHECK2-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8
	// CHECK2-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8			// CHECK2-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8
	// CHECK2-NEXT: [[CONV:%.]] = bitcast i64 [[T_VAR_ADDR]] to i32*			// CHECK2-NEXT: [[CONV:%.]] = bitcast i64 [[T_VAR_ADDR]] to i32*
	// CHECK2-NEXT: [[TMP0:%.]] = load [2 x i32], [2 x i32]** [[VEC_ADDR]], align 8			// CHECK2-NEXT: [[TMP0:%.]] = load [2 x i32], [2 x i32]** [[VEC_ADDR]], align 8
	// CHECK2-NEXT: [[TMP1:%.]] = load [2 x %struct.S], [2 x %struct.S]** [[S_ARR_ADDR]], align 8			// CHECK2-NEXT: [[TMP1:%.]] = load [2 x %struct.S], [2 x %struct.S]** [[S_ARR_ADDR]], align 8
	// CHECK2-NEXT: [[TMP2:%.]] = load %struct.S, %struct.S** [[VAR_ADDR]], align 8			// CHECK2-NEXT: [[TMP2:%.]] = load %struct.S, %struct.S** [[VAR_ADDR]], align 8
	// CHECK2-NEXT: [[CONV1:%.]] = bitcast i64 [[SIVAR_ADDR]] to i32*			// CHECK2-NEXT: [[CONV1:%.]] = bitcast i64 [[SIVAR_ADDR]] to i32*
	// CHECK2-NEXT: [[TMP3:%.]] = load i32, i32 [[CONV]], align 4			// CHECK2-NEXT: [[TMP3:%.]] = load i32, i32 [[CONV]], align 8
	// CHECK2-NEXT: [[CONV2:%.]] = bitcast i64 [[T_VAR_CASTED]] to i32*			// CHECK2-NEXT: [[CONV2:%.]] = bitcast i64 [[T_VAR_CASTED]] to i32*
	// CHECK2-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4			// CHECK2-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
	// CHECK2-NEXT: [[TMP4:%.]] = load i64, i64 [[T_VAR_CASTED]], align 8			// CHECK2-NEXT: [[TMP4:%.]] = load i64, i64 [[T_VAR_CASTED]], align 8
	// CHECK2-NEXT: [[TMP5:%.]] = load i32, i32 [[CONV1]], align 4			// CHECK2-NEXT: [[TMP5:%.]] = load i32, i32 [[CONV1]], align 8
	// CHECK2-NEXT: [[CONV3:%.]] = bitcast i64 [[SIVAR_CASTED]] to i32*			// CHECK2-NEXT: [[CONV3:%.]] = bitcast i64 [[SIVAR_CASTED]] to i32*
	// CHECK2-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4			// CHECK2-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4
	// CHECK2-NEXT: [[TMP6:%.]] = load i64, i64 [[SIVAR_CASTED]], align 8			// CHECK2-NEXT: [[TMP6:%.]] = load i64, i64 [[SIVAR_CASTED]], align 8
	// CHECK2-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32, i32, ...)* bitcast (void (i32, i32, [2 x i32], i64, [2 x %struct.S], %struct.S, i64) @.omp_outlined. to void (i32, i32, ...)), [2 x i32] [[TMP0]], i64 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP2]], i64 [[TMP6]])			// CHECK2-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32, i32, ...)* bitcast (void (i32, i32, [2 x i32], i64, [2 x %struct.S], %struct.S, i64) @.omp_outlined. to void (i32, i32, ...)), [2 x i32] [[TMP0]], i64 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP2]], i64 [[TMP6]])
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined.			// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined.
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	// CHECK2-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]			// CHECK2-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]
	// CHECK2: omp.inner.for.cond.cleanup:			// CHECK2: omp.inner.for.cond.cleanup:
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_END:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
	// CHECK2: omp.inner.for.body:			// CHECK2: omp.inner.for.body:
	// CHECK2-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5			// CHECK2-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1			// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1
	// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !5			// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !5
	// CHECK2-NEXT: [[TMP15:%.]] = load i32, i32 [[CONV]], align 4, !llvm.access.group !5			// CHECK2-NEXT: [[TMP15:%.]] = load i32, i32 [[CONV]], align 8, !llvm.access.group !5
	// CHECK2-NEXT: [[TMP16:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !5			// CHECK2-NEXT: [[TMP16:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !5
	// CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64			// CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64
	// CHECK2-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC2]], i64 0, i64 [[IDXPROM]]			// CHECK2-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC2]], i64 0, i64 [[IDXPROM]]
	// CHECK2-NEXT: store i32 [[TMP15]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !5			// CHECK2-NEXT: store i32 [[TMP15]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !5
	// CHECK2-NEXT: [[TMP17:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !5			// CHECK2-NEXT: [[TMP17:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !5
	// CHECK2-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP17]] to i64			// CHECK2-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP17]] to i64
	// CHECK2-NEXT: [[ARRAYIDX9:%.]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S] [[S_ARR3]], i64 0, i64 [[IDXPROM8]]			// CHECK2-NEXT: [[ARRAYIDX9:%.]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S] [[S_ARR3]], i64 0, i64 [[IDXPROM8]]
	// CHECK2-NEXT: [[TMP18:%.]] = bitcast %struct.S [[ARRAYIDX9]] to i8*			// CHECK2-NEXT: [[TMP18:%.]] = bitcast %struct.S [[ARRAYIDX9]] to i8*
	// CHECK2-NEXT: [[TMP19:%.]] = bitcast %struct.S [[VAR5]] to i8*			// CHECK2-NEXT: [[TMP19:%.]] = bitcast %struct.S [[VAR5]] to i8*
	// CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP18]], i8* align 4 [[TMP19]], i64 4, i1 false), !llvm.access.group !5			// CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP18]], i8* align 4 [[TMP19]], i64 4, i1 false), !llvm.access.group !5
	// CHECK2-NEXT: [[TMP20:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !5			// CHECK2-NEXT: [[TMP20:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !5
	// CHECK2-NEXT: [[TMP21:%.]] = load i32, i32 [[CONV1]], align 4, !llvm.access.group !5			// CHECK2-NEXT: [[TMP21:%.]] = load i32, i32 [[CONV1]], align 8, !llvm.access.group !5
	// CHECK2-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP21]], [[TMP20]]			// CHECK2-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP21]], [[TMP20]]
	// CHECK2-NEXT: store i32 [[ADD10]], i32* [[CONV1]], align 4, !llvm.access.group !5			// CHECK2-NEXT: store i32 [[ADD10]], i32* [[CONV1]], align 8, !llvm.access.group !5
	// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK2: omp.body.continue:			// CHECK2: omp.body.continue:
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK2: omp.inner.for.inc:			// CHECK2: omp.inner.for.inc:
	// CHECK2-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5			// CHECK2-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK2-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP22]], 1			// CHECK2-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP22]], 1
	// CHECK2-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5			// CHECK2-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]
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	// CHECK2-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8			// CHECK2-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8
	// CHECK2-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8			// CHECK2-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
	// CHECK2-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8			// CHECK2-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8
	// CHECK2-NEXT: [[CONV:%.]] = bitcast i64 [[T_VAR_ADDR]] to i32*			// CHECK2-NEXT: [[CONV:%.]] = bitcast i64 [[T_VAR_ADDR]] to i32*
	// CHECK2-NEXT: [[TMP0:%.]] = load [2 x i32], [2 x i32]** [[VEC_ADDR]], align 8			// CHECK2-NEXT: [[TMP0:%.]] = load [2 x i32], [2 x i32]** [[VEC_ADDR]], align 8
	// CHECK2-NEXT: [[TMP1:%.]] = load [2 x %struct.S.0], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8			// CHECK2-NEXT: [[TMP1:%.]] = load [2 x %struct.S.0], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
	// CHECK2-NEXT: [[TMP2:%.]] = load %struct.S.0, %struct.S.0** [[VAR_ADDR]], align 8			// CHECK2-NEXT: [[TMP2:%.]] = load %struct.S.0, %struct.S.0** [[VAR_ADDR]], align 8
	// CHECK2-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8			// CHECK2-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8
	// CHECK2-NEXT: [[TMP3:%.]] = load i32, i32 [[CONV]], align 4			// CHECK2-NEXT: [[TMP3:%.]] = load i32, i32 [[CONV]], align 8
	// CHECK2-NEXT: [[CONV1:%.]] = bitcast i64 [[T_VAR_CASTED]] to i32*			// CHECK2-NEXT: [[CONV1:%.]] = bitcast i64 [[T_VAR_CASTED]] to i32*
	// CHECK2-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4			// CHECK2-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4
	// CHECK2-NEXT: [[TMP4:%.]] = load i64, i64 [[T_VAR_CASTED]], align 8			// CHECK2-NEXT: [[TMP4:%.]] = load i64, i64 [[T_VAR_CASTED]], align 8
	// CHECK2-NEXT: [[TMP5:%.]] = load %struct.S.0, %struct.S.0** [[TMP]], align 8			// CHECK2-NEXT: [[TMP5:%.]] = load %struct.S.0, %struct.S.0** [[TMP]], align 8
	// CHECK2-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32, i32, ...)* bitcast (void (i32, i32, [2 x i32], i64, [2 x %struct.S.0], %struct.S.0) @.omp_outlined..3 to void (i32, i32, ...)), [2 x i32] [[TMP0]], i64 [[TMP4]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP5]])			// CHECK2-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32, i32, ...)* bitcast (void (i32, i32, [2 x i32], i64, [2 x %struct.S.0], %struct.S.0) @.omp_outlined..3 to void (i32, i32, ...)), [2 x i32] [[TMP0]], i64 [[TMP4]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP5]])
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	//			//
	//			//
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	// CHECK2-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]			// CHECK2-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]
	// CHECK2: omp.inner.for.cond.cleanup:			// CHECK2: omp.inner.for.cond.cleanup:
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_END:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
	// CHECK2: omp.inner.for.body:			// CHECK2: omp.inner.for.body:
	// CHECK2-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11			// CHECK2-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11
	// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1			// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1
	// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11			// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11
	// CHECK2-NEXT: [[TMP16:%.]] = load i32, i32 [[CONV]], align 4, !llvm.access.group !11			// CHECK2-NEXT: [[TMP16:%.]] = load i32, i32 [[CONV]], align 8, !llvm.access.group !11
	// CHECK2-NEXT: [[TMP17:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !11			// CHECK2-NEXT: [[TMP17:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !11
	// CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64			// CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64
	// CHECK2-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC2]], i64 0, i64 [[IDXPROM]]			// CHECK2-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC2]], i64 0, i64 [[IDXPROM]]
	// CHECK2-NEXT: store i32 [[TMP16]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !11			// CHECK2-NEXT: store i32 [[TMP16]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !11
	// CHECK2-NEXT: [[TMP18:%.]] = load %struct.S.0, %struct.S.0** [[_TMP7]], align 8, !llvm.access.group !11			// CHECK2-NEXT: [[TMP18:%.]] = load %struct.S.0, %struct.S.0** [[_TMP7]], align 8, !llvm.access.group !11
	// CHECK2-NEXT: [[TMP19:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !11			// CHECK2-NEXT: [[TMP19:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !11
	// CHECK2-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP19]] to i64			// CHECK2-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP19]] to i64
	// CHECK2-NEXT: [[ARRAYIDX10:%.]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0] [[S_ARR3]], i64 0, i64 [[IDXPROM9]]			// CHECK2-NEXT: [[ARRAYIDX10:%.]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0] [[S_ARR3]], i64 0, i64 [[IDXPROM9]]
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	// CHECK9-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8			// CHECK9-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8
	// CHECK9-NEXT: store i64 [[G]], i64* [[G_ADDR]], align 8			// CHECK9-NEXT: store i64 [[G]], i64* [[G_ADDR]], align 8
	// CHECK9-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8			// CHECK9-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8
	// CHECK9-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8			// CHECK9-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8
	// CHECK9-NEXT: [[CONV:%.]] = bitcast i64 [[G_ADDR]] to i32*			// CHECK9-NEXT: [[CONV:%.]] = bitcast i64 [[G_ADDR]] to i32*
	// CHECK9-NEXT: [[CONV1:%.]] = bitcast i64 [[SIVAR_ADDR]] to i32*			// CHECK9-NEXT: [[CONV1:%.]] = bitcast i64 [[SIVAR_ADDR]] to i32*
	// CHECK9-NEXT: [[CONV2:%.]] = bitcast i64 [[G1_ADDR]] to i32*			// CHECK9-NEXT: [[CONV2:%.]] = bitcast i64 [[G1_ADDR]] to i32*
	// CHECK9-NEXT: store i32* [[CONV2]], i32** [[TMP]], align 8			// CHECK9-NEXT: store i32* [[CONV2]], i32** [[TMP]], align 8
	// CHECK9-NEXT: [[TMP0:%.]] = load i32, i32 [[CONV]], align 4			// CHECK9-NEXT: [[TMP0:%.]] = load i32, i32 [[CONV]], align 8
	// CHECK9-NEXT: [[CONV3:%.]] = bitcast i64 [[G_CASTED]] to i32*			// CHECK9-NEXT: [[CONV3:%.]] = bitcast i64 [[G_CASTED]] to i32*
	// CHECK9-NEXT: store i32 [[TMP0]], i32* [[CONV3]], align 4			// CHECK9-NEXT: store i32 [[TMP0]], i32* [[CONV3]], align 4
	// CHECK9-NEXT: [[TMP1:%.]] = load i64, i64 [[G_CASTED]], align 8			// CHECK9-NEXT: [[TMP1:%.]] = load i64, i64 [[G_CASTED]], align 8
	// CHECK9-NEXT: [[TMP2:%.]] = load i32, i32** [[TMP]], align 8			// CHECK9-NEXT: [[TMP2:%.]] = load i32, i32** [[TMP]], align 8
	// CHECK9-NEXT: [[TMP3:%.]] = load volatile i32, i32 [[TMP2]], align 4			// CHECK9-NEXT: [[TMP3:%.]] = load volatile i32, i32 [[TMP2]], align 4
	// CHECK9-NEXT: [[CONV4:%.]] = bitcast i64 [[G1_CASTED]] to i32*			// CHECK9-NEXT: [[CONV4:%.]] = bitcast i64 [[G1_CASTED]] to i32*
	// CHECK9-NEXT: store i32 [[TMP3]], i32* [[CONV4]], align 4			// CHECK9-NEXT: store i32 [[TMP3]], i32* [[CONV4]], align 4
	// CHECK9-NEXT: [[TMP4:%.]] = load i64, i64 [[G1_CASTED]], align 8			// CHECK9-NEXT: [[TMP4:%.]] = load i64, i64 [[G1_CASTED]], align 8
	// CHECK9-NEXT: [[TMP5:%.]] = load i32, i32 [[CONV1]], align 4			// CHECK9-NEXT: [[TMP5:%.]] = load i32, i32 [[CONV1]], align 8
	// CHECK9-NEXT: [[CONV5:%.]] = bitcast i64 [[SIVAR_CASTED]] to i32*			// CHECK9-NEXT: [[CONV5:%.]] = bitcast i64 [[SIVAR_CASTED]] to i32*
	// CHECK9-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4			// CHECK9-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4
	// CHECK9-NEXT: [[TMP6:%.]] = load i64, i64 [[SIVAR_CASTED]], align 8			// CHECK9-NEXT: [[TMP6:%.]] = load i64, i64 [[SIVAR_CASTED]], align 8
	// CHECK9-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i64)* @.omp_outlined. to void (i32, i32, ...)*), i64 [[TMP1]], i64 [[TMP4]], i64 [[TMP6]])			// CHECK9-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i64)* @.omp_outlined. to void (i32, i32, ...)*), i64 [[TMP1]], i64 [[TMP4]], i64 [[TMP6]])
	// CHECK9-NEXT: ret void			// CHECK9-NEXT: ret void
	//			//
	//			//
	// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined.			// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined.
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	// CHECK9-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !4			// CHECK9-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !4
	// CHECK9-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK9-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK9-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK9-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK9: omp.inner.for.body:			// CHECK9: omp.inner.for.body:
	// CHECK9-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !4			// CHECK9-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !4
	// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1			// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
	// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !4			// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !4
	// CHECK9-NEXT: store i32 1, i32* [[CONV]], align 4, !llvm.access.group !4			// CHECK9-NEXT: store i32 1, i32* [[CONV]], align 8, !llvm.access.group !4
	// CHECK9-NEXT: [[TMP8:%.]] = load i32, i32** [[TMP]], align 8, !llvm.access.group !4			// CHECK9-NEXT: [[TMP8:%.]] = load i32, i32** [[TMP]], align 8, !llvm.access.group !4
	// CHECK9-NEXT: store volatile i32 1, i32* [[TMP8]], align 4, !llvm.access.group !4			// CHECK9-NEXT: store volatile i32 1, i32* [[TMP8]], align 4, !llvm.access.group !4
	// CHECK9-NEXT: store i32 2, i32* [[CONV2]], align 4, !llvm.access.group !4			// CHECK9-NEXT: store i32 2, i32* [[CONV2]], align 8, !llvm.access.group !4
	// CHECK9-NEXT: [[TMP9:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 0			// CHECK9-NEXT: [[TMP9:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 0
	// CHECK9-NEXT: store i32* [[CONV]], i32** [[TMP9]], align 8, !llvm.access.group !4			// CHECK9-NEXT: store i32* [[CONV]], i32** [[TMP9]], align 8, !llvm.access.group !4
	// CHECK9-NEXT: [[TMP10:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 1			// CHECK9-NEXT: [[TMP10:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 1
	// CHECK9-NEXT: [[TMP11:%.]] = load i32, i32** [[TMP]], align 8, !llvm.access.group !4			// CHECK9-NEXT: [[TMP11:%.]] = load i32, i32** [[TMP]], align 8, !llvm.access.group !4
	// CHECK9-NEXT: store i32* [[TMP11]], i32** [[TMP10]], align 8, !llvm.access.group !4			// CHECK9-NEXT: store i32* [[TMP11]], i32** [[TMP10]], align 8, !llvm.access.group !4
	// CHECK9-NEXT: [[TMP12:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 2			// CHECK9-NEXT: [[TMP12:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 2
	// CHECK9-NEXT: store i32* [[CONV2]], i32** [[TMP12]], align 8, !llvm.access.group !4			// CHECK9-NEXT: store i32* [[CONV2]], i32** [[TMP12]], align 8, !llvm.access.group !4
	// CHECK9-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(24) [[REF_TMP]]), !llvm.access.group !4			// CHECK9-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(24) [[REF_TMP]]), !llvm.access.group !4
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	// CHECK10-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8			// CHECK10-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8
	// CHECK10-NEXT: store i64 [[G]], i64* [[G_ADDR]], align 8			// CHECK10-NEXT: store i64 [[G]], i64* [[G_ADDR]], align 8
	// CHECK10-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8			// CHECK10-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8
	// CHECK10-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8			// CHECK10-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8
	// CHECK10-NEXT: [[CONV:%.]] = bitcast i64 [[G_ADDR]] to i32*			// CHECK10-NEXT: [[CONV:%.]] = bitcast i64 [[G_ADDR]] to i32*
	// CHECK10-NEXT: [[CONV1:%.]] = bitcast i64 [[SIVAR_ADDR]] to i32*			// CHECK10-NEXT: [[CONV1:%.]] = bitcast i64 [[SIVAR_ADDR]] to i32*
	// CHECK10-NEXT: [[CONV2:%.]] = bitcast i64 [[G1_ADDR]] to i32*			// CHECK10-NEXT: [[CONV2:%.]] = bitcast i64 [[G1_ADDR]] to i32*
	// CHECK10-NEXT: store i32* [[CONV2]], i32** [[TMP]], align 8			// CHECK10-NEXT: store i32* [[CONV2]], i32** [[TMP]], align 8
	// CHECK10-NEXT: [[TMP0:%.]] = load i32, i32 [[CONV]], align 4			// CHECK10-NEXT: [[TMP0:%.]] = load i32, i32 [[CONV]], align 8
	// CHECK10-NEXT: [[CONV3:%.]] = bitcast i64 [[G_CASTED]] to i32*			// CHECK10-NEXT: [[CONV3:%.]] = bitcast i64 [[G_CASTED]] to i32*
	// CHECK10-NEXT: store i32 [[TMP0]], i32* [[CONV3]], align 4			// CHECK10-NEXT: store i32 [[TMP0]], i32* [[CONV3]], align 4
	// CHECK10-NEXT: [[TMP1:%.]] = load i64, i64 [[G_CASTED]], align 8			// CHECK10-NEXT: [[TMP1:%.]] = load i64, i64 [[G_CASTED]], align 8
	// CHECK10-NEXT: [[TMP2:%.]] = load i32, i32** [[TMP]], align 8			// CHECK10-NEXT: [[TMP2:%.]] = load i32, i32** [[TMP]], align 8
	// CHECK10-NEXT: [[TMP3:%.]] = load volatile i32, i32 [[TMP2]], align 4			// CHECK10-NEXT: [[TMP3:%.]] = load volatile i32, i32 [[TMP2]], align 4
	// CHECK10-NEXT: [[CONV4:%.]] = bitcast i64 [[G1_CASTED]] to i32*			// CHECK10-NEXT: [[CONV4:%.]] = bitcast i64 [[G1_CASTED]] to i32*
	// CHECK10-NEXT: store i32 [[TMP3]], i32* [[CONV4]], align 4			// CHECK10-NEXT: store i32 [[TMP3]], i32* [[CONV4]], align 4
	// CHECK10-NEXT: [[TMP4:%.]] = load i64, i64 [[G1_CASTED]], align 8			// CHECK10-NEXT: [[TMP4:%.]] = load i64, i64 [[G1_CASTED]], align 8
	// CHECK10-NEXT: [[TMP5:%.]] = load i32, i32 [[CONV1]], align 4			// CHECK10-NEXT: [[TMP5:%.]] = load i32, i32 [[CONV1]], align 8
	// CHECK10-NEXT: [[CONV5:%.]] = bitcast i64 [[SIVAR_CASTED]] to i32*			// CHECK10-NEXT: [[CONV5:%.]] = bitcast i64 [[SIVAR_CASTED]] to i32*
	// CHECK10-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4			// CHECK10-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4
	// CHECK10-NEXT: [[TMP6:%.]] = load i64, i64 [[SIVAR_CASTED]], align 8			// CHECK10-NEXT: [[TMP6:%.]] = load i64, i64 [[SIVAR_CASTED]], align 8
	// CHECK10-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i64)* @.omp_outlined. to void (i32, i32, ...)*), i64 [[TMP1]], i64 [[TMP4]], i64 [[TMP6]])			// CHECK10-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i64)* @.omp_outlined. to void (i32, i32, ...)*), i64 [[TMP1]], i64 [[TMP4]], i64 [[TMP6]])
	// CHECK10-NEXT: ret void			// CHECK10-NEXT: ret void
	//			//
	//			//
	// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined.			// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined.
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	// CHECK10-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !4			// CHECK10-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !4
	// CHECK10-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK10-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK10-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK10-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK10: omp.inner.for.body:			// CHECK10: omp.inner.for.body:
	// CHECK10-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !4			// CHECK10-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !4
	// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1			// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
	// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !4			// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !4
	// CHECK10-NEXT: store i32 1, i32* [[CONV]], align 4, !llvm.access.group !4			// CHECK10-NEXT: store i32 1, i32* [[CONV]], align 8, !llvm.access.group !4
	// CHECK10-NEXT: [[TMP8:%.]] = load i32, i32** [[TMP]], align 8, !llvm.access.group !4			// CHECK10-NEXT: [[TMP8:%.]] = load i32, i32** [[TMP]], align 8, !llvm.access.group !4
	// CHECK10-NEXT: store volatile i32 1, i32* [[TMP8]], align 4, !llvm.access.group !4			// CHECK10-NEXT: store volatile i32 1, i32* [[TMP8]], align 4, !llvm.access.group !4
	// CHECK10-NEXT: store i32 2, i32* [[CONV2]], align 4, !llvm.access.group !4			// CHECK10-NEXT: store i32 2, i32* [[CONV2]], align 8, !llvm.access.group !4
	// CHECK10-NEXT: [[TMP9:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 0			// CHECK10-NEXT: [[TMP9:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 0
	// CHECK10-NEXT: store i32* [[CONV]], i32** [[TMP9]], align 8, !llvm.access.group !4			// CHECK10-NEXT: store i32* [[CONV]], i32** [[TMP9]], align 8, !llvm.access.group !4
	// CHECK10-NEXT: [[TMP10:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 1			// CHECK10-NEXT: [[TMP10:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 1
	// CHECK10-NEXT: [[TMP11:%.]] = load i32, i32** [[TMP]], align 8, !llvm.access.group !4			// CHECK10-NEXT: [[TMP11:%.]] = load i32, i32** [[TMP]], align 8, !llvm.access.group !4
	// CHECK10-NEXT: store i32* [[TMP11]], i32** [[TMP10]], align 8, !llvm.access.group !4			// CHECK10-NEXT: store i32* [[TMP11]], i32** [[TMP10]], align 8, !llvm.access.group !4
	// CHECK10-NEXT: [[TMP12:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 2			// CHECK10-NEXT: [[TMP12:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 2
	// CHECK10-NEXT: store i32* [[CONV2]], i32** [[TMP12]], align 8, !llvm.access.group !4			// CHECK10-NEXT: store i32* [[CONV2]], i32** [[TMP12]], align 8, !llvm.access.group !4
	// CHECK10-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(24) [[REF_TMP]]), !llvm.access.group !4			// CHECK10-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(24) [[REF_TMP]]), !llvm.access.group !4
	▲ Show 20 Lines • Show All 301 Lines • Show Last 20 Lines

clang/test/OpenMP/teams_distribute_simd_lastprivate_codegen.cpp

This file is larger than 256 KB, so syntax highlighting is disabled by default.

	Show First 20 Lines • Show All 229 Lines • ▼ Show 20 Lines
	// CHECK1-NEXT: br label [[COND_END]]			// CHECK1-NEXT: br label [[COND_END]]
	// CHECK1: cond.end:			// CHECK1: cond.end:
	// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ]			// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ]
	// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK1-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK1: omp.inner.for.cond:			// CHECK1: omp.inner.for.cond:
	// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !4
	// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !4
	// CHECK1-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]			// CHECK1-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]
	// CHECK1-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK1-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK1: omp.inner.for.body:			// CHECK1: omp.inner.for.body:
	// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !4
	// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1			// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1
	// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !4
	// CHECK1-NEXT: store double 1.000000e+00, double* [[G2]], align 8			// CHECK1-NEXT: store double 1.000000e+00, double* [[G2]], align 8, !llvm.access.group !4
	// CHECK1-NEXT: [[TMP13:%.]] = load double, double** [[_TMP4]], align 8			// CHECK1-NEXT: [[TMP13:%.]] = load double, double** [[_TMP4]], align 8, !llvm.access.group !4
	// CHECK1-NEXT: store volatile double 1.000000e+00, double* [[TMP13]], align 8			// CHECK1-NEXT: store volatile double 1.000000e+00, double* [[TMP13]], align 8, !llvm.access.group !4
	// CHECK1-NEXT: store i32 3, i32* [[SVAR5]], align 4			// CHECK1-NEXT: store i32 3, i32* [[SVAR5]], align 4, !llvm.access.group !4
	// CHECK1-NEXT: store float 4.000000e+00, float* [[SFVAR6]], align 4			// CHECK1-NEXT: store float 4.000000e+00, float* [[SFVAR6]], align 4, !llvm.access.group !4
	// CHECK1-NEXT: [[TMP14:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 0			// CHECK1-NEXT: [[TMP14:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 0
	// CHECK1-NEXT: store double* [[G2]], double** [[TMP14]], align 8			// CHECK1-NEXT: store double* [[G2]], double** [[TMP14]], align 8, !llvm.access.group !4
	// CHECK1-NEXT: [[TMP15:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 1			// CHECK1-NEXT: [[TMP15:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 1
	// CHECK1-NEXT: [[TMP16:%.]] = load double, double** [[_TMP4]], align 8			// CHECK1-NEXT: [[TMP16:%.]] = load double, double** [[_TMP4]], align 8, !llvm.access.group !4
	// CHECK1-NEXT: store double* [[TMP16]], double** [[TMP15]], align 8			// CHECK1-NEXT: store double* [[TMP16]], double** [[TMP15]], align 8, !llvm.access.group !4
	// CHECK1-NEXT: [[TMP17:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 2			// CHECK1-NEXT: [[TMP17:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 2
	// CHECK1-NEXT: store i32* [[SVAR5]], i32** [[TMP17]], align 8			// CHECK1-NEXT: store i32* [[SVAR5]], i32** [[TMP17]], align 8, !llvm.access.group !4
	// CHECK1-NEXT: [[TMP18:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 3			// CHECK1-NEXT: [[TMP18:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 3
	// CHECK1-NEXT: store float* [[SFVAR6]], float** [[TMP18]], align 8			// CHECK1-NEXT: store float* [[SFVAR6]], float** [[TMP18]], align 8, !llvm.access.group !4
	// CHECK1-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(32) [[REF_TMP]])			// CHECK1-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(32) [[REF_TMP]]), !llvm.access.group !4
	// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK1: omp.body.continue:			// CHECK1: omp.body.continue:
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK1: omp.inner.for.inc:			// CHECK1: omp.inner.for.inc:
	// CHECK1-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !4
	// CHECK1-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP19]], 1			// CHECK1-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP19]], 1
	// CHECK1-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]
	// CHECK1: omp.inner.for.end:			// CHECK1: omp.inner.for.end:
	// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK1: omp.loop.exit:			// CHECK1: omp.loop.exit:
	// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]])			// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]])
	// CHECK1-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK1-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK1-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0			// CHECK1-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0
	// CHECK1-NEXT: br i1 [[TMP21]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK1-NEXT: br i1 [[TMP21]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK1: .omp.final.then:			// CHECK1: .omp.final.then:
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	// CHECK2-NEXT: br label [[COND_END]]			// CHECK2-NEXT: br label [[COND_END]]
	// CHECK2: cond.end:			// CHECK2: cond.end:
	// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ]			// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ]
	// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK2-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK2: omp.inner.for.cond:			// CHECK2: omp.inner.for.cond:
	// CHECK2-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !4
	// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !4
	// CHECK2-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]			// CHECK2-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]
	// CHECK2-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK2-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK2: omp.inner.for.body:			// CHECK2: omp.inner.for.body:
	// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !4
	// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1			// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1
	// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !4
	// CHECK2-NEXT: store double 1.000000e+00, double* [[G2]], align 8			// CHECK2-NEXT: store double 1.000000e+00, double* [[G2]], align 8, !llvm.access.group !4
	// CHECK2-NEXT: [[TMP13:%.]] = load double, double** [[_TMP4]], align 8			// CHECK2-NEXT: [[TMP13:%.]] = load double, double** [[_TMP4]], align 8, !llvm.access.group !4
	// CHECK2-NEXT: store volatile double 1.000000e+00, double* [[TMP13]], align 8			// CHECK2-NEXT: store volatile double 1.000000e+00, double* [[TMP13]], align 8, !llvm.access.group !4
	// CHECK2-NEXT: store i32 3, i32* [[SVAR5]], align 4			// CHECK2-NEXT: store i32 3, i32* [[SVAR5]], align 4, !llvm.access.group !4
	// CHECK2-NEXT: store float 4.000000e+00, float* [[SFVAR6]], align 4			// CHECK2-NEXT: store float 4.000000e+00, float* [[SFVAR6]], align 4, !llvm.access.group !4
	// CHECK2-NEXT: [[TMP14:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 0			// CHECK2-NEXT: [[TMP14:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 0
	// CHECK2-NEXT: store double* [[G2]], double** [[TMP14]], align 8			// CHECK2-NEXT: store double* [[G2]], double** [[TMP14]], align 8, !llvm.access.group !4
	// CHECK2-NEXT: [[TMP15:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 1			// CHECK2-NEXT: [[TMP15:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 1
	// CHECK2-NEXT: [[TMP16:%.]] = load double, double** [[_TMP4]], align 8			// CHECK2-NEXT: [[TMP16:%.]] = load double, double** [[_TMP4]], align 8, !llvm.access.group !4
	// CHECK2-NEXT: store double* [[TMP16]], double** [[TMP15]], align 8			// CHECK2-NEXT: store double* [[TMP16]], double** [[TMP15]], align 8, !llvm.access.group !4
	// CHECK2-NEXT: [[TMP17:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 2			// CHECK2-NEXT: [[TMP17:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 2
	// CHECK2-NEXT: store i32* [[SVAR5]], i32** [[TMP17]], align 8			// CHECK2-NEXT: store i32* [[SVAR5]], i32** [[TMP17]], align 8, !llvm.access.group !4
	// CHECK2-NEXT: [[TMP18:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 3			// CHECK2-NEXT: [[TMP18:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 3
	// CHECK2-NEXT: store float* [[SFVAR6]], float** [[TMP18]], align 8			// CHECK2-NEXT: store float* [[SFVAR6]], float** [[TMP18]], align 8, !llvm.access.group !4
	// CHECK2-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(32) [[REF_TMP]])			// CHECK2-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(32) [[REF_TMP]]), !llvm.access.group !4
	// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK2: omp.body.continue:			// CHECK2: omp.body.continue:
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK2: omp.inner.for.inc:			// CHECK2: omp.inner.for.inc:
	// CHECK2-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !4
	// CHECK2-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP19]], 1			// CHECK2-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP19]], 1
	// CHECK2-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]
	// CHECK2: omp.inner.for.end:			// CHECK2: omp.inner.for.end:
	// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK2: omp.loop.exit:			// CHECK2: omp.loop.exit:
	// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]])			// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]])
	// CHECK2-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK2-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK2-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0			// CHECK2-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0
	// CHECK2-NEXT: br i1 [[TMP21]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK2-NEXT: br i1 [[TMP21]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK2: .omp.final.then:			// CHECK2: .omp.final.then:
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	// CHECK3-NEXT: br label [[COND_END]]			// CHECK3-NEXT: br label [[COND_END]]
	// CHECK3: cond.end:			// CHECK3: cond.end:
	// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ]			// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ]
	// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK3-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK3-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK3-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4			// CHECK3-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK3: omp.inner.for.cond:			// CHECK3: omp.inner.for.cond:
	// CHECK3-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK3-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK3-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK3-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !5
	// CHECK3-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]			// CHECK3-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]
	// CHECK3-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK3-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK3: omp.inner.for.body:			// CHECK3: omp.inner.for.body:
	// CHECK3-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK3-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1			// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1
	// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !5
	// CHECK3-NEXT: store double 1.000000e+00, double* [[G2]], align 8			// CHECK3-NEXT: store double 1.000000e+00, double* [[G2]], align 8, !llvm.access.group !5
	// CHECK3-NEXT: [[TMP13:%.]] = load double, double** [[_TMP4]], align 4			// CHECK3-NEXT: [[TMP13:%.]] = load double, double** [[_TMP4]], align 4, !llvm.access.group !5
	// CHECK3-NEXT: store volatile double 1.000000e+00, double* [[TMP13]], align 4			// CHECK3-NEXT: store volatile double 1.000000e+00, double* [[TMP13]], align 4, !llvm.access.group !5
	// CHECK3-NEXT: store i32 3, i32* [[SVAR5]], align 4			// CHECK3-NEXT: store i32 3, i32* [[SVAR5]], align 4, !llvm.access.group !5
	// CHECK3-NEXT: store float 4.000000e+00, float* [[SFVAR6]], align 4			// CHECK3-NEXT: store float 4.000000e+00, float* [[SFVAR6]], align 4, !llvm.access.group !5
	// CHECK3-NEXT: [[TMP14:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 0			// CHECK3-NEXT: [[TMP14:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 0
	// CHECK3-NEXT: store double* [[G2]], double** [[TMP14]], align 4			// CHECK3-NEXT: store double* [[G2]], double** [[TMP14]], align 4, !llvm.access.group !5
	// CHECK3-NEXT: [[TMP15:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 1			// CHECK3-NEXT: [[TMP15:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 1
	// CHECK3-NEXT: [[TMP16:%.]] = load double, double** [[_TMP4]], align 4			// CHECK3-NEXT: [[TMP16:%.]] = load double, double** [[_TMP4]], align 4, !llvm.access.group !5
	// CHECK3-NEXT: store double* [[TMP16]], double** [[TMP15]], align 4			// CHECK3-NEXT: store double* [[TMP16]], double** [[TMP15]], align 4, !llvm.access.group !5
	// CHECK3-NEXT: [[TMP17:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 2			// CHECK3-NEXT: [[TMP17:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 2
	// CHECK3-NEXT: store i32* [[SVAR5]], i32** [[TMP17]], align 4			// CHECK3-NEXT: store i32* [[SVAR5]], i32** [[TMP17]], align 4, !llvm.access.group !5
	// CHECK3-NEXT: [[TMP18:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 3			// CHECK3-NEXT: [[TMP18:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 3
	// CHECK3-NEXT: store float* [[SFVAR6]], float** [[TMP18]], align 4			// CHECK3-NEXT: store float* [[SFVAR6]], float** [[TMP18]], align 4, !llvm.access.group !5
	// CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 4 dereferenceable(16) [[REF_TMP]])			// CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 4 dereferenceable(16) [[REF_TMP]]), !llvm.access.group !5
	// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK3: omp.body.continue:			// CHECK3: omp.body.continue:
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK3: omp.inner.for.inc:			// CHECK3: omp.inner.for.inc:
	// CHECK3-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK3-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK3-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP19]], 1			// CHECK3-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP19]], 1
	// CHECK3-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4			// CHECK3-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]
	// CHECK3: omp.inner.for.end:			// CHECK3: omp.inner.for.end:
	// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK3: omp.loop.exit:			// CHECK3: omp.loop.exit:
	// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]])			// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]])
	// CHECK3-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK3-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK3-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0			// CHECK3-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0
	// CHECK3-NEXT: br i1 [[TMP21]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK3-NEXT: br i1 [[TMP21]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK3: .omp.final.then:			// CHECK3: .omp.final.then:
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	// CHECK4-NEXT: br label [[COND_END]]			// CHECK4-NEXT: br label [[COND_END]]
	// CHECK4: cond.end:			// CHECK4: cond.end:
	// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ]			// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ]
	// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK4-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK4-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK4-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4			// CHECK4-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK4: omp.inner.for.cond:			// CHECK4: omp.inner.for.cond:
	// CHECK4-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK4-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK4-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK4-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !5
	// CHECK4-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]			// CHECK4-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]
	// CHECK4-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK4-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK4: omp.inner.for.body:			// CHECK4: omp.inner.for.body:
	// CHECK4-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK4-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1			// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1
	// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !5
	// CHECK4-NEXT: store double 1.000000e+00, double* [[G2]], align 8			// CHECK4-NEXT: store double 1.000000e+00, double* [[G2]], align 8, !llvm.access.group !5
	// CHECK4-NEXT: [[TMP13:%.]] = load double, double** [[_TMP4]], align 4			// CHECK4-NEXT: [[TMP13:%.]] = load double, double** [[_TMP4]], align 4, !llvm.access.group !5
	// CHECK4-NEXT: store volatile double 1.000000e+00, double* [[TMP13]], align 4			// CHECK4-NEXT: store volatile double 1.000000e+00, double* [[TMP13]], align 4, !llvm.access.group !5
	// CHECK4-NEXT: store i32 3, i32* [[SVAR5]], align 4			// CHECK4-NEXT: store i32 3, i32* [[SVAR5]], align 4, !llvm.access.group !5
	// CHECK4-NEXT: store float 4.000000e+00, float* [[SFVAR6]], align 4			// CHECK4-NEXT: store float 4.000000e+00, float* [[SFVAR6]], align 4, !llvm.access.group !5
	// CHECK4-NEXT: [[TMP14:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 0			// CHECK4-NEXT: [[TMP14:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 0
	// CHECK4-NEXT: store double* [[G2]], double** [[TMP14]], align 4			// CHECK4-NEXT: store double* [[G2]], double** [[TMP14]], align 4, !llvm.access.group !5
	// CHECK4-NEXT: [[TMP15:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 1			// CHECK4-NEXT: [[TMP15:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 1
	// CHECK4-NEXT: [[TMP16:%.]] = load double, double** [[_TMP4]], align 4			// CHECK4-NEXT: [[TMP16:%.]] = load double, double** [[_TMP4]], align 4, !llvm.access.group !5
	// CHECK4-NEXT: store double* [[TMP16]], double** [[TMP15]], align 4			// CHECK4-NEXT: store double* [[TMP16]], double** [[TMP15]], align 4, !llvm.access.group !5
	// CHECK4-NEXT: [[TMP17:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 2			// CHECK4-NEXT: [[TMP17:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 2
	// CHECK4-NEXT: store i32* [[SVAR5]], i32** [[TMP17]], align 4			// CHECK4-NEXT: store i32* [[SVAR5]], i32** [[TMP17]], align 4, !llvm.access.group !5
	// CHECK4-NEXT: [[TMP18:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 3			// CHECK4-NEXT: [[TMP18:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 3
	// CHECK4-NEXT: store float* [[SFVAR6]], float** [[TMP18]], align 4			// CHECK4-NEXT: store float* [[SFVAR6]], float** [[TMP18]], align 4, !llvm.access.group !5
	// CHECK4-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 4 dereferenceable(16) [[REF_TMP]])			// CHECK4-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 4 dereferenceable(16) [[REF_TMP]]), !llvm.access.group !5
	// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK4: omp.body.continue:			// CHECK4: omp.body.continue:
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK4: omp.inner.for.inc:			// CHECK4: omp.inner.for.inc:
	// CHECK4-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK4-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK4-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP19]], 1			// CHECK4-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP19]], 1
	// CHECK4-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4			// CHECK4-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]
	// CHECK4: omp.inner.for.end:			// CHECK4: omp.inner.for.end:
	// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK4: omp.loop.exit:			// CHECK4: omp.loop.exit:
	// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]])			// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]])
	// CHECK4-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK4-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK4-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0			// CHECK4-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0
	// CHECK4-NEXT: br i1 [[TMP21]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK4-NEXT: br i1 [[TMP21]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK4: .omp.final.then:			// CHECK4: .omp.final.then:
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	// CHECK9-NEXT: br label [[COND_END]]			// CHECK9-NEXT: br label [[COND_END]]
	// CHECK9: cond.end:			// CHECK9: cond.end:
	// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ]			// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ]
	// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK9-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK9-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK9-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4			// CHECK9-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK9: omp.inner.for.cond:			// CHECK9: omp.inner.for.cond:
	// CHECK9-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK9-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK9-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !5
	// CHECK9-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]]			// CHECK9-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]]
	// CHECK9-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]			// CHECK9-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]
	// CHECK9: omp.inner.for.cond.cleanup:			// CHECK9: omp.inner.for.cond.cleanup:
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_END:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
	// CHECK9: omp.inner.for.body:			// CHECK9: omp.inner.for.body:
	// CHECK9-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP13]], 1			// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP13]], 1
	// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !5
	// CHECK9-NEXT: [[TMP14:%.]] = load i32, i32 [[T_VAR2]], align 4			// CHECK9-NEXT: [[TMP14:%.]] = load i32, i32 [[T_VAR2]], align 4, !llvm.access.group !5
	// CHECK9-NEXT: [[TMP15:%.]] = load i32, i32 [[I]], align 4			// CHECK9-NEXT: [[TMP15:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !5
	// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP15]] to i64			// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP15]] to i64
	// CHECK9-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC3]], i64 0, i64 [[IDXPROM]]			// CHECK9-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC3]], i64 0, i64 [[IDXPROM]]
	// CHECK9-NEXT: store i32 [[TMP14]], i32* [[ARRAYIDX]], align 4			// CHECK9-NEXT: store i32 [[TMP14]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !5
	// CHECK9-NEXT: [[TMP16:%.]] = load %struct.S, %struct.S** [[_TMP6]], align 8			// CHECK9-NEXT: [[TMP16:%.]] = load %struct.S, %struct.S** [[_TMP6]], align 8, !llvm.access.group !5
	// CHECK9-NEXT: [[TMP17:%.]] = load i32, i32 [[I]], align 4			// CHECK9-NEXT: [[TMP17:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !5
	// CHECK9-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP17]] to i64			// CHECK9-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP17]] to i64
	// CHECK9-NEXT: [[ARRAYIDX10:%.]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S] [[S_ARR4]], i64 0, i64 [[IDXPROM9]]			// CHECK9-NEXT: [[ARRAYIDX10:%.]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S] [[S_ARR4]], i64 0, i64 [[IDXPROM9]]
	// CHECK9-NEXT: [[TMP18:%.]] = bitcast %struct.S [[ARRAYIDX10]] to i8*			// CHECK9-NEXT: [[TMP18:%.]] = bitcast %struct.S [[ARRAYIDX10]] to i8*
	// CHECK9-NEXT: [[TMP19:%.]] = bitcast %struct.S [[TMP16]] to i8*			// CHECK9-NEXT: [[TMP19:%.]] = bitcast %struct.S [[TMP16]] to i8*
	// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP18]], i8* align 4 [[TMP19]], i64 4, i1 false)			// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP18]], i8* align 4 [[TMP19]], i64 4, i1 false), !llvm.access.group !5
	// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK9: omp.body.continue:			// CHECK9: omp.body.continue:
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK9: omp.inner.for.inc:			// CHECK9: omp.inner.for.inc:
	// CHECK9-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK9-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP20]], 1			// CHECK9-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP20]], 1
	// CHECK9-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4			// CHECK9-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]
	// CHECK9: omp.inner.for.end:			// CHECK9: omp.inner.for.end:
	// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK9: omp.loop.exit:			// CHECK9: omp.loop.exit:
	// CHECK9-NEXT: [[TMP21:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK9-NEXT: [[TMP21:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK9-NEXT: [[TMP22:%.]] = load i32, i32 [[TMP21]], align 4			// CHECK9-NEXT: [[TMP22:%.]] = load i32, i32 [[TMP21]], align 4
	// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]])			// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]])
	// CHECK9-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK9-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK9-NEXT: [[TMP24:%.*]] = icmp ne i32 [[TMP23]], 0			// CHECK9-NEXT: [[TMP24:%.*]] = icmp ne i32 [[TMP23]], 0
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	// CHECK9-NEXT: br label [[COND_END]]			// CHECK9-NEXT: br label [[COND_END]]
	// CHECK9: cond.end:			// CHECK9: cond.end:
	// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ]			// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ]
	// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK9-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK9-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK9-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4			// CHECK9-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK9: omp.inner.for.cond:			// CHECK9: omp.inner.for.cond:
	// CHECK9-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11
	// CHECK9-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK9-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !11
	// CHECK9-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]			// CHECK9-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]
	// CHECK9-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]			// CHECK9-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]
	// CHECK9: omp.inner.for.cond.cleanup:			// CHECK9: omp.inner.for.cond.cleanup:
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_END:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
	// CHECK9: omp.inner.for.body:			// CHECK9: omp.inner.for.body:
	// CHECK9-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11
	// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1			// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1
	// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11
	// CHECK9-NEXT: [[TMP13:%.]] = load i32, i32 [[T_VAR2]], align 4			// CHECK9-NEXT: [[TMP13:%.]] = load i32, i32 [[T_VAR2]], align 4, !llvm.access.group !11
	// CHECK9-NEXT: [[TMP14:%.]] = load i32, i32 [[I]], align 4			// CHECK9-NEXT: [[TMP14:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !11
	// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP14]] to i64			// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP14]] to i64
	// CHECK9-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC3]], i64 0, i64 [[IDXPROM]]			// CHECK9-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC3]], i64 0, i64 [[IDXPROM]]
	// CHECK9-NEXT: store i32 [[TMP13]], i32* [[ARRAYIDX]], align 4			// CHECK9-NEXT: store i32 [[TMP13]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !11
	// CHECK9-NEXT: [[TMP15:%.]] = load %struct.S.0, %struct.S.0** [[_TMP6]], align 8			// CHECK9-NEXT: [[TMP15:%.]] = load %struct.S.0, %struct.S.0** [[_TMP6]], align 8, !llvm.access.group !11
	// CHECK9-NEXT: [[TMP16:%.]] = load i32, i32 [[I]], align 4			// CHECK9-NEXT: [[TMP16:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !11
	// CHECK9-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP16]] to i64			// CHECK9-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP16]] to i64
	// CHECK9-NEXT: [[ARRAYIDX9:%.]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0] [[S_ARR4]], i64 0, i64 [[IDXPROM8]]			// CHECK9-NEXT: [[ARRAYIDX9:%.]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0] [[S_ARR4]], i64 0, i64 [[IDXPROM8]]
	// CHECK9-NEXT: [[TMP17:%.]] = bitcast %struct.S.0 [[ARRAYIDX9]] to i8*			// CHECK9-NEXT: [[TMP17:%.]] = bitcast %struct.S.0 [[ARRAYIDX9]] to i8*
	// CHECK9-NEXT: [[TMP18:%.]] = bitcast %struct.S.0 [[TMP15]] to i8*			// CHECK9-NEXT: [[TMP18:%.]] = bitcast %struct.S.0 [[TMP15]] to i8*
	// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP17]], i8* align 4 [[TMP18]], i64 4, i1 false)			// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP17]], i8* align 4 [[TMP18]], i64 4, i1 false), !llvm.access.group !11
	// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK9: omp.body.continue:			// CHECK9: omp.body.continue:
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK9: omp.inner.for.inc:			// CHECK9: omp.inner.for.inc:
	// CHECK9-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11
	// CHECK9-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP19]], 1			// CHECK9-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP19]], 1
	// CHECK9-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4			// CHECK9-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]
	// CHECK9: omp.inner.for.end:			// CHECK9: omp.inner.for.end:
	// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK9: omp.loop.exit:			// CHECK9: omp.loop.exit:
	// CHECK9-NEXT: [[TMP20:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK9-NEXT: [[TMP20:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK9-NEXT: [[TMP21:%.]] = load i32, i32 [[TMP20]], align 4			// CHECK9-NEXT: [[TMP21:%.]] = load i32, i32 [[TMP20]], align 4
	// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP21]])			// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP21]])
	// CHECK9-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK9-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK9-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0			// CHECK9-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0
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	// CHECK10-NEXT: br label [[COND_END]]			// CHECK10-NEXT: br label [[COND_END]]
	// CHECK10: cond.end:			// CHECK10: cond.end:
	// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ]			// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ]
	// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK10-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK10-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK10-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4			// CHECK10-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK10: omp.inner.for.cond:			// CHECK10: omp.inner.for.cond:
	// CHECK10-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK10-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK10-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !5
	// CHECK10-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]]			// CHECK10-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]]
	// CHECK10-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]			// CHECK10-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]
	// CHECK10: omp.inner.for.cond.cleanup:			// CHECK10: omp.inner.for.cond.cleanup:
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_END:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
	// CHECK10: omp.inner.for.body:			// CHECK10: omp.inner.for.body:
	// CHECK10-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP13]], 1			// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP13]], 1
	// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !5
	// CHECK10-NEXT: [[TMP14:%.]] = load i32, i32 [[T_VAR2]], align 4			// CHECK10-NEXT: [[TMP14:%.]] = load i32, i32 [[T_VAR2]], align 4, !llvm.access.group !5
	// CHECK10-NEXT: [[TMP15:%.]] = load i32, i32 [[I]], align 4			// CHECK10-NEXT: [[TMP15:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !5
	// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP15]] to i64			// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP15]] to i64
	// CHECK10-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC3]], i64 0, i64 [[IDXPROM]]			// CHECK10-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC3]], i64 0, i64 [[IDXPROM]]
	// CHECK10-NEXT: store i32 [[TMP14]], i32* [[ARRAYIDX]], align 4			// CHECK10-NEXT: store i32 [[TMP14]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !5
	// CHECK10-NEXT: [[TMP16:%.]] = load %struct.S, %struct.S** [[_TMP6]], align 8			// CHECK10-NEXT: [[TMP16:%.]] = load %struct.S, %struct.S** [[_TMP6]], align 8, !llvm.access.group !5
	// CHECK10-NEXT: [[TMP17:%.]] = load i32, i32 [[I]], align 4			// CHECK10-NEXT: [[TMP17:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !5
	// CHECK10-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP17]] to i64			// CHECK10-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP17]] to i64
	// CHECK10-NEXT: [[ARRAYIDX10:%.]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S] [[S_ARR4]], i64 0, i64 [[IDXPROM9]]			// CHECK10-NEXT: [[ARRAYIDX10:%.]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S] [[S_ARR4]], i64 0, i64 [[IDXPROM9]]
	// CHECK10-NEXT: [[TMP18:%.]] = bitcast %struct.S [[ARRAYIDX10]] to i8*			// CHECK10-NEXT: [[TMP18:%.]] = bitcast %struct.S [[ARRAYIDX10]] to i8*
	// CHECK10-NEXT: [[TMP19:%.]] = bitcast %struct.S [[TMP16]] to i8*			// CHECK10-NEXT: [[TMP19:%.]] = bitcast %struct.S [[TMP16]] to i8*
	// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP18]], i8* align 4 [[TMP19]], i64 4, i1 false)			// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP18]], i8* align 4 [[TMP19]], i64 4, i1 false), !llvm.access.group !5
	// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK10: omp.body.continue:			// CHECK10: omp.body.continue:
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK10: omp.inner.for.inc:			// CHECK10: omp.inner.for.inc:
	// CHECK10-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK10-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP20]], 1			// CHECK10-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP20]], 1
	// CHECK10-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4			// CHECK10-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]
	// CHECK10: omp.inner.for.end:			// CHECK10: omp.inner.for.end:
	// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK10: omp.loop.exit:			// CHECK10: omp.loop.exit:
	// CHECK10-NEXT: [[TMP21:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK10-NEXT: [[TMP21:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK10-NEXT: [[TMP22:%.]] = load i32, i32 [[TMP21]], align 4			// CHECK10-NEXT: [[TMP22:%.]] = load i32, i32 [[TMP21]], align 4
	// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]])			// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]])
	// CHECK10-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK10-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK10-NEXT: [[TMP24:%.*]] = icmp ne i32 [[TMP23]], 0			// CHECK10-NEXT: [[TMP24:%.*]] = icmp ne i32 [[TMP23]], 0
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	// CHECK10-NEXT: br label [[COND_END]]			// CHECK10-NEXT: br label [[COND_END]]
	// CHECK10: cond.end:			// CHECK10: cond.end:
	// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ]			// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ]
	// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK10-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK10-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK10-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4			// CHECK10-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK10: omp.inner.for.cond:			// CHECK10: omp.inner.for.cond:
	// CHECK10-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11
	// CHECK10-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK10-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !11
	// CHECK10-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]			// CHECK10-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]
	// CHECK10-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]			// CHECK10-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]
	// CHECK10: omp.inner.for.cond.cleanup:			// CHECK10: omp.inner.for.cond.cleanup:
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_END:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
	// CHECK10: omp.inner.for.body:			// CHECK10: omp.inner.for.body:
	// CHECK10-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11
	// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1			// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1
	// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11
	// CHECK10-NEXT: [[TMP13:%.]] = load i32, i32 [[T_VAR2]], align 4			// CHECK10-NEXT: [[TMP13:%.]] = load i32, i32 [[T_VAR2]], align 4, !llvm.access.group !11
	// CHECK10-NEXT: [[TMP14:%.]] = load i32, i32 [[I]], align 4			// CHECK10-NEXT: [[TMP14:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !11
	// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP14]] to i64			// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP14]] to i64
	// CHECK10-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC3]], i64 0, i64 [[IDXPROM]]			// CHECK10-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC3]], i64 0, i64 [[IDXPROM]]
	// CHECK10-NEXT: store i32 [[TMP13]], i32* [[ARRAYIDX]], align 4			// CHECK10-NEXT: store i32 [[TMP13]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !11
	// CHECK10-NEXT: [[TMP15:%.]] = load %struct.S.0, %struct.S.0** [[_TMP6]], align 8			// CHECK10-NEXT: [[TMP15:%.]] = load %struct.S.0, %struct.S.0** [[_TMP6]], align 8, !llvm.access.group !11
	// CHECK10-NEXT: [[TMP16:%.]] = load i32, i32 [[I]], align 4			// CHECK10-NEXT: [[TMP16:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !11
	// CHECK10-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP16]] to i64			// CHECK10-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP16]] to i64
	// CHECK10-NEXT: [[ARRAYIDX9:%.]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0] [[S_ARR4]], i64 0, i64 [[IDXPROM8]]			// CHECK10-NEXT: [[ARRAYIDX9:%.]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0] [[S_ARR4]], i64 0, i64 [[IDXPROM8]]
	// CHECK10-NEXT: [[TMP17:%.]] = bitcast %struct.S.0 [[ARRAYIDX9]] to i8*			// CHECK10-NEXT: [[TMP17:%.]] = bitcast %struct.S.0 [[ARRAYIDX9]] to i8*
	// CHECK10-NEXT: [[TMP18:%.]] = bitcast %struct.S.0 [[TMP15]] to i8*			// CHECK10-NEXT: [[TMP18:%.]] = bitcast %struct.S.0 [[TMP15]] to i8*
	// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP17]], i8* align 4 [[TMP18]], i64 4, i1 false)			// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP17]], i8* align 4 [[TMP18]], i64 4, i1 false), !llvm.access.group !11
	// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK10: omp.body.continue:			// CHECK10: omp.body.continue:
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK10: omp.inner.for.inc:			// CHECK10: omp.inner.for.inc:
	// CHECK10-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11
	// CHECK10-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP19]], 1			// CHECK10-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP19]], 1
	// CHECK10-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4			// CHECK10-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]
	// CHECK10: omp.inner.for.end:			// CHECK10: omp.inner.for.end:
	// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK10: omp.loop.exit:			// CHECK10: omp.loop.exit:
	// CHECK10-NEXT: [[TMP20:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK10-NEXT: [[TMP20:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK10-NEXT: [[TMP21:%.]] = load i32, i32 [[TMP20]], align 4			// CHECK10-NEXT: [[TMP21:%.]] = load i32, i32 [[TMP20]], align 4
	// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP21]])			// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP21]])
	// CHECK10-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK10-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK10-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0			// CHECK10-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0
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	// CHECK11-NEXT: br label [[COND_END]]			// CHECK11-NEXT: br label [[COND_END]]
	// CHECK11: cond.end:			// CHECK11: cond.end:
	// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ]			// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ]
	// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK11-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK11-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK11-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4			// CHECK11-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK11: omp.inner.for.cond:			// CHECK11: omp.inner.for.cond:
	// CHECK11-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK11-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !6
	// CHECK11-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK11-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !6
	// CHECK11-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]]			// CHECK11-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]]
	// CHECK11-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]			// CHECK11-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]
	// CHECK11: omp.inner.for.cond.cleanup:			// CHECK11: omp.inner.for.cond.cleanup:
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_END:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
	// CHECK11: omp.inner.for.body:			// CHECK11: omp.inner.for.body:
	// CHECK11-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK11-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !6
	// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP13]], 1			// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP13]], 1
	// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !6
	// CHECK11-NEXT: [[TMP14:%.]] = load i32, i32 [[T_VAR2]], align 4			// CHECK11-NEXT: [[TMP14:%.]] = load i32, i32 [[T_VAR2]], align 4, !llvm.access.group !6
	// CHECK11-NEXT: [[TMP15:%.]] = load i32, i32 [[I]], align 4			// CHECK11-NEXT: [[TMP15:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !6
	// CHECK11-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC3]], i32 0, i32 [[TMP15]]			// CHECK11-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC3]], i32 0, i32 [[TMP15]]
	// CHECK11-NEXT: store i32 [[TMP14]], i32* [[ARRAYIDX]], align 4			// CHECK11-NEXT: store i32 [[TMP14]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !6
	// CHECK11-NEXT: [[TMP16:%.]] = load %struct.S, %struct.S** [[_TMP6]], align 4			// CHECK11-NEXT: [[TMP16:%.]] = load %struct.S, %struct.S** [[_TMP6]], align 4, !llvm.access.group !6
	// CHECK11-NEXT: [[TMP17:%.]] = load i32, i32 [[I]], align 4			// CHECK11-NEXT: [[TMP17:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !6
	// CHECK11-NEXT: [[ARRAYIDX9:%.]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S] [[S_ARR4]], i32 0, i32 [[TMP17]]			// CHECK11-NEXT: [[ARRAYIDX9:%.]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S] [[S_ARR4]], i32 0, i32 [[TMP17]]
	// CHECK11-NEXT: [[TMP18:%.]] = bitcast %struct.S [[ARRAYIDX9]] to i8*			// CHECK11-NEXT: [[TMP18:%.]] = bitcast %struct.S [[ARRAYIDX9]] to i8*
	// CHECK11-NEXT: [[TMP19:%.]] = bitcast %struct.S [[TMP16]] to i8*			// CHECK11-NEXT: [[TMP19:%.]] = bitcast %struct.S [[TMP16]] to i8*
	// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP18]], i8* align 4 [[TMP19]], i32 4, i1 false)			// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP18]], i8* align 4 [[TMP19]], i32 4, i1 false), !llvm.access.group !6
	// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK11: omp.body.continue:			// CHECK11: omp.body.continue:
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK11: omp.inner.for.inc:			// CHECK11: omp.inner.for.inc:
	// CHECK11-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK11-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !6
	// CHECK11-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP20]], 1			// CHECK11-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP20]], 1
	// CHECK11-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4			// CHECK11-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]
	// CHECK11: omp.inner.for.end:			// CHECK11: omp.inner.for.end:
	// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK11: omp.loop.exit:			// CHECK11: omp.loop.exit:
	// CHECK11-NEXT: [[TMP21:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4			// CHECK11-NEXT: [[TMP21:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4
	// CHECK11-NEXT: [[TMP22:%.]] = load i32, i32 [[TMP21]], align 4			// CHECK11-NEXT: [[TMP22:%.]] = load i32, i32 [[TMP21]], align 4
	// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]])			// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]])
	// CHECK11-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK11-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK11-NEXT: [[TMP24:%.*]] = icmp ne i32 [[TMP23]], 0			// CHECK11-NEXT: [[TMP24:%.*]] = icmp ne i32 [[TMP23]], 0
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	// CHECK11-NEXT: br label [[COND_END]]			// CHECK11-NEXT: br label [[COND_END]]
	// CHECK11: cond.end:			// CHECK11: cond.end:
	// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ]			// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ]
	// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK11-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK11-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK11-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4			// CHECK11-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK11: omp.inner.for.cond:			// CHECK11: omp.inner.for.cond:
	// CHECK11-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK11-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12
	// CHECK11-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK11-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !12
	// CHECK11-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]			// CHECK11-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]
	// CHECK11-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]			// CHECK11-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]
	// CHECK11: omp.inner.for.cond.cleanup:			// CHECK11: omp.inner.for.cond.cleanup:
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_END:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
	// CHECK11: omp.inner.for.body:			// CHECK11: omp.inner.for.body:
	// CHECK11-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK11-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12
	// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1			// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1
	// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !12
	// CHECK11-NEXT: [[TMP13:%.]] = load i32, i32 [[T_VAR2]], align 4			// CHECK11-NEXT: [[TMP13:%.]] = load i32, i32 [[T_VAR2]], align 4, !llvm.access.group !12
	// CHECK11-NEXT: [[TMP14:%.]] = load i32, i32 [[I]], align 4			// CHECK11-NEXT: [[TMP14:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !12
	// CHECK11-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC3]], i32 0, i32 [[TMP14]]			// CHECK11-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC3]], i32 0, i32 [[TMP14]]
	// CHECK11-NEXT: store i32 [[TMP13]], i32* [[ARRAYIDX]], align 4			// CHECK11-NEXT: store i32 [[TMP13]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !12
	// CHECK11-NEXT: [[TMP15:%.]] = load %struct.S.0, %struct.S.0** [[_TMP6]], align 4			// CHECK11-NEXT: [[TMP15:%.]] = load %struct.S.0, %struct.S.0** [[_TMP6]], align 4, !llvm.access.group !12
	// CHECK11-NEXT: [[TMP16:%.]] = load i32, i32 [[I]], align 4			// CHECK11-NEXT: [[TMP16:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !12
	// CHECK11-NEXT: [[ARRAYIDX8:%.]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0] [[S_ARR4]], i32 0, i32 [[TMP16]]			// CHECK11-NEXT: [[ARRAYIDX8:%.]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0] [[S_ARR4]], i32 0, i32 [[TMP16]]
	// CHECK11-NEXT: [[TMP17:%.]] = bitcast %struct.S.0 [[ARRAYIDX8]] to i8*			// CHECK11-NEXT: [[TMP17:%.]] = bitcast %struct.S.0 [[ARRAYIDX8]] to i8*
	// CHECK11-NEXT: [[TMP18:%.]] = bitcast %struct.S.0 [[TMP15]] to i8*			// CHECK11-NEXT: [[TMP18:%.]] = bitcast %struct.S.0 [[TMP15]] to i8*
	// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP17]], i8* align 4 [[TMP18]], i32 4, i1 false)			// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP17]], i8* align 4 [[TMP18]], i32 4, i1 false), !llvm.access.group !12
	// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK11: omp.body.continue:			// CHECK11: omp.body.continue:
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK11: omp.inner.for.inc:			// CHECK11: omp.inner.for.inc:
	// CHECK11-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK11-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12
	// CHECK11-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP19]], 1			// CHECK11-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP19]], 1
	// CHECK11-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4			// CHECK11-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]
	// CHECK11: omp.inner.for.end:			// CHECK11: omp.inner.for.end:
	// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK11: omp.loop.exit:			// CHECK11: omp.loop.exit:
	// CHECK11-NEXT: [[TMP20:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4			// CHECK11-NEXT: [[TMP20:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4
	// CHECK11-NEXT: [[TMP21:%.]] = load i32, i32 [[TMP20]], align 4			// CHECK11-NEXT: [[TMP21:%.]] = load i32, i32 [[TMP20]], align 4
	// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP21]])			// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP21]])
	// CHECK11-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK11-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK11-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0			// CHECK11-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0
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	// CHECK12-NEXT: br label [[COND_END]]			// CHECK12-NEXT: br label [[COND_END]]
	// CHECK12: cond.end:			// CHECK12: cond.end:
	// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ]			// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ]
	// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK12-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK12-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK12-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4			// CHECK12-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK12: omp.inner.for.cond:			// CHECK12: omp.inner.for.cond:
	// CHECK12-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK12-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !6
	// CHECK12-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK12-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !6
	// CHECK12-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]]			// CHECK12-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]]
	// CHECK12-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]			// CHECK12-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]
	// CHECK12: omp.inner.for.cond.cleanup:			// CHECK12: omp.inner.for.cond.cleanup:
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_END:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
	// CHECK12: omp.inner.for.body:			// CHECK12: omp.inner.for.body:
	// CHECK12-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK12-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !6
	// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP13]], 1			// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP13]], 1
	// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !6
	// CHECK12-NEXT: [[TMP14:%.]] = load i32, i32 [[T_VAR2]], align 4			// CHECK12-NEXT: [[TMP14:%.]] = load i32, i32 [[T_VAR2]], align 4, !llvm.access.group !6
	// CHECK12-NEXT: [[TMP15:%.]] = load i32, i32 [[I]], align 4			// CHECK12-NEXT: [[TMP15:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !6
	// CHECK12-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC3]], i32 0, i32 [[TMP15]]			// CHECK12-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC3]], i32 0, i32 [[TMP15]]
	// CHECK12-NEXT: store i32 [[TMP14]], i32* [[ARRAYIDX]], align 4			// CHECK12-NEXT: store i32 [[TMP14]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !6
	// CHECK12-NEXT: [[TMP16:%.]] = load %struct.S, %struct.S** [[_TMP6]], align 4			// CHECK12-NEXT: [[TMP16:%.]] = load %struct.S, %struct.S** [[_TMP6]], align 4, !llvm.access.group !6
	// CHECK12-NEXT: [[TMP17:%.]] = load i32, i32 [[I]], align 4			// CHECK12-NEXT: [[TMP17:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !6
	// CHECK12-NEXT: [[ARRAYIDX9:%.]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S] [[S_ARR4]], i32 0, i32 [[TMP17]]			// CHECK12-NEXT: [[ARRAYIDX9:%.]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S] [[S_ARR4]], i32 0, i32 [[TMP17]]
	// CHECK12-NEXT: [[TMP18:%.]] = bitcast %struct.S [[ARRAYIDX9]] to i8*			// CHECK12-NEXT: [[TMP18:%.]] = bitcast %struct.S [[ARRAYIDX9]] to i8*
	// CHECK12-NEXT: [[TMP19:%.]] = bitcast %struct.S [[TMP16]] to i8*			// CHECK12-NEXT: [[TMP19:%.]] = bitcast %struct.S [[TMP16]] to i8*
	// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP18]], i8* align 4 [[TMP19]], i32 4, i1 false)			// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP18]], i8* align 4 [[TMP19]], i32 4, i1 false), !llvm.access.group !6
	// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK12: omp.body.continue:			// CHECK12: omp.body.continue:
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK12: omp.inner.for.inc:			// CHECK12: omp.inner.for.inc:
	// CHECK12-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK12-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !6
	// CHECK12-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP20]], 1			// CHECK12-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP20]], 1
	// CHECK12-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4			// CHECK12-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]
	// CHECK12: omp.inner.for.end:			// CHECK12: omp.inner.for.end:
	// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK12: omp.loop.exit:			// CHECK12: omp.loop.exit:
	// CHECK12-NEXT: [[TMP21:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4			// CHECK12-NEXT: [[TMP21:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4
	// CHECK12-NEXT: [[TMP22:%.]] = load i32, i32 [[TMP21]], align 4			// CHECK12-NEXT: [[TMP22:%.]] = load i32, i32 [[TMP21]], align 4
	// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]])			// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]])
	// CHECK12-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK12-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK12-NEXT: [[TMP24:%.*]] = icmp ne i32 [[TMP23]], 0			// CHECK12-NEXT: [[TMP24:%.*]] = icmp ne i32 [[TMP23]], 0
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	// CHECK12-NEXT: br label [[COND_END]]			// CHECK12-NEXT: br label [[COND_END]]
	// CHECK12: cond.end:			// CHECK12: cond.end:
	// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ]			// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ]
	// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK12-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK12-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK12-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4			// CHECK12-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK12: omp.inner.for.cond:			// CHECK12: omp.inner.for.cond:
	// CHECK12-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK12-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12
	// CHECK12-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK12-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !12
	// CHECK12-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]			// CHECK12-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]
	// CHECK12-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]			// CHECK12-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]
	// CHECK12: omp.inner.for.cond.cleanup:			// CHECK12: omp.inner.for.cond.cleanup:
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_END:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
	// CHECK12: omp.inner.for.body:			// CHECK12: omp.inner.for.body:
	// CHECK12-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK12-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12
	// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1			// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1
	// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !12
	// CHECK12-NEXT: [[TMP13:%.]] = load i32, i32 [[T_VAR2]], align 4			// CHECK12-NEXT: [[TMP13:%.]] = load i32, i32 [[T_VAR2]], align 4, !llvm.access.group !12
	// CHECK12-NEXT: [[TMP14:%.]] = load i32, i32 [[I]], align 4			// CHECK12-NEXT: [[TMP14:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !12
	// CHECK12-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC3]], i32 0, i32 [[TMP14]]			// CHECK12-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[VEC3]], i32 0, i32 [[TMP14]]
	// CHECK12-NEXT: store i32 [[TMP13]], i32* [[ARRAYIDX]], align 4			// CHECK12-NEXT: store i32 [[TMP13]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !12
	// CHECK12-NEXT: [[TMP15:%.]] = load %struct.S.0, %struct.S.0** [[_TMP6]], align 4			// CHECK12-NEXT: [[TMP15:%.]] = load %struct.S.0, %struct.S.0** [[_TMP6]], align 4, !llvm.access.group !12
	// CHECK12-NEXT: [[TMP16:%.]] = load i32, i32 [[I]], align 4			// CHECK12-NEXT: [[TMP16:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !12
	// CHECK12-NEXT: [[ARRAYIDX8:%.]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0] [[S_ARR4]], i32 0, i32 [[TMP16]]			// CHECK12-NEXT: [[ARRAYIDX8:%.]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0] [[S_ARR4]], i32 0, i32 [[TMP16]]
	// CHECK12-NEXT: [[TMP17:%.]] = bitcast %struct.S.0 [[ARRAYIDX8]] to i8*			// CHECK12-NEXT: [[TMP17:%.]] = bitcast %struct.S.0 [[ARRAYIDX8]] to i8*
	// CHECK12-NEXT: [[TMP18:%.]] = bitcast %struct.S.0 [[TMP15]] to i8*			// CHECK12-NEXT: [[TMP18:%.]] = bitcast %struct.S.0 [[TMP15]] to i8*
	// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP17]], i8* align 4 [[TMP18]], i32 4, i1 false)			// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP17]], i8* align 4 [[TMP18]], i32 4, i1 false), !llvm.access.group !12
	// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK12: omp.body.continue:			// CHECK12: omp.body.continue:
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK12: omp.inner.for.inc:			// CHECK12: omp.inner.for.inc:
	// CHECK12-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK12-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12
	// CHECK12-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP19]], 1			// CHECK12-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP19]], 1
	// CHECK12-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4			// CHECK12-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]
	// CHECK12: omp.inner.for.end:			// CHECK12: omp.inner.for.end:
	// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK12: omp.loop.exit:			// CHECK12: omp.loop.exit:
	// CHECK12-NEXT: [[TMP20:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4			// CHECK12-NEXT: [[TMP20:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4
	// CHECK12-NEXT: [[TMP21:%.]] = load i32, i32 [[TMP20]], align 4			// CHECK12-NEXT: [[TMP21:%.]] = load i32, i32 [[TMP20]], align 4
	// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP21]])			// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP21]])
	// CHECK12-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK12-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK12-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0			// CHECK12-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0
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clang/test/OpenMP/teams_distribute_simd_reduction_codegen.cpp

	Show First 20 Lines • Show All 164 Lines • ▼ Show 20 Lines
	// CHECK1-NEXT: br label [[COND_END]]			// CHECK1-NEXT: br label [[COND_END]]
	// CHECK1: cond.end:			// CHECK1: cond.end:
	// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]			// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
	// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK1-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK1-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK1-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK1: omp.inner.for.cond:			// CHECK1: omp.inner.for.cond:
	// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !5
	// CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK1: omp.inner.for.body:			// CHECK1: omp.inner.for.body:
	// CHECK1-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1			// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
	// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !5
	// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[I]], align 4			// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !5
	// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[SIVAR1]], align 4			// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[SIVAR1]], align 4, !llvm.access.group !5
	// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]]			// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]]
	// CHECK1-NEXT: store i32 [[ADD3]], i32* [[SIVAR1]], align 4			// CHECK1-NEXT: store i32 [[ADD3]], i32* [[SIVAR1]], align 4, !llvm.access.group !5
	// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK1: omp.body.continue:			// CHECK1: omp.body.continue:
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK1: omp.inner.for.inc:			// CHECK1: omp.inner.for.inc:
	// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1			// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1
	// CHECK1-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]
	// CHECK1: omp.inner.for.end:			// CHECK1: omp.inner.for.end:
	// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK1: omp.loop.exit:			// CHECK1: omp.loop.exit:
	// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])			// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
	// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK1-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0			// CHECK1-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0
	// CHECK1-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK1-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK1: .omp.final.then:			// CHECK1: .omp.final.then:
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	// CHECK1-NEXT: br label [[COND_END]]			// CHECK1-NEXT: br label [[COND_END]]
	// CHECK1: cond.end:			// CHECK1: cond.end:
	// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]			// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
	// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK1-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK1-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK1-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK1: omp.inner.for.cond:			// CHECK1: omp.inner.for.cond:
	// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11
	// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !11
	// CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK1: omp.inner.for.body:			// CHECK1: omp.inner.for.body:
	// CHECK1-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11
	// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1			// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
	// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11
	// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[I]], align 4			// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !11
	// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[T_VAR1]], align 4			// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[T_VAR1]], align 4, !llvm.access.group !11
	// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]]			// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]]
	// CHECK1-NEXT: store i32 [[ADD3]], i32* [[T_VAR1]], align 4			// CHECK1-NEXT: store i32 [[ADD3]], i32* [[T_VAR1]], align 4, !llvm.access.group !11
	// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK1: omp.body.continue:			// CHECK1: omp.body.continue:
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK1: omp.inner.for.inc:			// CHECK1: omp.inner.for.inc:
	// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11
	// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1			// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1
	// CHECK1-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]
	// CHECK1: omp.inner.for.end:			// CHECK1: omp.inner.for.end:
	// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK1: omp.loop.exit:			// CHECK1: omp.loop.exit:
	// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])			// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
	// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK1-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0			// CHECK1-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0
	// CHECK1-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK1-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK1: .omp.final.then:			// CHECK1: .omp.final.then:
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	// CHECK2-NEXT: br label [[COND_END]]			// CHECK2-NEXT: br label [[COND_END]]
	// CHECK2: cond.end:			// CHECK2: cond.end:
	// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]			// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
	// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK2-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK2-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK2-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK2: omp.inner.for.cond:			// CHECK2: omp.inner.for.cond:
	// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !5
	// CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK2: omp.inner.for.body:			// CHECK2: omp.inner.for.body:
	// CHECK2-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1			// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
	// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !5
	// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[I]], align 4			// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !5
	// CHECK2-NEXT: [[TMP10:%.]] = load i32, i32 [[SIVAR1]], align 4			// CHECK2-NEXT: [[TMP10:%.]] = load i32, i32 [[SIVAR1]], align 4, !llvm.access.group !5
	// CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]]			// CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]]
	// CHECK2-NEXT: store i32 [[ADD3]], i32* [[SIVAR1]], align 4			// CHECK2-NEXT: store i32 [[ADD3]], i32* [[SIVAR1]], align 4, !llvm.access.group !5
	// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK2: omp.body.continue:			// CHECK2: omp.body.continue:
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK2: omp.inner.for.inc:			// CHECK2: omp.inner.for.inc:
	// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1			// CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1
	// CHECK2-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]
	// CHECK2: omp.inner.for.end:			// CHECK2: omp.inner.for.end:
	// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK2: omp.loop.exit:			// CHECK2: omp.loop.exit:
	// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])			// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
	// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK2-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0			// CHECK2-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0
	// CHECK2-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK2-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK2: .omp.final.then:			// CHECK2: .omp.final.then:
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	// CHECK2-NEXT: br label [[COND_END]]			// CHECK2-NEXT: br label [[COND_END]]
	// CHECK2: cond.end:			// CHECK2: cond.end:
	// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]			// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
	// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK2-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK2-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK2-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK2: omp.inner.for.cond:			// CHECK2: omp.inner.for.cond:
	// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11
	// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !11
	// CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK2: omp.inner.for.body:			// CHECK2: omp.inner.for.body:
	// CHECK2-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11
	// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1			// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
	// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11
	// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[I]], align 4			// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !11
	// CHECK2-NEXT: [[TMP10:%.]] = load i32, i32 [[T_VAR1]], align 4			// CHECK2-NEXT: [[TMP10:%.]] = load i32, i32 [[T_VAR1]], align 4, !llvm.access.group !11
	// CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]]			// CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]]
	// CHECK2-NEXT: store i32 [[ADD3]], i32* [[T_VAR1]], align 4			// CHECK2-NEXT: store i32 [[ADD3]], i32* [[T_VAR1]], align 4, !llvm.access.group !11
	// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK2: omp.body.continue:			// CHECK2: omp.body.continue:
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK2: omp.inner.for.inc:			// CHECK2: omp.inner.for.inc:
	// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11
	// CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1			// CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1
	// CHECK2-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]
	// CHECK2: omp.inner.for.end:			// CHECK2: omp.inner.for.end:
	// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK2: omp.loop.exit:			// CHECK2: omp.loop.exit:
	// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])			// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
	// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK2-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0			// CHECK2-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0
	// CHECK2-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK2-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK2: .omp.final.then:			// CHECK2: .omp.final.then:
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	// CHECK3-NEXT: br label [[COND_END]]			// CHECK3-NEXT: br label [[COND_END]]
	// CHECK3: cond.end:			// CHECK3: cond.end:
	// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]			// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
	// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK3-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK3-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK3-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK3-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK3: omp.inner.for.cond:			// CHECK3: omp.inner.for.cond:
	// CHECK3-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK3-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !6
	// CHECK3-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK3-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !6
	// CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK3: omp.inner.for.body:			// CHECK3: omp.inner.for.body:
	// CHECK3-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK3-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !6
	// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1			// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
	// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !6
	// CHECK3-NEXT: [[TMP9:%.]] = load i32, i32 [[I]], align 4			// CHECK3-NEXT: [[TMP9:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !6
	// CHECK3-NEXT: [[TMP10:%.]] = load i32, i32 [[SIVAR1]], align 4			// CHECK3-NEXT: [[TMP10:%.]] = load i32, i32 [[SIVAR1]], align 4, !llvm.access.group !6
	// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]]			// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]]
	// CHECK3-NEXT: store i32 [[ADD3]], i32* [[SIVAR1]], align 4			// CHECK3-NEXT: store i32 [[ADD3]], i32* [[SIVAR1]], align 4, !llvm.access.group !6
	// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK3: omp.body.continue:			// CHECK3: omp.body.continue:
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK3: omp.inner.for.inc:			// CHECK3: omp.inner.for.inc:
	// CHECK3-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK3-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !6
	// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1			// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1
	// CHECK3-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4			// CHECK3-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]
	// CHECK3: omp.inner.for.end:			// CHECK3: omp.inner.for.end:
	// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK3: omp.loop.exit:			// CHECK3: omp.loop.exit:
	// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])			// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
	// CHECK3-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK3-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK3-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0			// CHECK3-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0
	// CHECK3-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK3-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK3: .omp.final.then:			// CHECK3: .omp.final.then:
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	// CHECK3-NEXT: br label [[COND_END]]			// CHECK3-NEXT: br label [[COND_END]]
	// CHECK3: cond.end:			// CHECK3: cond.end:
	// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]			// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
	// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK3-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK3-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK3-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK3-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK3: omp.inner.for.cond:			// CHECK3: omp.inner.for.cond:
	// CHECK3-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK3-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12
	// CHECK3-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK3-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !12
	// CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK3: omp.inner.for.body:			// CHECK3: omp.inner.for.body:
	// CHECK3-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK3-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12
	// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1			// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
	// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !12
	// CHECK3-NEXT: [[TMP9:%.]] = load i32, i32 [[I]], align 4			// CHECK3-NEXT: [[TMP9:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !12
	// CHECK3-NEXT: [[TMP10:%.]] = load i32, i32 [[T_VAR1]], align 4			// CHECK3-NEXT: [[TMP10:%.]] = load i32, i32 [[T_VAR1]], align 4, !llvm.access.group !12
	// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]]			// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]]
	// CHECK3-NEXT: store i32 [[ADD3]], i32* [[T_VAR1]], align 4			// CHECK3-NEXT: store i32 [[ADD3]], i32* [[T_VAR1]], align 4, !llvm.access.group !12
	// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK3: omp.body.continue:			// CHECK3: omp.body.continue:
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK3: omp.inner.for.inc:			// CHECK3: omp.inner.for.inc:
	// CHECK3-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK3-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12
	// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1			// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1
	// CHECK3-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4			// CHECK3-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]
	// CHECK3: omp.inner.for.end:			// CHECK3: omp.inner.for.end:
	// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK3: omp.loop.exit:			// CHECK3: omp.loop.exit:
	// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])			// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
	// CHECK3-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK3-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK3-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0			// CHECK3-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0
	// CHECK3-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK3-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK3: .omp.final.then:			// CHECK3: .omp.final.then:
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	// CHECK4-NEXT: br label [[COND_END]]			// CHECK4-NEXT: br label [[COND_END]]
	// CHECK4: cond.end:			// CHECK4: cond.end:
	// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]			// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
	// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK4-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK4-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK4-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK4-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK4: omp.inner.for.cond:			// CHECK4: omp.inner.for.cond:
	// CHECK4-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK4-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !6
	// CHECK4-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK4-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !6
	// CHECK4-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK4-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK4-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK4-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK4: omp.inner.for.body:			// CHECK4: omp.inner.for.body:
	// CHECK4-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK4-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !6
	// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1			// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
	// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !6
	// CHECK4-NEXT: [[TMP9:%.]] = load i32, i32 [[I]], align 4			// CHECK4-NEXT: [[TMP9:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !6
	// CHECK4-NEXT: [[TMP10:%.]] = load i32, i32 [[SIVAR1]], align 4			// CHECK4-NEXT: [[TMP10:%.]] = load i32, i32 [[SIVAR1]], align 4, !llvm.access.group !6
	// CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]]			// CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]]
	// CHECK4-NEXT: store i32 [[ADD3]], i32* [[SIVAR1]], align 4			// CHECK4-NEXT: store i32 [[ADD3]], i32* [[SIVAR1]], align 4, !llvm.access.group !6
	// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK4: omp.body.continue:			// CHECK4: omp.body.continue:
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK4: omp.inner.for.inc:			// CHECK4: omp.inner.for.inc:
	// CHECK4-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK4-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !6
	// CHECK4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1			// CHECK4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1
	// CHECK4-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4			// CHECK4-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]
	// CHECK4: omp.inner.for.end:			// CHECK4: omp.inner.for.end:
	// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK4: omp.loop.exit:			// CHECK4: omp.loop.exit:
	// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])			// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
	// CHECK4-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK4-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK4-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0			// CHECK4-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0
	// CHECK4-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK4-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK4: .omp.final.then:			// CHECK4: .omp.final.then:
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	// CHECK4-NEXT: br label [[COND_END]]			// CHECK4-NEXT: br label [[COND_END]]
	// CHECK4: cond.end:			// CHECK4: cond.end:
	// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]			// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
	// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK4-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK4-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK4-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK4-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK4: omp.inner.for.cond:			// CHECK4: omp.inner.for.cond:
	// CHECK4-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK4-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12
	// CHECK4-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK4-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !12
	// CHECK4-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK4-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK4-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK4-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK4: omp.inner.for.body:			// CHECK4: omp.inner.for.body:
	// CHECK4-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK4-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12
	// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1			// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
	// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !12
	// CHECK4-NEXT: [[TMP9:%.]] = load i32, i32 [[I]], align 4			// CHECK4-NEXT: [[TMP9:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !12
	// CHECK4-NEXT: [[TMP10:%.]] = load i32, i32 [[T_VAR1]], align 4			// CHECK4-NEXT: [[TMP10:%.]] = load i32, i32 [[T_VAR1]], align 4, !llvm.access.group !12
	// CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]]			// CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]]
	// CHECK4-NEXT: store i32 [[ADD3]], i32* [[T_VAR1]], align 4			// CHECK4-NEXT: store i32 [[ADD3]], i32* [[T_VAR1]], align 4, !llvm.access.group !12
	// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK4: omp.body.continue:			// CHECK4: omp.body.continue:
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK4: omp.inner.for.inc:			// CHECK4: omp.inner.for.inc:
	// CHECK4-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK4-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12
	// CHECK4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1			// CHECK4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1
	// CHECK4-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4			// CHECK4-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]
	// CHECK4: omp.inner.for.end:			// CHECK4: omp.inner.for.end:
	// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK4: omp.loop.exit:			// CHECK4: omp.loop.exit:
	// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])			// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
	// CHECK4-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK4-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK4-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0			// CHECK4-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0
	// CHECK4-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK4-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK4: .omp.final.then:			// CHECK4: .omp.final.then:
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	// CHECK9-NEXT: br label [[COND_END]]			// CHECK9-NEXT: br label [[COND_END]]
	// CHECK9: cond.end:			// CHECK9: cond.end:
	// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]			// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
	// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK9-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK9-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK9: omp.inner.for.cond:			// CHECK9: omp.inner.for.cond:
	// CHECK9-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !4
	// CHECK9-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK9-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !4
	// CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK9: omp.inner.for.body:			// CHECK9: omp.inner.for.body:
	// CHECK9-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !4
	// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1			// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
	// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !4
	// CHECK9-NEXT: [[TMP9:%.]] = load i32, i32 [[I]], align 4			// CHECK9-NEXT: [[TMP9:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !4
	// CHECK9-NEXT: [[TMP10:%.]] = load i32, i32 [[SIVAR1]], align 4			// CHECK9-NEXT: [[TMP10:%.]] = load i32, i32 [[SIVAR1]], align 4, !llvm.access.group !4
	// CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]]			// CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]]
	// CHECK9-NEXT: store i32 [[ADD3]], i32* [[SIVAR1]], align 4			// CHECK9-NEXT: store i32 [[ADD3]], i32* [[SIVAR1]], align 4, !llvm.access.group !4
	// CHECK9-NEXT: [[TMP11:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 0			// CHECK9-NEXT: [[TMP11:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 0
	// CHECK9-NEXT: store i32* [[SIVAR1]], i32** [[TMP11]], align 8			// CHECK9-NEXT: store i32* [[SIVAR1]], i32** [[TMP11]], align 8, !llvm.access.group !4
	// CHECK9-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(8) [[REF_TMP]])			// CHECK9-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(8) [[REF_TMP]]), !llvm.access.group !4
	// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK9: omp.body.continue:			// CHECK9: omp.body.continue:
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK9: omp.inner.for.inc:			// CHECK9: omp.inner.for.inc:
	// CHECK9-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !4
	// CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1			// CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1
	// CHECK9-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4			// CHECK9-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]
	// CHECK9: omp.inner.for.end:			// CHECK9: omp.inner.for.end:
	// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK9: omp.loop.exit:			// CHECK9: omp.loop.exit:
	// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])			// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
	// CHECK9-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK9-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK9-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0			// CHECK9-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
	// CHECK9-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK9-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK9: .omp.final.then:			// CHECK9: .omp.final.then:
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	// CHECK10-NEXT: br label [[COND_END]]			// CHECK10-NEXT: br label [[COND_END]]
	// CHECK10: cond.end:			// CHECK10: cond.end:
	// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]			// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
	// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK10-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK10-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK10-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK10-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK10: omp.inner.for.cond:			// CHECK10: omp.inner.for.cond:
	// CHECK10-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !4
	// CHECK10-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK10-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !4
	// CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK10: omp.inner.for.body:			// CHECK10: omp.inner.for.body:
	// CHECK10-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !4
	// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1			// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
	// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !4
	// CHECK10-NEXT: [[TMP9:%.]] = load i32, i32 [[I]], align 4			// CHECK10-NEXT: [[TMP9:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !4
	// CHECK10-NEXT: [[TMP10:%.]] = load i32, i32 [[SIVAR1]], align 4			// CHECK10-NEXT: [[TMP10:%.]] = load i32, i32 [[SIVAR1]], align 4, !llvm.access.group !4
	// CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]]			// CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]]
	// CHECK10-NEXT: store i32 [[ADD3]], i32* [[SIVAR1]], align 4			// CHECK10-NEXT: store i32 [[ADD3]], i32* [[SIVAR1]], align 4, !llvm.access.group !4
	// CHECK10-NEXT: [[TMP11:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 0			// CHECK10-NEXT: [[TMP11:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP]], i32 0, i32 0
	// CHECK10-NEXT: store i32* [[SIVAR1]], i32** [[TMP11]], align 8			// CHECK10-NEXT: store i32* [[SIVAR1]], i32** [[TMP11]], align 8, !llvm.access.group !4
	// CHECK10-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(8) [[REF_TMP]])			// CHECK10-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(8) [[REF_TMP]]), !llvm.access.group !4
	// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK10: omp.body.continue:			// CHECK10: omp.body.continue:
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK10: omp.inner.for.inc:			// CHECK10: omp.inner.for.inc:
	// CHECK10-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !4
	// CHECK10-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1			// CHECK10-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1
	// CHECK10-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4			// CHECK10-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]
	// CHECK10: omp.inner.for.end:			// CHECK10: omp.inner.for.end:
	// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK10: omp.loop.exit:			// CHECK10: omp.loop.exit:
	// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])			// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
	// CHECK10-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK10-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK10-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0			// CHECK10-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
	// CHECK10-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK10-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK10: .omp.final.then:			// CHECK10: .omp.final.then:
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clang/test/OpenMP/teams_private_codegen.cpp

	Show First 20 Lines • Show All 2,816 Lines • ▼ Show 20 Lines
	//			//
	//			//
	// CHECK12-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg			// CHECK12-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
	// CHECK12-SAME: () #[[ATTR6:[0-9]+]] {			// CHECK12-SAME: () #[[ATTR6:[0-9]+]] {
	// CHECK12-NEXT: entry:			// CHECK12-NEXT: entry:
	// CHECK12-NEXT: call void @__tgt_register_requires(i64 1)			// CHECK12-NEXT: call void @__tgt_register_requires(i64 1)
	// CHECK12-NEXT: ret void			// CHECK12-NEXT: ret void
	//			//
	//
	No newline at end of file

clang/test/OpenMP/threadprivate_codegen.cpp

This file is larger than 256 KB, so syntax highlighting is disabled by default.

	Show First 20 Lines • Show All 3,097 Lines • ▼ Show 20 Lines
	// SIMD2-LABEL: define {{[^@]+}}@__cxx_global_array_dtor			// SIMD2-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
	// SIMD2-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG166:![0-9]+]] {			// SIMD2-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG166:![0-9]+]] {
	// SIMD2-NEXT: entry:			// SIMD2-NEXT: entry:
	// SIMD2-NEXT: [[DOTADDR:%.]] = alloca i8, align 8			// SIMD2-NEXT: [[DOTADDR:%.]] = alloca i8, align 8
	// SIMD2-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8			// SIMD2-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8
	// SIMD2-NEXT: call void @llvm.dbg.declare(metadata i8** [[DOTADDR]], metadata [[META170:![0-9]+]], metadata !DIExpression()), !dbg [[DBG171:![0-9]+]]			// SIMD2-NEXT: call void @llvm.dbg.declare(metadata i8** [[DOTADDR]], metadata [[META170:![0-9]+]], metadata !DIExpression()), !dbg [[DBG171:![0-9]+]]
	// SIMD2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]], !dbg [[DBG171]]			// SIMD2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]], !dbg [[DBG171]]
	// SIMD2: arraydestroy.body:			// SIMD2: arraydestroy.body:
	// SIMD2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.]] = phi %struct.S1 [ getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 1, i64 0, i64 0), [[ENTRY:%.]] ], [ [[ARRAYDESTROY_ELEMENT:%.]], [[ARRAYDESTROY_BODY]] ], !dbg [[DBG171]]
	// SIMD2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1:%.]], %struct.S1 [[ARRAYDESTROY_ELEMENTPAST]], i64 -1, !dbg [[DBG171]]
	// SIMD2-NEXT: call void @_ZN2S1D1Ev(%struct.S1* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]], !dbg [[DBG171]]
	// SIMD2-NEXT: [[ARRAYDESTROY_DONE:%.]] = icmp eq %struct.S1 [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i32 0, i32 0, i32 0), !dbg [[DBG171]]
	// SIMD2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]], !dbg [[DBG171]]
	// SIMD2: arraydestroy.done1:			// SIMD2: arraydestroy.done1:
	// SIMD2-NEXT: ret void, !dbg [[DBG171]]			// SIMD2-NEXT: ret void, !dbg [[DBG171]]
	//			//
	//			//
	// SIMD2-LABEL: define {{[^@]+}}@main			// SIMD2-LABEL: define {{[^@]+}}@main
	// SIMD2-SAME: () #[[ATTR5:[0-9]+]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) !dbg [[DBG52:![0-9]+]] {			// SIMD2-SAME: () #[[ATTR5:[0-9]+]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) !dbg [[DBG52:![0-9]+]] {
	// SIMD2-NEXT: entry:			// SIMD2-NEXT: entry:
	// SIMD2-NEXT: [[RETVAL:%.*]] = alloca i32, align 4			// SIMD2-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
	▲ Show 20 Lines • Show All 3,052 Lines • ▼ Show 20 Lines
	// SIMD4-LABEL: define {{[^@]+}}@__cxx_global_array_dtor			// SIMD4-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
	// SIMD4-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG166:![0-9]+]] {			// SIMD4-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG166:![0-9]+]] {
	// SIMD4-NEXT: entry:			// SIMD4-NEXT: entry:
	// SIMD4-NEXT: [[DOTADDR:%.]] = alloca i8, align 8			// SIMD4-NEXT: [[DOTADDR:%.]] = alloca i8, align 8
	// SIMD4-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8			// SIMD4-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8
	// SIMD4-NEXT: call void @llvm.dbg.declare(metadata i8** [[DOTADDR]], metadata [[META170:![0-9]+]], metadata !DIExpression()), !dbg [[DBG171:![0-9]+]]			// SIMD4-NEXT: call void @llvm.dbg.declare(metadata i8** [[DOTADDR]], metadata [[META170:![0-9]+]], metadata !DIExpression()), !dbg [[DBG171:![0-9]+]]
	// SIMD4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]], !dbg [[DBG171]]			// SIMD4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]], !dbg [[DBG171]]
	// SIMD4: arraydestroy.body:			// SIMD4: arraydestroy.body:
	// SIMD4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.]] = phi %struct.S1 [ getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 1, i64 0, i64 0), [[ENTRY:%.]] ], [ [[ARRAYDESTROY_ELEMENT:%.]], [[ARRAYDESTROY_BODY]] ], !dbg [[DBG171]]
	// SIMD4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1:%.]], %struct.S1 [[ARRAYDESTROY_ELEMENTPAST]], i64 -1, !dbg [[DBG171]]
	// SIMD4-NEXT: call void @_ZN2S1D1Ev(%struct.S1* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]], !dbg [[DBG171]]
	// SIMD4-NEXT: [[ARRAYDESTROY_DONE:%.]] = icmp eq %struct.S1 [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i32 0, i32 0, i32 0), !dbg [[DBG171]]
	// SIMD4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]], !dbg [[DBG171]]
	// SIMD4: arraydestroy.done1:			// SIMD4: arraydestroy.done1:
	// SIMD4-NEXT: ret void, !dbg [[DBG171]]			// SIMD4-NEXT: ret void, !dbg [[DBG171]]
	//			//
	//			//
	// SIMD4-LABEL: define {{[^@]+}}@main			// SIMD4-LABEL: define {{[^@]+}}@main
	// SIMD4-SAME: () #[[ATTR5:[0-9]+]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) !dbg [[DBG52:![0-9]+]] {			// SIMD4-SAME: () #[[ATTR5:[0-9]+]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) !dbg [[DBG52:![0-9]+]] {
	// SIMD4-NEXT: entry:			// SIMD4-NEXT: entry:
	// SIMD4-NEXT: [[RETVAL:%.*]] = alloca i32, align 4			// SIMD4-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
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clang/test/OpenMP/tile_codegen.cpp

	Show First 20 Lines • Show All 152 Lines • ▼ Show 20 Lines
	// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32** [[I]], align 8			// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32** [[I]], align 8
	// CHECK1-NEXT: [[TMP8:%.]] = load i32, i32 [[TMP7]], align 4			// CHECK1-NEXT: [[TMP8:%.]] = load i32, i32 [[TMP7]], align 4
	// CHECK1-NEXT: call void (...) @body(i32 [[TMP8]])			// CHECK1-NEXT: call void (...) @body(i32 [[TMP8]])
	// CHECK1-NEXT: br label [[FOR_INC:%.*]]			// CHECK1-NEXT: br label [[FOR_INC:%.*]]
	// CHECK1: for.inc:			// CHECK1: for.inc:
	// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTTILE_0_IV_I]], align 4			// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTTILE_0_IV_I]], align 4
	// CHECK1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP9]], 1			// CHECK1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP9]], 1
	// CHECK1-NEXT: store i32 [[INC]], i32* [[DOTTILE_0_IV_I]], align 4			// CHECK1-NEXT: store i32 [[INC]], i32* [[DOTTILE_0_IV_I]], align 4
	// CHECK1-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP2:![0-9]+]]			// CHECK1-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP3:![0-9]+]]
	// CHECK1: for.end:			// CHECK1: for.end:
	// CHECK1-NEXT: br label [[FOR_INC9:%.*]]			// CHECK1-NEXT: br label [[FOR_INC9:%.*]]
	// CHECK1: for.inc9:			// CHECK1: for.inc9:
	// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTFLOOR_0_IV_I]], align 4			// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTFLOOR_0_IV_I]], align 4
	// CHECK1-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP10]], 5			// CHECK1-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP10]], 5
	// CHECK1-NEXT: store i32 [[ADD10]], i32* [[DOTFLOOR_0_IV_I]], align 4			// CHECK1-NEXT: store i32 [[ADD10]], i32* [[DOTFLOOR_0_IV_I]], align 4
	// CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]			// CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]
	// CHECK1: for.end11:			// CHECK1: for.end11:
	// CHECK1-NEXT: ret void			// CHECK1-NEXT: ret void
	//			//
	//			//
	// CHECK1-LABEL: define {{[^@]+}}@foo1			// CHECK1-LABEL: define {{[^@]+}}@foo1
	// CHECK1-SAME: (i32 [[START:%.]], i32 [[END:%.]], i32 [[STEP:%.*]]) #[[ATTR0]] {			// CHECK1-SAME: (i32 [[START:%.]], i32 [[END:%.]], i32 [[STEP:%.*]]) #[[ATTR0]] {
	// CHECK1-NEXT: entry:			// CHECK1-NEXT: entry:
	// CHECK1-NEXT: [[START_ADDR:%.*]] = alloca i32, align 4			// CHECK1-NEXT: [[START_ADDR:%.*]] = alloca i32, align 4
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	// CHECK1-NEXT: store i32 [[ADD15]], i32* [[I]], align 4			// CHECK1-NEXT: store i32 [[ADD15]], i32* [[I]], align 4
	// CHECK1-NEXT: [[TMP18:%.]] = load i32, i32 [[I]], align 4			// CHECK1-NEXT: [[TMP18:%.]] = load i32, i32 [[I]], align 4
	// CHECK1-NEXT: call void (...) @body(i32 [[TMP18]])			// CHECK1-NEXT: call void (...) @body(i32 [[TMP18]])
	// CHECK1-NEXT: br label [[FOR_INC:%.*]]			// CHECK1-NEXT: br label [[FOR_INC:%.*]]
	// CHECK1: for.inc:			// CHECK1: for.inc:
	// CHECK1-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTTILE_0_IV_I]], align 4			// CHECK1-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTTILE_0_IV_I]], align 4
	// CHECK1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP19]], 1			// CHECK1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP19]], 1
	// CHECK1-NEXT: store i32 [[INC]], i32* [[DOTTILE_0_IV_I]], align 4			// CHECK1-NEXT: store i32 [[INC]], i32* [[DOTTILE_0_IV_I]], align 4
	// CHECK1-NEXT: br label [[FOR_COND7]], !llvm.loop [[LOOP5:![0-9]+]]			// CHECK1-NEXT: br label [[FOR_COND7]], !llvm.loop [[LOOP6:![0-9]+]]
	// CHECK1: for.end:			// CHECK1: for.end:
	// CHECK1-NEXT: br label [[FOR_INC16:%.*]]			// CHECK1-NEXT: br label [[FOR_INC16:%.*]]
	// CHECK1: for.inc16:			// CHECK1: for.inc16:
	// CHECK1-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTFLOOR_0_IV_I]], align 4			// CHECK1-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTFLOOR_0_IV_I]], align 4
	// CHECK1-NEXT: [[ADD17:%.*]] = add nsw i32 [[TMP20]], 5			// CHECK1-NEXT: [[ADD17:%.*]] = add nsw i32 [[TMP20]], 5
	// CHECK1-NEXT: store i32 [[ADD17]], i32* [[DOTFLOOR_0_IV_I]], align 4			// CHECK1-NEXT: store i32 [[ADD17]], i32* [[DOTFLOOR_0_IV_I]], align 4
	// CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]			// CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]
	// CHECK1: for.end18:			// CHECK1: for.end18:
	// CHECK1-NEXT: ret void			// CHECK1-NEXT: ret void
	//			//
	//			//
	// CHECK1-LABEL: define {{[^@]+}}@foo2			// CHECK1-LABEL: define {{[^@]+}}@foo2
	// CHECK1-SAME: (i32 [[START:%.]], i32 [[END:%.]], i32 [[STEP:%.*]]) #[[ATTR0]] {			// CHECK1-SAME: (i32 [[START:%.]], i32 [[END:%.]], i32 [[STEP:%.*]]) #[[ATTR0]] {
	// CHECK1-NEXT: entry:			// CHECK1-NEXT: entry:
	// CHECK1-NEXT: [[START_ADDR:%.*]] = alloca i32, align 4			// CHECK1-NEXT: [[START_ADDR:%.*]] = alloca i32, align 4
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	// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32 [[I]], align 4			// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32 [[I]], align 4
	// CHECK1-NEXT: [[TMP13:%.]] = load i32, i32 [[J]], align 4			// CHECK1-NEXT: [[TMP13:%.]] = load i32, i32 [[J]], align 4
	// CHECK1-NEXT: call void (...) @body(i32 [[TMP12]], i32 [[TMP13]])			// CHECK1-NEXT: call void (...) @body(i32 [[TMP12]], i32 [[TMP13]])
	// CHECK1-NEXT: br label [[FOR_INC:%.*]]			// CHECK1-NEXT: br label [[FOR_INC:%.*]]
	// CHECK1: for.inc:			// CHECK1: for.inc:
	// CHECK1-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTTILE_1_IV_J]], align 4			// CHECK1-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTTILE_1_IV_J]], align 4
	// CHECK1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP14]], 1			// CHECK1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP14]], 1
	// CHECK1-NEXT: store i32 [[INC]], i32* [[DOTTILE_1_IV_J]], align 4			// CHECK1-NEXT: store i32 [[INC]], i32* [[DOTTILE_1_IV_J]], align 4
	// CHECK1-NEXT: br label [[FOR_COND10]], !llvm.loop [[LOOP7:![0-9]+]]			// CHECK1-NEXT: br label [[FOR_COND10]], !llvm.loop [[LOOP8:![0-9]+]]
	// CHECK1: for.end:			// CHECK1: for.end:
	// CHECK1-NEXT: br label [[FOR_INC22:%.*]]			// CHECK1-NEXT: br label [[FOR_INC22:%.*]]
	// CHECK1: for.inc22:			// CHECK1: for.inc22:
	// CHECK1-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTTILE_0_IV_I]], align 4			// CHECK1-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTTILE_0_IV_I]], align 4
	// CHECK1-NEXT: [[INC23:%.*]] = add nsw i32 [[TMP15]], 1			// CHECK1-NEXT: [[INC23:%.*]] = add nsw i32 [[TMP15]], 1
	// CHECK1-NEXT: store i32 [[INC23]], i32* [[DOTTILE_0_IV_I]], align 4			// CHECK1-NEXT: store i32 [[INC23]], i32* [[DOTTILE_0_IV_I]], align 4
	// CHECK1-NEXT: br label [[FOR_COND4]], !llvm.loop [[LOOP8:![0-9]+]]			// CHECK1-NEXT: br label [[FOR_COND4]], !llvm.loop [[LOOP9:![0-9]+]]
	// CHECK1: for.end24:			// CHECK1: for.end24:
	// CHECK1-NEXT: br label [[FOR_INC25:%.*]]			// CHECK1-NEXT: br label [[FOR_INC25:%.*]]
	// CHECK1: for.inc25:			// CHECK1: for.inc25:
	// CHECK1-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTFLOOR_1_IV_J]], align 4			// CHECK1-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTFLOOR_1_IV_J]], align 4
	// CHECK1-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP16]], 5			// CHECK1-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP16]], 5
	// CHECK1-NEXT: store i32 [[ADD26]], i32* [[DOTFLOOR_1_IV_J]], align 4			// CHECK1-NEXT: store i32 [[ADD26]], i32* [[DOTFLOOR_1_IV_J]], align 4
	// CHECK1-NEXT: br label [[FOR_COND1]], !llvm.loop [[LOOP9:![0-9]+]]			// CHECK1-NEXT: br label [[FOR_COND1]], !llvm.loop [[LOOP10:![0-9]+]]
	// CHECK1: for.end27:			// CHECK1: for.end27:
	// CHECK1-NEXT: br label [[FOR_INC28:%.*]]			// CHECK1-NEXT: br label [[FOR_INC28:%.*]]
	// CHECK1: for.inc28:			// CHECK1: for.inc28:
	// CHECK1-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTFLOOR_0_IV_I]], align 4			// CHECK1-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTFLOOR_0_IV_I]], align 4
	// CHECK1-NEXT: [[ADD29:%.*]] = add nsw i32 [[TMP17]], 5			// CHECK1-NEXT: [[ADD29:%.*]] = add nsw i32 [[TMP17]], 5
	// CHECK1-NEXT: store i32 [[ADD29]], i32* [[DOTFLOOR_0_IV_I]], align 4			// CHECK1-NEXT: store i32 [[ADD29]], i32* [[DOTFLOOR_0_IV_I]], align 4
	// CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]			// CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]
	// CHECK1: for.end30:			// CHECK1: for.end30:
	// CHECK1-NEXT: ret void			// CHECK1-NEXT: ret void
	//			//
	//			//
	// CHECK1-LABEL: define {{[^@]+}}@foo3			// CHECK1-LABEL: define {{[^@]+}}@foo3
	// CHECK1-SAME: () #[[ATTR0]] {			// CHECK1-SAME: () #[[ATTR0]] {
	// CHECK1-NEXT: entry:			// CHECK1-NEXT: entry:
	// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4			// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
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	// CHECK1-NEXT: [[TMP18:%.]] = load i32, i32 [[I]], align 4			// CHECK1-NEXT: [[TMP18:%.]] = load i32, i32 [[I]], align 4
	// CHECK1-NEXT: [[TMP19:%.]] = load i32, i32 [[J]], align 4			// CHECK1-NEXT: [[TMP19:%.]] = load i32, i32 [[J]], align 4
	// CHECK1-NEXT: call void (...) @body(i32 [[TMP18]], i32 [[TMP19]])			// CHECK1-NEXT: call void (...) @body(i32 [[TMP18]], i32 [[TMP19]])
	// CHECK1-NEXT: br label [[FOR_INC:%.*]]			// CHECK1-NEXT: br label [[FOR_INC:%.*]]
	// CHECK1: for.inc:			// CHECK1: for.inc:
	// CHECK1-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTTILE_1_IV_J]], align 4			// CHECK1-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTTILE_1_IV_J]], align 4
	// CHECK1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP20]], 1			// CHECK1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP20]], 1
	// CHECK1-NEXT: store i32 [[INC]], i32* [[DOTTILE_1_IV_J]], align 4			// CHECK1-NEXT: store i32 [[INC]], i32* [[DOTTILE_1_IV_J]], align 4
	// CHECK1-NEXT: br label [[FOR_COND15]], !llvm.loop [[LOOP11:![0-9]+]]			// CHECK1-NEXT: br label [[FOR_COND15]], !llvm.loop [[LOOP12:![0-9]+]]
	// CHECK1: for.end:			// CHECK1: for.end:
	// CHECK1-NEXT: br label [[FOR_INC27:%.*]]			// CHECK1-NEXT: br label [[FOR_INC27:%.*]]
	// CHECK1: for.inc27:			// CHECK1: for.inc27:
	// CHECK1-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTTILE_0_IV_I]], align 4			// CHECK1-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTTILE_0_IV_I]], align 4
	// CHECK1-NEXT: [[INC28:%.*]] = add nsw i32 [[TMP21]], 1			// CHECK1-NEXT: [[INC28:%.*]] = add nsw i32 [[TMP21]], 1
	// CHECK1-NEXT: store i32 [[INC28]], i32* [[DOTTILE_0_IV_I]], align 4			// CHECK1-NEXT: store i32 [[INC28]], i32* [[DOTTILE_0_IV_I]], align 4
	// CHECK1-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP12:![0-9]+]]			// CHECK1-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP13:![0-9]+]]
	// CHECK1: for.end29:			// CHECK1: for.end29:
	// CHECK1-NEXT: br label [[FOR_INC30:%.*]]			// CHECK1-NEXT: br label [[FOR_INC30:%.*]]
	// CHECK1: for.inc30:			// CHECK1: for.inc30:
	// CHECK1-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTFLOOR_1_IV_J]], align 4			// CHECK1-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTFLOOR_1_IV_J]], align 4
	// CHECK1-NEXT: [[ADD31:%.*]] = add nsw i32 [[TMP22]], 5			// CHECK1-NEXT: [[ADD31:%.*]] = add nsw i32 [[TMP22]], 5
	// CHECK1-NEXT: store i32 [[ADD31]], i32* [[DOTFLOOR_1_IV_J]], align 4			// CHECK1-NEXT: store i32 [[ADD31]], i32* [[DOTFLOOR_1_IV_J]], align 4
	// CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]			// CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]]
	// CHECK1: for.end32:			// CHECK1: for.end32:
	// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK1: omp.body.continue:			// CHECK1: omp.body.continue:
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK1: omp.inner.for.inc:			// CHECK1: omp.inner.for.inc:
	// CHECK1-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK1-NEXT: [[ADD33:%.*]] = add nsw i32 [[TMP23]], 1			// CHECK1-NEXT: [[ADD33:%.*]] = add nsw i32 [[TMP23]], 1
	// CHECK1-NEXT: store i32 [[ADD33]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[ADD33]], i32* [[DOTOMP_IV]], align 4
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	// CHECK1-NEXT: [[TMP20:%.]] = load i32, i32 [[I]], align 4			// CHECK1-NEXT: [[TMP20:%.]] = load i32, i32 [[I]], align 4
	// CHECK1-NEXT: [[TMP21:%.]] = load i32, i32 [[J]], align 4			// CHECK1-NEXT: [[TMP21:%.]] = load i32, i32 [[J]], align 4
	// CHECK1-NEXT: call void (...) @body(i32 [[TMP20]], i32 [[TMP21]])			// CHECK1-NEXT: call void (...) @body(i32 [[TMP20]], i32 [[TMP21]])
	// CHECK1-NEXT: br label [[FOR_INC:%.*]]			// CHECK1-NEXT: br label [[FOR_INC:%.*]]
	// CHECK1: for.inc:			// CHECK1: for.inc:
	// CHECK1-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTTILE_1_IV_J]], align 4			// CHECK1-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTTILE_1_IV_J]], align 4
	// CHECK1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP22]], 1			// CHECK1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP22]], 1
	// CHECK1-NEXT: store i32 [[INC]], i32* [[DOTTILE_1_IV_J]], align 4			// CHECK1-NEXT: store i32 [[INC]], i32* [[DOTTILE_1_IV_J]], align 4
	// CHECK1-NEXT: br label [[FOR_COND20]], !llvm.loop [[LOOP14:![0-9]+]]			// CHECK1-NEXT: br label [[FOR_COND20]], !llvm.loop [[LOOP15:![0-9]+]]
	// CHECK1: for.end:			// CHECK1: for.end:
	// CHECK1-NEXT: br label [[FOR_INC32:%.*]]			// CHECK1-NEXT: br label [[FOR_INC32:%.*]]
	// CHECK1: for.inc32:			// CHECK1: for.inc32:
	// CHECK1-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTTILE_0_IV_I]], align 4			// CHECK1-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTTILE_0_IV_I]], align 4
	// CHECK1-NEXT: [[INC33:%.*]] = add nsw i32 [[TMP23]], 1			// CHECK1-NEXT: [[INC33:%.*]] = add nsw i32 [[TMP23]], 1
	// CHECK1-NEXT: store i32 [[INC33]], i32* [[DOTTILE_0_IV_I]], align 4			// CHECK1-NEXT: store i32 [[INC33]], i32* [[DOTTILE_0_IV_I]], align 4
	// CHECK1-NEXT: br label [[FOR_COND8]], !llvm.loop [[LOOP15:![0-9]+]]			// CHECK1-NEXT: br label [[FOR_COND8]], !llvm.loop [[LOOP16:![0-9]+]]
	// CHECK1: for.end34:			// CHECK1: for.end34:
	// CHECK1-NEXT: br label [[FOR_INC35:%.*]]			// CHECK1-NEXT: br label [[FOR_INC35:%.*]]
	// CHECK1: for.inc35:			// CHECK1: for.inc35:
	// CHECK1-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTFLOOR_1_IV_J]], align 4			// CHECK1-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTFLOOR_1_IV_J]], align 4
	// CHECK1-NEXT: [[ADD36:%.*]] = add nsw i32 [[TMP24]], 5			// CHECK1-NEXT: [[ADD36:%.*]] = add nsw i32 [[TMP24]], 5
	// CHECK1-NEXT: store i32 [[ADD36]], i32* [[DOTFLOOR_1_IV_J]], align 4			// CHECK1-NEXT: store i32 [[ADD36]], i32* [[DOTFLOOR_1_IV_J]], align 4
	// CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]]			// CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]]
	// CHECK1: for.end37:			// CHECK1: for.end37:
	// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK1: omp.body.continue:			// CHECK1: omp.body.continue:
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK1: omp.inner.for.inc:			// CHECK1: omp.inner.for.inc:
	// CHECK1-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK1-NEXT: [[ADD38:%.*]] = add nsw i32 [[TMP25]], 1			// CHECK1-NEXT: [[ADD38:%.*]] = add nsw i32 [[TMP25]], 1
	// CHECK1-NEXT: store i32 [[ADD38]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[ADD38]], i32* [[DOTOMP_IV]], align 4
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	// CHECK1-NEXT: store i32 [[ADD11]], i32* [[I]], align 4			// CHECK1-NEXT: store i32 [[ADD11]], i32* [[I]], align 4
	// CHECK1-NEXT: [[TMP13:%.]] = load i32, i32 [[I]], align 4			// CHECK1-NEXT: [[TMP13:%.]] = load i32, i32 [[I]], align 4
	// CHECK1-NEXT: call void (...) @body(i32 [[TMP13]])			// CHECK1-NEXT: call void (...) @body(i32 [[TMP13]])
	// CHECK1-NEXT: br label [[FOR_INC:%.*]]			// CHECK1-NEXT: br label [[FOR_INC:%.*]]
	// CHECK1: for.inc:			// CHECK1: for.inc:
	// CHECK1-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTTILE_0_IV_I]], align 4			// CHECK1-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTTILE_0_IV_I]], align 4
	// CHECK1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP14]], 1			// CHECK1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP14]], 1
	// CHECK1-NEXT: store i32 [[INC]], i32* [[DOTTILE_0_IV_I]], align 4			// CHECK1-NEXT: store i32 [[INC]], i32* [[DOTTILE_0_IV_I]], align 4
	// CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]]			// CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]]
	// CHECK1: for.end:			// CHECK1: for.end:
	// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK1: omp.body.continue:			// CHECK1: omp.body.continue:
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK1: omp.inner.for.inc:			// CHECK1: omp.inner.for.inc:
	// CHECK1-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK1-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP15]], 1			// CHECK1-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP15]], 1
	// CHECK1-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4
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	// CHECK1-NEXT: store i32 [[ADD14]], i32* [[I]], align 4			// CHECK1-NEXT: store i32 [[ADD14]], i32* [[I]], align 4
	// CHECK1-NEXT: [[TMP15:%.]] = load i32, i32 [[I]], align 4			// CHECK1-NEXT: [[TMP15:%.]] = load i32, i32 [[I]], align 4
	// CHECK1-NEXT: call void (...) @body(i32 [[TMP15]])			// CHECK1-NEXT: call void (...) @body(i32 [[TMP15]])
	// CHECK1-NEXT: br label [[FOR_INC:%.*]]			// CHECK1-NEXT: br label [[FOR_INC:%.*]]
	// CHECK1: for.inc:			// CHECK1: for.inc:
	// CHECK1-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTTILE_0_IV_I]], align 4			// CHECK1-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTTILE_0_IV_I]], align 4
	// CHECK1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP16]], 1			// CHECK1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP16]], 1
	// CHECK1-NEXT: store i32 [[INC]], i32* [[DOTTILE_0_IV_I]], align 4			// CHECK1-NEXT: store i32 [[INC]], i32* [[DOTTILE_0_IV_I]], align 4
	// CHECK1-NEXT: br label [[FOR_COND6]], !llvm.loop [[LOOP20:![0-9]+]]			// CHECK1-NEXT: br label [[FOR_COND6]], !llvm.loop [[LOOP21:![0-9]+]]
	// CHECK1: for.end:			// CHECK1: for.end:
	// CHECK1-NEXT: br label [[FOR_INC15:%.*]]			// CHECK1-NEXT: br label [[FOR_INC15:%.*]]
	// CHECK1: for.inc15:			// CHECK1: for.inc15:
	// CHECK1-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTFLOOR_0_IV_I]], align 4			// CHECK1-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTFLOOR_0_IV_I]], align 4
	// CHECK1-NEXT: [[ADD16:%.*]] = add nsw i32 [[TMP17]], 5			// CHECK1-NEXT: [[ADD16:%.*]] = add nsw i32 [[TMP17]], 5
	// CHECK1-NEXT: store i32 [[ADD16]], i32* [[DOTFLOOR_0_IV_I]], align 4			// CHECK1-NEXT: store i32 [[ADD16]], i32* [[DOTFLOOR_0_IV_I]], align 4
	// CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]]			// CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]]
	// CHECK1: for.end17:			// CHECK1: for.end17:
	// CHECK1-NEXT: ret void			// CHECK1-NEXT: ret void
	//			//
	//			//
	// CHECK1-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_tile_codegen.cpp			// CHECK1-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_tile_codegen.cpp
	// CHECK1-SAME: () #[[ATTR1]] section ".text.startup" {			// CHECK1-SAME: () #[[ATTR1]] section ".text.startup" {
	// CHECK1-NEXT: entry:			// CHECK1-NEXT: entry:
	// CHECK1-NEXT: call void @__cxx_global_var_init()			// CHECK1-NEXT: call void @__cxx_global_var_init()
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	// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32** [[I]], align 8			// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32** [[I]], align 8
	// CHECK2-NEXT: [[TMP8:%.]] = load i32, i32 [[TMP7]], align 4			// CHECK2-NEXT: [[TMP8:%.]] = load i32, i32 [[TMP7]], align 4
	// CHECK2-NEXT: call void (...) @body(i32 [[TMP8]])			// CHECK2-NEXT: call void (...) @body(i32 [[TMP8]])
	// CHECK2-NEXT: br label [[FOR_INC:%.*]]			// CHECK2-NEXT: br label [[FOR_INC:%.*]]
	// CHECK2: for.inc:			// CHECK2: for.inc:
	// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTTILE_0_IV_I]], align 4			// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTTILE_0_IV_I]], align 4
	// CHECK2-NEXT: [[INC:%.*]] = add nsw i32 [[TMP9]], 1			// CHECK2-NEXT: [[INC:%.*]] = add nsw i32 [[TMP9]], 1
	// CHECK2-NEXT: store i32 [[INC]], i32* [[DOTTILE_0_IV_I]], align 4			// CHECK2-NEXT: store i32 [[INC]], i32* [[DOTTILE_0_IV_I]], align 4
	// CHECK2-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP2:![0-9]+]]			// CHECK2-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP3:![0-9]+]]
	// CHECK2: for.end:			// CHECK2: for.end:
	// CHECK2-NEXT: br label [[FOR_INC9:%.*]]			// CHECK2-NEXT: br label [[FOR_INC9:%.*]]
	// CHECK2: for.inc9:			// CHECK2: for.inc9:
	// CHECK2-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTFLOOR_0_IV_I]], align 4			// CHECK2-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTFLOOR_0_IV_I]], align 4
	// CHECK2-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP10]], 5			// CHECK2-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP10]], 5
	// CHECK2-NEXT: store i32 [[ADD10]], i32* [[DOTFLOOR_0_IV_I]], align 4			// CHECK2-NEXT: store i32 [[ADD10]], i32* [[DOTFLOOR_0_IV_I]], align 4
	// CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]			// CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]
	// CHECK2: for.end11:			// CHECK2: for.end11:
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@body			// CHECK2-LABEL: define {{[^@]+}}@body
	// CHECK2-SAME: (...) #[[ATTR2:[0-9]+]] {			// CHECK2-SAME: (...) #[[ATTR2:[0-9]+]] {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
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	// CHECK2-NEXT: store i32 [[ADD15]], i32* [[I]], align 4			// CHECK2-NEXT: store i32 [[ADD15]], i32* [[I]], align 4
	// CHECK2-NEXT: [[TMP18:%.]] = load i32, i32 [[I]], align 4			// CHECK2-NEXT: [[TMP18:%.]] = load i32, i32 [[I]], align 4
	// CHECK2-NEXT: call void (...) @body(i32 [[TMP18]])			// CHECK2-NEXT: call void (...) @body(i32 [[TMP18]])
	// CHECK2-NEXT: br label [[FOR_INC:%.*]]			// CHECK2-NEXT: br label [[FOR_INC:%.*]]
	// CHECK2: for.inc:			// CHECK2: for.inc:
	// CHECK2-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTTILE_0_IV_I]], align 4			// CHECK2-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTTILE_0_IV_I]], align 4
	// CHECK2-NEXT: [[INC:%.*]] = add nsw i32 [[TMP19]], 1			// CHECK2-NEXT: [[INC:%.*]] = add nsw i32 [[TMP19]], 1
	// CHECK2-NEXT: store i32 [[INC]], i32* [[DOTTILE_0_IV_I]], align 4			// CHECK2-NEXT: store i32 [[INC]], i32* [[DOTTILE_0_IV_I]], align 4
	// CHECK2-NEXT: br label [[FOR_COND7]], !llvm.loop [[LOOP5:![0-9]+]]			// CHECK2-NEXT: br label [[FOR_COND7]], !llvm.loop [[LOOP6:![0-9]+]]
	// CHECK2: for.end:			// CHECK2: for.end:
	// CHECK2-NEXT: br label [[FOR_INC16:%.*]]			// CHECK2-NEXT: br label [[FOR_INC16:%.*]]
	// CHECK2: for.inc16:			// CHECK2: for.inc16:
	// CHECK2-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTFLOOR_0_IV_I]], align 4			// CHECK2-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTFLOOR_0_IV_I]], align 4
	// CHECK2-NEXT: [[ADD17:%.*]] = add nsw i32 [[TMP20]], 5			// CHECK2-NEXT: [[ADD17:%.*]] = add nsw i32 [[TMP20]], 5
	// CHECK2-NEXT: store i32 [[ADD17]], i32* [[DOTFLOOR_0_IV_I]], align 4			// CHECK2-NEXT: store i32 [[ADD17]], i32* [[DOTFLOOR_0_IV_I]], align 4
	// CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]			// CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]
	// CHECK2: for.end18:			// CHECK2: for.end18:
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@foo2			// CHECK2-LABEL: define {{[^@]+}}@foo2
	// CHECK2-SAME: (i32 [[START:%.]], i32 [[END:%.]], i32 [[STEP:%.*]]) #[[ATTR2]] {			// CHECK2-SAME: (i32 [[START:%.]], i32 [[END:%.]], i32 [[STEP:%.*]]) #[[ATTR2]] {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	// CHECK2-NEXT: [[START_ADDR:%.*]] = alloca i32, align 4			// CHECK2-NEXT: [[START_ADDR:%.*]] = alloca i32, align 4
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	// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32 [[I]], align 4			// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32 [[I]], align 4
	// CHECK2-NEXT: [[TMP13:%.]] = load i32, i32 [[J]], align 4			// CHECK2-NEXT: [[TMP13:%.]] = load i32, i32 [[J]], align 4
	// CHECK2-NEXT: call void (...) @body(i32 [[TMP12]], i32 [[TMP13]])			// CHECK2-NEXT: call void (...) @body(i32 [[TMP12]], i32 [[TMP13]])
	// CHECK2-NEXT: br label [[FOR_INC:%.*]]			// CHECK2-NEXT: br label [[FOR_INC:%.*]]
	// CHECK2: for.inc:			// CHECK2: for.inc:
	// CHECK2-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTTILE_1_IV_J]], align 4			// CHECK2-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTTILE_1_IV_J]], align 4
	// CHECK2-NEXT: [[INC:%.*]] = add nsw i32 [[TMP14]], 1			// CHECK2-NEXT: [[INC:%.*]] = add nsw i32 [[TMP14]], 1
	// CHECK2-NEXT: store i32 [[INC]], i32* [[DOTTILE_1_IV_J]], align 4			// CHECK2-NEXT: store i32 [[INC]], i32* [[DOTTILE_1_IV_J]], align 4
	// CHECK2-NEXT: br label [[FOR_COND10]], !llvm.loop [[LOOP7:![0-9]+]]			// CHECK2-NEXT: br label [[FOR_COND10]], !llvm.loop [[LOOP8:![0-9]+]]
	// CHECK2: for.end:			// CHECK2: for.end:
	// CHECK2-NEXT: br label [[FOR_INC22:%.*]]			// CHECK2-NEXT: br label [[FOR_INC22:%.*]]
	// CHECK2: for.inc22:			// CHECK2: for.inc22:
	// CHECK2-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTTILE_0_IV_I]], align 4			// CHECK2-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTTILE_0_IV_I]], align 4
	// CHECK2-NEXT: [[INC23:%.*]] = add nsw i32 [[TMP15]], 1			// CHECK2-NEXT: [[INC23:%.*]] = add nsw i32 [[TMP15]], 1
	// CHECK2-NEXT: store i32 [[INC23]], i32* [[DOTTILE_0_IV_I]], align 4			// CHECK2-NEXT: store i32 [[INC23]], i32* [[DOTTILE_0_IV_I]], align 4
	// CHECK2-NEXT: br label [[FOR_COND4]], !llvm.loop [[LOOP8:![0-9]+]]			// CHECK2-NEXT: br label [[FOR_COND4]], !llvm.loop [[LOOP9:![0-9]+]]
	// CHECK2: for.end24:			// CHECK2: for.end24:
	// CHECK2-NEXT: br label [[FOR_INC25:%.*]]			// CHECK2-NEXT: br label [[FOR_INC25:%.*]]
	// CHECK2: for.inc25:			// CHECK2: for.inc25:
	// CHECK2-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTFLOOR_1_IV_J]], align 4			// CHECK2-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTFLOOR_1_IV_J]], align 4
	// CHECK2-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP16]], 5			// CHECK2-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP16]], 5
	// CHECK2-NEXT: store i32 [[ADD26]], i32* [[DOTFLOOR_1_IV_J]], align 4			// CHECK2-NEXT: store i32 [[ADD26]], i32* [[DOTFLOOR_1_IV_J]], align 4
	// CHECK2-NEXT: br label [[FOR_COND1]], !llvm.loop [[LOOP9:![0-9]+]]			// CHECK2-NEXT: br label [[FOR_COND1]], !llvm.loop [[LOOP10:![0-9]+]]
	// CHECK2: for.end27:			// CHECK2: for.end27:
	// CHECK2-NEXT: br label [[FOR_INC28:%.*]]			// CHECK2-NEXT: br label [[FOR_INC28:%.*]]
	// CHECK2: for.inc28:			// CHECK2: for.inc28:
	// CHECK2-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTFLOOR_0_IV_I]], align 4			// CHECK2-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTFLOOR_0_IV_I]], align 4
	// CHECK2-NEXT: [[ADD29:%.*]] = add nsw i32 [[TMP17]], 5			// CHECK2-NEXT: [[ADD29:%.*]] = add nsw i32 [[TMP17]], 5
	// CHECK2-NEXT: store i32 [[ADD29]], i32* [[DOTFLOOR_0_IV_I]], align 4			// CHECK2-NEXT: store i32 [[ADD29]], i32* [[DOTFLOOR_0_IV_I]], align 4
	// CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]			// CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]
	// CHECK2: for.end30:			// CHECK2: for.end30:
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@foo3			// CHECK2-LABEL: define {{[^@]+}}@foo3
	// CHECK2-SAME: () #[[ATTR2]] {			// CHECK2-SAME: () #[[ATTR2]] {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	// CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4			// CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
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	// CHECK2-NEXT: [[TMP18:%.]] = load i32, i32 [[I]], align 4			// CHECK2-NEXT: [[TMP18:%.]] = load i32, i32 [[I]], align 4
	// CHECK2-NEXT: [[TMP19:%.]] = load i32, i32 [[J]], align 4			// CHECK2-NEXT: [[TMP19:%.]] = load i32, i32 [[J]], align 4
	// CHECK2-NEXT: call void (...) @body(i32 [[TMP18]], i32 [[TMP19]])			// CHECK2-NEXT: call void (...) @body(i32 [[TMP18]], i32 [[TMP19]])
	// CHECK2-NEXT: br label [[FOR_INC:%.*]]			// CHECK2-NEXT: br label [[FOR_INC:%.*]]
	// CHECK2: for.inc:			// CHECK2: for.inc:
	// CHECK2-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTTILE_1_IV_J]], align 4			// CHECK2-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTTILE_1_IV_J]], align 4
	// CHECK2-NEXT: [[INC:%.*]] = add nsw i32 [[TMP20]], 1			// CHECK2-NEXT: [[INC:%.*]] = add nsw i32 [[TMP20]], 1
	// CHECK2-NEXT: store i32 [[INC]], i32* [[DOTTILE_1_IV_J]], align 4			// CHECK2-NEXT: store i32 [[INC]], i32* [[DOTTILE_1_IV_J]], align 4
	// CHECK2-NEXT: br label [[FOR_COND15]], !llvm.loop [[LOOP11:![0-9]+]]			// CHECK2-NEXT: br label [[FOR_COND15]], !llvm.loop [[LOOP12:![0-9]+]]
	// CHECK2: for.end:			// CHECK2: for.end:
	// CHECK2-NEXT: br label [[FOR_INC27:%.*]]			// CHECK2-NEXT: br label [[FOR_INC27:%.*]]
	// CHECK2: for.inc27:			// CHECK2: for.inc27:
	// CHECK2-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTTILE_0_IV_I]], align 4			// CHECK2-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTTILE_0_IV_I]], align 4
	// CHECK2-NEXT: [[INC28:%.*]] = add nsw i32 [[TMP21]], 1			// CHECK2-NEXT: [[INC28:%.*]] = add nsw i32 [[TMP21]], 1
	// CHECK2-NEXT: store i32 [[INC28]], i32* [[DOTTILE_0_IV_I]], align 4			// CHECK2-NEXT: store i32 [[INC28]], i32* [[DOTTILE_0_IV_I]], align 4
	// CHECK2-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP12:![0-9]+]]			// CHECK2-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP13:![0-9]+]]
	// CHECK2: for.end29:			// CHECK2: for.end29:
	// CHECK2-NEXT: br label [[FOR_INC30:%.*]]			// CHECK2-NEXT: br label [[FOR_INC30:%.*]]
	// CHECK2: for.inc30:			// CHECK2: for.inc30:
	// CHECK2-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTFLOOR_1_IV_J]], align 4			// CHECK2-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTFLOOR_1_IV_J]], align 4
	// CHECK2-NEXT: [[ADD31:%.*]] = add nsw i32 [[TMP22]], 5			// CHECK2-NEXT: [[ADD31:%.*]] = add nsw i32 [[TMP22]], 5
	// CHECK2-NEXT: store i32 [[ADD31]], i32* [[DOTFLOOR_1_IV_J]], align 4			// CHECK2-NEXT: store i32 [[ADD31]], i32* [[DOTFLOOR_1_IV_J]], align 4
	// CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]			// CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]]
	// CHECK2: for.end32:			// CHECK2: for.end32:
	// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK2: omp.body.continue:			// CHECK2: omp.body.continue:
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK2: omp.inner.for.inc:			// CHECK2: omp.inner.for.inc:
	// CHECK2-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK2-NEXT: [[ADD33:%.*]] = add nsw i32 [[TMP23]], 1			// CHECK2-NEXT: [[ADD33:%.*]] = add nsw i32 [[TMP23]], 1
	// CHECK2-NEXT: store i32 [[ADD33]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[ADD33]], i32* [[DOTOMP_IV]], align 4
	▲ Show 20 Lines • Show All 122 Lines • ▼ Show 20 Lines
	// CHECK2-NEXT: [[TMP20:%.]] = load i32, i32 [[I]], align 4			// CHECK2-NEXT: [[TMP20:%.]] = load i32, i32 [[I]], align 4
	// CHECK2-NEXT: [[TMP21:%.]] = load i32, i32 [[J]], align 4			// CHECK2-NEXT: [[TMP21:%.]] = load i32, i32 [[J]], align 4
	// CHECK2-NEXT: call void (...) @body(i32 [[TMP20]], i32 [[TMP21]])			// CHECK2-NEXT: call void (...) @body(i32 [[TMP20]], i32 [[TMP21]])
	// CHECK2-NEXT: br label [[FOR_INC:%.*]]			// CHECK2-NEXT: br label [[FOR_INC:%.*]]
	// CHECK2: for.inc:			// CHECK2: for.inc:
	// CHECK2-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTTILE_1_IV_J]], align 4			// CHECK2-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTTILE_1_IV_J]], align 4
	// CHECK2-NEXT: [[INC:%.*]] = add nsw i32 [[TMP22]], 1			// CHECK2-NEXT: [[INC:%.*]] = add nsw i32 [[TMP22]], 1
	// CHECK2-NEXT: store i32 [[INC]], i32* [[DOTTILE_1_IV_J]], align 4			// CHECK2-NEXT: store i32 [[INC]], i32* [[DOTTILE_1_IV_J]], align 4
	// CHECK2-NEXT: br label [[FOR_COND20]], !llvm.loop [[LOOP14:![0-9]+]]			// CHECK2-NEXT: br label [[FOR_COND20]], !llvm.loop [[LOOP15:![0-9]+]]
	// CHECK2: for.end:			// CHECK2: for.end:
	// CHECK2-NEXT: br label [[FOR_INC32:%.*]]			// CHECK2-NEXT: br label [[FOR_INC32:%.*]]
	// CHECK2: for.inc32:			// CHECK2: for.inc32:
	// CHECK2-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTTILE_0_IV_I]], align 4			// CHECK2-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTTILE_0_IV_I]], align 4
	// CHECK2-NEXT: [[INC33:%.*]] = add nsw i32 [[TMP23]], 1			// CHECK2-NEXT: [[INC33:%.*]] = add nsw i32 [[TMP23]], 1
	// CHECK2-NEXT: store i32 [[INC33]], i32* [[DOTTILE_0_IV_I]], align 4			// CHECK2-NEXT: store i32 [[INC33]], i32* [[DOTTILE_0_IV_I]], align 4
	// CHECK2-NEXT: br label [[FOR_COND8]], !llvm.loop [[LOOP15:![0-9]+]]			// CHECK2-NEXT: br label [[FOR_COND8]], !llvm.loop [[LOOP16:![0-9]+]]
	// CHECK2: for.end34:			// CHECK2: for.end34:
	// CHECK2-NEXT: br label [[FOR_INC35:%.*]]			// CHECK2-NEXT: br label [[FOR_INC35:%.*]]
	// CHECK2: for.inc35:			// CHECK2: for.inc35:
	// CHECK2-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTFLOOR_1_IV_J]], align 4			// CHECK2-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTFLOOR_1_IV_J]], align 4
	// CHECK2-NEXT: [[ADD36:%.*]] = add nsw i32 [[TMP24]], 5			// CHECK2-NEXT: [[ADD36:%.*]] = add nsw i32 [[TMP24]], 5
	// CHECK2-NEXT: store i32 [[ADD36]], i32* [[DOTFLOOR_1_IV_J]], align 4			// CHECK2-NEXT: store i32 [[ADD36]], i32* [[DOTFLOOR_1_IV_J]], align 4
	// CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]]			// CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]]
	// CHECK2: for.end37:			// CHECK2: for.end37:
	// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK2: omp.body.continue:			// CHECK2: omp.body.continue:
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK2: omp.inner.for.inc:			// CHECK2: omp.inner.for.inc:
	// CHECK2-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK2-NEXT: [[ADD38:%.*]] = add nsw i32 [[TMP25]], 1			// CHECK2-NEXT: [[ADD38:%.*]] = add nsw i32 [[TMP25]], 1
	// CHECK2-NEXT: store i32 [[ADD38]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[ADD38]], i32* [[DOTOMP_IV]], align 4
	▲ Show 20 Lines • Show All 296 Lines • ▼ Show 20 Lines
	// CHECK2-NEXT: store i32 [[ADD11]], i32* [[I]], align 4			// CHECK2-NEXT: store i32 [[ADD11]], i32* [[I]], align 4
	// CHECK2-NEXT: [[TMP13:%.]] = load i32, i32 [[I]], align 4			// CHECK2-NEXT: [[TMP13:%.]] = load i32, i32 [[I]], align 4
	// CHECK2-NEXT: call void (...) @body(i32 [[TMP13]])			// CHECK2-NEXT: call void (...) @body(i32 [[TMP13]])
	// CHECK2-NEXT: br label [[FOR_INC:%.*]]			// CHECK2-NEXT: br label [[FOR_INC:%.*]]
	// CHECK2: for.inc:			// CHECK2: for.inc:
	// CHECK2-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTTILE_0_IV_I]], align 4			// CHECK2-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTTILE_0_IV_I]], align 4
	// CHECK2-NEXT: [[INC:%.*]] = add nsw i32 [[TMP14]], 1			// CHECK2-NEXT: [[INC:%.*]] = add nsw i32 [[TMP14]], 1
	// CHECK2-NEXT: store i32 [[INC]], i32* [[DOTTILE_0_IV_I]], align 4			// CHECK2-NEXT: store i32 [[INC]], i32* [[DOTTILE_0_IV_I]], align 4
	// CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]]			// CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]]
	// CHECK2: for.end:			// CHECK2: for.end:
	// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK2: omp.body.continue:			// CHECK2: omp.body.continue:
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK2: omp.inner.for.inc:			// CHECK2: omp.inner.for.inc:
	// CHECK2-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK2-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP15]], 1			// CHECK2-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP15]], 1
	// CHECK2-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4
	▲ Show 20 Lines • Show All 79 Lines • ▼ Show 20 Lines
	// CHECK2-NEXT: store i32 [[ADD14]], i32* [[I]], align 4			// CHECK2-NEXT: store i32 [[ADD14]], i32* [[I]], align 4
	// CHECK2-NEXT: [[TMP15:%.]] = load i32, i32 [[I]], align 4			// CHECK2-NEXT: [[TMP15:%.]] = load i32, i32 [[I]], align 4
	// CHECK2-NEXT: call void (...) @body(i32 [[TMP15]])			// CHECK2-NEXT: call void (...) @body(i32 [[TMP15]])
	// CHECK2-NEXT: br label [[FOR_INC:%.*]]			// CHECK2-NEXT: br label [[FOR_INC:%.*]]
	// CHECK2: for.inc:			// CHECK2: for.inc:
	// CHECK2-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTTILE_0_IV_I]], align 4			// CHECK2-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTTILE_0_IV_I]], align 4
	// CHECK2-NEXT: [[INC:%.*]] = add nsw i32 [[TMP16]], 1			// CHECK2-NEXT: [[INC:%.*]] = add nsw i32 [[TMP16]], 1
	// CHECK2-NEXT: store i32 [[INC]], i32* [[DOTTILE_0_IV_I]], align 4			// CHECK2-NEXT: store i32 [[INC]], i32* [[DOTTILE_0_IV_I]], align 4
	// CHECK2-NEXT: br label [[FOR_COND6]], !llvm.loop [[LOOP20:![0-9]+]]			// CHECK2-NEXT: br label [[FOR_COND6]], !llvm.loop [[LOOP21:![0-9]+]]
	// CHECK2: for.end:			// CHECK2: for.end:
	// CHECK2-NEXT: br label [[FOR_INC15:%.*]]			// CHECK2-NEXT: br label [[FOR_INC15:%.*]]
	// CHECK2: for.inc15:			// CHECK2: for.inc15:
	// CHECK2-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTFLOOR_0_IV_I]], align 4			// CHECK2-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTFLOOR_0_IV_I]], align 4
	// CHECK2-NEXT: [[ADD16:%.*]] = add nsw i32 [[TMP17]], 5			// CHECK2-NEXT: [[ADD16:%.*]] = add nsw i32 [[TMP17]], 5
	// CHECK2-NEXT: store i32 [[ADD16]], i32* [[DOTFLOOR_0_IV_I]], align 4			// CHECK2-NEXT: store i32 [[ADD16]], i32* [[DOTFLOOR_0_IV_I]], align 4
	// CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]]			// CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]]
	// CHECK2: for.end17:			// CHECK2: for.end17:
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_tile_codegen.cpp			// CHECK2-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_tile_codegen.cpp
	// CHECK2-SAME: () #[[ATTR0]] section ".text.startup" {			// CHECK2-SAME: () #[[ATTR0]] section ".text.startup" {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	// CHECK2-NEXT: call void @__cxx_global_var_init()			// CHECK2-NEXT: call void @__cxx_global_var_init()
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	//			//

This is an archive of the discontinued LLVM Phabricator instance.

[OpenMP][3/3] Introduce the KernelEnvironment into Clang testsClosedPublic

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Event Timeline

Revision Contents

Diff 398489

clang/test/OpenMP/amdgcn_target_codegen.cpp

clang/test/OpenMP/declare_target_codegen_globalization.cpp

clang/test/OpenMP/distribute_firstprivate_codegen.cpp

clang/test/OpenMP/distribute_lastprivate_codegen.cpp

clang/test/OpenMP/distribute_parallel_for_lastprivate_codegen.cpp

clang/test/OpenMP/distribute_parallel_for_num_threads_codegen.cpp

clang/test/OpenMP/distribute_parallel_for_private_codegen.cpp

clang/test/OpenMP/distribute_parallel_for_proc_bind_codegen.cpp

clang/test/OpenMP/distribute_parallel_for_simd_firstprivate_codegen.cpp

clang/test/OpenMP/distribute_parallel_for_simd_lastprivate_codegen.cpp

clang/test/OpenMP/distribute_parallel_for_simd_num_threads_codegen.cpp

clang/test/OpenMP/distribute_parallel_for_simd_private_codegen.cpp

clang/test/OpenMP/distribute_parallel_for_simd_proc_bind_codegen.cpp

clang/test/OpenMP/distribute_private_codegen.cpp

clang/test/OpenMP/distribute_simd_firstprivate_codegen.cpp

clang/test/OpenMP/distribute_simd_lastprivate_codegen.cpp

clang/test/OpenMP/distribute_simd_private_codegen.cpp

clang/test/OpenMP/distribute_simd_reduction_codegen.cpp

clang/test/OpenMP/for_lastprivate_codegen.cpp

clang/test/OpenMP/for_private_codegen.cpp

clang/test/OpenMP/nvptx_SPMD_codegen.cpp

clang/test/OpenMP/nvptx_data_sharing.cpp

clang/test/OpenMP/nvptx_distribute_parallel_generic_mode_codegen.cpp

clang/test/OpenMP/nvptx_force_full_runtime_SPMD_codegen.cpp

clang/test/OpenMP/nvptx_lambda_capturing.cpp

clang/test/OpenMP/nvptx_multi_target_parallel_codegen.cpp

clang/test/OpenMP/nvptx_nested_parallel_codegen.cpp

clang/test/OpenMP/nvptx_parallel_codegen.cpp

clang/test/OpenMP/nvptx_parallel_for_codegen.cpp

clang/test/OpenMP/nvptx_target_codegen.cpp

clang/test/OpenMP/nvptx_target_parallel_codegen.cpp

clang/test/OpenMP/nvptx_target_parallel_num_threads_codegen.cpp

clang/test/OpenMP/nvptx_target_parallel_reduction_codegen.cpp

clang/test/OpenMP/nvptx_target_parallel_reduction_codegen_tbaa_PR46146.cpp

clang/test/OpenMP/nvptx_target_printf_codegen.c

clang/test/OpenMP/nvptx_target_simd_codegen.cpp

clang/test/OpenMP/nvptx_target_teams_codegen.cpp

clang/test/OpenMP/nvptx_target_teams_distribute_codegen.cpp

clang/test/OpenMP/nvptx_target_teams_distribute_parallel_for_codegen.cpp

clang/test/OpenMP/nvptx_target_teams_distribute_parallel_for_generic_mode_codegen.cpp

clang/test/OpenMP/nvptx_target_teams_distribute_parallel_for_simd_codegen.cpp

clang/test/OpenMP/nvptx_target_teams_distribute_simd_codegen.cpp

clang/test/OpenMP/nvptx_teams_codegen.cpp

clang/test/OpenMP/openmp_win_codegen.cpp

clang/test/OpenMP/parallel_codegen.cpp

clang/test/OpenMP/parallel_for_simd_aligned_codegen.cpp

clang/test/OpenMP/parallel_private_codegen.cpp

clang/test/OpenMP/parallel_reduction_codegen.cpp

clang/test/OpenMP/parallel_sections_codegen.cpp

clang/test/OpenMP/sections_lastprivate_codegen.cpp

clang/test/OpenMP/sections_private_codegen.cpp

clang/test/OpenMP/sections_reduction_codegen.cpp

clang/test/OpenMP/single_private_codegen.cpp

clang/test/OpenMP/target_data_map_codegen_hold.cpp

clang/test/OpenMP/target_globals_codegen.cpp

clang/test/OpenMP/target_map_codegen_hold.cpp

clang/test/OpenMP/target_parallel_debug_codegen.cpp

clang/test/OpenMP/target_parallel_for_debug_codegen.cpp

clang/test/OpenMP/target_teams_distribute_parallel_for_proc_bind_codegen.cpp

clang/test/OpenMP/target_teams_distribute_parallel_for_reduction_codegen.cpp

clang/test/OpenMP/target_teams_distribute_parallel_for_simd_codegen.cpp

clang/test/OpenMP/target_teams_distribute_parallel_for_simd_collapse_codegen.cpp

clang/test/OpenMP/target_teams_distribute_parallel_for_simd_dist_schedule_codegen.cpp

clang/test/OpenMP/target_teams_distribute_parallel_for_simd_firstprivate_codegen.cpp

clang/test/OpenMP/target_teams_distribute_parallel_for_simd_if_codegen.cpp

clang/test/OpenMP/target_teams_distribute_parallel_for_simd_proc_bind_codegen.cpp

clang/test/OpenMP/target_teams_distribute_parallel_for_simd_reduction_codegen.cpp

clang/test/OpenMP/target_teams_distribute_reduction_codegen.cpp

clang/test/OpenMP/taskgroup_codegen.cpp

clang/test/OpenMP/teams_distribute_collapse_codegen.cpp

clang/test/OpenMP/teams_distribute_lastprivate_codegen.cpp

clang/test/OpenMP/teams_distribute_parallel_for_collapse_codegen.cpp

[OpenMP][3/3] Introduce the KernelEnvironment into Clang tests
ClosedPublic