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Differential D116655

[AArch64] Rename CPY to DUP. NFC
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Authored by dmgreen on Jan 5 2022, 5:14 AM.

Details

Reviewers
tmatheson
simon_tatham
Commits
rGca7ffe09dc6e: [AArch64] Rename CPY to DUP. NFC
Summary

These instructions have nothing to do with the new MOP CPY instructions, and are better named DUP to avoid confusion.

Diff Detail

Event Timeline

dmgreen created this revision.Jan 5 2022, 5:14 AM
Herald added subscribers: hiraditya, kristof.beyls. · View Herald TranscriptJan 5 2022, 5:14 AM
dmgreen requested review of this revision.Jan 5 2022, 5:14 AM
Herald added a project: Restricted Project. · View Herald TranscriptJan 5 2022, 5:14 AM
Harbormaster completed remote builds in B141654: Diff 397538.Jan 5 2022, 5:15 AM
dmgreen mentioned this in D116157: [AArch64] Adding "armv8.8-a" memcpy/memset support..Jan 5 2022, 5:15 AM
tmatheson added a comment.Jan 5 2022, 6:51 AM

This renames the following instructions that were captured by the scheduler regex: CPYi8, CPYi16, CPYi32, CPYi64.

The regex was also (unintentionally?) capturing the following SVE instructoins: CPY_ZPmI_B, CPY_ZPmI_D, CPY_ZPmI_H, CPY_ZPmI_S, CPY_ZPmR_B, CPY_ZPmR_D, CPY_ZPmR_H, CPY_ZPmR_S, CPY_ZPmV_B, CPY_ZPmV_D, CPY_ZPmV_H, CPY_ZPmV_S, CPY_ZPzI_B, CPY_ZPzI_D, CPY_ZPzI_H, CPY_ZPzI_S

Do we need to do anything with them?

dmgreen added a comment.Jan 5 2022, 8:35 AM
In D116655#3222267, @tmatheson wrote:

This renames the following instructions that were captured by the scheduler regex: CPYi8, CPYi16, CPYi32, CPYi64.

The regex was also (unintentionally?) capturing the following SVE instructoins: CPY_ZPmI_B, CPY_ZPmI_D, CPY_ZPmI_H, CPY_ZPmI_S, CPY_ZPmR_B, CPY_ZPmR_D, CPY_ZPmR_H, CPY_ZPmR_S, CPY_ZPmV_B, CPY_ZPmV_D, CPY_ZPmV_H, CPY_ZPmV_S, CPY_ZPzI_B, CPY_ZPzI_D, CPY_ZPzI_H, CPY_ZPzI_S

Do we need to do anything with them?

I though it was fine - the only cpu that has scheduling info and SVE instructions at the moment is the A64FX. That schedule has other lines for the CPY instructions, but looking again it looks like they are actually commented out.

I've uncommented them so they are the same as before.

dmgreen updated this revision to Diff 397594.Jan 5 2022, 8:37 AM
Harbormaster completed remote builds in B141688: Diff 397594.Jan 5 2022, 9:23 AM
tmatheson accepted this revision.Jan 5 2022, 10:03 AM

LGTM

This revision is now accepted and ready to land.Jan 5 2022, 10:03 AM
This revision was landed with ongoing or failed builds.Jan 5 2022, 12:02 PM
Closed by commit rGca7ffe09dc6e: [AArch64] Rename CPY to DUP. NFC (authored by dmgreen). · Explain Why
This revision was automatically updated to reflect the committed changes.
dmgreen added a commit: rGca7ffe09dc6e: [AArch64] Rename CPY to DUP. NFC.

Revision Contents

Diff 397662

llvm/lib/Target/AArch64/AArch64InstrFormats.td

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Show First 20 Lines • Show All 7,694 Lines • ▼ Show 20 Lines def : SIMDTableLookupAlias<asm # ".16b",
V128, VecListThree128>; V128, VecListThree128>;
def : SIMDTableLookupAlias<asm # ".16b", def : SIMDTableLookupAlias<asm # ".16b",
!cast<Instruction>(NAME#"v16i8Four"), !cast<Instruction>(NAME#"v16i8Four"),
V128, VecListFour128>; V128, VecListFour128>;
} }
//---------------------------------------------------------------------------- //----------------------------------------------------------------------------
// AdvSIMD scalar CPY // AdvSIMD scalar DUP
//---------------------------------------------------------------------------- //----------------------------------------------------------------------------
let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
class BaseSIMDScalarCPY<RegisterClass regtype, RegisterOperand vectype, class BaseSIMDScalarDUP<RegisterClass regtype, RegisterOperand vectype,
string asm, string kind, Operand idxtype> string asm, string kind, Operand idxtype>
: I<(outs regtype:$dst), (ins vectype:$src, idxtype:$idx), asm, : I<(outs regtype:$dst), (ins vectype:$src, idxtype:$idx), asm,
"{\t$dst, $src" # kind # "$idx" # "{\t$dst, $src" # kind # "$idx" #
"|\t$dst, $src$idx}", "", []>, "|\t$dst, $src$idx}", "", []>,
Sched<[WriteVd]> { Sched<[WriteVd]> {
bits<5> dst; bits<5> dst;
bits<5> src; bits<5> src;
let Inst{31-21} = 0b01011110000; let Inst{31-21} = 0b01011110000;
let Inst{15-10} = 0b000001; let Inst{15-10} = 0b000001;
let Inst{9-5} = src; let Inst{9-5} = src;
let Inst{4-0} = dst; let Inst{4-0} = dst;
} }
class SIMDScalarCPYAlias<string asm, string size, Instruction inst, class SIMDScalarDUPAlias<string asm, string size, Instruction inst,
RegisterClass regtype, RegisterOperand vectype, Operand idxtype> RegisterClass regtype, RegisterOperand vectype, Operand idxtype>
: InstAlias<asm # "{\t$dst, $src" # size # "$index" : InstAlias<asm # "{\t$dst, $src" # size # "$index"
# "|\t$dst, $src$index}", # "|\t$dst, $src$index}",
(inst regtype:$dst, vectype:$src, idxtype:$index), 0>; (inst regtype:$dst, vectype:$src, idxtype:$index), 0>;
multiclass SIMDScalarCPY<string asm> { multiclass SIMDScalarDUP<string asm> {
def i8 : BaseSIMDScalarCPY<FPR8, V128, asm, ".b", VectorIndexB> { def i8 : BaseSIMDScalarDUP<FPR8, V128, asm, ".b", VectorIndexB> {
bits<4> idx; bits<4> idx;
let Inst{20-17} = idx; let Inst{20-17} = idx;
let Inst{16} = 1; let Inst{16} = 1;
} }
def i16 : BaseSIMDScalarCPY<FPR16, V128, asm, ".h", VectorIndexH> { def i16 : BaseSIMDScalarDUP<FPR16, V128, asm, ".h", VectorIndexH> {
bits<3> idx; bits<3> idx;
let Inst{20-18} = idx; let Inst{20-18} = idx;
let Inst{17-16} = 0b10; let Inst{17-16} = 0b10;
} }
def i32 : BaseSIMDScalarCPY<FPR32, V128, asm, ".s", VectorIndexS> { def i32 : BaseSIMDScalarDUP<FPR32, V128, asm, ".s", VectorIndexS> {
bits<2> idx; bits<2> idx;
let Inst{20-19} = idx; let Inst{20-19} = idx;
let Inst{18-16} = 0b100; let Inst{18-16} = 0b100;
} }
def i64 : BaseSIMDScalarCPY<FPR64, V128, asm, ".d", VectorIndexD> { def i64 : BaseSIMDScalarDUP<FPR64, V128, asm, ".d", VectorIndexD> {
bits<1> idx; bits<1> idx;
let Inst{20} = idx; let Inst{20} = idx;
let Inst{19-16} = 0b1000; let Inst{19-16} = 0b1000;
} }
def : Pat<(v1i64 (scalar_to_vector (i64 (vector_extract (v2i64 V128:$src), def : Pat<(v1i64 (scalar_to_vector (i64 (vector_extract (v2i64 V128:$src),
VectorIndexD:$idx)))), VectorIndexD:$idx)))),
(!cast<Instruction>(NAME # i64) V128:$src, VectorIndexD:$idx)>; (!cast<Instruction>(NAME # i64) V128:$src, VectorIndexD:$idx)>;
// 'DUP' mnemonic aliases. // 'DUP' mnemonic aliases.
def : SIMDScalarCPYAlias<"dup", ".b", def : SIMDScalarDUPAlias<"dup", ".b",
!cast<Instruction>(NAME#"i8"), !cast<Instruction>(NAME#"i8"),
FPR8, V128, VectorIndexB>; FPR8, V128, VectorIndexB>;
def : SIMDScalarCPYAlias<"dup", ".h", def : SIMDScalarDUPAlias<"dup", ".h",
!cast<Instruction>(NAME#"i16"), !cast<Instruction>(NAME#"i16"),
FPR16, V128, VectorIndexH>; FPR16, V128, VectorIndexH>;
def : SIMDScalarCPYAlias<"dup", ".s", def : SIMDScalarDUPAlias<"dup", ".s",
!cast<Instruction>(NAME#"i32"), !cast<Instruction>(NAME#"i32"),
FPR32, V128, VectorIndexS>; FPR32, V128, VectorIndexS>;
def : SIMDScalarCPYAlias<"dup", ".d", def : SIMDScalarDUPAlias<"dup", ".d",
!cast<Instruction>(NAME#"i64"), !cast<Instruction>(NAME#"i64"),
FPR64, V128, VectorIndexD>; FPR64, V128, VectorIndexD>;
} }
//---------------------------------------------------------------------------- //----------------------------------------------------------------------------
// AdvSIMD modified immediate instructions // AdvSIMD modified immediate instructions
//---------------------------------------------------------------------------- //----------------------------------------------------------------------------
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llvm/lib/Target/AArch64/AArch64InstrInfo.td

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Show First 20 Lines • Show All 5,368 Lines • ▼ Show 20 Linesdef : Pat<(v8i8 (int_aarch64_neon_tbx1 (v8i8 V64:$Rd),
(v16i8 VecListOne128:$Rn), (v8i8 V64:$Ri))), (v16i8 VecListOne128:$Rn), (v8i8 V64:$Ri))),
(TBXv8i8One V64:$Rd, VecListOne128:$Rn, V64:$Ri)>; (TBXv8i8One V64:$Rd, VecListOne128:$Rn, V64:$Ri)>;
def : Pat<(v16i8 (int_aarch64_neon_tbx1 (v16i8 V128:$Rd), def : Pat<(v16i8 (int_aarch64_neon_tbx1 (v16i8 V128:$Rd),
(v16i8 V128:$Ri), (v16i8 V128:$Rn))), (v16i8 V128:$Ri), (v16i8 V128:$Rn))),
(TBXv16i8One V128:$Rd, V128:$Ri, V128:$Rn)>; (TBXv16i8One V128:$Rd, V128:$Ri, V128:$Rn)>;
//---------------------------------------------------------------------------- //----------------------------------------------------------------------------
// AdvSIMD scalar CPY instruction // AdvSIMD scalar DUP instruction
//---------------------------------------------------------------------------- //----------------------------------------------------------------------------
defm CPY : SIMDScalarCPY<"mov">; defm DUP : SIMDScalarDUP<"mov">;
//---------------------------------------------------------------------------- //----------------------------------------------------------------------------
// AdvSIMD scalar pairwise instructions // AdvSIMD scalar pairwise instructions
//---------------------------------------------------------------------------- //----------------------------------------------------------------------------
defm ADDP : SIMDPairwiseScalarD<0, 0b11011, "addp">; defm ADDP : SIMDPairwiseScalarD<0, 0b11011, "addp">;
defm FADDP : SIMDFPPairwiseScalar<0, 0b01101, "faddp">; defm FADDP : SIMDFPPairwiseScalar<0, 0b01101, "faddp">;
defm FMAXNMP : SIMDFPPairwiseScalar<0, 0b01100, "fmaxnmp">; defm FMAXNMP : SIMDFPPairwiseScalar<0, 0b01100, "fmaxnmp">;
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defm : Neon_INS_elt_pattern<v8f16, v4f16, f16, INSvi16lane>; defm : Neon_INS_elt_pattern<v8f16, v4f16, f16, INSvi16lane>;
defm : Neon_INS_elt_pattern<v8bf16, v4bf16, bf16, INSvi16lane>; defm : Neon_INS_elt_pattern<v8bf16, v4bf16, bf16, INSvi16lane>;
defm : Neon_INS_elt_pattern<v4f32, v2f32, f32, INSvi32lane>; defm : Neon_INS_elt_pattern<v4f32, v2f32, f32, INSvi32lane>;
defm : Neon_INS_elt_pattern<v2f64, v1f64, f64, INSvi64lane>; defm : Neon_INS_elt_pattern<v2f64, v1f64, f64, INSvi64lane>;
// Floating point vector extractions are codegen'd as either a sequence of // Floating point vector extractions are codegen'd as either a sequence of
// subregister extractions, or a MOV (aka CPY here, alias for DUP) if // subregister extractions, or a MOV (aka DUP here) if
// the lane number is anything other than zero. // the lane number is anything other than zero.
def : Pat<(vector_extract (v2f64 V128:$Rn), 0), def : Pat<(vector_extract (v2f64 V128:$Rn), 0),
(f64 (EXTRACT_SUBREG V128:$Rn, dsub))>; (f64 (EXTRACT_SUBREG V128:$Rn, dsub))>;
def : Pat<(vector_extract (v4f32 V128:$Rn), 0), def : Pat<(vector_extract (v4f32 V128:$Rn), 0),
(f32 (EXTRACT_SUBREG V128:$Rn, ssub))>; (f32 (EXTRACT_SUBREG V128:$Rn, ssub))>;
def : Pat<(vector_extract (v8f16 V128:$Rn), 0), def : Pat<(vector_extract (v8f16 V128:$Rn), 0),
(f16 (EXTRACT_SUBREG V128:$Rn, hsub))>; (f16 (EXTRACT_SUBREG V128:$Rn, hsub))>;
def : Pat<(vector_extract (v8bf16 V128:$Rn), 0), def : Pat<(vector_extract (v8bf16 V128:$Rn), 0),
(bf16 (EXTRACT_SUBREG V128:$Rn, hsub))>; (bf16 (EXTRACT_SUBREG V128:$Rn, hsub))>;
def : Pat<(vector_extract (v2f64 V128:$Rn), VectorIndexD:$idx), def : Pat<(vector_extract (v2f64 V128:$Rn), VectorIndexD:$idx),
(f64 (CPYi64 V128:$Rn, VectorIndexD:$idx))>; (f64 (DUPi64 V128:$Rn, VectorIndexD:$idx))>;
def : Pat<(vector_extract (v4f32 V128:$Rn), VectorIndexS:$idx), def : Pat<(vector_extract (v4f32 V128:$Rn), VectorIndexS:$idx),
(f32 (CPYi32 V128:$Rn, VectorIndexS:$idx))>; (f32 (DUPi32 V128:$Rn, VectorIndexS:$idx))>;
def : Pat<(vector_extract (v8f16 V128:$Rn), VectorIndexH:$idx), def : Pat<(vector_extract (v8f16 V128:$Rn), VectorIndexH:$idx),
(f16 (CPYi16 V128:$Rn, VectorIndexH:$idx))>; (f16 (DUPi16 V128:$Rn, VectorIndexH:$idx))>;
def : Pat<(vector_extract (v8bf16 V128:$Rn), VectorIndexH:$idx), def : Pat<(vector_extract (v8bf16 V128:$Rn), VectorIndexH:$idx),
(bf16 (CPYi16 V128:$Rn, VectorIndexH:$idx))>; (bf16 (DUPi16 V128:$Rn, VectorIndexH:$idx))>;
// All concat_vectors operations are canonicalised to act on i64 vectors for // All concat_vectors operations are canonicalised to act on i64 vectors for
// AArch64. In the general case we need an instruction, which had just as well be // AArch64. In the general case we need an instruction, which had just as well be
// INS. // INS.
class ConcatPat<ValueType DstTy, ValueType SrcTy> class ConcatPat<ValueType DstTy, ValueType SrcTy>
: Pat<(DstTy (concat_vectors (SrcTy V64:$Rd), V64:$Rn)), : Pat<(DstTy (concat_vectors (SrcTy V64:$Rd), V64:$Rn)),
(INSvi64lane (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), 1, (INSvi64lane (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), 1,
(INSERT_SUBREG (IMPLICIT_DEF), V64:$Rn, dsub), 0)>; (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rn, dsub), 0)>;
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// We have to resort to tricks to turn a single-input store into a store pair, // We have to resort to tricks to turn a single-input store into a store pair,
// because there is no single-input nontemporal store, only STNP. // because there is no single-input nontemporal store, only STNP.
let Predicates = [IsLE] in { let Predicates = [IsLE] in {
let AddedComplexity = 15 in { let AddedComplexity = 15 in {
class NTStore128Pat<ValueType VT> : class NTStore128Pat<ValueType VT> :
Pat<(nontemporalstore (VT FPR128:$Rt), Pat<(nontemporalstore (VT FPR128:$Rt),
(am_indexed7s64 GPR64sp:$Rn, simm7s8:$offset)), (am_indexed7s64 GPR64sp:$Rn, simm7s8:$offset)),
(STNPDi (EXTRACT_SUBREG FPR128:$Rt, dsub), (STNPDi (EXTRACT_SUBREG FPR128:$Rt, dsub),
(CPYi64 FPR128:$Rt, (i64 1)), (DUPi64 FPR128:$Rt, (i64 1)),
GPR64sp:$Rn, simm7s8:$offset)>; GPR64sp:$Rn, simm7s8:$offset)>;
def : NTStore128Pat<v2i64>; def : NTStore128Pat<v2i64>;
def : NTStore128Pat<v4i32>; def : NTStore128Pat<v4i32>;
def : NTStore128Pat<v8i16>; def : NTStore128Pat<v8i16>;
def : NTStore128Pat<v16i8>; def : NTStore128Pat<v16i8>;
class NTStore64Pat<ValueType VT> : class NTStore64Pat<ValueType VT> :
Pat<(nontemporalstore (VT FPR64:$Rt), Pat<(nontemporalstore (VT FPR64:$Rt),
(am_indexed7s32 GPR64sp:$Rn, simm7s4:$offset)), (am_indexed7s32 GPR64sp:$Rn, simm7s4:$offset)),
(STNPSi (EXTRACT_SUBREG FPR64:$Rt, ssub), (STNPSi (EXTRACT_SUBREG FPR64:$Rt, ssub),
(CPYi32 (SUBREG_TO_REG (i64 0), FPR64:$Rt, dsub), (i64 1)), (DUPi32 (SUBREG_TO_REG (i64 0), FPR64:$Rt, dsub), (i64 1)),
GPR64sp:$Rn, simm7s4:$offset)>; GPR64sp:$Rn, simm7s4:$offset)>;
// FIXME: Shouldn't v1f64 loads/stores be promoted to v1i64? // FIXME: Shouldn't v1f64 loads/stores be promoted to v1i64?
def : NTStore64Pat<v1f64>; def : NTStore64Pat<v1f64>;
def : NTStore64Pat<v1i64>; def : NTStore64Pat<v1i64>;
def : NTStore64Pat<v2i32>; def : NTStore64Pat<v2i32>;
def : NTStore64Pat<v4i16>; def : NTStore64Pat<v4i16>;
def : NTStore64Pat<v8i8>; def : NTStore64Pat<v8i8>;
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llvm/lib/Target/AArch64/AArch64SchedA57.td

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// Q form - v16i8, v8i16, v4i32 // Q form - v16i8, v8i16, v4i32
// D form - v1i8, v1i16, v1i32, v1i64 // D form - v1i8, v1i16, v1i32, v1i64
// Q form - v16i8, v8i16, v4i32, v2i64 // Q form - v16i8, v8i16, v4i32, v2i64
// ASIMD bitwise insert, Q-form // ASIMD bitwise insert, Q-form
def : InstRW<[A57Write_3cyc_2V], (instregex "^(BIF|BIT|BSL|BSP)v16i8")>; def : InstRW<[A57Write_3cyc_2V], (instregex "^(BIF|BIT|BSL|BSP)v16i8")>;
// ASIMD duplicate, gen reg, D-form and Q-form // ASIMD duplicate, gen reg, D-form and Q-form
def : InstRW<[A57Write_8cyc_1L_1V], (instregex "^CPY[^PMEF]")>; def : InstRW<[A57Write_8cyc_1L_1V], (instregex "^DUP(i8|i16|i32|i64)$")>;
def : InstRW<[A57Write_8cyc_1L_1V], (instregex "^DUPv.+gpr")>; def : InstRW<[A57Write_8cyc_1L_1V], (instregex "^DUPv.+gpr")>;
// ASIMD move, saturating // ASIMD move, saturating
def : InstRW<[A57Write_4cyc_1X], (instregex "^[SU]QXTU?N")>; def : InstRW<[A57Write_4cyc_1X], (instregex "^[SU]QXTU?N")>;
// ASIMD reciprocal estimate, D-form // ASIMD reciprocal estimate, D-form
def : InstRW<[A57Write_5cyc_1V], (instregex "^[FU](RECP|RSQRT)(E|X)(v2f32|v1i32|v2i32|v1i64)")>; def : InstRW<[A57Write_5cyc_1V], (instregex "^[FU](RECP|RSQRT)(E|X)(v2f32|v1i32|v2i32|v1i64)")>;
// ASIMD reciprocal estimate, Q-form // ASIMD reciprocal estimate, Q-form
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llvm/lib/Target/AArch64/AArch64SchedA64FX.td

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// ASIMD count, D-form // ASIMD count, D-form
// ASIMD count, Q-form // ASIMD count, Q-form
def : InstRW<[A64FXWrite_4Cyc_GI0], def : InstRW<[A64FXWrite_4Cyc_GI0],
(instregex "^CLSv", "^CLZv", "^CNTv")>; (instregex "^CLSv", "^CLZv", "^CNTv")>;
// ASIMD duplicate, gen reg // ASIMD duplicate, gen reg
// ASIMD duplicate, element // ASIMD duplicate, element
def : InstRW<[A64FXWrite_DUPGENERAL], (instregex "^DUPv")>; def : InstRW<[A64FXWrite_DUPGENERAL], (instregex "^DUPv")>;
def : InstRW<[A64FXWrite_6Cyc_GI0], (instregex "^CPY[^PMEF]")>; def : InstRW<[A64FXWrite_6Cyc_GI0], (instregex "^DUP(i8|i16|i32|i64)$")>;
def : InstRW<[A64FXWrite_6Cyc_GI0], (instregex "^DUPv.+gpr")>; def : InstRW<[A64FXWrite_6Cyc_GI0], (instregex "^DUPv.+gpr")>;
// ASIMD extract // ASIMD extract
def : InstRW<[A64FXWrite_6Cyc_GI0], (instregex "^EXTv")>; def : InstRW<[A64FXWrite_6Cyc_GI0], (instregex "^EXTv")>;
// ASIMD extract narrow // ASIMD extract narrow
def : InstRW<[A64FXWrite_6Cyc_GI3], (instregex "^XTNv")>; def : InstRW<[A64FXWrite_6Cyc_GI3], (instregex "^XTNv")>;
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// [70] "cntw $Rd, $pattern, mul $imm4"; // [70] "cntw $Rd, $pattern, mul $imm4";
def : InstRW<[A64FXWrite_1Cyc_GI24], (instrs CNTW_XPiI)>; def : InstRW<[A64FXWrite_1Cyc_GI24], (instrs CNTW_XPiI)>;
// [71] "compact $Zd, $Pg, $Zn"; // [71] "compact $Zd, $Pg, $Zn";
def : InstRW<[A64FXWrite_6Cyc_GI0], (instrs COMPACT_ZPZ_D, COMPACT_ZPZ_S)>; def : InstRW<[A64FXWrite_6Cyc_GI0], (instrs COMPACT_ZPZ_D, COMPACT_ZPZ_S)>;
// [72] "cpy $Zd, $Pg/m, $Rn"; // [72] "cpy $Zd, $Pg/m, $Rn";
//@@@ def : InstRW<[XXXXXX], (instrs CPY_ZPmR_B, CPY_ZPmR_D, CPY_ZPmR_H, CPY_ZPmR_S)>; def : InstRW<[A64FXWrite_6Cyc_GI0], (instrs CPY_ZPmR_B, CPY_ZPmR_D, CPY_ZPmR_H, CPY_ZPmR_S)>;
// [73] "cpy $Zd, $Pg/m, $Vn"; // [73] "cpy $Zd, $Pg/m, $Vn";
//@@@ def : InstRW<[XXXXXX], (instrs CPY_ZPmV_B, CPY_ZPmV_D, CPY_ZPmV_H, CPY_ZPmV_S)>; def : InstRW<[A64FXWrite_6Cyc_GI0], (instrs CPY_ZPmV_B, CPY_ZPmV_D, CPY_ZPmV_H, CPY_ZPmV_S)>;
// [74] "cpy $Zd, $Pg/m, $imm"; // [74] "cpy $Zd, $Pg/m, $imm";
//@@@ def : InstRW<[XXXXXX], (instrs CPY_ZPmI_B, CPY_ZPmI_D, CPY_ZPmI_H, CPY_ZPmI_S)>; def : InstRW<[A64FXWrite_6Cyc_GI0], (instrs CPY_ZPmI_B, CPY_ZPmI_D, CPY_ZPmI_H, CPY_ZPmI_S)>;
// [75] "cpy $Zd, $Pg/z, $imm"; // [75] "cpy $Zd, $Pg/z, $imm";
//@@@ def : InstRW<[XXXXXX], (instrs CPY_ZPzI_B, CPY_ZPzI_D, CPY_ZPzI_H, CPY_ZPzI_S)>; def : InstRW<[A64FXWrite_6Cyc_GI0], (instrs CPY_ZPzI_B, CPY_ZPzI_D, CPY_ZPzI_H, CPY_ZPzI_S)>;
// [76] "ctermeq $Rn, $Rm"; // [76] "ctermeq $Rn, $Rm";
def : InstRW<[A64FXWrite_2Cyc_GI24], (instrs CTERMEQ_WW, CTERMEQ_XX)>; def : InstRW<[A64FXWrite_2Cyc_GI24], (instrs CTERMEQ_WW, CTERMEQ_XX)>;
// [77] "ctermne $Rn, $Rm"; // [77] "ctermne $Rn, $Rm";
def : InstRW<[A64FXWrite_2Cyc_GI24], (instrs CTERMNE_WW, CTERMNE_XX)>; def : InstRW<[A64FXWrite_2Cyc_GI24], (instrs CTERMNE_WW, CTERMNE_XX)>;
// [78] "decb $Rdn, $pattern, mul $imm4"; // [78] "decb $Rdn, $pattern, mul $imm4";
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llvm/lib/Target/AArch64/AArch64SchedExynosM3.td

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// ASIMD miscellaneous instructions. // ASIMD miscellaneous instructions.
def : InstRW<[M3WriteNALU1], (instregex "^RBITv")>; def : InstRW<[M3WriteNALU1], (instregex "^RBITv")>;
def : InstRW<[M3WriteNALU1], (instregex "^(BIF|BIT|BSL|BSP)v")>; def : InstRW<[M3WriteNALU1], (instregex "^(BIF|BIT|BSL|BSP)v")>;
def : InstRW<[M3WriteNEONB], (instregex "^DUPv.+gpr")>; def : InstRW<[M3WriteNEONB], (instregex "^DUPv.+gpr")>;
def : InstRW<[M3WriteNSHF1], (instregex "^DUPv.+lane")>; def : InstRW<[M3WriteNSHF1], (instregex "^DUPv.+lane")>;
def : InstRW<[M3WriteNSHF1], (instregex "^EXTv")>; def : InstRW<[M3WriteNSHF1], (instregex "^EXTv")>;
def : InstRW<[M3WriteNSHF1], (instregex "^[SU]?Q?XTU?Nv")>; def : InstRW<[M3WriteNSHF1], (instregex "^[SU]?Q?XTU?Nv")>;
def : InstRW<[M3WriteNSHF1], (instregex "^CPY[^PMEF]")>; def : InstRW<[M3WriteNSHF1], (instregex "^DUP(i8|i16|i32|i64)$")>;
def : InstRW<[M3WriteNSHF1], (instregex "^INSv.+lane")>; def : InstRW<[M3WriteNSHF1], (instregex "^INSv.+lane")>;
def : InstRW<[M3WriteMOVI], (instregex "^MOVI")>; def : InstRW<[M3WriteMOVI], (instregex "^MOVI")>;
def : InstRW<[M3WriteNALU1], (instregex "^FMOVv")>; def : InstRW<[M3WriteNALU1], (instregex "^FMOVv")>;
def : InstRW<[M3WriteFCVT4], (instregex "^[FU](RECP|RSQRT)Ev[248]")>; def : InstRW<[M3WriteFCVT4], (instregex "^[FU](RECP|RSQRT)Ev[248]")>;
def : InstRW<[M3WriteFMAC4, def : InstRW<[M3WriteFMAC4,
M3ReadFMAC], (instregex "^F(RECP|RSQRT)Sv")>; M3ReadFMAC], (instregex "^F(RECP|RSQRT)Sv")>;
def : InstRW<[M3WriteNSHF1], (instregex "^REV(16|32|64)v")>; def : InstRW<[M3WriteNSHF1], (instregex "^REV(16|32|64)v")>;
def : InstRW<[M3WriteNSHF1], (instregex "^TB[LX]v")>; def : InstRW<[M3WriteNSHF1], (instregex "^TB[LX]v")>;
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llvm/lib/Target/AArch64/AArch64SchedExynosM4.td

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def : InstRW<[M4WriteNEONX], (instrs FSQRTv4f32)>; def : InstRW<[M4WriteNEONX], (instrs FSQRTv4f32)>;
def : InstRW<[M4WriteNEONY], (instrs FSQRTv2f64)>; def : InstRW<[M4WriteNEONY], (instrs FSQRTv2f64)>;
// ASIMD miscellaneous instructions. // ASIMD miscellaneous instructions.
def : InstRW<[M4WriteNALU1], (instregex "^RBITv")>; def : InstRW<[M4WriteNALU1], (instregex "^RBITv")>;
def : InstRW<[M4WriteNALU1], (instregex "^(BIF|BIT|BSL|BSP)v")>; def : InstRW<[M4WriteNALU1], (instregex "^(BIF|BIT|BSL|BSP)v")>;
def : InstRW<[M4WriteNALU1], (instregex "^CL[STZ]v")>; def : InstRW<[M4WriteNALU1], (instregex "^CL[STZ]v")>;
def : InstRW<[M4WriteNEONB], (instregex "^DUPv.+gpr")>; def : InstRW<[M4WriteNEONB], (instregex "^DUPv.+gpr")>;
def : InstRW<[M4WriteNSHF1], (instregex "^CPY[^PMEF]")>; def : InstRW<[M4WriteNSHF1], (instregex "^DUP(i8|i16|i32|i64)$")>;
def : InstRW<[M4WriteNSHF1], (instregex "^DUPv.+lane")>; def : InstRW<[M4WriteNSHF1], (instregex "^DUPv.+lane")>;
def : InstRW<[M4WriteNSHF1], (instregex "^EXTv")>; def : InstRW<[M4WriteNSHF1], (instregex "^EXTv")>;
def : InstRW<[M4WriteNSHT4A], (instregex "^XTNv")>; def : InstRW<[M4WriteNSHT4A], (instregex "^XTNv")>;
def : InstRW<[M4WriteNSHT4A], (instregex "^[SU]?QXTU?Nv")>; def : InstRW<[M4WriteNSHT4A], (instregex "^[SU]?QXTU?Nv")>;
def : InstRW<[M4WriteNEONB], (instregex "^INSv.+gpr")>; def : InstRW<[M4WriteNEONB], (instregex "^INSv.+gpr")>;
def : InstRW<[M4WriteNSHF1], (instregex "^INSv.+lane")>; def : InstRW<[M4WriteNSHF1], (instregex "^INSv.+lane")>;
def : InstRW<[M4WriteMOVI], (instregex "^(MOV|MVN)I")>; def : InstRW<[M4WriteMOVI], (instregex "^(MOV|MVN)I")>;
def : InstRW<[M4WriteNALU1H], (instregex "^FMOVv.f16")>; def : InstRW<[M4WriteNALU1H], (instregex "^FMOVv.f16")>;
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llvm/lib/Target/AArch64/AArch64SchedExynosM5.td

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def : InstRW<[M5WriteNEONX], (instrs FSQRTv4f32)>; def : InstRW<[M5WriteNEONX], (instrs FSQRTv4f32)>;
def : InstRW<[M5WriteNEONY], (instrs FSQRTv2f64)>; def : InstRW<[M5WriteNEONY], (instrs FSQRTv2f64)>;
// ASIMD miscellaneous instructions. // ASIMD miscellaneous instructions.
def : InstRW<[M5WriteNALU2], (instregex "^RBITv")>; def : InstRW<[M5WriteNALU2], (instregex "^RBITv")>;
def : InstRW<[M5WriteNALU2], (instregex "^(BIF|BIT|BSL|BSP)v")>; def : InstRW<[M5WriteNALU2], (instregex "^(BIF|BIT|BSL|BSP)v")>;
def : InstRW<[M5WriteNALU2], (instregex "^CL[STZ]v")>; def : InstRW<[M5WriteNALU2], (instregex "^CL[STZ]v")>;
def : InstRW<[M5WriteNEONB], (instregex "^DUPv.+gpr")>; def : InstRW<[M5WriteNEONB], (instregex "^DUPv.+gpr")>;
def : InstRW<[M5WriteNSHF2], (instregex "^CPY[^PMEF]")>; def : InstRW<[M5WriteNSHF2], (instregex "^DUP(i8|i16|i32|i64)$")>;
def : InstRW<[M5WriteNSHF2], (instregex "^DUPv.+lane")>; def : InstRW<[M5WriteNSHF2], (instregex "^DUPv.+lane")>;
def : InstRW<[M5WriteNSHF2], (instregex "^EXTv")>; def : InstRW<[M5WriteNSHF2], (instregex "^EXTv")>;
def : InstRW<[M5WriteNSHT4A], (instregex "^XTNv")>; def : InstRW<[M5WriteNSHT4A], (instregex "^XTNv")>;
def : InstRW<[M5WriteNSHT4A], (instregex "^[SU]?QXTU?Nv")>; def : InstRW<[M5WriteNSHT4A], (instregex "^[SU]?QXTU?Nv")>;
def : InstRW<[M5WriteNEONB], (instregex "^INSv.+gpr")>; def : InstRW<[M5WriteNEONB], (instregex "^INSv.+gpr")>;
def : InstRW<[M5WriteNSHF2], (instregex "^INSv.+lane")>; def : InstRW<[M5WriteNSHF2], (instregex "^INSv.+lane")>;
def : InstRW<[M5WriteMOVI], (instregex "^(MOV|MVN)I")>; def : InstRW<[M5WriteMOVI], (instregex "^(MOV|MVN)I")>;
def : InstRW<[M5WriteNALU1], (instregex "^FMOVv.f(16|32|64)")>; def : InstRW<[M5WriteNALU1], (instregex "^FMOVv.f(16|32|64)")>;
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llvm/lib/Target/AArch64/AArch64SchedFalkorDetails.td

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def : InstRW<[FalkorWr_1XYZ_1cyc], (instregex "^SUB(S)?(W|X)r(r|i)$")>; def : InstRW<[FalkorWr_1XYZ_1cyc], (instregex "^SUB(S)?(W|X)r(r|i)$")>;
def : InstRW<[FalkorWr_ADDSUBsx], (instregex "^ADD(S)?(W|X)r(s|x|x64)$")>; def : InstRW<[FalkorWr_ADDSUBsx], (instregex "^ADD(S)?(W|X)r(s|x|x64)$")>;
def : InstRW<[FalkorWr_ADDSUBsx], (instregex "^SUB(S)?(W|X)r(s|x|x64)$")>; def : InstRW<[FalkorWr_ADDSUBsx], (instregex "^SUB(S)?(W|X)r(s|x|x64)$")>;
// SIMD Miscellaneous Instructions // SIMD Miscellaneous Instructions
// ----------------------------------------------------------------------------- // -----------------------------------------------------------------------------
def : InstRW<[FalkorWr_1GTOV_1cyc], (instregex "^DUP(v8i8|v4i16|v2i32)(gpr|lane)$")>; def : InstRW<[FalkorWr_1GTOV_1cyc], (instregex "^DUP(v8i8|v4i16|v2i32)(gpr|lane)$")>;
def : InstRW<[FalkorWr_1VXVY_1cyc], (instregex "^DUP(v16i8|v8i16)(gpr|lane)$")>; def : InstRW<[FalkorWr_1VXVY_1cyc], (instregex "^DUP(v16i8|v8i16)(gpr|lane)$")>;
def : InstRW<[FalkorWr_1VXVY_1cyc], (instregex "^CPY(i8|i16|i32|i64)$")>; def : InstRW<[FalkorWr_1VXVY_1cyc], (instregex "^DUP(i8|i16|i32|i64)$")>;
def : InstRW<[FalkorWr_1GTOV_1cyc], (instregex "^INSv(i8|i16)(gpr|lane)$")>; def : InstRW<[FalkorWr_1GTOV_1cyc], (instregex "^INSv(i8|i16)(gpr|lane)$")>;
def : InstRW<[FalkorWr_1VTOG_1cyc], (instregex "^(S|U)MOVv.*$")>; def : InstRW<[FalkorWr_1VTOG_1cyc], (instregex "^(S|U)MOVv.*$")>;
def : InstRW<[FalkorWr_1VXVY_1cyc], (instregex "^(BIF|BIT|BSL|BSP)v8i8$")>; def : InstRW<[FalkorWr_1VXVY_1cyc], (instregex "^(BIF|BIT|BSL|BSP)v8i8$")>;
def : InstRW<[FalkorWr_1VXVY_1cyc], (instrs EXTv8i8)>; def : InstRW<[FalkorWr_1VXVY_1cyc], (instrs EXTv8i8)>;
def : InstRW<[FalkorWr_1VXVY_0cyc], (instregex "(MOVI|MVNI)(D|v8b_ns|v2i32|v4i16|v2s_msl)$")>; // imm fwd def : InstRW<[FalkorWr_1VXVY_0cyc], (instregex "(MOVI|MVNI)(D|v8b_ns|v2i32|v4i16|v2s_msl)$")>; // imm fwd
def : InstRW<[FalkorWr_1VXVY_1cyc], (instrs TBLv8i8One)>; def : InstRW<[FalkorWr_1VXVY_1cyc], (instrs TBLv8i8One)>;
def : InstRW<[FalkorWr_1VXVY_1cyc], (instrs NOTv8i8)>; def : InstRW<[FalkorWr_1VXVY_1cyc], (instrs NOTv8i8)>;
def : InstRW<[FalkorWr_1VXVY_1cyc], (instregex "^REV(16|32|64)v.*$")>; def : InstRW<[FalkorWr_1VXVY_1cyc], (instregex "^REV(16|32|64)v.*$")>;
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llvm/lib/Target/AArch64/AArch64SchedThunderX2T99.td

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// ASIMD count, D-form // ASIMD count, D-form
// ASIMD count, Q-form // ASIMD count, Q-form
def : InstRW<[THX2T99Write_5Cyc_F01], def : InstRW<[THX2T99Write_5Cyc_F01],
(instregex "^CLSv", "^CLZv", "^CNTv")>; (instregex "^CLSv", "^CLZv", "^CNTv")>;
// ASIMD duplicate, gen reg // ASIMD duplicate, gen reg
// ASIMD duplicate, element // ASIMD duplicate, element
def : InstRW<[THX2T99Write_5Cyc_F01], (instregex "^DUPv")>; def : InstRW<[THX2T99Write_5Cyc_F01], (instregex "^DUPv")>;
def : InstRW<[THX2T99Write_5Cyc_F01], (instregex "^CPY[^PMEF]")>; def : InstRW<[THX2T99Write_5Cyc_F01], (instregex "^DUP(i8|i16|i32|i64)$")>;
def : InstRW<[THX2T99Write_5Cyc_F01], (instregex "^DUPv.+gpr")>; def : InstRW<[THX2T99Write_5Cyc_F01], (instregex "^DUPv.+gpr")>;
// ASIMD extract // ASIMD extract
def : InstRW<[THX2T99Write_5Cyc_F01], (instregex "^EXTv")>; def : InstRW<[THX2T99Write_5Cyc_F01], (instregex "^EXTv")>;
// ASIMD extract narrow // ASIMD extract narrow
def : InstRW<[THX2T99Write_7Cyc_F01], (instregex "^XTNv")>; def : InstRW<[THX2T99Write_7Cyc_F01], (instregex "^XTNv")>;
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llvm/lib/Target/AArch64/AArch64SchedThunderX3T110.td

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// ASIMD count, D-form // ASIMD count, D-form
// ASIMD count, Q-form // ASIMD count, Q-form
def : InstRW<[THX3T110Write_3_4Cyc_F23_F0123], def : InstRW<[THX3T110Write_3_4Cyc_F23_F0123],
(instregex "^CLSv", "^CLZv", "^CNTv")>; (instregex "^CLSv", "^CLZv", "^CNTv")>;
// ASIMD duplicate, gen reg // ASIMD duplicate, gen reg
// ASIMD duplicate, element // ASIMD duplicate, element
def : InstRW<[THX3T110Write_5Cyc_F0123], (instregex "^DUPv")>; def : InstRW<[THX3T110Write_5Cyc_F0123], (instregex "^DUPv")>;
def : InstRW<[THX3T110Write_5Cyc_F0123], (instregex "^CPY[^PMEF]")>; def : InstRW<[THX3T110Write_5Cyc_F0123], (instregex "^DUP(i8|i16|i32|i64)$")>;
def : InstRW<[THX3T110Write_5Cyc_F0123], (instregex "^DUPv.+gpr")>; def : InstRW<[THX3T110Write_5Cyc_F0123], (instregex "^DUPv.+gpr")>;
// ASIMD extract // ASIMD extract
def : InstRW<[THX3T110Write_5Cyc_F0123], (instregex "^EXTv")>; def : InstRW<[THX3T110Write_5Cyc_F0123], (instregex "^EXTv")>;
// ASIMD extract narrow // ASIMD extract narrow
def : InstRW<[THX3T110Write_5Cyc_F0123], (instregex "^XTNv")>; def : InstRW<[THX3T110Write_5Cyc_F0123], (instregex "^XTNv")>;
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llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp

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} }
static bool getLaneCopyOpcode(unsigned &CopyOpc, unsigned &ExtractSubReg, static bool getLaneCopyOpcode(unsigned &CopyOpc, unsigned &ExtractSubReg,
const unsigned EltSize) { const unsigned EltSize) {
// Choose a lane copy opcode and subregister based off of the size of the // Choose a lane copy opcode and subregister based off of the size of the
// vector's elements. // vector's elements.
switch (EltSize) { switch (EltSize) {
case 8: case 8:
CopyOpc = AArch64::CPYi8; CopyOpc = AArch64::DUPi8;
ExtractSubReg = AArch64::bsub; ExtractSubReg = AArch64::bsub;
break; break;
case 16: case 16:
CopyOpc = AArch64::CPYi16; CopyOpc = AArch64::DUPi16;
ExtractSubReg = AArch64::hsub; ExtractSubReg = AArch64::hsub;
break; break;
case 32: case 32:
CopyOpc = AArch64::CPYi32; CopyOpc = AArch64::DUPi32;
ExtractSubReg = AArch64::ssub; ExtractSubReg = AArch64::ssub;
break; break;
case 64: case 64:
CopyOpc = AArch64::CPYi64; CopyOpc = AArch64::DUPi64;
ExtractSubReg = AArch64::dsub; ExtractSubReg = AArch64::dsub;
break; break;
default: default:
// Unknown size, bail out. // Unknown size, bail out.
LLVM_DEBUG(dbgs() << "Elt size '" << EltSize << "' unsupported.\n"); LLVM_DEBUG(dbgs() << "Elt size '" << EltSize << "' unsupported.\n");
return false; return false;
} }
return true; return true;
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llvm/test/CodeGen/AArch64/GlobalISel/contract-store.mir

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regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $x0, $x1 liveins: $x0, $x1
; CHECK-LABEL: name: contract_g_unmerge_values_first ; CHECK-LABEL: name: contract_g_unmerge_values_first
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK-NEXT: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY]], 0 :: (dereferenceable load (<2 x s64>)) ; CHECK-NEXT: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY]], 0 :: (dereferenceable load (<2 x s64>))
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY [[LDRQui]].dsub ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY [[LDRQui]].dsub
; CHECK-NEXT: [[CPYi64_:%[0-9]+]]:fpr64 = CPYi64 [[LDRQui]], 1 ; CHECK-NEXT: [[DUPi64_:%[0-9]+]]:fpr64 = DUPi64 [[LDRQui]], 1
; CHECK-NEXT: STRDui [[COPY1]], [[COPY]], 0 :: (store (s64)) ; CHECK-NEXT: STRDui [[COPY1]], [[COPY]], 0 :: (store (s64))
%0:gpr(p0) = COPY $x0 %0:gpr(p0) = COPY $x0
%1:fpr(<2 x s64>) = G_LOAD %0:gpr(p0) :: (dereferenceable load (<2 x s64>)) %1:fpr(<2 x s64>) = G_LOAD %0:gpr(p0) :: (dereferenceable load (<2 x s64>))
%2:fpr(s64), %3:fpr(s64) = G_UNMERGE_VALUES %1:fpr(<2 x s64>) %2:fpr(s64), %3:fpr(s64) = G_UNMERGE_VALUES %1:fpr(<2 x s64>)
%4:gpr(s64) = COPY %2 %4:gpr(s64) = COPY %2
%5:gpr(s64) = COPY %3 %5:gpr(s64) = COPY %3
G_STORE %4:gpr(s64), %0 :: (store (s64)) G_STORE %4:gpr(s64), %0 :: (store (s64))
... ...
--- ---
name: contract_g_unmerge_values_second name: contract_g_unmerge_values_second
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $x0, $x1 liveins: $x0, $x1
; CHECK-LABEL: name: contract_g_unmerge_values_second ; CHECK-LABEL: name: contract_g_unmerge_values_second
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK-NEXT: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY]], 0 :: (dereferenceable load (<2 x s64>)) ; CHECK-NEXT: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY]], 0 :: (dereferenceable load (<2 x s64>))
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY [[LDRQui]].dsub ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY [[LDRQui]].dsub
; CHECK-NEXT: [[CPYi64_:%[0-9]+]]:fpr64 = CPYi64 [[LDRQui]], 1 ; CHECK-NEXT: [[DUPi64_:%[0-9]+]]:fpr64 = DUPi64 [[LDRQui]], 1
; CHECK-NEXT: STRDui [[CPYi64_]], [[COPY]], 0 :: (store (s64)) ; CHECK-NEXT: STRDui [[DUPi64_]], [[COPY]], 0 :: (store (s64))
%0:gpr(p0) = COPY $x0 %0:gpr(p0) = COPY $x0
%1:fpr(<2 x s64>) = G_LOAD %0:gpr(p0) :: (dereferenceable load (<2 x s64>)) %1:fpr(<2 x s64>) = G_LOAD %0:gpr(p0) :: (dereferenceable load (<2 x s64>))
%2:fpr(s64), %3:fpr(s64) = G_UNMERGE_VALUES %1:fpr(<2 x s64>) %2:fpr(s64), %3:fpr(s64) = G_UNMERGE_VALUES %1:fpr(<2 x s64>)
%4:gpr(s64) = COPY %2 %4:gpr(s64) = COPY %2
%5:gpr(s64) = COPY %3 %5:gpr(s64) = COPY %3
G_STORE %5:gpr(s64), %0 :: (store (s64)) G_STORE %5:gpr(s64), %0 :: (store (s64))
... ...
--- ---
Show All 16 Lines

llvm/test/CodeGen/AArch64/GlobalISel/select-extract-vector-elt.mir

Show All 16 Lines bb.0:
liveins: $d0 liveins: $d0
; CHECK-LABEL: name: v2s32_fpr ; CHECK-LABEL: name: v2s32_fpr
; CHECK: liveins: $d0 ; CHECK: liveins: $d0
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.dsub ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.dsub
; CHECK-NEXT: [[CPYi32_:%[0-9]+]]:fpr32 = CPYi32 [[INSERT_SUBREG]], 1 ; CHECK-NEXT: [[DUPi32_:%[0-9]+]]:fpr32 = DUPi32 [[INSERT_SUBREG]], 1
; CHECK-NEXT: $s0 = COPY [[CPYi32_]] ; CHECK-NEXT: $s0 = COPY [[DUPi32_]]
; CHECK-NEXT: RET_ReallyLR implicit $s0 ; CHECK-NEXT: RET_ReallyLR implicit $s0
%0:fpr(<2 x s32>) = COPY $d0 %0:fpr(<2 x s32>) = COPY $d0
%2:gpr(s64) = G_CONSTANT i64 1 %2:gpr(s64) = G_CONSTANT i64 1
%3:fpr(s64) = COPY %2(s64) %3:fpr(s64) = COPY %2(s64)
%1:fpr(s32) = G_EXTRACT_VECTOR_ELT %0(<2 x s32>), %3(s64) %1:fpr(s32) = G_EXTRACT_VECTOR_ELT %0(<2 x s32>), %3(s64)
$s0 = COPY %1(s32) $s0 = COPY %1(s32)
RET_ReallyLR implicit $s0 RET_ReallyLR implicit $s0
Show All 36 Lines
body: | body: |
bb.0: bb.0:
liveins: $q0 liveins: $q0
; CHECK-LABEL: name: v2s64_fpr ; CHECK-LABEL: name: v2s64_fpr
; CHECK: liveins: $q0 ; CHECK: liveins: $q0
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
; CHECK-NEXT: [[CPYi64_:%[0-9]+]]:fpr64 = CPYi64 [[COPY]], 2 ; CHECK-NEXT: [[DUPi64_:%[0-9]+]]:fpr64 = DUPi64 [[COPY]], 2
; CHECK-NEXT: $d0 = COPY [[CPYi64_]] ; CHECK-NEXT: $d0 = COPY [[DUPi64_]]
; CHECK-NEXT: RET_ReallyLR implicit $d0 ; CHECK-NEXT: RET_ReallyLR implicit $d0
%0:fpr(<2 x s64>) = COPY $q0 %0:fpr(<2 x s64>) = COPY $q0
%2:gpr(s64) = G_CONSTANT i64 2 %2:gpr(s64) = G_CONSTANT i64 2
%3:fpr(s64) = COPY %2(s64) %3:fpr(s64) = COPY %2(s64)
%1:fpr(s64) = G_EXTRACT_VECTOR_ELT %0(<2 x s64>), %3(s64) %1:fpr(s64) = G_EXTRACT_VECTOR_ELT %0(<2 x s64>), %3(s64)
$d0 = COPY %1(s64) $d0 = COPY %1(s64)
RET_ReallyLR implicit $d0 RET_ReallyLR implicit $d0
Show All 14 Lines bb.0:
liveins: $d0 liveins: $d0
; CHECK-LABEL: name: v4s16_fpr ; CHECK-LABEL: name: v4s16_fpr
; CHECK: liveins: $d0 ; CHECK: liveins: $d0
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.dsub ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.dsub
; CHECK-NEXT: [[CPYi16_:%[0-9]+]]:fpr16 = CPYi16 [[INSERT_SUBREG]], 1 ; CHECK-NEXT: [[DUPi16_:%[0-9]+]]:fpr16 = DUPi16 [[INSERT_SUBREG]], 1
; CHECK-NEXT: $h0 = COPY [[CPYi16_]] ; CHECK-NEXT: $h0 = COPY [[DUPi16_]]
; CHECK-NEXT: RET_ReallyLR implicit $h0 ; CHECK-NEXT: RET_ReallyLR implicit $h0
%0:fpr(<4 x s16>) = COPY $d0 %0:fpr(<4 x s16>) = COPY $d0
%2:gpr(s64) = G_CONSTANT i64 1 %2:gpr(s64) = G_CONSTANT i64 1
%3:fpr(s64) = COPY %2(s64) %3:fpr(s64) = COPY %2(s64)
%1:fpr(s16) = G_EXTRACT_VECTOR_ELT %0(<4 x s16>), %3(s64) %1:fpr(s16) = G_EXTRACT_VECTOR_ELT %0(<4 x s16>), %3(s64)
$h0 = COPY %1(s16) $h0 = COPY %1(s16)
RET_ReallyLR implicit $h0 RET_ReallyLR implicit $h0
... ...
--- ---
name: v8s16_fpr name: v8s16_fpr
alignment: 4 alignment: 4
legalized: true legalized: true
regBankSelected: true regBankSelected: true
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
liveins: $q0 liveins: $q0
; CHECK-LABEL: name: v8s16_fpr ; CHECK-LABEL: name: v8s16_fpr
; CHECK: liveins: $q0 ; CHECK: liveins: $q0
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
; CHECK-NEXT: [[CPYi16_:%[0-9]+]]:fpr16 = CPYi16 [[COPY]], 1 ; CHECK-NEXT: [[DUPi16_:%[0-9]+]]:fpr16 = DUPi16 [[COPY]], 1
; CHECK-NEXT: $h0 = COPY [[CPYi16_]] ; CHECK-NEXT: $h0 = COPY [[DUPi16_]]
; CHECK-NEXT: RET_ReallyLR implicit $h0 ; CHECK-NEXT: RET_ReallyLR implicit $h0
%0:fpr(<8 x s16>) = COPY $q0 %0:fpr(<8 x s16>) = COPY $q0
%2:gpr(s64) = G_CONSTANT i64 1 %2:gpr(s64) = G_CONSTANT i64 1
%3:fpr(s64) = COPY %2(s64) %3:fpr(s64) = COPY %2(s64)
%1:fpr(s16) = G_EXTRACT_VECTOR_ELT %0(<8 x s16>), %3(s64) %1:fpr(s16) = G_EXTRACT_VECTOR_ELT %0(<8 x s16>), %3(s64)
$h0 = COPY %1(s16) $h0 = COPY %1(s16)
RET_ReallyLR implicit $h0 RET_ReallyLR implicit $h0
... ...
--- ---
name: v8s16_fpr_zext name: v8s16_fpr_zext
alignment: 4 alignment: 4
legalized: true legalized: true
regBankSelected: true regBankSelected: true
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
liveins: $q0 liveins: $q0
; CHECK-LABEL: name: v8s16_fpr_zext ; CHECK-LABEL: name: v8s16_fpr_zext
; CHECK: liveins: $q0 ; CHECK: liveins: $q0
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
; CHECK-NEXT: [[CPYi16_:%[0-9]+]]:fpr16 = CPYi16 [[COPY]], 1 ; CHECK-NEXT: [[DUPi16_:%[0-9]+]]:fpr16 = DUPi16 [[COPY]], 1
; CHECK-NEXT: $h0 = COPY [[CPYi16_]] ; CHECK-NEXT: $h0 = COPY [[DUPi16_]]
; CHECK-NEXT: RET_ReallyLR implicit $h0 ; CHECK-NEXT: RET_ReallyLR implicit $h0
%0:fpr(<8 x s16>) = COPY $q0 %0:fpr(<8 x s16>) = COPY $q0
%1:gpr(s32) = G_CONSTANT i32 1 %1:gpr(s32) = G_CONSTANT i32 1
%2:gpr(s64) = G_ZEXT %1 %2:gpr(s64) = G_ZEXT %1
%3:fpr(s64) = COPY %2(s64) %3:fpr(s64) = COPY %2(s64)
%4:fpr(s16) = G_EXTRACT_VECTOR_ELT %0(<8 x s16>), %3(s64) %4:fpr(s16) = G_EXTRACT_VECTOR_ELT %0(<8 x s16>), %3(s64)
$h0 = COPY %4(s16) $h0 = COPY %4(s16)
RET_ReallyLR implicit $h0 RET_ReallyLR implicit $h0
... ...
--- ---
name: v8s16_fpr_sext name: v8s16_fpr_sext
alignment: 4 alignment: 4
legalized: true legalized: true
regBankSelected: true regBankSelected: true
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
liveins: $q0 liveins: $q0
; CHECK-LABEL: name: v8s16_fpr_sext ; CHECK-LABEL: name: v8s16_fpr_sext
; CHECK: liveins: $q0 ; CHECK: liveins: $q0
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
; CHECK-NEXT: [[CPYi16_:%[0-9]+]]:fpr16 = CPYi16 [[COPY]], 1 ; CHECK-NEXT: [[DUPi16_:%[0-9]+]]:fpr16 = DUPi16 [[COPY]], 1
; CHECK-NEXT: $h0 = COPY [[CPYi16_]] ; CHECK-NEXT: $h0 = COPY [[DUPi16_]]
; CHECK-NEXT: RET_ReallyLR implicit $h0 ; CHECK-NEXT: RET_ReallyLR implicit $h0
%0:fpr(<8 x s16>) = COPY $q0 %0:fpr(<8 x s16>) = COPY $q0
%1:gpr(s32) = G_CONSTANT i32 1 %1:gpr(s32) = G_CONSTANT i32 1
%2:gpr(s64) = G_SEXT %1 %2:gpr(s64) = G_SEXT %1
%3:fpr(s64) = COPY %2(s64) %3:fpr(s64) = COPY %2(s64)
%4:fpr(s16) = G_EXTRACT_VECTOR_ELT %0(<8 x s16>), %3(s64) %4:fpr(s16) = G_EXTRACT_VECTOR_ELT %0(<8 x s16>), %3(s64)
$h0 = COPY %4(s16) $h0 = COPY %4(s16)
RET_ReallyLR implicit $h0 RET_ReallyLR implicit $h0
... ...
--- ---
name: v8s16_fpr_trunc name: v8s16_fpr_trunc
alignment: 4 alignment: 4
legalized: true legalized: true
regBankSelected: true regBankSelected: true
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
liveins: $q0 liveins: $q0
; CHECK-LABEL: name: v8s16_fpr_trunc ; CHECK-LABEL: name: v8s16_fpr_trunc
; CHECK: liveins: $q0 ; CHECK: liveins: $q0
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
; CHECK-NEXT: [[CPYi16_:%[0-9]+]]:fpr16 = CPYi16 [[COPY]], 1 ; CHECK-NEXT: [[DUPi16_:%[0-9]+]]:fpr16 = DUPi16 [[COPY]], 1
; CHECK-NEXT: $h0 = COPY [[CPYi16_]] ; CHECK-NEXT: $h0 = COPY [[DUPi16_]]
; CHECK-NEXT: RET_ReallyLR implicit $h0 ; CHECK-NEXT: RET_ReallyLR implicit $h0
%0:fpr(<8 x s16>) = COPY $q0 %0:fpr(<8 x s16>) = COPY $q0
%1:gpr(s64) = G_CONSTANT i64 1 %1:gpr(s64) = G_CONSTANT i64 1
%2:gpr(s32) = G_TRUNC %1 %2:gpr(s32) = G_TRUNC %1
%3:gpr(s64) = G_SEXT %2 %3:gpr(s64) = G_SEXT %2
%4:fpr(s64) = COPY %3(s64) %4:fpr(s64) = COPY %3(s64)
%5:fpr(s16) = G_EXTRACT_VECTOR_ELT %0(<8 x s16>), %4(s64) %5:fpr(s16) = G_EXTRACT_VECTOR_ELT %0(<8 x s16>), %4(s64)
$h0 = COPY %5(s16) $h0 = COPY %5(s16)
▲ Show 20 Lines • Show All 66 Lines • ▼ Show 20 Lines
body: | body: |
bb.0: bb.0:
liveins: $q0 liveins: $q0
; CHECK-LABEL: name: v2p0 ; CHECK-LABEL: name: v2p0
; CHECK: liveins: $q0 ; CHECK: liveins: $q0
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
; CHECK-NEXT: [[CPYi64_:%[0-9]+]]:fpr64 = CPYi64 [[COPY]], 1 ; CHECK-NEXT: [[DUPi64_:%[0-9]+]]:fpr64 = DUPi64 [[COPY]], 1
; CHECK-NEXT: $d0 = COPY [[CPYi64_]] ; CHECK-NEXT: $d0 = COPY [[DUPi64_]]
; CHECK-NEXT: RET_ReallyLR implicit $d0 ; CHECK-NEXT: RET_ReallyLR implicit $d0
%0:fpr(<2 x p0>) = COPY $q0 %0:fpr(<2 x p0>) = COPY $q0
%2:gpr(s64) = G_CONSTANT i64 1 %2:gpr(s64) = G_CONSTANT i64 1
%1:fpr(p0) = G_EXTRACT_VECTOR_ELT %0(<2 x p0>), %2(s64) %1:fpr(p0) = G_EXTRACT_VECTOR_ELT %0(<2 x p0>), %2(s64)
$d0 = COPY %1(p0) $d0 = COPY %1(p0)
RET_ReallyLR implicit $d0 RET_ReallyLR implicit $d0
... ...

llvm/test/CodeGen/AArch64/GlobalISel/select-extract.mir

Show All 9 Linesbody: |
bb.0: bb.0:
liveins: $q0 liveins: $q0
; CHECK-LABEL: name: extract_64_128 ; CHECK-LABEL: name: extract_64_128
; CHECK: liveins: $q0 ; CHECK: liveins: $q0
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY [[COPY]].dsub ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY [[COPY]].dsub
; CHECK-NEXT: [[CPYi64_:%[0-9]+]]:fpr64 = CPYi64 [[COPY]], 1 ; CHECK-NEXT: [[DUPi64_:%[0-9]+]]:fpr64 = DUPi64 [[COPY]], 1
; CHECK-NEXT: $d3 = COPY [[COPY1]] ; CHECK-NEXT: $d3 = COPY [[COPY1]]
; CHECK-NEXT: $d4 = COPY [[CPYi64_]] ; CHECK-NEXT: $d4 = COPY [[DUPi64_]]
; CHECK-NEXT: RET_ReallyLR implicit $d3 ; CHECK-NEXT: RET_ReallyLR implicit $d3
%0:fpr(s128) = COPY $q0 %0:fpr(s128) = COPY $q0
%2:fpr(s64) = G_EXTRACT %0(s128), 0 %2:fpr(s64) = G_EXTRACT %0(s128), 0
%3:fpr(s64) = G_EXTRACT %0(s128), 64 %3:fpr(s64) = G_EXTRACT %0(s128), 64
$d3 = COPY %2(s64) $d3 = COPY %2(s64)
$d4 = COPY %3(s64) $d4 = COPY %3(s64)
RET_ReallyLR implicit $d3 RET_ReallyLR implicit $d3
... ...

llvm/test/CodeGen/AArch64/GlobalISel/select-frint-nofp16.mir

Show First 20 Lines • Show All 46 Lines • ▼ Show 20 Lines bb.0:
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.dsub ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.dsub
; CHECK-NEXT: [[DEF1:%[0-9]+]]:fpr128 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF1:%[0-9]+]]:fpr128 = IMPLICIT_DEF
; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF1]], [[COPY]], %subreg.dsub ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF1]], [[COPY]], %subreg.dsub
; CHECK-NEXT: [[DEF2:%[0-9]+]]:fpr128 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF2:%[0-9]+]]:fpr128 = IMPLICIT_DEF
; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF2]], [[COPY]], %subreg.dsub ; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF2]], [[COPY]], %subreg.dsub
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY [[INSERT_SUBREG]].hsub ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY [[INSERT_SUBREG]].hsub
; CHECK-NEXT: [[CPYi16_:%[0-9]+]]:fpr16 = CPYi16 [[INSERT_SUBREG]], 1 ; CHECK-NEXT: [[DUPi16_:%[0-9]+]]:fpr16 = DUPi16 [[INSERT_SUBREG]], 1
; CHECK-NEXT: [[CPYi16_1:%[0-9]+]]:fpr16 = CPYi16 [[INSERT_SUBREG1]], 2 ; CHECK-NEXT: [[DUPi16_1:%[0-9]+]]:fpr16 = DUPi16 [[INSERT_SUBREG1]], 2
; CHECK-NEXT: [[CPYi16_2:%[0-9]+]]:fpr16 = CPYi16 [[INSERT_SUBREG2]], 3 ; CHECK-NEXT: [[DUPi16_2:%[0-9]+]]:fpr16 = DUPi16 [[INSERT_SUBREG2]], 3
; CHECK-NEXT: [[FCVTSHr:%[0-9]+]]:fpr32 = FCVTSHr [[COPY1]] ; CHECK-NEXT: [[FCVTSHr:%[0-9]+]]:fpr32 = FCVTSHr [[COPY1]]
; CHECK-NEXT: [[FRINTXSr:%[0-9]+]]:fpr32 = FRINTXSr [[FCVTSHr]] ; CHECK-NEXT: [[FRINTXSr:%[0-9]+]]:fpr32 = FRINTXSr [[FCVTSHr]]
; CHECK-NEXT: [[FCVTHSr:%[0-9]+]]:fpr16 = FCVTHSr [[FRINTXSr]] ; CHECK-NEXT: [[FCVTHSr:%[0-9]+]]:fpr16 = FCVTHSr [[FRINTXSr]]
; CHECK-NEXT: [[FCVTSHr1:%[0-9]+]]:fpr32 = FCVTSHr [[CPYi16_]] ; CHECK-NEXT: [[FCVTSHr1:%[0-9]+]]:fpr32 = FCVTSHr [[DUPi16_]]
; CHECK-NEXT: [[FRINTXSr1:%[0-9]+]]:fpr32 = FRINTXSr [[FCVTSHr1]] ; CHECK-NEXT: [[FRINTXSr1:%[0-9]+]]:fpr32 = FRINTXSr [[FCVTSHr1]]
; CHECK-NEXT: [[FCVTHSr1:%[0-9]+]]:fpr16 = FCVTHSr [[FRINTXSr1]] ; CHECK-NEXT: [[FCVTHSr1:%[0-9]+]]:fpr16 = FCVTHSr [[FRINTXSr1]]
; CHECK-NEXT: [[FCVTSHr2:%[0-9]+]]:fpr32 = FCVTSHr [[CPYi16_1]] ; CHECK-NEXT: [[FCVTSHr2:%[0-9]+]]:fpr32 = FCVTSHr [[DUPi16_1]]
; CHECK-NEXT: [[FRINTXSr2:%[0-9]+]]:fpr32 = FRINTXSr [[FCVTSHr2]] ; CHECK-NEXT: [[FRINTXSr2:%[0-9]+]]:fpr32 = FRINTXSr [[FCVTSHr2]]
; CHECK-NEXT: [[FCVTHSr2:%[0-9]+]]:fpr16 = FCVTHSr [[FRINTXSr2]] ; CHECK-NEXT: [[FCVTHSr2:%[0-9]+]]:fpr16 = FCVTHSr [[FRINTXSr2]]
; CHECK-NEXT: [[FCVTSHr3:%[0-9]+]]:fpr32 = FCVTSHr [[CPYi16_2]] ; CHECK-NEXT: [[FCVTSHr3:%[0-9]+]]:fpr32 = FCVTSHr [[DUPi16_2]]
; CHECK-NEXT: [[FRINTXSr3:%[0-9]+]]:fpr32 = FRINTXSr [[FCVTSHr3]] ; CHECK-NEXT: [[FRINTXSr3:%[0-9]+]]:fpr32 = FRINTXSr [[FCVTSHr3]]
; CHECK-NEXT: [[FCVTHSr3:%[0-9]+]]:fpr16 = FCVTHSr [[FRINTXSr3]] ; CHECK-NEXT: [[FCVTHSr3:%[0-9]+]]:fpr16 = FCVTHSr [[FRINTXSr3]]
; CHECK-NEXT: [[DEF3:%[0-9]+]]:fpr128 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF3:%[0-9]+]]:fpr128 = IMPLICIT_DEF
; CHECK-NEXT: [[INSERT_SUBREG3:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF3]], [[FCVTHSr]], %subreg.hsub ; CHECK-NEXT: [[INSERT_SUBREG3:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF3]], [[FCVTHSr]], %subreg.hsub
; CHECK-NEXT: [[DEF4:%[0-9]+]]:fpr128 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF4:%[0-9]+]]:fpr128 = IMPLICIT_DEF
; CHECK-NEXT: [[INSERT_SUBREG4:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF4]], [[FCVTHSr1]], %subreg.hsub ; CHECK-NEXT: [[INSERT_SUBREG4:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF4]], [[FCVTHSr1]], %subreg.hsub
; CHECK-NEXT: [[INSvi16lane:%[0-9]+]]:fpr128 = INSvi16lane [[INSERT_SUBREG3]], 1, [[INSERT_SUBREG4]], 0 ; CHECK-NEXT: [[INSvi16lane:%[0-9]+]]:fpr128 = INSvi16lane [[INSERT_SUBREG3]], 1, [[INSERT_SUBREG4]], 0
; CHECK-NEXT: [[DEF5:%[0-9]+]]:fpr128 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF5:%[0-9]+]]:fpr128 = IMPLICIT_DEF
Show All 35 Linesbody: |
bb.0: bb.0:
liveins: $q0 liveins: $q0
; CHECK-LABEL: name: test_v8f16.rint ; CHECK-LABEL: name: test_v8f16.rint
; CHECK: liveins: $q0 ; CHECK: liveins: $q0
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY [[COPY]].hsub ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY [[COPY]].hsub
; CHECK-NEXT: [[CPYi16_:%[0-9]+]]:fpr16 = CPYi16 [[COPY]], 1 ; CHECK-NEXT: [[DUPi16_:%[0-9]+]]:fpr16 = DUPi16 [[COPY]], 1
; CHECK-NEXT: [[CPYi16_1:%[0-9]+]]:fpr16 = CPYi16 [[COPY]], 2 ; CHECK-NEXT: [[DUPi16_1:%[0-9]+]]:fpr16 = DUPi16 [[COPY]], 2
; CHECK-NEXT: [[CPYi16_2:%[0-9]+]]:fpr16 = CPYi16 [[COPY]], 3 ; CHECK-NEXT: [[DUPi16_2:%[0-9]+]]:fpr16 = DUPi16 [[COPY]], 3
; CHECK-NEXT: [[CPYi16_3:%[0-9]+]]:fpr16 = CPYi16 [[COPY]], 4 ; CHECK-NEXT: [[DUPi16_3:%[0-9]+]]:fpr16 = DUPi16 [[COPY]], 4
; CHECK-NEXT: [[CPYi16_4:%[0-9]+]]:fpr16 = CPYi16 [[COPY]], 5 ; CHECK-NEXT: [[DUPi16_4:%[0-9]+]]:fpr16 = DUPi16 [[COPY]], 5
; CHECK-NEXT: [[CPYi16_5:%[0-9]+]]:fpr16 = CPYi16 [[COPY]], 6 ; CHECK-NEXT: [[DUPi16_5:%[0-9]+]]:fpr16 = DUPi16 [[COPY]], 6
; CHECK-NEXT: [[CPYi16_6:%[0-9]+]]:fpr16 = CPYi16 [[COPY]], 7 ; CHECK-NEXT: [[DUPi16_6:%[0-9]+]]:fpr16 = DUPi16 [[COPY]], 7
; CHECK-NEXT: [[FCVTSHr:%[0-9]+]]:fpr32 = FCVTSHr [[COPY1]] ; CHECK-NEXT: [[FCVTSHr:%[0-9]+]]:fpr32 = FCVTSHr [[COPY1]]
; CHECK-NEXT: [[FRINTXSr:%[0-9]+]]:fpr32 = FRINTXSr [[FCVTSHr]] ; CHECK-NEXT: [[FRINTXSr:%[0-9]+]]:fpr32 = FRINTXSr [[FCVTSHr]]
; CHECK-NEXT: [[FCVTHSr:%[0-9]+]]:fpr16 = FCVTHSr [[FRINTXSr]] ; CHECK-NEXT: [[FCVTHSr:%[0-9]+]]:fpr16 = FCVTHSr [[FRINTXSr]]
; CHECK-NEXT: [[FCVTSHr1:%[0-9]+]]:fpr32 = FCVTSHr [[CPYi16_]] ; CHECK-NEXT: [[FCVTSHr1:%[0-9]+]]:fpr32 = FCVTSHr [[DUPi16_]]
; CHECK-NEXT: [[FRINTXSr1:%[0-9]+]]:fpr32 = FRINTXSr [[FCVTSHr1]] ; CHECK-NEXT: [[FRINTXSr1:%[0-9]+]]:fpr32 = FRINTXSr [[FCVTSHr1]]
; CHECK-NEXT: [[FCVTHSr1:%[0-9]+]]:fpr16 = FCVTHSr [[FRINTXSr1]] ; CHECK-NEXT: [[FCVTHSr1:%[0-9]+]]:fpr16 = FCVTHSr [[FRINTXSr1]]
; CHECK-NEXT: [[FCVTSHr2:%[0-9]+]]:fpr32 = FCVTSHr [[CPYi16_1]] ; CHECK-NEXT: [[FCVTSHr2:%[0-9]+]]:fpr32 = FCVTSHr [[DUPi16_1]]
; CHECK-NEXT: [[FRINTXSr2:%[0-9]+]]:fpr32 = FRINTXSr [[FCVTSHr2]] ; CHECK-NEXT: [[FRINTXSr2:%[0-9]+]]:fpr32 = FRINTXSr [[FCVTSHr2]]
; CHECK-NEXT: [[FCVTHSr2:%[0-9]+]]:fpr16 = FCVTHSr [[FRINTXSr2]] ; CHECK-NEXT: [[FCVTHSr2:%[0-9]+]]:fpr16 = FCVTHSr [[FRINTXSr2]]
; CHECK-NEXT: [[FCVTSHr3:%[0-9]+]]:fpr32 = FCVTSHr [[CPYi16_2]] ; CHECK-NEXT: [[FCVTSHr3:%[0-9]+]]:fpr32 = FCVTSHr [[DUPi16_2]]
; CHECK-NEXT: [[FRINTXSr3:%[0-9]+]]:fpr32 = FRINTXSr [[FCVTSHr3]] ; CHECK-NEXT: [[FRINTXSr3:%[0-9]+]]:fpr32 = FRINTXSr [[FCVTSHr3]]
; CHECK-NEXT: [[FCVTHSr3:%[0-9]+]]:fpr16 = FCVTHSr [[FRINTXSr3]] ; CHECK-NEXT: [[FCVTHSr3:%[0-9]+]]:fpr16 = FCVTHSr [[FRINTXSr3]]
; CHECK-NEXT: [[FCVTSHr4:%[0-9]+]]:fpr32 = FCVTSHr [[CPYi16_3]] ; CHECK-NEXT: [[FCVTSHr4:%[0-9]+]]:fpr32 = FCVTSHr [[DUPi16_3]]
; CHECK-NEXT: [[FRINTXSr4:%[0-9]+]]:fpr32 = FRINTXSr [[FCVTSHr4]] ; CHECK-NEXT: [[FRINTXSr4:%[0-9]+]]:fpr32 = FRINTXSr [[FCVTSHr4]]
; CHECK-NEXT: [[FCVTHSr4:%[0-9]+]]:fpr16 = FCVTHSr [[FRINTXSr4]] ; CHECK-NEXT: [[FCVTHSr4:%[0-9]+]]:fpr16 = FCVTHSr [[FRINTXSr4]]
; CHECK-NEXT: [[FCVTSHr5:%[0-9]+]]:fpr32 = FCVTSHr [[CPYi16_4]] ; CHECK-NEXT: [[FCVTSHr5:%[0-9]+]]:fpr32 = FCVTSHr [[DUPi16_4]]
; CHECK-NEXT: [[FRINTXSr5:%[0-9]+]]:fpr32 = FRINTXSr [[FCVTSHr5]] ; CHECK-NEXT: [[FRINTXSr5:%[0-9]+]]:fpr32 = FRINTXSr [[FCVTSHr5]]
; CHECK-NEXT: [[FCVTHSr5:%[0-9]+]]:fpr16 = FCVTHSr [[FRINTXSr5]] ; CHECK-NEXT: [[FCVTHSr5:%[0-9]+]]:fpr16 = FCVTHSr [[FRINTXSr5]]
; CHECK-NEXT: [[FCVTSHr6:%[0-9]+]]:fpr32 = FCVTSHr [[CPYi16_5]] ; CHECK-NEXT: [[FCVTSHr6:%[0-9]+]]:fpr32 = FCVTSHr [[DUPi16_5]]
; CHECK-NEXT: [[FRINTXSr6:%[0-9]+]]:fpr32 = FRINTXSr [[FCVTSHr6]] ; CHECK-NEXT: [[FRINTXSr6:%[0-9]+]]:fpr32 = FRINTXSr [[FCVTSHr6]]
; CHECK-NEXT: [[FCVTHSr6:%[0-9]+]]:fpr16 = FCVTHSr [[FRINTXSr6]] ; CHECK-NEXT: [[FCVTHSr6:%[0-9]+]]:fpr16 = FCVTHSr [[FRINTXSr6]]
; CHECK-NEXT: [[FCVTSHr7:%[0-9]+]]:fpr32 = FCVTSHr [[CPYi16_6]] ; CHECK-NEXT: [[FCVTSHr7:%[0-9]+]]:fpr32 = FCVTSHr [[DUPi16_6]]
; CHECK-NEXT: [[FRINTXSr7:%[0-9]+]]:fpr32 = FRINTXSr [[FCVTSHr7]] ; CHECK-NEXT: [[FRINTXSr7:%[0-9]+]]:fpr32 = FRINTXSr [[FCVTSHr7]]
; CHECK-NEXT: [[FCVTHSr7:%[0-9]+]]:fpr16 = FCVTHSr [[FRINTXSr7]] ; CHECK-NEXT: [[FCVTHSr7:%[0-9]+]]:fpr16 = FCVTHSr [[FRINTXSr7]]
; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[FCVTHSr]], %subreg.hsub ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[FCVTHSr]], %subreg.hsub
; CHECK-NEXT: [[DEF1:%[0-9]+]]:fpr128 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF1:%[0-9]+]]:fpr128 = IMPLICIT_DEF
; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF1]], [[FCVTHSr1]], %subreg.hsub ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF1]], [[FCVTHSr1]], %subreg.hsub
; CHECK-NEXT: [[INSvi16lane:%[0-9]+]]:fpr128 = INSvi16lane [[INSERT_SUBREG]], 1, [[INSERT_SUBREG1]], 0 ; CHECK-NEXT: [[INSvi16lane:%[0-9]+]]:fpr128 = INSvi16lane [[INSERT_SUBREG]], 1, [[INSERT_SUBREG1]], 0
; CHECK-NEXT: [[DEF2:%[0-9]+]]:fpr128 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF2:%[0-9]+]]:fpr128 = IMPLICIT_DEF
▲ Show 20 Lines • Show All 48 Lines • Show Last 20 Lines

llvm/test/CodeGen/AArch64/GlobalISel/select-unmerge.mir

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body: | body: |
bb.1: bb.1:
liveins: $q0 liveins: $q0
; CHECK-LABEL: name: test_v2s64_unmerge ; CHECK-LABEL: name: test_v2s64_unmerge
; CHECK: liveins: $q0 ; CHECK: liveins: $q0
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY [[COPY]].dsub ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY [[COPY]].dsub
; CHECK-NEXT: [[CPYi64_:%[0-9]+]]:fpr64 = CPYi64 [[COPY]], 1 ; CHECK-NEXT: [[DUPi64_:%[0-9]+]]:fpr64 = DUPi64 [[COPY]], 1
; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY1]], %subreg.dsub ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY1]], %subreg.dsub
; CHECK-NEXT: [[DEF1:%[0-9]+]]:fpr128 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF1:%[0-9]+]]:fpr128 = IMPLICIT_DEF
; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF1]], [[CPYi64_]], %subreg.dsub ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF1]], [[DUPi64_]], %subreg.dsub
; CHECK-NEXT: [[INSvi64lane:%[0-9]+]]:fpr128 = INSvi64lane [[INSERT_SUBREG]], 1, [[INSERT_SUBREG1]], 0 ; CHECK-NEXT: [[INSvi64lane:%[0-9]+]]:fpr128 = INSvi64lane [[INSERT_SUBREG]], 1, [[INSERT_SUBREG1]], 0
; CHECK-NEXT: $q0 = COPY [[INSvi64lane]] ; CHECK-NEXT: $q0 = COPY [[INSvi64lane]]
; CHECK-NEXT: RET_ReallyLR implicit $q0 ; CHECK-NEXT: RET_ReallyLR implicit $q0
%0:fpr(<2 x s64>) = COPY $q0 %0:fpr(<2 x s64>) = COPY $q0
; Since 2 * 64 = 128, we can just directly copy. ; Since 2 * 64 = 128, we can just directly copy.
%2:fpr(s64), %3:fpr(s64) = G_UNMERGE_VALUES %0(<2 x s64>) %2:fpr(s64), %3:fpr(s64) = G_UNMERGE_VALUES %0(<2 x s64>)
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body: | body: |
bb.1: bb.1:
liveins: $q0 liveins: $q0
; CHECK-LABEL: name: test_v4s32_unmerge ; CHECK-LABEL: name: test_v4s32_unmerge
; CHECK: liveins: $q0 ; CHECK: liveins: $q0
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY [[COPY]].ssub ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY [[COPY]].ssub
; CHECK-NEXT: [[CPYi32_:%[0-9]+]]:fpr32 = CPYi32 [[COPY]], 1 ; CHECK-NEXT: [[DUPi32_:%[0-9]+]]:fpr32 = DUPi32 [[COPY]], 1
; CHECK-NEXT: [[CPYi32_1:%[0-9]+]]:fpr32 = CPYi32 [[COPY]], 2 ; CHECK-NEXT: [[DUPi32_1:%[0-9]+]]:fpr32 = DUPi32 [[COPY]], 2
; CHECK-NEXT: [[CPYi32_2:%[0-9]+]]:fpr32 = CPYi32 [[COPY]], 3 ; CHECK-NEXT: [[DUPi32_2:%[0-9]+]]:fpr32 = DUPi32 [[COPY]], 3
; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY1]], %subreg.ssub ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY1]], %subreg.ssub
; CHECK-NEXT: [[DEF1:%[0-9]+]]:fpr128 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF1:%[0-9]+]]:fpr128 = IMPLICIT_DEF
; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF1]], [[CPYi32_]], %subreg.ssub ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF1]], [[DUPi32_]], %subreg.ssub
; CHECK-NEXT: [[INSvi32lane:%[0-9]+]]:fpr128 = INSvi32lane [[INSERT_SUBREG]], 1, [[INSERT_SUBREG1]], 0 ; CHECK-NEXT: [[INSvi32lane:%[0-9]+]]:fpr128 = INSvi32lane [[INSERT_SUBREG]], 1, [[INSERT_SUBREG1]], 0
; CHECK-NEXT: [[DEF2:%[0-9]+]]:fpr128 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF2:%[0-9]+]]:fpr128 = IMPLICIT_DEF
; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF2]], [[CPYi32_1]], %subreg.ssub ; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF2]], [[DUPi32_1]], %subreg.ssub
; CHECK-NEXT: [[INSvi32lane1:%[0-9]+]]:fpr128 = INSvi32lane [[INSvi32lane]], 2, [[INSERT_SUBREG2]], 0 ; CHECK-NEXT: [[INSvi32lane1:%[0-9]+]]:fpr128 = INSvi32lane [[INSvi32lane]], 2, [[INSERT_SUBREG2]], 0
; CHECK-NEXT: [[DEF3:%[0-9]+]]:fpr128 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF3:%[0-9]+]]:fpr128 = IMPLICIT_DEF
; CHECK-NEXT: [[INSERT_SUBREG3:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF3]], [[CPYi32_2]], %subreg.ssub ; CHECK-NEXT: [[INSERT_SUBREG3:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF3]], [[DUPi32_2]], %subreg.ssub
; CHECK-NEXT: [[INSvi32lane2:%[0-9]+]]:fpr128 = INSvi32lane [[INSvi32lane1]], 3, [[INSERT_SUBREG3]], 0 ; CHECK-NEXT: [[INSvi32lane2:%[0-9]+]]:fpr128 = INSvi32lane [[INSvi32lane1]], 3, [[INSERT_SUBREG3]], 0
; CHECK-NEXT: $q0 = COPY [[INSvi32lane2]] ; CHECK-NEXT: $q0 = COPY [[INSvi32lane2]]
; CHECK-NEXT: RET_ReallyLR implicit $q0 ; CHECK-NEXT: RET_ReallyLR implicit $q0
%0:fpr(<4 x s32>) = COPY $q0 %0:fpr(<4 x s32>) = COPY $q0
; Since 4 * 32 = 128, we can just directly copy. ; Since 4 * 32 = 128, we can just directly copy.
%2:fpr(s32), %3:fpr(s32), %4:fpr(s32), %5:fpr(s32) = G_UNMERGE_VALUES %0(<4 x s32>) %2:fpr(s32), %3:fpr(s32), %4:fpr(s32), %5:fpr(s32) = G_UNMERGE_VALUES %0(<4 x s32>)
Show All 19 Lines bb.1:
; CHECK-LABEL: name: test_v2s16_unmerge ; CHECK-LABEL: name: test_v2s16_unmerge
; CHECK: liveins: $s0 ; CHECK: liveins: $s0
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $s0 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.ssub ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.ssub
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY [[INSERT_SUBREG]].hsub ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY [[INSERT_SUBREG]].hsub
; CHECK-NEXT: [[CPYi16_:%[0-9]+]]:fpr16 = CPYi16 [[INSERT_SUBREG]], 1 ; CHECK-NEXT: [[DUPi16_:%[0-9]+]]:fpr16 = DUPi16 [[INSERT_SUBREG]], 1
; CHECK-NEXT: [[DEF1:%[0-9]+]]:fpr128 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF1:%[0-9]+]]:fpr128 = IMPLICIT_DEF
; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF1]], [[COPY1]], %subreg.hsub ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF1]], [[COPY1]], %subreg.hsub
; CHECK-NEXT: [[DEF2:%[0-9]+]]:fpr128 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF2:%[0-9]+]]:fpr128 = IMPLICIT_DEF
; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF2]], [[CPYi16_]], %subreg.hsub ; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF2]], [[DUPi16_]], %subreg.hsub
; CHECK-NEXT: [[INSvi16lane:%[0-9]+]]:fpr128 = INSvi16lane [[INSERT_SUBREG1]], 1, [[INSERT_SUBREG2]], 0 ; CHECK-NEXT: [[INSvi16lane:%[0-9]+]]:fpr128 = INSvi16lane [[INSERT_SUBREG1]], 1, [[INSERT_SUBREG2]], 0
; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr32 = COPY [[INSvi16lane]].ssub ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr32 = COPY [[INSvi16lane]].ssub
; CHECK-NEXT: $s0 = COPY [[COPY2]] ; CHECK-NEXT: $s0 = COPY [[COPY2]]
; CHECK-NEXT: RET_ReallyLR implicit $s0 ; CHECK-NEXT: RET_ReallyLR implicit $s0
%0:fpr(<2 x s16>) = COPY $s0 %0:fpr(<2 x s16>) = COPY $s0
; Since 2 * 16 != 128, we need to widen using implicit defs. ; Since 2 * 16 != 128, we need to widen using implicit defs.
; Note that we expect to reuse one of the INSERT_SUBREG results, as CPYi16 ; Note that we expect to reuse one of the INSERT_SUBREG results, as CPYi16
Show All 28 Lines bb.1:
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.dsub ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.dsub
; CHECK-NEXT: [[DEF1:%[0-9]+]]:fpr128 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF1:%[0-9]+]]:fpr128 = IMPLICIT_DEF
; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF1]], [[COPY]], %subreg.dsub ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF1]], [[COPY]], %subreg.dsub
; CHECK-NEXT: [[DEF2:%[0-9]+]]:fpr128 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF2:%[0-9]+]]:fpr128 = IMPLICIT_DEF
; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF2]], [[COPY]], %subreg.dsub ; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF2]], [[COPY]], %subreg.dsub
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY [[INSERT_SUBREG]].hsub ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY [[INSERT_SUBREG]].hsub
; CHECK-NEXT: [[CPYi16_:%[0-9]+]]:fpr16 = CPYi16 [[INSERT_SUBREG]], 1 ; CHECK-NEXT: [[DUPi16_:%[0-9]+]]:fpr16 = DUPi16 [[INSERT_SUBREG]], 1
; CHECK-NEXT: [[CPYi16_1:%[0-9]+]]:fpr16 = CPYi16 [[INSERT_SUBREG1]], 2 ; CHECK-NEXT: [[DUPi16_1:%[0-9]+]]:fpr16 = DUPi16 [[INSERT_SUBREG1]], 2
; CHECK-NEXT: [[CPYi16_2:%[0-9]+]]:fpr16 = CPYi16 [[INSERT_SUBREG2]], 3 ; CHECK-NEXT: [[DUPi16_2:%[0-9]+]]:fpr16 = DUPi16 [[INSERT_SUBREG2]], 3
; CHECK-NEXT: [[DEF3:%[0-9]+]]:fpr128 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF3:%[0-9]+]]:fpr128 = IMPLICIT_DEF
; CHECK-NEXT: [[INSERT_SUBREG3:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF3]], [[COPY1]], %subreg.hsub ; CHECK-NEXT: [[INSERT_SUBREG3:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF3]], [[COPY1]], %subreg.hsub
; CHECK-NEXT: [[DEF4:%[0-9]+]]:fpr128 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF4:%[0-9]+]]:fpr128 = IMPLICIT_DEF
; CHECK-NEXT: [[INSERT_SUBREG4:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF4]], [[CPYi16_]], %subreg.hsub ; CHECK-NEXT: [[INSERT_SUBREG4:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF4]], [[DUPi16_]], %subreg.hsub
; CHECK-NEXT: [[INSvi16lane:%[0-9]+]]:fpr128 = INSvi16lane [[INSERT_SUBREG3]], 1, [[INSERT_SUBREG4]], 0 ; CHECK-NEXT: [[INSvi16lane:%[0-9]+]]:fpr128 = INSvi16lane [[INSERT_SUBREG3]], 1, [[INSERT_SUBREG4]], 0
; CHECK-NEXT: [[DEF5:%[0-9]+]]:fpr128 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF5:%[0-9]+]]:fpr128 = IMPLICIT_DEF
; CHECK-NEXT: [[INSERT_SUBREG5:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF5]], [[CPYi16_1]], %subreg.hsub ; CHECK-NEXT: [[INSERT_SUBREG5:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF5]], [[DUPi16_1]], %subreg.hsub
; CHECK-NEXT: [[INSvi16lane1:%[0-9]+]]:fpr128 = INSvi16lane [[INSvi16lane]], 2, [[INSERT_SUBREG5]], 0 ; CHECK-NEXT: [[INSvi16lane1:%[0-9]+]]:fpr128 = INSvi16lane [[INSvi16lane]], 2, [[INSERT_SUBREG5]], 0
; CHECK-NEXT: [[DEF6:%[0-9]+]]:fpr128 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF6:%[0-9]+]]:fpr128 = IMPLICIT_DEF
; CHECK-NEXT: [[INSERT_SUBREG6:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF6]], [[CPYi16_2]], %subreg.hsub ; CHECK-NEXT: [[INSERT_SUBREG6:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF6]], [[DUPi16_2]], %subreg.hsub
; CHECK-NEXT: [[INSvi16lane2:%[0-9]+]]:fpr128 = INSvi16lane [[INSvi16lane1]], 3, [[INSERT_SUBREG6]], 0 ; CHECK-NEXT: [[INSvi16lane2:%[0-9]+]]:fpr128 = INSvi16lane [[INSvi16lane1]], 3, [[INSERT_SUBREG6]], 0
; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY [[INSvi16lane2]].dsub ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY [[INSvi16lane2]].dsub
; CHECK-NEXT: $d0 = COPY [[COPY2]] ; CHECK-NEXT: $d0 = COPY [[COPY2]]
; CHECK-NEXT: RET_ReallyLR implicit $d0 ; CHECK-NEXT: RET_ReallyLR implicit $d0
%0:fpr(<4 x s16>) = COPY $d0 %0:fpr(<4 x s16>) = COPY $d0
; Since 4 * 16 != 128, we need to widen using implicit defs. ; Since 4 * 16 != 128, we need to widen using implicit defs.
; Note that we expect to reuse one of the INSERT_SUBREG results, as CPYi16 ; Note that we expect to reuse one of the INSERT_SUBREG results, as CPYi16
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body: | body: |
bb.1: bb.1:
liveins: $q0 liveins: $q0
; CHECK-LABEL: name: test_v8s16_unmerge ; CHECK-LABEL: name: test_v8s16_unmerge
; CHECK: liveins: $q0 ; CHECK: liveins: $q0
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY [[COPY]].hsub ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY [[COPY]].hsub
; CHECK-NEXT: [[CPYi16_:%[0-9]+]]:fpr16 = CPYi16 [[COPY]], 1 ; CHECK-NEXT: [[DUPi16_:%[0-9]+]]:fpr16 = DUPi16 [[COPY]], 1
; CHECK-NEXT: [[CPYi16_1:%[0-9]+]]:fpr16 = CPYi16 [[COPY]], 2 ; CHECK-NEXT: [[DUPi16_1:%[0-9]+]]:fpr16 = DUPi16 [[COPY]], 2
; CHECK-NEXT: [[CPYi16_2:%[0-9]+]]:fpr16 = CPYi16 [[COPY]], 3 ; CHECK-NEXT: [[DUPi16_2:%[0-9]+]]:fpr16 = DUPi16 [[COPY]], 3
; CHECK-NEXT: [[CPYi16_3:%[0-9]+]]:fpr16 = CPYi16 [[COPY]], 4 ; CHECK-NEXT: [[DUPi16_3:%[0-9]+]]:fpr16 = DUPi16 [[COPY]], 4
; CHECK-NEXT: [[CPYi16_4:%[0-9]+]]:fpr16 = CPYi16 [[COPY]], 5 ; CHECK-NEXT: [[DUPi16_4:%[0-9]+]]:fpr16 = DUPi16 [[COPY]], 5
; CHECK-NEXT: [[CPYi16_5:%[0-9]+]]:fpr16 = CPYi16 [[COPY]], 6 ; CHECK-NEXT: [[DUPi16_5:%[0-9]+]]:fpr16 = DUPi16 [[COPY]], 6
; CHECK-NEXT: [[CPYi16_6:%[0-9]+]]:fpr16 = CPYi16 [[COPY]], 7 ; CHECK-NEXT: [[DUPi16_6:%[0-9]+]]:fpr16 = DUPi16 [[COPY]], 7
; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY1]], %subreg.hsub ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY1]], %subreg.hsub
; CHECK-NEXT: [[DEF1:%[0-9]+]]:fpr128 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF1:%[0-9]+]]:fpr128 = IMPLICIT_DEF
; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF1]], [[CPYi16_]], %subreg.hsub ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF1]], [[DUPi16_]], %subreg.hsub
; CHECK-NEXT: [[INSvi16lane:%[0-9]+]]:fpr128 = INSvi16lane [[INSERT_SUBREG]], 1, [[INSERT_SUBREG1]], 0 ; CHECK-NEXT: [[INSvi16lane:%[0-9]+]]:fpr128 = INSvi16lane [[INSERT_SUBREG]], 1, [[INSERT_SUBREG1]], 0
; CHECK-NEXT: [[DEF2:%[0-9]+]]:fpr128 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF2:%[0-9]+]]:fpr128 = IMPLICIT_DEF
; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF2]], [[CPYi16_1]], %subreg.hsub ; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF2]], [[DUPi16_1]], %subreg.hsub
; CHECK-NEXT: [[INSvi16lane1:%[0-9]+]]:fpr128 = INSvi16lane [[INSvi16lane]], 2, [[INSERT_SUBREG2]], 0 ; CHECK-NEXT: [[INSvi16lane1:%[0-9]+]]:fpr128 = INSvi16lane [[INSvi16lane]], 2, [[INSERT_SUBREG2]], 0
; CHECK-NEXT: [[DEF3:%[0-9]+]]:fpr128 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF3:%[0-9]+]]:fpr128 = IMPLICIT_DEF
; CHECK-NEXT: [[INSERT_SUBREG3:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF3]], [[CPYi16_2]], %subreg.hsub ; CHECK-NEXT: [[INSERT_SUBREG3:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF3]], [[DUPi16_2]], %subreg.hsub
; CHECK-NEXT: [[INSvi16lane2:%[0-9]+]]:fpr128 = INSvi16lane [[INSvi16lane1]], 3, [[INSERT_SUBREG3]], 0 ; CHECK-NEXT: [[INSvi16lane2:%[0-9]+]]:fpr128 = INSvi16lane [[INSvi16lane1]], 3, [[INSERT_SUBREG3]], 0
; CHECK-NEXT: [[DEF4:%[0-9]+]]:fpr128 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF4:%[0-9]+]]:fpr128 = IMPLICIT_DEF
; CHECK-NEXT: [[INSERT_SUBREG4:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF4]], [[CPYi16_3]], %subreg.hsub ; CHECK-NEXT: [[INSERT_SUBREG4:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF4]], [[DUPi16_3]], %subreg.hsub
; CHECK-NEXT: [[INSvi16lane3:%[0-9]+]]:fpr128 = INSvi16lane [[INSvi16lane2]], 4, [[INSERT_SUBREG4]], 0 ; CHECK-NEXT: [[INSvi16lane3:%[0-9]+]]:fpr128 = INSvi16lane [[INSvi16lane2]], 4, [[INSERT_SUBREG4]], 0
; CHECK-NEXT: [[DEF5:%[0-9]+]]:fpr128 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF5:%[0-9]+]]:fpr128 = IMPLICIT_DEF
; CHECK-NEXT: [[INSERT_SUBREG5:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF5]], [[CPYi16_4]], %subreg.hsub ; CHECK-NEXT: [[INSERT_SUBREG5:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF5]], [[DUPi16_4]], %subreg.hsub
; CHECK-NEXT: [[INSvi16lane4:%[0-9]+]]:fpr128 = INSvi16lane [[INSvi16lane3]], 5, [[INSERT_SUBREG5]], 0 ; CHECK-NEXT: [[INSvi16lane4:%[0-9]+]]:fpr128 = INSvi16lane [[INSvi16lane3]], 5, [[INSERT_SUBREG5]], 0
; CHECK-NEXT: [[DEF6:%[0-9]+]]:fpr128 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF6:%[0-9]+]]:fpr128 = IMPLICIT_DEF
; CHECK-NEXT: [[INSERT_SUBREG6:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF6]], [[CPYi16_5]], %subreg.hsub ; CHECK-NEXT: [[INSERT_SUBREG6:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF6]], [[DUPi16_5]], %subreg.hsub
; CHECK-NEXT: [[INSvi16lane5:%[0-9]+]]:fpr128 = INSvi16lane [[INSvi16lane4]], 6, [[INSERT_SUBREG6]], 0 ; CHECK-NEXT: [[INSvi16lane5:%[0-9]+]]:fpr128 = INSvi16lane [[INSvi16lane4]], 6, [[INSERT_SUBREG6]], 0
; CHECK-NEXT: [[DEF7:%[0-9]+]]:fpr128 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF7:%[0-9]+]]:fpr128 = IMPLICIT_DEF
; CHECK-NEXT: [[INSERT_SUBREG7:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF7]], [[CPYi16_6]], %subreg.hsub ; CHECK-NEXT: [[INSERT_SUBREG7:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF7]], [[DUPi16_6]], %subreg.hsub
; CHECK-NEXT: [[INSvi16lane6:%[0-9]+]]:fpr128 = INSvi16lane [[INSvi16lane5]], 7, [[INSERT_SUBREG7]], 0 ; CHECK-NEXT: [[INSvi16lane6:%[0-9]+]]:fpr128 = INSvi16lane [[INSvi16lane5]], 7, [[INSERT_SUBREG7]], 0
; CHECK-NEXT: $q0 = COPY [[INSvi16lane6]] ; CHECK-NEXT: $q0 = COPY [[INSvi16lane6]]
; CHECK-NEXT: RET_ReallyLR implicit $q0 ; CHECK-NEXT: RET_ReallyLR implicit $q0
%0:fpr(<8 x s16>) = COPY $q0 %0:fpr(<8 x s16>) = COPY $q0
; Since 8 * 16 = 128, we can just directly copy. ; Since 8 * 16 = 128, we can just directly copy.
%2:fpr(s16), %3:fpr(s16), %4:fpr(s16), %5:fpr(s16), %6:fpr(s16), %7:fpr(s16), %8:fpr(s16), %9:fpr(s16) = G_UNMERGE_VALUES %0(<8 x s16>) %2:fpr(s16), %3:fpr(s16), %4:fpr(s16), %5:fpr(s16), %6:fpr(s16), %7:fpr(s16), %8:fpr(s16), %9:fpr(s16) = G_UNMERGE_VALUES %0(<8 x s16>)
Show All 24 Lines bb.1:
; CHECK-NEXT: [[INSERT_SUBREG3:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF3]], [[COPY]], %subreg.dsub ; CHECK-NEXT: [[INSERT_SUBREG3:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF3]], [[COPY]], %subreg.dsub
; CHECK-NEXT: [[DEF4:%[0-9]+]]:fpr128 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF4:%[0-9]+]]:fpr128 = IMPLICIT_DEF
; CHECK-NEXT: [[INSERT_SUBREG4:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF4]], [[COPY]], %subreg.dsub ; CHECK-NEXT: [[INSERT_SUBREG4:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF4]], [[COPY]], %subreg.dsub
; CHECK-NEXT: [[DEF5:%[0-9]+]]:fpr128 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF5:%[0-9]+]]:fpr128 = IMPLICIT_DEF
; CHECK-NEXT: [[INSERT_SUBREG5:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF5]], [[COPY]], %subreg.dsub ; CHECK-NEXT: [[INSERT_SUBREG5:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF5]], [[COPY]], %subreg.dsub
; CHECK-NEXT: [[DEF6:%[0-9]+]]:fpr128 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF6:%[0-9]+]]:fpr128 = IMPLICIT_DEF
; CHECK-NEXT: [[INSERT_SUBREG6:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF6]], [[COPY]], %subreg.dsub ; CHECK-NEXT: [[INSERT_SUBREG6:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF6]], [[COPY]], %subreg.dsub
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr8 = COPY [[INSERT_SUBREG]].bsub ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr8 = COPY [[INSERT_SUBREG]].bsub
; CHECK-NEXT: [[CPYi8_:%[0-9]+]]:fpr8 = CPYi8 [[INSERT_SUBREG]], 1 ; CHECK-NEXT: [[DUPi8_:%[0-9]+]]:fpr8 = DUPi8 [[INSERT_SUBREG]], 1
; CHECK-NEXT: [[CPYi8_1:%[0-9]+]]:fpr8 = CPYi8 [[INSERT_SUBREG1]], 2 ; CHECK-NEXT: [[DUPi8_1:%[0-9]+]]:fpr8 = DUPi8 [[INSERT_SUBREG1]], 2
; CHECK-NEXT: [[CPYi8_2:%[0-9]+]]:fpr8 = CPYi8 [[INSERT_SUBREG2]], 3 ; CHECK-NEXT: [[DUPi8_2:%[0-9]+]]:fpr8 = DUPi8 [[INSERT_SUBREG2]], 3
; CHECK-NEXT: [[CPYi8_3:%[0-9]+]]:fpr8 = CPYi8 [[INSERT_SUBREG3]], 4 ; CHECK-NEXT: [[DUPi8_3:%[0-9]+]]:fpr8 = DUPi8 [[INSERT_SUBREG3]], 4
; CHECK-NEXT: [[CPYi8_4:%[0-9]+]]:fpr8 = CPYi8 [[INSERT_SUBREG4]], 5 ; CHECK-NEXT: [[DUPi8_4:%[0-9]+]]:fpr8 = DUPi8 [[INSERT_SUBREG4]], 5
; CHECK-NEXT: [[CPYi8_5:%[0-9]+]]:fpr8 = CPYi8 [[INSERT_SUBREG5]], 6 ; CHECK-NEXT: [[DUPi8_5:%[0-9]+]]:fpr8 = DUPi8 [[INSERT_SUBREG5]], 6
; CHECK-NEXT: [[CPYi8_6:%[0-9]+]]:fpr8 = CPYi8 [[INSERT_SUBREG6]], 7 ; CHECK-NEXT: [[DUPi8_6:%[0-9]+]]:fpr8 = DUPi8 [[INSERT_SUBREG6]], 7
; CHECK-NEXT: $b0 = COPY [[COPY1]] ; CHECK-NEXT: $b0 = COPY [[COPY1]]
; CHECK-NEXT: $b1 = COPY [[CPYi8_]] ; CHECK-NEXT: $b1 = COPY [[DUPi8_]]
; CHECK-NEXT: $b2 = COPY [[CPYi8_1]] ; CHECK-NEXT: $b2 = COPY [[DUPi8_1]]
; CHECK-NEXT: $b3 = COPY [[CPYi8_2]] ; CHECK-NEXT: $b3 = COPY [[DUPi8_2]]
; CHECK-NEXT: $b4 = COPY [[CPYi8_3]] ; CHECK-NEXT: $b4 = COPY [[DUPi8_3]]
; CHECK-NEXT: $b5 = COPY [[CPYi8_4]] ; CHECK-NEXT: $b5 = COPY [[DUPi8_4]]
; CHECK-NEXT: $b6 = COPY [[CPYi8_5]] ; CHECK-NEXT: $b6 = COPY [[DUPi8_5]]
; CHECK-NEXT: $b7 = COPY [[CPYi8_6]] ; CHECK-NEXT: $b7 = COPY [[DUPi8_6]]
; CHECK-NEXT: RET_ReallyLR implicit $d0 ; CHECK-NEXT: RET_ReallyLR implicit $d0
%0:fpr(<8 x s8>) = COPY $d0 %0:fpr(<8 x s8>) = COPY $d0
%2:fpr(s8), %3:fpr(s8), %4:fpr(s8), %5:fpr(s8), %6:fpr(s8), %7:fpr(s8), %8:fpr(s8), %9:fpr(s8) = G_UNMERGE_VALUES %0(<8 x s8>) %2:fpr(s8), %3:fpr(s8), %4:fpr(s8), %5:fpr(s8), %6:fpr(s8), %7:fpr(s8), %8:fpr(s8), %9:fpr(s8) = G_UNMERGE_VALUES %0(<8 x s8>)
$b0 = COPY %2 $b0 = COPY %2
$b1 = COPY %3 $b1 = COPY %3
$b2 = COPY %4 $b2 = COPY %4
$b3 = COPY %5 $b3 = COPY %5
$b4 = COPY %6 $b4 = COPY %6
Show All 11 Lines
body: | body: |
bb.1: bb.1:
liveins: $q0 liveins: $q0
; CHECK-LABEL: name: test_vecsplit_2v2s32_v4s32 ; CHECK-LABEL: name: test_vecsplit_2v2s32_v4s32
; CHECK: liveins: $q0 ; CHECK: liveins: $q0
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY [[COPY]].dsub ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY [[COPY]].dsub
; CHECK-NEXT: [[CPYi64_:%[0-9]+]]:fpr64 = CPYi64 [[COPY]], 1 ; CHECK-NEXT: [[DUPi64_:%[0-9]+]]:fpr64 = DUPi64 [[COPY]], 1
; CHECK-NEXT: $d0 = COPY [[COPY1]] ; CHECK-NEXT: $d0 = COPY [[COPY1]]
; CHECK-NEXT: $d1 = COPY [[CPYi64_]] ; CHECK-NEXT: $d1 = COPY [[DUPi64_]]
; CHECK-NEXT: RET_ReallyLR implicit $d0 ; CHECK-NEXT: RET_ReallyLR implicit $d0
%0:fpr(<4 x s32>) = COPY $q0 %0:fpr(<4 x s32>) = COPY $q0
%1:fpr(<2 x s32>), %2:fpr(<2 x s32>) = G_UNMERGE_VALUES %0(<4 x s32>) %1:fpr(<2 x s32>), %2:fpr(<2 x s32>) = G_UNMERGE_VALUES %0(<4 x s32>)
$d0 = COPY %1(<2 x s32>) $d0 = COPY %1(<2 x s32>)
$d1 = COPY %2(<2 x s32>) $d1 = COPY %2(<2 x s32>)
RET_ReallyLR implicit $d0 RET_ReallyLR implicit $d0
... ...
--- ---
name: test_vecsplit_2v2s16_v4s16 name: test_vecsplit_2v2s16_v4s16
alignment: 4 alignment: 4
legalized: true legalized: true
regBankSelected: true regBankSelected: true
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.1: bb.1:
liveins: $d0 liveins: $d0
; CHECK-LABEL: name: test_vecsplit_2v2s16_v4s16 ; CHECK-LABEL: name: test_vecsplit_2v2s16_v4s16
; CHECK: liveins: $d0 ; CHECK: liveins: $d0
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY [[COPY]].ssub ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY [[COPY]].ssub
; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.dsub ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.dsub
; CHECK-NEXT: [[CPYi32_:%[0-9]+]]:fpr32 = CPYi32 [[INSERT_SUBREG]], 1 ; CHECK-NEXT: [[DUPi32_:%[0-9]+]]:fpr32 = DUPi32 [[INSERT_SUBREG]], 1
; CHECK-NEXT: $s0 = COPY [[COPY1]] ; CHECK-NEXT: $s0 = COPY [[COPY1]]
; CHECK-NEXT: $s1 = COPY [[CPYi32_]] ; CHECK-NEXT: $s1 = COPY [[DUPi32_]]
; CHECK-NEXT: RET_ReallyLR implicit $s0 ; CHECK-NEXT: RET_ReallyLR implicit $s0
%0:fpr(<4 x s16>) = COPY $d0 %0:fpr(<4 x s16>) = COPY $d0
%1:fpr(<2 x s16>), %2:fpr(<2 x s16>) = G_UNMERGE_VALUES %0(<4 x s16>) %1:fpr(<2 x s16>), %2:fpr(<2 x s16>) = G_UNMERGE_VALUES %0(<4 x s16>)
$s0 = COPY %1(<2 x s16>) $s0 = COPY %1(<2 x s16>)
$s1 = COPY %2(<2 x s16>) $s1 = COPY %2(<2 x s16>)
RET_ReallyLR implicit $s0 RET_ReallyLR implicit $s0
... ...
--- ---
name: test_s128 name: test_s128
alignment: 4 alignment: 4
legalized: true legalized: true
regBankSelected: true regBankSelected: true
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.1: bb.1:
liveins: $q0 liveins: $q0
; CHECK-LABEL: name: test_s128 ; CHECK-LABEL: name: test_s128
; CHECK: liveins: $q0 ; CHECK: liveins: $q0
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY [[COPY]].dsub ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY [[COPY]].dsub
; CHECK-NEXT: [[CPYi64_:%[0-9]+]]:fpr64 = CPYi64 [[COPY]], 1 ; CHECK-NEXT: [[DUPi64_:%[0-9]+]]:fpr64 = DUPi64 [[COPY]], 1
; CHECK-NEXT: $d0 = COPY [[COPY1]] ; CHECK-NEXT: $d0 = COPY [[COPY1]]
; CHECK-NEXT: $d1 = COPY [[CPYi64_]] ; CHECK-NEXT: $d1 = COPY [[DUPi64_]]
; CHECK-NEXT: RET_ReallyLR implicit $d0, implicit $d1 ; CHECK-NEXT: RET_ReallyLR implicit $d0, implicit $d1
%0:fpr(s128) = COPY $q0 %0:fpr(s128) = COPY $q0
%1:fpr(s64), %2:fpr(s64) = G_UNMERGE_VALUES %0(s128) %1:fpr(s64), %2:fpr(s64) = G_UNMERGE_VALUES %0(s128)
$d0 = COPY %1(s64) $d0 = COPY %1(s64)
$d1 = COPY %2(s64) $d1 = COPY %2(s64)
RET_ReallyLR implicit $d0, implicit $d1 RET_ReallyLR implicit $d0, implicit $d1
... ...