[jitlink] add R_RISCV_BRANCH to jitlink

[fourdim]

Summary

This patch supported the R_RISCV_BRANCH relocation.

[fourdim]

Add prefix for hexadecimal numeric.

[fourdim]

Include the recent commits.

[fourdim]

Include the recent commits.

[fourdim]

Fix the behavior after extractBits function's update.

[StephenFan]

llvm/lib/ExecutionEngine/JITLink/ELF_riscv.cpp

167

More concise.

[fourdim]

Address the comments.

[lhames]

LGTM! Thanks very much @fourdim!

[fourdim]

Include the recent commits.

llvm/include/llvm/ExecutionEngine/JITLink/riscv.h

enum EdgeKind_riscv : Edge::Kind {
 
   /// A plain 64-bit pointer value relocation
   ///
   /// Fixup expression:
   ///   Fixup <- Target + Addend : uint32
   ///
   R_RISCV_64,
 
+  /// Low 12 bits of PC-relative branch pointer value relocation
+  ///
+  /// Fixup expression:
+  ///   Fixup <- (Target - Fixup + Addend) & 0xFFF
+  ///
+  R_RISCV_BRANCH,
+
   /// High 20 bits of 32-bit pointer value relocation
   ///
   /// Fixup expression
   ///   Fixup <- (Target + Addend + 0x800) >> 12
   R_RISCV_HI20,
 
   /// Low 12 bits of 32-bit pointer value relocation
   ///

llvm/lib/ExecutionEngine/JITLink/ELF_riscv.cpp

static Expected<const Edge &> getRISCVPCRelHi20(const Edge &E) {
   return make_error<JITLinkError>(
       "No HI20 PCREL relocation type be found for LO12 PCREL relocation type");
 }
 
 static uint32_t extractBits(uint32_t Num, unsigned Low, unsigned Size) {
   return (Num & (((1ULL << (Size + 1)) - 1) << Low)) >> Low;
 }
 
+inline Error checkAlignment(llvm::orc::ExecutorAddr loc, uint64_t v, int n,
+                            const Edge &E) {
+  if (v & (n - 1))
+    return make_error<JITLinkError>("0x" + llvm::utohexstr(loc.getValue()) +
+                                    " improper alignment for relocation " +
+                                    formatv("{0:d}", E.getKind()) + ": 0x" +
+                                    llvm::utohexstr(v) + " is not aligned to " +
+                                    Twine(n) + " bytes");
+  return Error::success();
+}
+
 class ELFJITLinker_riscv : public JITLinker<ELFJITLinker_riscv> {
   friend class JITLinker<ELFJITLinker_riscv>;
 
 public:
   ELFJITLinker_riscv(std::unique_ptr<JITLinkContext> Ctx,
                      std::unique_ptr<LinkGraph> G, PassConfiguration PassConfig)
       : JITLinker(std::move(Ctx), std::move(G), std::move(PassConfig)) {}
 
case R_RISCV_32: {
       *(little32_t *)FixupPtr = static_cast<uint32_t>(Value);
       break;
     }
     case R_RISCV_64: {
       int64_t Value = (E.getTarget().getAddress() + E.getAddend()).getValue();
       *(little64_t *)FixupPtr = static_cast<uint64_t>(Value);
       break;
     }
+    case R_RISCV_BRANCH: {
+      int64_t Value = E.getTarget().getAddress() + E.getAddend() - FixupAddress;
+      Error AlignmentIssue = checkAlignment(FixupAddress, Value, 2, E);
+      if (AlignmentIssue) {
+        return AlignmentIssue;
+      }
+      int64_t Lo = Value & 0xFFF;
+      uint32_t Imm31_25 = extractBits(Lo, 5, 6) << 25 | extractBits(Lo, 12, 1)
+                                                            << 31;
+      uint32_t Imm11_7 = extractBits(Lo, 1, 4) << 8 | extractBits(Lo, 11, 1)
+                                                          << 7;
+      uint32_t RawInstr = *(little32_t *)FixupPtr;
+      *(little32_t *)FixupPtr = (RawInstr & 0x1FFF07F) | Imm31_25 | Imm11_7;
+      break;
+    }
     case R_RISCV_HI20: {
       int64_t Value = (E.getTarget().getAddress() + E.getAddend()).getValue();
       int32_t Hi = (Value + 0x800) & 0xFFFFF000;
       uint32_t RawInstr = *(little32_t *)FixupPtr;
       *(little32_t *)FixupPtr = (RawInstr & 0xFFF) | static_cast<uint32_t>(Hi);
       break;
     }
     case R_RISCV_LO12_I: {
private:
   static Expected<riscv::EdgeKind_riscv>
   getRelocationKind(const uint32_t Type) {
     using namespace riscv;
     switch (Type) {
     case ELF::R_RISCV_32:
       return EdgeKind_riscv::R_RISCV_32;
     case ELF::R_RISCV_64:
       return EdgeKind_riscv::R_RISCV_64;
+    case ELF::R_RISCV_BRANCH:
+      return EdgeKind_riscv::R_RISCV_BRANCH;
     case ELF::R_RISCV_HI20:
       return EdgeKind_riscv::R_RISCV_HI20;
     case ELF::R_RISCV_LO12_I:
       return EdgeKind_riscv::R_RISCV_LO12_I;
     case ELF::R_RISCV_CALL:
       return EdgeKind_riscv::R_RISCV_CALL;
     case ELF::R_RISCV_PCREL_HI20:
       return EdgeKind_riscv::R_RISCV_PCREL_HI20;

llvm/lib/ExecutionEngine/JITLink/riscv.cpp

 namespace riscv {
 
 const char *getEdgeKindName(Edge::Kind K) {
   switch (K) {
   case R_RISCV_32:
     return "R_RISCV_32";
   case R_RISCV_64:
     return "R_RISCV_64";
+  case R_RISCV_BRANCH:
+    return "R_RISCV_BRANCH";
   case R_RISCV_HI20:
     return "R_RISCV_HI20";
   case R_RISCV_LO12_I:
     return "R_RISCV_LO12_I";
   case R_RISCV_PCREL_HI20:
     return "R_RISCV_PCREL_HI20";
   case R_RISCV_PCREL_LO12_I:
     return "R_RISCV_PCREL_LO12_I";

llvm/test/ExecutionEngine/JITLink/RISCV/ELF_branch.s

+# RUN: rm -rf %t && mkdir -p %t
+# RUN: llvm-mc -triple=riscv64 -filetype=obj \
+# RUN:     -o %t/elf_riscv64_branch.o %s
+# RUN: llvm-mc -triple=riscv32 -filetype=obj \
+# RUN:     -o %t/elf_riscv32_branch.o %s
+# RUN: llvm-jitlink -noexec \
+# RUN:     -slab-allocate 100Kb -slab-address 0xfff00000 -slab-page-size 4096 \
+# RUN:     -define-abs external_func=0xfe \
+# RUN:     -check %s %t/elf_riscv64_branch.o
+# RUN: llvm-jitlink -noexec \
+# RUN:     -slab-allocate 100Kb -slab-address 0xfff00000 -slab-page-size 4096 \
+# RUN:     -define-abs external_func=0xfe \
+# RUN:     -check %s %t/elf_riscv32_branch.o
+#
+
+        .text
+        .file   "testcase.c"
+
+# Empty main entry point.
+        .globl  main
+        .p2align  1
+        .type   main,@function
+main:
+        ret
+
+        .size   main, .-main
+
+# Test R_RISCV_BRANCH
+
+# jitlink-check: decode_operand(test_branch, 2)[11:0] = (external_func - test_branch)[11:0]
+  .globl  test_branch
+  .p2align  1
+  .type  test_branch,@function
+test_branch:
+  bge a0, a1, external_func
+
+  .size test_branch, .-test_branch