[RISCV] Fold (and (not (srl X, C)), 1) to (xor (bexti X, C), 1) when have Zbs extension.

[jacquesguan]

Summary

When have Zbs extension, we could use bexti to fold (and (not (srl X, C)), 1) to (xor (bexti X, C), 1).

[craig.topper]

Have you seen real cases of this pattern? InstCombine canonicalizes this to (xor (and (srl X, C), 1), 1) before we get to SelectionDAG.

[jacquesguan]

In D115629#3189585, @craig.topper wrote:

Have you seen real cases of this pattern? InstCombine canonicalizes this to (xor (and (srl X, C), 1), 1) before we get to SelectionDAG.

Yes. As you said, InstCombine do canonicalize this to xor (and (srl X, C), 1), 1 , but DAGCombine will also fold (xor (and x, y), y) -> (and (not x), y). So we still get and (not (srl X, C)), 1 in SelectionDAG. I will add another case xor (and (srl X, C), 1), 1 to show this.

[jacquesguan]

Add xor (and (srl X, C), 1), 1 test case.

[craig.topper]

llvm/lib/Target/RISCV/RISCVInstrInfoZb.td

795

I wonder if the (XORI (BEXTI GPR:$rs1, $shamt), 1) we would have gotten from the original InstCombine canonicalization would be better.

Guess it depends on whether the Zbs instructions are implemented as well as XORI or not. There is no c.xori or that would have been a good reason to favor xori.

[jacquesguan]

llvm/lib/Target/RISCV/RISCVInstrInfoZb.td

795

Thanks, so that I could change DAGCombine to keep xor (and(srl X, C),1), 1 when we have single-Bit extract instruction in backend. In this situation, at least, we fold (and(srl X, C),1) into BEXTI X, C. What's your option about this?

[jacquesguan]

llvm/lib/Target/RISCV/RISCVInstrInfoZb.td

795

Sorry, I misunderstanded your comment. Please ignore my last reply. I would simply change that pattern into

def : Pat<(and (not (srl GPR:$rs1, uimmlog2xlen:$shamt)), (XLenVT 1)),
                   (XORI (BEXTI GPR:$rs1, uimmlog2xlen:$shamt), (XLenVT 1))

[jacquesguan]

use xori instead of binvi.

[craig.topper]

Should we have a test in rv64zbs.ll too?

[jacquesguan]

Add RV64 test.

[jacquesguan]

In D115629#3194194, @craig.topper wrote:

Should we have a test in rv64zbs.ll too?

Done, thanks a lot.

[craig.topper]

llvm/test/CodeGen/RISCV/rv32zbs.ll

360

sbexti->bexti I'll rename the existing test cases today.

[jacquesguan]

Update test case and change commit message.

llvm/test/CodeGen/RISCV/rv32zbs.ll

360

Done.

[craig.topper]

LGTM. Please fix the title to remove the mention of binvi since we aren't using that now.

llvm/lib/Target/RISCV/RISCVInstrInfoZb.td

 def : Pat<(or GPR:$rs1, BSETINVMask:$mask),
           (BSETI GPR:$rs1, BSETINVMask:$mask)>;
 def : Pat<(xor GPR:$rs1, BSETINVMask:$mask),
           (BINVI GPR:$rs1, BSETINVMask:$mask)>;
 
 def : Pat<(and (srl GPR:$rs1, uimmlog2xlen:$shamt), (XLenVT 1)),
           (BEXTI GPR:$rs1, uimmlog2xlen:$shamt)>;
 
+def : Pat<(and (not (srl GPR:$rs1, uimmlog2xlen:$shamt)), (XLenVT 1)),
+          (XORI (BEXTI GPR:$rs1, uimmlog2xlen:$shamt), (XLenVT 1))>;
+
 def : Pat<(or GPR:$r, BSETINVTwoBitsMask:$i),
           (BSETI (BSETI GPR:$r, (TrailingZerosXForm BSETINVTwoBitsMask:$i)),
                  (BSETINVTwoBitsMaskHigh BSETINVTwoBitsMask:$i))>;
 def : Pat<(xor GPR:$r, BSETINVTwoBitsMask:$i),
           (BINVI (BINVI GPR:$r, (TrailingZerosXForm BSETINVTwoBitsMask:$i)),
                  (BSETINVTwoBitsMaskHigh BSETINVTwoBitsMask:$i))>;
 def : Pat<(or GPR:$r, BSETINVORIMask:$i),
           (BSETI (ORI GPR:$r, (BSETINVORIMaskLow BSETINVORIMask:$i)),

llvm/test/CodeGen/RISCV/rv32zbs.ll

 ; RV32ZBS-NEXT:    bexti a0, a0, 5
 ; RV32ZBS-NEXT:    li a1, 0
 ; RV32ZBS-NEXT:    ret
   %shr = lshr i64 %a, 5
   %and = and i64 %shr, 1
   ret i64 %and
 }
 
+define i32 @bexti_xor_i32(i32 %a) nounwind {
+; RV32I-LABEL: bexti_xor_i32:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    srli a0, a0, 7
+; RV32I-NEXT:    not a0, a0
+; RV32I-NEXT:    andi a0, a0, 1
+; RV32I-NEXT:    ret
+;
+; RV32ZBS-LABEL: bexti_xor_i32:
+; RV32ZBS:       # %bb.0:
+; RV32ZBS-NEXT:    bexti a0, a0, 7
+; RV32ZBS-NEXT:    xori a0, a0, 1
+; RV32ZBS-NEXT:    ret
+  %shr = lshr i32 %a, 7
+  %not = xor i32 %shr, -1
+  %and = and i32 %not, 1
+  ret i32 %and
+}
+
+define i64 @bexti_xor_i64(i64 %a) nounwind {
+; RV32I-LABEL: bexti_xor_i64:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    srli a0, a0, 7
+; RV32I-NEXT:    not a0, a0
+; RV32I-NEXT:    andi a0, a0, 1
+; RV32I-NEXT:    li a1, 0
+; RV32I-NEXT:    ret
+;
+; RV32ZBS-LABEL: bexti_xor_i64:
+; RV32ZBS:       # %bb.0:
+; RV32ZBS-NEXT:    bexti a0, a0, 7
+; RV32ZBS-NEXT:    xori a0, a0, 1
+; RV32ZBS-NEXT:    li a1, 0
+; RV32ZBS-NEXT:    ret
+  %shr = lshr i64 %a, 7
+  %not = xor i64 %shr, -1
+  %and = and i64 %not, 1
+  ret i64 %and
+}
+
+define i32 @bexti_xor_i32_1(i32 %a) nounwind {
+; RV32I-LABEL: bexti_xor_i32_1:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    srli a0, a0, 7
+; RV32I-NEXT:    not a0, a0
+; RV32I-NEXT:    andi a0, a0, 1
+; RV32I-NEXT:    ret
+;
+; RV32ZBS-LABEL: bexti_xor_i32_1:
+; RV32ZBS:       # %bb.0:
+; RV32ZBS-NEXT:    bexti a0, a0, 7
+; RV32ZBS-NEXT:    xori a0, a0, 1
+; RV32ZBS-NEXT:    ret
+  %shr = lshr i32 %a, 7
+  %and = and i32 %shr, 1
+  %xor = xor i32 %and, 1
+  ret i32 %xor
+}
+
+define i64 @bexti_xor_i64_1(i64 %a) nounwind {
+; RV32I-LABEL: bexti_xor_i64_1:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    srli a0, a0, 7
+; RV32I-NEXT:    not a0, a0
+; RV32I-NEXT:    andi a0, a0, 1
+; RV32I-NEXT:    li a1, 0
+; RV32I-NEXT:    ret
+;
+; RV32ZBS-LABEL: bexti_xor_i64_1:
+; RV32ZBS:       # %bb.0:
+; RV32ZBS-NEXT:    bexti a0, a0, 7
+; RV32ZBS-NEXT:    xori a0, a0, 1
+; RV32ZBS-NEXT:    li a1, 0
+; RV32ZBS-NEXT:    ret
+  %shr = lshr i64 %a, 7
+  %and = and i64 %shr, 1
+  %xor = xor i64 %and, 1
+  ret i64 %xor
+}
+
 define i32 @bclri_i32_10(i32 %a) nounwind {
 ; RV32I-LABEL: bclri_i32_10:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    andi a0, a0, -1025
 ; RV32I-NEXT:    ret
 ;
 ; RV32ZBS-LABEL: bclri_i32_10:
 ; RV32ZBS:       # %bb.0:

llvm/test/CodeGen/RISCV/rv64zbs.ll

 ; RV64ZBS:       # %bb.0:
 ; RV64ZBS-NEXT:    bexti a0, a0, 5
 ; RV64ZBS-NEXT:    ret
   %shr = lshr i64 %a, 5
   %and = and i64 %shr, 1
   ret i64 %and
 }
 
+define signext i32 @bexti_xor_i32(i32 signext %a) nounwind {
+; RV64I-LABEL: bexti_xor_i32:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    srli a0, a0, 7
+; RV64I-NEXT:    not a0, a0
+; RV64I-NEXT:    andi a0, a0, 1
+; RV64I-NEXT:    ret
+;
+; RV64ZBS-LABEL: bexti_xor_i32:
+; RV64ZBS:       # %bb.0:
+; RV64ZBS-NEXT:    bexti a0, a0, 7
+; RV64ZBS-NEXT:    xori a0, a0, 1
+; RV64ZBS-NEXT:    ret
+  %shr = lshr i32 %a, 7
+  %not = xor i32 %shr, -1
+  %and = and i32 %not, 1
+  ret i32 %and
+}
+
+define i64 @bexti_xor_i64(i64 %a) nounwind {
+; RV64I-LABEL: bexti_xor_i64:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    srli a0, a0, 7
+; RV64I-NEXT:    not a0, a0
+; RV64I-NEXT:    andi a0, a0, 1
+; RV64I-NEXT:    ret
+;
+; RV64ZBS-LABEL: bexti_xor_i64:
+; RV64ZBS:       # %bb.0:
+; RV64ZBS-NEXT:    bexti a0, a0, 7
+; RV64ZBS-NEXT:    xori a0, a0, 1
+; RV64ZBS-NEXT:    ret
+  %shr = lshr i64 %a, 7
+  %not = xor i64 %shr, -1
+  %and = and i64 %not, 1
+  ret i64 %and
+}
+
+define signext i32 @bexti_xor_i32_1(i32 signext %a) nounwind {
+; RV64I-LABEL: bexti_xor_i32_1:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    srli a0, a0, 7
+; RV64I-NEXT:    not a0, a0
+; RV64I-NEXT:    andi a0, a0, 1
+; RV64I-NEXT:    ret
+;
+; RV64ZBS-LABEL: bexti_xor_i32_1:
+; RV64ZBS:       # %bb.0:
+; RV64ZBS-NEXT:    bexti a0, a0, 7
+; RV64ZBS-NEXT:    xori a0, a0, 1
+; RV64ZBS-NEXT:    ret
+  %shr = lshr i32 %a, 7
+  %and = and i32 %shr, 1
+  %xor = xor i32 %and, 1
+  ret i32 %xor
+}
+
+define i64 @bexti_xor_i64_1(i64 %a) nounwind {
+; RV64I-LABEL: bexti_xor_i64_1:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    srli a0, a0, 7
+; RV64I-NEXT:    not a0, a0
+; RV64I-NEXT:    andi a0, a0, 1
+; RV64I-NEXT:    ret
+;
+; RV64ZBS-LABEL: bexti_xor_i64_1:
+; RV64ZBS:       # %bb.0:
+; RV64ZBS-NEXT:    bexti a0, a0, 7
+; RV64ZBS-NEXT:    xori a0, a0, 1
+; RV64ZBS-NEXT:    ret
+  %shr = lshr i64 %a, 7
+  %and = and i64 %shr, 1
+  %xor = xor i64 %and, 1
+  ret i64 %xor
+}
+
 define signext i32 @bclri_i32_10(i32 signext %a) nounwind {
 ; RV64I-LABEL: bclri_i32_10:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    andi a0, a0, -1025
 ; RV64I-NEXT:    ret
 ;
 ; RV64ZBS-LABEL: bclri_i32_10:
 ; RV64ZBS:       # %bb.0: